1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * PCIC device/interrupt handler 31 * The "pcic" driver handles the Intel 82365SL, Cirrus Logic 32 * and Toshiba (and possibly other clones) PCMCIA adapter chip 33 * sets. It implements a subset of Socket Services as defined 34 * in the Solaris PCMCIA design documents 35 */ 36 37 /* 38 * currently defined "properties" 39 * 40 * clock-frequency bus clock frequency 41 * smi system management interrupt override 42 * need-mult-irq need status IRQ for each pair of sockets 43 * disable-audio don't route audio signal to speaker 44 */ 45 46 47 #include <sys/types.h> 48 #include <sys/inttypes.h> 49 #include <sys/param.h> 50 #include <sys/systm.h> 51 #include <sys/user.h> 52 #include <sys/buf.h> 53 #include <sys/file.h> 54 #include <sys/uio.h> 55 #include <sys/conf.h> 56 #include <sys/stat.h> 57 #include <sys/autoconf.h> 58 #include <sys/vtoc.h> 59 #include <sys/dkio.h> 60 #include <sys/ddi.h> 61 #include <sys/sunddi.h> 62 #include <sys/sunndi.h> 63 #include <sys/var.h> 64 #include <sys/callb.h> 65 #include <sys/open.h> 66 #include <sys/ddidmareq.h> 67 #include <sys/dma_engine.h> 68 #include <sys/kstat.h> 69 #include <sys/kmem.h> 70 #include <sys/modctl.h> 71 #include <sys/pci.h> 72 #include <sys/pci_impl.h> 73 74 #include <sys/pctypes.h> 75 #include <sys/pcmcia.h> 76 #include <sys/sservice.h> 77 78 #include <sys/note.h> 79 80 #include <sys/pcic_reg.h> 81 #include <sys/pcic_var.h> 82 83 #if defined(__sparc) 84 #include <sys/pci/pci_nexus.h> 85 #endif 86 87 #include <sys/syshw.h> 88 #include "cardbus/cardbus.h" 89 90 #define SOFTC_SIZE (sizeof (anp_t)) 91 92 static int pcic_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 93 static int pcic_attach(dev_info_t *, ddi_attach_cmd_t); 94 static int pcic_detach(dev_info_t *, ddi_detach_cmd_t); 95 static uint_t pcic_intr(caddr_t, caddr_t); 96 static int pcic_do_io_intr(pcicdev_t *, uint32_t); 97 static int pcic_probe(dev_info_t *); 98 99 static int pcic_open(dev_t *, int, int, cred_t *); 100 static int pcic_close(dev_t, int, int, cred_t *); 101 static int pcic_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 102 103 typedef struct pcm_regs pcm_regs_t; 104 105 static void pcic_init_assigned(dev_info_t *); 106 static int pcic_apply_avail_ranges(dev_info_t *, pcm_regs_t *, 107 pci_regspec_t *, int); 108 int pci_resource_setup_avail(dev_info_t *, pci_regspec_t *, int); 109 110 /* 111 * On x86 platforms the ddi_iobp_alloc(9F) and ddi_mem_alloc(9F) calls 112 * are xlated into DMA ctlops. To make this nexus work on x86, we 113 * need to have the default ddi_dma_mctl ctlops in the bus_ops 114 * structure, just to pass the request to the parent. The correct 115 * ctlops should be ddi_no_dma_mctl because so far we don't do DMA. 116 */ 117 static 118 struct bus_ops pcmciabus_ops = { 119 BUSO_REV, 120 pcmcia_bus_map, 121 NULL, 122 NULL, 123 NULL, 124 i_ddi_map_fault, 125 ddi_no_dma_map, 126 ddi_no_dma_allochdl, 127 ddi_no_dma_freehdl, 128 ddi_no_dma_bindhdl, 129 ddi_no_dma_unbindhdl, 130 ddi_no_dma_flush, 131 ddi_no_dma_win, 132 ddi_dma_mctl, 133 pcmcia_ctlops, 134 pcmcia_prop_op, 135 NULL, /* (*bus_get_eventcookie)(); */ 136 NULL, /* (*bus_add_eventcall)(); */ 137 NULL, /* (*bus_remove_eventcall)(); */ 138 NULL, /* (*bus_post_event)(); */ 139 NULL, /* (*bus_intr_ctl)(); */ 140 NULL, /* (*bus_config)(); */ 141 NULL, /* (*bus_unconfig)(); */ 142 NULL, /* (*bus_fm_init)(); */ 143 NULL, /* (*bus_fm_fini)(); */ 144 NULL, /* (*bus_enter)() */ 145 NULL, /* (*bus_exit)() */ 146 NULL, /* (*bus_power)() */ 147 pcmcia_intr_ops /* (*bus_intr_op)(); */ 148 }; 149 150 static struct cb_ops pcic_cbops = { 151 pcic_open, 152 pcic_close, 153 nodev, 154 nodev, 155 nodev, 156 nodev, 157 nodev, 158 pcic_ioctl, 159 nodev, 160 nodev, 161 nodev, 162 nochpoll, 163 ddi_prop_op, 164 NULL, 165 #ifdef CARDBUS 166 D_NEW | D_MP | D_HOTPLUG 167 #else 168 D_NEW | D_MP 169 #endif 170 }; 171 172 static struct dev_ops pcic_devops = { 173 DEVO_REV, 174 0, 175 pcic_getinfo, 176 nulldev, 177 pcic_probe, 178 pcic_attach, 179 pcic_detach, 180 nulldev, 181 &pcic_cbops, 182 &pcmciabus_ops, 183 NULL 184 }; 185 186 void *pcic_soft_state_p = NULL; 187 static int pcic_maxinst = -1; 188 static timeout_id_t pcic_delayed_resume_toid; 189 190 int pcic_do_insertion = 1; 191 int pcic_do_removal = 1; 192 193 struct irqmap { 194 int irq; 195 int count; 196 } pcic_irq_map[16]; 197 198 199 int pcic_debug = 0x0; 200 static void pcic_err(dev_info_t *dip, int level, const char *fmt, ...); 201 extern void cardbus_dump_pci_config(dev_info_t *dip); 202 extern void cardbus_dump_socket(dev_info_t *dip); 203 extern int cardbus_validate_iline(dev_info_t *dip, ddi_acc_handle_t handle); 204 static void pcic_dump_debqueue(char *msg); 205 206 #if defined(PCIC_DEBUG) 207 static void xxdmp_all_regs(pcicdev_t *, int, uint32_t); 208 209 #define pcic_mutex_enter(a) \ 210 { \ 211 pcic_err(NULL, 10, "Set lock at %d\n", __LINE__); \ 212 mutex_enter(a); \ 213 }; 214 215 #define pcic_mutex_exit(a) \ 216 { \ 217 pcic_err(NULL, 10, "Clear lock at %d\n", __LINE__); \ 218 mutex_exit(a); \ 219 }; 220 221 #else 222 #define pcic_mutex_enter(a) mutex_enter(a) 223 #define pcic_mutex_exit(a) mutex_exit(a) 224 #endif 225 226 #define PCIC_VCC_3VLEVEL 1 227 #define PCIC_VCC_5VLEVEL 2 228 #define PCIC_VCC_12LEVEL 3 229 230 /* bit patterns to select voltage levels */ 231 int pcic_vpp_levels[13] = { 232 0, 0, 0, 233 1, /* 3.3V */ 234 0, 235 1, /* 5V */ 236 0, 0, 0, 0, 0, 0, 237 2 /* 12V */ 238 }; 239 240 uint8_t pcic_cbv_levels[13] = { 241 0, 0, 0, 242 3, /* 3.3V */ 243 0, 244 2, /* 5V */ 245 0, 0, 0, 0, 0, 0, 246 1 /* 12V */ 247 }; 248 249 struct power_entry pcic_power[4] = { 250 { 251 0, VCC|VPP1|VPP2 252 }, 253 { 254 33, /* 3.3Volt */ 255 VCC|VPP1|VPP2 256 }, 257 { 258 5*10, /* 5Volt */ 259 VCC|VPP1|VPP2 /* currently only know about this */ 260 }, 261 { 262 12*10, /* 12Volt */ 263 VPP1|VPP2 264 } 265 }; 266 267 /* 268 * Base used to allocate ranges of PCI memory on x86 systems 269 * Each instance gets a chunk above the base that is used to map 270 * in the memory and I/O windows for that device. 271 * Pages below the base are also allocated for the EXCA registers, 272 * one per instance. 273 */ 274 #define PCIC_PCI_MEMCHUNK 0x1000000 275 276 static int pcic_wait_insert_time = 5000000; /* In micro-seconds */ 277 static int pcic_debounce_time = 200000; /* In micro-seconds */ 278 279 struct debounce { 280 pcic_socket_t *pcs; 281 clock_t expire; 282 struct debounce *next; 283 }; 284 285 static syshw_t pcic_syshw = { 286 0, "PC Card Socket 0", SH_CONNECTION, 287 SYSHW_CAN_SIGNAL_CHANGE|SYSHW_STATE_VALID|SYSHW_VAL0_VALID, 288 B_FALSE, {2, 0, 0, 0} 289 }; 290 291 static struct debounce *pcic_deb_queue = NULL; 292 static kmutex_t pcic_deb_mtx; 293 static kcondvar_t pcic_deb_cv; 294 static kthread_t *pcic_deb_threadid; 295 296 static inthandler_t *pcic_handlers; 297 298 static void pcic_setup_adapter(pcicdev_t *); 299 static int pcic_change(pcicdev_t *, int); 300 static int pcic_ll_reset(pcicdev_t *, int); 301 static void pcic_mswait(pcicdev_t *, int, int); 302 static boolean_t pcic_check_ready(pcicdev_t *, int); 303 static void pcic_set_cdtimers(pcicdev_t *, int, uint32_t, int); 304 static void pcic_ready_wait(pcicdev_t *, int); 305 extern int pcmcia_get_intr(dev_info_t *, int); 306 extern int pcmcia_return_intr(dev_info_t *, int); 307 308 static int pcic_callback(dev_info_t *, int (*)(), int); 309 static int pcic_inquire_adapter(dev_info_t *, inquire_adapter_t *); 310 static int pcic_get_adapter(dev_info_t *, get_adapter_t *); 311 static int pcic_get_page(dev_info_t *, get_page_t *); 312 static int pcic_get_socket(dev_info_t *, get_socket_t *); 313 static int pcic_get_status(dev_info_t *, get_ss_status_t *); 314 static int pcic_get_window(dev_info_t *, get_window_t *); 315 static int pcic_inquire_socket(dev_info_t *, inquire_socket_t *); 316 static int pcic_inquire_window(dev_info_t *, inquire_window_t *); 317 static int pcic_reset_socket(dev_info_t *, int, int); 318 static int pcic_set_page(dev_info_t *, set_page_t *); 319 static int pcic_set_window(dev_info_t *, set_window_t *); 320 static int pcic_set_socket(dev_info_t *, set_socket_t *); 321 static int pcic_set_interrupt(dev_info_t *, set_irq_handler_t *); 322 static int pcic_clear_interrupt(dev_info_t *, clear_irq_handler_t *); 323 static void pcic_pm_detection(void *); 324 static void pcic_iomem_pci_ctl(ddi_acc_handle_t, uchar_t *, unsigned); 325 static int clext_reg_read(pcicdev_t *, int, uchar_t); 326 static void clext_reg_write(pcicdev_t *, int, uchar_t, uchar_t); 327 static int pcic_calc_speed(pcicdev_t *, uint32_t); 328 static int pcic_card_state(pcicdev_t *, pcic_socket_t *); 329 static int pcic_find_pci_type(pcicdev_t *); 330 static void pcic_82092_smiirq_ctl(pcicdev_t *, int, int, int); 331 static void pcic_handle_cd_change(pcicdev_t *, pcic_socket_t *, uint8_t); 332 static uint_t pcic_cd_softint(caddr_t, caddr_t); 333 static uint8_t pcic_getb(pcicdev_t *, int, int); 334 static void pcic_putb(pcicdev_t *, int, int, int8_t); 335 static int pcic_set_vcc_level(pcicdev_t *, set_socket_t *); 336 static uint_t pcic_softintr(caddr_t, caddr_t); 337 338 static void pcic_debounce(pcic_socket_t *); 339 static void pcic_delayed_resume(void *); 340 static void *pcic_add_debqueue(pcic_socket_t *, int); 341 static void pcic_rm_debqueue(void *); 342 static void pcic_deb_thread(); 343 344 static boolean_t pcic_load_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp); 345 static void pcic_unload_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp); 346 static uint32_t pcic_getcb(pcicdev_t *pcic, int reg); 347 static void pcic_putcb(pcicdev_t *pcic, int reg, uint32_t value); 348 static void pcic_cb_enable_intr(dev_info_t *); 349 static void pcic_cb_disable_intr(dev_info_t *); 350 static void pcic_enable_io_intr(pcicdev_t *pcic, int socket, int irq); 351 static void pcic_disable_io_intr(pcicdev_t *pcic, int socket); 352 353 static cb_nexus_cb_t pcic_cbnexus_ops = { 354 pcic_cb_enable_intr, 355 pcic_cb_disable_intr 356 }; 357 358 static int pcic_exca_powerctl(pcicdev_t *pcic, int socket, int powerlevel); 359 static int pcic_cbus_powerctl(pcicdev_t *pcic, int socket); 360 361 static void pcic_syshw_cardstate(syshw_t *, void *); 362 363 #if defined(__sparc) 364 static int pcic_fault(enum pci_fault_ops op, void *arg); 365 #endif 366 367 /* 368 * Default to support for Voyager IIi if sparc is defined. 369 * Appart from the PCI base addresses this only effect the TI1250. 370 */ 371 #if defined(sparc) 372 #define VOYAGER 373 #endif 374 375 376 /* 377 * pcmcia_attach() uses 0 and 128 upwards for the initpcmcia and devctl 378 * interfaces so we use 254. 379 */ 380 #define SYSHW_MINOR 254 381 382 /* 383 * Forward declarations for syshw interface (See end of file). 384 */ 385 static void syshw_attach(pcicdev_t *); 386 static void syshw_detach(pcicdev_t *); 387 static void syshw_resume(pcicdev_t *); 388 389 #ifdef VOYAGER 390 static uint_t syshw_intr(caddr_t); 391 static uint_t syshw_intr_hi(pcicdev_t *); 392 #endif 393 394 static int syshw_open(dev_t *, int, int, cred_t *); 395 static int syshw_close(dev_t, int, int, cred_t *); 396 static int syshw_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 397 static uint32_t syshw_add2map(syshw_t *, void (*)(syshw_t *, void *), void *); 398 static void syshw_send_signal(int); 399 400 /* 401 * pcmcia interface operations structure 402 * this is the private interface that is exported to the nexus 403 */ 404 pcmcia_if_t pcic_if_ops = { 405 PCIF_MAGIC, 406 PCIF_VERSION, 407 pcic_callback, 408 pcic_get_adapter, 409 pcic_get_page, 410 pcic_get_socket, 411 pcic_get_status, 412 pcic_get_window, 413 pcic_inquire_adapter, 414 pcic_inquire_socket, 415 pcic_inquire_window, 416 pcic_reset_socket, 417 pcic_set_page, 418 pcic_set_window, 419 pcic_set_socket, 420 pcic_set_interrupt, 421 pcic_clear_interrupt, 422 NULL, 423 }; 424 425 /* 426 * chip type identification routines 427 * this list of functions is searched until one of them succeeds 428 * or all fail. i82365SL is assumed if failed. 429 */ 430 static int pcic_ci_cirrus(pcicdev_t *); 431 static int pcic_ci_vadem(pcicdev_t *); 432 static int pcic_ci_ricoh(pcicdev_t *); 433 434 int (*pcic_ci_funcs[])(pcicdev_t *) = { 435 pcic_ci_cirrus, 436 pcic_ci_vadem, 437 pcic_ci_ricoh, 438 NULL 439 }; 440 441 static struct modldrv modldrv = { 442 &mod_driverops, /* Type of module. This one is a driver */ 443 "PCIC PCMCIA adapter driver %I%", /* Name of the module. */ 444 &pcic_devops, /* driver ops */ 445 }; 446 447 static struct modlinkage modlinkage = { 448 MODREV_1, (void *)&modldrv, NULL 449 }; 450 451 int 452 _init() 453 { 454 int stat; 455 456 /* Allocate soft state */ 457 if ((stat = ddi_soft_state_init(&pcic_soft_state_p, 458 SOFTC_SIZE, 2)) != DDI_SUCCESS) 459 return (stat); 460 461 if ((stat = mod_install(&modlinkage)) != 0) 462 ddi_soft_state_fini(&pcic_soft_state_p); 463 464 return (stat); 465 } 466 467 int 468 _fini() 469 { 470 int stat = 0; 471 472 if ((stat = mod_remove(&modlinkage)) != 0) 473 return (stat); 474 475 if (pcic_deb_threadid) { 476 mutex_enter(&pcic_deb_mtx); 477 pcic_deb_threadid = 0; 478 while (!pcic_deb_threadid) 479 cv_wait(&pcic_deb_cv, &pcic_deb_mtx); 480 pcic_deb_threadid = 0; 481 mutex_exit(&pcic_deb_mtx); 482 483 mutex_destroy(&pcic_deb_mtx); 484 cv_destroy(&pcic_deb_cv); 485 } 486 487 ddi_soft_state_fini(&pcic_soft_state_p); 488 489 return (stat); 490 } 491 492 int 493 _info(struct modinfo *modinfop) 494 { 495 return (mod_info(&modlinkage, modinfop)); 496 } 497 498 /* 499 * pcic_getinfo() 500 * provide instance/device information about driver 501 */ 502 /*ARGSUSED*/ 503 static int 504 pcic_getinfo(dev_info_t *dip, ddi_info_cmd_t cmd, void *arg, void **result) 505 { 506 anp_t *anp; 507 int error = DDI_SUCCESS; 508 minor_t minor; 509 510 switch (cmd) { 511 case DDI_INFO_DEVT2DEVINFO: 512 minor = getminor((dev_t)arg); 513 if (minor == SYSHW_MINOR) 514 minor = 0; 515 else 516 minor &= 0x7f; 517 if (!(anp = ddi_get_soft_state(pcic_soft_state_p, minor))) 518 *result = NULL; 519 else 520 *result = anp->an_dip; 521 break; 522 case DDI_INFO_DEVT2INSTANCE: 523 minor = getminor((dev_t)arg); 524 if (minor == SYSHW_MINOR) 525 minor = 0; 526 else 527 minor &= 0x7f; 528 *result = (void *)((long)minor); 529 break; 530 default: 531 error = DDI_FAILURE; 532 break; 533 } 534 return (error); 535 } 536 537 static int 538 pcic_probe(dev_info_t *dip) 539 { 540 int value; 541 ddi_device_acc_attr_t attr; 542 ddi_acc_handle_t handle; 543 uchar_t *index, *data; 544 545 if (ddi_dev_is_sid(dip) == DDI_SUCCESS) 546 return (DDI_PROBE_DONTCARE); 547 548 /* 549 * find a PCIC device (any vendor) 550 * while there can be up to 4 such devices in 551 * a system, we currently only look for 1 552 * per probe. There will be up to 2 chips per 553 * instance since they share I/O space 554 */ 555 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 556 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 557 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 558 559 if (ddi_regs_map_setup(dip, PCIC_ISA_CONTROL_REG_NUM, 560 (caddr_t *)&index, 561 PCIC_ISA_CONTROL_REG_OFFSET, 562 PCIC_ISA_CONTROL_REG_LENGTH, 563 &attr, &handle) != DDI_SUCCESS) 564 return (DDI_PROBE_FAILURE); 565 566 data = index + 1; 567 568 #if defined(PCIC_DEBUG) 569 if (pcic_debug) 570 cmn_err(CE_CONT, "pcic_probe: entered\n"); 571 if (pcic_debug) 572 cmn_err(CE_CONT, "\tindex=%p\n", (void *)index); 573 #endif 574 ddi_put8(handle, index, PCIC_CHIP_REVISION); 575 ddi_put8(handle, data, 0); 576 value = ddi_get8(handle, data); 577 #if defined(PCIC_DEBUG) 578 if (pcic_debug) 579 cmn_err(CE_CONT, "\tchip revision register = %x\n", value); 580 #endif 581 if ((value & PCIC_REV_MASK) >= PCIC_REV_LEVEL_LOW && 582 (value & 0x30) == 0) { 583 /* 584 * we probably have a PCIC chip in the system 585 * do a little more checking. If we find one, 586 * reset everything in case of softboot 587 */ 588 ddi_put8(handle, index, PCIC_MAPPING_ENABLE); 589 ddi_put8(handle, data, 0); 590 value = ddi_get8(handle, data); 591 #if defined(PCIC_DEBUG) 592 if (pcic_debug) 593 cmn_err(CE_CONT, "\tzero test = %x\n", value); 594 #endif 595 /* should read back as zero */ 596 if (value == 0) { 597 /* 598 * we do have one and it is off the bus 599 */ 600 #if defined(PCIC_DEBUG) 601 if (pcic_debug) 602 cmn_err(CE_CONT, "pcic_probe: success\n"); 603 #endif 604 ddi_regs_map_free(&handle); 605 return (DDI_PROBE_SUCCESS); 606 } 607 } 608 #if defined(PCIC_DEBUG) 609 if (pcic_debug) 610 cmn_err(CE_CONT, "pcic_probe: failed\n"); 611 #endif 612 ddi_regs_map_free(&handle); 613 return (DDI_PROBE_FAILURE); 614 } 615 616 /* 617 * These are just defaults they can also be changed via a property in the 618 * conf file. 619 */ 620 static int pci_config_reg_num = PCIC_PCI_CONFIG_REG_NUM; 621 static int pci_control_reg_num = PCIC_PCI_CONTROL_REG_NUM; 622 static int pcic_do_pcmcia_sr = 0; 623 static int pcic_use_cbpwrctl = PCF_CBPWRCTL; 624 625 /* 626 * enable insertion/removal interrupt for 32bit cards 627 */ 628 static int 629 cardbus_enable_cd_intr(dev_info_t *dip) 630 { 631 ddi_acc_handle_t iohandle; 632 caddr_t ioaddr; 633 ddi_device_acc_attr_t attr; 634 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 635 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 636 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 637 (void) ddi_regs_map_setup(dip, 1, 638 (caddr_t *)&ioaddr, 639 0, 640 4096, 641 &attr, &iohandle); 642 643 /* CSC Interrupt: Card detect interrupt on */ 644 ddi_put32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_MASK), 645 ddi_get32(iohandle, 646 (uint32_t *)(ioaddr+CB_STATUS_MASK)) | CB_SE_CCDMASK); 647 648 ddi_put32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_EVENT), 649 ddi_get32(iohandle, (uint32_t *)(ioaddr+CB_STATUS_EVENT))); 650 651 ddi_regs_map_free(&iohandle); 652 return (1); 653 } 654 655 /* 656 * pcic_attach() 657 * attach the PCIC (Intel 82365SL/CirrusLogic/Toshiba) driver 658 * to the system. This is a child of "sysbus" since that is where 659 * the hardware lives, but it provides services to the "pcmcia" 660 * nexus driver. It gives a pointer back via its private data 661 * structure which contains both the dip and socket services entry 662 * points 663 */ 664 static int 665 pcic_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 666 { 667 anp_t *pcic_nexus; 668 pcicdev_t *pcic; 669 int irqlevel, value; 670 int pci_cfrn, pci_ctrn; 671 int i, j, smi, actual; 672 char *typename; 673 char bus_type[16] = "(unknown)"; 674 int len = sizeof (bus_type); 675 ddi_device_acc_attr_t attr; 676 anp_t *anp = ddi_get_driver_private(dip); 677 uint_t pri; 678 syshw_t *shwp; 679 680 #if defined(PCIC_DEBUG) 681 if (pcic_debug) { 682 cmn_err(CE_CONT, "pcic_attach: entered\n"); 683 } 684 #endif 685 switch (cmd) { 686 case DDI_ATTACH: 687 break; 688 case DDI_RESUME: 689 pcic = anp->an_private; 690 /* 691 * for now, this is a simulated resume. 692 * a real one may need different things. 693 */ 694 if (pcic != NULL && pcic->pc_flags & PCF_SUSPENDED) { 695 mutex_enter(&pcic->pc_lock); 696 /* should probe for new sockets showing up */ 697 pcic_setup_adapter(pcic); 698 syshw_resume(pcic); 699 pcic->pc_flags &= ~PCF_SUSPENDED; 700 mutex_exit(&pcic->pc_lock); 701 (void) pcmcia_begin_resume(dip); 702 /* 703 * this will do the CARD_INSERTION 704 * due to needing time for threads to 705 * run, it must be delayed for a short amount 706 * of time. pcmcia_wait_insert checks for all 707 * children to be removed and then triggers insert. 708 */ 709 /* 710 * The reason for having a single timeout here 711 * rather than seperate timeout()s for each instance 712 * is due to the limited number (2) of callout threads 713 * available in Solaris 2.6. A single 1250A ends up 714 * as two instances of the interface with one slot each. 715 * The pcic_delayed_resume() function ends by calling 716 * pcmcia_wait_insert() which at one point does a 717 * delay(). delay() is implemented with a timeout() 718 * call so you end up with both the callout() 719 * threads waiting to be woken up by another callout(). 720 * This situation locks up the machine hence the 721 * convolution here to only use one timeout. 722 */ 723 if (!pcic_delayed_resume_toid) 724 pcic_delayed_resume_toid = 725 timeout(pcic_delayed_resume, (caddr_t)0, 726 drv_usectohz(pcic_wait_insert_time)); 727 728 /* 729 * for complete implementation need END_RESUME (later) 730 */ 731 return (DDI_SUCCESS); 732 733 } 734 return (DDI_SUCCESS); 735 default: 736 return (DDI_FAILURE); 737 } 738 739 /* 740 * Allocate soft state associated with this instance. 741 */ 742 if (ddi_soft_state_zalloc(pcic_soft_state_p, 743 ddi_get_instance(dip)) != DDI_SUCCESS) { 744 cmn_err(CE_CONT, "pcic%d: Unable to alloc state\n", 745 ddi_get_instance(dip)); 746 return (DDI_FAILURE); 747 } 748 749 pcic_nexus = ddi_get_soft_state(pcic_soft_state_p, 750 ddi_get_instance(dip)); 751 752 pcic = kmem_zalloc(sizeof (pcicdev_t), KM_SLEEP); 753 754 pcic->dip = dip; 755 pcic_nexus->an_dip = dip; 756 pcic_nexus->an_if = &pcic_if_ops; 757 pcic_nexus->an_private = pcic; 758 pcic->pc_numpower = sizeof (pcic_power)/sizeof (pcic_power[0]); 759 pcic->pc_power = pcic_power; 760 761 pci_ctrn = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 762 "pci-control-reg-number", pci_control_reg_num); 763 pci_cfrn = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 764 "pci-config-reg-number", pci_config_reg_num); 765 766 ddi_set_driver_private(dip, pcic_nexus); 767 768 /* 769 * pcic->pc_irq is really the IPL level we want to run at 770 * set the default values here and override from intr spec 771 */ 772 pcic->pc_irq = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 773 "interrupt-priorities", -1); 774 775 if (pcic->pc_irq == -1) { 776 int actual; 777 uint_t pri; 778 ddi_intr_handle_t hdl; 779 780 /* see if intrspec tells us different */ 781 if (ddi_intr_alloc(dip, &hdl, DDI_INTR_TYPE_FIXED, 782 0, 1, &actual, DDI_INTR_ALLOC_NORMAL) == DDI_SUCCESS) { 783 if (ddi_intr_get_pri(hdl, &pri) == DDI_SUCCESS) 784 pcic->pc_irq = pri; 785 else 786 pcic->pc_irq = LOCK_LEVEL + 1; 787 (void) ddi_intr_free(hdl); 788 } 789 } 790 pcic_nexus->an_ipl = pcic->pc_irq; 791 792 /* 793 * Check our parent bus type. We do different things based on which 794 * bus we're on. 795 */ 796 if (ddi_prop_op(DDI_DEV_T_ANY, ddi_get_parent(dip), 797 PROP_LEN_AND_VAL_BUF, DDI_PROP_CANSLEEP, 798 "device_type", (caddr_t)&bus_type[0], &len) != 799 DDI_PROP_SUCCESS) { 800 if (ddi_prop_op(DDI_DEV_T_ANY, ddi_get_parent(dip), 801 PROP_LEN_AND_VAL_BUF, DDI_PROP_CANSLEEP, 802 "bus-type", (caddr_t)&bus_type[0], &len) != 803 DDI_PROP_SUCCESS) { 804 805 cmn_err(CE_CONT, 806 "pcic%d: can't find parent bus type\n", 807 ddi_get_instance(dip)); 808 809 kmem_free(pcic, sizeof (pcicdev_t)); 810 return (DDI_FAILURE); 811 } 812 } /* ddi_prop_op("device_type") */ 813 814 if (strcmp(bus_type, DEVI_PCI_NEXNAME) == 0) { 815 pcic->pc_flags = PCF_PCIBUS; 816 } else { 817 #if defined(__sparc) 818 cmn_err(CE_CONT, "pcic%d: unsupported parent bus type: [%s]\n", 819 ddi_get_instance(dip), bus_type); 820 821 kmem_free(pcic, sizeof (pcicdev_t)); 822 return (DDI_FAILURE); 823 #else 824 pcic->pc_flags = 0; 825 #endif 826 } 827 828 if ((pcic->bus_speed = ddi_getprop(DDI_DEV_T_ANY, ddi_get_parent(dip), 829 DDI_PROP_CANSLEEP, 830 "clock-frequency", 0)) == 0) { 831 if (pcic->pc_flags & PCF_PCIBUS) 832 pcic->bus_speed = PCIC_PCI_DEF_SYSCLK; 833 else 834 pcic->bus_speed = PCIC_ISA_DEF_SYSCLK; 835 } else { 836 /* 837 * OBP can declare the speed in Hz... 838 */ 839 if (pcic->bus_speed > 1000000) 840 pcic->bus_speed /= 1000000; 841 } /* ddi_prop_op("clock-frequency") */ 842 843 pcic->pc_io_type = PCIC_IO_TYPE_82365SL; /* default mode */ 844 845 #ifdef PCIC_DEBUG 846 if (pcic_debug) { 847 cmn_err(CE_CONT, 848 "pcic%d: parent bus type = [%s], speed = %d MHz\n", 849 ddi_get_instance(dip), 850 bus_type, pcic->bus_speed); 851 } 852 #endif 853 854 /* 855 * The reg properties on a PCI node are different than those 856 * on a non-PCI node. Handle that difference here. 857 * If it turns out to be a CardBus chip, we have even more 858 * differences. 859 */ 860 if (pcic->pc_flags & PCF_PCIBUS) { 861 int class_code; 862 #if defined(__i386) || defined(__amd64) 863 pcic->pc_base = 0x1000000; 864 pcic->pc_bound = (uint32_t)~0; 865 pcic->pc_iobase = 0x1000; 866 pcic->pc_iobound = 0xefff; 867 #elif defined(__sparc) 868 pcic->pc_base = 0x0; 869 pcic->pc_bound = (uint32_t)~0; 870 pcic->pc_iobase = 0x00000; 871 pcic->pc_iobound = 0xffff; 872 #endif 873 874 /* usually need to get at config space so map first */ 875 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 876 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 877 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 878 879 if (ddi_regs_map_setup(dip, pci_cfrn, 880 (caddr_t *)&pcic->cfgaddr, 881 PCIC_PCI_CONFIG_REG_OFFSET, 882 PCIC_PCI_CONFIG_REG_LENGTH, 883 &attr, 884 &pcic->cfg_handle) != 885 DDI_SUCCESS) { 886 cmn_err(CE_CONT, 887 "pcic%d: unable to map config space" 888 "regs\n", 889 ddi_get_instance(dip)); 890 891 kmem_free(pcic, sizeof (pcicdev_t)); 892 return (DDI_FAILURE); 893 } /* ddi_regs_map_setup */ 894 895 class_code = ddi_getprop(DDI_DEV_T_ANY, dip, 896 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 897 "class-code", -1); 898 #ifdef PCIC_DEBUG 899 if (pcic_debug) { 900 cmn_err(CE_CONT, "pcic_attach class_code=%x\n", 901 class_code); 902 } 903 #endif 904 905 switch (class_code) { 906 case PCIC_PCI_CARDBUS: 907 pcic->pc_flags |= PCF_CARDBUS; 908 pcic->pc_io_type = PCIC_IO_TYPE_YENTA; 909 /* 910 * Get access to the adapter registers on the 911 * PCI bus. A 4K memory page 912 */ 913 #if defined(PCIC_DEBUG) 914 pcic_err(dip, 8, "Is Cardbus device\n"); 915 if (pcic_debug) { 916 int nr; 917 long rs; 918 (void) ddi_dev_nregs(dip, &nr); 919 pcic_err(dip, 9, "\tdev, cfgaddr 0x%p," 920 "cfghndl 0x%p nregs %d", 921 (void *)pcic->cfgaddr, 922 (void *)pcic->cfg_handle, nr); 923 924 (void) ddi_dev_regsize(dip, 925 PCIC_PCI_CONTROL_REG_NUM, &rs); 926 927 pcic_err(dip, 9, "\tsize of reg %d is 0x%x\n", 928 PCIC_PCI_CONTROL_REG_NUM, (int)rs); 929 } 930 #endif 931 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 932 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 933 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 934 935 if (ddi_regs_map_setup(dip, pci_ctrn, 936 (caddr_t *)&pcic->ioaddr, 937 PCIC_PCI_CONTROL_REG_OFFSET, 938 PCIC_CB_CONTROL_REG_LENGTH, 939 &attr, &pcic->handle) != 940 DDI_SUCCESS) { 941 cmn_err(CE_CONT, 942 "pcic%d: unable to map PCI regs\n", 943 ddi_get_instance(dip)); 944 ddi_regs_map_free(&pcic->cfg_handle); 945 kmem_free(pcic, sizeof (pcicdev_t)); 946 return (DDI_FAILURE); 947 } /* ddi_regs_map_setup */ 948 949 /* 950 * Find out the chip type - If we're on a PCI bus, 951 * the adapter has that information in the PCI 952 * config space. 953 * Note that we call pcic_find_pci_type here since 954 * it needs a valid mapped pcic->handle to 955 * access some of the adapter registers in 956 * some cases. 957 */ 958 if (pcic_find_pci_type(pcic) != DDI_SUCCESS) { 959 ddi_regs_map_free(&pcic->handle); 960 ddi_regs_map_free(&pcic->cfg_handle); 961 kmem_free(pcic, sizeof (pcicdev_t)); 962 cmn_err(CE_WARN, "pcic: %s: unsupported " 963 "bridge\n", 964 ddi_get_name_addr(dip)); 965 return (DDI_FAILURE); 966 } 967 break; 968 969 default: 970 case PCIC_PCI_PCMCIA: 971 /* 972 * Get access to the adapter IO registers on the 973 * PCI bus config space. 974 */ 975 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 976 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 977 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 978 979 /* 980 * We need a default mapping to the adapter's IO 981 * control register space. For most adapters 982 * that are of class PCIC_PCI_PCMCIA (or of 983 * a default class) the control registers 984 * will be using the 82365-type control/data 985 * format. 986 */ 987 if (ddi_regs_map_setup(dip, pci_ctrn, 988 (caddr_t *)&pcic->ioaddr, 989 PCIC_PCI_CONTROL_REG_OFFSET, 990 PCIC_PCI_CONTROL_REG_LENGTH, 991 &attr, 992 &pcic->handle) != DDI_SUCCESS) { 993 cmn_err(CE_CONT, 994 "pcic%d: unable to map PCI regs\n", 995 ddi_get_instance(dip)); 996 ddi_regs_map_free(&pcic->cfg_handle); 997 kmem_free(pcic, sizeof (pcicdev_t)); 998 return (DDI_FAILURE); 999 } /* ddi_regs_map_setup */ 1000 1001 /* 1002 * Find out the chip type - If we're on a PCI bus, 1003 * the adapter has that information in the PCI 1004 * config space. 1005 * Note that we call pcic_find_pci_type here since 1006 * it needs a valid mapped pcic->handle to 1007 * access some of the adapter registers in 1008 * some cases. 1009 */ 1010 if (pcic_find_pci_type(pcic) != DDI_SUCCESS) { 1011 ddi_regs_map_free(&pcic->handle); 1012 ddi_regs_map_free(&pcic->cfg_handle); 1013 kmem_free(pcic, sizeof (pcicdev_t)); 1014 cmn_err(CE_WARN, "pcic: %s: unsupported " 1015 "bridge\n", 1016 ddi_get_name_addr(dip)); 1017 return (DDI_FAILURE); 1018 } 1019 1020 /* 1021 * Some PCI-PCMCIA(R2) adapters are Yenta-compliant 1022 * for extended registers even though they are 1023 * not CardBus adapters. For those adapters, 1024 * re-map pcic->handle to be large enough to 1025 * encompass the Yenta registers. 1026 */ 1027 switch (pcic->pc_type) { 1028 case PCIC_TI_PCI1031: 1029 ddi_regs_map_free(&pcic->handle); 1030 1031 if (ddi_regs_map_setup(dip, 1032 PCIC_PCI_CONTROL_REG_NUM, 1033 (caddr_t *)&pcic->ioaddr, 1034 PCIC_PCI_CONTROL_REG_OFFSET, 1035 PCIC_CB_CONTROL_REG_LENGTH, 1036 &attr, 1037 &pcic->handle) != DDI_SUCCESS) { 1038 cmn_err(CE_CONT, 1039 "pcic%d: unable to map " 1040 "PCI regs\n", 1041 ddi_get_instance(dip)); 1042 ddi_regs_map_free(&pcic->cfg_handle); 1043 kmem_free(pcic, sizeof (pcicdev_t)); 1044 return (DDI_FAILURE); 1045 } /* ddi_regs_map_setup */ 1046 break; 1047 default: 1048 break; 1049 } /* switch (pcic->pc_type) */ 1050 break; 1051 } /* switch (class_code) */ 1052 } else { 1053 /* 1054 * We're not on a PCI bus, so assume an ISA bus type 1055 * register property. Get access to the adapter IO 1056 * registers on a non-PCI bus. 1057 */ 1058 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 1059 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 1060 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1061 pcic->mem_reg_num = PCIC_ISA_MEM_REG_NUM; 1062 pcic->io_reg_num = PCIC_ISA_IO_REG_NUM; 1063 1064 if (ddi_regs_map_setup(dip, PCIC_ISA_CONTROL_REG_NUM, 1065 (caddr_t *)&pcic->ioaddr, 1066 PCIC_ISA_CONTROL_REG_OFFSET, 1067 PCIC_ISA_CONTROL_REG_LENGTH, 1068 &attr, 1069 &pcic->handle) != DDI_SUCCESS) { 1070 cmn_err(CE_CONT, 1071 "pcic%d: unable to map ISA registers\n", 1072 ddi_get_instance(dip)); 1073 1074 kmem_free(pcic, sizeof (pcicdev_t)); 1075 return (DDI_FAILURE); 1076 } /* ddi_regs_map_setup */ 1077 1078 /* ISA bus is limited to 24-bits, but not first 640K */ 1079 pcic->pc_base = 0xd0000; 1080 pcic->pc_bound = (uint32_t)~0; 1081 pcic->pc_iobase = 0x1000; 1082 pcic->pc_iobound = 0xefff; 1083 } /* !PCF_PCIBUS */ 1084 1085 #ifdef PCIC_DEBUG 1086 if (pcic_debug) { 1087 cmn_err(CE_CONT, "pcic_attach pc_flags=%x pc_type=%x\n", 1088 pcic->pc_flags, pcic->pc_type); 1089 } 1090 #endif 1091 1092 /* 1093 * Setup various adapter registers for the PCI case. For the 1094 * non-PCI case, find out the chip type. 1095 */ 1096 if (pcic->pc_flags & PCF_PCIBUS) { 1097 int iline; 1098 #if defined(__sparc) 1099 iline = 0; 1100 #else 1101 iline = cardbus_validate_iline(dip, pcic->cfg_handle); 1102 #endif 1103 1104 /* set flags and socket counts based on chip type */ 1105 switch (pcic->pc_type) { 1106 uint32_t cfg; 1107 case PCIC_INTEL_i82092: 1108 cfg = ddi_get8(pcic->cfg_handle, 1109 pcic->cfgaddr + PCIC_82092_PCICON); 1110 /* we can only support 4 Socket version */ 1111 if (cfg & PCIC_82092_4_SOCKETS) { 1112 pcic->pc_numsockets = 4; 1113 pcic->pc_type = PCIC_INTEL_i82092; 1114 if (iline != 0xFF) 1115 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1116 else 1117 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA; 1118 } else { 1119 cmn_err(CE_CONT, 1120 "pcic%d: Intel 82092 adapter " 1121 "in unsupported configuration: 0x%x", 1122 ddi_get_instance(pcic->dip), cfg); 1123 pcic->pc_numsockets = 0; 1124 } /* PCIC_82092_4_SOCKETS */ 1125 break; 1126 case PCIC_CL_PD6730: 1127 case PCIC_CL_PD6729: 1128 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1129 cfg = ddi_getprop(DDI_DEV_T_ANY, dip, 1130 DDI_PROP_CANSLEEP, 1131 "interrupts", 0); 1132 /* if not interrupt pin then must use ISA style IRQs */ 1133 if (cfg == 0 || iline == 0xFF) 1134 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA; 1135 else { 1136 /* 1137 * we have the option to use PCI interrupts. 1138 * this might not be optimal but in some cases 1139 * is the only thing possible (sparc case). 1140 * we now deterine what is possible. 1141 */ 1142 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1143 } 1144 pcic->pc_numsockets = 2; 1145 pcic->pc_flags |= PCF_IO_REMAP; 1146 break; 1147 case PCIC_TI_PCI1031: 1148 /* this chip doesn't do CardBus but looks like one */ 1149 pcic->pc_flags &= ~PCF_CARDBUS; 1150 /* FALLTHROUGH */ 1151 default: 1152 pcic->pc_flags |= PCF_IO_REMAP; 1153 /* FALLTHROUGH */ 1154 /* indicate feature even if not supported */ 1155 pcic->pc_flags |= PCF_DMA | PCF_ZV; 1156 /* Not sure if these apply to all these chips */ 1157 pcic->pc_flags |= (PCF_VPPX|PCF_33VCAP); 1158 pcic->pc_flags |= pcic_use_cbpwrctl; 1159 1160 pcic->pc_numsockets = 1; /* one per function */ 1161 if (iline != 0xFF) { 1162 uint8_t cfg; 1163 pcic->pc_intr_mode = PCIC_INTR_MODE_PCI_1; 1164 1165 cfg = ddi_get8(pcic->cfg_handle, 1166 (pcic->cfgaddr + PCIC_BRIDGE_CTL_REG)); 1167 cfg &= (~PCIC_FUN_INT_MOD_ISA); 1168 ddi_put8(pcic->cfg_handle, (pcic->cfgaddr + 1169 PCIC_BRIDGE_CTL_REG), cfg); 1170 } 1171 else 1172 pcic->pc_intr_mode = PCIC_INTR_MODE_ISA; 1173 pcic->pc_io_type = PCIC_IOTYPE_YENTA; 1174 break; 1175 } 1176 } else { 1177 /* 1178 * We're not on a PCI bus so do some more 1179 * checking for adapter type here. 1180 * For the non-PCI bus case: 1181 * It could be any one of a number of different chips 1182 * If we can't determine anything else, it is assumed 1183 * to be an Intel 82365SL. The Cirrus Logic PD6710 1184 * has an extension register that provides unique 1185 * identification. Toshiba chip isn't detailed as yet. 1186 */ 1187 1188 /* Init the CL id mode */ 1189 pcic_putb(pcic, 0, PCIC_CHIP_INFO, 0); 1190 value = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 1191 1192 /* default to Intel i82365SL and then refine */ 1193 pcic->pc_type = PCIC_I82365SL; 1194 pcic->pc_chipname = PCIC_TYPE_I82365SL; 1195 for (value = 0; pcic_ci_funcs[value] != NULL; value++) { 1196 /* go until one succeeds or none left */ 1197 if (pcic_ci_funcs[value](pcic)) 1198 break; 1199 } 1200 1201 /* any chip specific flags get set here */ 1202 switch (pcic->pc_type) { 1203 case PCIC_CL_PD6722: 1204 pcic->pc_flags |= PCF_DMA; 1205 } 1206 1207 for (i = 0; i < PCIC_MAX_SOCKETS; i++) { 1208 /* 1209 * look for total number of sockets. 1210 * basically check each possible socket for 1211 * presence like in probe 1212 */ 1213 1214 /* turn all windows off */ 1215 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1216 value = pcic_getb(pcic, i, PCIC_MAPPING_ENABLE); 1217 1218 /* 1219 * if a zero is read back, then this socket 1220 * might be present. It would be except for 1221 * some systems that map the secondary PCIC 1222 * chip space back to the first. 1223 */ 1224 if (value != 0) { 1225 /* definitely not so skip */ 1226 /* note: this is for Compaq support */ 1227 continue; 1228 } 1229 1230 /* further tests */ 1231 value = pcic_getb(pcic, i, PCIC_CHIP_REVISION) & 1232 PCIC_REV_MASK; 1233 if (!(value >= PCIC_REV_LEVEL_LOW && 1234 value <= PCIC_REV_LEVEL_HI)) 1235 break; 1236 1237 pcic_putb(pcic, i, PCIC_SYSMEM_0_STARTLOW, 0xaa); 1238 pcic_putb(pcic, i, PCIC_SYSMEM_1_STARTLOW, 0x55); 1239 value = pcic_getb(pcic, i, PCIC_SYSMEM_0_STARTLOW); 1240 1241 j = pcic_getb(pcic, i, PCIC_SYSMEM_1_STARTLOW); 1242 if (value != 0xaa || j != 0x55) 1243 break; 1244 1245 /* 1246 * at this point we know if we have hardware 1247 * of some type and not just the bus holding 1248 * a pattern for us. We still have to determine 1249 * the case where more than 2 sockets are 1250 * really the same due to peculiar mappings of 1251 * hardware. 1252 */ 1253 j = pcic->pc_numsockets++; 1254 pcic->pc_sockets[j].pcs_flags = 0; 1255 pcic->pc_sockets[j].pcs_io = pcic->ioaddr; 1256 pcic->pc_sockets[j].pcs_socket = i; 1257 1258 /* put PC Card into RESET, just in case */ 1259 value = pcic_getb(pcic, i, PCIC_INTERRUPT); 1260 pcic_putb(pcic, i, PCIC_INTERRUPT, 1261 value & ~PCIC_RESET); 1262 } 1263 1264 #if defined(PCIC_DEBUG) 1265 if (pcic_debug) 1266 cmn_err(CE_CONT, "num sockets = %d\n", 1267 pcic->pc_numsockets); 1268 #endif 1269 if (pcic->pc_numsockets == 0) { 1270 ddi_regs_map_free(&pcic->handle); 1271 kmem_free(pcic, sizeof (pcicdev_t)); 1272 return (DDI_FAILURE); 1273 } 1274 1275 /* 1276 * need to think this through again in light of 1277 * Compaq not following the model that all the 1278 * chip vendors recommend. IBM 755 seems to be 1279 * afflicted as well. Basically, if the vendor 1280 * wired things wrong, socket 0 responds for socket 2 1281 * accesses, etc. 1282 */ 1283 if (pcic->pc_numsockets > 2) { 1284 int count = pcic->pc_numsockets / 4; 1285 for (i = 0; i < count; i++) { 1286 /* put pattern into socket 0 */ 1287 pcic_putb(pcic, i, 1288 PCIC_SYSMEM_0_STARTLOW, 0x11); 1289 1290 /* put pattern into socket 2 */ 1291 pcic_putb(pcic, i + 2, 1292 PCIC_SYSMEM_0_STARTLOW, 0x33); 1293 1294 /* read back socket 0 */ 1295 value = pcic_getb(pcic, i, 1296 PCIC_SYSMEM_0_STARTLOW); 1297 1298 /* read back chip 1 socket 0 */ 1299 j = pcic_getb(pcic, i + 2, 1300 PCIC_SYSMEM_0_STARTLOW); 1301 if (j == value) { 1302 pcic->pc_numsockets -= 2; 1303 } 1304 } 1305 } 1306 1307 smi = 0xff; /* no more override */ 1308 1309 if (ddi_getprop(DDI_DEV_T_NONE, dip, 1310 DDI_PROP_DONTPASS, "need-mult-irq", 1311 0xffff) != 0xffff) 1312 pcic->pc_flags |= PCF_MULT_IRQ; 1313 1314 } /* !PCF_PCIBUS */ 1315 1316 /* 1317 * some platforms/busses need to have resources setup 1318 * this is temporary until a real resource allocator is 1319 * implemented. 1320 */ 1321 1322 pcic_init_assigned(dip); 1323 1324 typename = pcic->pc_chipname; 1325 1326 #ifdef PCIC_DEBUG 1327 if (pcic_debug) { 1328 int nregs, nintrs; 1329 1330 if (ddi_dev_nregs(dip, &nregs) != DDI_SUCCESS) 1331 nregs = 0; 1332 1333 if (ddi_dev_nintrs(dip, &nintrs) != DDI_SUCCESS) 1334 nintrs = 0; 1335 1336 cmn_err(CE_CONT, 1337 "pcic%d: %d register sets, %d interrupts\n", 1338 ddi_get_instance(dip), nregs, nintrs); 1339 1340 nintrs = 0; 1341 while (nregs--) { 1342 off_t size; 1343 1344 if (ddi_dev_regsize(dip, nintrs, &size) == 1345 DDI_SUCCESS) { 1346 cmn_err(CE_CONT, 1347 "\tregnum %d size %ld (0x%lx)" 1348 "bytes", 1349 nintrs, size, size); 1350 if (nintrs == 1351 (pcic->pc_io_type == PCIC_IO_TYPE_82365SL ? 1352 PCIC_ISA_CONTROL_REG_NUM : 1353 PCIC_PCI_CONTROL_REG_NUM)) 1354 cmn_err(CE_CONT, 1355 " mapped at: 0x%p\n", 1356 (void *)pcic->ioaddr); 1357 else 1358 cmn_err(CE_CONT, "\n"); 1359 } else { 1360 cmn_err(CE_CONT, 1361 "\tddi_dev_regsize(rnumber" 1362 "= %d) returns DDI_FAILURE\n", 1363 nintrs); 1364 } 1365 nintrs++; 1366 } /* while */ 1367 } /* if (pcic_debug) */ 1368 #endif 1369 1370 cv_init(&pcic->pm_cv, NULL, CV_DRIVER, NULL); 1371 1372 if (!ddi_getprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 1373 "disable-audio", 0)) 1374 pcic->pc_flags |= PCF_AUDIO; 1375 1376 if (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_CANSLEEP, 1377 "disable-cardbus", 0)) 1378 pcic->pc_flags &= ~PCF_CARDBUS; 1379 1380 (void) ddi_prop_update_string(DDI_DEV_T_NONE, dip, PCICPROP_CTL, 1381 typename); 1382 1383 /* 1384 * Init all socket SMI levels to 0 (no SMI) 1385 */ 1386 for (i = 0; i < PCIC_MAX_SOCKETS; i++) { 1387 pcic->pc_sockets[i].pcs_smi = 0; 1388 pcic->pc_sockets[i].pcs_debounce_id = 0; 1389 pcic->pc_sockets[i].pcs_pcic = pcic; 1390 } 1391 pcic->pc_lastreg = -1; /* just to make sure we are in sync */ 1392 1393 /* 1394 * Setup the IRQ handler(s) 1395 */ 1396 switch (pcic->pc_intr_mode) { 1397 int xx; 1398 case PCIC_INTR_MODE_ISA: 1399 /* 1400 * On a non-PCI bus, we just use whatever SMI IRQ level was 1401 * specified above, and the IO IRQ levels are allocated 1402 * dynamically. 1403 */ 1404 for (xx = 15, smi = 0; xx >= 0; xx--) { 1405 if (PCIC_IRQ(xx) & 1406 PCIC_AVAIL_IRQS) { 1407 smi = pcmcia_get_intr(dip, xx); 1408 if (smi >= 0) 1409 break; 1410 } 1411 } 1412 #if defined(PCIC_DEBUG) 1413 if (pcic_debug) 1414 cmn_err(CE_NOTE, "\tselected IRQ %d as SMI\n", smi); 1415 #endif 1416 /* init to same so share is easy */ 1417 for (i = 0; i < pcic->pc_numsockets; i++) 1418 pcic->pc_sockets[i].pcs_smi = smi; 1419 /* any special handling of IRQ levels */ 1420 if (pcic->pc_flags & PCF_MULT_IRQ) { 1421 for (i = 2; i < pcic->pc_numsockets; i++) { 1422 if ((i & 1) == 0) { 1423 int xx; 1424 for (xx = 15, smi = 0; xx >= 0; xx--) { 1425 if (PCIC_IRQ(xx) & 1426 PCIC_AVAIL_IRQS) { 1427 smi = 1428 pcmcia_get_intr(dip, 1429 xx); 1430 if (smi >= 0) 1431 break; 1432 } 1433 } 1434 } 1435 if (smi >= 0) 1436 pcic->pc_sockets[i].pcs_smi = smi; 1437 } 1438 } 1439 pcic->pc_intr_htblp = kmem_alloc(pcic->pc_numsockets * 1440 sizeof (ddi_intr_handle_t), KM_SLEEP); 1441 for (i = 0, irqlevel = -1; i < pcic->pc_numsockets; i++) { 1442 struct intrspec *ispecp; 1443 struct ddi_parent_private_data *pdp; 1444 1445 if (irqlevel == pcic->pc_sockets[i].pcs_smi) 1446 continue; 1447 else { 1448 irqlevel = pcic->pc_sockets[i].pcs_smi; 1449 } 1450 /* 1451 * now convert the allocated IRQ into an intrspec 1452 * and ask our parent to add it. Don't use 1453 * the ddi_add_intr since we don't have a 1454 * default intrspec in all cases. 1455 * 1456 * note: this sort of violates DDI but we don't 1457 * get hardware intrspecs for many of the devices. 1458 * at the same time, we know how to allocate them 1459 * so we do the right thing. 1460 */ 1461 if (ddi_intr_alloc(dip, &pcic->pc_intr_htblp[i], 1462 DDI_INTR_TYPE_FIXED, 0, 1, &actual, 1463 DDI_INTR_ALLOC_NORMAL) != DDI_SUCCESS) { 1464 cmn_err(CE_WARN, "%s: ddi_intr_alloc failed", 1465 ddi_get_name(dip)); 1466 goto isa_exit1; 1467 } 1468 1469 /* 1470 * See earlier note: 1471 * Since some devices don't have 'intrspec' 1472 * we make one up in rootnex. 1473 * 1474 * However, it is not properly initialized as 1475 * the data it needs is present in this driver 1476 * and there is no interface to pass that up. 1477 * Specially 'irqlevel' is very important and 1478 * it is part of pcic struct. 1479 * 1480 * Set 'intrspec' up here; otherwise adding the 1481 * interrupt will fail. 1482 */ 1483 pdp = ddi_get_parent_data(dip); 1484 ispecp = (struct intrspec *)&pdp->par_intr[0]; 1485 ispecp->intrspec_vec = irqlevel; 1486 ispecp->intrspec_pri = pcic->pc_irq; 1487 1488 /* Stay compatible w/ PCMCIA */ 1489 pcic->pc_pri = (ddi_iblock_cookie_t) 1490 (uintptr_t)pcic->pc_irq; 1491 pcic->pc_dcookie.idev_priority = 1492 (uintptr_t)pcic->pc_pri; 1493 pcic->pc_dcookie.idev_vector = (ushort_t)irqlevel; 1494 1495 (void) ddi_intr_set_pri(pcic->pc_intr_htblp[i], 1496 pcic->pc_irq); 1497 1498 if (i == 0) { 1499 mutex_init(&pcic->intr_lock, NULL, MUTEX_DRIVER, 1500 DDI_INTR_PRI(pcic->pc_irq)); 1501 mutex_init(&pcic->pc_lock, NULL, MUTEX_DRIVER, 1502 NULL); 1503 } 1504 1505 if (ddi_intr_add_handler(pcic->pc_intr_htblp[i], 1506 pcic_intr, (caddr_t)pcic, NULL)) { 1507 cmn_err(CE_WARN, 1508 "%s: ddi_intr_add_handler failed", 1509 ddi_get_name(dip)); 1510 goto isa_exit2; 1511 } 1512 1513 if (ddi_intr_enable(pcic->pc_intr_htblp[i])) { 1514 cmn_err(CE_WARN, "%s: ddi_intr_enable failed", 1515 ddi_get_name(dip)); 1516 for (j = i; j < 0; j--) 1517 (void) ddi_intr_remove_handler( 1518 pcic->pc_intr_htblp[j]); 1519 goto isa_exit2; 1520 } 1521 } 1522 break; 1523 case PCIC_INTR_MODE_PCI_1: 1524 case PCIC_INTR_MODE_PCI: 1525 /* 1526 * If we're on a PCI bus, we route all interrupts, both SMI 1527 * and IO interrupts, through a single interrupt line. 1528 * Assign the SMI IRQ level to the IO IRQ level here. 1529 */ 1530 pcic->pc_pci_intr_hdlp = kmem_alloc(sizeof (ddi_intr_handle_t), 1531 KM_SLEEP); 1532 if (ddi_intr_alloc(dip, pcic->pc_pci_intr_hdlp, 1533 DDI_INTR_TYPE_FIXED, 0, 1, &actual, 1534 DDI_INTR_ALLOC_NORMAL) != DDI_SUCCESS) 1535 goto pci_exit1; 1536 1537 if (ddi_intr_get_pri(pcic->pc_pci_intr_hdlp[0], 1538 &pri) != DDI_SUCCESS) { 1539 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]); 1540 goto pci_exit1; 1541 } 1542 1543 pcic->pc_pri = (void *)(uintptr_t)pri; 1544 mutex_init(&pcic->intr_lock, NULL, MUTEX_DRIVER, pcic->pc_pri); 1545 mutex_init(&pcic->pc_lock, NULL, MUTEX_DRIVER, NULL); 1546 1547 if (ddi_intr_add_handler(pcic->pc_pci_intr_hdlp[0], 1548 pcic_intr, (caddr_t)pcic, NULL)) 1549 goto pci_exit2; 1550 1551 if (ddi_intr_enable(pcic->pc_pci_intr_hdlp[0])) { 1552 (void) ddi_intr_remove_handler( 1553 pcic->pc_pci_intr_hdlp[0]); 1554 goto pci_exit2; 1555 } 1556 1557 /* Stay compatible w/ PCMCIA */ 1558 pcic->pc_dcookie.idev_priority = (ushort_t)pri; 1559 1560 /* init to same (PCI) so share is easy */ 1561 for (i = 0; i < pcic->pc_numsockets; i++) 1562 pcic->pc_sockets[i].pcs_smi = 0xF; /* any valid */ 1563 break; 1564 } 1565 1566 /* 1567 * Setup the adapter hardware to some reasonable defaults. 1568 */ 1569 mutex_enter(&pcic->pc_lock); 1570 /* mark the driver state as attached */ 1571 pcic->pc_flags |= PCF_ATTACHED; 1572 pcic_setup_adapter(pcic); 1573 1574 for (j = 0; j < pcic->pc_numsockets; j++) 1575 if (ddi_intr_add_softint(dip, 1576 &pcic->pc_sockets[j].pcs_cd_softint_hdl, 1577 PCIC_SOFTINT_PRI_VAL, pcic_cd_softint, 1578 (caddr_t)&pcic->pc_sockets[j]) != DDI_SUCCESS) 1579 goto pci_exit2; 1580 1581 #if defined(PCIC_DEBUG) 1582 if (pcic_debug) 1583 cmn_err(CE_CONT, "type = %s sockets = %d\n", typename, 1584 pcic->pc_numsockets); 1585 #endif 1586 1587 pcic_nexus->an_iblock = &pcic->pc_pri; 1588 pcic_nexus->an_idev = &pcic->pc_dcookie; 1589 1590 mutex_exit(&pcic->pc_lock); 1591 1592 #ifdef CARDBUS 1593 (void) cardbus_enable_cd_intr(dip); 1594 if (pcic_debug) { 1595 1596 cardbus_dump_pci_config(dip); 1597 cardbus_dump_socket(dip); 1598 } 1599 1600 /* 1601 * Give the Cardbus misc module a chance to do it's per-adapter 1602 * instance setup. Note that there is no corresponding detach() 1603 * call. 1604 */ 1605 if (pcic->pc_flags & PCF_CARDBUS) 1606 if (cardbus_attach(dip, &pcic_cbnexus_ops) != DDI_SUCCESS) { 1607 cmn_err(CE_CONT, 1608 "pcic_attach: cardbus_attach failed\n"); 1609 goto pci_exit2; 1610 } 1611 #endif 1612 1613 /* 1614 * Give the PCMCIA misc module a chance to do it's per-adapter 1615 * instance setup. 1616 */ 1617 if ((i = pcmcia_attach(dip, pcic_nexus)) != DDI_SUCCESS) 1618 goto pci_exit2; 1619 1620 syshw_attach(pcic); 1621 if (pcic_maxinst == -1) { 1622 /* This assumes that all instances run at the same IPL. */ 1623 mutex_init(&pcic_deb_mtx, NULL, MUTEX_DRIVER, NULL); 1624 cv_init(&pcic_deb_cv, NULL, CV_DRIVER, NULL); 1625 pcic_deb_threadid = thread_create((caddr_t)NULL, 0, 1626 pcic_deb_thread, (caddr_t)NULL, 0, &p0, TS_RUN, 1627 v.v_maxsyspri - 2); 1628 } 1629 pcic_maxinst = max(pcic_maxinst, ddi_get_instance(dip)); 1630 /* 1631 * Setup a debounce timeout to do an initial card detect 1632 * and enable interrupts. 1633 */ 1634 for (j = 0; j < pcic->pc_numsockets; j++) { 1635 shwp = kmem_alloc(sizeof (syshw_t), KM_SLEEP); 1636 if (shwp) { 1637 bcopy(&pcic_syshw, shwp, sizeof (pcic_syshw)); 1638 pcic_syshw.id_string[15]++; 1639 pcic->pc_sockets[j].pcs_syshwsig = 1640 syshw_add2map(shwp, pcic_syshw_cardstate, 1641 &pcic->pc_sockets[j]); 1642 } 1643 pcic->pc_sockets[j].pcs_debounce_id = 1644 pcic_add_debqueue(&pcic->pc_sockets[j], 1645 drv_usectohz(pcic_debounce_time)); 1646 } 1647 1648 return (i); 1649 1650 isa_exit2: 1651 mutex_destroy(&pcic->intr_lock); 1652 mutex_destroy(&pcic->pc_lock); 1653 for (j = i; j < 0; j--) 1654 (void) ddi_intr_free(pcic->pc_intr_htblp[j]); 1655 isa_exit1: 1656 (void) pcmcia_return_intr(dip, pcic->pc_sockets[i].pcs_smi); 1657 ddi_regs_map_free(&pcic->handle); 1658 if (pcic->pc_flags & PCF_PCIBUS) 1659 ddi_regs_map_free(&pcic->cfg_handle); 1660 kmem_free(pcic->pc_intr_htblp, pcic->pc_numsockets * 1661 sizeof (ddi_intr_handle_t)); 1662 kmem_free(pcic, sizeof (pcicdev_t)); 1663 return (DDI_FAILURE); 1664 1665 pci_exit2: 1666 mutex_destroy(&pcic->intr_lock); 1667 mutex_destroy(&pcic->pc_lock); 1668 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]); 1669 pci_exit1: 1670 ddi_regs_map_free(&pcic->handle); 1671 if (pcic->pc_flags & PCF_PCIBUS) 1672 ddi_regs_map_free(&pcic->cfg_handle); 1673 kmem_free(pcic->pc_pci_intr_hdlp, sizeof (ddi_intr_handle_t)); 1674 kmem_free(pcic, sizeof (pcicdev_t)); 1675 return (DDI_FAILURE); 1676 } 1677 1678 /* 1679 * pcic_detach() 1680 * request to detach from the system 1681 */ 1682 static int 1683 pcic_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 1684 { 1685 anp_t *anp = ddi_get_driver_private(dip); 1686 pcicdev_t *pcic = anp->an_private; 1687 int i; 1688 1689 switch (cmd) { 1690 case DDI_DETACH: 1691 /* don't detach if the nexus still talks to us */ 1692 if (pcic->pc_callback != NULL) 1693 return (DDI_FAILURE); 1694 syshw_detach(pcic); 1695 1696 /* kill off the pm simulation */ 1697 if (pcic->pc_pmtimer) 1698 (void) untimeout(pcic->pc_pmtimer); 1699 1700 /* turn everything off for all sockets and chips */ 1701 for (i = 0; i < pcic->pc_numsockets; i++) { 1702 if (pcic->pc_sockets[i].pcs_debounce_id) 1703 pcic_rm_debqueue( 1704 pcic->pc_sockets[i].pcs_debounce_id); 1705 pcic->pc_sockets[i].pcs_debounce_id = 0; 1706 1707 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 0); 1708 pcic_putb(pcic, i, PCIC_CARD_DETECT, 0); 1709 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1710 /* disable interrupts and put card into RESET */ 1711 pcic_putb(pcic, i, PCIC_INTERRUPT, 0); 1712 } 1713 (void) ddi_intr_disable(pcic->pc_pci_intr_hdlp[0]); 1714 (void) ddi_intr_remove_handler(pcic->pc_pci_intr_hdlp[0]); 1715 (void) ddi_intr_free(pcic->pc_pci_intr_hdlp[0]); 1716 kmem_free(pcic->pc_pci_intr_hdlp, sizeof (ddi_intr_handle_t)); 1717 pcic->pc_flags = 0; 1718 mutex_destroy(&pcic->pc_lock); 1719 mutex_destroy(&pcic->intr_lock); 1720 cv_destroy(&pcic->pm_cv); 1721 if (pcic->pc_flags & PCF_PCIBUS) 1722 ddi_regs_map_free(&pcic->cfg_handle); 1723 if (pcic->handle) 1724 ddi_regs_map_free(&pcic->handle); 1725 kmem_free(pcic, sizeof (pcicdev_t)); 1726 ddi_soft_state_free(pcic_soft_state_p, ddi_get_instance(dip)); 1727 return (DDI_SUCCESS); 1728 1729 case DDI_SUSPEND: 1730 case DDI_PM_SUSPEND: 1731 /* 1732 * we got a suspend event (either real or imagined) 1733 * so notify the nexus proper that all existing cards 1734 * should go away. 1735 */ 1736 mutex_enter(&pcic->pc_lock); 1737 #ifdef CARDBUS 1738 if (pcic->pc_flags & PCF_CARDBUS) 1739 for (i = 0; i < pcic->pc_numsockets; i++) 1740 if ((pcic->pc_sockets[i].pcs_flags & 1741 (PCS_CARD_PRESENT|PCS_CARD_ISCARDBUS)) == 1742 (PCS_CARD_PRESENT|PCS_CARD_ISCARDBUS)) 1743 if (!cardbus_can_suspend(dip)) { 1744 mutex_exit(&pcic->pc_lock); 1745 cmn_err(CE_WARN, 1746 "Please unconfigure all " 1747 "CardBus devices before " 1748 "attempting to suspend\n"); 1749 return (DDI_FAILURE); 1750 } 1751 #endif 1752 /* turn everything off for all sockets and chips */ 1753 for (i = 0; i < pcic->pc_numsockets; i++) { 1754 if (pcic->pc_sockets[i].pcs_debounce_id) 1755 pcic_rm_debqueue( 1756 pcic->pc_sockets[i].pcs_debounce_id); 1757 pcic->pc_sockets[i].pcs_debounce_id = 0; 1758 1759 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 0); 1760 pcic_putb(pcic, i, PCIC_CARD_DETECT, 0); 1761 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1762 /* disable interrupts and put card into RESET */ 1763 pcic_putb(pcic, i, PCIC_INTERRUPT, 0); 1764 pcic_putb(pcic, i, PCIC_POWER_CONTROL, 0); 1765 if (pcic->pc_flags & PCF_CBPWRCTL) 1766 pcic_putcb(pcic, CB_CONTROL, 0); 1767 1768 if (pcic->pc_sockets[i].pcs_flags & PCS_CARD_PRESENT) { 1769 pcic->pc_sockets[i].pcs_flags = PCS_STARTING; 1770 /* 1771 * Because we are half way through a save 1772 * all this does is schedule a removal event 1773 * to cs for when the system comes back. 1774 * This doesn't actually matter. 1775 */ 1776 if (!pcic_do_pcmcia_sr && pcic_do_removal && 1777 pcic->pc_callback) { 1778 PC_CALLBACK(pcic->dip, pcic->pc_cb_arg, 1779 PCE_CARD_REMOVAL, 1780 pcic->pc_sockets[i].pcs_socket); 1781 } 1782 } 1783 } 1784 1785 pcic->pc_flags |= PCF_SUSPENDED; 1786 mutex_exit(&pcic->pc_lock); 1787 pcic_delayed_resume_toid = 0; 1788 1789 /* 1790 * when true power management exists, save the adapter 1791 * state here to enable a recovery. For the emulation 1792 * condition, the state is gone 1793 */ 1794 return (DDI_SUCCESS); 1795 1796 default: 1797 return (EINVAL); 1798 } 1799 } 1800 1801 static uint32_t pcic_tisysctl_onbits = ((1<<27) | (1<<15) | (1<<14)); 1802 static uint32_t pcic_tisysctl_offbits = 0; 1803 static uint32_t pcic_default_latency = 0x40; 1804 1805 static void 1806 pcic_setup_adapter(pcicdev_t *pcic) 1807 { 1808 int i; 1809 int value, flags; 1810 1811 if (pcic->pc_flags & PCF_PCIBUS) { 1812 /* 1813 * all PCI-to-PCMCIA bus bridges need memory and I/O enabled 1814 */ 1815 flags = (PCIC_ENABLE_IO | PCIC_ENABLE_MEM); 1816 pcic_iomem_pci_ctl(pcic->cfg_handle, pcic->cfgaddr, flags); 1817 } 1818 /* enable each socket */ 1819 for (i = 0; i < pcic->pc_numsockets; i++) { 1820 pcic->pc_sockets[i].pcs_flags = 0; 1821 /* find out the socket capabilities (I/O vs memory) */ 1822 value = pcic_getb(pcic, i, 1823 PCIC_CHIP_REVISION) & PCIC_REV_ID_MASK; 1824 if (value == PCIC_REV_ID_IO || value == PCIC_REV_ID_BOTH) 1825 pcic->pc_sockets[i].pcs_flags |= PCS_SOCKET_IO; 1826 1827 /* disable all windows just in case */ 1828 pcic_putb(pcic, i, PCIC_MAPPING_ENABLE, 0); 1829 1830 switch (pcic->pc_type) { 1831 uint32_t cfg32; 1832 uint16_t cfg16; 1833 uint8_t cfg; 1834 1835 /* enable extended registers for Vadem */ 1836 case PCIC_VADEM_VG469: 1837 case PCIC_VADEM: 1838 1839 /* enable card status change interrupt for socket */ 1840 break; 1841 1842 case PCIC_I82365SL: 1843 break; 1844 1845 case PCIC_CL_PD6710: 1846 pcic_putb(pcic, 0, PCIC_MISC_CTL_2, PCIC_LED_ENABLE); 1847 break; 1848 1849 /* 1850 * On the CL_6730, we need to set up the interrupt 1851 * signalling mode (PCI mode) and set the SMI and 1852 * IRQ interrupt lines to PCI/level-mode. 1853 */ 1854 case PCIC_CL_PD6730: 1855 switch (pcic->pc_intr_mode) { 1856 case PCIC_INTR_MODE_PCI_1: 1857 clext_reg_write(pcic, i, PCIC_CLEXT_MISC_CTL_3, 1858 ((clext_reg_read(pcic, i, 1859 PCIC_CLEXT_MISC_CTL_3) & 1860 ~PCIC_CLEXT_INT_PCI) | 1861 PCIC_CLEXT_INT_PCI)); 1862 clext_reg_write(pcic, i, PCIC_CLEXT_EXT_CTL_1, 1863 (PCIC_CLEXT_IRQ_LVL_MODE | 1864 PCIC_CLEXT_SMI_LVL_MODE)); 1865 cfg = PCIC_CL_LP_DYN_MODE; 1866 pcic_putb(pcic, i, PCIC_MISC_CTL_2, cfg); 1867 break; 1868 case PCIC_INTR_MODE_ISA: 1869 break; 1870 } 1871 break; 1872 /* 1873 * On the CL_6729, we set the SMI and IRQ interrupt 1874 * lines to PCI/level-mode. as well as program the 1875 * correct clock speed divider bit. 1876 */ 1877 case PCIC_CL_PD6729: 1878 switch (pcic->pc_intr_mode) { 1879 case PCIC_INTR_MODE_PCI_1: 1880 clext_reg_write(pcic, i, PCIC_CLEXT_EXT_CTL_1, 1881 (PCIC_CLEXT_IRQ_LVL_MODE | 1882 PCIC_CLEXT_SMI_LVL_MODE)); 1883 1884 break; 1885 case PCIC_INTR_MODE_ISA: 1886 break; 1887 } 1888 if (pcic->bus_speed > PCIC_PCI_25MHZ && i == 0) { 1889 cfg = 0; 1890 cfg |= PCIC_CL_TIMER_CLK_DIV; 1891 pcic_putb(pcic, i, PCIC_MISC_CTL_2, cfg); 1892 } 1893 break; 1894 case PCIC_INTEL_i82092: 1895 cfg = PCIC_82092_EN_TIMING; 1896 if (pcic->bus_speed < PCIC_SYSCLK_33MHZ) 1897 cfg |= PCIC_82092_PCICLK_25MHZ; 1898 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + 1899 PCIC_82092_PCICON, cfg); 1900 break; 1901 case PCIC_TI_PCI1130: 1902 case PCIC_TI_PCI1131: 1903 case PCIC_TI_PCI1250: 1904 case PCIC_TI_PCI1031: 1905 cfg = ddi_get8(pcic->cfg_handle, 1906 pcic->cfgaddr + PCIC_DEVCTL_REG); 1907 cfg &= ~PCIC_DEVCTL_INTR_MASK; 1908 switch (pcic->pc_intr_mode) { 1909 case PCIC_INTR_MODE_ISA: 1910 cfg |= PCIC_DEVCTL_INTR_ISA; 1911 break; 1912 } 1913 #ifdef PCIC_DEBUG 1914 if (pcic_debug) { 1915 cmn_err(CE_CONT, "pcic_setup_adapter: " 1916 "write reg 0x%x=%x \n", 1917 PCIC_DEVCTL_REG, cfg); 1918 } 1919 #endif 1920 ddi_put8(pcic->cfg_handle, 1921 pcic->cfgaddr + PCIC_DEVCTL_REG, 1922 cfg); 1923 1924 cfg = ddi_get8(pcic->cfg_handle, 1925 pcic->cfgaddr + PCIC_CRDCTL_REG); 1926 cfg &= ~(PCIC_CRDCTL_PCIINTR|PCIC_CRDCTL_PCICSC| 1927 PCIC_CRDCTL_PCIFUNC); 1928 switch (pcic->pc_intr_mode) { 1929 case PCIC_INTR_MODE_PCI_1: 1930 cfg |= PCIC_CRDCTL_PCIINTR | 1931 PCIC_CRDCTL_PCICSC | 1932 PCIC_CRDCTL_PCIFUNC; 1933 pcic->pc_flags |= PCF_USE_SMI; 1934 break; 1935 } 1936 #ifdef PCIC_DEBUG 1937 if (pcic_debug) { 1938 cmn_err(CE_CONT, "pcic_setup_adapter: " 1939 " write reg 0x%x=%x \n", 1940 PCIC_CRDCTL_REG, cfg); 1941 } 1942 #endif 1943 ddi_put8(pcic->cfg_handle, 1944 pcic->cfgaddr + PCIC_CRDCTL_REG, 1945 cfg); 1946 break; 1947 case PCIC_TI_PCI1221: 1948 case PCIC_TI_PCI1225: 1949 cfg = ddi_get8(pcic->cfg_handle, 1950 pcic->cfgaddr + PCIC_DEVCTL_REG); 1951 cfg |= (PCIC_DEVCTL_INTR_DFLT | PCIC_DEVCTL_3VCAPABLE); 1952 #ifdef PCIC_DEBUG 1953 if (pcic_debug) { 1954 cmn_err(CE_CONT, "pcic_setup_adapter: " 1955 " write reg 0x%x=%x \n", 1956 PCIC_DEVCTL_REG, cfg); 1957 } 1958 #endif 1959 ddi_put8(pcic->cfg_handle, 1960 pcic->cfgaddr + PCIC_DEVCTL_REG, cfg); 1961 1962 cfg = ddi_get8(pcic->cfg_handle, 1963 pcic->cfgaddr + PCIC_DIAG_REG); 1964 if (pcic->pc_type == PCIC_TI_PCI1225) { 1965 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC); 1966 } else { 1967 cfg |= PCIC_DIAG_ASYNC; 1968 } 1969 pcic->pc_flags |= PCF_USE_SMI; 1970 #ifdef PCIC_DEBUG 1971 if (pcic_debug) { 1972 cmn_err(CE_CONT, "pcic_setup_adapter: " 1973 " write reg 0x%x=%x \n", 1974 PCIC_DIAG_REG, cfg); 1975 } 1976 #endif 1977 ddi_put8(pcic->cfg_handle, 1978 pcic->cfgaddr + PCIC_DIAG_REG, cfg); 1979 break; 1980 case PCIC_TI_PCI1520: 1981 case PCIC_TI_VENDOR: 1982 if (pcic->pc_intr_mode == PCIC_INTR_MODE_ISA) { 1983 cfg = ddi_get8(pcic->cfg_handle, 1984 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 1985 cfg |= PCIC_FUN_INT_MOD_ISA; 1986 ddi_put8(pcic->cfg_handle, 1987 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 1988 cfg); 1989 } 1990 cfg = ddi_get8(pcic->cfg_handle, 1991 pcic->cfgaddr + PCIC_DEVCTL_REG); 1992 cfg &= ~PCIC_DEVCTL_INTR_MASK; 1993 if (pcic->pc_intr_mode == PCIC_INTR_MODE_ISA) 1994 cfg |= PCIC_DEVCTL_INTR_ISA; 1995 ddi_put8(pcic->cfg_handle, 1996 pcic->cfgaddr + PCIC_DEVCTL_REG, 1997 cfg); 1998 1999 /* tie INTA and INTB together */ 2000 cfg = ddi_get8(pcic->cfg_handle, 2001 (pcic->cfgaddr + PCIC_SYSCTL_REG + 3)); 2002 cfg |= PCIC_SYSCTL_INTRTIE; 2003 ddi_put8(pcic->cfg_handle, (pcic->cfgaddr + 2004 PCIC_SYSCTL_REG + 3), cfg); 2005 cfg = ddi_get8(pcic->cfg_handle, 2006 pcic->cfgaddr + PCIC_DIAG_REG); 2007 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC); 2008 ddi_put8(pcic->cfg_handle, 2009 pcic->cfgaddr + PCIC_DIAG_REG, cfg); 2010 break; 2011 case PCIC_TI_PCI1410: 2012 cfg = ddi_get8(pcic->cfg_handle, 2013 pcic->cfgaddr + PCIC_DIAG_REG); 2014 cfg |= (PCIC_DIAG_CSC | PCIC_DIAG_ASYNC); 2015 ddi_put8(pcic->cfg_handle, 2016 pcic->cfgaddr + PCIC_DIAG_REG, cfg); 2017 break; 2018 case PCIC_TOSHIBA_TOPIC100: 2019 case PCIC_TOSHIBA_TOPIC95: 2020 case PCIC_TOSHIBA_VENDOR: 2021 cfg = ddi_get8(pcic->cfg_handle, pcic->cfgaddr + 2022 PCIC_TOSHIBA_SLOT_CTL_REG); 2023 cfg |= (PCIC_TOSHIBA_SCR_SLOTON | 2024 PCIC_TOSHIBA_SCR_SLOTEN); 2025 cfg &= (~PCIC_TOSHIBA_SCR_PRT_MASK); 2026 cfg |= PCIC_TOSHIBA_SCR_PRT_3E2; 2027 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + 2028 PCIC_TOSHIBA_SLOT_CTL_REG, cfg); 2029 cfg = ddi_get8(pcic->cfg_handle, pcic->cfgaddr + 2030 PCIC_TOSHIBA_INTR_CTL_REG); 2031 switch (pcic->pc_intr_mode) { 2032 case PCIC_INTR_MODE_ISA: 2033 cfg &= ~PCIC_TOSHIBA_ICR_SRC; 2034 ddi_put8(pcic->cfg_handle, 2035 pcic->cfgaddr + 2036 PCIC_TOSHIBA_INTR_CTL_REG, cfg); 2037 2038 cfg = ddi_get8(pcic->cfg_handle, 2039 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 2040 cfg |= PCIC_FUN_INT_MOD_ISA; 2041 ddi_put8(pcic->cfg_handle, 2042 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 2043 cfg); 2044 break; 2045 case PCIC_INTR_MODE_PCI_1: 2046 cfg |= PCIC_TOSHIBA_ICR_SRC; 2047 cfg &= (~PCIC_TOSHIBA_ICR_PIN_MASK); 2048 cfg |= PCIC_TOSHIBA_ICR_PIN_INTA; 2049 ddi_put8(pcic->cfg_handle, 2050 pcic->cfgaddr + 2051 PCIC_TOSHIBA_INTR_CTL_REG, cfg); 2052 break; 2053 } 2054 break; 2055 case PCIC_O2MICRO_VENDOR: 2056 cfg32 = ddi_get32(pcic->cfg_handle, 2057 (uint32_t *)(pcic->cfgaddr + 2058 PCIC_O2MICRO_MISC_CTL)); 2059 switch (pcic->pc_intr_mode) { 2060 case PCIC_INTR_MODE_ISA: 2061 cfg32 |= (PCIC_O2MICRO_ISA_LEGACY | 2062 PCIC_O2MICRO_INT_MOD_PCI); 2063 ddi_put32(pcic->cfg_handle, 2064 (uint32_t *)(pcic->cfgaddr + 2065 PCIC_O2MICRO_MISC_CTL), 2066 cfg32); 2067 cfg = ddi_get8(pcic->cfg_handle, 2068 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 2069 cfg |= PCIC_FUN_INT_MOD_ISA; 2070 ddi_put8(pcic->cfg_handle, 2071 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 2072 cfg); 2073 break; 2074 case PCIC_INTR_MODE_PCI_1: 2075 cfg32 &= ~PCIC_O2MICRO_ISA_LEGACY; 2076 cfg32 |= PCIC_O2MICRO_INT_MOD_PCI; 2077 ddi_put32(pcic->cfg_handle, 2078 (uint32_t *)(pcic->cfgaddr + 2079 PCIC_O2MICRO_MISC_CTL), 2080 cfg32); 2081 break; 2082 } 2083 break; 2084 case PCIC_RICOH_VENDOR: 2085 if (pcic->pc_intr_mode == PCIC_INTR_MODE_ISA) { 2086 cfg16 = ddi_get16(pcic->cfg_handle, 2087 (uint16_t *)(pcic->cfgaddr + 2088 PCIC_RICOH_MISC_CTL_2)); 2089 cfg16 |= (PCIC_RICOH_CSC_INT_MOD | 2090 PCIC_RICOH_FUN_INT_MOD); 2091 ddi_put16(pcic->cfg_handle, 2092 (uint16_t *)(pcic->cfgaddr + 2093 PCIC_RICOH_MISC_CTL_2), 2094 cfg16); 2095 2096 cfg16 = ddi_get16(pcic->cfg_handle, 2097 (uint16_t *)(pcic->cfgaddr + 2098 PCIC_RICOH_MISC_CTL)); 2099 cfg16 |= PCIC_RICOH_SIRQ_EN; 2100 ddi_put16(pcic->cfg_handle, 2101 (uint16_t *)(pcic->cfgaddr + 2102 PCIC_RICOH_MISC_CTL), 2103 cfg16); 2104 2105 cfg = ddi_get8(pcic->cfg_handle, 2106 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG); 2107 cfg |= PCIC_FUN_INT_MOD_ISA; 2108 ddi_put8(pcic->cfg_handle, 2109 pcic->cfgaddr + PCIC_BRIDGE_CTL_REG, 2110 cfg); 2111 } 2112 break; 2113 default: 2114 break; 2115 } /* switch */ 2116 2117 /* setup general card status change interrupt */ 2118 switch (pcic->pc_type) { 2119 case PCIC_TI_PCI1225: 2120 case PCIC_TI_PCI1221: 2121 case PCIC_TI_PCI1031: 2122 case PCIC_TI_PCI1520: 2123 case PCIC_TI_PCI1410: 2124 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 2125 PCIC_CHANGE_DEFAULT); 2126 break; 2127 default: 2128 if (pcic->pc_intr_mode == 2129 PCIC_INTR_MODE_PCI_1) { 2130 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 2131 PCIC_CHANGE_DEFAULT); 2132 break; 2133 } else { 2134 pcic_putb(pcic, i, PCIC_MANAGEMENT_INT, 2135 PCIC_CHANGE_DEFAULT | 2136 (pcic->pc_sockets[i].pcs_smi << 4)); 2137 break; 2138 } 2139 } 2140 2141 pcic->pc_flags |= PCF_INTRENAB; 2142 2143 /* take card out of RESET */ 2144 pcic_putb(pcic, i, PCIC_INTERRUPT, PCIC_RESET); 2145 /* turn power off and let CS do this */ 2146 pcic_putb(pcic, i, PCIC_POWER_CONTROL, 0); 2147 2148 /* final chip specific initialization */ 2149 switch (pcic->pc_type) { 2150 case PCIC_VADEM: 2151 pcic_putb(pcic, i, PCIC_VG_CONTROL, 2152 PCIC_VC_DELAYENABLE); 2153 pcic->pc_flags |= PCF_DEBOUNCE; 2154 /* FALLTHROUGH */ 2155 case PCIC_I82365SL: 2156 pcic_putb(pcic, i, PCIC_GLOBAL_CONTROL, 2157 PCIC_GC_CSC_WRITE); 2158 /* clear any pending interrupts */ 2159 value = pcic_getb(pcic, i, PCIC_CARD_STATUS_CHANGE); 2160 pcic_putb(pcic, i, PCIC_CARD_STATUS_CHANGE, value); 2161 break; 2162 /* The 82092 uses PCI config space to enable interrupts */ 2163 case PCIC_INTEL_i82092: 2164 pcic_82092_smiirq_ctl(pcic, i, PCIC_82092_CTL_SMI, 2165 PCIC_82092_INT_ENABLE); 2166 break; 2167 case PCIC_CL_PD6729: 2168 if (pcic->bus_speed >= PCIC_PCI_DEF_SYSCLK && i == 0) { 2169 value = pcic_getb(pcic, i, PCIC_MISC_CTL_2); 2170 pcic_putb(pcic, i, PCIC_MISC_CTL_2, 2171 value | PCIC_CL_TIMER_CLK_DIV); 2172 } 2173 break; 2174 } /* switch */ 2175 2176 #if defined(PCIC_DEBUG) 2177 if (pcic_debug) 2178 cmn_err(CE_CONT, 2179 "socket %d value=%x, flags = %x (%s)\n", 2180 i, value, pcic->pc_sockets[i].pcs_flags, 2181 (pcic->pc_sockets[i].pcs_flags & 2182 PCS_CARD_PRESENT) ? 2183 "card present" : "no card"); 2184 #endif 2185 } 2186 } 2187 2188 /* 2189 * pcic_intr(caddr_t, caddr_t) 2190 * interrupt handler for the PCIC style adapter 2191 * handles all basic interrupts and also checks 2192 * for status changes and notifies the nexus if 2193 * necessary 2194 * 2195 * On PCI bus adapters, also handles all card 2196 * IO interrupts. 2197 */ 2198 /*ARGSUSED*/ 2199 uint32_t 2200 pcic_intr(caddr_t arg1, caddr_t arg2) 2201 { 2202 pcicdev_t *pcic = (pcicdev_t *)arg1; 2203 int value = 0, i, ret = DDI_INTR_UNCLAIMED; 2204 uint8_t status; 2205 uint_t io_ints; 2206 2207 #if defined(PCIC_DEBUG) 2208 pcic_err(pcic->dip, 0xf, 2209 "pcic_intr: enter pc_flags=0x%x PCF_ATTACHED=0x%x" 2210 " pc_numsockets=%d \n", 2211 pcic->pc_flags, PCF_ATTACHED, pcic->pc_numsockets); 2212 #endif 2213 2214 if (!(pcic->pc_flags & PCF_ATTACHED)) 2215 return (DDI_INTR_UNCLAIMED); 2216 2217 mutex_enter(&pcic->intr_lock); 2218 2219 if (pcic->pc_flags & PCF_SUSPENDED) { 2220 mutex_exit(&pcic->intr_lock); 2221 return (ret); 2222 } 2223 2224 /* 2225 * need to change to only ACK and touch the slot that 2226 * actually caused the interrupt. Currently everything 2227 * is acked 2228 * 2229 * we need to look at all known sockets to determine 2230 * what might have happened, so step through the list 2231 * of them 2232 */ 2233 #ifdef VOYAGER 2234 ret = syshw_intr_hi(pcic); 2235 #endif 2236 2237 /* 2238 * Set the bitmask for IO interrupts to initially include all sockets 2239 */ 2240 io_ints = (1 << pcic->pc_numsockets) - 1; 2241 2242 for (i = 0; i < pcic->pc_numsockets; i++) { 2243 int card_type; 2244 pcic_socket_t *sockp; 2245 int value_cb = 0; 2246 2247 sockp = &pcic->pc_sockets[i]; 2248 /* get the socket's I/O addresses */ 2249 2250 if (sockp->pcs_flags & PCS_WAITING) { 2251 io_ints &= ~(1 << i); 2252 continue; 2253 } 2254 2255 if (sockp->pcs_flags & PCS_CARD_IO) 2256 card_type = IF_IO; 2257 else 2258 card_type = IF_MEMORY; 2259 2260 if (pcic->pc_io_type == PCIC_IO_TYPE_YENTA) 2261 value_cb = pcic_getcb(pcic, CB_STATUS_EVENT); 2262 2263 value = pcic_change(pcic, i); 2264 2265 if ((value != 0) || (value_cb != 0)) { 2266 int x = pcic->pc_cb_arg; 2267 2268 ret = DDI_INTR_CLAIMED; 2269 2270 #if defined(PCIC_DEBUG) 2271 pcic_err(pcic->dip, 0x9, 2272 "card_type = %d, value_cb = 0x%x\n", 2273 card_type, 2274 value_cb ? value_cb : 2275 pcic_getcb(pcic, CB_STATUS_EVENT)); 2276 if (pcic_debug) 2277 cmn_err(CE_CONT, 2278 "\tchange on socket %d (%x)\n", i, 2279 value); 2280 #endif 2281 /* find out what happened */ 2282 status = pcic_getb(pcic, i, PCIC_INTERFACE_STATUS); 2283 2284 /* acknowledge the interrupt */ 2285 if (value_cb) 2286 pcic_putcb(pcic, CB_STATUS_EVENT, value_cb); 2287 2288 if (value) 2289 pcic_putb(pcic, i, PCIC_CARD_STATUS_CHANGE, 2290 value); 2291 2292 if (pcic->pc_callback == NULL) { 2293 /* if not callback handler, nothing to do */ 2294 continue; 2295 } 2296 2297 /* Card Detect */ 2298 if (value & PCIC_CD_DETECT || 2299 value_cb & CB_PS_CCDMASK) { 2300 uint8_t irq; 2301 #if defined(PCIC_DEBUG) 2302 if (pcic_debug) 2303 cmn_err(CE_CONT, 2304 "\tcd_detect: status=%x," 2305 " flags=%x\n", 2306 status, sockp->pcs_flags); 2307 #else 2308 #ifdef lint 2309 if (status == 0) 2310 status++; 2311 #endif 2312 #endif 2313 /* 2314 * Turn off all interrupts for this socket here. 2315 */ 2316 irq = pcic_getb(pcic, sockp->pcs_socket, 2317 PCIC_MANAGEMENT_INT); 2318 irq &= ~PCIC_CHANGE_MASK; 2319 pcic_putb(pcic, sockp->pcs_socket, 2320 PCIC_MANAGEMENT_INT, irq); 2321 2322 pcic_putcb(pcic, CB_STATUS_MASK, 0x0); 2323 2324 if (!sockp->pcs_cd_softint_flg) { 2325 sockp->pcs_cd_softint_flg = 1; 2326 (void) ddi_intr_trigger_softint( 2327 sockp->pcs_cd_softint_hdl, NULL); 2328 } 2329 2330 io_ints &= ~(1 << i); 2331 } /* PCIC_CD_DETECT */ 2332 2333 /* Ready/Change Detect */ 2334 sockp->pcs_state ^= SBM_RDYBSY; 2335 if (card_type == IF_MEMORY && value & PCIC_RD_DETECT) { 2336 sockp->pcs_flags |= PCS_READY; 2337 PC_CALLBACK(pcic->dip, x, PCE_CARD_READY, i); 2338 } 2339 2340 /* Battery Warn Detect */ 2341 if (card_type == IF_MEMORY && 2342 value & PCIC_BW_DETECT && 2343 !(sockp->pcs_state & SBM_BVD2)) { 2344 sockp->pcs_state |= SBM_BVD2; 2345 PC_CALLBACK(pcic->dip, x, 2346 PCE_CARD_BATTERY_WARN, i); 2347 } 2348 2349 /* Battery Dead Detect */ 2350 if (value & PCIC_BD_DETECT) { 2351 /* 2352 * need to work out event if RI not enabled 2353 * and card_type == IF_IO 2354 */ 2355 if (card_type == IF_MEMORY && 2356 !(sockp->pcs_state & SBM_BVD1)) { 2357 sockp->pcs_state |= SBM_BVD1; 2358 PC_CALLBACK(pcic->dip, x, 2359 PCE_CARD_BATTERY_DEAD, 2360 i); 2361 } else { 2362 /* 2363 * information in pin replacement 2364 * register if one is available 2365 */ 2366 PC_CALLBACK(pcic->dip, x, 2367 PCE_CARD_STATUS_CHANGE, 2368 i); 2369 } /* IF_MEMORY */ 2370 } /* PCIC_BD_DETECT */ 2371 } /* if pcic_change */ 2372 /* 2373 * for any controllers that we can detect whether a socket 2374 * had an interrupt for the PC Card, we should sort that out 2375 * here. 2376 */ 2377 } /* for pc_numsockets */ 2378 2379 /* 2380 * If we're on a PCI bus, we may need to cycle through each IO 2381 * interrupt handler that is registered since they all 2382 * share the same interrupt line. 2383 */ 2384 2385 2386 #if defined(PCIC_DEBUG) 2387 pcic_err(pcic->dip, 0xf, 2388 "pcic_intr: pc_intr_mode=%d pc_type=%x io_ints=0x%x\n", 2389 pcic->pc_intr_mode, pcic->pc_type, io_ints); 2390 #endif 2391 2392 switch (pcic->pc_intr_mode) { 2393 case PCIC_INTR_MODE_PCI_1: 2394 value = ~0; 2395 /* fix value if adapter can tell us about I/O intrs */ 2396 switch (pcic->pc_type) { 2397 2398 case PCIC_TI_PCI1031: 2399 case PCIC_TI_PCI1130: 2400 case PCIC_TI_PCI1131: 2401 case PCIC_TI_PCI1250: 2402 case PCIC_TI_PCI1225: 2403 case PCIC_TI_PCI1221: 2404 case PCIC_TI_PCI1520: 2405 case PCIC_TI_PCI1410: 2406 case PCIC_TI_VENDOR: 2407 i = ddi_get8(pcic->cfg_handle, 2408 pcic->cfgaddr + PCIC_CRDCTL_REG); 2409 if (i & PCIC_CRDCTL_IFG) 2410 value = 1; 2411 else 2412 value = 0; 2413 i |= PCIC_CRDCTL_IFG; 2414 /* clear the condition */ 2415 ddi_put8(pcic->cfg_handle, 2416 pcic->cfgaddr + PCIC_CRDCTL_REG, i); 2417 break; 2418 case PCIC_TOSHIBA_TOPIC100: 2419 case PCIC_TOSHIBA_TOPIC95: 2420 case PCIC_TOSHIBA_VENDOR: 2421 case PCIC_RICOH_VENDOR: 2422 case PCIC_O2MICRO_VENDOR: 2423 default: 2424 value = 1; 2425 break; 2426 } 2427 if (value && pcic_do_io_intr(pcic, value) == DDI_INTR_CLAIMED) 2428 ret = DDI_INTR_CLAIMED; 2429 break; 2430 default: 2431 break; 2432 } 2433 2434 mutex_exit(&pcic->intr_lock); 2435 2436 #if defined(PCIC_DEBUG) 2437 pcic_err(pcic->dip, 0xf, 2438 "pcic_intr: ret=%d value=%d DDI_INTR_CLAIMED=%d\n", 2439 ret, value, DDI_INTR_CLAIMED); 2440 #endif 2441 2442 return (ret); 2443 } 2444 2445 /* 2446 * pcic_change() 2447 * check to see if this socket had a change in state 2448 * by checking the status change register 2449 */ 2450 static int 2451 pcic_change(pcicdev_t *pcic, int socket) 2452 { 2453 return (pcic_getb(pcic, socket, PCIC_CARD_STATUS_CHANGE)); 2454 } 2455 2456 /* 2457 * pcic_do_io_intr - calls client interrupt handlers 2458 */ 2459 static int 2460 pcic_do_io_intr(pcicdev_t *pcic, uint32_t sockets) 2461 { 2462 inthandler_t *tmp; 2463 int ret = DDI_INTR_UNCLAIMED; 2464 2465 #if defined(PCIC_DEBUG) 2466 pcic_err(pcic->dip, 0xf, 2467 "pcic_do_io_intr: pcic=%p sockets=%d irq_top=%p\n", 2468 (void *)pcic, (int)sockets, (void *)pcic->irq_top); 2469 #endif 2470 2471 if (pcic->irq_top != NULL) { 2472 tmp = pcic->irq_current; 2473 2474 do { 2475 int cur = pcic->irq_current->socket; 2476 pcic_socket_t *sockp = 2477 &pcic->pc_sockets[cur]; 2478 2479 #if defined(PCIC_DEBUG) 2480 pcic_err(pcic->dip, 0xf, 2481 "\t pcs_flags=0x%x PCS_CARD_PRESENT=0x%x\n", 2482 sockp->pcs_flags, PCS_CARD_PRESENT); 2483 pcic_err(pcic->dip, 0xf, 2484 "\t sockets=%d cur=%d intr=%p arg1=%p " 2485 "arg2=%p\n", 2486 sockets, cur, (void *)pcic->irq_current->intr, 2487 pcic->irq_current->arg1, 2488 pcic->irq_current->arg2); 2489 #endif 2490 if (sockp->pcs_flags & PCS_CARD_PRESENT && 2491 sockets & (1 << cur)) { 2492 2493 if ((*pcic->irq_current->intr)(pcic->irq_current->arg1, 2494 pcic->irq_current->arg2) == DDI_INTR_CLAIMED) 2495 ret = DDI_INTR_CLAIMED; 2496 2497 #if defined(PCIC_DEBUG) 2498 pcic_err(pcic->dip, 0xf, 2499 "\t ret=%d DDI_INTR_CLAIMED=%d\n", 2500 ret, DDI_INTR_CLAIMED); 2501 #endif 2502 } 2503 2504 2505 if ((pcic->irq_current = pcic->irq_current->next) == NULL) 2506 pcic->irq_current = pcic->irq_top; 2507 2508 } while (pcic->irq_current != tmp); 2509 2510 if ((pcic->irq_current = pcic->irq_current->next) == NULL) 2511 pcic->irq_current = pcic->irq_top; 2512 2513 } else { 2514 ret = DDI_INTR_UNCLAIMED; 2515 } 2516 2517 #if defined(PCIC_DEBUG) 2518 pcic_err(pcic->dip, 0xf, 2519 "pcic_do_io_intr: exit ret=%d DDI_INTR_CLAIMED=%d\n", 2520 ret, DDI_INTR_CLAIMED); 2521 #endif 2522 2523 return (ret); 2524 2525 } 2526 2527 /* 2528 * pcic_inquire_adapter() 2529 * SocketServices InquireAdapter function 2530 * get characteristics of the physical adapter 2531 */ 2532 /*ARGSUSED*/ 2533 static int 2534 pcic_inquire_adapter(dev_info_t *dip, inquire_adapter_t *config) 2535 { 2536 anp_t *anp = ddi_get_driver_private(dip); 2537 pcicdev_t *pcic = anp->an_private; 2538 2539 config->NumSockets = pcic->pc_numsockets; 2540 config->NumWindows = pcic->pc_numsockets * PCIC_NUMWINSOCK; 2541 config->NumEDCs = 0; 2542 config->AdpCaps = 0; 2543 config->ActiveHigh = 0; 2544 config->ActiveLow = PCIC_AVAIL_IRQS; 2545 config->NumPower = pcic->pc_numpower; 2546 config->power_entry = pcic->pc_power; /* until we resolve this */ 2547 #if defined(PCIC_DEBUG) 2548 if (pcic_debug) { 2549 cmn_err(CE_CONT, "pcic_inquire_adapter:\n"); 2550 cmn_err(CE_CONT, "\tNumSockets=%d\n", config->NumSockets); 2551 cmn_err(CE_CONT, "\tNumWindows=%d\n", config->NumWindows); 2552 } 2553 #endif 2554 config->ResourceFlags = 0; 2555 switch (pcic->pc_intr_mode) { 2556 case PCIC_INTR_MODE_PCI_1: 2557 config->ResourceFlags |= RES_OWN_IRQ | RES_IRQ_NEXUS | 2558 RES_IRQ_SHAREABLE; 2559 break; 2560 } 2561 return (SUCCESS); 2562 } 2563 2564 /* 2565 * pcic_callback() 2566 * The PCMCIA nexus calls us via this function 2567 * in order to set the callback function we are 2568 * to call the nexus with 2569 */ 2570 /*ARGSUSED*/ 2571 static int 2572 pcic_callback(dev_info_t *dip, int (*handler)(), int arg) 2573 { 2574 anp_t *anp = ddi_get_driver_private(dip); 2575 pcicdev_t *pcic = anp->an_private; 2576 2577 if (handler != NULL) { 2578 pcic->pc_callback = handler; 2579 pcic->pc_cb_arg = arg; 2580 pcic->pc_flags |= PCF_CALLBACK; 2581 } else { 2582 pcic->pc_callback = NULL; 2583 pcic->pc_cb_arg = 0; 2584 pcic->pc_flags &= ~PCF_CALLBACK; 2585 } 2586 /* 2587 * we're now registered with the nexus 2588 * it is acceptable to do callbacks at this point. 2589 * don't call back from here though since it could block 2590 */ 2591 return (PC_SUCCESS); 2592 } 2593 2594 /* 2595 * pcic_calc_speed (pcicdev_t *pcic, uint32_t speed) 2596 * calculate the speed bits from the specified memory speed 2597 * there may be more to do here 2598 */ 2599 2600 static int 2601 pcic_calc_speed(pcicdev_t *pcic, uint32_t speed) 2602 { 2603 uint32_t wspeed = 1; /* assume 1 wait state when unknown */ 2604 uint32_t bspeed = PCIC_ISA_DEF_SYSCLK; 2605 2606 switch (pcic->pc_type) { 2607 case PCIC_I82365SL: 2608 case PCIC_VADEM: 2609 case PCIC_VADEM_VG469: 2610 default: 2611 /* Intel chip wants it in waitstates */ 2612 wspeed = mhztons(PCIC_ISA_DEF_SYSCLK) * 3; 2613 if (speed <= wspeed) 2614 wspeed = 0; 2615 else if (speed <= (wspeed += mhztons(bspeed))) 2616 wspeed = 1; 2617 else if (speed <= (wspeed += mhztons(bspeed))) 2618 wspeed = 2; 2619 else 2620 wspeed = 3; 2621 wspeed <<= 6; /* put in right bit positions */ 2622 break; 2623 2624 case PCIC_INTEL_i82092: 2625 wspeed = SYSMEM_82092_80NS; 2626 if (speed > 80) 2627 wspeed = SYSMEM_82092_100NS; 2628 if (speed > 100) 2629 wspeed = SYSMEM_82092_150NS; 2630 if (speed > 150) 2631 wspeed = SYSMEM_82092_200NS; 2632 if (speed > 200) 2633 wspeed = SYSMEM_82092_250NS; 2634 if (speed > 250) 2635 wspeed = SYSMEM_82092_600NS; 2636 wspeed <<= 5; /* put in right bit positions */ 2637 break; 2638 2639 } /* switch */ 2640 2641 return (wspeed); 2642 } 2643 2644 /* 2645 * These values are taken from the PC Card Standard Electrical Specification. 2646 * Generally the larger value is taken if 2 are possible. 2647 */ 2648 static struct pcic_card_times { 2649 uint16_t cycle; /* Speed as found in the atribute space of he card. */ 2650 uint16_t setup; /* Corresponding address setup time. */ 2651 uint16_t width; /* Corresponding width, OE or WE. */ 2652 uint16_t hold; /* Corresponding data or address hold time. */ 2653 } pcic_card_times[] = { 2654 2655 /* 2656 * Note: The rounded up times for 250, 200 & 150 have been increased 2657 * due to problems with the 3-Com ethernet cards (pcelx) on UBIIi. 2658 * See BugID 00663. 2659 */ 2660 2661 /* 2662 * Rounded up times Original times from 2663 * that add up to the the PCMCIA Spec. 2664 * cycle time. 2665 */ 2666 {600, 180, 370, 140}, /* 100, 300, 70 */ 2667 {400, 120, 300, 90}, /* Made this one up */ 2668 {250, 100, 190, 70}, /* 30, 150, 30 */ 2669 {200, 80, 170, 70}, /* 20, 120, 30 */ 2670 {150, 50, 110, 40}, /* 20, 80, 20 */ 2671 {100, 40, 80, 40}, /* 10, 60, 15 */ 2672 {0, 10, 60, 15} /* 10, 60, 15 */ 2673 }; 2674 2675 /* 2676 * pcic_set_cdtimers 2677 * This is specific to several Cirrus Logic chips 2678 */ 2679 static void 2680 pcic_set_cdtimers(pcicdev_t *pcic, int socket, uint32_t speed, int tset) 2681 { 2682 int cmd, set, rec, offset, clk_pulse; 2683 struct pcic_card_times *ctp; 2684 2685 if ((tset == IOMEM_CLTIMER_SET_1) || (tset == SYSMEM_CLTIMER_SET_1)) 2686 offset = 3; 2687 else 2688 offset = 0; 2689 2690 clk_pulse = mhztons(pcic->bus_speed); 2691 for (ctp = pcic_card_times; speed < ctp->cycle; ctp++); 2692 2693 /* 2694 * Add (clk_pulse/2) and an extra 1 to account for rounding errors. 2695 */ 2696 set = ((ctp->setup + 10 + 1 + (clk_pulse/2))/clk_pulse) - 1; 2697 if (set < 0) 2698 set = 0; 2699 2700 cmd = ((ctp->width + 10 + 1 + (clk_pulse/2))/clk_pulse) - 1; 2701 if (cmd < 0) 2702 cmd = 0; 2703 2704 rec = ((ctp->hold + 10 + 1 + (clk_pulse/2))/clk_pulse) - 2; 2705 if (rec < 0) 2706 rec = 0; 2707 2708 #if defined(PCIC_DEBUG) 2709 pcic_err(pcic->dip, 8, "pcic_set_cdtimers(%d, Timer Set %d)\n" 2710 "ct=%d, cp=%d, cmd=0x%x, setup=0x%x, rec=0x%x\n", 2711 (unsigned)speed, offset == 3 ? 1 : 0, 2712 ctp->cycle, clk_pulse, cmd, set, rec); 2713 #endif 2714 2715 pcic_putb(pcic, socket, PCIC_TIME_COMMAND_0 + offset, cmd); 2716 pcic_putb(pcic, socket, PCIC_TIME_SETUP_0 + offset, set); 2717 pcic_putb(pcic, socket, PCIC_TIME_RECOVER_0 + offset, rec); 2718 } 2719 2720 /* 2721 * pcic_set_window 2722 * essentially the same as the Socket Services specification 2723 * We use socket and not adapter since they are identifiable 2724 * but the rest is the same 2725 * 2726 * dip pcic driver's device information 2727 * window parameters for the request 2728 */ 2729 static int 2730 pcic_set_window(dev_info_t *dip, set_window_t *window) 2731 { 2732 anp_t *anp = ddi_get_driver_private(dip); 2733 pcicdev_t *pcic = anp->an_private; 2734 int select; 2735 int socket, pages, which, ret; 2736 pcic_socket_t *sockp = &pcic->pc_sockets[window->socket]; 2737 ra_return_t res; 2738 ndi_ra_request_t req; 2739 uint32_t base = window->base; 2740 2741 #if defined(PCIC_DEBUG) 2742 if (pcic_debug) { 2743 cmn_err(CE_CONT, "pcic_set_window: entered\n"); 2744 cmn_err(CE_CONT, 2745 "\twindow=%d, socket=%d, WindowSize=%d, speed=%d\n", 2746 window->window, window->socket, window->WindowSize, 2747 window->speed); 2748 cmn_err(CE_CONT, 2749 "\tbase=%x, state=%x\n", (unsigned)window->base, 2750 (unsigned)window->state); 2751 } 2752 #endif 2753 2754 /* 2755 * do some basic sanity checking on what we support 2756 * we don't do paged mode 2757 */ 2758 if (window->state & WS_PAGED) { 2759 cmn_err(CE_WARN, "pcic_set_window: BAD_ATTRIBUTE\n"); 2760 return (BAD_ATTRIBUTE); 2761 } 2762 2763 /* 2764 * we don't care about previous mappings. 2765 * Card Services will deal with that so don't 2766 * even check 2767 */ 2768 2769 socket = window->socket; 2770 2771 if (!(window->state & WS_IO)) { 2772 int win, tmp; 2773 pcs_memwin_t *memp; 2774 #if defined(PCIC_DEBUG) 2775 if (pcic_debug) 2776 cmn_err(CE_CONT, "\twindow type is memory\n"); 2777 #endif 2778 /* this is memory window mapping */ 2779 win = window->window % PCIC_NUMWINSOCK; 2780 tmp = window->window / PCIC_NUMWINSOCK; 2781 2782 /* only windows 2-6 can do memory mapping */ 2783 if (tmp != window->socket || win < PCIC_IOWINDOWS) { 2784 cmn_err(CE_CONT, 2785 "\tattempt to map to non-mem window\n"); 2786 return (BAD_WINDOW); 2787 } 2788 2789 if (window->WindowSize == 0) 2790 window->WindowSize = MEM_MIN; 2791 else if ((window->WindowSize & (PCIC_PAGE-1)) != 0) { 2792 cmn_err(CE_WARN, "pcic_set_window: BAD_SIZE\n"); 2793 return (BAD_SIZE); 2794 } 2795 2796 mutex_enter(&pcic->pc_lock); /* protect the registers */ 2797 2798 memp = &sockp->pcs_windows[win].mem; 2799 memp->pcw_speed = window->speed; 2800 2801 win -= PCIC_IOWINDOWS; /* put in right range */ 2802 2803 if (window->WindowSize != memp->pcw_len) 2804 which = memp->pcw_len; 2805 else 2806 which = 0; 2807 2808 if (window->state & WS_ENABLED) { 2809 uint32_t wspeed; 2810 #if defined(PCIC_DEBUG) 2811 if (pcic_debug) { 2812 cmn_err(CE_CONT, 2813 "\tbase=%x, win=%d\n", (unsigned)base, 2814 win); 2815 if (which) 2816 cmn_err(CE_CONT, 2817 "\tneed to remap window\n"); 2818 } 2819 #endif 2820 2821 if (which && (memp->pcw_status & PCW_MAPPED)) { 2822 ddi_regs_map_free(&memp->pcw_handle); 2823 res.ra_addr_lo = memp->pcw_base; 2824 res.ra_len = memp->pcw_len; 2825 (void) pcmcia_free_mem(dip, &res); 2826 memp->pcw_status &= ~(PCW_MAPPED|PCW_ENABLED); 2827 memp->pcw_hostmem = NULL; 2828 memp->pcw_base = NULL; 2829 memp->pcw_len = 0; 2830 } 2831 2832 which = window->WindowSize >> PAGE_SHIFT; 2833 2834 if (!(memp->pcw_status & PCW_MAPPED)) { 2835 ret = 0; 2836 2837 memp->pcw_base = base; 2838 bzero(&req, sizeof (req)); 2839 req.ra_len = which << PAGE_SHIFT; 2840 req.ra_addr = (uint64_t)memp->pcw_base; 2841 req.ra_boundbase = pcic->pc_base; 2842 req.ra_boundlen = pcic->pc_bound; 2843 req.ra_flags = (memp->pcw_base ? 2844 NDI_RA_ALLOC_SPECIFIED : 0) | 2845 NDI_RA_ALLOC_BOUNDED; 2846 req.ra_align_mask = 2847 (PAGESIZE - 1) | (PCIC_PAGE - 1); 2848 #if defined(PCIC_DEBUG) 2849 pcic_err(dip, 8, 2850 "\tlen 0x%"PRIx64 2851 "addr 0x%"PRIx64"bbase 0x%"PRIx64 2852 " blen 0x%"PRIx64" flags 0x%x" 2853 " algn 0x%"PRIx64"\n", 2854 req.ra_len, req.ra_addr, 2855 req.ra_boundbase, 2856 req.ra_boundlen, req.ra_flags, 2857 req.ra_align_mask); 2858 #endif 2859 2860 ret = pcmcia_alloc_mem(dip, &req, &res); 2861 if (ret == DDI_FAILURE) { 2862 mutex_exit(&pcic->pc_lock); 2863 cmn_err(CE_WARN, 2864 "\tpcmcia_alloc_mem() failed\n"); 2865 return (BAD_SIZE); 2866 } 2867 memp->pcw_base = res.ra_addr_lo; 2868 base = memp->pcw_base; 2869 2870 #if defined(PCIC_DEBUG) 2871 if (pcic_debug) 2872 cmn_err(CE_CONT, 2873 "\tsetwindow: new base=%x\n", 2874 (unsigned)memp->pcw_base); 2875 #endif 2876 memp->pcw_len = window->WindowSize; 2877 2878 which = pcmcia_map_reg(pcic->dip, 2879 window->child, 2880 &res, 2881 (uint32_t)(window->state & 2882 0xffff) | 2883 (window->socket << 16), 2884 (caddr_t *)&memp->pcw_hostmem, 2885 &memp->pcw_handle, 2886 &window->attr, NULL); 2887 2888 if (which != DDI_SUCCESS) { 2889 2890 cmn_err(CE_WARN, "\tpcmcia_map_reg() " 2891 "failed\n"); 2892 2893 res.ra_addr_lo = memp->pcw_base; 2894 res.ra_len = memp->pcw_len; 2895 (void) pcmcia_free_mem(pcic->dip, &res); 2896 2897 mutex_exit(&pcic->pc_lock); 2898 2899 return (BAD_WINDOW); 2900 } 2901 memp->pcw_status |= PCW_MAPPED; 2902 #if defined(PCIC_DEBUG) 2903 if (pcic_debug) 2904 cmn_err(CE_CONT, 2905 "\tmap=%x, hostmem=%p\n", 2906 which, 2907 (void *)memp->pcw_hostmem); 2908 #endif 2909 } else { 2910 base = memp->pcw_base; 2911 } 2912 2913 /* report the handle back to caller */ 2914 window->handle = memp->pcw_handle; 2915 2916 #if defined(PCIC_DEBUG) 2917 if (pcic_debug) { 2918 cmn_err(CE_CONT, 2919 "\twindow mapped to %x@%x len=%d\n", 2920 (unsigned)window->base, 2921 (unsigned)memp->pcw_base, 2922 memp->pcw_len); 2923 } 2924 #endif 2925 2926 /* find the register set offset */ 2927 select = win * PCIC_MEM_1_OFFSET; 2928 #if defined(PCIC_DEBUG) 2929 if (pcic_debug) 2930 cmn_err(CE_CONT, "\tselect=%x\n", select); 2931 #endif 2932 2933 /* 2934 * at this point, the register window indicator has 2935 * been converted to be an offset from the first 2936 * set of registers that are used for programming 2937 * the window mapping and the offset used to select 2938 * the correct set of registers to access the 2939 * specified socket. This allows basing everything 2940 * off the _0 window 2941 */ 2942 2943 /* map the physical page base address */ 2944 which = (window->state & WS_16BIT) ? SYSMEM_DATA_16 : 0; 2945 which |= (window->speed <= MEM_SPEED_MIN) ? 2946 SYSMEM_ZERO_WAIT : 0; 2947 2948 /* need to select register set */ 2949 select = PCIC_MEM_1_OFFSET * win; 2950 2951 pcic_putb(pcic, socket, 2952 PCIC_SYSMEM_0_STARTLOW + select, 2953 SYSMEM_LOW(base)); 2954 pcic_putb(pcic, socket, 2955 PCIC_SYSMEM_0_STARTHI + select, 2956 SYSMEM_HIGH(base) | which); 2957 2958 /* 2959 * Some adapters can decode window addresses greater 2960 * than 16-bits worth, so handle them here. 2961 */ 2962 switch (pcic->pc_type) { 2963 case PCIC_INTEL_i82092: 2964 pcic_putb(pcic, socket, 2965 PCIC_82092_CPAGE, 2966 SYSMEM_EXT(base)); 2967 break; 2968 case PCIC_CL_PD6729: 2969 case PCIC_CL_PD6730: 2970 clext_reg_write(pcic, socket, 2971 PCIC_CLEXT_MMAP0_UA + win, 2972 SYSMEM_EXT(base)); 2973 break; 2974 case PCIC_TI_PCI1130: 2975 /* 2976 * Note that the TI chip has one upper byte 2977 * per socket so all windows get bound to a 2978 * 16MB segment. This must be detected and 2979 * handled appropriately. We can detect that 2980 * it is done by seeing if the pc_base has 2981 * changed and changing when the register 2982 * is first set. This will force the bounds 2983 * to be correct. 2984 */ 2985 if (pcic->pc_bound == 0xffffffff) { 2986 pcic_putb(pcic, socket, 2987 PCIC_TI_WINDOW_PAGE_PCI, 2988 SYSMEM_EXT(base)); 2989 pcic->pc_base = SYSMEM_EXT(base) << 24; 2990 pcic->pc_bound = 0x1000000; 2991 } 2992 break; 2993 case PCIC_TI_PCI1031: 2994 case PCIC_TI_PCI1131: 2995 case PCIC_TI_PCI1250: 2996 case PCIC_TI_PCI1225: 2997 case PCIC_TI_PCI1221: 2998 case PCIC_SMC_34C90: 2999 case PCIC_CL_PD6832: 3000 case PCIC_RICOH_RL5C466: 3001 case PCIC_TI_PCI1410: 3002 case PCIC_ENE_1410: 3003 case PCIC_TI_PCI1510: 3004 case PCIC_TI_PCI1520: 3005 case PCIC_O2_OZ6912: 3006 case PCIC_TI_PCI1420: 3007 case PCIC_ENE_1420: 3008 case PCIC_TI_VENDOR: 3009 case PCIC_TOSHIBA_TOPIC100: 3010 case PCIC_TOSHIBA_TOPIC95: 3011 case PCIC_TOSHIBA_VENDOR: 3012 case PCIC_RICOH_VENDOR: 3013 case PCIC_O2MICRO_VENDOR: 3014 pcic_putb(pcic, socket, 3015 PCIC_YENTA_MEM_PAGE + win, 3016 SYSMEM_EXT(base)); 3017 break; 3018 default: 3019 cmn_err(CE_NOTE, "pcic_set_window: unknown " 3020 "cardbus vendor:0x%X\n", 3021 pcic->pc_type); 3022 pcic_putb(pcic, socket, 3023 PCIC_YENTA_MEM_PAGE + win, 3024 SYSMEM_EXT(base)); 3025 3026 break; 3027 } /* switch */ 3028 3029 /* 3030 * specify the length of the mapped range 3031 * we convert to pages (rounding up) so that 3032 * the hardware gets the right thing 3033 */ 3034 pages = (window->WindowSize+PCIC_PAGE-1)/PCIC_PAGE; 3035 3036 /* 3037 * Setup this window's timing. 3038 */ 3039 switch (pcic->pc_type) { 3040 case PCIC_CL_PD6729: 3041 case PCIC_CL_PD6730: 3042 case PCIC_CL_PD6710: 3043 case PCIC_CL_PD6722: 3044 wspeed = SYSMEM_CLTIMER_SET_0; 3045 pcic_set_cdtimers(pcic, socket, 3046 window->speed, 3047 wspeed); 3048 break; 3049 3050 case PCIC_INTEL_i82092: 3051 default: 3052 wspeed = pcic_calc_speed(pcic, window->speed); 3053 break; 3054 } /* switch */ 3055 3056 #if defined(PCIC_DEBUG) 3057 if (pcic_debug) 3058 cmn_err(CE_CONT, 3059 "\twindow %d speed bits = %x for " 3060 "%dns\n", 3061 win, (unsigned)wspeed, window->speed); 3062 #endif 3063 3064 pcic_putb(pcic, socket, PCIC_SYSMEM_0_STOPLOW + select, 3065 SYSMEM_LOW(base + 3066 (pages * PCIC_PAGE)-1)); 3067 3068 wspeed |= SYSMEM_HIGH(base + (pages * PCIC_PAGE)-1); 3069 pcic_putb(pcic, socket, PCIC_SYSMEM_0_STOPHI + select, 3070 wspeed); 3071 3072 /* 3073 * now map the card's memory pages - we start with page 3074 * 0 3075 * we also default to AM -- set page might change it 3076 */ 3077 base = memp->pcw_base; 3078 pcic_putb(pcic, socket, 3079 PCIC_CARDMEM_0_LOW + select, 3080 CARDMEM_LOW(0 - (uint32_t)base)); 3081 3082 pcic_putb(pcic, socket, 3083 PCIC_CARDMEM_0_HI + select, 3084 CARDMEM_HIGH(0 - (uint32_t)base) | 3085 CARDMEM_REG_ACTIVE); 3086 3087 /* 3088 * enable the window even though redundant 3089 * and SetPage may do it again. 3090 */ 3091 select = pcic_getb(pcic, socket, 3092 PCIC_MAPPING_ENABLE); 3093 select |= SYSMEM_WINDOW(win); 3094 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, select); 3095 memp->pcw_offset = 0; 3096 memp->pcw_status |= PCW_ENABLED; 3097 } else { 3098 /* 3099 * not only do we unmap the memory, the 3100 * window has been turned off. 3101 */ 3102 if (which && memp->pcw_status & PCW_MAPPED) { 3103 ddi_regs_map_free(&memp->pcw_handle); 3104 res.ra_addr_lo = memp->pcw_base; 3105 res.ra_len = memp->pcw_len; 3106 (void) pcmcia_free_mem(pcic->dip, &res); 3107 memp->pcw_hostmem = NULL; 3108 memp->pcw_status &= ~PCW_MAPPED; 3109 } 3110 3111 /* disable current mapping */ 3112 select = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3113 select &= ~SYSMEM_WINDOW(win); 3114 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, select); 3115 memp->pcw_status &= ~PCW_ENABLED; 3116 } 3117 memp->pcw_len = window->WindowSize; 3118 window->handle = memp->pcw_handle; 3119 #if defined(PCIC_DEBUG) 3120 if (pcic_debug) 3121 xxdmp_all_regs(pcic, window->socket, -1); 3122 #endif 3123 } else { 3124 /* 3125 * This is a request for an IO window 3126 */ 3127 int win, tmp; 3128 pcs_iowin_t *winp; 3129 /* I/O windows */ 3130 #if defined(PCIC_DEBUG) 3131 if (pcic_debug) 3132 cmn_err(CE_CONT, "\twindow type is I/O\n"); 3133 #endif 3134 3135 /* only windows 0 and 1 can do I/O */ 3136 win = window->window % PCIC_NUMWINSOCK; 3137 tmp = window->window / PCIC_NUMWINSOCK; 3138 3139 if (win >= PCIC_IOWINDOWS || tmp != window->socket) { 3140 cmn_err(CE_WARN, 3141 "\twindow is out of range (%d)\n", 3142 window->window); 3143 return (BAD_WINDOW); 3144 } 3145 3146 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3147 3148 winp = &sockp->pcs_windows[win].io; 3149 winp->pcw_speed = window->speed; 3150 if (window->WindowSize != 1 && window->WindowSize & 1) { 3151 /* we don't want an odd-size window */ 3152 window->WindowSize++; 3153 } 3154 winp->pcw_len = window->WindowSize; 3155 3156 if (window->state & WS_ENABLED) { 3157 if (winp->pcw_status & PCW_MAPPED) { 3158 ddi_regs_map_free(&winp->pcw_handle); 3159 res.ra_addr_lo = winp->pcw_base; 3160 res.ra_len = winp->pcw_len; 3161 (void) pcmcia_free_io(pcic->dip, &res); 3162 winp->pcw_status &= ~(PCW_MAPPED|PCW_ENABLED); 3163 } 3164 3165 /* 3166 * if the I/O address wasn't allocated, allocate 3167 * it now. If it was allocated, it better 3168 * be free to use. 3169 * The winp->pcw_offset value is set and used 3170 * later on if the particular adapter 3171 * that we're running on has the ability 3172 * to translate IO accesses to the card 3173 * (such as some adapters in the Cirrus 3174 * Logic family). 3175 */ 3176 winp->pcw_offset = 0; 3177 3178 /* 3179 * Setup the request parameters for the 3180 * requested base and length. If 3181 * we're on an adapter that has 3182 * IO window offset registers, then 3183 * we don't need a specific base 3184 * address, just a length, and then 3185 * we'll cause the correct IO address 3186 * to be generated on the socket by 3187 * setting up the IO window offset 3188 * registers. 3189 * For adapters that support this capability, we 3190 * always use the IO window offset registers, 3191 * even if the passed base/length would be in 3192 * range. 3193 */ 3194 base = window->base; 3195 bzero(&req, sizeof (req)); 3196 req.ra_len = window->WindowSize; 3197 3198 req.ra_addr = (uint64_t) 3199 ((pcic->pc_flags & PCF_IO_REMAP) ? 0 : base); 3200 req.ra_flags = (req.ra_addr) ? 3201 NDI_RA_ALLOC_SPECIFIED : 0; 3202 3203 req.ra_flags |= NDI_RA_ALIGN_SIZE; 3204 /* need to rethink this */ 3205 req.ra_boundbase = pcic->pc_iobase; 3206 req.ra_boundlen = pcic->pc_iobound; 3207 req.ra_flags |= NDI_RA_ALLOC_BOUNDED; 3208 3209 #if defined(PCIC_DEBUG) 3210 pcic_err(dip, 8, 3211 "\tlen 0x%"PRIx64" addr 0x%"PRIx64 3212 "bbase 0x%"PRIx64 3213 "blen 0x%"PRIx64" flags 0x%x algn 0x%" 3214 PRIx64"\n", 3215 req.ra_len, (uint64_t)req.ra_addr, 3216 req.ra_boundbase, 3217 req.ra_boundlen, req.ra_flags, 3218 req.ra_align_mask); 3219 #endif 3220 3221 /* 3222 * Try to allocate the space. If we fail this, 3223 * return the appropriate error depending 3224 * on whether the caller specified a 3225 * specific base address or not. 3226 */ 3227 if (pcmcia_alloc_io(dip, &req, &res) == DDI_FAILURE) { 3228 winp->pcw_status &= ~PCW_ENABLED; 3229 mutex_exit(&pcic->pc_lock); 3230 cmn_err(CE_WARN, "Failed to alloc I/O:\n" 3231 "\tlen 0x%" PRIx64 " addr 0x%" PRIx64 3232 "bbase 0x%" PRIx64 3233 "blen 0x%" PRIx64 "flags 0x%x" 3234 "algn 0x%" PRIx64 "\n", 3235 req.ra_len, req.ra_addr, 3236 req.ra_boundbase, 3237 req.ra_boundlen, req.ra_flags, 3238 req.ra_align_mask); 3239 3240 return (base?BAD_BASE:BAD_SIZE); 3241 } /* pcmcia_alloc_io */ 3242 3243 /* 3244 * Don't change the original base. Either we use 3245 * the offset registers below (PCF_IO_REMAP is set) 3246 * or it was allocated correctly anyway. 3247 */ 3248 winp->pcw_base = res.ra_addr_lo; 3249 3250 #if defined(PCIC_DEBUG) 3251 pcic_err(dip, 8, 3252 "\tsetwindow: new base=%x orig base 0x%x\n", 3253 (unsigned)winp->pcw_base, base); 3254 #endif 3255 3256 if ((which = pcmcia_map_reg(pcic->dip, 3257 window->child, 3258 &res, 3259 (uint32_t)(window->state & 3260 0xffff) | 3261 (window->socket << 16), 3262 (caddr_t *)&winp->pcw_hostmem, 3263 &winp->pcw_handle, 3264 &window->attr, 3265 base)) != DDI_SUCCESS) { 3266 3267 cmn_err(CE_WARN, "pcmcia_map_reg()" 3268 "failed\n"); 3269 3270 res.ra_addr_lo = winp->pcw_base; 3271 res.ra_len = winp->pcw_len; 3272 (void) pcmcia_free_io(pcic->dip, &res); 3273 3274 mutex_exit(&pcic->pc_lock); 3275 return (BAD_WINDOW); 3276 } 3277 3278 window->handle = winp->pcw_handle; 3279 winp->pcw_status |= PCW_MAPPED; 3280 3281 /* find the register set offset */ 3282 select = win * PCIC_IO_OFFSET; 3283 3284 #if defined(PCIC_DEBUG) 3285 if (pcic_debug) { 3286 cmn_err(CE_CONT, 3287 "\tenable: window=%d, select=%x, " 3288 "base=%x, handle=%p\n", 3289 win, select, 3290 (unsigned)window->base, 3291 (void *)window->handle); 3292 } 3293 #endif 3294 /* 3295 * at this point, the register window indicator has 3296 * been converted to be an offset from the first 3297 * set of registers that are used for programming 3298 * the window mapping and the offset used to select 3299 * the correct set of registers to access the 3300 * specified socket. This allows basing everything 3301 * off the _0 window 3302 */ 3303 3304 /* map the I/O base in */ 3305 pcic_putb(pcic, socket, 3306 PCIC_IO_ADDR_0_STARTLOW + select, 3307 LOW_BYTE((uint32_t)winp->pcw_base)); 3308 pcic_putb(pcic, socket, 3309 PCIC_IO_ADDR_0_STARTHI + select, 3310 HIGH_BYTE((uint32_t)winp->pcw_base)); 3311 3312 pcic_putb(pcic, socket, 3313 PCIC_IO_ADDR_0_STOPLOW + select, 3314 LOW_BYTE((uint32_t)winp->pcw_base + 3315 window->WindowSize - 1)); 3316 pcic_putb(pcic, socket, 3317 PCIC_IO_ADDR_0_STOPHI + select, 3318 HIGH_BYTE((uint32_t)winp->pcw_base + 3319 window->WindowSize - 1)); 3320 3321 /* 3322 * We've got the requested IO space, now see if we 3323 * need to adjust the IO window offset registers 3324 * so that the correct IO address is generated 3325 * at the socket. If this window doesn't have 3326 * this capability, then we're all done setting 3327 * up the IO resources. 3328 */ 3329 if (pcic->pc_flags & PCF_IO_REMAP) { 3330 3331 3332 /* 3333 * Note that only 16 bits are used to program 3334 * the registers but leave 32 bits on pcw_offset 3335 * so that we can generate the original base 3336 * in get_window() 3337 */ 3338 winp->pcw_offset = (base - winp->pcw_base); 3339 3340 pcic_putb(pcic, socket, 3341 PCIC_IO_OFFSET_LOW + 3342 (win * PCIC_IO_OFFSET_OFFSET), 3343 winp->pcw_offset & 0x0ff); 3344 pcic_putb(pcic, socket, 3345 PCIC_IO_OFFSET_HI + 3346 (win * PCIC_IO_OFFSET_OFFSET), 3347 (winp->pcw_offset >> 8) & 0x0ff); 3348 3349 } /* PCF_IO_REMAP */ 3350 3351 /* now get the other details (size, etc) right */ 3352 3353 /* 3354 * Set the data size control bits here. Most of the 3355 * adapters will ignore IOMEM_16BIT when 3356 * IOMEM_IOCS16 is set, except for the Intel 3357 * 82092, which only pays attention to the 3358 * IOMEM_16BIT bit. Sigh... Intel can't even 3359 * make a proper clone of their own chip. 3360 * The 82092 also apparently can't set the timing 3361 * of I/O windows. 3362 */ 3363 which = (window->state & WS_16BIT) ? 3364 (IOMEM_16BIT | IOMEM_IOCS16) : 0; 3365 3366 switch (pcic->pc_type) { 3367 case PCIC_CL_PD6729: 3368 case PCIC_CL_PD6730: 3369 case PCIC_CL_PD6710: 3370 case PCIC_CL_PD6722: 3371 case PCIC_CL_PD6832: 3372 /* 3373 * Select Timer Set 1 - this will take 3374 * effect when the PCIC_IO_CONTROL 3375 * register is written to later on; 3376 * the call to pcic_set_cdtimers 3377 * just sets up the timer itself. 3378 */ 3379 which |= IOMEM_CLTIMER_SET_1; 3380 pcic_set_cdtimers(pcic, socket, 3381 window->speed, 3382 IOMEM_CLTIMER_SET_1); 3383 which |= IOMEM_IOCS16; 3384 break; 3385 case PCIC_TI_PCI1031: 3386 3387 if (window->state & WS_16BIT) 3388 which |= IOMEM_WAIT16; 3389 3390 break; 3391 case PCIC_TI_PCI1130: 3392 3393 if (window->state & WS_16BIT) 3394 which |= IOMEM_WAIT16; 3395 3396 break; 3397 case PCIC_INTEL_i82092: 3398 break; 3399 default: 3400 if (window->speed > 3401 mhztons(pcic->bus_speed) * 3) 3402 which |= IOMEM_WAIT16; 3403 #ifdef notdef 3404 if (window->speed < 3405 mhztons(pcic->bus_speed) * 6) 3406 which |= IOMEM_ZERO_WAIT; 3407 #endif 3408 break; 3409 } /* switch (pc_type) */ 3410 3411 /* 3412 * Setup the data width and timing 3413 */ 3414 select = pcic_getb(pcic, socket, PCIC_IO_CONTROL); 3415 select &= ~(PCIC_IO_WIN_MASK << (win * 4)); 3416 select |= IOMEM_SETWIN(win, which); 3417 pcic_putb(pcic, socket, PCIC_IO_CONTROL, select); 3418 3419 /* 3420 * Enable the IO window 3421 */ 3422 select = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3423 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, 3424 select | IOMEM_WINDOW(win)); 3425 3426 winp->pcw_status |= PCW_ENABLED; 3427 3428 #if defined(PCIC_DEBUG) 3429 if (pcic_debug) { 3430 cmn_err(CE_CONT, 3431 "\twhich = %x, select = %x (%x)\n", 3432 which, select, 3433 IOMEM_SETWIN(win, which)); 3434 xxdmp_all_regs(pcic, window->socket * 0x40, 24); 3435 } 3436 #endif 3437 } else { 3438 /* 3439 * not only do we unmap the IO space, the 3440 * window has been turned off. 3441 */ 3442 if (winp->pcw_status & PCW_MAPPED) { 3443 ddi_regs_map_free(&winp->pcw_handle); 3444 res.ra_addr_lo = winp->pcw_base; 3445 res.ra_len = winp->pcw_len; 3446 (void) pcmcia_free_io(pcic->dip, &res); 3447 winp->pcw_status &= ~PCW_MAPPED; 3448 } 3449 3450 /* disable current mapping */ 3451 select = pcic_getb(pcic, socket, 3452 PCIC_MAPPING_ENABLE); 3453 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, 3454 select &= ~IOMEM_WINDOW(win)); 3455 winp->pcw_status &= ~PCW_ENABLED; 3456 3457 winp->pcw_base = 0; 3458 winp->pcw_len = 0; 3459 winp->pcw_offset = 0; 3460 window->base = 0; 3461 /* now make sure we don't accidentally re-enable */ 3462 /* find the register set offset */ 3463 select = win * PCIC_IO_OFFSET; 3464 pcic_putb(pcic, socket, 3465 PCIC_IO_ADDR_0_STARTLOW + select, 0); 3466 pcic_putb(pcic, socket, 3467 PCIC_IO_ADDR_0_STARTHI + select, 0); 3468 pcic_putb(pcic, socket, 3469 PCIC_IO_ADDR_0_STOPLOW + select, 0); 3470 pcic_putb(pcic, socket, 3471 PCIC_IO_ADDR_0_STOPHI + select, 0); 3472 } 3473 } 3474 mutex_exit(&pcic->pc_lock); 3475 3476 return (SUCCESS); 3477 } 3478 3479 /* 3480 * pcic_card_state() 3481 * compute the instantaneous Card State information 3482 */ 3483 static int 3484 pcic_card_state(pcicdev_t *pcic, pcic_socket_t *sockp) 3485 { 3486 int value, result; 3487 #if defined(PCIC_DEBUG) 3488 int orig_value; 3489 #endif 3490 3491 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3492 3493 value = pcic_getb(pcic, sockp->pcs_socket, PCIC_INTERFACE_STATUS); 3494 3495 #if defined(PCIC_DEBUG) 3496 orig_value = value; 3497 if (pcic_debug >= 8) 3498 cmn_err(CE_CONT, "pcic_card_state(%p) if status = %b for %d\n", 3499 (void *)sockp, 3500 value, 3501 "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI", 3502 sockp->pcs_socket); 3503 #endif 3504 /* 3505 * Lie to socket services if we are not ready. 3506 * This is when we are starting up or during debounce timeouts 3507 * or if the card is a cardbus card. 3508 */ 3509 if (!(sockp->pcs_flags & (PCS_STARTING|PCS_CARD_ISCARDBUS)) && 3510 !sockp->pcs_debounce_id && 3511 (value & PCIC_ISTAT_CD_MASK) == PCIC_CD_PRESENT_OK) { 3512 result = SBM_CD; 3513 3514 if (value & PCIC_WRITE_PROTECT || !(value & PCIC_POWER_ON)) 3515 result |= SBM_WP; 3516 if (value & PCIC_POWER_ON) { 3517 if (value & PCIC_READY) 3518 result |= SBM_RDYBSY; 3519 value = (~value) & (PCIC_BVD1 | PCIC_BVD2); 3520 if (value & PCIC_BVD1) 3521 result |= SBM_BVD1; 3522 if (value & PCIC_BVD2) 3523 result |= SBM_BVD2; 3524 } 3525 } else 3526 result = 0; 3527 3528 mutex_exit(&pcic->pc_lock); 3529 3530 #if defined(PCIC_DEBUG) 3531 pcic_err(pcic->dip, 8, 3532 "pcic_card_state(%p) if status = %b for %d (rval=0x%x)\n", 3533 (void *) sockp, orig_value, 3534 "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI", 3535 sockp->pcs_socket, result); 3536 #endif 3537 3538 return (result); 3539 } 3540 3541 /* 3542 * pcic_set_page() 3543 * SocketServices SetPage function 3544 * set the page of PC Card memory that should be in the mapped 3545 * window 3546 */ 3547 /*ARGSUSED*/ 3548 static int 3549 pcic_set_page(dev_info_t *dip, set_page_t *page) 3550 { 3551 anp_t *anp = ddi_get_driver_private(dip); 3552 pcicdev_t *pcic = anp->an_private; 3553 int select; 3554 int which, socket, window; 3555 uint32_t base; 3556 pcs_memwin_t *memp; 3557 3558 /* get real socket/window numbers */ 3559 window = page->window % PCIC_NUMWINSOCK; 3560 socket = page->window / PCIC_NUMWINSOCK; 3561 3562 #if defined(PCIC_DEBUG) 3563 if (pcic_debug) { 3564 cmn_err(CE_CONT, 3565 "pcic_set_page: window=%d, socket=%d, page=%d\n", 3566 window, socket, page->page); 3567 } 3568 #endif 3569 /* only windows 2-6 work on memory */ 3570 if (window < PCIC_IOWINDOWS) 3571 return (BAD_WINDOW); 3572 3573 /* only one page supported (but any size) */ 3574 if (page->page != 0) 3575 return (BAD_PAGE); 3576 3577 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3578 3579 memp = &pcic->pc_sockets[socket].pcs_windows[window].mem; 3580 window -= PCIC_IOWINDOWS; 3581 3582 #if defined(PCIC_DEBUG) 3583 if (pcic_debug) 3584 cmn_err(CE_CONT, "\tpcw_base=%x, pcw_hostmem=%p, pcw_len=%x\n", 3585 (uint32_t)memp->pcw_base, 3586 (void *)memp->pcw_hostmem, memp->pcw_len); 3587 #endif 3588 3589 /* window must be enabled */ 3590 if (!(memp->pcw_status & PCW_ENABLED)) 3591 return (BAD_ATTRIBUTE); 3592 3593 /* find the register set offset */ 3594 select = window * PCIC_MEM_1_OFFSET; 3595 #if defined(PCIC_DEBUG) 3596 if (pcic_debug) 3597 cmn_err(CE_CONT, "\tselect=%x\n", select); 3598 #endif 3599 3600 /* 3601 * now map the card's memory pages - we start with page 0 3602 */ 3603 3604 which = 0; /* assume simple case */ 3605 if (page->state & PS_ATTRIBUTE) { 3606 which |= CARDMEM_REG_ACTIVE; 3607 memp->pcw_status |= PCW_ATTRIBUTE; 3608 } else { 3609 memp->pcw_status &= ~PCW_ATTRIBUTE; 3610 } 3611 3612 /* 3613 * if caller says Write Protect, enforce it. 3614 */ 3615 if (page->state & PS_WP) { 3616 which |= CARDMEM_WRITE_PROTECT; 3617 memp->pcw_status |= PCW_WP; 3618 } else { 3619 memp->pcw_status &= ~PCW_WP; 3620 } 3621 #if defined(PCIC_DEBUG) 3622 if (pcic_debug) { 3623 cmn_err(CE_CONT, "\tmemory type = %s\n", 3624 (which & CARDMEM_REG_ACTIVE) ? "attribute" : "common"); 3625 if (which & CARDMEM_WRITE_PROTECT) 3626 cmn_err(CE_CONT, "\twrite protect\n"); 3627 cmn_err(CE_CONT, "\tpage offset=%x pcw_base=%x (%x)\n", 3628 (unsigned)page->offset, 3629 (unsigned)memp->pcw_base, 3630 (int)page->offset - (int)memp->pcw_base & 0xffffff); 3631 } 3632 #endif 3633 /* address computation based on 64MB range and not larger */ 3634 base = (uint32_t)memp->pcw_base & 0x3ffffff; 3635 pcic_putb(pcic, socket, PCIC_CARDMEM_0_LOW + select, 3636 CARDMEM_LOW((int)page->offset - (int)base)); 3637 (void) pcic_getb(pcic, socket, PCIC_CARDMEM_0_LOW + select); 3638 pcic_putb(pcic, socket, PCIC_CARDMEM_0_HI + select, 3639 CARDMEM_HIGH((int)page->offset - base) | which); 3640 (void) pcic_getb(pcic, socket, PCIC_CARDMEM_0_HI + select); 3641 3642 /* 3643 * while not really necessary, this just makes sure 3644 * nothing turned the window off behind our backs 3645 */ 3646 which = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3647 which |= SYSMEM_WINDOW(window); 3648 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, which); 3649 (void) pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 3650 3651 memp->pcw_offset = (off_t)page->offset; 3652 3653 #if defined(PCIC_DEBUG) 3654 if (pcic_debug) { 3655 cmn_err(CE_CONT, "\tbase=%p, *base=%x\n", 3656 (void *)memp->pcw_hostmem, 3657 (uint32_t)*memp->pcw_hostmem); 3658 3659 xxdmp_all_regs(pcic, socket, -1); 3660 3661 cmn_err(CE_CONT, "\tbase=%p, *base=%x\n", 3662 (void *)memp->pcw_hostmem, 3663 (uint32_t)*memp->pcw_hostmem); 3664 } 3665 #endif 3666 3667 if (which & PCW_ATTRIBUTE) 3668 pcic_mswait(pcic, socket, 2); 3669 3670 mutex_exit(&pcic->pc_lock); 3671 3672 return (SUCCESS); 3673 } 3674 3675 /* 3676 * pcic_set_vcc_level() 3677 * 3678 * set voltage based on adapter information 3679 * 3680 * this routine implements a limited solution for support of 3.3v cards. 3681 * the general solution, which would fully support the pcmcia spec 3682 * as far as allowing client drivers to request which voltage levels 3683 * to be set, requires more framework support and driver changes - ess 3684 */ 3685 static int 3686 pcic_set_vcc_level(pcicdev_t *pcic, set_socket_t *socket) 3687 { 3688 uint32_t socket_present_state; 3689 3690 #if defined(PCIC_DEBUG) 3691 if (pcic_debug) { 3692 cmn_err(CE_CONT, 3693 "pcic_set_vcc_level(pcic=%p, VccLevel=%d)\n", 3694 (void *)pcic, socket->VccLevel); 3695 } 3696 #endif 3697 3698 /* 3699 * check VccLevel 3700 * if this is zero, power is being turned off 3701 * if it is non-zero, power is being turned on. 3702 */ 3703 if (socket->VccLevel == 0) { 3704 return (0); 3705 } 3706 3707 /* 3708 * range checking for sanity's sake 3709 */ 3710 if (socket->VccLevel >= pcic->pc_numpower) { 3711 return (BAD_VCC); 3712 } 3713 3714 switch (pcic->pc_io_type) { 3715 /* 3716 * Yenta-compliant adapters have vcc info in the extended registers 3717 * Other adapters can be added as needed, but the 'default' case 3718 * has been left as it was previously so as not to break existing 3719 * adapters. 3720 */ 3721 case PCIC_IO_TYPE_YENTA: 3722 /* 3723 * Here we ignore the VccLevel passed in and read the 3724 * card type from the adapter socket present state register 3725 */ 3726 socket_present_state = 3727 ddi_get32(pcic->handle, (uint32_t *)(pcic->ioaddr + 3728 PCIC_PRESENT_STATE_REG)); 3729 #if defined(PCIC_DEBUG) 3730 if (pcic_debug) { 3731 cmn_err(CE_CONT, 3732 "socket present state = 0x%x\n", 3733 socket_present_state); 3734 } 3735 #endif 3736 switch (socket_present_state & PCIC_VCC_MASK) { 3737 case PCIC_VCC_3VCARD: 3738 /* fall through */ 3739 case PCIC_VCC_3VCARD|PCIC_VCC_5VCARD: 3740 socket->VccLevel = PCIC_VCC_3VLEVEL; 3741 return 3742 (POWER_3VCARD_ENABLE|POWER_OUTPUT_ENABLE); 3743 case PCIC_VCC_5VCARD: 3744 socket->VccLevel = PCIC_VCC_5VLEVEL; 3745 return 3746 (POWER_CARD_ENABLE|POWER_OUTPUT_ENABLE); 3747 default: 3748 /* 3749 * if no card is present, this can be the 3750 * case of a client making a SetSocket call 3751 * after card removal. In this case we return 3752 * the current power level 3753 */ 3754 return ((unsigned)ddi_get8(pcic->handle, 3755 pcic->ioaddr + CB_R2_OFFSET + 3756 PCIC_POWER_CONTROL)); 3757 } 3758 3759 default: 3760 3761 switch (socket->VccLevel) { 3762 case PCIC_VCC_3VLEVEL: 3763 return (BAD_VCC); 3764 case PCIC_VCC_5VLEVEL: 3765 /* enable Vcc */ 3766 return (POWER_CARD_ENABLE|POWER_OUTPUT_ENABLE); 3767 default: 3768 return (BAD_VCC); 3769 } 3770 } 3771 } 3772 3773 3774 /* 3775 * pcic_set_socket() 3776 * Socket Services SetSocket call 3777 * sets basic socket configuration 3778 */ 3779 static int 3780 pcic_set_socket(dev_info_t *dip, set_socket_t *socket) 3781 { 3782 anp_t *anp = ddi_get_driver_private(dip); 3783 pcicdev_t *pcic = anp->an_private; 3784 pcic_socket_t *sockp = &pcic->pc_sockets[socket->socket]; 3785 int irq, interrupt, mirq; 3786 int powerlevel = 0; 3787 int ind, value, orig_pwrctl; 3788 3789 #if defined(PCIC_DEBUG) 3790 if (pcic_debug) { 3791 cmn_err(CE_CONT, 3792 "pcic_set_socket(dip=%p, socket=%d)" 3793 " Vcc=%d Vpp1=%d Vpp2=%d\n", (void *)dip, 3794 socket->socket, socket->VccLevel, socket->Vpp1Level, 3795 socket->Vpp2Level); 3796 } 3797 #endif 3798 /* 3799 * check VccLevel, etc. before setting mutex 3800 * if this is zero, power is being turned off 3801 * if it is non-zero, power is being turned on. 3802 * the default case is to assume Vcc only. 3803 */ 3804 3805 /* this appears to be very implementation specific */ 3806 3807 if (socket->Vpp1Level != socket->Vpp2Level) 3808 return (BAD_VPP); 3809 3810 if (socket->VccLevel == 0 || !(sockp->pcs_flags & PCS_CARD_PRESENT)) { 3811 powerlevel = 0; 3812 sockp->pcs_vcc = 0; 3813 sockp->pcs_vpp1 = 0; 3814 sockp->pcs_vpp2 = 0; 3815 } else { 3816 #if defined(PCIC_DEBUG) 3817 pcic_err(dip, 9, "\tVcc=%d Vpp1Level=%d, Vpp2Level=%d\n", 3818 socket->VccLevel, socket->Vpp1Level, socket->Vpp2Level); 3819 #endif 3820 /* valid Vcc power level? */ 3821 if (socket->VccLevel >= pcic->pc_numpower) 3822 return (BAD_VCC); 3823 3824 switch (pcic_power[socket->VccLevel].PowerLevel) { 3825 case 33: /* 3.3V */ 3826 case 60: /* for bad CIS in Option GPRS card */ 3827 if (!(pcic->pc_flags & PCF_33VCAP)) { 3828 cmn_err(CE_WARN, 3829 "%s%d: Bad Request for 3.3V " 3830 "(Controller incapable)\n", 3831 ddi_get_name(pcic->dip), 3832 ddi_get_instance(pcic->dip)); 3833 return (BAD_VCC); 3834 } 3835 /* FALLTHROUGH */ 3836 case 50: /* 5V */ 3837 if ((pcic->pc_io_type == PCIC_IO_TYPE_YENTA) && 3838 pcic_getcb(pcic, CB_PRESENT_STATE) & 3839 CB_PS_33VCARD) { 3840 /* 3841 * This is actually a 3.3V card. 3842 * Solaris Card Services 3843 * doesn't understand 3.3V 3844 * so we cheat and change 3845 * the setting to the one appropriate to 3.3V. 3846 * Note that this is the entry number 3847 * in the pcic_power[] array. 3848 */ 3849 sockp->pcs_vcc = PCIC_VCC_3VLEVEL; 3850 } else 3851 sockp->pcs_vcc = socket->VccLevel; 3852 break; 3853 default: 3854 return (BAD_VCC); 3855 } 3856 3857 /* enable Vcc */ 3858 powerlevel = POWER_CARD_ENABLE; 3859 3860 #if defined(PCIC_DEBUG) 3861 if (pcic_debug) { 3862 cmn_err(CE_CONT, "\tVcc=%d powerlevel=%x\n", 3863 socket->VccLevel, powerlevel); 3864 } 3865 #endif 3866 ind = 0; /* default index to 0 power */ 3867 if ((int)socket->Vpp1Level >= 0 && 3868 socket->Vpp1Level < pcic->pc_numpower) { 3869 if (!(pcic_power[socket->Vpp1Level].ValidSignals 3870 & VPP1)) { 3871 return (BAD_VPP); 3872 } 3873 ind = pcic_power[socket->Vpp1Level].PowerLevel/10; 3874 powerlevel |= pcic_vpp_levels[ind]; 3875 sockp->pcs_vpp1 = socket->Vpp1Level; 3876 } 3877 if ((int)socket->Vpp2Level >= 0 && 3878 socket->Vpp2Level < pcic->pc_numpower) { 3879 if (!(pcic_power[socket->Vpp2Level].ValidSignals 3880 & VPP2)) { 3881 return (BAD_VPP); 3882 } 3883 ind = pcic_power[socket->Vpp2Level].PowerLevel/10; 3884 powerlevel |= (pcic_vpp_levels[ind] << 2); 3885 sockp->pcs_vpp2 = socket->Vpp2Level; 3886 } 3887 3888 if (pcic->pc_flags & PCF_VPPX) { 3889 /* 3890 * this adapter doesn't allow separate Vpp1/Vpp2 3891 * if one is turned on, both are turned on and only 3892 * the Vpp1 bits should be set 3893 */ 3894 if (sockp->pcs_vpp2 != sockp->pcs_vpp1) { 3895 /* must be the same if one not zero */ 3896 if (sockp->pcs_vpp1 != 0 && 3897 sockp->pcs_vpp2 != 0) { 3898 cmn_err(CE_WARN, 3899 "%s%d: Bad Power Request " 3900 "(Vpp1/2 not the same)\n", 3901 ddi_get_name(pcic->dip), 3902 ddi_get_instance(pcic->dip)); 3903 return (BAD_VPP); 3904 } 3905 } 3906 powerlevel &= ~(3<<2); 3907 } 3908 3909 #if defined(PCIC_DEBUG) 3910 if (pcic_debug) { 3911 cmn_err(CE_CONT, "\tpowerlevel=%x, ind=%x\n", 3912 powerlevel, ind); 3913 } 3914 #endif 3915 } 3916 mutex_enter(&pcic->pc_lock); /* protect the registers */ 3917 3918 /* turn socket->IREQRouting off while programming */ 3919 interrupt = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT); 3920 interrupt &= ~PCIC_INTR_MASK; 3921 if (pcic->pc_flags & PCF_USE_SMI) 3922 interrupt |= PCIC_INTR_ENABLE; 3923 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, interrupt); 3924 3925 switch (pcic->pc_type) { 3926 case PCIC_INTEL_i82092: 3927 pcic_82092_smiirq_ctl(pcic, socket->socket, PCIC_82092_CTL_IRQ, 3928 PCIC_82092_INT_DISABLE); 3929 break; 3930 default: 3931 break; 3932 } /* switch */ 3933 3934 /* the SCIntMask specifies events to detect */ 3935 mirq = pcic_getb(pcic, socket->socket, PCIC_MANAGEMENT_INT); 3936 3937 #if defined(PCIC_DEBUG) 3938 if (pcic_debug) 3939 cmn_err(CE_CONT, 3940 "\tSCIntMask=%x, interrupt=%x, mirq=%x\n", 3941 socket->SCIntMask, interrupt, mirq); 3942 #endif 3943 mirq &= ~(PCIC_BD_DETECT|PCIC_BW_DETECT|PCIC_RD_DETECT); 3944 pcic_putb(pcic, socket->socket, PCIC_MANAGEMENT_INT, 3945 mirq & ~PCIC_CHANGE_MASK); 3946 3947 /* save the mask we want to use */ 3948 sockp->pcs_intmask = socket->SCIntMask; 3949 3950 /* 3951 * Until there is a card present it's not worth enabling 3952 * any interrupts except "Card detect". This is done 3953 * elsewhere in the driver so don't change things if 3954 * there is no card! 3955 */ 3956 if (sockp->pcs_flags & PCS_CARD_PRESENT) { 3957 3958 /* now update the hardware to reflect events desired */ 3959 if (sockp->pcs_intmask & SBM_BVD1 || socket->IFType == IF_IO) 3960 mirq |= PCIC_BD_DETECT; 3961 3962 if (sockp->pcs_intmask & SBM_BVD2) 3963 mirq |= PCIC_BW_DETECT; 3964 3965 if (sockp->pcs_intmask & SBM_RDYBSY) 3966 mirq |= PCIC_RD_DETECT; 3967 3968 if (sockp->pcs_intmask & SBM_CD) 3969 mirq |= PCIC_CD_DETECT; 3970 } 3971 3972 if (sockp->pcs_flags & PCS_READY) { 3973 /* 3974 * card just came ready. 3975 * make sure enough time elapses 3976 * before touching it. 3977 */ 3978 sockp->pcs_flags &= ~PCS_READY; 3979 pcic_mswait(pcic, socket->socket, 10); 3980 } 3981 3982 #if defined(PCIC_DEBUG) 3983 if (pcic_debug) { 3984 cmn_err(CE_CONT, "\tstatus change set to %x\n", mirq); 3985 } 3986 #endif 3987 3988 switch (pcic->pc_type) { 3989 case PCIC_I82365SL: 3990 case PCIC_VADEM: 3991 case PCIC_VADEM_VG469: 3992 /* 3993 * The Intel version has different options. This is a 3994 * special case of GPI which might be used for eject 3995 */ 3996 3997 irq = pcic_getb(pcic, socket->socket, PCIC_CARD_DETECT); 3998 if (sockp->pcs_intmask & (SBM_EJECT|SBM_INSERT) && 3999 pcic->pc_flags & PCF_GPI_EJECT) { 4000 irq |= PCIC_GPI_ENABLE; 4001 } else { 4002 irq &= ~PCIC_GPI_ENABLE; 4003 } 4004 pcic_putb(pcic, socket->socket, PCIC_CARD_DETECT, irq); 4005 break; 4006 case PCIC_CL_PD6710: 4007 case PCIC_CL_PD6722: 4008 if (socket->IFType == IF_IO) { 4009 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_2, 0x0); 4010 value = pcic_getb(pcic, socket->socket, 4011 PCIC_MISC_CTL_1); 4012 if (pcic->pc_flags & PCF_AUDIO) 4013 value |= PCIC_MC_SPEAKER_ENB; 4014 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1, 4015 value); 4016 } else { 4017 value = pcic_getb(pcic, socket->socket, 4018 PCIC_MISC_CTL_1); 4019 value &= ~PCIC_MC_SPEAKER_ENB; 4020 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1, 4021 value); 4022 } 4023 break; 4024 case PCIC_CL_PD6729: 4025 case PCIC_CL_PD6730: 4026 case PCIC_CL_PD6832: 4027 value = pcic_getb(pcic, socket->socket, PCIC_MISC_CTL_1); 4028 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) { 4029 value |= PCIC_MC_SPEAKER_ENB; 4030 } else { 4031 value &= ~PCIC_MC_SPEAKER_ENB; 4032 } 4033 4034 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33) 4035 value |= PCIC_MC_3VCC; 4036 else 4037 value &= ~PCIC_MC_3VCC; 4038 4039 pcic_putb(pcic, socket->socket, PCIC_MISC_CTL_1, value); 4040 break; 4041 4042 case PCIC_O2_OZ6912: 4043 value = pcic_getcb(pcic, CB_MISCCTRL); 4044 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) 4045 value |= (1<<25); 4046 else 4047 value &= ~(1<<25); 4048 pcic_putcb(pcic, CB_MISCCTRL, value); 4049 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33) 4050 powerlevel |= 0x08; 4051 break; 4052 4053 case PCIC_TI_PCI1250: 4054 case PCIC_TI_PCI1221: 4055 case PCIC_TI_PCI1225: 4056 case PCIC_TI_PCI1410: 4057 case PCIC_ENE_1410: 4058 case PCIC_TI_PCI1510: 4059 case PCIC_TI_PCI1520: 4060 case PCIC_TI_PCI1420: 4061 case PCIC_ENE_1420: 4062 value = ddi_get8(pcic->cfg_handle, 4063 pcic->cfgaddr + PCIC_CRDCTL_REG); 4064 if ((socket->IFType == IF_IO) && (pcic->pc_flags & PCF_AUDIO)) { 4065 value |= PCIC_CRDCTL_SPKR_ENBL; 4066 } else { 4067 value &= ~PCIC_CRDCTL_SPKR_ENBL; 4068 } 4069 ddi_put8(pcic->cfg_handle, 4070 pcic->cfgaddr + PCIC_CRDCTL_REG, value); 4071 if (pcic_power[sockp->pcs_vcc].PowerLevel == 33) 4072 powerlevel |= 0x08; 4073 break; 4074 } 4075 4076 /* 4077 * ctlind processing -- we can ignore this 4078 * there aren't any outputs on the chip for this and 4079 * the GUI will display what it thinks is correct 4080 */ 4081 4082 /* 4083 * If outputs are enabled and the power is going off 4084 * turn off outputs first. 4085 */ 4086 4087 /* power setup -- if necessary */ 4088 orig_pwrctl = pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL); 4089 if ((orig_pwrctl & POWER_OUTPUT_ENABLE) && sockp->pcs_vcc == 0) { 4090 orig_pwrctl &= ~POWER_OUTPUT_ENABLE; 4091 pcic_putb(pcic, socket->socket, 4092 PCIC_POWER_CONTROL, orig_pwrctl); 4093 (void) pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL); 4094 } 4095 4096 if (pcic->pc_flags & PCF_CBPWRCTL) { 4097 value = pcic_cbus_powerctl(pcic, socket->socket); 4098 powerlevel = 0; 4099 } else 4100 value = pcic_exca_powerctl(pcic, socket->socket, powerlevel); 4101 4102 if (value != SUCCESS) { 4103 mutex_exit(&pcic->pc_lock); 4104 return (value); 4105 } 4106 4107 /* 4108 * If outputs were disabled and the power is going on 4109 * turn on outputs afterwards. 4110 */ 4111 if (!(orig_pwrctl & POWER_OUTPUT_ENABLE) && sockp->pcs_vcc != 0) { 4112 orig_pwrctl = pcic_getb(pcic, socket->socket, 4113 PCIC_POWER_CONTROL); 4114 orig_pwrctl |= POWER_OUTPUT_ENABLE; 4115 pcic_putb(pcic, socket->socket, 4116 PCIC_POWER_CONTROL, orig_pwrctl); 4117 (void) pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL); 4118 } 4119 4120 /* 4121 * Once we have done the power stuff can re-enable management 4122 * interrupts. 4123 */ 4124 pcic_putb(pcic, socket->socket, PCIC_MANAGEMENT_INT, mirq); 4125 4126 #if defined(PCIC_DEBUG) 4127 pcic_err(dip, 8, "\tmanagement int set to %x pwrctl to 0x%x " 4128 "cbctl 0x%x\n", 4129 mirq, pcic_getb(pcic, socket->socket, PCIC_POWER_CONTROL), 4130 pcic_getcb(pcic, CB_CONTROL)); 4131 #endif 4132 4133 /* irq processing */ 4134 if (socket->IFType == IF_IO) { 4135 /* IRQ only for I/O */ 4136 irq = socket->IREQRouting & PCIC_INTR_MASK; 4137 value = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT); 4138 value &= ~PCIC_INTR_MASK; 4139 4140 /* to enable I/O operation */ 4141 value |= PCIC_IO_CARD | PCIC_RESET; 4142 sockp->pcs_flags |= PCS_CARD_IO; 4143 if (irq != sockp->pcs_irq) { 4144 if (sockp->pcs_irq != 0) 4145 cmn_err(CE_CONT, 4146 "SetSocket: IRQ mismatch %x != %x!\n", 4147 irq, sockp->pcs_irq); 4148 else 4149 sockp->pcs_irq = irq; 4150 } 4151 irq = sockp->pcs_irq; 4152 4153 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, value); 4154 if (socket->IREQRouting & IRQ_ENABLE) { 4155 pcic_enable_io_intr(pcic, socket->socket, irq); 4156 sockp->pcs_flags |= PCS_IRQ_ENABLED; 4157 } else { 4158 pcic_disable_io_intr(pcic, socket->socket); 4159 sockp->pcs_flags &= ~PCS_IRQ_ENABLED; 4160 } 4161 #if defined(PCIC_DEBUG) 4162 if (pcic_debug) { 4163 cmn_err(CE_CONT, 4164 "\tsocket type is I/O and irq %x is %s\n", irq, 4165 (socket->IREQRouting & IRQ_ENABLE) ? 4166 "enabled" : "not enabled"); 4167 xxdmp_all_regs(pcic, socket->socket, 20); 4168 } 4169 #endif 4170 } else { 4171 /* make sure I/O mode is off */ 4172 4173 sockp->pcs_irq = 0; 4174 4175 value = pcic_getb(pcic, socket->socket, PCIC_INTERRUPT); 4176 value &= ~PCIC_IO_CARD; 4177 pcic_putb(pcic, socket->socket, PCIC_INTERRUPT, value); 4178 pcic_disable_io_intr(pcic, socket->socket); 4179 sockp->pcs_flags &= ~(PCS_CARD_IO|PCS_IRQ_ENABLED); 4180 } 4181 4182 sockp->pcs_state &= ~socket->State; 4183 4184 mutex_exit(&pcic->pc_lock); 4185 return (SUCCESS); 4186 } 4187 4188 /* 4189 * pcic_inquire_socket() 4190 * SocketServices InquireSocket function 4191 * returns basic characteristics of the socket 4192 */ 4193 /*ARGSUSED*/ 4194 static int 4195 pcic_inquire_socket(dev_info_t *dip, inquire_socket_t *socket) 4196 { 4197 anp_t *anp = ddi_get_driver_private(dip); 4198 pcicdev_t *pcic = anp->an_private; 4199 int value; 4200 4201 socket->SCIntCaps = PCIC_DEFAULT_INT_CAPS; 4202 socket->SCRptCaps = PCIC_DEFAULT_RPT_CAPS; 4203 socket->CtlIndCaps = PCIC_DEFAULT_CTL_CAPS; 4204 value = pcic->pc_sockets[socket->socket].pcs_flags; 4205 socket->SocketCaps = (value & PCS_SOCKET_IO) ? IF_IO : IF_MEMORY; 4206 socket->ActiveHigh = 0; 4207 /* these are the usable IRQs */ 4208 socket->ActiveLow = 0xfff0; 4209 return (SUCCESS); 4210 } 4211 4212 /* 4213 * pcic_inquire_window() 4214 * SocketServices InquireWindow function 4215 * returns detailed characteristics of the window 4216 * this is where windows get tied to sockets 4217 */ 4218 /*ARGSUSED*/ 4219 static int 4220 pcic_inquire_window(dev_info_t *dip, inquire_window_t *window) 4221 { 4222 int type, socket; 4223 4224 type = window->window % PCIC_NUMWINSOCK; 4225 socket = window->window / PCIC_NUMWINSOCK; 4226 4227 #if defined(PCIC_DEBUG) 4228 if (pcic_debug >= 8) 4229 cmn_err(CE_CONT, 4230 "pcic_inquire_window: window = %d/%d socket=%d\n", 4231 window->window, type, socket); 4232 #endif 4233 if (type < PCIC_IOWINDOWS) { 4234 window->WndCaps = WC_IO|WC_WAIT; 4235 type = IF_IO; 4236 } else { 4237 window->WndCaps = WC_COMMON|WC_ATTRIBUTE|WC_WAIT; 4238 type = IF_MEMORY; 4239 } 4240 4241 /* initialize the socket map - one socket per window */ 4242 PR_ZERO(window->Sockets); 4243 PR_SET(window->Sockets, socket); 4244 4245 if (type == IF_IO) { 4246 iowin_char_t *io; 4247 io = &window->iowin_char; 4248 io->IOWndCaps = WC_BASE|WC_SIZE|WC_WENABLE|WC_8BIT| 4249 WC_16BIT; 4250 io->FirstByte = (baseaddr_t)IOMEM_FIRST; 4251 io->LastByte = (baseaddr_t)IOMEM_LAST; 4252 io->MinSize = IOMEM_MIN; 4253 io->MaxSize = IOMEM_MAX; 4254 io->ReqGran = IOMEM_GRAN; 4255 io->AddrLines = IOMEM_DECODE; 4256 io->EISASlot = 0; 4257 } else { 4258 mem_win_char_t *mem; 4259 mem = &window->mem_win_char; 4260 mem->MemWndCaps = WC_BASE|WC_SIZE|WC_WENABLE|WC_8BIT| 4261 WC_16BIT|WC_WP; 4262 4263 mem->FirstByte = (baseaddr_t)MEM_FIRST; 4264 mem->LastByte = (baseaddr_t)MEM_LAST; 4265 4266 mem->MinSize = MEM_MIN; 4267 mem->MaxSize = MEM_MAX; 4268 mem->ReqGran = PCIC_PAGE; 4269 mem->ReqBase = 0; 4270 mem->ReqOffset = PCIC_PAGE; 4271 mem->Slowest = MEM_SPEED_MAX; 4272 mem->Fastest = MEM_SPEED_MIN; 4273 } 4274 return (SUCCESS); 4275 } 4276 4277 /* 4278 * pcic_get_adapter() 4279 * SocketServices GetAdapter function 4280 * this is nearly a no-op. 4281 */ 4282 /*ARGSUSED*/ 4283 static int 4284 pcic_get_adapter(dev_info_t *dip, get_adapter_t *adapt) 4285 { 4286 anp_t *anp = ddi_get_driver_private(dip); 4287 pcicdev_t *pcic = anp->an_private; 4288 4289 if (pcic->pc_flags & PCF_INTRENAB) 4290 adapt->SCRouting = IRQ_ENABLE; 4291 adapt->state = 0; 4292 return (SUCCESS); 4293 } 4294 4295 /* 4296 * pcic_get_page() 4297 * SocketServices GetPage function 4298 * returns info about the window 4299 */ 4300 /*ARGSUSED*/ 4301 static int 4302 pcic_get_page(dev_info_t *dip, get_page_t *page) 4303 { 4304 anp_t *anp = ddi_get_driver_private(dip); 4305 pcicdev_t *pcic = anp->an_private; 4306 int socket, window; 4307 pcs_memwin_t *winp; 4308 4309 socket = page->window / PCIC_NUMWINSOCK; 4310 window = page->window % PCIC_NUMWINSOCK; 4311 4312 /* I/O windows are the first two */ 4313 if (window < PCIC_IOWINDOWS || socket >= pcic->pc_numsockets) { 4314 return (BAD_WINDOW); 4315 } 4316 4317 winp = &pcic->pc_sockets[socket].pcs_windows[window].mem; 4318 4319 if (page->page != 0) 4320 return (BAD_PAGE); 4321 4322 page->state = 0; 4323 if (winp->pcw_status & PCW_ENABLED) 4324 page->state |= PS_ENABLED; 4325 if (winp->pcw_status & PCW_ATTRIBUTE) 4326 page->state |= PS_ATTRIBUTE; 4327 if (winp->pcw_status & PCW_WP) 4328 page->state |= PS_WP; 4329 4330 page->offset = (off_t)winp->pcw_offset; 4331 4332 return (SUCCESS); 4333 } 4334 4335 /* 4336 * pcic_get_socket() 4337 * SocketServices GetSocket 4338 * returns information about the current socket setting 4339 */ 4340 /*ARGSUSED*/ 4341 static int 4342 pcic_get_socket(dev_info_t *dip, get_socket_t *socket) 4343 { 4344 anp_t *anp = ddi_get_driver_private(dip); 4345 pcicdev_t *pcic = anp->an_private; 4346 int socknum, irq_enabled; 4347 pcic_socket_t *sockp; 4348 4349 socknum = socket->socket; 4350 sockp = &pcic->pc_sockets[socknum]; 4351 4352 socket->SCIntMask = sockp->pcs_intmask; 4353 sockp->pcs_state = pcic_card_state(pcic, sockp); 4354 4355 socket->state = sockp->pcs_state; 4356 if (socket->state & SBM_CD) { 4357 socket->VccLevel = sockp->pcs_vcc; 4358 socket->Vpp1Level = sockp->pcs_vpp1; 4359 socket->Vpp2Level = sockp->pcs_vpp2; 4360 irq_enabled = (sockp->pcs_flags & PCS_IRQ_ENABLED) ? 4361 IRQ_ENABLE : 0; 4362 socket->IRQRouting = sockp->pcs_irq | irq_enabled; 4363 socket->IFType = (sockp->pcs_flags & PCS_CARD_IO) ? 4364 IF_IO : IF_MEMORY; 4365 } else { 4366 socket->VccLevel = 0; 4367 socket->Vpp1Level = 0; 4368 socket->Vpp2Level = 0; 4369 socket->IRQRouting = 0; 4370 socket->IFType = IF_MEMORY; 4371 } 4372 socket->CtlInd = 0; /* no indicators */ 4373 4374 return (SUCCESS); 4375 } 4376 4377 /* 4378 * pcic_get_status() 4379 * SocketServices GetStatus 4380 * returns status information about the PC Card in 4381 * the selected socket 4382 */ 4383 /*ARGSUSED*/ 4384 static int 4385 pcic_get_status(dev_info_t *dip, get_ss_status_t *status) 4386 { 4387 anp_t *anp = ddi_get_driver_private(dip); 4388 pcicdev_t *pcic = anp->an_private; 4389 int socknum, irq_enabled; 4390 pcic_socket_t *sockp; 4391 4392 socknum = status->socket; 4393 sockp = &pcic->pc_sockets[socknum]; 4394 4395 status->CardState = pcic_card_state(pcic, sockp); 4396 status->SocketState = sockp->pcs_state; 4397 status->CtlInd = 0; /* no indicators */ 4398 4399 if (sockp->pcs_flags & PCS_CARD_PRESENT) 4400 status->SocketState |= SBM_CD; 4401 if (status->CardState & SBM_CD) { 4402 irq_enabled = (sockp->pcs_flags & PCS_CARD_ENABLED) ? 4403 IRQ_ENABLE : 0; 4404 status->IRQRouting = sockp->pcs_irq | irq_enabled; 4405 status->IFType = (sockp->pcs_flags & PCS_CARD_IO) ? 4406 IF_IO : IF_MEMORY; 4407 } else { 4408 status->IRQRouting = 0; 4409 status->IFType = IF_MEMORY; 4410 } 4411 4412 #if defined(PCIC_DEBUG) 4413 if (pcic_debug >= 8) 4414 cmn_err(CE_CONT, "pcic_get_status: socket=%d, CardState=%x," 4415 "SocketState=%x\n", 4416 socknum, status->CardState, status->SocketState); 4417 #endif 4418 switch (pcic->pc_type) { 4419 uint32_t present_state; 4420 case PCIC_TI_PCI1410: 4421 case PCIC_TI_PCI1520: 4422 case PCIC_TI_PCI1420: 4423 case PCIC_ENE_1420: 4424 case PCIC_TOSHIBA_TOPIC100: 4425 case PCIC_TOSHIBA_TOPIC95: 4426 case PCIC_TOSHIBA_VENDOR: 4427 case PCIC_O2MICRO_VENDOR: 4428 case PCIC_TI_VENDOR: 4429 case PCIC_RICOH_VENDOR: 4430 present_state = pcic_getcb(pcic, CB_PRESENT_STATE); 4431 if (present_state & PCIC_CB_CARD) 4432 status->IFType = IF_CARDBUS; 4433 #if defined(PCIC_DEBUG) 4434 if (pcic_debug >= 8) 4435 cmn_err(CE_CONT, "pcic_get_status: present_state=0x%x\n", 4436 present_state); 4437 #endif 4438 break; 4439 default: 4440 break; 4441 } 4442 4443 return (SUCCESS); 4444 } 4445 4446 /* 4447 * pcic_get_window() 4448 * SocketServices GetWindow function 4449 * returns state information about the specified window 4450 */ 4451 /*ARGSUSED*/ 4452 static int 4453 pcic_get_window(dev_info_t *dip, get_window_t *window) 4454 { 4455 anp_t *anp = ddi_get_driver_private(dip); 4456 pcicdev_t *pcic = anp->an_private; 4457 int socket, win; 4458 pcic_socket_t *sockp; 4459 pcs_memwin_t *winp; 4460 4461 socket = window->window / PCIC_NUMWINSOCK; 4462 win = window->window % PCIC_NUMWINSOCK; 4463 #if defined(PCIC_DEBUG) 4464 if (pcic_debug) { 4465 cmn_err(CE_CONT, "pcic_get_window(socket=%d, window=%d)\n", 4466 socket, win); 4467 } 4468 #endif 4469 4470 if (socket > pcic->pc_numsockets) 4471 return (BAD_WINDOW); 4472 4473 sockp = &pcic->pc_sockets[socket]; 4474 winp = &sockp->pcs_windows[win].mem; 4475 4476 window->socket = socket; 4477 window->size = winp->pcw_len; 4478 window->speed = winp->pcw_speed; 4479 window->handle = (ddi_acc_handle_t)winp->pcw_handle; 4480 window->base = (uint32_t)winp->pcw_base + winp->pcw_offset; 4481 4482 if (win >= PCIC_IOWINDOWS) { 4483 window->state = 0; 4484 } else { 4485 window->state = WS_IO; 4486 } 4487 if (winp->pcw_status & PCW_ENABLED) 4488 window->state |= WS_ENABLED; 4489 4490 if (winp->pcw_status & PCS_CARD_16BIT) 4491 window->state |= WS_16BIT; 4492 #if defined(PCIC_DEBUG) 4493 if (pcic_debug) 4494 cmn_err(CE_CONT, "\tsize=%d, speed=%d, base=%p, state=%x\n", 4495 window->size, (unsigned)window->speed, 4496 (void *)window->handle, window->state); 4497 #endif 4498 4499 return (SUCCESS); 4500 } 4501 4502 /* 4503 * pcic_ll_reset 4504 * low level reset 4505 * separated out so it can be called when already locked 4506 * 4507 * There are two variables that control the RESET timing: 4508 * pcic_prereset_time - time in mS before asserting RESET 4509 * pcic_reset_time - time in mS to assert RESET 4510 * 4511 */ 4512 int pcic_prereset_time = 1; 4513 int pcic_reset_time = 10; 4514 int pcic_postreset_time = 20; 4515 int pcic_vpp_is_vcc_during_reset = 0; 4516 4517 static int 4518 pcic_ll_reset(pcicdev_t *pcic, int socket) 4519 { 4520 int windowbits, iobits; 4521 uint32_t pwr; 4522 4523 /* save windows that were on */ 4524 windowbits = pcic_getb(pcic, socket, PCIC_MAPPING_ENABLE); 4525 if (pcic_reset_time == 0) 4526 return (windowbits); 4527 /* turn all windows off */ 4528 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, 0); 4529 4530 #if defined(PCIC_DEBUG) 4531 pcic_err(pcic->dip, 6, 4532 "pcic_ll_reset(socket %d) powerlevel=%x cbctl 0x%x cbps 0x%x\n", 4533 socket, pcic_getb(pcic, socket, PCIC_POWER_CONTROL), 4534 pcic_getcb(pcic, CB_CONTROL), 4535 pcic_getcb(pcic, CB_PRESENT_STATE)); 4536 #endif 4537 4538 if (pcic_vpp_is_vcc_during_reset) { 4539 4540 /* 4541 * Set VPP to VCC for the duration of the reset - for aironet 4542 * card. 4543 */ 4544 if (pcic->pc_flags & PCF_CBPWRCTL) { 4545 pwr = pcic_getcb(pcic, CB_CONTROL); 4546 pcic_putcb(pcic, CB_CONTROL, (pwr&~CB_C_VPPMASK)|CB_C_VPPVCC); 4547 (void) pcic_getcb(pcic, CB_CONTROL); 4548 } else { 4549 pwr = pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 4550 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, 4551 pwr | 1); 4552 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 4553 } 4554 } 4555 4556 if (pcic_prereset_time > 0) { 4557 pcic_err(pcic->dip, 8, "pcic_ll_reset pre_wait %d mS\n", 4558 pcic_prereset_time); 4559 pcic_mswait(pcic, socket, pcic_prereset_time); 4560 } 4561 4562 /* turn interrupts off and start a reset */ 4563 pcic_err(pcic->dip, 8, 4564 "pcic_ll_reset turn interrupts off and start a reset\n"); 4565 iobits = pcic_getb(pcic, socket, PCIC_INTERRUPT); 4566 iobits &= ~(PCIC_INTR_MASK | PCIC_RESET); 4567 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits); 4568 (void) pcic_getb(pcic, socket, PCIC_INTERRUPT); 4569 4570 switch (pcic->pc_type) { 4571 case PCIC_INTEL_i82092: 4572 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ, 4573 PCIC_82092_INT_DISABLE); 4574 break; 4575 default: 4576 break; 4577 } /* switch */ 4578 4579 pcic->pc_sockets[socket].pcs_state = 0; 4580 4581 if (pcic_reset_time > 0) { 4582 pcic_err(pcic->dip, 8, "pcic_ll_reset reset_wait %d mS\n", 4583 pcic_reset_time); 4584 pcic_mswait(pcic, socket, pcic_reset_time); 4585 } 4586 4587 pcic_err(pcic->dip, 8, "pcic_ll_reset take it out of reset now\n"); 4588 4589 /* take it out of RESET now */ 4590 pcic_putb(pcic, socket, PCIC_INTERRUPT, PCIC_RESET | iobits); 4591 (void) pcic_getb(pcic, socket, PCIC_INTERRUPT); 4592 4593 /* 4594 * can't access the card for 20ms, but we really don't 4595 * want to sit around that long. The pcic is still usable. 4596 * memory accesses must wait for RDY to come up. 4597 */ 4598 if (pcic_postreset_time > 0) { 4599 pcic_err(pcic->dip, 8, "pcic_ll_reset post_wait %d mS\n", 4600 pcic_postreset_time); 4601 pcic_mswait(pcic, socket, pcic_postreset_time); 4602 } 4603 4604 if (pcic_vpp_is_vcc_during_reset > 1) { 4605 4606 /* 4607 * Return VPP power to whatever it was before. 4608 */ 4609 if (pcic->pc_flags & PCF_CBPWRCTL) { 4610 pcic_putcb(pcic, CB_CONTROL, pwr); 4611 (void) pcic_getcb(pcic, CB_CONTROL); 4612 } else { 4613 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, pwr); 4614 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 4615 } 4616 } 4617 4618 pcic_err(pcic->dip, 7, "pcic_ll_reset returning 0x%x\n", windowbits); 4619 4620 return (windowbits); 4621 } 4622 4623 /* 4624 * pcic_reset_socket() 4625 * SocketServices ResetSocket function 4626 * puts the PC Card in the socket into the RESET state 4627 * and then takes it out after the the cycle time 4628 * The socket is back to initial state when done 4629 */ 4630 static int 4631 pcic_reset_socket(dev_info_t *dip, int socket, int mode) 4632 { 4633 anp_t *anp = ddi_get_driver_private(dip); 4634 pcicdev_t *pcic = anp->an_private; 4635 int value; 4636 int i, mint; 4637 pcic_socket_t *sockp; 4638 4639 #if defined(PCIC_DEBUG) 4640 if (pcic_debug >= 8) 4641 cmn_err(CE_CONT, "pcic_reset_socket(%p, %d, %d/%s)\n", 4642 (void *)dip, socket, mode, 4643 mode == RESET_MODE_FULL ? "full" : "partial"); 4644 #endif 4645 4646 mutex_enter(&pcic->pc_lock); /* protect the registers */ 4647 4648 /* Turn off management interupts. */ 4649 mint = pcic_getb(pcic, socket, PCIC_MANAGEMENT_INT); 4650 pcic_putb(pcic, socket, PCIC_MANAGEMENT_INT, mint & ~PCIC_CHANGE_MASK); 4651 4652 sockp = &pcic->pc_sockets[socket]; 4653 4654 value = pcic_ll_reset(pcic, socket); 4655 if (mode == RESET_MODE_FULL) { 4656 /* disable and unmap all mapped windows */ 4657 for (i = 0; i < PCIC_NUMWINSOCK; i++) { 4658 if (i < PCIC_IOWINDOWS) { 4659 if (sockp->pcs_windows[i].io.pcw_status & 4660 PCW_MAPPED) { 4661 pcs_iowin_t *io; 4662 io = &sockp->pcs_windows[i].io; 4663 io->pcw_status &= ~PCW_ENABLED; 4664 } 4665 } else { 4666 if (sockp->pcs_windows[i].mem.pcw_status & 4667 PCW_MAPPED) { 4668 pcs_memwin_t *mem; 4669 mem = &sockp->pcs_windows[i].mem; 4670 mem->pcw_status &= ~PCW_ENABLED; 4671 } 4672 } 4673 } 4674 } else { 4675 /* turn windows back on */ 4676 pcic_putb(pcic, socket, PCIC_MAPPING_ENABLE, value); 4677 /* wait the rest of the time here */ 4678 pcic_mswait(pcic, socket, 10); 4679 } 4680 pcic_putb(pcic, socket, PCIC_MANAGEMENT_INT, mint); 4681 mutex_exit(&pcic->pc_lock); 4682 return (SUCCESS); 4683 } 4684 4685 /* 4686 * pcic_set_interrupt() 4687 * SocketServices SetInterrupt function 4688 */ 4689 static int 4690 pcic_set_interrupt(dev_info_t *dip, set_irq_handler_t *handler) 4691 { 4692 anp_t *anp = ddi_get_driver_private(dip); 4693 pcicdev_t *pcic = anp->an_private; 4694 int value = DDI_SUCCESS; 4695 inthandler_t *intr; 4696 4697 #if defined(PCIC_DEBUG) 4698 if (pcic_debug) { 4699 cmn_err(CE_CONT, 4700 "pcic_set_interrupt: entered pc_intr_mode=0x%x\n", 4701 pcic->pc_intr_mode); 4702 cmn_err(CE_CONT, 4703 "\t irq_top=%p handler=%p handler_id=%x\n", 4704 (void *)pcic->irq_top, (void *)handler->handler, 4705 handler->handler_id); 4706 } 4707 #endif 4708 4709 /* 4710 * If we're on a PCI bus, we route all IO IRQs through a single 4711 * PCI interrupt (typically INT A#) so we don't have to do 4712 * much other than add the caller to general interrupt handler 4713 * and set some state. 4714 */ 4715 4716 intr = kmem_zalloc(sizeof (inthandler_t), KM_NOSLEEP); 4717 if (intr == NULL) 4718 return (NO_RESOURCE); 4719 4720 switch (pcic->pc_intr_mode) { 4721 case PCIC_INTR_MODE_PCI_1: 4722 /* 4723 * We only allow above-lock-level IO IRQ handlers 4724 * in the PCI bus case. 4725 */ 4726 4727 mutex_enter(&pcic->intr_lock); 4728 4729 if (pcic->irq_top == NULL) { 4730 pcic->irq_top = intr; 4731 pcic->irq_current = pcic->irq_top; 4732 } else { 4733 while (pcic->irq_current->next != NULL) 4734 pcic->irq_current = pcic->irq_current->next; 4735 pcic->irq_current->next = intr; 4736 pcic->irq_current = pcic->irq_current->next; 4737 } 4738 4739 pcic->irq_current->intr = 4740 (ddi_intr_handler_t *)handler->handler; 4741 pcic->irq_current->handler_id = handler->handler_id; 4742 pcic->irq_current->arg1 = handler->arg1; 4743 pcic->irq_current->arg2 = handler->arg2; 4744 pcic->irq_current->socket = handler->socket; 4745 4746 mutex_exit(&pcic->intr_lock); 4747 4748 handler->iblk_cookie = &pcic->pc_pri; 4749 handler->idev_cookie = &pcic->pc_dcookie; 4750 break; 4751 4752 default: 4753 intr->intr = (ddi_intr_handler_t *)handler->handler; 4754 intr->handler_id = handler->handler_id; 4755 intr->arg1 = handler->arg1; 4756 intr->arg2 = handler->arg2; 4757 intr->socket = handler->socket; 4758 intr->irq = handler->irq; 4759 4760 /* 4761 * need to revisit this to see if interrupts can be 4762 * shared someday. Note that IRQ is set in the common 4763 * code. 4764 */ 4765 mutex_enter(&pcic->pc_lock); 4766 if (pcic->pc_handlers == NULL) { 4767 pcic->pc_handlers = intr; 4768 intr->next = intr->prev = intr; 4769 } else { 4770 insque(intr, pcic->pc_handlers); 4771 } 4772 mutex_exit(&pcic->pc_lock); 4773 4774 break; 4775 } 4776 4777 /* 4778 * need to fill in cookies in event of multiple high priority 4779 * interrupt handlers on same IRQ 4780 */ 4781 4782 #if defined(PCIC_DEBUG) 4783 if (pcic_debug) { 4784 cmn_err(CE_CONT, 4785 "pcic_set_interrupt: exit irq_top=%p value=%d\n", 4786 (void *)pcic->irq_top, value); 4787 } 4788 #endif 4789 4790 if (value == DDI_SUCCESS) { 4791 return (SUCCESS); 4792 } else { 4793 return (BAD_IRQ); 4794 } 4795 } 4796 4797 /* 4798 * pcic_clear_interrupt() 4799 * SocketServices ClearInterrupt function 4800 * 4801 * Interrupts for PCIC are complicated by the fact that we must 4802 * follow several different models for interrupts. 4803 * ISA: there is an interrupt per adapter and per socket and 4804 * they can't be shared. 4805 * PCI: some adapters have one PCI interrupt available while others 4806 * have up to 4. Solaris may or may not allow us to use more 4807 * than 1 so we essentially share them all at this point. 4808 * Hybrid: PCI bridge but interrupts wired to host interrupt controller. 4809 * This is like ISA but we have to fudge and create an intrspec 4810 * that PCI's parent understands and bypass the PCI nexus. 4811 * multifunction: this requires sharing the interrupts on a per-socket 4812 * basis. 4813 */ 4814 static int 4815 pcic_clear_interrupt(dev_info_t *dip, clear_irq_handler_t *handler) 4816 { 4817 anp_t *anp = ddi_get_driver_private(dip); 4818 pcicdev_t *pcic = anp->an_private; 4819 inthandler_t *intr, *prev, *current; 4820 int i; 4821 4822 /* 4823 * If we're on a PCI bus, we route all IO IRQs through a single 4824 * PCI interrupt (typically INT A#) so we don't have to do 4825 * much other than remove the caller from the general 4826 * interrupt handler callout list. 4827 */ 4828 4829 #if defined(PCIC_DEBUG) 4830 if (pcic_debug) { 4831 cmn_err(CE_CONT, 4832 "pcic_clear_interrupt: entered pc_intr_mode=0x%x\n", 4833 pcic->pc_intr_mode); 4834 cmn_err(CE_CONT, 4835 "\t irq_top=%p handler=%p handler_id=%x\n", 4836 (void *)pcic->irq_top, (void *)handler->handler, 4837 handler->handler_id); 4838 } 4839 #endif 4840 4841 switch (pcic->pc_intr_mode) { 4842 case PCIC_INTR_MODE_PCI_1: 4843 4844 mutex_enter(&pcic->intr_lock); 4845 if (pcic->irq_top == NULL) { 4846 mutex_exit(&pcic->intr_lock); 4847 return (BAD_IRQ); 4848 } 4849 4850 intr = NULL; 4851 pcic->irq_current = pcic->irq_top; 4852 4853 while ((pcic->irq_current != NULL) && 4854 (pcic->irq_current->handler_id != 4855 handler->handler_id)) { 4856 intr = pcic->irq_current; 4857 pcic->irq_current = pcic->irq_current->next; 4858 } 4859 4860 if (pcic->irq_current == NULL) { 4861 mutex_exit(&pcic->intr_lock); 4862 return (BAD_IRQ); 4863 } 4864 4865 if (intr != NULL) { 4866 intr->next = pcic->irq_current->next; 4867 } else { 4868 pcic->irq_top = pcic->irq_current->next; 4869 } 4870 4871 current = pcic->irq_current; 4872 pcic->irq_current = pcic->irq_top; 4873 mutex_exit(&pcic->intr_lock); 4874 kmem_free(current, sizeof (inthandler_t)); 4875 4876 break; 4877 4878 default: 4879 4880 mutex_enter(&pcic->pc_lock); 4881 intr = pcic_handlers; 4882 prev = (inthandler_t *)&pcic_handlers; 4883 4884 while (intr != NULL) { 4885 if (intr->handler_id == handler->handler_id) { 4886 i = intr->irq & PCIC_INTR_MASK; 4887 if (--pcic_irq_map[i].count == 0) { 4888 /* multi-handler form */ 4889 (void) ddi_intr_disable(pcic->pc_intr_htblp[i]); 4890 (void) ddi_intr_remove_handler( 4891 pcic->pc_intr_htblp[i]); 4892 (void) ddi_intr_free(pcic->pc_intr_htblp[i]); 4893 (void) pcmcia_return_intr(pcic->dip, i); 4894 #if defined(PCIC_DEBUG) 4895 if (pcic_debug) { 4896 cmn_err(CE_CONT, 4897 "removing interrupt %d at %s " 4898 "priority\n", i, "high"); 4899 cmn_err(CE_CONT, 4900 "ddi_remove_intr(%p, %x, %p)\n", 4901 (void *)dip, 4902 0, 4903 (void *)intr->iblk_cookie); 4904 } 4905 #endif 4906 } 4907 prev->next = intr->next; 4908 kmem_free(intr, sizeof (inthandler_t)); 4909 intr = prev->next; 4910 } else { 4911 prev = intr; 4912 intr = intr->next; 4913 } /* if (handler_id) */ 4914 } /* while */ 4915 4916 mutex_exit(&pcic->pc_lock); 4917 } 4918 4919 #if defined(PCIC_DEBUG) 4920 if (pcic_debug) { 4921 cmn_err(CE_CONT, 4922 "pcic_clear_interrupt: exit irq_top=%p\n", 4923 (void *)pcic->irq_top); 4924 } 4925 #endif 4926 4927 4928 return (SUCCESS); 4929 } 4930 4931 struct intel_regs { 4932 char *name; 4933 int off; 4934 char *fmt; 4935 } iregs[] = { 4936 {"ident ", 0}, 4937 {"if-status ", 1, "\020\1BVD1\2BVD2\3CD1\4CD2\5WP\6RDY\7PWR\10~GPI"}, 4938 {"power ", 2, "\020\1Vpp1c0\2Vpp1c1\3Vpp2c0\4Vpp2c1\5PE\6AUTO" 4939 "\7DRD\10OE"}, 4940 {"cardstatus", 4, "\020\1BD\2BW\3RC\4CD\5GPI\6R1\7R2\010R3"}, 4941 {"enable ", 6, "\020\1MW0\2MW1\3MW2\4MW3\5MW4\6MEM16\7IO0\10IO1"}, 4942 {"cd-gcr ", 0x16, "\020\1MDI16\2CRE\3GPIE\4GPIT\5CDR\6S/W"}, 4943 {"GCR ", 0x1e, "\020\1PD\2LEVEL\3WCSC\4PLS14"}, 4944 {"int-gcr ", 3, "\020\5INTR\6IO\7~RST\10RI"}, 4945 {"management", 5, "\020\1BDE\2BWE\3RE\4CDE"}, 4946 {"volt-sense", 0x1f, "\020\1A_VS1\2A_VS2\3B_VS1\4B_VS2"}, 4947 {"volt-sel ", 0x2f, "\020\5EXTCONF\6BUSSELECT\7MIXEDV\10ISAV"}, 4948 {"VG ext A ", 0x3c, "\20\3IVS\4CABLE\5CSTEP\6TEST\7RIO"}, 4949 {"io-ctrl ", 7, "\020\1DS0\2IOCS0\3ZWS0\4WS0\5DS1\6IOS1\7ZWS1\10WS1"}, 4950 {"io0-slow ", 8}, 4951 {"io0-shi ", 9}, 4952 {"io0-elow ", 0xa}, 4953 {"io0-ehi ", 0xb}, 4954 {"io1-slow ", 0xc}, 4955 {"io1-shi ", 0xd}, 4956 {"io1-elow ", 0xe}, 4957 {"io1-ehi ", 0xf}, 4958 {"mem0-slow ", 0x10}, 4959 {"mem0-shi ", 0x11, "\020\7ZW\10DS"}, 4960 {"mem0-elow ", 0x12}, 4961 {"mem0-ehi ", 0x13, "\020\7WS0\10WS1"}, 4962 {"card0-low ", 0x14}, 4963 {"card0-hi ", 0x15, "\020\7AM\10WP"}, 4964 {"mem1-slow ", 0x18}, 4965 {"mem1-shi ", 0x19, "\020\7ZW\10DS"}, 4966 {"mem1-elow ", 0x1a}, 4967 {"mem1-ehi ", 0x1b, "\020\7WS0\10WS1"}, 4968 {"card1-low ", 0x1c}, 4969 {"card1-hi ", 0x1d, "\020\7AM\10WP"}, 4970 {"mem2-slow ", 0x20}, 4971 {"mem2-shi ", 0x21, "\020\7ZW\10DS"}, 4972 {"mem2-elow ", 0x22}, 4973 {"mem2-ehi ", 0x23, "\020\7WS0\10WS1"}, 4974 {"card2-low ", 0x24}, 4975 {"card2-hi ", 0x25, "\020\7AM\10WP"}, 4976 {"mem3-slow ", 0x28}, 4977 {"mem3-shi ", 0x29, "\020\7ZW\10DS"}, 4978 {"mem3-elow ", 0x2a}, 4979 {"mem3-ehi ", 0x2b, "\020\7WS0\10WS1"}, 4980 {"card3-low ", 0x2c}, 4981 {"card3-hi ", 0x2d, "\020\7AM\10WP"}, 4982 4983 {"mem4-slow ", 0x30}, 4984 {"mem4-shi ", 0x31, "\020\7ZW\10DS"}, 4985 {"mem4-elow ", 0x32}, 4986 {"mem4-ehi ", 0x33, "\020\7WS0\10WS1"}, 4987 {"card4-low ", 0x34}, 4988 {"card4-hi ", 0x35, "\020\7AM\10WP"}, 4989 {"mpage0 ", 0x40}, 4990 {"mpage1 ", 0x41}, 4991 {"mpage2 ", 0x42}, 4992 {"mpage3 ", 0x43}, 4993 {"mpage4 ", 0x44}, 4994 {NULL}, 4995 }; 4996 4997 static struct intel_regs cregs[] = { 4998 {"misc-ctl1 ", 0x16, "\20\2VCC3\3PMI\4PSI\5SPKR\10INPACK"}, 4999 {"fifo ", 0x17, "\20\6DIOP\7DMEMP\10EMPTY"}, 5000 {"misc-ctl2 ", 0x1e, "\20\1XCLK\2LOW\3SUSP\4CORE5V\5TCD\10RIOUT"}, 5001 {"chip-info ", 0x1f, "\20\6DUAL"}, 5002 {"IO-offlow0", 0x36}, 5003 {"IO-offhi0 ", 0x37}, 5004 {"IO-offlow1", 0x38}, 5005 {"IO-offhi1 ", 0x39}, 5006 NULL, 5007 }; 5008 5009 static struct intel_regs cxregs[] = { 5010 {"ext-ctl-1 ", 0x03, 5011 "\20\1VCCLCK\2AUTOCLR\3LED\4INVIRQC\5INVIRQM\6PUC"}, 5012 {"misc-ctl3 ", 0x25, "\20\5HWSUSP"}, 5013 {"mem0-up ", 0x05}, 5014 {"mem1-up ", 0x06}, 5015 {"mem2-up ", 0x07}, 5016 {"mem3-up ", 0x08}, 5017 {"mem4-up ", 0x09}, 5018 {NULL} 5019 }; 5020 5021 void 5022 xxdmp_cl_regs(pcicdev_t *pcic, int socket, uint32_t len) 5023 { 5024 int i, value, j; 5025 char buff[256]; 5026 char *fmt; 5027 5028 cmn_err(CE_CONT, "--------- Cirrus Logic Registers --------\n"); 5029 for (buff[0] = '\0', i = 0; cregs[i].name != NULL && len-- != 0; i++) { 5030 int sval; 5031 if (cregs[i].off == PCIC_MISC_CTL_2) 5032 sval = 0; 5033 else 5034 sval = socket; 5035 value = pcic_getb(pcic, sval, cregs[i].off); 5036 if (i & 1) { 5037 if (cregs[i].fmt) 5038 fmt = "%s\t%s\t%b\n"; 5039 else 5040 fmt = "%s\t%s\t%x\n"; 5041 cmn_err(CE_CONT, fmt, buff, 5042 cregs[i].name, value, cregs[i].fmt); 5043 buff[0] = '\0'; 5044 } else { 5045 if (cregs[i].fmt) 5046 fmt = "\t%s\t%b"; 5047 else 5048 fmt = "\t%s\t%x"; 5049 (void) sprintf(buff, fmt, 5050 cregs[i].name, value, cregs[i].fmt); 5051 for (j = strlen(buff); j < 40; j++) 5052 buff[j] = ' '; 5053 buff[40] = '\0'; 5054 } 5055 } 5056 cmn_err(CE_CONT, "%s\n", buff); 5057 5058 i = pcic_getb(pcic, socket, PCIC_TIME_SETUP_0); 5059 j = pcic_getb(pcic, socket, PCIC_TIME_SETUP_1); 5060 cmn_err(CE_CONT, "\tsetup-tim0\t%x\tsetup-tim1\t%x\n", i, j); 5061 5062 i = pcic_getb(pcic, socket, PCIC_TIME_COMMAND_0); 5063 j = pcic_getb(pcic, socket, PCIC_TIME_COMMAND_1); 5064 cmn_err(CE_CONT, "\tcmd-tim0 \t%x\tcmd-tim1 \t%x\n", i, j); 5065 5066 i = pcic_getb(pcic, socket, PCIC_TIME_RECOVER_0); 5067 j = pcic_getb(pcic, socket, PCIC_TIME_RECOVER_1); 5068 cmn_err(CE_CONT, "\trcvr-tim0 \t%x\trcvr-tim1 \t%x\n", i, j); 5069 5070 cmn_err(CE_CONT, "--------- Extended Registers --------\n"); 5071 5072 for (buff[0] = '\0', i = 0; cxregs[i].name != NULL && len-- != 0; i++) { 5073 value = clext_reg_read(pcic, socket, cxregs[i].off); 5074 if (i & 1) { 5075 if (cxregs[i].fmt) 5076 fmt = "%s\t%s\t%b\n"; 5077 else 5078 fmt = "%s\t%s\t%x\n"; 5079 cmn_err(CE_CONT, fmt, buff, 5080 cxregs[i].name, value, cxregs[i].fmt); 5081 buff[0] = '\0'; 5082 } else { 5083 if (cxregs[i].fmt) 5084 fmt = "\t%s\t%b"; 5085 else 5086 fmt = "\t%s\t%x"; 5087 (void) sprintf(buff, fmt, 5088 cxregs[i].name, value, cxregs[i].fmt); 5089 for (j = strlen(buff); j < 40; j++) 5090 buff[j] = ' '; 5091 buff[40] = '\0'; 5092 } 5093 } 5094 } 5095 5096 #if defined(PCIC_DEBUG) 5097 static void 5098 xxdmp_all_regs(pcicdev_t *pcic, int socket, uint32_t len) 5099 { 5100 int i, value, j; 5101 char buff[256]; 5102 char *fmt; 5103 5104 #if defined(PCIC_DEBUG) 5105 if (pcic_debug < 2) 5106 return; 5107 #endif 5108 cmn_err(CE_CONT, 5109 "----------- PCIC Registers for socket %d---------\n", 5110 socket); 5111 cmn_err(CE_CONT, 5112 "\tname value name value\n"); 5113 5114 for (buff[0] = '\0', i = 0; iregs[i].name != NULL && len-- != 0; i++) { 5115 value = pcic_getb(pcic, socket, iregs[i].off); 5116 if (i & 1) { 5117 if (iregs[i].fmt) 5118 fmt = "%s\t%s\t%b\n"; 5119 else 5120 fmt = "%s\t%s\t%x\n"; 5121 cmn_err(CE_CONT, fmt, buff, 5122 iregs[i].name, value, iregs[i].fmt); 5123 buff[0] = '\0'; 5124 } else { 5125 if (iregs[i].fmt) 5126 fmt = "\t%s\t%b"; 5127 else 5128 fmt = "\t%s\t%x"; 5129 (void) sprintf(buff, fmt, 5130 iregs[i].name, value, iregs[i].fmt); 5131 for (j = strlen(buff); j < 40; j++) 5132 buff[j] = ' '; 5133 buff[40] = '\0'; 5134 } 5135 } 5136 switch (pcic->pc_type) { 5137 case PCIC_CL_PD6710: 5138 case PCIC_CL_PD6722: 5139 case PCIC_CL_PD6729: 5140 case PCIC_CL_PD6832: 5141 (void) xxdmp_cl_regs(pcic, socket, 0xFFFF); 5142 break; 5143 } 5144 cmn_err(CE_CONT, "%s\n", buff); 5145 } 5146 #endif 5147 5148 /* 5149 * pcic_mswait(ms) 5150 * sleep ms milliseconds 5151 * call drv_usecwait once for each ms 5152 */ 5153 static void 5154 pcic_mswait(pcicdev_t *pcic, int socket, int ms) 5155 { 5156 if (ms) { 5157 pcic->pc_sockets[socket].pcs_flags |= PCS_WAITING; 5158 pcic_mutex_exit(&pcic->pc_lock); 5159 delay(drv_usectohz(ms*1000)); 5160 pcic_mutex_enter(&pcic->pc_lock); 5161 pcic->pc_sockets[socket].pcs_flags &= ~PCS_WAITING; 5162 } 5163 } 5164 5165 /* 5166 * pcic_check_ready(pcic, index, off) 5167 * Wait for card to come ready 5168 * We only wait if the card is NOT in RESET 5169 * and power is on. 5170 */ 5171 static boolean_t 5172 pcic_check_ready(pcicdev_t *pcic, int socket) 5173 { 5174 int ifstate, intstate; 5175 5176 intstate = pcic_getb(pcic, socket, PCIC_INTERRUPT); 5177 ifstate = pcic_getb(pcic, socket, PCIC_INTERFACE_STATUS); 5178 5179 if ((intstate & PCIC_RESET) && 5180 ((ifstate & (PCIC_READY|PCIC_POWER_ON|PCIC_ISTAT_CD_MASK)) == 5181 (PCIC_READY|PCIC_POWER_ON|PCIC_CD_PRESENT_OK))) 5182 return (B_TRUE); 5183 5184 #ifdef PCIC_DEBUG 5185 pcic_err(NULL, 5, "pcic_check_read: Card not ready, intstate = 0x%x, " 5186 "ifstate = 0x%x\n", intstate, ifstate); 5187 if (pcic_debug) { 5188 pcic_debug += 4; 5189 xxdmp_all_regs(pcic, socket, -1); 5190 pcic_debug -= 4; 5191 } 5192 #endif 5193 return (B_FALSE); 5194 } 5195 5196 /* 5197 * Cirrus Logic extended register read/write routines 5198 */ 5199 static int 5200 clext_reg_read(pcicdev_t *pcic, int sn, uchar_t ext_reg) 5201 { 5202 int val; 5203 5204 switch (pcic->pc_io_type) { 5205 case PCIC_IO_TYPE_YENTA: 5206 val = ddi_get8(pcic->handle, 5207 pcic->ioaddr + CB_CLEXT_OFFSET + ext_reg); 5208 break; 5209 default: 5210 pcic_putb(pcic, sn, PCIC_CL_EXINDEX, ext_reg); 5211 val = pcic_getb(pcic, sn, PCIC_CL_EXINDEX + 1); 5212 break; 5213 } 5214 5215 return (val); 5216 } 5217 5218 static void 5219 clext_reg_write(pcicdev_t *pcic, int sn, uchar_t ext_reg, uchar_t value) 5220 { 5221 switch (pcic->pc_io_type) { 5222 case PCIC_IO_TYPE_YENTA: 5223 ddi_put8(pcic->handle, 5224 pcic->ioaddr + CB_CLEXT_OFFSET + ext_reg, value); 5225 break; 5226 default: 5227 pcic_putb(pcic, sn, PCIC_CL_EXINDEX, ext_reg); 5228 pcic_putb(pcic, sn, PCIC_CL_EXINDEX + 1, value); 5229 break; 5230 } 5231 } 5232 5233 /* 5234 * Misc PCI functions 5235 */ 5236 static void 5237 pcic_iomem_pci_ctl(ddi_acc_handle_t handle, uchar_t *cfgaddr, unsigned flags) 5238 { 5239 unsigned cmd; 5240 5241 if (flags & (PCIC_ENABLE_IO | PCIC_ENABLE_MEM)) { 5242 cmd = ddi_get16(handle, (ushort_t *)(cfgaddr + 4)); 5243 if ((cmd & (PCI_COMM_IO|PCI_COMM_MAE)) == 5244 (PCI_COMM_IO|PCI_COMM_MAE)) 5245 return; 5246 5247 if (flags & PCIC_ENABLE_IO) 5248 cmd |= PCI_COMM_IO; 5249 5250 if (flags & PCIC_ENABLE_MEM) 5251 cmd |= PCI_COMM_MAE; 5252 5253 ddi_put16(handle, (ushort_t *)(cfgaddr + 4), cmd); 5254 } /* if (PCIC_ENABLE_IO | PCIC_ENABLE_MEM) */ 5255 } 5256 5257 /* 5258 * pcic_find_pci_type - Find and return PCI-PCMCIA adapter type 5259 */ 5260 static int 5261 pcic_find_pci_type(pcicdev_t *pcic) 5262 { 5263 uint32_t vend, device; 5264 5265 vend = ddi_getprop(DDI_DEV_T_ANY, pcic->dip, 5266 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 5267 "vendor-id", -1); 5268 device = ddi_getprop(DDI_DEV_T_ANY, pcic->dip, 5269 DDI_PROP_CANSLEEP|DDI_PROP_DONTPASS, 5270 "device-id", -1); 5271 5272 device = PCI_ID(vend, device); 5273 pcic->pc_type = device; 5274 pcic->pc_chipname = "PCI:unknown"; 5275 5276 switch (device) { 5277 case PCIC_INTEL_i82092: 5278 pcic->pc_chipname = PCIC_TYPE_i82092; 5279 break; 5280 case PCIC_CL_PD6729: 5281 pcic->pc_chipname = PCIC_TYPE_PD6729; 5282 /* 5283 * Some 6730's incorrectly identify themselves 5284 * as a 6729, so we need to do some more tests 5285 * here to see if the device that's claiming 5286 * to be a 6729 is really a 6730. 5287 */ 5288 if ((clext_reg_read(pcic, 0, PCIC_CLEXT_MISC_CTL_3) & 5289 PCIC_CLEXT_MISC_CTL_3_REV_MASK) == 5290 0) { 5291 pcic->pc_chipname = PCIC_TYPE_PD6730; 5292 pcic->pc_type = PCIC_CL_PD6730; 5293 } 5294 break; 5295 case PCIC_CL_PD6730: 5296 pcic->pc_chipname = PCIC_TYPE_PD6730; 5297 break; 5298 case PCIC_CL_PD6832: 5299 pcic->pc_chipname = PCIC_TYPE_PD6832; 5300 break; 5301 case PCIC_SMC_34C90: 5302 pcic->pc_chipname = PCIC_TYPE_34C90; 5303 break; 5304 case PCIC_TOSHIBA_TOPIC95: 5305 pcic->pc_chipname = PCIC_TYPE_TOPIC95; 5306 break; 5307 case PCIC_TOSHIBA_TOPIC100: 5308 pcic->pc_chipname = PCIC_TYPE_TOPIC100; 5309 break; 5310 case PCIC_TI_PCI1031: 5311 pcic->pc_chipname = PCIC_TYPE_PCI1031; 5312 break; 5313 case PCIC_TI_PCI1130: 5314 pcic->pc_chipname = PCIC_TYPE_PCI1130; 5315 break; 5316 case PCIC_TI_PCI1131: 5317 pcic->pc_chipname = PCIC_TYPE_PCI1131; 5318 break; 5319 case PCIC_TI_PCI1250: 5320 pcic->pc_chipname = PCIC_TYPE_PCI1250; 5321 break; 5322 case PCIC_TI_PCI1225: 5323 pcic->pc_chipname = PCIC_TYPE_PCI1225; 5324 break; 5325 case PCIC_TI_PCI1410: 5326 pcic->pc_chipname = PCIC_TYPE_PCI1410; 5327 break; 5328 case PCIC_TI_PCI1510: 5329 pcic->pc_chipname = PCIC_TYPE_PCI1510; 5330 break; 5331 case PCIC_TI_PCI1520: 5332 pcic->pc_chipname = PCIC_TYPE_PCI1520; 5333 break; 5334 case PCIC_TI_PCI1221: 5335 pcic->pc_chipname = PCIC_TYPE_PCI1221; 5336 break; 5337 case PCIC_TI_PCI1050: 5338 pcic->pc_chipname = PCIC_TYPE_PCI1050; 5339 break; 5340 case PCIC_ENE_1410: 5341 pcic->pc_chipname = PCIC_TYPE_1410; 5342 break; 5343 case PCIC_O2_OZ6912: 5344 pcic->pc_chipname = PCIC_TYPE_OZ6912; 5345 break; 5346 case PCIC_RICOH_RL5C466: 5347 pcic->pc_chipname = PCIC_TYPE_RL5C466; 5348 break; 5349 case PCIC_TI_PCI1420: 5350 pcic->pc_chipname = PCIC_TYPE_PCI1420; 5351 break; 5352 case PCIC_ENE_1420: 5353 pcic->pc_chipname = PCIC_TYPE_1420; 5354 break; 5355 default: 5356 switch (PCI_ID(vend, (uint32_t)0)) { 5357 case PCIC_TOSHIBA_VENDOR: 5358 pcic->pc_chipname = PCIC_TYPE_TOSHIBA; 5359 pcic->pc_type = PCIC_TOSHIBA_VENDOR; 5360 break; 5361 case PCIC_TI_VENDOR: 5362 pcic->pc_chipname = PCIC_TYPE_TI; 5363 pcic->pc_type = PCIC_TI_VENDOR; 5364 break; 5365 case PCIC_O2MICRO_VENDOR: 5366 pcic->pc_chipname = PCIC_TYPE_O2MICRO; 5367 pcic->pc_type = PCIC_O2MICRO_VENDOR; 5368 break; 5369 case PCIC_RICOH_VENDOR: 5370 pcic->pc_chipname = PCIC_TYPE_RICOH; 5371 pcic->pc_type = PCIC_RICOH_VENDOR; 5372 break; 5373 default: 5374 if (!(pcic->pc_flags & PCF_CARDBUS)) 5375 return (DDI_FAILURE); 5376 pcic->pc_chipname = PCIC_TYPE_YENTA; 5377 break; 5378 } 5379 } 5380 return (DDI_SUCCESS); 5381 } 5382 5383 static void 5384 pcic_82092_smiirq_ctl(pcicdev_t *pcic, int socket, int intr, int state) 5385 { 5386 uchar_t ppirr = ddi_get8(pcic->cfg_handle, 5387 pcic->cfgaddr + PCIC_82092_PPIRR); 5388 uchar_t val; 5389 5390 if (intr == PCIC_82092_CTL_SMI) { 5391 val = PCIC_82092_SMI_CTL(socket, 5392 PCIC_82092_INT_DISABLE); 5393 ppirr &= ~val; 5394 val = PCIC_82092_SMI_CTL(socket, state); 5395 ppirr |= val; 5396 } else { 5397 val = PCIC_82092_IRQ_CTL(socket, 5398 PCIC_82092_INT_DISABLE); 5399 ppirr &= ~val; 5400 val = PCIC_82092_IRQ_CTL(socket, state); 5401 ppirr |= val; 5402 } 5403 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + PCIC_82092_PPIRR, 5404 ppirr); 5405 } 5406 5407 static uint_t 5408 pcic_cd_softint(caddr_t arg1, caddr_t arg2) 5409 { 5410 pcic_socket_t *sockp = (pcic_socket_t *)arg1; 5411 uint_t rc = DDI_INTR_UNCLAIMED; 5412 5413 _NOTE(ARGUNUSED(arg2)) 5414 5415 mutex_enter(&sockp->pcs_pcic->pc_lock); 5416 if (sockp->pcs_cd_softint_flg) { 5417 uint8_t status; 5418 sockp->pcs_cd_softint_flg = 0; 5419 rc = DDI_INTR_CLAIMED; 5420 status = pcic_getb(sockp->pcs_pcic, sockp->pcs_socket, 5421 PCIC_INTERFACE_STATUS); 5422 pcic_handle_cd_change(sockp->pcs_pcic, sockp, status); 5423 } 5424 mutex_exit(&sockp->pcs_pcic->pc_lock); 5425 return (rc); 5426 } 5427 5428 int pcic_debounce_cnt = PCIC_REM_DEBOUNCE_CNT; 5429 int pcic_debounce_intr_time = PCIC_REM_DEBOUNCE_TIME; 5430 int pcic_debounce_cnt_ok = PCIC_DEBOUNCE_OK_CNT; 5431 5432 #ifdef CARDBUS 5433 static uint32_t pcic_cbps_on = 0; 5434 static uint32_t pcic_cbps_off = CB_PS_NOTACARD | CB_PS_CCDMASK | 5435 CB_PS_XVCARD | CB_PS_YVCARD; 5436 #else 5437 static uint32_t pcic_cbps_on = CB_PS_16BITCARD; 5438 static uint32_t pcic_cbps_off = CB_PS_NOTACARD | CB_PS_CCDMASK | 5439 CB_PS_CBCARD | 5440 CB_PS_XVCARD | CB_PS_YVCARD; 5441 #endif 5442 static void 5443 pcic_handle_cd_change(pcicdev_t *pcic, pcic_socket_t *sockp, uint8_t status) 5444 { 5445 boolean_t do_debounce = B_FALSE; 5446 int debounce_time = drv_usectohz(pcic_debounce_time); 5447 uint8_t irq; 5448 timeout_id_t debounce; 5449 5450 /* 5451 * Always reset debounce but may need to check original state later. 5452 */ 5453 debounce = sockp->pcs_debounce_id; 5454 sockp->pcs_debounce_id = 0; 5455 5456 /* 5457 * Check to see whether a card is present or not. There are 5458 * only two states that we are concerned with - the state 5459 * where both CD pins are asserted, which means that the 5460 * card is fully seated, and the state where neither CD 5461 * pin is asserted, which means that the card is not 5462 * present. 5463 * The CD signals are generally very noisy and cause a lot of 5464 * contact bounce as the card is being inserted and 5465 * removed, so we need to do some software debouncing. 5466 */ 5467 5468 #ifdef PCIC_DEBUG 5469 pcic_err(pcic->dip, 6, 5470 "pcic%d handle_cd_change: socket %d card status 0x%x" 5471 " deb 0x%p\n", ddi_get_instance(pcic->dip), 5472 sockp->pcs_socket, status, debounce); 5473 #endif 5474 switch (status & PCIC_ISTAT_CD_MASK) { 5475 case PCIC_CD_PRESENT_OK: 5476 sockp->pcs_flags &= ~(PCS_CARD_REMOVED|PCS_CARD_CBREM); 5477 if (!(sockp->pcs_flags & PCS_CARD_PRESENT)) { 5478 uint32_t cbps; 5479 #ifdef PCIC_DEBUG 5480 pcic_err(pcic->dip, 8, "New card (0x%x)\n", sockp->pcs_flags); 5481 #endif 5482 cbps = pcic_getcb(pcic, CB_PRESENT_STATE); 5483 #ifdef PCIC_DEBUG 5484 pcic_err(pcic->dip, 8, "CBus PS (0x%x)\n", cbps); 5485 #endif 5486 /* 5487 * Check the CB bits are sane. 5488 */ 5489 if ((cbps & pcic_cbps_on) != pcic_cbps_on || 5490 cbps & pcic_cbps_off) { 5491 cmn_err(CE_WARN, 5492 "%s%d: Odd Cardbus Present State 0x%x\n", 5493 ddi_get_name(pcic->dip), 5494 ddi_get_instance(pcic->dip), 5495 cbps); 5496 pcic_putcb(pcic, CB_EVENT_FORCE, CB_EF_CVTEST); 5497 debounce = 0; 5498 debounce_time = drv_usectohz(1000000); 5499 } 5500 if (debounce) { 5501 sockp->pcs_flags |= PCS_CARD_PRESENT; 5502 if (pcic_do_insertion) { 5503 5504 cbps = pcic_getcb(pcic, CB_PRESENT_STATE); 5505 5506 if (cbps & CB_PS_16BITCARD) { 5507 pcic_err(pcic->dip, 8, "16 bit card inserted\n"); 5508 sockp->pcs_flags |= PCS_CARD_IS16BIT; 5509 /* calls pcm_adapter_callback() */ 5510 if (pcic->pc_callback) { 5511 5512 (void) ddi_prop_update_string(DDI_DEV_T_NONE, 5513 pcic->dip, PCM_DEVICETYPE, 5514 "pccard"); 5515 PC_CALLBACK(pcic->dip, pcic->pc_cb_arg, 5516 PCE_CARD_INSERT, 5517 sockp->pcs_socket); 5518 } 5519 } else if (cbps & CB_PS_CBCARD) { 5520 pcic_err(pcic->dip, 8, "32 bit card inserted\n"); 5521 5522 if (pcic->pc_flags & PCF_CARDBUS) { 5523 sockp->pcs_flags |= PCS_CARD_ISCARDBUS; 5524 #ifdef CARDBUS 5525 if (!pcic_load_cardbus(pcic, sockp)) { 5526 pcic_unload_cardbus(pcic, sockp); 5527 } 5528 5529 #else 5530 cmn_err(CE_NOTE, 5531 "32 bit Cardbus not supported in" 5532 " this device driver\n"); 5533 #endif 5534 } else { 5535 /* 5536 * Ignore the card 5537 */ 5538 cmn_err(CE_NOTE, 5539 "32 bit Cardbus not supported on this" 5540 " device\n"); 5541 } 5542 } else { 5543 cmn_err(CE_NOTE, 5544 "Unsupported PCMCIA card inserted\n"); 5545 } 5546 } 5547 syshw_send_signal(sockp->pcs_syshwsig); 5548 } else { 5549 do_debounce = B_TRUE; 5550 } 5551 } else { 5552 /* 5553 * It is possible to come through here if the system 5554 * starts up with cards already inserted. Do nothing 5555 * and don't worry about it. 5556 */ 5557 #ifdef PCIC_DEBUG 5558 pcic_err(pcic->dip, 5, 5559 "pcic%d: Odd card insertion indication on socket %d\n", 5560 ddi_get_instance(pcic->dip), 5561 sockp->pcs_socket); 5562 #endif 5563 } 5564 break; 5565 5566 default: 5567 if (!(sockp->pcs_flags & PCS_CARD_PRESENT)) { 5568 /* 5569 * Someone has started to insert a card so delay a while. 5570 */ 5571 do_debounce = B_TRUE; 5572 break; 5573 } 5574 /* 5575 * Otherwise this is basically the same as not present 5576 * so fall through. 5577 */ 5578 5579 /* FALLTHRU */ 5580 case 0: 5581 if (sockp->pcs_flags & PCS_CARD_PRESENT) { 5582 if (pcic->pc_flags & PCF_CBPWRCTL) { 5583 pcic_putcb(pcic, CB_CONTROL, 0); 5584 } else { 5585 pcic_putb(pcic, sockp->pcs_socket, PCIC_POWER_CONTROL, 0); 5586 (void) pcic_getb(pcic, sockp->pcs_socket, 5587 PCIC_POWER_CONTROL); 5588 } 5589 #ifdef PCIC_DEBUG 5590 pcic_err(pcic->dip, 8, "Card removed\n"); 5591 #endif 5592 sockp->pcs_flags &= ~PCS_CARD_PRESENT; 5593 5594 if (sockp->pcs_flags & PCS_CARD_IS16BIT) { 5595 sockp->pcs_flags &= ~PCS_CARD_IS16BIT; 5596 if (pcic_do_removal && pcic->pc_callback) { 5597 PC_CALLBACK(pcic->dip, pcic->pc_cb_arg, 5598 PCE_CARD_REMOVAL, sockp->pcs_socket); 5599 } 5600 } 5601 if (sockp->pcs_flags & PCS_CARD_ISCARDBUS) { 5602 sockp->pcs_flags &= ~PCS_CARD_ISCARDBUS; 5603 sockp->pcs_flags |= PCS_CARD_CBREM; 5604 } 5605 sockp->pcs_flags |= PCS_CARD_REMOVED; 5606 5607 do_debounce = B_TRUE; 5608 } 5609 if (debounce && (sockp->pcs_flags & PCS_CARD_REMOVED)) { 5610 if (sockp->pcs_flags & PCS_CARD_CBREM) { 5611 /* 5612 * Ensure that we do the unloading in the 5613 * debounce handler, that way we're not doing 5614 * nasty things in an interrupt handler. e.g. 5615 * a USB device will wait for data which will 5616 * obviously never come because we've 5617 * unplugged the device, but the wait will 5618 * wait forever because no interrupts can 5619 * come in... 5620 */ 5621 #ifdef CARDBUS 5622 pcic_unload_cardbus(pcic, sockp); 5623 /* pcic_dump_all(pcic); */ 5624 #endif 5625 sockp->pcs_flags &= ~PCS_CARD_CBREM; 5626 } 5627 syshw_send_signal(sockp->pcs_syshwsig); 5628 sockp->pcs_flags &= ~PCS_CARD_REMOVED; 5629 } 5630 break; 5631 } /* switch */ 5632 5633 if (do_debounce) { 5634 /* 5635 * Delay doing 5636 * anything for a while so that things can settle 5637 * down a little. Interrupts are already disabled. 5638 * Reset the state and we'll reevaluate the 5639 * whole kit 'n kaboodle when the timeout fires 5640 */ 5641 #ifdef PCIC_DEBUG 5642 pcic_err(pcic->dip, 8, "Queueing up debounce timeout for " 5643 "socket %d.%d\n", 5644 ddi_get_instance(pcic->dip), 5645 sockp->pcs_socket); 5646 #endif 5647 sockp->pcs_debounce_id = pcic_add_debqueue(sockp, debounce_time); 5648 5649 /* 5650 * We bug out here without re-enabling interrupts. They will 5651 * be re-enabled when the debounce timeout swings through 5652 * here. 5653 */ 5654 return; 5655 } 5656 5657 /* 5658 * Turn on Card detect interrupts. Other interrupts will be 5659 * enabled during set_socket calls. 5660 * 5661 * Note that set_socket only changes interrupt settings when there 5662 * is a card present. 5663 */ 5664 irq = pcic_getb(pcic, sockp->pcs_socket, PCIC_MANAGEMENT_INT); 5665 irq |= PCIC_CD_DETECT; 5666 pcic_putb(pcic, sockp->pcs_socket, PCIC_MANAGEMENT_INT, irq); 5667 5668 pcic_err(pcic->dip, 7, "Leaving pcic_handle_cd_change\n"); 5669 } 5670 5671 /* 5672 * pcic_getb() 5673 * get an I/O byte based on the yardware decode method 5674 */ 5675 static uint8_t 5676 pcic_getb(pcicdev_t *pcic, int socket, int reg) 5677 { 5678 int work; 5679 5680 #if defined(PCIC_DEBUG) 5681 if (pcic_debug == 0x7fff) { 5682 cmn_err(CE_CONT, "pcic_getb0: pcic=%p socket=%d reg=%d\n", 5683 (void *)pcic, socket, reg); 5684 cmn_err(CE_CONT, "pcic_getb1: type=%d handle=%p ioaddr=%p \n", 5685 pcic->pc_io_type, (void *)pcic->handle, 5686 (void *)pcic->ioaddr); 5687 } 5688 #endif 5689 5690 switch (pcic->pc_io_type) { 5691 case PCIC_IO_TYPE_YENTA: 5692 return (ddi_get8(pcic->handle, 5693 pcic->ioaddr + CB_R2_OFFSET + reg)); 5694 default: 5695 work = (socket * PCIC_SOCKET_1) | reg; 5696 ddi_put8(pcic->handle, pcic->ioaddr, work); 5697 return (ddi_get8(pcic->handle, pcic->ioaddr + 1)); 5698 } 5699 } 5700 5701 static void 5702 pcic_putb(pcicdev_t *pcic, int socket, int reg, int8_t value) 5703 { 5704 int work; 5705 5706 #if defined(PCIC_DEBUG) 5707 if (pcic_debug == 0x7fff) { 5708 cmn_err(CE_CONT, 5709 "pcic_putb0: pcic=%p socket=%d reg=%d value=%x \n", 5710 (void *)pcic, socket, reg, value); 5711 cmn_err(CE_CONT, 5712 "pcic_putb1: type=%d handle=%p ioaddr=%p \n", 5713 pcic->pc_io_type, (void *)pcic->handle, 5714 (void *)pcic->ioaddr); 5715 } 5716 #endif 5717 5718 5719 switch (pcic->pc_io_type) { 5720 case PCIC_IO_TYPE_YENTA: 5721 ddi_put8(pcic->handle, pcic->ioaddr + CB_R2_OFFSET + reg, 5722 value); 5723 break; 5724 default: 5725 work = (socket * PCIC_SOCKET_1) | reg; 5726 ddi_put8(pcic->handle, pcic->ioaddr, work); 5727 ddi_put8(pcic->handle, pcic->ioaddr + 1, value); 5728 break; 5729 } 5730 } 5731 5732 /* 5733 * chip identification functions 5734 */ 5735 5736 /* 5737 * chip identification: Cirrus Logic PD6710/6720/6722 5738 */ 5739 static int 5740 pcic_ci_cirrus(pcicdev_t *pcic) 5741 { 5742 int value1, value2; 5743 5744 /* Init the CL id mode */ 5745 value1 = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 5746 pcic_putb(pcic, 0, PCIC_CHIP_INFO, 0); 5747 value1 = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 5748 value2 = pcic_getb(pcic, 0, PCIC_CHIP_INFO); 5749 5750 if ((value1 & PCIC_CI_ID) == PCIC_CI_ID && 5751 (value2 & PCIC_CI_ID) == 0) { 5752 /* chip is a Cirrus Logic and not Intel */ 5753 pcic->pc_type = PCIC_CL_PD6710; 5754 if (value1 & PCIC_CI_SLOTS) 5755 pcic->pc_chipname = PCIC_TYPE_PD6720; 5756 else 5757 pcic->pc_chipname = PCIC_TYPE_PD6710; 5758 /* now fine tune things just in case a 6722 */ 5759 value1 = clext_reg_read(pcic, 0, PCIC_CLEXT_DMASK_0); 5760 if (value1 == 0) { 5761 clext_reg_write(pcic, 0, PCIC_CLEXT_SCRATCH, 0x55); 5762 value1 = clext_reg_read(pcic, 0, PCIC_CLEXT_SCRATCH); 5763 if (value1 == 0x55) { 5764 pcic->pc_chipname = PCIC_TYPE_PD6722; 5765 pcic->pc_type = PCIC_CL_PD6722; 5766 clext_reg_write(pcic, 0, PCIC_CLEXT_SCRATCH, 0); 5767 } 5768 } 5769 return (1); 5770 } 5771 return (0); 5772 } 5773 5774 /* 5775 * chip identification: Vadem (VG365/465/468/469) 5776 */ 5777 5778 static void 5779 pcic_vadem_enable(pcicdev_t *pcic) 5780 { 5781 ddi_put8(pcic->handle, pcic->ioaddr, PCIC_VADEM_P1); 5782 ddi_put8(pcic->handle, pcic->ioaddr, PCIC_VADEM_P2); 5783 ddi_put8(pcic->handle, pcic->ioaddr, pcic->pc_lastreg); 5784 } 5785 5786 static int 5787 pcic_ci_vadem(pcicdev_t *pcic) 5788 { 5789 int value; 5790 5791 pcic_vadem_enable(pcic); 5792 value = pcic_getb(pcic, 0, PCIC_CHIP_REVISION); 5793 pcic_putb(pcic, 0, PCIC_CHIP_REVISION, 0xFF); 5794 if (pcic_getb(pcic, 0, PCIC_CHIP_REVISION) == 5795 (value | PCIC_VADEM_D3) || 5796 (pcic_getb(pcic, 0, PCIC_CHIP_REVISION) & PCIC_REV_MASK) == 5797 PCIC_VADEM_469) { 5798 int vadem, new; 5799 pcic_vadem_enable(pcic); 5800 vadem = pcic_getb(pcic, 0, PCIC_VG_DMA) & 5801 ~(PCIC_V_UNLOCK | PCIC_V_VADEMREV); 5802 new = vadem | (PCIC_V_VADEMREV|PCIC_V_UNLOCK); 5803 pcic_putb(pcic, 0, PCIC_VG_DMA, new); 5804 value = pcic_getb(pcic, 0, PCIC_CHIP_REVISION); 5805 5806 /* want to lock but leave mouse or other on */ 5807 pcic_putb(pcic, 0, PCIC_VG_DMA, vadem); 5808 switch (value & PCIC_REV_MASK) { 5809 case PCIC_VADEM_365: 5810 pcic->pc_chipname = PCIC_VG_365; 5811 pcic->pc_type = PCIC_VADEM; 5812 break; 5813 case PCIC_VADEM_465: 5814 pcic->pc_chipname = PCIC_VG_465; 5815 pcic->pc_type = PCIC_VADEM; 5816 pcic->pc_flags |= PCF_1SOCKET; 5817 break; 5818 case PCIC_VADEM_468: 5819 pcic->pc_chipname = PCIC_VG_468; 5820 pcic->pc_type = PCIC_VADEM; 5821 break; 5822 case PCIC_VADEM_469: 5823 pcic->pc_chipname = PCIC_VG_469; 5824 pcic->pc_type = PCIC_VADEM_VG469; 5825 break; 5826 } 5827 return (1); 5828 } 5829 return (0); 5830 } 5831 5832 /* 5833 * chip identification: Ricoh 5834 */ 5835 static int 5836 pcic_ci_ricoh(pcicdev_t *pcic) 5837 { 5838 int value; 5839 5840 value = pcic_getb(pcic, 0, PCIC_RF_CHIP_IDENT); 5841 switch (value) { 5842 case PCIC_RF_296: 5843 pcic->pc_type = PCIC_RICOH; 5844 pcic->pc_chipname = PCIC_TYPE_RF5C296; 5845 return (1); 5846 case PCIC_RF_396: 5847 pcic->pc_type = PCIC_RICOH; 5848 pcic->pc_chipname = PCIC_TYPE_RF5C396; 5849 return (1); 5850 } 5851 return (0); 5852 } 5853 5854 5855 /* 5856 * set up available address spaces in busra 5857 */ 5858 static void 5859 pcic_init_assigned(dev_info_t *dip) 5860 { 5861 pcm_regs_t *pcic_avail_p; 5862 pci_regspec_t *pci_avail_p, *regs; 5863 int len, entries, rlen; 5864 dev_info_t *pdip; 5865 5866 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 5867 "available", (caddr_t)&pcic_avail_p, &len) == DDI_PROP_SUCCESS) { 5868 /* 5869 * found "available" property at the cardbus/pcmcia node 5870 * need to translate address space entries from pcmcia 5871 * format to pci format 5872 */ 5873 entries = len / sizeof (pcm_regs_t); 5874 pci_avail_p = kmem_alloc(sizeof (pci_regspec_t) * entries, 5875 KM_SLEEP); 5876 if (pcic_apply_avail_ranges(dip, pcic_avail_p, pci_avail_p, 5877 entries) == DDI_SUCCESS) 5878 (void) pci_resource_setup_avail(dip, pci_avail_p, 5879 entries); 5880 kmem_free(pcic_avail_p, len); 5881 kmem_free(pci_avail_p, entries * sizeof (pci_regspec_t)); 5882 return; 5883 } 5884 5885 /* 5886 * "legacy" platforms will have "available" property in pci node 5887 */ 5888 for (pdip = ddi_get_parent(dip); pdip; pdip = ddi_get_parent(pdip)) { 5889 if (ddi_getlongprop(DDI_DEV_T_ANY, pdip, DDI_PROP_DONTPASS, 5890 "available", (caddr_t)&pci_avail_p, &len) == 5891 DDI_PROP_SUCCESS) { 5892 /* (void) pci_resource_setup(pdip); */ 5893 kmem_free(pci_avail_p, len); 5894 break; 5895 } 5896 } 5897 5898 if (pdip == NULL) { 5899 int len; 5900 char bus_type[16] = "(unknown)"; 5901 dev_info_t *par; 5902 5903 cmn_err(CE_CONT, 5904 "?pcic_init_assigned: no available property for pcmcia\n"); 5905 5906 /* 5907 * This code is taken from pci_resource_setup() but does 5908 * not attempt to use the "available" property to populate 5909 * the ndi maps that are created. 5910 * The fact that we will actually 5911 * free some resource below (that was allocated by OBP) 5912 * should be enough to be going on with. 5913 */ 5914 for (par = dip; par != NULL; par = ddi_get_parent(par)) { 5915 len = sizeof (bus_type); 5916 5917 if ((ddi_prop_op(DDI_DEV_T_ANY, par, 5918 PROP_LEN_AND_VAL_BUF, 5919 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, 5920 "device_type", 5921 (caddr_t)&bus_type, &len) == DDI_SUCCESS) && 5922 (strcmp(bus_type, "pci") == 0)) 5923 break; 5924 } 5925 if (par != NULL && 5926 (ndi_ra_map_setup(par, NDI_RA_TYPE_MEM) != NDI_SUCCESS || 5927 ndi_ra_map_setup(par, NDI_RA_TYPE_IO) != NDI_SUCCESS)) 5928 par = NULL; 5929 } else { 5930 #ifdef CARDBUS 5931 cardbus_bus_range_t *bus_range; 5932 int k; 5933 5934 if (ddi_getlongprop(DDI_DEV_T_ANY, pdip, 0, "bus-range", 5935 (caddr_t)&bus_range, &k) == DDI_PROP_SUCCESS) { 5936 if (bus_range->lo != bus_range->hi) 5937 pcic_err(pdip, 9, "allowable bus range is " 5938 "%u->%u\n", bus_range->lo, bus_range->hi); 5939 else { 5940 pcic_err(pdip, 0, 5941 "!No spare PCI bus numbers, range is " 5942 "%u->%u, cardbus isn't usable\n", 5943 bus_range->lo, bus_range->hi); 5944 } 5945 kmem_free(bus_range, k); 5946 } else 5947 pcic_err(pdip, 0, "!No bus-range property seems to " 5948 "have been set up\n"); 5949 #endif 5950 /* 5951 * Have a valid parent with the "available" property 5952 */ 5953 (void) pci_resource_setup(pdip); 5954 } 5955 5956 if ((strcmp(ddi_get_name(dip), "pcma") == 0) && 5957 ddi_getlongprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 5958 "assigned-addresses", 5959 (caddr_t)®s, &rlen) == DDI_SUCCESS) { 5960 ra_return_t ra; 5961 5962 /* 5963 * On the UltraBook IIi the ranges are assigned under 5964 * openboot. If we don't free them here the first I/O 5965 * space that can be used is up above 0x10000 which 5966 * doesn't work for this driver due to restrictions 5967 * on the PCI I/O addresses the controllers can cope with. 5968 * They are never going to be used by anything else 5969 * so free them up to the general pool. AG. 5970 */ 5971 pcic_err(dip, 1, "Free assigned addresses\n"); 5972 5973 if ((PCI_REG_ADDR_G(regs[0].pci_phys_hi) == 5974 PCI_REG_ADDR_G(PCI_ADDR_MEM32)) && 5975 regs[0].pci_size_low == 0x1000000) { 5976 ra.ra_addr_lo = regs[0].pci_phys_low; 5977 ra.ra_len = regs[0].pci_size_low; 5978 (void) pcmcia_free_mem(dip, &ra); 5979 } 5980 if ((PCI_REG_ADDR_G(regs[1].pci_phys_hi) == 5981 PCI_REG_ADDR_G(PCI_ADDR_IO)) && 5982 (regs[1].pci_size_low == 0x8000 || 5983 regs[1].pci_size_low == 0x4000)) /* UB-IIi || UB-I */ 5984 { 5985 ra.ra_addr_lo = regs[1].pci_phys_low; 5986 ra.ra_len = regs[1].pci_size_low; 5987 (void) pcmcia_free_io(dip, &ra); 5988 } 5989 kmem_free((caddr_t)regs, rlen); 5990 } 5991 } 5992 5993 /* 5994 * translate "available" from pcmcia format to pci format 5995 */ 5996 static int 5997 pcic_apply_avail_ranges(dev_info_t *dip, pcm_regs_t *pcic_p, 5998 pci_regspec_t *pci_p, int entries) 5999 { 6000 int i, range_len, range_entries; 6001 pcic_ranges_t *pcic_range_p; 6002 6003 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "ranges", 6004 (caddr_t)&pcic_range_p, &range_len) != DDI_PROP_SUCCESS) { 6005 cmn_err(CE_CONT, "?pcic_apply_avail_ranges: " 6006 "no ranges property for pcmcia\n"); 6007 return (DDI_FAILURE); 6008 } 6009 6010 range_entries = range_len / sizeof (pcic_ranges_t); 6011 6012 /* for each "available" entry to be translated */ 6013 for (i = 0; i < entries; i++, pcic_p++, pci_p++) { 6014 int j; 6015 pcic_ranges_t *range_p = pcic_range_p; 6016 pci_p->pci_phys_hi = -1u; /* default invalid value */ 6017 6018 /* for each "ranges" entry to be searched */ 6019 for (j = 0; j < range_entries; j++, range_p++) { 6020 uint64_t range_end = range_p->pcic_range_caddrlo + 6021 range_p->pcic_range_size; 6022 uint64_t avail_end = pcic_p->phys_lo + pcic_p->phys_len; 6023 6024 if ((range_p->pcic_range_caddrhi != pcic_p->phys_hi) || 6025 (range_p->pcic_range_caddrlo > pcic_p->phys_lo) || 6026 (range_end < avail_end)) 6027 continue; 6028 6029 pci_p->pci_phys_hi = range_p->pcic_range_paddrhi; 6030 pci_p->pci_phys_mid = range_p->pcic_range_paddrmid; 6031 pci_p->pci_phys_low = range_p->pcic_range_paddrlo 6032 + (pcic_p->phys_lo - range_p->pcic_range_caddrlo); 6033 pci_p->pci_size_hi = 0; 6034 pci_p->pci_size_low = pcic_p->phys_len; 6035 } 6036 } 6037 kmem_free(pcic_range_p, range_len); 6038 return (DDI_SUCCESS); 6039 } 6040 6041 static int 6042 pcic_open(dev_t *dev, int flag, int otyp, cred_t *cred) 6043 { 6044 if (getminor(*dev) == SYSHW_MINOR) 6045 return (syshw_open(dev, flag, otyp, cred)); 6046 #ifdef CARDBUS 6047 if (cardbus_is_cb_minor(*dev)) 6048 return (cardbus_open(dev, flag, otyp, cred)); 6049 #endif 6050 return (EINVAL); 6051 } 6052 6053 static int 6054 pcic_close(dev_t dev, int flag, int otyp, cred_t *cred) 6055 { 6056 if (getminor(dev) == SYSHW_MINOR) 6057 return (syshw_close(dev, flag, otyp, cred)); 6058 #ifdef CARDBUS 6059 if (cardbus_is_cb_minor(dev)) 6060 return (cardbus_close(dev, flag, otyp, cred)); 6061 #endif 6062 return (EINVAL); 6063 } 6064 6065 static int 6066 pcic_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *cred, 6067 int *rval) 6068 { 6069 if (getminor(dev) == SYSHW_MINOR) 6070 return (syshw_ioctl(dev, cmd, arg, mode, cred, rval)); 6071 #ifdef CARDBUS 6072 if (cardbus_is_cb_minor(dev)) 6073 return (cardbus_ioctl(dev, cmd, arg, mode, cred, rval)); 6074 #endif 6075 return (EINVAL); 6076 } 6077 6078 6079 static boolean_t 6080 pcic_load_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp) 6081 { 6082 uint32_t present_state; 6083 dev_info_t *dip = pcic->dip; 6084 set_socket_t s; 6085 get_socket_t g; 6086 boolean_t retval; 6087 unsigned vccLevel; 6088 6089 pcic_err(dip, 8, "entering pcic_load_cardbus\n"); 6090 6091 pcic_mutex_exit(&pcic->pc_lock); 6092 6093 bzero(&s, sizeof (set_socket_t)); 6094 s.socket = sockp->pcs_socket; 6095 s.SCIntMask = SBM_CD|SBM_RDYBSY; 6096 s.IFType = IF_CARDBUS; 6097 s.State = (unsigned)~0; 6098 6099 present_state = pcic_getcb(pcic, CB_PRESENT_STATE); 6100 if (present_state & PCIC_VCC_3VCARD) 6101 s.VccLevel = PCIC_VCC_3VLEVEL; 6102 else if (present_state & PCIC_VCC_5VCARD) 6103 s.VccLevel = PCIC_VCC_5VLEVEL; 6104 else { 6105 cmn_err(CE_CONT, 6106 "pcic_load_cardbus: unsupported card voltage\n"); 6107 goto failure; 6108 } 6109 vccLevel = s.VccLevel; 6110 s.Vpp1Level = s.Vpp2Level = 0; 6111 6112 if (pcic_set_socket(dip, &s) != SUCCESS) 6113 goto failure; 6114 6115 if (pcic_reset_socket(dip, sockp->pcs_socket, 6116 RESET_MODE_CARD_ONLY) != SUCCESS) 6117 goto failure; 6118 6119 bzero(&g, sizeof (get_socket_t)); 6120 g.socket = sockp->pcs_socket; 6121 if (pcic_get_socket(dip, &g) != SUCCESS) 6122 goto failure; 6123 6124 bzero(&s, sizeof (set_socket_t)); 6125 s.socket = sockp->pcs_socket; 6126 s.SCIntMask = SBM_CD; 6127 s.IREQRouting = g.IRQRouting; 6128 s.IFType = g.IFType; 6129 s.CtlInd = g.CtlInd; 6130 s.State = (unsigned)~0; 6131 s.VccLevel = vccLevel; 6132 s.Vpp1Level = s.Vpp2Level = 0; 6133 6134 if (pcic_set_socket(dip, &s) != SUCCESS) 6135 goto failure; 6136 6137 retval = cardbus_load_cardbus(dip, sockp->pcs_socket, pcic->pc_base); 6138 goto exit; 6139 6140 failure: 6141 retval = B_FALSE; 6142 6143 exit: 6144 pcic_mutex_enter(&pcic->pc_lock); 6145 pcic_err(dip, 8, "exit pcic_load_cardbus (%s)\n", 6146 retval ? "success" : "failure"); 6147 return (retval); 6148 } 6149 6150 static void 6151 pcic_unload_cardbus(pcicdev_t *pcic, const pcic_socket_t *sockp) 6152 { 6153 dev_info_t *dip = pcic->dip; 6154 set_socket_t s; 6155 6156 pcic_mutex_exit(&pcic->pc_lock); 6157 6158 cardbus_unload_cardbus(dip); 6159 6160 bzero(&s, sizeof (set_socket_t)); 6161 s.socket = sockp->pcs_socket; 6162 s.SCIntMask = SBM_CD|SBM_RDYBSY; 6163 s.IREQRouting = 0; 6164 s.IFType = IF_MEMORY; 6165 s.CtlInd = 0; 6166 s.State = 0; 6167 s.VccLevel = s.Vpp1Level = s.Vpp2Level = 0; 6168 6169 (void) pcic_set_socket(dip, &s); 6170 6171 pcic_mutex_enter(&pcic->pc_lock); 6172 } 6173 6174 static uint32_t 6175 pcic_getcb(pcicdev_t *pcic, int reg) 6176 { 6177 ASSERT(pcic->pc_io_type == PCIC_IO_TYPE_YENTA); 6178 6179 return (ddi_get32(pcic->handle, 6180 (uint32_t *)(pcic->ioaddr + CB_CB_OFFSET + reg))); 6181 } 6182 6183 static void 6184 pcic_putcb(pcicdev_t *pcic, int reg, uint32_t value) 6185 { 6186 ASSERT(pcic->pc_io_type == PCIC_IO_TYPE_YENTA); 6187 6188 ddi_put32(pcic->handle, 6189 (uint32_t *)(pcic->ioaddr + CB_CB_OFFSET + reg), value); 6190 } 6191 6192 static void 6193 pcic_enable_io_intr(pcicdev_t *pcic, int socket, int irq) 6194 { 6195 uint8_t value; 6196 uint16_t brdgctl; 6197 6198 value = pcic_getb(pcic, socket, PCIC_INTERRUPT) & ~PCIC_INTR_MASK; 6199 pcic_putb(pcic, socket, PCIC_INTERRUPT, value | irq); 6200 6201 switch (pcic->pc_type) { 6202 case PCIC_INTEL_i82092: 6203 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ, 6204 PCIC_82092_INT_ENABLE); 6205 break; 6206 case PCIC_O2_OZ6912: 6207 value = pcic_getb(pcic, 0, PCIC_CENTDMA); 6208 value |= 0x8; 6209 pcic_putb(pcic, 0, PCIC_CENTDMA, value); 6210 break; 6211 case PCIC_CL_PD6832: 6212 case PCIC_TI_PCI1250: 6213 case PCIC_TI_PCI1221: 6214 case PCIC_TI_PCI1225: 6215 case PCIC_TI_PCI1410: 6216 case PCIC_ENE_1410: 6217 case PCIC_TI_PCI1510: 6218 case PCIC_TI_PCI1520: 6219 case PCIC_TI_PCI1420: 6220 case PCIC_ENE_1420: 6221 /* route card functional interrupts to PCI interrupts */ 6222 brdgctl = ddi_get16(pcic->cfg_handle, 6223 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6224 pcic_err(NULL, 1, 6225 "pcic_enable_io_intr brdgctl(0x%x) was: 0x%x\n", 6226 PCI_CBUS_BRIDGE_CTRL, brdgctl); 6227 brdgctl &= ~PCIC_BRDGCTL_INTR_MASK; 6228 ddi_put16(pcic->cfg_handle, 6229 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL), 6230 brdgctl); 6231 /* Flush the write */ 6232 (void) ddi_get16(pcic->cfg_handle, 6233 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6234 break; 6235 default: 6236 break; 6237 } 6238 } 6239 6240 static void 6241 pcic_disable_io_intr(pcicdev_t *pcic, int socket) 6242 { 6243 uint8_t value; 6244 uint16_t brdgctl; 6245 6246 value = pcic_getb(pcic, socket, PCIC_INTERRUPT) & ~PCIC_INTR_MASK; 6247 pcic_putb(pcic, socket, PCIC_INTERRUPT, value); 6248 6249 switch (pcic->pc_type) { 6250 case PCIC_INTEL_i82092: 6251 pcic_82092_smiirq_ctl(pcic, socket, PCIC_82092_CTL_IRQ, 6252 PCIC_82092_INT_DISABLE); 6253 break; 6254 case PCIC_O2_OZ6912: 6255 value = pcic_getb(pcic, 0, PCIC_CENTDMA); 6256 value &= ~0x8; 6257 pcic_putb(pcic, 0, PCIC_CENTDMA, value); 6258 /* Flush the write */ 6259 (void) pcic_getb(pcic, 0, PCIC_CENTDMA); 6260 break; 6261 case PCIC_CL_PD6832: 6262 case PCIC_TI_PCI1250: 6263 case PCIC_TI_PCI1221: 6264 case PCIC_TI_PCI1225: 6265 case PCIC_TI_PCI1410: 6266 case PCIC_ENE_1410: 6267 case PCIC_TI_PCI1510: 6268 case PCIC_TI_PCI1520: 6269 case PCIC_TI_PCI1420: 6270 case PCIC_ENE_1420: 6271 /* 6272 * This maps I/O interrupts to ExCA which 6273 * have been turned off by the write to 6274 * PCIC_INTERRUPT above. It would appear to 6275 * be the only way to actually turn I/O Ints off 6276 * while retaining CS Ints. 6277 */ 6278 brdgctl = ddi_get16(pcic->cfg_handle, 6279 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6280 pcic_err(NULL, 1, 6281 "pcic_disable_io_intr brdgctl(0x%x) was: 0x%x\n", 6282 PCI_CBUS_BRIDGE_CTRL, brdgctl); 6283 brdgctl |= PCIC_BRDGCTL_INTR_MASK; 6284 ddi_put16(pcic->cfg_handle, 6285 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL), 6286 brdgctl); 6287 /* Flush the write */ 6288 (void) ddi_get16(pcic->cfg_handle, 6289 (uint16_t *)(pcic->cfgaddr + PCI_CBUS_BRIDGE_CTRL)); 6290 break; 6291 default: 6292 break; 6293 } 6294 } 6295 6296 static void 6297 pcic_cb_enable_intr(dev_info_t *dip) 6298 { 6299 anp_t *anp = ddi_get_driver_private(dip); 6300 pcicdev_t *pcic = anp->an_private; 6301 6302 mutex_enter(&pcic->pc_lock); 6303 pcic_enable_io_intr(pcic, 0, pcic->pc_sockets[0].pcs_irq); 6304 mutex_exit(&pcic->pc_lock); 6305 } 6306 6307 static void 6308 pcic_cb_disable_intr(dev_info_t *dip) 6309 { 6310 anp_t *anp = ddi_get_driver_private(dip); 6311 pcicdev_t *pcic = anp->an_private; 6312 6313 mutex_enter(&pcic->pc_lock); 6314 pcic_disable_io_intr(pcic, 0); 6315 mutex_exit(&pcic->pc_lock); 6316 } 6317 6318 static int 6319 log_pci_cfg_err(ushort_t e, int bridge_secondary) 6320 { 6321 int nerr = 0; 6322 if (e & PCI_STAT_PERROR) { 6323 nerr++; 6324 cmn_err(CE_CONT, "detected parity error.\n"); 6325 } 6326 if (e & PCI_STAT_S_SYSERR) { 6327 nerr++; 6328 if (bridge_secondary) 6329 cmn_err(CE_CONT, "received system error.\n"); 6330 else 6331 cmn_err(CE_CONT, "signalled system error.\n"); 6332 } 6333 if (e & PCI_STAT_R_MAST_AB) { 6334 nerr++; 6335 cmn_err(CE_CONT, "received master abort.\n"); 6336 } 6337 if (e & PCI_STAT_R_TARG_AB) 6338 cmn_err(CE_CONT, "received target abort.\n"); 6339 if (e & PCI_STAT_S_TARG_AB) 6340 cmn_err(CE_CONT, "signalled target abort\n"); 6341 if (e & PCI_STAT_S_PERROR) { 6342 nerr++; 6343 cmn_err(CE_CONT, "signalled parity error\n"); 6344 } 6345 return (nerr); 6346 } 6347 6348 #if defined(__sparc) 6349 static int 6350 pcic_fault(enum pci_fault_ops op, void *arg) 6351 { 6352 pcicdev_t *pcic = (pcicdev_t *)arg; 6353 ushort_t pci_cfg_stat = 6354 pci_config_get16(pcic->cfg_handle, PCI_CONF_STAT); 6355 ushort_t pci_cfg_sec_stat = 6356 pci_config_get16(pcic->cfg_handle, 0x16); 6357 char nm[24]; 6358 int nerr = 0; 6359 6360 cardbus_dump_pci_config(pcic->dip); 6361 6362 switch (op) { 6363 case FAULT_LOG: 6364 (void) sprintf(nm, "%s-%d", ddi_driver_name(pcic->dip), 6365 ddi_get_instance(pcic->dip)); 6366 6367 cmn_err(CE_WARN, "%s: PCIC fault log start:\n", nm); 6368 cmn_err(CE_WARN, "%s: primary err (%x):\n", nm, pci_cfg_stat); 6369 nerr += log_pci_cfg_err(pci_cfg_stat, 0); 6370 cmn_err(CE_WARN, "%s: sec err (%x):\n", nm, pci_cfg_sec_stat); 6371 nerr += log_pci_cfg_err(pci_cfg_sec_stat, 1); 6372 cmn_err(CE_CONT, "%s: PCI fault log end.\n", nm); 6373 return (nerr); 6374 case FAULT_POKEFINI: 6375 case FAULT_RESET: 6376 pci_config_put16(pcic->cfg_handle, 6377 PCI_CONF_STAT, pci_cfg_stat); 6378 pci_config_put16(pcic->cfg_handle, 0x16, pci_cfg_sec_stat); 6379 break; 6380 case FAULT_POKEFLT: 6381 if (!(pci_cfg_stat & PCI_STAT_S_SYSERR)) 6382 return (1); 6383 if (!(pci_cfg_sec_stat & PCI_STAT_R_MAST_AB)) 6384 return (1); 6385 break; 6386 default: 6387 break; 6388 } 6389 return (DDI_SUCCESS); 6390 } 6391 #endif 6392 6393 static void 6394 pcic_delayed_resume(void *arg) 6395 { 6396 int i, j, interrupt; 6397 anp_t *pcic_nexus; 6398 pcicdev_t *pcic; 6399 6400 _NOTE(ARGUNUSED(arg)) 6401 6402 #if defined(PCIC_DEBUG) 6403 pcic_err(NULL, 6, "pcic_delayed_resume(): entered\n"); 6404 #endif 6405 for (j = 0; j <= pcic_maxinst; j++) { 6406 6407 pcic_nexus = ddi_get_soft_state(pcic_soft_state_p, j); 6408 if (!pcic_nexus) 6409 continue; 6410 pcic = (pcicdev_t *)pcic_nexus->an_private; 6411 if (!pcic) 6412 continue; 6413 6414 pcic_mutex_enter(&pcic->pc_lock); /* protect the registers */ 6415 for (i = 0; i < pcic->pc_numsockets; i++) { 6416 /* Enable interrupts on PCI if needs be */ 6417 interrupt = pcic_getb(pcic, i, PCIC_INTERRUPT); 6418 if (pcic->pc_flags & PCF_USE_SMI) 6419 interrupt |= PCIC_INTR_ENABLE; 6420 pcic_putb(pcic, i, PCIC_INTERRUPT, 6421 PCIC_RESET | interrupt); 6422 pcic->pc_sockets[i].pcs_debounce_id = 6423 pcic_add_debqueue(&pcic->pc_sockets[i], 6424 drv_usectohz(pcic_debounce_time)); 6425 } 6426 pcic_mutex_exit(&pcic->pc_lock); /* protect the registers */ 6427 if (pcic_do_pcmcia_sr) 6428 (void) pcmcia_wait_insert(pcic->dip); 6429 } 6430 } 6431 6432 static void 6433 pcic_debounce(pcic_socket_t *pcs) 6434 { 6435 uint8_t status, stschng; 6436 6437 pcic_mutex_enter(&pcs->pcs_pcic->pc_lock); 6438 pcs->pcs_flags &= ~PCS_STARTING; 6439 stschng = pcic_getb(pcs->pcs_pcic, pcs->pcs_socket, 6440 PCIC_CARD_STATUS_CHANGE); 6441 status = pcic_getb(pcs->pcs_pcic, pcs->pcs_socket, 6442 PCIC_INTERFACE_STATUS); 6443 #ifdef PCIC_DEBUG 6444 pcic_err(pcs->pcs_pcic->dip, 8, 6445 "pcic_debounce(0x%p, dip=0x%p) socket %d st 0x%x " 6446 "chg 0x%x flg 0x%x\n", 6447 (void *)pcs, (void *) pcs->pcs_pcic->dip, pcs->pcs_socket, 6448 status, stschng, pcs->pcs_flags); 6449 #endif 6450 6451 pcic_putb(pcs->pcs_pcic, pcs->pcs_socket, PCIC_CARD_STATUS_CHANGE, 6452 PCIC_CD_DETECT); 6453 pcic_handle_cd_change(pcs->pcs_pcic, pcs, status); 6454 pcic_mutex_exit(&pcs->pcs_pcic->pc_lock); 6455 } 6456 6457 static void 6458 pcic_deb_thread() 6459 { 6460 callb_cpr_t cprinfo; 6461 struct debounce *debp; 6462 clock_t lastt; 6463 6464 CALLB_CPR_INIT(&cprinfo, &pcic_deb_mtx, 6465 callb_generic_cpr, "pcic debounce thread"); 6466 mutex_enter(&pcic_deb_mtx); 6467 while (pcic_deb_threadid) { 6468 while (pcic_deb_queue) { 6469 #ifdef PCIC_DEBUG 6470 pcic_dump_debqueue("Thread"); 6471 #endif 6472 debp = pcic_deb_queue; 6473 (void) drv_getparm(LBOLT, &lastt); 6474 if (lastt >= debp->expire) { 6475 pcic_deb_queue = debp->next; 6476 mutex_exit(&pcic_deb_mtx); 6477 pcic_debounce(debp->pcs); 6478 mutex_enter(&pcic_deb_mtx); 6479 kmem_free(debp, sizeof (*debp)); 6480 } else { 6481 (void) cv_timedwait(&pcic_deb_cv, 6482 &pcic_deb_mtx, debp->expire); 6483 } 6484 } 6485 CALLB_CPR_SAFE_BEGIN(&cprinfo); 6486 cv_wait(&pcic_deb_cv, &pcic_deb_mtx); 6487 CALLB_CPR_SAFE_END(&cprinfo, &pcic_deb_mtx); 6488 } 6489 pcic_deb_threadid = (kthread_t *)1; 6490 cv_signal(&pcic_deb_cv); 6491 CALLB_CPR_EXIT(&cprinfo); /* Also exits the mutex */ 6492 thread_exit(); 6493 } 6494 6495 static void * 6496 pcic_add_debqueue(pcic_socket_t *pcs, int clocks) 6497 { 6498 clock_t lbolt; 6499 struct debounce *dbp, **dbpp = &pcic_deb_queue; 6500 6501 (void) drv_getparm(LBOLT, &lbolt); 6502 dbp = kmem_alloc(sizeof (struct debounce), KM_NOSLEEP); 6503 6504 dbp->expire = lbolt + clocks; 6505 dbp->pcs = pcs; 6506 mutex_enter(&pcic_deb_mtx); 6507 while (*dbpp) { 6508 if (dbp->expire > (*dbpp)->expire) 6509 dbpp = &((*dbpp)->next); 6510 else 6511 break; 6512 } 6513 dbp->next = *dbpp; 6514 *dbpp = dbp; 6515 #ifdef PCIC_DEBUG 6516 pcic_dump_debqueue("Add"); 6517 #endif 6518 cv_signal(&pcic_deb_cv); 6519 mutex_exit(&pcic_deb_mtx); 6520 return (dbp); 6521 } 6522 6523 static void 6524 pcic_rm_debqueue(void *id) 6525 { 6526 struct debounce *dbp, **dbpp = &pcic_deb_queue; 6527 6528 dbp = (struct debounce *)id; 6529 mutex_enter(&pcic_deb_mtx); 6530 while (*dbpp) { 6531 if (*dbpp == dbp) { 6532 *dbpp = dbp->next; 6533 kmem_free(dbp, sizeof (*dbp)); 6534 #ifdef PCIC_DEBUG 6535 pcic_dump_debqueue("Remove"); 6536 #endif 6537 cv_signal(&pcic_deb_cv); 6538 mutex_exit(&pcic_deb_mtx); 6539 return; 6540 } 6541 dbpp = &((*dbpp)->next); 6542 } 6543 pcic_err(NULL, 6, "pcic: Failed to find debounce id 0x%p\n", id); 6544 mutex_exit(&pcic_deb_mtx); 6545 } 6546 6547 6548 static int pcic_powerdelay = 0; 6549 6550 static int 6551 pcic_exca_powerctl(pcicdev_t *pcic, int socket, int powerlevel) 6552 { 6553 int ind, value, orig_pwrctl; 6554 6555 /* power setup -- if necessary */ 6556 orig_pwrctl = pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6557 6558 #if defined(PCIC_DEBUG) 6559 pcic_err(pcic->dip, 6, 6560 "pcic_exca_powerctl(socket %d) powerlevel=%x orig 0x%x\n", 6561 socket, powerlevel, orig_pwrctl); 6562 #endif 6563 /* Preserve the PCIC_OUTPUT_ENABLE (control lines output enable) bit. */ 6564 powerlevel = (powerlevel & ~POWER_OUTPUT_ENABLE) | 6565 (orig_pwrctl & POWER_OUTPUT_ENABLE); 6566 if (powerlevel != orig_pwrctl) { 6567 if (powerlevel & ~POWER_OUTPUT_ENABLE) { 6568 int ifs; 6569 /* 6570 * set power to socket 6571 * note that the powerlevel was calculated earlier 6572 */ 6573 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel); 6574 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6575 6576 /* 6577 * this second write to the power control register 6578 * is needed to resolve a problem on 6579 * the IBM ThinkPad 750 6580 * where the first write doesn't latch. 6581 * The second write appears to always work and 6582 * doesn't hurt the operation of other chips 6583 * so we can just use it -- this is good since we can't 6584 * determine what chip the 750 actually uses 6585 * (I suspect an early Ricoh). 6586 */ 6587 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel); 6588 6589 value = pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6590 pcic_mswait(pcic, socket, pcic_powerdelay); 6591 #if defined(PCIC_DEBUG) 6592 pcic_err(pcic->dip, 8, 6593 "\tpowerlevel reg = %x (ifs %x)\n", 6594 value, pcic_getb(pcic, socket, 6595 PCIC_INTERFACE_STATUS)); 6596 pcic_err(pcic->dip, 8, 6597 "CBus regs: PS 0x%x, Control 0x%x\n", 6598 pcic_getcb(pcic, CB_PRESENT_STATE), 6599 pcic_getcb(pcic, CB_CONTROL)); 6600 #endif 6601 /* 6602 * since power was touched, make sure it says it 6603 * is on. This lets it become stable. 6604 */ 6605 for (ind = 0; ind < 20; ind++) { 6606 ifs = pcic_getb(pcic, socket, 6607 PCIC_INTERFACE_STATUS); 6608 if (ifs & PCIC_POWER_ON) 6609 break; 6610 else { 6611 pcic_putb(pcic, socket, 6612 PCIC_POWER_CONTROL, 0); 6613 (void) pcic_getb(pcic, socket, 6614 PCIC_POWER_CONTROL); 6615 pcic_mswait(pcic, socket, 40); 6616 if (ind == 10) { 6617 pcic_putcb(pcic, CB_EVENT_FORCE, 6618 CB_EF_CVTEST); 6619 pcic_mswait(pcic, socket, 100); 6620 } 6621 pcic_putb(pcic, socket, 6622 PCIC_POWER_CONTROL, 6623 powerlevel & ~POWER_OUTPUT_ENABLE); 6624 (void) pcic_getb(pcic, socket, 6625 PCIC_POWER_CONTROL); 6626 pcic_mswait(pcic, socket, 6627 pcic_powerdelay); 6628 pcic_putb(pcic, socket, 6629 PCIC_POWER_CONTROL, powerlevel); 6630 (void) pcic_getb(pcic, socket, 6631 PCIC_POWER_CONTROL); 6632 pcic_mswait(pcic, socket, 6633 pcic_powerdelay); 6634 } 6635 } 6636 6637 if (!(ifs & PCIC_POWER_ON)) { 6638 cmn_err(CE_WARN, 6639 "pcic socket %d: Power didn't get turned" 6640 "on!\nif status 0x%x pwrc 0x%x(x%x) " 6641 "misc1 0x%x igc 0x%x ind %d\n", 6642 socket, ifs, 6643 pcic_getb(pcic, socket, PCIC_POWER_CONTROL), 6644 orig_pwrctl, 6645 pcic_getb(pcic, socket, PCIC_MISC_CTL_1), 6646 pcic_getb(pcic, socket, PCIC_INTERRUPT), 6647 ind); 6648 return (BAD_VCC); 6649 } 6650 #if defined(PCIC_DEBUG) 6651 pcic_err(pcic->dip, 8, 6652 "\tind = %d, if status %x pwrc 0x%x " 6653 "misc1 0x%x igc 0x%x\n", 6654 ind, ifs, 6655 pcic_getb(pcic, socket, PCIC_POWER_CONTROL), 6656 pcic_getb(pcic, socket, PCIC_MISC_CTL_1), 6657 pcic_getb(pcic, socket, PCIC_INTERRUPT)); 6658 #endif 6659 } else { 6660 /* explicitly turned off the power */ 6661 pcic_putb(pcic, socket, PCIC_POWER_CONTROL, powerlevel); 6662 (void) pcic_getb(pcic, socket, PCIC_POWER_CONTROL); 6663 } 6664 } 6665 return (SUCCESS); 6666 } 6667 6668 static int pcic_cbdoreset_during_poweron = 1; 6669 static int 6670 pcic_cbus_powerctl(pcicdev_t *pcic, int socket) 6671 { 6672 uint32_t cbctl = 0, orig_cbctl, cbstev, cbps; 6673 int ind, iobits; 6674 pcic_socket_t *sockp = &pcic->pc_sockets[socket]; 6675 6676 pcic_putcb(pcic, CB_STATUS_EVENT, CB_SE_POWER_CYCLE); 6677 6678 ind = pcic_power[sockp->pcs_vpp1].PowerLevel/10; 6679 cbctl |= pcic_cbv_levels[ind]; 6680 6681 ind = pcic_power[sockp->pcs_vcc].PowerLevel/10; 6682 cbctl |= (pcic_cbv_levels[ind]<<4); 6683 6684 orig_cbctl = pcic_getcb(pcic, CB_CONTROL); 6685 6686 #if defined(PCIC_DEBUG) 6687 pcic_err(pcic->dip, 6, 6688 "pcic_cbus_powerctl(socket %d) vcc %d vpp1 %d " 6689 "cbctl 0x%x->0x%x\n", 6690 socket, sockp->pcs_vcc, sockp->pcs_vpp1, orig_cbctl, cbctl); 6691 #endif 6692 if (cbctl != orig_cbctl) { 6693 if (pcic_cbdoreset_during_poweron && 6694 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) { 6695 iobits = pcic_getb(pcic, socket, PCIC_INTERRUPT); 6696 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits & ~PCIC_RESET); 6697 } 6698 pcic_putcb(pcic, CB_CONTROL, cbctl); 6699 6700 if ((cbctl & CB_C_VCCMASK) == (orig_cbctl & CB_C_VCCMASK)) { 6701 pcic_mswait(pcic, socket, pcic_powerdelay); 6702 return (SUCCESS); 6703 } 6704 for (ind = 0; ind < 20; ind++) { 6705 cbstev = pcic_getcb(pcic, CB_STATUS_EVENT); 6706 6707 if (cbstev & CB_SE_POWER_CYCLE) { 6708 6709 /* 6710 * delay 400 ms: though the standard defines that the Vcc 6711 * set-up time is 20 ms, some PC-Card bridge requires longer 6712 * duration. 6713 * Note: We should check the status AFTER the delay to give time 6714 * for things to stabilize. 6715 */ 6716 pcic_mswait(pcic, socket, 400); 6717 6718 cbps = pcic_getcb(pcic, CB_PRESENT_STATE); 6719 if (cbctl && !(cbps & CB_PS_POWER_CYCLE)) { 6720 /* break; */ 6721 cmn_err(CE_WARN, "cbus_powerctl: power off??\n"); 6722 } 6723 if (cbctl & CB_PS_BADVCC) { 6724 cmn_err(CE_WARN, "cbus_powerctl: bad power request\n"); 6725 break; 6726 } 6727 6728 #if defined(PCIC_DEBUG) 6729 pcic_err(pcic->dip, 8, 6730 "cbstev = 0x%x cbps = 0x%x cbctl 0x%x(0x%x)", 6731 cbstev, pcic_getcb(pcic, CB_PRESENT_STATE), 6732 cbctl, orig_cbctl); 6733 #endif 6734 if (pcic_cbdoreset_during_poweron && 6735 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) { 6736 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits); 6737 } 6738 return (SUCCESS); 6739 } 6740 pcic_mswait(pcic, socket, 40); 6741 } 6742 if (pcic_cbdoreset_during_poweron && 6743 (orig_cbctl & (CB_C_VCCMASK|CB_C_VPPMASK)) == 0) { 6744 pcic_putb(pcic, socket, PCIC_INTERRUPT, iobits); 6745 } 6746 cmn_err(CE_WARN, 6747 "pcic socket %d: Power didn't get turned on/off!\n" 6748 "cbstev = 0x%x cbps = 0x%x cbctl 0x%x(0x%x) " 6749 "vcc %d vpp1 %d", socket, cbstev, 6750 pcic_getcb(pcic, CB_PRESENT_STATE), 6751 cbctl, orig_cbctl, sockp->pcs_vcc, sockp->pcs_vpp1); 6752 return (BAD_VCC); 6753 } 6754 return (SUCCESS); 6755 } 6756 6757 static int pcic_do_pprintf = 0; 6758 6759 static void 6760 pcic_dump_debqueue(char *msg) 6761 { 6762 struct debounce *debp = pcic_deb_queue; 6763 clock_t lbolt; 6764 6765 (void) drv_getparm(LBOLT, &lbolt); 6766 pcic_err(NULL, 6, debp ? "pcic debounce list (%s) lbolt 0x%x:\n" : 6767 "pcic debounce_list (%s) EMPTY lbolt 0x%x\n", msg, lbolt); 6768 while (debp) { 6769 pcic_err(NULL, 6, "%p: exp 0x%x next 0x%p id 0x%p\n", 6770 (void *) debp, (int)debp->expire, (void *) debp->next, 6771 debp->pcs->pcs_debounce_id); 6772 debp = debp->next; 6773 } 6774 } 6775 6776 6777 /* PRINTFLIKE3 */ 6778 static void 6779 pcic_err(dev_info_t *dip, int level, const char *fmt, ...) 6780 { 6781 if (pcic_debug && (level <= pcic_debug)) { 6782 va_list adx; 6783 int instance; 6784 char buf[256]; 6785 const char *name; 6786 #if !defined(PCIC_DEBUG) 6787 int ce; 6788 char qmark = 0; 6789 6790 if (level <= 3) 6791 ce = CE_WARN; 6792 else 6793 ce = CE_CONT; 6794 if (level == 4) 6795 qmark = 1; 6796 #endif 6797 6798 if (dip) { 6799 instance = ddi_get_instance(dip); 6800 /* name = ddi_binding_name(dip); */ 6801 name = ddi_driver_name(dip); 6802 } else { 6803 instance = 0; 6804 name = ""; 6805 } 6806 6807 va_start(adx, fmt); 6808 (void) vsprintf(buf, fmt, adx); 6809 va_end(adx); 6810 6811 #if defined(PCIC_DEBUG) 6812 if (pcic_do_pprintf) { 6813 if (dip) { 6814 if (instance >= 0) 6815 prom_printf("%s(%d),0x%p: %s", name, 6816 instance, dip, buf); 6817 else 6818 prom_printf("%s,0x%p: %s", 6819 name, dip, buf); 6820 } else 6821 prom_printf(buf); 6822 } else { 6823 if (dip) { 6824 if (instance >= 0) 6825 cmn_err(CE_CONT, "%s(%d),0x%p: %s", 6826 name, instance, (void *) dip, buf); 6827 else 6828 cmn_err(CE_CONT, "%s,0x%p: %s", 6829 name, (void *) dip, buf); 6830 } else 6831 cmn_err(CE_CONT, buf); 6832 } 6833 #else 6834 if (dip) 6835 cmn_err(ce, qmark ? "?%s%d: %s" : "%s%d: %s", name, 6836 instance, buf); 6837 else 6838 cmn_err(ce, qmark ? "?%s" : buf, buf); 6839 #endif 6840 } 6841 } 6842 6843 6844 static void 6845 pcic_syshw_cardstate(syshw_t *item, void *arg) 6846 { 6847 pcic_socket_t *pcs = (pcic_socket_t *)arg; 6848 6849 if (pcs->pcs_flags & PCS_CARD_PRESENT) { 6850 item->state = B_TRUE; 6851 if (pcs->pcs_flags & PCS_CARD_IS16BIT) 6852 item->values[0] = 1; 6853 else if (pcs->pcs_flags & PCS_CARD_ISCARDBUS) 6854 item->values[0] = 2; 6855 else 6856 item->values[0] = 0; 6857 } else { 6858 item->state = B_FALSE; 6859 item->values[0] = 0; 6860 } 6861 } 6862 6863 /* 6864 * Tadpole additional for the syshw interface used to control the 6865 * start/stop switch which is physically linked to the GPIO1 pin 6866 * on the 1250a. 6867 */ 6868 6869 #define CLIENT_CALLED 0x8000000 6870 #define NCE_EVENT_MASK 0xffff 6871 6872 typedef struct _client { 6873 pid_t pid; /* set by kernel */ 6874 int flags; /* NCE_REGISTER... */ 6875 int priority; /* >100 unless root */ 6876 int events; /* pending event flags */ 6877 int event_sig; /* SIG... etc */ 6878 struct _client *next; /* set by kernel */ 6879 struct _client *prev; /* set by kernel */ 6880 } client_data; 6881 6882 static client_data *cl_data; 6883 static int n_clients; 6884 static kmutex_t client_mtx, intr_mtx; 6885 6886 static void delete_client(int); 6887 6888 #ifdef VOYAGER 6889 static uint32_t runstop_sig; 6890 static ddi_softintr_t softint_id; 6891 static uchar_t softint_flag; 6892 static int switch_debounce_time = 100; /* in milliseconds */ 6893 static timeout_id_t switch_to_id; 6894 6895 static syshw_t syshw_run_stop = { 6896 0, "Run/Stop", SH_SWITCH, 6897 SYSHW_CAN_SIGNAL_CHANGE|SYSHW_STATE_VALID, 6898 B_FALSE, { 0 } }; 6899 6900 static void 6901 syshw_get_run_stop(syshw_t *item, void *arg) 6902 { 6903 pcicdev_t *pcic = (pcicdev_t *)arg; 6904 6905 if (ddi_get8(pcic->cfg_handle, 6906 pcic->cfgaddr + PCIC_GPIO1_REG) & PCIC_GPIO_DIN) 6907 item->state = B_TRUE; 6908 else 6909 item->state = B_FALSE; 6910 } 6911 6912 6913 #endif 6914 6915 static void 6916 syshw_attach(pcicdev_t *pcic) 6917 { 6918 if (ddi_get_instance(pcic->dip) != 0) 6919 return; 6920 6921 #ifdef VOYAGER 6922 if (pcic->pc_type == PCIC_TI_PCI1250) { 6923 6924 /* 6925 * Only setup run/stop on a Voyager. 6926 * This is currently defined as 6927 * a TI1250 on a SPARC architecture. May have to make this a 6928 * property definition in the future. 6929 */ 6930 if (ddi_add_softintr(pcic->dip, 6931 DDI_SOFTINT_LOW, &softint_id, 6932 NULL, NULL, syshw_intr, 6933 (caddr_t)pcic) == DDI_SUCCESS) { 6934 runstop_sig = syshw_add2map(&syshw_run_stop, 6935 syshw_get_run_stop, pcic); 6936 mutex_init(&intr_mtx, NULL, MUTEX_DRIVER, 6937 pcic->pc_pri); 6938 ddi_put8(pcic->cfg_handle, 6939 pcic->cfgaddr + PCIC_GPIO1_REG, 6940 PCIC_GPIO_FINPUT | PCIC_GPIO_INTENBL | 6941 PCIC_GPIO_DELTA); 6942 } 6943 } 6944 #endif 6945 mutex_init(&client_mtx, "syshw client", MUTEX_DRIVER, NULL); 6946 (void) ddi_create_minor_node(pcic->dip, "syshw", S_IFCHR, 6947 SYSHW_MINOR, NULL, NULL); 6948 } 6949 6950 static void 6951 syshw_detach(pcicdev_t *pcic) 6952 { 6953 #ifdef VOYAGER 6954 if (pcic->pc_type == PCIC_TI_PCI1250) { 6955 pcic_mutex_enter(&intr_mtx); 6956 6957 /* 6958 * Turn off this interrupt. 6959 */ 6960 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + PCIC_GPIO1_REG, 6961 PCIC_GPIO_FINPUT); 6962 6963 if (switch_to_id) 6964 (void) untimeout(switch_to_id); 6965 switch_to_id = 0; 6966 softint_flag = 0; 6967 6968 pcic_mutex_exit(&intr_mtx); 6969 ddi_remove_softintr(softint_id); 6970 mutex_destroy(&intr_mtx); 6971 } 6972 #endif 6973 6974 ddi_remove_minor_node(pcic->dip, NULL); 6975 mutex_destroy(&client_mtx); 6976 } 6977 6978 static void 6979 syshw_resume(pcicdev_t *pcic) 6980 { 6981 #ifdef VOYAGER 6982 if (pcic->pc_type == PCIC_TI_PCI1250) { 6983 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + PCIC_GPIO1_REG, 6984 PCIC_GPIO_FINPUT | PCIC_GPIO_INTENBL | PCIC_GPIO_DELTA); 6985 } 6986 #else 6987 _NOTE(ARGUNUSED(pcic)) 6988 #endif 6989 } 6990 6991 #ifdef VOYAGER 6992 static uint_t 6993 syshw_intr_hi(pcicdev_t *pcic) 6994 { 6995 uchar_t regval; 6996 6997 if (pcic->pc_type != PCIC_TI_PCI1250) 6998 return (DDI_INTR_UNCLAIMED); 6999 7000 regval = ddi_get8(pcic->cfg_handle, pcic->cfgaddr + PCIC_GPIO1_REG); 7001 if (regval & PCIC_GPIO_DELTA) { 7002 pcic_mutex_enter(&intr_mtx); 7003 if (softint_flag == 0 && switch_to_id == 0) { 7004 softint_flag = 1; 7005 ddi_trigger_softintr(softint_id); 7006 } 7007 ddi_put8(pcic->cfg_handle, pcic->cfgaddr + PCIC_GPIO1_REG, 7008 regval); 7009 pcic_mutex_exit(&intr_mtx); 7010 return (DDI_INTR_CLAIMED); 7011 } 7012 7013 return (DDI_INTR_UNCLAIMED); 7014 } 7015 7016 /* 7017 * Don't deliver the signal until the debounce period has expired. 7018 * Unfortuately this means it end up as a three tier interrupt just 7019 * to indicate a bit change. 7020 */ 7021 static void 7022 syshw_debounce_to(void *arg) 7023 { 7024 _NOTE(ARGUNUSED(arg)) 7025 7026 if (switch_to_id) { 7027 pcic_mutex_enter(&intr_mtx); 7028 switch_to_id = 0; 7029 pcic_mutex_exit(&intr_mtx); 7030 syshw_send_signal(runstop_sig); 7031 return; 7032 } 7033 } 7034 7035 static uint_t 7036 syshw_intr(caddr_t arg) 7037 { 7038 _NOTE(ARGUNUSED(arg)) 7039 7040 if (softint_flag) { 7041 pcic_mutex_enter(&intr_mtx); 7042 softint_flag = 0; 7043 if (!switch_to_id) 7044 switch_to_id = timeout(syshw_debounce_to, arg, 7045 drv_usectohz(switch_debounce_time * 1000)); 7046 pcic_mutex_exit(&intr_mtx); 7047 return (DDI_INTR_CLAIMED); 7048 } 7049 return (DDI_INTR_UNCLAIMED); 7050 } 7051 #endif 7052 7053 /* 7054 * Send signals to the registered clients 7055 */ 7056 static void 7057 syshw_send_signal(int events) 7058 { 7059 client_data *ptr; 7060 proc_t *pr; 7061 int done_flag; 7062 7063 ptr = cl_data; 7064 while (ptr != NULL) { 7065 done_flag = CLIENT_CALLED; 7066 7067 if ((ptr->flags & events) && 7068 (ptr->event_sig != 0) && 7069 ((ptr->flags & done_flag) == 0)) { 7070 7071 /* 7072 * only call the process if: 7073 * it has not already received the nce signal 7074 * its signal was not zero (just in case) 7075 * and it is registered to receive this signal 7076 */ 7077 pcic_mutex_enter(&pidlock); 7078 pr = prfind(ptr->pid); 7079 pcic_mutex_exit(&pidlock); 7080 if (pr == NULL) { 7081 /* 7082 * This process has died, 7083 * so we free its memory and move on 7084 * start at the begining again: 7085 * a waste of cycles but it makes things easy.. 7086 */ 7087 delete_client(ptr->pid); 7088 ptr = cl_data; 7089 } else { 7090 ptr->events |= (events & ptr->flags & 7091 NCE_EVENT_MASK); 7092 psignal(pr, ptr->event_sig); 7093 ptr->flags |= done_flag; 7094 ptr = ptr->next; 7095 } 7096 } else { 7097 ptr = ptr->next; 7098 } 7099 } 7100 7101 ptr = cl_data; 7102 while (ptr != NULL) { 7103 ptr->flags &= ~done_flag; 7104 ptr = ptr->next; 7105 } 7106 } 7107 7108 static int 7109 syshw_open(dev_t *dev, int flag, int otyp, cred_t *cred) 7110 { 7111 _NOTE(ARGUNUSED(dev, flag, cred)) 7112 7113 if (otyp != OTYP_CHR) 7114 return (EINVAL); 7115 7116 return (0); 7117 } 7118 7119 static int 7120 syshw_close(dev_t dev, int flag, int otyp, cred_t *cred) 7121 { 7122 _NOTE(ARGUNUSED(dev, flag, otyp, cred)) 7123 7124 return (0); 7125 } 7126 7127 /* 7128 * Add a client to the list of interested processes 7129 */ 7130 static void 7131 add_client(client_data *new) 7132 { 7133 client_data * ptr; 7134 7135 n_clients++; 7136 if (cl_data == NULL) { 7137 cl_data = new; 7138 return; 7139 } 7140 7141 ptr = cl_data; 7142 while ((ptr->next != NULL) && (ptr->priority <= new->priority)) 7143 ptr = ptr->next; 7144 7145 if (ptr == cl_data) { 7146 /* at head of the list */ 7147 cl_data = new; 7148 new->next = ptr; 7149 new->prev = NULL; 7150 if (ptr != NULL) 7151 ptr->prev = new; 7152 } else { 7153 /* somewhere else in the list - insert after */ 7154 new->next = ptr->next; 7155 ptr->next = new; 7156 new->prev = ptr; 7157 if (new->next != NULL) 7158 (new->next)->prev = new; 7159 } 7160 } 7161 7162 /* 7163 * Locate a client data structure in the client list by looking for a PID match. 7164 */ 7165 static client_data * 7166 locate_client(pid_t pid) 7167 { 7168 client_data * ptr = cl_data; 7169 7170 while ((ptr != NULL) && (ptr->pid != pid)) 7171 ptr = ptr->next; 7172 7173 return (ptr); 7174 } 7175 7176 /* 7177 * Remove a client record from the client list 7178 */ 7179 static void 7180 delete_client(pid_t pid) 7181 { 7182 client_data * ptr; 7183 7184 ptr = locate_client(pid); 7185 if (ptr == NULL) 7186 return; /* hmmm!! */ 7187 7188 n_clients--; 7189 7190 if (ptr == cl_data) { 7191 /* remove the head of the list */ 7192 cl_data = ptr->next; 7193 } 7194 if (ptr->prev != NULL) 7195 (ptr->prev)->next = ptr->next; 7196 if (ptr->next != NULL) 7197 (ptr->next)->prev = ptr->prev; 7198 7199 kmem_free(ptr, sizeof (client_data)); 7200 } 7201 7202 static void 7203 unregister_event_client() 7204 { 7205 pcic_mutex_enter(&client_mtx); 7206 delete_client(ddi_get_pid()); 7207 pcic_mutex_exit(&client_mtx); 7208 } 7209 7210 static int 7211 register_event_client(client_data *u_client) 7212 { 7213 int error; 7214 client_data * client; 7215 7216 pcic_mutex_enter(&client_mtx); 7217 client = locate_client(ddi_get_pid()); 7218 if (client) { 7219 /* 7220 * we are re-registering ourself 7221 * so we delete the previous entry 7222 */ 7223 delete_client(ddi_get_pid()); 7224 } 7225 7226 client = (client_data *)kmem_alloc(sizeof (client_data), KM_SLEEP); 7227 7228 if (client) { 7229 client->pid = ddi_get_pid(); 7230 client->priority = u_client->priority; 7231 client->flags = u_client->flags & NCE_EVENT_MASK; 7232 client->events = 0; 7233 client->event_sig = u_client->event_sig; 7234 client->next = NULL; 7235 client->prev = NULL; 7236 add_client(client); 7237 error = 0; 7238 } else 7239 error = EIO; 7240 7241 pcic_mutex_exit(&client_mtx); 7242 return (error); 7243 } 7244 7245 /* 7246 * Read the currently pending event flags for the process in question 7247 */ 7248 static int 7249 check_events_pending(caddr_t data) 7250 { 7251 client_data * client; 7252 int error = 0; 7253 7254 pcic_mutex_enter(&client_mtx); 7255 client = locate_client(ddi_get_pid()); 7256 if (client) { 7257 if (copyout((caddr_t)&client->events, data, sizeof (int))) 7258 error = EFAULT; 7259 else 7260 client->events = 0; 7261 } else 7262 error = EINVAL; 7263 7264 pcic_mutex_exit(&client_mtx); 7265 return (error); 7266 } 7267 7268 7269 #define MAXITEMS 8 7270 static syshw_t *syshw_map[MAXITEMS]; 7271 static void (*syshw_getfuncs[MAXITEMS])(syshw_t *, void *); 7272 static void *syshw_getfunc_args[MAXITEMS]; 7273 static int nsyshw_items = 0; 7274 #define NSYSHW_ITEMS nsyshw_items 7275 7276 static uint32_t 7277 syshw_add2map(syshw_t *item, void (*getfunc)(syshw_t *, void *), void *getarg) 7278 { 7279 uint32_t rval = (1 << nsyshw_items); 7280 if (nsyshw_items == MAXITEMS) 7281 return (0); 7282 item->hw_id = nsyshw_items; 7283 syshw_map[nsyshw_items] = item; 7284 syshw_getfuncs[nsyshw_items] = getfunc; 7285 syshw_getfunc_args[nsyshw_items] = getarg; 7286 nsyshw_items++; 7287 return (rval); 7288 } 7289 7290 static int 7291 syshw_ioctl(dev_t dev, int cmd, intptr_t ioctldata, int mode, 7292 cred_t *cred, int *rval) 7293 { 7294 caddr_t data = (caddr_t)ioctldata; 7295 syshw_t sh; 7296 hwev_t hwev; 7297 client_data dummy_client; 7298 int rc = 0, i; 7299 7300 _NOTE(ARGUNUSED(dev, mode, cred, rval)) 7301 7302 switch (cmd) { 7303 default: 7304 rc = EINVAL; 7305 break; 7306 7307 case SYSHW_GET_ITEM: 7308 case SYSHW_GET_ITEM_MAXVALUES: 7309 if (copyin(data, (caddr_t)&sh, sizeof (sh))) { 7310 rc = EFAULT; 7311 break; 7312 } 7313 7314 if (sh.hw_id >= NSYSHW_ITEMS) { 7315 rc = EINVAL; 7316 break; 7317 } 7318 7319 sh = *syshw_map[sh.hw_id]; 7320 if (!sh.id_string[0]) { 7321 rc = ENOTTY; 7322 break; 7323 } 7324 if (cmd == SYSHW_GET_ITEM) { 7325 if (syshw_getfuncs[sh.hw_id]) 7326 syshw_getfuncs[sh.hw_id](&sh, 7327 syshw_getfunc_args[sh.hw_id]); 7328 else 7329 rc = ENOTTY; 7330 } 7331 7332 if (copyout((caddr_t)&sh, data, sizeof (sh))) { 7333 rc = EFAULT; 7334 break; 7335 } 7336 break; 7337 7338 case SYSHW_SET_ITEM: 7339 if (copyin(data, (caddr_t)&sh, sizeof (sh))) { 7340 rc = EFAULT; 7341 break; 7342 } 7343 7344 if (sh.hw_id >= NSYSHW_ITEMS || 7345 !syshw_map[sh.hw_id]->id_string[0] || 7346 !(syshw_map[sh.hw_id]->capabilities & 7347 (SYSHW_STATE_MODIFY | SYSHW_VAL0_MODIFY | 7348 SYSHW_VAL1_MODIFY | SYSHW_VAL2_MODIFY | 7349 SYSHW_VAL3_MODIFY))) { 7350 rc = EINVAL; 7351 break; 7352 } 7353 7354 switch (sh.hw_id) { 7355 default: 7356 rc = EINVAL; 7357 break; 7358 } 7359 break; 7360 7361 case SYSHW_EVREG: 7362 if (copyin(data, (caddr_t)&hwev, sizeof (hwev))) { 7363 rc = EFAULT; 7364 break; 7365 } 7366 7367 for (i = 0; i < NSYSHW_ITEMS; i++) { 7368 if (hwev.events & (1 << i) && 7369 !(syshw_map[i]->capabilities & 7370 SYSHW_CAN_SIGNAL_CHANGE)) { 7371 rc = EINVAL; 7372 break; 7373 } 7374 } 7375 if (hwev.event_sig != SIGUSR1 && hwev.event_sig != SIGUSR2) 7376 rc = EINVAL; 7377 7378 if (!rc) { 7379 dummy_client.priority = 100; 7380 dummy_client.flags = hwev.events; 7381 dummy_client.event_sig = hwev.event_sig; 7382 rc = register_event_client(&dummy_client); 7383 } 7384 break; 7385 7386 case SYSHW_EVUNREG: 7387 unregister_event_client(); 7388 break; 7389 7390 case SYSHW_CHKEV: 7391 rc = check_events_pending(data); 7392 break; 7393 } 7394 return (rc); 7395 } 7396