xref: /illumos-gate/usr/src/uts/common/io/pciex/pcieb.c (revision a9c12afd)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 /*
27  * Common x86 and SPARC PCI-E to PCI bus bridge nexus driver
28  */
29 
30 #include <sys/sysmacros.h>
31 #include <sys/conf.h>
32 #include <sys/kmem.h>
33 #include <sys/debug.h>
34 #include <sys/modctl.h>
35 #include <sys/autoconf.h>
36 #include <sys/ddi_impldefs.h>
37 #include <sys/pci.h>
38 #include <sys/ddi.h>
39 #include <sys/sunddi.h>
40 #include <sys/sunndi.h>
41 #include <sys/fm/util.h>
42 #include <sys/pci_cap.h>
43 #include <sys/pci_impl.h>
44 #include <sys/pcie_impl.h>
45 #include <sys/open.h>
46 #include <sys/stat.h>
47 #include <sys/file.h>
48 #include <sys/promif.h>		/* prom_printf */
49 #include <sys/disp.h>
50 #include <sys/pcie_pwr.h>
51 #include <sys/hotplug/pci/pcie_hp.h>
52 #include "pcieb.h"
53 #ifdef PX_PLX
54 #include <io/pciex/pcieb_plx.h>
55 #endif /* PX_PLX */
56 
57 /*LINTLIBRARY*/
58 
59 /* panic flag */
60 int pcieb_die = PF_ERR_FATAL_FLAGS;
61 
62 /* flag to turn on MSI support */
63 int pcieb_enable_msi = 1;
64 
65 #if defined(DEBUG)
66 uint_t pcieb_dbg_print = 0;
67 
68 static char *pcieb_debug_sym [] = {	/* same sequence as pcieb_debug_bit */
69 	/*  0 */ "attach",
70 	/*  1 */ "pwr",
71 	/*  2 */ "intr"
72 };
73 #endif /* DEBUG */
74 
75 static int pcieb_bus_map(dev_info_t *, dev_info_t *, ddi_map_req_t *, off_t,
76 	off_t, caddr_t *);
77 static int pcieb_ctlops(dev_info_t *, dev_info_t *, ddi_ctl_enum_t, void *,
78 	void *);
79 static int pcieb_fm_init(pcieb_devstate_t *pcieb_p);
80 static void pcieb_fm_fini(pcieb_devstate_t *pcieb_p);
81 static int pcieb_fm_init_child(dev_info_t *dip, dev_info_t *cdip, int cap,
82     ddi_iblock_cookie_t *ibc_p);
83 static int pcieb_dma_allochdl(dev_info_t *dip, dev_info_t *rdip,
84 	ddi_dma_attr_t *attr_p, int (*waitfp)(caddr_t), caddr_t arg,
85 	ddi_dma_handle_t *handlep);
86 static int pcieb_dma_mctl(dev_info_t *dip, dev_info_t *rdip,
87 	ddi_dma_handle_t handle, enum ddi_dma_ctlops cmd, off_t *offp,
88 	size_t *lenp, caddr_t *objp, uint_t cache_flags);
89 static int pcieb_intr_ops(dev_info_t *dip, dev_info_t *rdip,
90 	ddi_intr_op_t intr_op, ddi_intr_handle_impl_t *hdlp, void *result);
91 
92 static struct bus_ops pcieb_bus_ops = {
93 	BUSO_REV,
94 	pcieb_bus_map,
95 	0,
96 	0,
97 	0,
98 	i_ddi_map_fault,
99 	ddi_dma_map,
100 	pcieb_dma_allochdl,
101 	ddi_dma_freehdl,
102 	ddi_dma_bindhdl,
103 	ddi_dma_unbindhdl,
104 	ddi_dma_flush,
105 	ddi_dma_win,
106 	pcieb_dma_mctl,
107 	pcieb_ctlops,
108 	ddi_bus_prop_op,
109 	ndi_busop_get_eventcookie,	/* (*bus_get_eventcookie)();	*/
110 	ndi_busop_add_eventcall,	/* (*bus_add_eventcall)();	*/
111 	ndi_busop_remove_eventcall,	/* (*bus_remove_eventcall)();	*/
112 	ndi_post_event,			/* (*bus_post_event)();		*/
113 	NULL,				/* (*bus_intr_ctl)();		*/
114 	NULL,				/* (*bus_config)(); 		*/
115 	NULL,				/* (*bus_unconfig)(); 		*/
116 	pcieb_fm_init_child,		/* (*bus_fm_init)(); 		*/
117 	NULL,				/* (*bus_fm_fini)(); 		*/
118 	i_ndi_busop_access_enter,	/* (*bus_fm_access_enter)(); 	*/
119 	i_ndi_busop_access_exit,	/* (*bus_fm_access_exit)(); 	*/
120 	pcie_bus_power,			/* (*bus_power)(); 	*/
121 	pcieb_intr_ops,			/* (*bus_intr_op)(); 		*/
122 	pcie_hp_common_ops		/* (*bus_hp_op)(); 		*/
123 };
124 
125 static int	pcieb_open(dev_t *, int, int, cred_t *);
126 static int	pcieb_close(dev_t, int, int, cred_t *);
127 static int	pcieb_ioctl(dev_t, int, intptr_t, int, cred_t *, int *);
128 static int	pcieb_info(dev_info_t *, ddi_info_cmd_t, void *, void **);
129 static uint_t 	pcieb_intr_handler(caddr_t arg1, caddr_t arg2);
130 
131 /* PM related functions */
132 static int	pcieb_pwr_setup(dev_info_t *dip);
133 static int	pcieb_pwr_init_and_raise(dev_info_t *dip, pcie_pwr_t *pwr_p);
134 static void	pcieb_pwr_teardown(dev_info_t *dip);
135 static int	pcieb_pwr_disable(dev_info_t *dip);
136 
137 /* Hotplug related functions */
138 static void pcieb_id_props(pcieb_devstate_t *pcieb);
139 
140 /*
141  * soft state pointer
142  */
143 void *pcieb_state;
144 
145 static struct cb_ops pcieb_cb_ops = {
146 	pcieb_open,			/* open */
147 	pcieb_close,			/* close */
148 	nodev,				/* strategy */
149 	nodev,				/* print */
150 	nodev,				/* dump */
151 	nodev,				/* read */
152 	nodev,				/* write */
153 	pcieb_ioctl,			/* ioctl */
154 	nodev,				/* devmap */
155 	nodev,				/* mmap */
156 	nodev,				/* segmap */
157 	nochpoll,			/* poll */
158 	pcie_prop_op,			/* cb_prop_op */
159 	NULL,				/* streamtab */
160 	D_NEW | D_MP | D_HOTPLUG,	/* Driver compatibility flag */
161 	CB_REV,				/* rev */
162 	nodev,				/* int (*cb_aread)() */
163 	nodev				/* int (*cb_awrite)() */
164 };
165 
166 static int	pcieb_probe(dev_info_t *);
167 static int	pcieb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd);
168 static int	pcieb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd);
169 
170 static struct dev_ops pcieb_ops = {
171 	DEVO_REV,		/* devo_rev */
172 	0,			/* refcnt  */
173 	pcieb_info,		/* info */
174 	nulldev,		/* identify */
175 	pcieb_probe,		/* probe */
176 	pcieb_attach,		/* attach */
177 	pcieb_detach,		/* detach */
178 	nulldev,		/* reset */
179 	&pcieb_cb_ops,		/* driver operations */
180 	&pcieb_bus_ops,		/* bus operations */
181 	pcie_power,		/* power */
182 	ddi_quiesce_not_needed,		/* quiesce */
183 };
184 
185 /*
186  * Module linkage information for the kernel.
187  */
188 
189 static struct modldrv modldrv = {
190 	&mod_driverops, /* Type of module */
191 	"PCIe bridge/switch driver",
192 	&pcieb_ops,	/* driver ops */
193 };
194 
195 static struct modlinkage modlinkage = {
196 	MODREV_1,
197 	(void *)&modldrv,
198 	NULL
199 };
200 
201 /*
202  * forward function declarations:
203  */
204 static void	pcieb_uninitchild(dev_info_t *);
205 static int 	pcieb_initchild(dev_info_t *child);
206 static void	pcieb_create_ranges_prop(dev_info_t *, ddi_acc_handle_t);
207 static boolean_t pcieb_is_pcie_device_type(dev_info_t *dip);
208 
209 /* interrupt related declarations */
210 static int	pcieb_msi_supported(dev_info_t *);
211 static int	pcieb_intr_attach(pcieb_devstate_t *pcieb);
212 static int	pcieb_intr_init(pcieb_devstate_t *pcieb_p, int intr_type);
213 static void	pcieb_intr_fini(pcieb_devstate_t *pcieb_p);
214 
215 int
216 _init(void)
217 {
218 	int e;
219 
220 	if ((e = ddi_soft_state_init(&pcieb_state, sizeof (pcieb_devstate_t),
221 	    1)) == 0 && (e = mod_install(&modlinkage)) != 0)
222 		ddi_soft_state_fini(&pcieb_state);
223 	return (e);
224 }
225 
226 int
227 _fini(void)
228 {
229 	int e;
230 
231 	if ((e = mod_remove(&modlinkage)) == 0) {
232 		ddi_soft_state_fini(&pcieb_state);
233 	}
234 	return (e);
235 }
236 
237 int
238 _info(struct modinfo *modinfop)
239 {
240 	return (mod_info(&modlinkage, modinfop));
241 }
242 
243 /* ARGSUSED */
244 static int
245 pcieb_info(dev_info_t *dip, ddi_info_cmd_t infocmd, void *arg, void **result)
246 {
247 	minor_t		minor = getminor((dev_t)arg);
248 	int		instance = PCI_MINOR_NUM_TO_INSTANCE(minor);
249 	pcieb_devstate_t *pcieb = ddi_get_soft_state(pcieb_state, instance);
250 	int		ret = DDI_SUCCESS;
251 
252 	switch (infocmd) {
253 	case DDI_INFO_DEVT2INSTANCE:
254 		*result = (void *)(intptr_t)instance;
255 		break;
256 	case DDI_INFO_DEVT2DEVINFO:
257 		if (pcieb == NULL) {
258 			ret = DDI_FAILURE;
259 			break;
260 		}
261 
262 		*result = (void *)pcieb->pcieb_dip;
263 		break;
264 	default:
265 		ret = DDI_FAILURE;
266 		break;
267 	}
268 
269 	return (ret);
270 }
271 
272 
273 /*ARGSUSED*/
274 static int
275 pcieb_probe(dev_info_t *devi)
276 {
277 	return (DDI_PROBE_SUCCESS);
278 }
279 
280 static int
281 pcieb_attach(dev_info_t *devi, ddi_attach_cmd_t cmd)
282 {
283 	int			instance;
284 	char			device_type[8];
285 	pcieb_devstate_t	*pcieb;
286 	pcie_bus_t		*bus_p = PCIE_DIP2UPBUS(devi);
287 	ddi_acc_handle_t	config_handle = bus_p->bus_cfg_hdl;
288 
289 	switch (cmd) {
290 	case DDI_RESUME:
291 		(void) pcie_pwr_resume(devi);
292 		return (DDI_SUCCESS);
293 
294 	default:
295 		return (DDI_FAILURE);
296 
297 	case DDI_ATTACH:
298 		break;
299 	}
300 
301 	if (!(PCIE_IS_BDG(bus_p))) {
302 		PCIEB_DEBUG(DBG_ATTACH, devi, "This is not a switch or"
303 		" bridge\n");
304 		return (DDI_FAILURE);
305 	}
306 
307 	/*
308 	 * If PCIE_LINKCTL_LINK_DISABLE bit in the PCIe Config
309 	 * Space (PCIe Capability Link Control Register) is set,
310 	 * then do not bind the driver.
311 	 */
312 	if (PCIE_CAP_GET(16, bus_p, PCIE_LINKCTL) & PCIE_LINKCTL_LINK_DISABLE)
313 		return (DDI_FAILURE);
314 
315 	/*
316 	 * Allocate and get soft state structure.
317 	 */
318 	instance = ddi_get_instance(devi);
319 	if (ddi_soft_state_zalloc(pcieb_state, instance) != DDI_SUCCESS)
320 		return (DDI_FAILURE);
321 	pcieb = ddi_get_soft_state(pcieb_state, instance);
322 	pcieb->pcieb_dip = devi;
323 
324 	if ((pcieb_fm_init(pcieb)) != DDI_SUCCESS) {
325 		PCIEB_DEBUG(DBG_ATTACH, devi, "Failed in pcieb_fm_init\n");
326 		goto fail;
327 	}
328 	pcieb->pcieb_init_flags |= PCIEB_INIT_FM;
329 
330 	mutex_init(&pcieb->pcieb_mutex, NULL, MUTEX_DRIVER, NULL);
331 	mutex_init(&pcieb->pcieb_err_mutex, NULL, MUTEX_DRIVER,
332 	    (void *)pcieb->pcieb_fm_ibc);
333 	mutex_init(&pcieb->pcieb_peek_poke_mutex, NULL, MUTEX_DRIVER,
334 	    (void *)pcieb->pcieb_fm_ibc);
335 
336 	/* create special properties for device identification */
337 	pcieb_id_props(pcieb);
338 
339 	/*
340 	 * Power management setup. This also makes sure that switch/bridge
341 	 * is at D0 during attach.
342 	 */
343 	if (pwr_common_setup(devi) != DDI_SUCCESS) {
344 		PCIEB_DEBUG(DBG_PWR, devi, "pwr_common_setup failed\n");
345 		goto fail;
346 	}
347 
348 	if (pcieb_pwr_setup(devi) != DDI_SUCCESS) {
349 		PCIEB_DEBUG(DBG_PWR, devi, "pxb_pwr_setup failed \n");
350 		goto fail;
351 	}
352 
353 	/*
354 	 * Make sure the "device_type" property exists.
355 	 */
356 	if (pcieb_is_pcie_device_type(devi))
357 		(void) strcpy(device_type, "pciex");
358 	else
359 		(void) strcpy(device_type, "pci");
360 
361 	(void) ddi_prop_update_string(DDI_DEV_T_NONE, devi,
362 	    "device_type", device_type);
363 
364 	/*
365 	 * Check whether the "ranges" property is present.
366 	 * Otherwise create the ranges property by reading
367 	 * the configuration registers
368 	 */
369 	if (ddi_prop_exists(DDI_DEV_T_ANY, devi, DDI_PROP_DONTPASS,
370 	    "ranges") == 0) {
371 		pcieb_create_ranges_prop(devi, config_handle);
372 	}
373 
374 	if (PCIE_IS_PCI_BDG(bus_p))
375 		pcieb_set_pci_perf_parameters(devi, config_handle);
376 
377 #ifdef PX_PLX
378 	pcieb_attach_plx_workarounds(pcieb);
379 #endif /* PX_PLX */
380 
381 	if (pcie_init(devi, NULL) != DDI_SUCCESS)
382 		goto fail;
383 
384 	/*
385 	 * Initialize interrupt handlers. Ignore return value.
386 	 */
387 	(void) pcieb_intr_attach(pcieb);
388 
389 	(void) pcie_hpintr_enable(devi);
390 
391 	/* Do any platform specific workarounds needed at this time */
392 	pcieb_plat_attach_workaround(devi);
393 
394 	/*
395 	 * If this is a root port, determine and set the max payload size.
396 	 * Since this will involve scanning the fabric, all error enabling
397 	 * and sw workarounds should be in place before doing this.
398 	 */
399 	if (PCIE_IS_RP(bus_p))
400 		pcie_init_root_port_mps(devi);
401 
402 	ddi_report_dev(devi);
403 	return (DDI_SUCCESS);
404 
405 fail:
406 	(void) pcieb_detach(devi, DDI_DETACH);
407 	return (DDI_FAILURE);
408 }
409 
410 static int
411 pcieb_detach(dev_info_t *devi, ddi_detach_cmd_t cmd)
412 {
413 	pcieb_devstate_t *pcieb;
414 	int error = DDI_SUCCESS;
415 
416 	switch (cmd) {
417 	case DDI_SUSPEND:
418 		error = pcie_pwr_suspend(devi);
419 		return (error);
420 
421 	case DDI_DETACH:
422 		break;
423 
424 	default:
425 		return (DDI_FAILURE);
426 	}
427 
428 	pcieb = ddi_get_soft_state(pcieb_state, ddi_get_instance(devi));
429 
430 	/* disable hotplug interrupt */
431 	(void) pcie_hpintr_disable(devi);
432 
433 	/* remove interrupt handlers */
434 	pcieb_intr_fini(pcieb);
435 
436 	/* uninitialize inband PCI-E HPC if present */
437 	(void) pcie_uninit(devi);
438 
439 	(void) ddi_prop_remove(DDI_DEV_T_NONE, devi, "device_type");
440 
441 	(void) ndi_prop_remove(DDI_DEV_T_NONE, pcieb->pcieb_dip,
442 	    "pcie_ce_mask");
443 
444 	if (pcieb->pcieb_init_flags & PCIEB_INIT_FM)
445 		pcieb_fm_fini(pcieb);
446 
447 	pcieb_pwr_teardown(devi);
448 	pwr_common_teardown(devi);
449 
450 	mutex_destroy(&pcieb->pcieb_peek_poke_mutex);
451 	mutex_destroy(&pcieb->pcieb_err_mutex);
452 	mutex_destroy(&pcieb->pcieb_mutex);
453 
454 	/*
455 	 * And finally free the per-pci soft state.
456 	 */
457 	ddi_soft_state_free(pcieb_state, ddi_get_instance(devi));
458 
459 	return (DDI_SUCCESS);
460 }
461 
462 static int
463 pcieb_bus_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp,
464     off_t offset, off_t len, caddr_t *vaddrp)
465 {
466 	dev_info_t *pdip;
467 
468 	if (PCIE_IS_RP(PCIE_DIP2BUS(dip)) && mp->map_handlep != NULL) {
469 		ddi_acc_impl_t *hdlp =
470 		    (ddi_acc_impl_t *)(mp->map_handlep)->ah_platform_private;
471 
472 		pcieb_set_prot_scan(dip, hdlp);
473 	}
474 	pdip = (dev_info_t *)DEVI(dip)->devi_parent;
475 	return ((DEVI(pdip)->devi_ops->devo_bus_ops->bus_map)(pdip, rdip, mp,
476 	    offset, len, vaddrp));
477 }
478 
479 static int
480 pcieb_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_ctl_enum_t ctlop,
481     void *arg, void *result)
482 {
483 	pci_regspec_t *drv_regp;
484 	int	reglen;
485 	int	rn;
486 	int	totreg;
487 	pcieb_devstate_t *pcieb = ddi_get_soft_state(pcieb_state,
488 	    ddi_get_instance(dip));
489 	struct detachspec *ds;
490 	struct attachspec *as;
491 
492 	switch (ctlop) {
493 	case DDI_CTLOPS_REPORTDEV:
494 		if (rdip == (dev_info_t *)0)
495 			return (DDI_FAILURE);
496 
497 		if (ddi_get_parent(rdip) == dip) {
498 			cmn_err(CE_CONT, "?PCIE-device: %s@%s, %s%d\n",
499 			    ddi_node_name(rdip), ddi_get_name_addr(rdip),
500 			    ddi_driver_name(rdip), ddi_get_instance(rdip));
501 		}
502 
503 		/* Pass it up for fabric sync */
504 		(void) ddi_ctlops(dip, rdip, ctlop, arg, result);
505 		return (DDI_SUCCESS);
506 
507 	case DDI_CTLOPS_INITCHILD:
508 		return (pcieb_initchild((dev_info_t *)arg));
509 
510 	case DDI_CTLOPS_UNINITCHILD:
511 		pcieb_uninitchild((dev_info_t *)arg);
512 		return (DDI_SUCCESS);
513 
514 	case DDI_CTLOPS_SIDDEV:
515 		return (DDI_SUCCESS);
516 
517 	case DDI_CTLOPS_REGSIZE:
518 	case DDI_CTLOPS_NREGS:
519 		if (rdip == (dev_info_t *)0)
520 			return (DDI_FAILURE);
521 		break;
522 
523 	case DDI_CTLOPS_PEEK:
524 	case DDI_CTLOPS_POKE:
525 		return (pcieb_plat_peekpoke(dip, rdip, ctlop, arg, result));
526 	case DDI_CTLOPS_ATTACH:
527 		if (!pcie_is_child(dip, rdip))
528 			return (DDI_SUCCESS);
529 
530 		as = (struct attachspec *)arg;
531 		switch (as->when) {
532 		case DDI_PRE:
533 			if (as->cmd == DDI_RESUME) {
534 				pcie_clear_errors(rdip);
535 				if (pcieb_plat_ctlops(rdip, ctlop, arg) !=
536 				    DDI_SUCCESS)
537 					return (DDI_FAILURE);
538 			}
539 
540 			if (as->cmd == DDI_ATTACH)
541 				return (pcie_pm_hold(dip));
542 
543 			return (DDI_SUCCESS);
544 
545 		case DDI_POST:
546 			if (as->cmd == DDI_ATTACH &&
547 			    as->result != DDI_SUCCESS) {
548 				/*
549 				 * Attach failed for the child device. The child
550 				 * driver may have made PM calls before the
551 				 * attach failed. pcie_pm_remove_child() should
552 				 * cleanup PM state and holds (if any)
553 				 * associated with the child device.
554 				 */
555 				return (pcie_pm_remove_child(dip, rdip));
556 			}
557 
558 			if (as->result == DDI_SUCCESS) {
559 				pf_init(rdip, (void *)pcieb->pcieb_fm_ibc,
560 				    as->cmd);
561 
562 				(void) pcieb_plat_ctlops(rdip, ctlop, arg);
563 			}
564 
565 			/*
566 			 * For empty hotplug-capable slots, we should explicitly
567 			 * disable the errors, so that we won't panic upon
568 			 * unsupported hotplug messages.
569 			 */
570 			if ((!ddi_prop_exists(DDI_DEV_T_ANY, rdip,
571 			    DDI_PROP_DONTPASS, "hotplug-capable")) ||
572 			    ddi_get_child(rdip)) {
573 				(void) pcie_postattach_child(rdip);
574 				return (DDI_SUCCESS);
575 			}
576 
577 			pcie_disable_errors(rdip);
578 
579 			return (DDI_SUCCESS);
580 		default:
581 			break;
582 		}
583 		return (DDI_SUCCESS);
584 
585 	case DDI_CTLOPS_DETACH:
586 		if (!pcie_is_child(dip, rdip))
587 			return (DDI_SUCCESS);
588 
589 		ds = (struct detachspec *)arg;
590 		switch (ds->when) {
591 		case DDI_PRE:
592 			pf_fini(rdip, ds->cmd);
593 			return (DDI_SUCCESS);
594 
595 		case DDI_POST:
596 			if (pcieb_plat_ctlops(rdip, ctlop, arg) != DDI_SUCCESS)
597 				return (DDI_FAILURE);
598 			if (ds->cmd == DDI_DETACH &&
599 			    ds->result == DDI_SUCCESS) {
600 				return (pcie_pm_remove_child(dip, rdip));
601 			}
602 			return (DDI_SUCCESS);
603 		default:
604 			break;
605 		}
606 		return (DDI_SUCCESS);
607 	default:
608 		return (ddi_ctlops(dip, rdip, ctlop, arg, result));
609 	}
610 
611 	*(int *)result = 0;
612 	if (ddi_getlongprop(DDI_DEV_T_ANY, rdip,
613 	    DDI_PROP_DONTPASS | DDI_PROP_CANSLEEP, "reg", (caddr_t)&drv_regp,
614 	    &reglen) != DDI_SUCCESS)
615 		return (DDI_FAILURE);
616 
617 	totreg = reglen / sizeof (pci_regspec_t);
618 	if (ctlop == DDI_CTLOPS_NREGS)
619 		*(int *)result = totreg;
620 	else if (ctlop == DDI_CTLOPS_REGSIZE) {
621 		rn = *(int *)arg;
622 		if (rn >= totreg) {
623 			kmem_free(drv_regp, reglen);
624 			return (DDI_FAILURE);
625 		}
626 
627 		*(off_t *)result = drv_regp[rn].pci_size_low |
628 		    ((uint64_t)drv_regp[rn].pci_size_hi << 32);
629 	}
630 
631 	kmem_free(drv_regp, reglen);
632 	return (DDI_SUCCESS);
633 }
634 
635 /*
636  * name_child
637  *
638  * This function is called from init_child to name a node. It is
639  * also passed as a callback for node merging functions.
640  *
641  * return value: DDI_SUCCESS, DDI_FAILURE
642  */
643 static int
644 pcieb_name_child(dev_info_t *child, char *name, int namelen)
645 {
646 	pci_regspec_t *pci_rp;
647 	uint_t device, func;
648 	char **unit_addr;
649 	uint_t n;
650 
651 	/*
652 	 * For .conf nodes, use unit-address property as name
653 	 */
654 	if (ndi_dev_is_persistent_node(child) == 0) {
655 		if (ddi_prop_lookup_string_array(DDI_DEV_T_ANY, child,
656 		    DDI_PROP_DONTPASS, "unit-address", &unit_addr, &n) !=
657 		    DDI_PROP_SUCCESS) {
658 			cmn_err(CE_WARN,
659 			    "cannot find unit-address in %s.conf",
660 			    ddi_driver_name(child));
661 			return (DDI_FAILURE);
662 		}
663 		if (n != 1 || *unit_addr == NULL || **unit_addr == 0) {
664 			cmn_err(CE_WARN, "unit-address property in %s.conf"
665 			    " not well-formed", ddi_driver_name(child));
666 			ddi_prop_free(unit_addr);
667 			return (DDI_FAILURE);
668 		}
669 		(void) snprintf(name, namelen, "%s", *unit_addr);
670 		ddi_prop_free(unit_addr);
671 		return (DDI_SUCCESS);
672 	}
673 
674 	/*
675 	 * Get the address portion of the node name based on
676 	 * the function and device number.
677 	 */
678 	if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, child,
679 	    DDI_PROP_DONTPASS, "reg", (int **)&pci_rp, &n) != DDI_SUCCESS) {
680 		return (DDI_FAILURE);
681 	}
682 
683 	/* copy the device identifications */
684 	device = PCI_REG_DEV_G(pci_rp[0].pci_phys_hi);
685 	func = PCI_REG_FUNC_G(pci_rp[0].pci_phys_hi);
686 
687 	if (pcie_ari_is_enabled(ddi_get_parent(child))
688 	    == PCIE_ARI_FORW_ENABLED) {
689 		func = (device << 3) | func;
690 		device = 0;
691 	}
692 
693 	if (func != 0)
694 		(void) snprintf(name, namelen, "%x,%x", device, func);
695 	else
696 		(void) snprintf(name, namelen, "%x", device);
697 
698 	ddi_prop_free(pci_rp);
699 	return (DDI_SUCCESS);
700 }
701 
702 static int
703 pcieb_initchild(dev_info_t *child)
704 {
705 	char name[MAXNAMELEN];
706 	int result = DDI_FAILURE;
707 	pcieb_devstate_t *pcieb =
708 	    (pcieb_devstate_t *)ddi_get_soft_state(pcieb_state,
709 	    ddi_get_instance(ddi_get_parent(child)));
710 
711 	/*
712 	 * Name the child
713 	 */
714 	if (pcieb_name_child(child, name, MAXNAMELEN) != DDI_SUCCESS) {
715 		result = DDI_FAILURE;
716 		goto done;
717 	}
718 	ddi_set_name_addr(child, name);
719 
720 	/*
721 	 * Pseudo nodes indicate a prototype node with per-instance
722 	 * properties to be merged into the real h/w device node.
723 	 * The interpretation of the unit-address is DD[,F]
724 	 * where DD is the device id and F is the function.
725 	 */
726 	if (ndi_dev_is_persistent_node(child) == 0) {
727 		extern int pci_allow_pseudo_children;
728 
729 		/*
730 		 * Try to merge the properties from this prototype
731 		 * node into real h/w nodes.
732 		 */
733 		if (ndi_merge_node(child, pcieb_name_child) != DDI_SUCCESS) {
734 			/*
735 			 * Merged ok - return failure to remove the node.
736 			 */
737 			ddi_set_name_addr(child, NULL);
738 			result = DDI_FAILURE;
739 			goto done;
740 		}
741 
742 		/* workaround for ddivs to run under PCI-E */
743 		if (pci_allow_pseudo_children) {
744 			result = DDI_SUCCESS;
745 			goto done;
746 		}
747 
748 		/*
749 		 * The child was not merged into a h/w node,
750 		 * but there's not much we can do with it other
751 		 * than return failure to cause the node to be removed.
752 		 */
753 		cmn_err(CE_WARN, "!%s@%s: %s.conf properties not merged",
754 		    ddi_driver_name(child), ddi_get_name_addr(child),
755 		    ddi_driver_name(child));
756 		ddi_set_name_addr(child, NULL);
757 		result = DDI_NOT_WELL_FORMED;
758 		goto done;
759 	}
760 
761 	/* platform specific initchild */
762 	pcieb_plat_initchild(child);
763 
764 	if (pcie_pm_hold(pcieb->pcieb_dip) != DDI_SUCCESS) {
765 		PCIEB_DEBUG(DBG_PWR, pcieb->pcieb_dip,
766 		    "INITCHILD: px_pm_hold failed\n");
767 		result = DDI_FAILURE;
768 		goto done;
769 	}
770 	/* Any return from here must call pcie_pm_release */
771 
772 	/*
773 	 * If configuration registers were previously saved by
774 	 * child (before it entered D3), then let the child do the
775 	 * restore to set up the config regs as it'll first need to
776 	 * power the device out of D3.
777 	 */
778 	if (ddi_prop_exists(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS,
779 	    "config-regs-saved-by-child") == 1) {
780 		PCIEB_DEBUG(DBG_PWR, ddi_get_parent(child),
781 		    "INITCHILD: config regs to be restored by child"
782 		    " for %s@%s\n", ddi_node_name(child),
783 		    ddi_get_name_addr(child));
784 
785 		result = DDI_SUCCESS;
786 		goto cleanup;
787 	}
788 
789 	PCIEB_DEBUG(DBG_PWR, ddi_get_parent(child),
790 	    "INITCHILD: config regs setup for %s@%s\n",
791 	    ddi_node_name(child), ddi_get_name_addr(child));
792 
793 	pcie_init_dom(child);
794 
795 	if (pcie_initchild(child) != DDI_SUCCESS) {
796 		result = DDI_FAILURE;
797 		pcie_fini_dom(child);
798 		goto cleanup;
799 	}
800 
801 #ifdef PX_PLX
802 	if (pcieb_init_plx_workarounds(pcieb, child) == DDI_FAILURE) {
803 		result = DDI_FAILURE;
804 		pcie_fini_dom(child);
805 		goto cleanup;
806 	}
807 #endif /* PX_PLX */
808 
809 	result = DDI_SUCCESS;
810 cleanup:
811 	pcie_pm_release(pcieb->pcieb_dip);
812 done:
813 	return (result);
814 }
815 
816 static void
817 pcieb_uninitchild(dev_info_t *dip)
818 {
819 
820 	pcie_uninitchild(dip);
821 
822 	pcieb_plat_uninitchild(dip);
823 
824 	ddi_set_name_addr(dip, NULL);
825 
826 	/*
827 	 * Strip the node to properly convert it back to prototype form
828 	 */
829 	ddi_remove_minor_node(dip, NULL);
830 
831 	ddi_prop_remove_all(dip);
832 }
833 
834 static boolean_t
835 pcieb_is_pcie_device_type(dev_info_t *dip)
836 {
837 	pcie_bus_t	*bus_p = PCIE_DIP2BUS(dip);
838 
839 	if (PCIE_IS_SW(bus_p) || PCIE_IS_RP(bus_p) || PCIE_IS_PCI2PCIE(bus_p))
840 		return (B_TRUE);
841 
842 	return (B_FALSE);
843 }
844 
845 static int
846 pcieb_intr_attach(pcieb_devstate_t *pcieb)
847 {
848 	int			intr_types;
849 	dev_info_t		*dip = pcieb->pcieb_dip;
850 
851 	/* Allow platform specific code to do any initialization first */
852 	pcieb_plat_intr_attach(pcieb);
853 
854 	/*
855 	 * Initialize interrupt handlers.
856 	 * If both MSI and FIXED are supported, try to attach MSI first.
857 	 * If MSI fails for any reason, then try FIXED, but only allow one
858 	 * type to be attached.
859 	 */
860 	if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) {
861 		PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_get_supported_types"
862 		    " failed\n");
863 		goto FAIL;
864 	}
865 
866 	if ((intr_types & DDI_INTR_TYPE_MSI) &&
867 	    (pcieb_msi_supported(dip) == DDI_SUCCESS)) {
868 		if (pcieb_intr_init(pcieb, DDI_INTR_TYPE_MSI) == DDI_SUCCESS)
869 			intr_types = DDI_INTR_TYPE_MSI;
870 		else {
871 			PCIEB_DEBUG(DBG_ATTACH, dip, "Unable to attach MSI"
872 			    " handler\n");
873 		}
874 	}
875 
876 	if (intr_types != DDI_INTR_TYPE_MSI) {
877 		/*
878 		 * MSIs are not supported or MSI initialization failed. For Root
879 		 * Ports mark this so error handling might try to fallback to
880 		 * some other mechanism if available (machinecheck etc.).
881 		 */
882 		if (PCIE_IS_RP(PCIE_DIP2UPBUS(dip)))
883 			pcieb->pcieb_no_aer_msi = B_TRUE;
884 	}
885 
886 	if (intr_types & DDI_INTR_TYPE_FIXED) {
887 		if (pcieb_intr_init(pcieb, DDI_INTR_TYPE_FIXED) !=
888 		    DDI_SUCCESS) {
889 			PCIEB_DEBUG(DBG_ATTACH, dip,
890 			    "Unable to attach INTx handler\n");
891 			goto FAIL;
892 		}
893 	}
894 	return (DDI_SUCCESS);
895 
896 FAIL:
897 	return (DDI_FAILURE);
898 }
899 
900 /*
901  * This function initializes internally generated interrupts only.
902  * It does not affect any interrupts generated by downstream devices
903  * or the forwarding of them.
904  *
905  * Enable Device Specific Interrupts or Hotplug features here.
906  * Enabling features may change how many interrupts are requested
907  * by the device.  If features are not enabled first, the
908  * device might not ask for any interrupts.
909  */
910 
911 static int
912 pcieb_intr_init(pcieb_devstate_t *pcieb, int intr_type)
913 {
914 	dev_info_t	*dip = pcieb->pcieb_dip;
915 	int		nintrs, request, count, x;
916 	int		intr_cap = 0;
917 	int		inum = 0;
918 	int		ret, hp_msi_off;
919 	pcie_bus_t	*bus_p = PCIE_DIP2UPBUS(dip);
920 	uint16_t	vendorid = bus_p->bus_dev_ven_id & 0xFFFF;
921 	boolean_t	is_hp = B_FALSE;
922 	boolean_t	is_pme = B_FALSE;
923 
924 	PCIEB_DEBUG(DBG_ATTACH, dip, "pcieb_intr_init: Attaching %s handler\n",
925 	    (intr_type == DDI_INTR_TYPE_MSI) ? "MSI" : "INTx");
926 
927 	request = 0;
928 	if (PCIE_IS_HOTPLUG_ENABLED(dip)) {
929 		request++;
930 		is_hp = B_TRUE;
931 	}
932 
933 	/*
934 	 * Hotplug and PME share the same MSI vector. If hotplug is not
935 	 * supported check if MSI is needed for PME.
936 	 */
937 	if ((intr_type == DDI_INTR_TYPE_MSI) && PCIE_IS_RP(bus_p) &&
938 	    (vendorid == NVIDIA_VENDOR_ID)) {
939 		is_pme = B_TRUE;
940 		if (!is_hp)
941 			request++;
942 	}
943 
944 	/*
945 	 * Setup MSI if this device is a Rootport and has AER. Currently no
946 	 * SPARC Root Port supports fabric errors being reported through it.
947 	 */
948 	if (intr_type == DDI_INTR_TYPE_MSI) {
949 		if (PCIE_IS_RP(bus_p) && PCIE_HAS_AER(bus_p))
950 			request++;
951 	}
952 
953 	if (request == 0)
954 		return (DDI_SUCCESS);
955 
956 	/*
957 	 * Get number of supported interrupts.
958 	 *
959 	 * Several Bridges/Switches will not have this property set, resulting
960 	 * in a FAILURE, if the device is not configured in a way that
961 	 * interrupts are needed. (eg. hotplugging)
962 	 */
963 	ret = ddi_intr_get_nintrs(dip, intr_type, &nintrs);
964 	if ((ret != DDI_SUCCESS) || (nintrs == 0)) {
965 		PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_get_nintrs ret:%d"
966 		    " req:%d\n", ret, nintrs);
967 		return (DDI_FAILURE);
968 	}
969 
970 	PCIEB_DEBUG(DBG_ATTACH, dip, "bdf 0x%x: ddi_intr_get_nintrs: nintrs %d",
971 	    " request %d\n", bus_p->bus_bdf, nintrs, request);
972 
973 	if (request > nintrs)
974 		request = nintrs;
975 
976 	/* Allocate an array of interrupt handlers */
977 	pcieb->pcieb_htable_size = sizeof (ddi_intr_handle_t) * request;
978 	pcieb->pcieb_htable = kmem_zalloc(pcieb->pcieb_htable_size,
979 	    KM_SLEEP);
980 	pcieb->pcieb_init_flags |= PCIEB_INIT_HTABLE;
981 
982 	ret = ddi_intr_alloc(dip, pcieb->pcieb_htable, intr_type, inum,
983 	    request, &count, DDI_INTR_ALLOC_NORMAL);
984 	if ((ret != DDI_SUCCESS) || (count == 0)) {
985 		PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_alloc() ret: %d ask: %d"
986 		    " actual: %d\n", ret, request, count);
987 		goto FAIL;
988 	}
989 	pcieb->pcieb_init_flags |= PCIEB_INIT_ALLOC;
990 
991 	/* Save the actual number of interrupts allocated */
992 	pcieb->pcieb_intr_count = count;
993 	if (count < request) {
994 		PCIEB_DEBUG(DBG_ATTACH, dip, "bdf 0%x: Requested Intr: %d"
995 		    " Received: %d\n", bus_p->bus_bdf, request, count);
996 	}
997 
998 	/*
999 	 * NVidia (MCP55 and other) chipsets have a errata that if the number
1000 	 * of requested MSI intrs is not allocated we have to fall back to INTx.
1001 	 */
1002 	if (intr_type == DDI_INTR_TYPE_MSI) {
1003 		if (PCIE_IS_RP(bus_p) && (vendorid == NVIDIA_VENDOR_ID)) {
1004 			if (request != count)
1005 				goto FAIL;
1006 		}
1007 	}
1008 
1009 	/* Get interrupt priority */
1010 	ret = ddi_intr_get_pri(pcieb->pcieb_htable[0],
1011 	    &pcieb->pcieb_intr_priority);
1012 	if (ret != DDI_SUCCESS) {
1013 		PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_get_pri() ret: %d\n",
1014 		    ret);
1015 		goto FAIL;
1016 	}
1017 
1018 	if (pcieb->pcieb_intr_priority >= LOCK_LEVEL) {
1019 		pcieb->pcieb_intr_priority = LOCK_LEVEL - 1;
1020 		ret = ddi_intr_set_pri(pcieb->pcieb_htable[0],
1021 		    pcieb->pcieb_intr_priority);
1022 		if (ret != DDI_SUCCESS) {
1023 			PCIEB_DEBUG(DBG_ATTACH, dip, "ddi_intr_set_pri() ret:"
1024 			" %d\n", ret);
1025 
1026 			goto FAIL;
1027 		}
1028 	}
1029 
1030 	mutex_init(&pcieb->pcieb_intr_mutex, NULL, MUTEX_DRIVER, NULL);
1031 
1032 	pcieb->pcieb_init_flags |= PCIEB_INIT_MUTEX;
1033 
1034 	for (count = 0; count < pcieb->pcieb_intr_count; count++) {
1035 		ret = ddi_intr_add_handler(pcieb->pcieb_htable[count],
1036 		    pcieb_intr_handler, (caddr_t)pcieb,
1037 		    (caddr_t)(uintptr_t)(inum + count));
1038 
1039 		if (ret != DDI_SUCCESS) {
1040 			PCIEB_DEBUG(DBG_ATTACH, dip, "Cannot add "
1041 			    "interrupt(%d)\n", ret);
1042 			break;
1043 		}
1044 	}
1045 
1046 	/* If unsucessful, remove the added handlers */
1047 	if (ret != DDI_SUCCESS) {
1048 		for (x = 0; x < count; x++) {
1049 			(void) ddi_intr_remove_handler(pcieb->pcieb_htable[x]);
1050 		}
1051 		goto FAIL;
1052 	}
1053 
1054 	pcieb->pcieb_init_flags |= PCIEB_INIT_HANDLER;
1055 
1056 	(void) ddi_intr_get_cap(pcieb->pcieb_htable[0], &intr_cap);
1057 
1058 	/*
1059 	 * Get this intr lock because we are not quite ready to handle
1060 	 * interrupts immediately after enabling it. The MSI multi register
1061 	 * gets programmed in ddi_intr_enable after which we need to get the
1062 	 * MSI offsets for Hotplug/AER.
1063 	 */
1064 	mutex_enter(&pcieb->pcieb_intr_mutex);
1065 
1066 	if (intr_cap & DDI_INTR_FLAG_BLOCK) {
1067 		(void) ddi_intr_block_enable(pcieb->pcieb_htable,
1068 		    pcieb->pcieb_intr_count);
1069 		pcieb->pcieb_init_flags |= PCIEB_INIT_BLOCK;
1070 	} else {
1071 		for (count = 0; count < pcieb->pcieb_intr_count; count++) {
1072 			(void) ddi_intr_enable(pcieb->pcieb_htable[count]);
1073 		}
1074 	}
1075 	pcieb->pcieb_init_flags |= PCIEB_INIT_ENABLE;
1076 
1077 	/* Save the interrupt type */
1078 	pcieb->pcieb_intr_type = intr_type;
1079 
1080 	/* Get the MSI offset for hotplug/PME from the PCIe cap reg */
1081 	if (intr_type == DDI_INTR_TYPE_MSI) {
1082 		hp_msi_off = PCI_CAP_GET16(bus_p->bus_cfg_hdl, NULL,
1083 		    bus_p->bus_pcie_off, PCIE_PCIECAP) &
1084 		    PCIE_PCIECAP_INT_MSG_NUM;
1085 
1086 		if (hp_msi_off >= count) {
1087 			PCIEB_DEBUG(DBG_ATTACH, dip, "MSI number %d in PCIe "
1088 			    "cap > max allocated %d\n", hp_msi_off, count);
1089 			mutex_exit(&pcieb->pcieb_intr_mutex);
1090 			goto FAIL;
1091 		}
1092 
1093 		if (is_hp)
1094 			pcieb->pcieb_isr_tab[hp_msi_off] |= PCIEB_INTR_SRC_HP;
1095 
1096 		if (is_pme)
1097 			pcieb->pcieb_isr_tab[hp_msi_off] |= PCIEB_INTR_SRC_PME;
1098 	} else {
1099 		/* INTx handles only Hotplug interrupts */
1100 		if (is_hp)
1101 			pcieb->pcieb_isr_tab[0] |= PCIEB_INTR_SRC_HP;
1102 	}
1103 
1104 
1105 	/*
1106 	 * Get the MSI offset for errors from the AER Root Error status
1107 	 * register.
1108 	 */
1109 	if ((intr_type == DDI_INTR_TYPE_MSI) && PCIE_IS_RP(bus_p)) {
1110 		if (PCIE_HAS_AER(bus_p)) {
1111 			int aer_msi_off;
1112 			aer_msi_off = (PCI_XCAP_GET32(bus_p->bus_cfg_hdl, NULL,
1113 			    bus_p->bus_aer_off, PCIE_AER_RE_STS) >>
1114 			    PCIE_AER_RE_STS_MSG_NUM_SHIFT) &
1115 			    PCIE_AER_RE_STS_MSG_NUM_MASK;
1116 
1117 			if (aer_msi_off >= count) {
1118 				PCIEB_DEBUG(DBG_ATTACH, dip, "MSI number %d in"
1119 				    " AER cap > max allocated %d\n",
1120 				    aer_msi_off, count);
1121 				mutex_exit(&pcieb->pcieb_intr_mutex);
1122 				goto FAIL;
1123 			}
1124 			pcieb->pcieb_isr_tab[aer_msi_off] |= PCIEB_INTR_SRC_AER;
1125 		} else {
1126 			/*
1127 			 * This RP does not have AER. Fallback to the
1128 			 * SERR+Machinecheck approach if available.
1129 			 */
1130 			pcieb->pcieb_no_aer_msi = B_TRUE;
1131 		}
1132 	}
1133 
1134 	mutex_exit(&pcieb->pcieb_intr_mutex);
1135 	return (DDI_SUCCESS);
1136 
1137 FAIL:
1138 	pcieb_intr_fini(pcieb);
1139 	return (DDI_FAILURE);
1140 }
1141 
1142 static void
1143 pcieb_intr_fini(pcieb_devstate_t *pcieb)
1144 {
1145 	int x;
1146 	int count = pcieb->pcieb_intr_count;
1147 	int flags = pcieb->pcieb_init_flags;
1148 
1149 	if ((flags & PCIEB_INIT_ENABLE) &&
1150 	    (flags & PCIEB_INIT_BLOCK)) {
1151 		(void) ddi_intr_block_disable(pcieb->pcieb_htable, count);
1152 		flags &= ~(PCIEB_INIT_ENABLE |
1153 		    PCIEB_INIT_BLOCK);
1154 	}
1155 
1156 	if (flags & PCIEB_INIT_MUTEX)
1157 		mutex_destroy(&pcieb->pcieb_intr_mutex);
1158 
1159 	for (x = 0; x < count; x++) {
1160 		if (flags & PCIEB_INIT_ENABLE)
1161 			(void) ddi_intr_disable(pcieb->pcieb_htable[x]);
1162 
1163 		if (flags & PCIEB_INIT_HANDLER)
1164 			(void) ddi_intr_remove_handler(pcieb->pcieb_htable[x]);
1165 
1166 		if (flags & PCIEB_INIT_ALLOC)
1167 			(void) ddi_intr_free(pcieb->pcieb_htable[x]);
1168 	}
1169 
1170 	flags &= ~(PCIEB_INIT_ENABLE | PCIEB_INIT_HANDLER | PCIEB_INIT_ALLOC |
1171 	    PCIEB_INIT_MUTEX);
1172 
1173 	if (flags & PCIEB_INIT_HTABLE)
1174 		kmem_free(pcieb->pcieb_htable, pcieb->pcieb_htable_size);
1175 
1176 	flags &= ~PCIEB_INIT_HTABLE;
1177 
1178 	pcieb->pcieb_init_flags &= flags;
1179 }
1180 
1181 /*
1182  * Checks if this device needs MSIs enabled or not.
1183  */
1184 /*ARGSUSED*/
1185 static int
1186 pcieb_msi_supported(dev_info_t *dip)
1187 {
1188 	return ((pcieb_enable_msi && pcieb_plat_msi_supported(dip)) ?
1189 	    DDI_SUCCESS: DDI_FAILURE);
1190 }
1191 
1192 /*ARGSUSED*/
1193 static int
1194 pcieb_fm_init_child(dev_info_t *dip, dev_info_t *tdip, int cap,
1195     ddi_iblock_cookie_t *ibc)
1196 {
1197 	pcieb_devstate_t  *pcieb = ddi_get_soft_state(pcieb_state,
1198 	    ddi_get_instance(dip));
1199 
1200 	ASSERT(ibc != NULL);
1201 	*ibc = pcieb->pcieb_fm_ibc;
1202 
1203 	return (DEVI(dip)->devi_fmhdl->fh_cap | DDI_FM_ACCCHK_CAPABLE |
1204 	    DDI_FM_DMACHK_CAPABLE);
1205 }
1206 
1207 static int
1208 pcieb_fm_init(pcieb_devstate_t *pcieb_p)
1209 {
1210 	dev_info_t	*dip = pcieb_p->pcieb_dip;
1211 	int		fm_cap = DDI_FM_EREPORT_CAPABLE;
1212 
1213 	/*
1214 	 * Request our capability level and get our parents capability
1215 	 * and ibc.
1216 	 */
1217 	ddi_fm_init(dip, &fm_cap, &pcieb_p->pcieb_fm_ibc);
1218 
1219 	return (DDI_SUCCESS);
1220 }
1221 
1222 /*
1223  * Breakdown our FMA resources
1224  */
1225 static void
1226 pcieb_fm_fini(pcieb_devstate_t *pcieb_p)
1227 {
1228 	/*
1229 	 * Clean up allocated fm structures
1230 	 */
1231 	ddi_fm_fini(pcieb_p->pcieb_dip);
1232 }
1233 
1234 static int
1235 pcieb_open(dev_t *devp, int flags, int otyp, cred_t *credp)
1236 {
1237 	int		inst = PCI_MINOR_NUM_TO_INSTANCE(getminor(*devp));
1238 	pcieb_devstate_t	*pcieb = ddi_get_soft_state(pcieb_state, inst);
1239 	int	rv;
1240 
1241 	if (pcieb == NULL)
1242 		return (ENXIO);
1243 
1244 	mutex_enter(&pcieb->pcieb_mutex);
1245 	rv = pcie_open(pcieb->pcieb_dip, devp, flags, otyp, credp);
1246 	mutex_exit(&pcieb->pcieb_mutex);
1247 
1248 	return (rv);
1249 }
1250 
1251 static int
1252 pcieb_close(dev_t dev, int flags, int otyp, cred_t *credp)
1253 {
1254 	int		inst = PCI_MINOR_NUM_TO_INSTANCE(getminor(dev));
1255 	pcieb_devstate_t	*pcieb = ddi_get_soft_state(pcieb_state, inst);
1256 	int	rv;
1257 
1258 	if (pcieb == NULL)
1259 		return (ENXIO);
1260 
1261 	mutex_enter(&pcieb->pcieb_mutex);
1262 	rv = pcie_close(pcieb->pcieb_dip, dev, flags, otyp, credp);
1263 	mutex_exit(&pcieb->pcieb_mutex);
1264 
1265 	return (rv);
1266 }
1267 
1268 static int
1269 pcieb_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp,
1270 	int *rvalp)
1271 {
1272 	int		inst = PCI_MINOR_NUM_TO_INSTANCE(getminor(dev));
1273 	pcieb_devstate_t	*pcieb = ddi_get_soft_state(pcieb_state, inst);
1274 	int		rv;
1275 
1276 	if (pcieb == NULL)
1277 		return (ENXIO);
1278 
1279 	/* To handle devctl and hotplug related ioctls */
1280 	rv = pcie_ioctl(pcieb->pcieb_dip, dev, cmd, arg, mode, credp, rvalp);
1281 
1282 	return (rv);
1283 }
1284 
1285 /*
1286  * Common interrupt handler for hotplug, PME and errors.
1287  */
1288 static uint_t
1289 pcieb_intr_handler(caddr_t arg1, caddr_t arg2)
1290 {
1291 	pcieb_devstate_t *pcieb_p = (pcieb_devstate_t *)arg1;
1292 	dev_info_t	*dip = pcieb_p->pcieb_dip;
1293 	ddi_fm_error_t	derr;
1294 	int		sts = 0;
1295 	int		ret = DDI_INTR_UNCLAIMED;
1296 	int		isrc;
1297 
1298 	if (!(pcieb_p->pcieb_init_flags & PCIEB_INIT_ENABLE))
1299 		goto FAIL;
1300 
1301 	mutex_enter(&pcieb_p->pcieb_intr_mutex);
1302 	isrc = pcieb_p->pcieb_isr_tab[(int)(uintptr_t)arg2];
1303 	mutex_exit(&pcieb_p->pcieb_intr_mutex);
1304 
1305 	PCIEB_DEBUG(DBG_INTR, dip, "Received intr number %d\n",
1306 	    (int)(uintptr_t)arg2);
1307 
1308 	if (isrc == PCIEB_INTR_SRC_UNKNOWN)
1309 		goto FAIL;
1310 
1311 	if (isrc & PCIEB_INTR_SRC_HP)
1312 		ret = pcie_intr(dip);
1313 
1314 	if (isrc & PCIEB_INTR_SRC_PME)
1315 		ret = DDI_INTR_CLAIMED;
1316 
1317 	/* AER Error */
1318 	if (isrc & PCIEB_INTR_SRC_AER) {
1319 		/*
1320 		 *  If MSI is shared with PME/hotplug then check Root Error
1321 		 *  Status Reg before claiming it. For now it's ok since
1322 		 *  we know we get 2 MSIs.
1323 		 */
1324 		ret = DDI_INTR_CLAIMED;
1325 		bzero(&derr, sizeof (ddi_fm_error_t));
1326 		derr.fme_version = DDI_FME_VERSION;
1327 		mutex_enter(&pcieb_p->pcieb_peek_poke_mutex);
1328 		mutex_enter(&pcieb_p->pcieb_err_mutex);
1329 
1330 		pf_eh_enter(PCIE_DIP2BUS(dip));
1331 		PCIE_ROOT_EH_SRC(PCIE_DIP2PFD(dip))->intr_type =
1332 		    PF_INTR_TYPE_AER;
1333 
1334 		if ((DEVI(dip)->devi_fmhdl->fh_cap) & DDI_FM_EREPORT_CAPABLE)
1335 			sts = pf_scan_fabric(dip, &derr, NULL);
1336 		pf_eh_exit(PCIE_DIP2BUS(dip));
1337 
1338 		mutex_exit(&pcieb_p->pcieb_err_mutex);
1339 		mutex_exit(&pcieb_p->pcieb_peek_poke_mutex);
1340 		if (pcieb_die & sts)
1341 			fm_panic("%s-%d: PCI(-X) Express Fatal Error. (0x%x)",
1342 			    ddi_driver_name(dip), ddi_get_instance(dip), sts);
1343 	}
1344 FAIL:
1345 	return (ret);
1346 }
1347 
1348 /*
1349  * Some PCI-X to PCI-E bridges do not support full 64-bit addressing on the
1350  * PCI-X side of the bridge.  We build a special version of this driver for
1351  * those bridges, which uses PCIEB_ADDR_LIMIT_LO and/or PCIEB_ADDR_LIMIT_HI
1352  * to define the range of values which the chip can handle.  The code below
1353  * then clamps the DMA address range supplied by the driver, preventing the
1354  * PCI-E nexus driver from allocating any memory the bridge can't deal
1355  * with.
1356  */
1357 static int
1358 pcieb_dma_allochdl(dev_info_t *dip, dev_info_t *rdip,
1359 	ddi_dma_attr_t *attr_p, int (*waitfp)(caddr_t), caddr_t arg,
1360 	ddi_dma_handle_t *handlep)
1361 {
1362 	int		ret;
1363 #ifdef	PCIEB_BCM
1364 	uint64_t	lim;
1365 
1366 	/*
1367 	 * If the leaf device's limits are outside than what the Broadcom
1368 	 * bridge can handle, we need to clip the values passed up the chain.
1369 	 */
1370 	lim = attr_p->dma_attr_addr_lo;
1371 	attr_p->dma_attr_addr_lo = MAX(lim, PCIEB_ADDR_LIMIT_LO);
1372 
1373 	lim = attr_p->dma_attr_addr_hi;
1374 	attr_p->dma_attr_addr_hi = MIN(lim, PCIEB_ADDR_LIMIT_HI);
1375 
1376 #endif	/* PCIEB_BCM */
1377 
1378 	/*
1379 	 * This is a software workaround to fix the Broadcom 5714/5715 PCIe-PCI
1380 	 * bridge prefetch bug. Intercept the DMA alloc handle request and set
1381 	 * PX_DMAI_FLAGS_MAP_BUFZONE flag in the handle. If this flag is set,
1382 	 * the px nexus driver will allocate an extra page & make it valid one,
1383 	 * for any DVMA request that comes from any of the Broadcom bridge child
1384 	 * devices.
1385 	 */
1386 	if ((ret = ddi_dma_allochdl(dip, rdip, attr_p, waitfp, arg,
1387 	    handlep)) == DDI_SUCCESS) {
1388 		ddi_dma_impl_t	*mp = (ddi_dma_impl_t *)*handlep;
1389 #ifdef	PCIEB_BCM
1390 		mp->dmai_inuse |= PX_DMAI_FLAGS_MAP_BUFZONE;
1391 #endif	/* PCIEB_BCM */
1392 		/*
1393 		 * For a given rdip, update mp->dmai_bdf with the bdf value
1394 		 * of pcieb's immediate child or secondary bus-id of the
1395 		 * PCIe2PCI bridge.
1396 		 */
1397 		mp->dmai_minxfer = pcie_get_bdf_for_dma_xfer(dip, rdip);
1398 	}
1399 
1400 	return (ret);
1401 }
1402 
1403 /*
1404  * FDVMA feature is not supported for any child device of Broadcom 5714/5715
1405  * PCIe-PCI bridge due to prefetch bug. Return failure immediately, so that
1406  * these drivers will switch to regular DVMA path.
1407  */
1408 /*ARGSUSED*/
1409 static int
1410 pcieb_dma_mctl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle,
1411 	enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp,
1412 	uint_t cache_flags)
1413 {
1414 	int	ret;
1415 
1416 #ifdef	PCIEB_BCM
1417 	if (cmd == DDI_DMA_RESERVE)
1418 		return (DDI_FAILURE);
1419 #endif	/* PCIEB_BCM */
1420 
1421 	if (((ret = ddi_dma_mctl(dip, rdip, handle, cmd, offp, lenp, objp,
1422 	    cache_flags)) == DDI_SUCCESS) && (cmd == DDI_DMA_RESERVE)) {
1423 		ddi_dma_impl_t	*mp = (ddi_dma_impl_t *)*objp;
1424 
1425 		/*
1426 		 * For a given rdip, update mp->dmai_bdf with the bdf value
1427 		 * of pcieb's immediate child or secondary bus-id of the
1428 		 * PCIe2PCI bridge.
1429 		 */
1430 		mp->dmai_minxfer = pcie_get_bdf_for_dma_xfer(dip, rdip);
1431 	}
1432 
1433 	return (ret);
1434 }
1435 
1436 static int
1437 pcieb_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
1438     ddi_intr_handle_impl_t *hdlp, void *result)
1439 {
1440 	return (pcieb_plat_intr_ops(dip, rdip, intr_op, hdlp, result));
1441 
1442 }
1443 
1444 /*
1445  * Power management related initialization specific to pcieb.
1446  * Called by pcieb_attach()
1447  */
1448 static int
1449 pcieb_pwr_setup(dev_info_t *dip)
1450 {
1451 	char *comp_array[5];
1452 	int i;
1453 	ddi_acc_handle_t conf_hdl;
1454 	uint16_t pmcap, cap_ptr;
1455 	pcie_pwr_t *pwr_p;
1456 
1457 	/* Some platforms/devices may choose to disable PM */
1458 	if (pcieb_plat_pwr_disable(dip)) {
1459 		(void) pcieb_pwr_disable(dip);
1460 		return (DDI_SUCCESS);
1461 	}
1462 
1463 	ASSERT(PCIE_PMINFO(dip));
1464 	pwr_p = PCIE_NEXUS_PMINFO(dip);
1465 	ASSERT(pwr_p);
1466 
1467 	/* Code taken from pci_pci driver */
1468 	if (pci_config_setup(dip, &pwr_p->pwr_conf_hdl) != DDI_SUCCESS) {
1469 		PCIEB_DEBUG(DBG_PWR, dip, "pcieb_pwr_setup: pci_config_setup "
1470 		    "failed\n");
1471 		return (DDI_FAILURE);
1472 	}
1473 	conf_hdl = pwr_p->pwr_conf_hdl;
1474 
1475 	/*
1476 	 * Walk the capabilities searching for a PM entry.
1477 	 */
1478 	if ((PCI_CAP_LOCATE(conf_hdl, PCI_CAP_ID_PM, &cap_ptr)) ==
1479 	    DDI_FAILURE) {
1480 		PCIEB_DEBUG(DBG_PWR, dip, "switch/bridge does not support PM. "
1481 		    " PCI PM data structure not found in config header\n");
1482 		pci_config_teardown(&conf_hdl);
1483 		return (DDI_SUCCESS);
1484 	}
1485 	/*
1486 	 * Save offset to pmcsr for future references.
1487 	 */
1488 	pwr_p->pwr_pmcsr_offset = cap_ptr + PCI_PMCSR;
1489 	pmcap = PCI_CAP_GET16(conf_hdl, NULL, cap_ptr, PCI_PMCAP);
1490 	if (pmcap & PCI_PMCAP_D1) {
1491 		PCIEB_DEBUG(DBG_PWR, dip, "D1 state supported\n");
1492 		pwr_p->pwr_pmcaps |= PCIE_SUPPORTS_D1;
1493 	}
1494 	if (pmcap & PCI_PMCAP_D2) {
1495 		PCIEB_DEBUG(DBG_PWR, dip, "D2 state supported\n");
1496 		pwr_p->pwr_pmcaps |= PCIE_SUPPORTS_D2;
1497 	}
1498 
1499 	i = 0;
1500 	comp_array[i++] = "NAME=PCIe switch/bridge PM";
1501 	comp_array[i++] = "0=Power Off (D3)";
1502 	if (pwr_p->pwr_pmcaps & PCIE_SUPPORTS_D2)
1503 		comp_array[i++] = "1=D2";
1504 	if (pwr_p->pwr_pmcaps & PCIE_SUPPORTS_D1)
1505 		comp_array[i++] = "2=D1";
1506 	comp_array[i++] = "3=Full Power D0";
1507 
1508 	/*
1509 	 * Create pm-components property, if it does not exist already.
1510 	 */
1511 	if (ddi_prop_update_string_array(DDI_DEV_T_NONE, dip,
1512 	    "pm-components", comp_array, i) != DDI_PROP_SUCCESS) {
1513 		PCIEB_DEBUG(DBG_PWR, dip, "could not create pm-components "
1514 		    " prop\n");
1515 		pci_config_teardown(&conf_hdl);
1516 		return (DDI_FAILURE);
1517 	}
1518 	return (pcieb_pwr_init_and_raise(dip, pwr_p));
1519 }
1520 
1521 /*
1522  * undo whatever is done in pcieb_pwr_setup. called by pcieb_detach()
1523  */
1524 static void
1525 pcieb_pwr_teardown(dev_info_t *dip)
1526 {
1527 	pcie_pwr_t	*pwr_p;
1528 
1529 	if (!PCIE_PMINFO(dip) || !(pwr_p = PCIE_NEXUS_PMINFO(dip)))
1530 		return;
1531 
1532 	(void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "pm-components");
1533 	if (pwr_p->pwr_conf_hdl)
1534 		pci_config_teardown(&pwr_p->pwr_conf_hdl);
1535 }
1536 
1537 /*
1538  * Initializes the power level and raise the power to D0, if it is
1539  * not at D0.
1540  */
1541 static int
1542 pcieb_pwr_init_and_raise(dev_info_t *dip, pcie_pwr_t *pwr_p)
1543 {
1544 	uint16_t pmcsr;
1545 	int ret = DDI_SUCCESS;
1546 
1547 	/*
1548 	 * Intialize our power level from PMCSR. The common code initializes
1549 	 * this to UNKNOWN. There is no guarantee that we will be at full
1550 	 * power at attach. If we are not at D0, raise the power.
1551 	 */
1552 	pmcsr = pci_config_get16(pwr_p->pwr_conf_hdl, pwr_p->pwr_pmcsr_offset);
1553 	pmcsr &= PCI_PMCSR_STATE_MASK;
1554 	switch (pmcsr) {
1555 	case PCI_PMCSR_D0:
1556 		pwr_p->pwr_func_lvl = PM_LEVEL_D0;
1557 		break;
1558 
1559 	case PCI_PMCSR_D1:
1560 		pwr_p->pwr_func_lvl = PM_LEVEL_D1;
1561 		break;
1562 
1563 	case PCI_PMCSR_D2:
1564 		pwr_p->pwr_func_lvl = PM_LEVEL_D2;
1565 		break;
1566 
1567 	case PCI_PMCSR_D3HOT:
1568 		pwr_p->pwr_func_lvl = PM_LEVEL_D3;
1569 		break;
1570 
1571 	default:
1572 		break;
1573 	}
1574 
1575 	/* Raise the power to D0. */
1576 	if (pwr_p->pwr_func_lvl != PM_LEVEL_D0 &&
1577 	    ((ret = pm_raise_power(dip, 0, PM_LEVEL_D0)) != DDI_SUCCESS)) {
1578 		/*
1579 		 * Read PMCSR again. If it is at D0, ignore the return
1580 		 * value from pm_raise_power.
1581 		 */
1582 		pmcsr = pci_config_get16(pwr_p->pwr_conf_hdl,
1583 		    pwr_p->pwr_pmcsr_offset);
1584 		if ((pmcsr & PCI_PMCSR_STATE_MASK) == PCI_PMCSR_D0)
1585 			ret = DDI_SUCCESS;
1586 		else {
1587 			PCIEB_DEBUG(DBG_PWR, dip, "pcieb_pwr_setup: could not "
1588 			    "raise power to D0 \n");
1589 		}
1590 	}
1591 	if (ret == DDI_SUCCESS)
1592 		pwr_p->pwr_func_lvl = PM_LEVEL_D0;
1593 	return (ret);
1594 }
1595 
1596 /*
1597  * Disable PM for x86 and PLX 8532 switch.
1598  * For PLX Transitioning one port on this switch to low power causes links
1599  * on other ports on the same station to die. Due to PLX erratum #34, we
1600  * can't allow the downstream device go to non-D0 state.
1601  */
1602 static int
1603 pcieb_pwr_disable(dev_info_t *dip)
1604 {
1605 	pcie_pwr_t *pwr_p;
1606 
1607 	ASSERT(PCIE_PMINFO(dip));
1608 	pwr_p = PCIE_NEXUS_PMINFO(dip);
1609 	ASSERT(pwr_p);
1610 	PCIEB_DEBUG(DBG_PWR, dip, "pcieb_pwr_disable: disabling PM\n");
1611 	pwr_p->pwr_func_lvl = PM_LEVEL_D0;
1612 	pwr_p->pwr_flags = PCIE_NO_CHILD_PM;
1613 	return (DDI_SUCCESS);
1614 }
1615 
1616 #ifdef DEBUG
1617 int pcieb_dbg_intr_print = 0;
1618 void
1619 pcieb_dbg(uint_t bit, dev_info_t *dip, char *fmt, ...)
1620 {
1621 	va_list ap;
1622 
1623 	if (!pcieb_dbg_print)
1624 		return;
1625 
1626 	if (dip)
1627 		prom_printf("%s(%d): %s", ddi_driver_name(dip),
1628 		    ddi_get_instance(dip), pcieb_debug_sym[bit]);
1629 
1630 	va_start(ap, fmt);
1631 	if (servicing_interrupt()) {
1632 		if (pcieb_dbg_intr_print)
1633 			prom_vprintf(fmt, ap);
1634 	} else {
1635 		prom_vprintf(fmt, ap);
1636 	}
1637 
1638 	va_end(ap);
1639 }
1640 #endif
1641 
1642 static void
1643 pcieb_id_props(pcieb_devstate_t *pcieb)
1644 {
1645 	uint64_t serialid = 0;	/* 40b field of EUI-64 serial no. register */
1646 	uint16_t cap_ptr;
1647 	uint8_t fic = 0;	/* 1 = first in chassis device */
1648 	pcie_bus_t *bus_p = PCIE_DIP2BUS(pcieb->pcieb_dip);
1649 	ddi_acc_handle_t config_handle = bus_p->bus_cfg_hdl;
1650 
1651 	/*
1652 	 * Identify first in chassis.  In the special case of a Sun branded
1653 	 * PLX device, it obviously is first in chassis.  Otherwise, in the
1654 	 * general case, look for an Expansion Slot Register and check its
1655 	 * first-in-chassis bit.
1656 	 */
1657 #ifdef	PX_PLX
1658 	uint16_t vendor_id = bus_p->bus_dev_ven_id & 0xFFFF;
1659 	uint16_t device_id = bus_p->bus_dev_ven_id >> 16;
1660 	if ((vendor_id == PXB_VENDOR_SUN) &&
1661 	    ((device_id == PXB_DEVICE_PLX_PCIX) ||
1662 	    (device_id == PXB_DEVICE_PLX_PCIE))) {
1663 		fic = 1;
1664 	}
1665 #endif	/* PX_PLX */
1666 	if ((fic == 0) && ((PCI_CAP_LOCATE(config_handle,
1667 	    PCI_CAP_ID_SLOT_ID, &cap_ptr)) != DDI_FAILURE)) {
1668 		uint8_t esr = PCI_CAP_GET8(config_handle, NULL,
1669 		    cap_ptr, PCI_CAP_ID_REGS_OFF);
1670 		if (PCI_CAPSLOT_FIC(esr))
1671 			fic = 1;
1672 	}
1673 
1674 	if ((PCI_CAP_LOCATE(config_handle,
1675 	    PCI_CAP_XCFG_SPC(PCIE_EXT_CAP_ID_SER), &cap_ptr)) != DDI_FAILURE) {
1676 		/* Serialid can be 0 thru a full 40b number */
1677 		serialid = PCI_XCAP_GET32(config_handle, NULL,
1678 		    cap_ptr, PCIE_SER_SID_UPPER_DW);
1679 		serialid <<= 32;
1680 		serialid |= PCI_XCAP_GET32(config_handle, NULL,
1681 		    cap_ptr, PCIE_SER_SID_LOWER_DW);
1682 	}
1683 
1684 	if (fic)
1685 		(void) ndi_prop_create_boolean(DDI_DEV_T_NONE, pcieb->pcieb_dip,
1686 		    "first-in-chassis");
1687 	if (serialid)
1688 		(void) ddi_prop_update_int64(DDI_DEV_T_NONE, pcieb->pcieb_dip,
1689 		    "serialid#", serialid);
1690 }
1691 
1692 static void
1693 pcieb_create_ranges_prop(dev_info_t *dip,
1694 	ddi_acc_handle_t config_handle)
1695 {
1696 	uint32_t base, limit;
1697 	ppb_ranges_t	ranges[PCIEB_RANGE_LEN];
1698 	uint8_t io_base_lo, io_limit_lo;
1699 	uint16_t io_base_hi, io_limit_hi, mem_base, mem_limit;
1700 	int i = 0, rangelen = sizeof (ppb_ranges_t)/sizeof (int);
1701 
1702 	io_base_lo = pci_config_get8(config_handle, PCI_BCNF_IO_BASE_LOW);
1703 	io_limit_lo = pci_config_get8(config_handle, PCI_BCNF_IO_LIMIT_LOW);
1704 	io_base_hi = pci_config_get16(config_handle, PCI_BCNF_IO_BASE_HI);
1705 	io_limit_hi = pci_config_get16(config_handle, PCI_BCNF_IO_LIMIT_HI);
1706 	mem_base = pci_config_get16(config_handle, PCI_BCNF_MEM_BASE);
1707 	mem_limit = pci_config_get16(config_handle, PCI_BCNF_MEM_LIMIT);
1708 
1709 	/*
1710 	 * Create ranges for IO space
1711 	 */
1712 	ranges[i].size_low = ranges[i].size_high = 0;
1713 	ranges[i].parent_mid = ranges[i].child_mid = ranges[i].parent_high = 0;
1714 	ranges[i].child_high = ranges[i].parent_high |=
1715 	    (PCI_REG_REL_M | PCI_ADDR_IO);
1716 	base = PCIEB_16bit_IOADDR(io_base_lo);
1717 	limit = PCIEB_16bit_IOADDR(io_limit_lo);
1718 
1719 	if ((io_base_lo & 0xf) == PCIEB_32BIT_IO) {
1720 		base = PCIEB_LADDR(base, io_base_hi);
1721 	}
1722 	if ((io_limit_lo & 0xf) == PCIEB_32BIT_IO) {
1723 		limit = PCIEB_LADDR(limit, io_limit_hi);
1724 	}
1725 
1726 	if ((io_base_lo & PCIEB_32BIT_IO) && (io_limit_hi > 0)) {
1727 		base = PCIEB_LADDR(base, io_base_hi);
1728 		limit = PCIEB_LADDR(limit, io_limit_hi);
1729 	}
1730 
1731 	/*
1732 	 * Create ranges for 32bit memory space
1733 	 */
1734 	base = PCIEB_32bit_MEMADDR(mem_base);
1735 	limit = PCIEB_32bit_MEMADDR(mem_limit);
1736 	ranges[i].size_low = ranges[i].size_high = 0;
1737 	ranges[i].parent_mid = ranges[i].child_mid = ranges[i].parent_high = 0;
1738 	ranges[i].child_high = ranges[i].parent_high |=
1739 	    (PCI_REG_REL_M | PCI_ADDR_MEM32);
1740 	ranges[i].child_low = ranges[i].parent_low = base;
1741 	if (limit >= base) {
1742 		ranges[i].size_low = limit - base + PCIEB_MEMGRAIN;
1743 		i++;
1744 	}
1745 
1746 	if (i) {
1747 		(void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "ranges",
1748 		    (int *)ranges, i * rangelen);
1749 	}
1750 }
1751 
1752 /*
1753  * For PCI and PCI-X devices including PCIe2PCI bridge, initialize
1754  * cache-line-size and latency timer configuration registers.
1755  */
1756 void
1757 pcieb_set_pci_perf_parameters(dev_info_t *dip, ddi_acc_handle_t cfg_hdl)
1758 {
1759 	uint_t	n;
1760 
1761 	/* Initialize cache-line-size configuration register if needed */
1762 	if (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
1763 	    "cache-line-size", 0) == 0) {
1764 		pci_config_put8(cfg_hdl, PCI_CONF_CACHE_LINESZ,
1765 		    PCIEB_CACHE_LINE_SIZE);
1766 		n = pci_config_get8(cfg_hdl, PCI_CONF_CACHE_LINESZ);
1767 		if (n != 0) {
1768 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1769 			    "cache-line-size", n);
1770 		}
1771 	}
1772 
1773 	/* Initialize latency timer configuration registers if needed */
1774 	if (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS,
1775 	    "latency-timer", 0) == 0) {
1776 		uchar_t	min_gnt, latency_timer;
1777 		uchar_t header_type;
1778 
1779 		/* Determine the configuration header type */
1780 		header_type = pci_config_get8(cfg_hdl, PCI_CONF_HEADER);
1781 
1782 		if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_ONE) {
1783 			latency_timer = PCIEB_LATENCY_TIMER;
1784 			pci_config_put8(cfg_hdl, PCI_BCNF_LATENCY_TIMER,
1785 			    latency_timer);
1786 		} else {
1787 			min_gnt = pci_config_get8(cfg_hdl, PCI_CONF_MIN_G);
1788 			latency_timer = min_gnt * 8;
1789 		}
1790 
1791 		pci_config_put8(cfg_hdl, PCI_CONF_LATENCY_TIMER,
1792 		    latency_timer);
1793 		n = pci_config_get8(cfg_hdl, PCI_CONF_LATENCY_TIMER);
1794 		if (n != 0) {
1795 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, dip,
1796 			    "latency-timer", n);
1797 		}
1798 	}
1799 }
1800