1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, v.1, (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://opensource.org/licenses/CDDL-1.0. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2014-2017 Cavium, Inc. 24 * The contents of this file are subject to the terms of the Common Development 25 * and Distribution License, v.1, (the "License"). 26 27 * You may not use this file except in compliance with the License. 28 29 * You can obtain a copy of the License at available 30 * at http://opensource.org/licenses/CDDL-1.0 31 32 * See the License for the specific language governing permissions and 33 * limitations under the License. 34 */ 35 36 #ifndef __ECORE_HSI_INIT_TOOL__ 37 #define __ECORE_HSI_INIT_TOOL__ 38 /**************************************/ 39 /* Init Tool HSI constants and macros */ 40 /**************************************/ 41 42 /* Width of GRC address in bits (addresses are specified in dwords) */ 43 #define GRC_ADDR_BITS 23 44 #define MAX_GRC_ADDR ((1 << GRC_ADDR_BITS) - 1) 45 46 /* indicates an init that should be applied to any phase ID */ 47 #define ANY_PHASE_ID 0xffff 48 49 /* Max size in dwords of a zipped array */ 50 #define MAX_ZIPPED_SIZE 8192 51 52 53 enum chip_ids 54 { 55 CHIP_BB, 56 CHIP_K2, 57 CHIP_E5, 58 MAX_CHIP_IDS 59 }; 60 61 62 struct fw_asserts_ram_section 63 { 64 __le16 section_ram_line_offset /* The offset of the section in the RAM in RAM lines (64-bit units) */; 65 __le16 section_ram_line_size /* The size of the section in RAM lines (64-bit units) */; 66 u8 list_dword_offset /* The offset of the asserts list within the section in dwords */; 67 u8 list_element_dword_size /* The size of an assert list element in dwords */; 68 u8 list_num_elements /* The number of elements in the asserts list */; 69 u8 list_next_index_dword_offset /* The offset of the next list index field within the section in dwords */; 70 }; 71 72 73 struct fw_ver_num 74 { 75 u8 major /* Firmware major version number */; 76 u8 minor /* Firmware minor version number */; 77 u8 rev /* Firmware revision version number */; 78 u8 eng /* Firmware engineering version number (for bootleg versions) */; 79 }; 80 81 struct fw_ver_info 82 { 83 __le16 tools_ver /* Tools version number */; 84 u8 image_id /* FW image ID (e.g. main, l2b, kuku) */; 85 u8 reserved1; 86 struct fw_ver_num num /* FW version number */; 87 __le32 timestamp /* FW Timestamp in unix time (sec. since 1970) */; 88 __le32 reserved2; 89 }; 90 91 struct fw_info 92 { 93 struct fw_ver_info ver /* FW version information */; 94 struct fw_asserts_ram_section fw_asserts_section /* Info regarding the FW asserts section in the Storm RAM */; 95 }; 96 97 98 struct fw_info_location 99 { 100 __le32 grc_addr /* GRC address where the fw_info struct is located. */; 101 __le32 size /* Size of the fw_info structure (thats located at the grc_addr). */; 102 }; 103 104 105 106 107 enum init_modes 108 { 109 MODE_BB_A0_DEPRECATED, 110 MODE_BB, 111 MODE_K2, 112 MODE_ASIC, 113 MODE_EMUL_REDUCED, 114 MODE_EMUL_FULL, 115 MODE_FPGA, 116 MODE_CHIPSIM, 117 MODE_SF, 118 MODE_MF_SD, 119 MODE_MF_SI, 120 MODE_PORTS_PER_ENG_1, 121 MODE_PORTS_PER_ENG_2, 122 MODE_PORTS_PER_ENG_4, 123 MODE_100G, 124 MODE_E5, 125 MAX_INIT_MODES 126 }; 127 128 129 enum init_phases 130 { 131 PHASE_ENGINE, 132 PHASE_PORT, 133 PHASE_PF, 134 PHASE_VF, 135 PHASE_QM_PF, 136 MAX_INIT_PHASES 137 }; 138 139 140 enum init_split_types 141 { 142 SPLIT_TYPE_NONE, 143 SPLIT_TYPE_PORT, 144 SPLIT_TYPE_PF, 145 SPLIT_TYPE_PORT_PF, 146 SPLIT_TYPE_VF, 147 MAX_INIT_SPLIT_TYPES 148 }; 149 150 151 /* 152 * Binary buffer header 153 */ 154 struct bin_buffer_hdr 155 { 156 __le32 offset /* buffer offset in bytes from the beginning of the binary file */; 157 __le32 length /* buffer length in bytes */; 158 }; 159 160 161 /* 162 * binary init buffer types 163 */ 164 enum bin_init_buffer_type 165 { 166 BIN_BUF_INIT_FW_VER_INFO /* fw_ver_info struct */, 167 BIN_BUF_INIT_CMD /* init commands */, 168 BIN_BUF_INIT_VAL /* init data */, 169 BIN_BUF_INIT_MODE_TREE /* init modes tree */, 170 BIN_BUF_INIT_IRO /* internal RAM offsets */, 171 MAX_BIN_INIT_BUFFER_TYPE 172 }; 173 174 175 /* 176 * init array header: raw 177 */ 178 struct init_array_raw_hdr 179 { 180 __le32 data; 181 #define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */ 182 #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0 183 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF /* init array params */ 184 #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4 185 }; 186 187 /* 188 * init array header: standard 189 */ 190 struct init_array_standard_hdr 191 { 192 __le32 data; 193 #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */ 194 #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0 195 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF /* Init array size (in dwords) */ 196 #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4 197 }; 198 199 /* 200 * init array header: zipped 201 */ 202 struct init_array_zipped_hdr 203 { 204 __le32 data; 205 #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */ 206 #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0 207 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF /* Init array zipped size (in bytes) */ 208 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4 209 }; 210 211 /* 212 * init array header: pattern 213 */ 214 struct init_array_pattern_hdr 215 { 216 __le32 data; 217 #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */ 218 #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0 219 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF /* pattern size in dword */ 220 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4 221 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF /* pattern repetitions */ 222 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8 223 }; 224 225 /* 226 * init array header union 227 */ 228 union init_array_hdr 229 { 230 struct init_array_raw_hdr raw /* raw init array header */; 231 struct init_array_standard_hdr standard /* standard init array header */; 232 struct init_array_zipped_hdr zipped /* zipped init array header */; 233 struct init_array_pattern_hdr pattern /* pattern init array header */; 234 }; 235 236 237 238 239 240 /* 241 * init array types 242 */ 243 enum init_array_types 244 { 245 INIT_ARR_STANDARD /* standard init array */, 246 INIT_ARR_ZIPPED /* zipped init array */, 247 INIT_ARR_PATTERN /* a repeated pattern */, 248 MAX_INIT_ARRAY_TYPES 249 }; 250 251 252 253 /* 254 * init operation: callback 255 */ 256 struct init_callback_op 257 { 258 __le32 op_data; 259 #define INIT_CALLBACK_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 260 #define INIT_CALLBACK_OP_OP_SHIFT 0 261 #define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF 262 #define INIT_CALLBACK_OP_RESERVED_SHIFT 4 263 __le16 callback_id /* Callback ID */; 264 __le16 block_id /* Blocks ID */; 265 }; 266 267 268 /* 269 * init operation: delay 270 */ 271 struct init_delay_op 272 { 273 __le32 op_data; 274 #define INIT_DELAY_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 275 #define INIT_DELAY_OP_OP_SHIFT 0 276 #define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF 277 #define INIT_DELAY_OP_RESERVED_SHIFT 4 278 __le32 delay /* delay in us */; 279 }; 280 281 282 /* 283 * init operation: if_mode 284 */ 285 struct init_if_mode_op 286 { 287 __le32 op_data; 288 #define INIT_IF_MODE_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 289 #define INIT_IF_MODE_OP_OP_SHIFT 0 290 #define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF 291 #define INIT_IF_MODE_OP_RESERVED1_SHIFT 4 292 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF /* Commands to skip if the modes dont match */ 293 #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16 294 __le16 reserved2; 295 __le16 modes_buf_offset /* offset (in bytes) in modes expression buffer */; 296 }; 297 298 299 /* 300 * init operation: if_phase 301 */ 302 struct init_if_phase_op 303 { 304 __le32 op_data; 305 #define INIT_IF_PHASE_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 306 #define INIT_IF_PHASE_OP_OP_SHIFT 0 307 #define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1 /* Indicates if DMAE is enabled in this phase */ 308 #define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4 309 #define INIT_IF_PHASE_OP_RESERVED1_MASK 0x7FF 310 #define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5 311 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF /* Commands to skip if the phases dont match */ 312 #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16 313 __le32 phase_data; 314 #define INIT_IF_PHASE_OP_PHASE_MASK 0xFF /* Init phase */ 315 #define INIT_IF_PHASE_OP_PHASE_SHIFT 0 316 #define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF 317 #define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8 318 #define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF /* Init phase ID */ 319 #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16 320 }; 321 322 323 /* 324 * init mode operators 325 */ 326 enum init_mode_ops 327 { 328 INIT_MODE_OP_NOT /* init mode not operator */, 329 INIT_MODE_OP_OR /* init mode or operator */, 330 INIT_MODE_OP_AND /* init mode and operator */, 331 MAX_INIT_MODE_OPS 332 }; 333 334 335 /* 336 * init operation: raw 337 */ 338 struct init_raw_op 339 { 340 __le32 op_data; 341 #define INIT_RAW_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 342 #define INIT_RAW_OP_OP_SHIFT 0 343 #define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF /* init param 1 */ 344 #define INIT_RAW_OP_PARAM1_SHIFT 4 345 __le32 param2 /* Init param 2 */; 346 }; 347 348 /* 349 * init array params 350 */ 351 struct init_op_array_params 352 { 353 __le16 size /* array size in dwords */; 354 __le16 offset /* array start offset in dwords */; 355 }; 356 357 /* 358 * Write init operation arguments 359 */ 360 union init_write_args 361 { 362 __le32 inline_val /* value to write, used when init source is INIT_SRC_INLINE */; 363 __le32 zeros_count /* number of zeros to write, used when init source is INIT_SRC_ZEROS */; 364 __le32 array_offset /* array offset to write, used when init source is INIT_SRC_ARRAY */; 365 struct init_op_array_params runtime /* runtime array params to write, used when init source is INIT_SRC_RUNTIME */; 366 }; 367 368 /* 369 * init operation: write 370 */ 371 struct init_write_op 372 { 373 __le32 data; 374 #define INIT_WRITE_OP_OP_MASK 0xF /* init operation, from init_op_types enum */ 375 #define INIT_WRITE_OP_OP_SHIFT 0 376 #define INIT_WRITE_OP_SOURCE_MASK 0x7 /* init source type, taken from init_source_types enum */ 377 #define INIT_WRITE_OP_SOURCE_SHIFT 4 378 #define INIT_WRITE_OP_RESERVED_MASK 0x1 379 #define INIT_WRITE_OP_RESERVED_SHIFT 7 380 #define INIT_WRITE_OP_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */ 381 #define INIT_WRITE_OP_WIDE_BUS_SHIFT 8 382 #define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF /* internal (absolute) GRC address, in dwords */ 383 #define INIT_WRITE_OP_ADDRESS_SHIFT 9 384 union init_write_args args /* Write init operation arguments */; 385 }; 386 387 /* 388 * init operation: read 389 */ 390 struct init_read_op 391 { 392 __le32 op_data; 393 #define INIT_READ_OP_OP_MASK 0xF /* init operation, from init_op_types enum */ 394 #define INIT_READ_OP_OP_SHIFT 0 395 #define INIT_READ_OP_POLL_TYPE_MASK 0xF /* polling type, from init_poll_types enum */ 396 #define INIT_READ_OP_POLL_TYPE_SHIFT 4 397 #define INIT_READ_OP_RESERVED_MASK 0x1 398 #define INIT_READ_OP_RESERVED_SHIFT 8 399 #define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF /* internal (absolute) GRC address, in dwords */ 400 #define INIT_READ_OP_ADDRESS_SHIFT 9 401 __le32 expected_val /* expected polling value, used only when polling is done */; 402 }; 403 404 /* 405 * Init operations union 406 */ 407 union init_op 408 { 409 struct init_raw_op raw /* raw init operation */; 410 struct init_write_op write /* write init operation */; 411 struct init_read_op read /* read init operation */; 412 struct init_if_mode_op if_mode /* if_mode init operation */; 413 struct init_if_phase_op if_phase /* if_phase init operation */; 414 struct init_callback_op callback /* callback init operation */; 415 struct init_delay_op delay /* delay init operation */; 416 }; 417 418 419 420 /* 421 * Init command operation types 422 */ 423 enum init_op_types 424 { 425 INIT_OP_READ /* GRC read init command */, 426 INIT_OP_WRITE /* GRC write init command */, 427 INIT_OP_IF_MODE /* Skip init commands if the init modes expression doesnt match */, 428 INIT_OP_IF_PHASE /* Skip init commands if the init phase doesnt match */, 429 INIT_OP_DELAY /* delay init command */, 430 INIT_OP_CALLBACK /* callback init command */, 431 MAX_INIT_OP_TYPES 432 }; 433 434 435 /* 436 * init polling types 437 */ 438 enum init_poll_types 439 { 440 INIT_POLL_NONE /* No polling */, 441 INIT_POLL_EQ /* init value is included in the init command */, 442 INIT_POLL_OR /* init value is all zeros */, 443 INIT_POLL_AND /* init value is an array of values */, 444 MAX_INIT_POLL_TYPES 445 }; 446 447 448 449 450 /* 451 * init source types 452 */ 453 enum init_source_types 454 { 455 INIT_SRC_INLINE /* init value is included in the init command */, 456 INIT_SRC_ZEROS /* init value is all zeros */, 457 INIT_SRC_ARRAY /* init value is an array of values */, 458 INIT_SRC_RUNTIME /* init value is provided during runtime */, 459 MAX_INIT_SOURCE_TYPES 460 }; 461 462 463 464 465 /* 466 * Internal RAM Offsets macro data 467 */ 468 struct iro 469 { 470 __le32 base /* RAM field offset */; 471 __le16 m1 /* multiplier 1 */; 472 __le16 m2 /* multiplier 2 */; 473 __le16 m3 /* multiplier 3 */; 474 __le16 size /* RAM field size */; 475 }; 476 477 #endif /* __ECORE_HSI_INIT_TOOL__ */ 478