114b24e2bSVaishali Kulkarni /*
214b24e2bSVaishali Kulkarni * CDDL HEADER START
314b24e2bSVaishali Kulkarni *
414b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the
514b24e2bSVaishali Kulkarni * Common Development and Distribution License, v.1, (the "License").
614b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License.
714b24e2bSVaishali Kulkarni *
814b24e2bSVaishali Kulkarni * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
914b24e2bSVaishali Kulkarni * or http://opensource.org/licenses/CDDL-1.0.
1014b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions
1114b24e2bSVaishali Kulkarni * and limitations under the License.
1214b24e2bSVaishali Kulkarni *
1314b24e2bSVaishali Kulkarni * When distributing Covered Code, include this CDDL HEADER in each
1414b24e2bSVaishali Kulkarni * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1514b24e2bSVaishali Kulkarni * If applicable, add the following below this CDDL HEADER, with the
1614b24e2bSVaishali Kulkarni * fields enclosed by brackets "[]" replaced with your own identifying
1714b24e2bSVaishali Kulkarni * information: Portions Copyright [yyyy] [name of copyright owner]
1814b24e2bSVaishali Kulkarni *
1914b24e2bSVaishali Kulkarni * CDDL HEADER END
2014b24e2bSVaishali Kulkarni */
2114b24e2bSVaishali Kulkarni
2214b24e2bSVaishali Kulkarni /*
2314b24e2bSVaishali Kulkarni * Copyright 2014-2017 Cavium, Inc.
2414b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the Common Development
2514b24e2bSVaishali Kulkarni * and Distribution License, v.1, (the "License").
2614b24e2bSVaishali Kulkarni
2714b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License.
2814b24e2bSVaishali Kulkarni
2914b24e2bSVaishali Kulkarni * You can obtain a copy of the License at available
3014b24e2bSVaishali Kulkarni * at http://opensource.org/licenses/CDDL-1.0
3114b24e2bSVaishali Kulkarni
3214b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions and
3314b24e2bSVaishali Kulkarni * limitations under the License.
3414b24e2bSVaishali Kulkarni */
3514b24e2bSVaishali Kulkarni
3614b24e2bSVaishali Kulkarni #include "bcm_osal.h"
3714b24e2bSVaishali Kulkarni #include "ecore_hw.h"
3814b24e2bSVaishali Kulkarni #include "ecore_init_ops.h"
3914b24e2bSVaishali Kulkarni #include "reg_addr.h"
4014b24e2bSVaishali Kulkarni #include "ecore_rt_defs.h"
4114b24e2bSVaishali Kulkarni #include "ecore_hsi_common.h"
4214b24e2bSVaishali Kulkarni #include "ecore_hsi_init_func.h"
4314b24e2bSVaishali Kulkarni #include "ecore_hsi_eth.h"
4414b24e2bSVaishali Kulkarni #include "ecore_hsi_init_tool.h"
4514b24e2bSVaishali Kulkarni #include "ecore_iro.h"
4614b24e2bSVaishali Kulkarni #include "ecore_init_fw_funcs.h"
4714b24e2bSVaishali Kulkarni
4814b24e2bSVaishali Kulkarni #define CDU_VALIDATION_DEFAULT_CFG 61
4914b24e2bSVaishali Kulkarni
5014b24e2bSVaishali Kulkarni static u16 con_region_offsets[3][E4_NUM_OF_CONNECTION_TYPES] = {
5114b24e2bSVaishali Kulkarni { 400, 336, 352, 304, 304, 384, 416, 352}, /* region 3 offsets */
5214b24e2bSVaishali Kulkarni { 528, 496, 416, 448, 448, 512, 544, 480}, /* region 4 offsets */
5314b24e2bSVaishali Kulkarni { 608, 544, 496, 512, 576, 592, 624, 560} /* region 5 offsets */
5414b24e2bSVaishali Kulkarni };
5514b24e2bSVaishali Kulkarni static u16 task_region_offsets[1][E4_NUM_OF_CONNECTION_TYPES] = {
5614b24e2bSVaishali Kulkarni { 240, 240, 112, 0, 0, 0, 0, 96} /* region 1 offsets */
5714b24e2bSVaishali Kulkarni };
5814b24e2bSVaishali Kulkarni
5914b24e2bSVaishali Kulkarni /* General constants */
6014b24e2bSVaishali Kulkarni #define QM_PQ_MEM_4KB(pq_size) (pq_size ? DIV_ROUND_UP((pq_size + 1) * QM_PQ_ELEMENT_SIZE, 0x1000) : 0)
6114b24e2bSVaishali Kulkarni #define QM_PQ_SIZE_256B(pq_size) (pq_size ? DIV_ROUND_UP(pq_size, 0x100) - 1 : 0)
6214b24e2bSVaishali Kulkarni #define QM_INVALID_PQ_ID 0xffff
6314b24e2bSVaishali Kulkarni
6414b24e2bSVaishali Kulkarni /* Feature enable */
6514b24e2bSVaishali Kulkarni #define QM_BYPASS_EN 1
6614b24e2bSVaishali Kulkarni #define QM_BYTE_CRD_EN 1
6714b24e2bSVaishali Kulkarni
6814b24e2bSVaishali Kulkarni /* Other PQ constants */
6914b24e2bSVaishali Kulkarni #define QM_OTHER_PQS_PER_PF 4
7014b24e2bSVaishali Kulkarni
7114b24e2bSVaishali Kulkarni /* WFQ constants: */
7214b24e2bSVaishali Kulkarni
7314b24e2bSVaishali Kulkarni /* Upper bound in MB, 10 * burst size of 1ms in 50Gbps */
7414b24e2bSVaishali Kulkarni #define QM_WFQ_UPPER_BOUND 62500000
7514b24e2bSVaishali Kulkarni
7614b24e2bSVaishali Kulkarni /* Bit of VOQ in WFQ VP PQ map */
7714b24e2bSVaishali Kulkarni #define QM_WFQ_VP_PQ_VOQ_SHIFT 0
7814b24e2bSVaishali Kulkarni
7914b24e2bSVaishali Kulkarni /* Bit of PF in WFQ VP PQ map */
8014b24e2bSVaishali Kulkarni #define QM_WFQ_VP_PQ_PF_SHIFT 5
8114b24e2bSVaishali Kulkarni
8214b24e2bSVaishali Kulkarni /* 0x9000 = 4*9*1024 */
8314b24e2bSVaishali Kulkarni #define QM_WFQ_INC_VAL(weight) ((weight) * 0x9000)
8414b24e2bSVaishali Kulkarni
8514b24e2bSVaishali Kulkarni /* 0.7 * upper bound (62500000) */
8614b24e2bSVaishali Kulkarni #define QM_WFQ_MAX_INC_VAL 43750000
8714b24e2bSVaishali Kulkarni
8814b24e2bSVaishali Kulkarni /* RL constants: */
8914b24e2bSVaishali Kulkarni
9014b24e2bSVaishali Kulkarni /* Upper bound is set to 10 * burst size of 1ms in 50Gbps */
9114b24e2bSVaishali Kulkarni #define QM_RL_UPPER_BOUND 62500000
9214b24e2bSVaishali Kulkarni
9314b24e2bSVaishali Kulkarni /* Period in us */
9414b24e2bSVaishali Kulkarni #define QM_RL_PERIOD 5
9514b24e2bSVaishali Kulkarni
9614b24e2bSVaishali Kulkarni /* Period in 25MHz cycles */
9714b24e2bSVaishali Kulkarni #define QM_RL_PERIOD_CLK_25M (25 * QM_RL_PERIOD)
9814b24e2bSVaishali Kulkarni
9914b24e2bSVaishali Kulkarni /* 0.7 * upper bound (62500000) */
10014b24e2bSVaishali Kulkarni #define QM_RL_MAX_INC_VAL 43750000
10114b24e2bSVaishali Kulkarni
10214b24e2bSVaishali Kulkarni /* RL increment value - rate is specified in mbps. the factor of 1.01 was
10314b24e2bSVaishali Kulkarni * added after seeing only 99% factor reached in a 25Gbps port with DPDK RFC
10414b24e2bSVaishali Kulkarni * 2544 test. In this scenario the PF RL was reducing the line rate to 99%
10514b24e2bSVaishali Kulkarni * although the credit increment value was the correct one and FW calculated
10614b24e2bSVaishali Kulkarni * correct packet sizes. The reason for the inaccuracy of the RL is unknown at
10714b24e2bSVaishali Kulkarni * this point.
10814b24e2bSVaishali Kulkarni */
10914b24e2bSVaishali Kulkarni #define QM_RL_INC_VAL(rate) OSAL_MAX_T(u32, (u32)(((rate ? rate : 1000000) * QM_RL_PERIOD * 101) / (8 * 100)), 1)
11014b24e2bSVaishali Kulkarni
11114b24e2bSVaishali Kulkarni /* AFullOprtnstcCrdMask constants */
11214b24e2bSVaishali Kulkarni #define QM_OPPOR_LINE_VOQ_DEF 1
11314b24e2bSVaishali Kulkarni #define QM_OPPOR_FW_STOP_DEF 0
11414b24e2bSVaishali Kulkarni #define QM_OPPOR_PQ_EMPTY_DEF 1
11514b24e2bSVaishali Kulkarni
11614b24e2bSVaishali Kulkarni /* Command Queue constants: */
11714b24e2bSVaishali Kulkarni
11814b24e2bSVaishali Kulkarni /* Pure LB CmdQ lines (+spare) */
11914b24e2bSVaishali Kulkarni #define PBF_CMDQ_PURE_LB_LINES 150
12014b24e2bSVaishali Kulkarni
12114b24e2bSVaishali Kulkarni #define PBF_CMDQ_LINES_RT_OFFSET(voq) (PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET + voq * (PBF_REG_YCMD_QS_NUM_LINES_VOQ1_RT_OFFSET - PBF_REG_YCMD_QS_NUM_LINES_VOQ0_RT_OFFSET))
12214b24e2bSVaishali Kulkarni
12314b24e2bSVaishali Kulkarni #define PBF_BTB_GUARANTEED_RT_OFFSET(voq) (PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET + voq * (PBF_REG_BTB_GUARANTEED_VOQ1_RT_OFFSET - PBF_REG_BTB_GUARANTEED_VOQ0_RT_OFFSET))
12414b24e2bSVaishali Kulkarni
12514b24e2bSVaishali Kulkarni #define QM_VOQ_LINE_CRD(pbf_cmd_lines) ((((pbf_cmd_lines) - 4) * 2) | QM_LINE_CRD_REG_SIGN_BIT)
12614b24e2bSVaishali Kulkarni
12714b24e2bSVaishali Kulkarni /* BTB: blocks constants (block size = 256B) */
12814b24e2bSVaishali Kulkarni
12914b24e2bSVaishali Kulkarni /* 256B blocks in 9700B packet */
13014b24e2bSVaishali Kulkarni #define BTB_JUMBO_PKT_BLOCKS 38
13114b24e2bSVaishali Kulkarni
13214b24e2bSVaishali Kulkarni /* Headroom per-port */
13314b24e2bSVaishali Kulkarni #define BTB_HEADROOM_BLOCKS BTB_JUMBO_PKT_BLOCKS
13414b24e2bSVaishali Kulkarni #define BTB_PURE_LB_FACTOR 10
13514b24e2bSVaishali Kulkarni
13614b24e2bSVaishali Kulkarni /* Factored (hence really 0.7) */
13714b24e2bSVaishali Kulkarni #define BTB_PURE_LB_RATIO 7
13814b24e2bSVaishali Kulkarni
13914b24e2bSVaishali Kulkarni /* QM stop command constants */
14014b24e2bSVaishali Kulkarni #define QM_STOP_PQ_MASK_WIDTH 32
14114b24e2bSVaishali Kulkarni #define QM_STOP_CMD_ADDR 2
14214b24e2bSVaishali Kulkarni #define QM_STOP_CMD_STRUCT_SIZE 2
14314b24e2bSVaishali Kulkarni #define QM_STOP_CMD_PAUSE_MASK_OFFSET 0
14414b24e2bSVaishali Kulkarni #define QM_STOP_CMD_PAUSE_MASK_SHIFT 0
145*7e3488dcSToomas Soome #define QM_STOP_CMD_PAUSE_MASK_MASK UINT_MAX
14614b24e2bSVaishali Kulkarni #define QM_STOP_CMD_GROUP_ID_OFFSET 1
14714b24e2bSVaishali Kulkarni #define QM_STOP_CMD_GROUP_ID_SHIFT 16
14814b24e2bSVaishali Kulkarni #define QM_STOP_CMD_GROUP_ID_MASK 15
14914b24e2bSVaishali Kulkarni #define QM_STOP_CMD_PQ_TYPE_OFFSET 1
15014b24e2bSVaishali Kulkarni #define QM_STOP_CMD_PQ_TYPE_SHIFT 24
15114b24e2bSVaishali Kulkarni #define QM_STOP_CMD_PQ_TYPE_MASK 1
15214b24e2bSVaishali Kulkarni #define QM_STOP_CMD_MAX_POLL_COUNT 100
15314b24e2bSVaishali Kulkarni #define QM_STOP_CMD_POLL_PERIOD_US 500
15414b24e2bSVaishali Kulkarni
15514b24e2bSVaishali Kulkarni /* QM command macros */
15614b24e2bSVaishali Kulkarni #define QM_CMD_STRUCT_SIZE(cmd) cmd##_STRUCT_SIZE
15714b24e2bSVaishali Kulkarni #define QM_CMD_SET_FIELD(var, cmd, field, value) SET_FIELD(var[cmd##_##field##_OFFSET], cmd##_##field, value)
15814b24e2bSVaishali Kulkarni
15914b24e2bSVaishali Kulkarni /* QM: VOQ macros */
16014b24e2bSVaishali Kulkarni #define PHYS_VOQ(port, tc, max_phys_tcs_per_port) ((port) * (max_phys_tcs_per_port) + (tc))
16114b24e2bSVaishali Kulkarni #define LB_VOQ(port) (MAX_PHYS_VOQS + (port))
16214b24e2bSVaishali Kulkarni #define VOQ(port, tc, max_phys_tcs_per_port) ((tc) < LB_TC ? PHYS_VOQ(port, tc, max_phys_tcs_per_port) : LB_VOQ(port))
16314b24e2bSVaishali Kulkarni
16414b24e2bSVaishali Kulkarni
16514b24e2bSVaishali Kulkarni /******************** INTERNAL IMPLEMENTATION *********************/
16614b24e2bSVaishali Kulkarni
16714b24e2bSVaishali Kulkarni /* Prepare PF RL enable/disable runtime init values */
ecore_enable_pf_rl(struct ecore_hwfn * p_hwfn,bool pf_rl_en)16814b24e2bSVaishali Kulkarni static void ecore_enable_pf_rl(struct ecore_hwfn *p_hwfn,
16914b24e2bSVaishali Kulkarni bool pf_rl_en)
17014b24e2bSVaishali Kulkarni {
17114b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_RLPFENABLE_RT_OFFSET, pf_rl_en ? 1 : 0);
17214b24e2bSVaishali Kulkarni if (pf_rl_en) {
17314b24e2bSVaishali Kulkarni
17414b24e2bSVaishali Kulkarni /* Enable RLs for all VOQs */
17514b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_RLPFVOQENABLE_RT_OFFSET, (1 << MAX_NUM_VOQS) - 1);
17614b24e2bSVaishali Kulkarni
17714b24e2bSVaishali Kulkarni /* Write RL period */
17814b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_RLPFPERIOD_RT_OFFSET, QM_RL_PERIOD_CLK_25M);
17914b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_RLPFPERIODTIMER_RT_OFFSET, QM_RL_PERIOD_CLK_25M);
18014b24e2bSVaishali Kulkarni
18114b24e2bSVaishali Kulkarni /* Set credit threshold for QM bypass flow */
18214b24e2bSVaishali Kulkarni if (QM_BYPASS_EN)
18314b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET, QM_RL_UPPER_BOUND);
18414b24e2bSVaishali Kulkarni }
18514b24e2bSVaishali Kulkarni }
18614b24e2bSVaishali Kulkarni
18714b24e2bSVaishali Kulkarni /* Prepare PF WFQ enable/disable runtime init values */
ecore_enable_pf_wfq(struct ecore_hwfn * p_hwfn,bool pf_wfq_en)18814b24e2bSVaishali Kulkarni static void ecore_enable_pf_wfq(struct ecore_hwfn *p_hwfn,
18914b24e2bSVaishali Kulkarni bool pf_wfq_en)
19014b24e2bSVaishali Kulkarni {
19114b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_WFQPFENABLE_RT_OFFSET, pf_wfq_en ? 1 : 0);
19214b24e2bSVaishali Kulkarni
19314b24e2bSVaishali Kulkarni /* Set credit threshold for QM bypass flow */
19414b24e2bSVaishali Kulkarni if (pf_wfq_en && QM_BYPASS_EN)
19514b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET, QM_WFQ_UPPER_BOUND);
19614b24e2bSVaishali Kulkarni }
19714b24e2bSVaishali Kulkarni
19814b24e2bSVaishali Kulkarni /* Prepare VPORT RL enable/disable runtime init values */
ecore_enable_vport_rl(struct ecore_hwfn * p_hwfn,bool vport_rl_en)19914b24e2bSVaishali Kulkarni static void ecore_enable_vport_rl(struct ecore_hwfn *p_hwfn,
20014b24e2bSVaishali Kulkarni bool vport_rl_en)
20114b24e2bSVaishali Kulkarni {
20214b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_RLGLBLENABLE_RT_OFFSET, vport_rl_en ? 1 : 0);
20314b24e2bSVaishali Kulkarni if (vport_rl_en) {
20414b24e2bSVaishali Kulkarni
20514b24e2bSVaishali Kulkarni /* Write RL period (use timer 0 only) */
20614b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_RLGLBLPERIOD_0_RT_OFFSET, QM_RL_PERIOD_CLK_25M);
20714b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET, QM_RL_PERIOD_CLK_25M);
20814b24e2bSVaishali Kulkarni
20914b24e2bSVaishali Kulkarni /* Set credit threshold for QM bypass flow */
21014b24e2bSVaishali Kulkarni if (QM_BYPASS_EN)
21114b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET, QM_RL_UPPER_BOUND);
21214b24e2bSVaishali Kulkarni }
21314b24e2bSVaishali Kulkarni }
21414b24e2bSVaishali Kulkarni
21514b24e2bSVaishali Kulkarni /* Prepare VPORT WFQ enable/disable runtime init values */
ecore_enable_vport_wfq(struct ecore_hwfn * p_hwfn,bool vport_wfq_en)21614b24e2bSVaishali Kulkarni static void ecore_enable_vport_wfq(struct ecore_hwfn *p_hwfn,
21714b24e2bSVaishali Kulkarni bool vport_wfq_en)
21814b24e2bSVaishali Kulkarni {
21914b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_WFQVPENABLE_RT_OFFSET, vport_wfq_en ? 1 : 0);
22014b24e2bSVaishali Kulkarni
22114b24e2bSVaishali Kulkarni /* Set credit threshold for QM bypass flow */
22214b24e2bSVaishali Kulkarni if (vport_wfq_en && QM_BYPASS_EN)
22314b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET, QM_WFQ_UPPER_BOUND);
22414b24e2bSVaishali Kulkarni }
22514b24e2bSVaishali Kulkarni
22614b24e2bSVaishali Kulkarni /* Prepare runtime init values to allocate PBF command queue lines for
22714b24e2bSVaishali Kulkarni * the specified VOQ.
22814b24e2bSVaishali Kulkarni */
ecore_cmdq_lines_voq_rt_init(struct ecore_hwfn * p_hwfn,u8 voq,u16 cmdq_lines)22914b24e2bSVaishali Kulkarni static void ecore_cmdq_lines_voq_rt_init(struct ecore_hwfn *p_hwfn,
23014b24e2bSVaishali Kulkarni u8 voq,
23114b24e2bSVaishali Kulkarni u16 cmdq_lines)
23214b24e2bSVaishali Kulkarni {
23314b24e2bSVaishali Kulkarni u32 qm_line_crd;
23414b24e2bSVaishali Kulkarni
23514b24e2bSVaishali Kulkarni qm_line_crd = QM_VOQ_LINE_CRD(cmdq_lines);
23614b24e2bSVaishali Kulkarni
23714b24e2bSVaishali Kulkarni OVERWRITE_RT_REG(p_hwfn, PBF_CMDQ_LINES_RT_OFFSET(voq), (u32)cmdq_lines);
23814b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_VOQCRDLINE_RT_OFFSET + voq, qm_line_crd);
23914b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_VOQINITCRDLINE_RT_OFFSET + voq, qm_line_crd);
24014b24e2bSVaishali Kulkarni }
24114b24e2bSVaishali Kulkarni
24214b24e2bSVaishali Kulkarni /* Prepare runtime init values to allocate PBF command queue lines. */
ecore_cmdq_lines_rt_init(struct ecore_hwfn * p_hwfn,u8 max_ports_per_engine,u8 max_phys_tcs_per_port,struct init_qm_port_params port_params[MAX_NUM_PORTS])24314b24e2bSVaishali Kulkarni static void ecore_cmdq_lines_rt_init(struct ecore_hwfn *p_hwfn,
24414b24e2bSVaishali Kulkarni u8 max_ports_per_engine,
24514b24e2bSVaishali Kulkarni u8 max_phys_tcs_per_port,
24614b24e2bSVaishali Kulkarni struct init_qm_port_params port_params[MAX_NUM_PORTS])
24714b24e2bSVaishali Kulkarni {
24814b24e2bSVaishali Kulkarni u8 tc, voq, port_id, num_tcs_in_port;
24914b24e2bSVaishali Kulkarni
25014b24e2bSVaishali Kulkarni /* Clear PBF lines for all VOQs */
25114b24e2bSVaishali Kulkarni for (voq = 0; voq < MAX_NUM_VOQS; voq++)
25214b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, PBF_CMDQ_LINES_RT_OFFSET(voq), 0);
25314b24e2bSVaishali Kulkarni
25414b24e2bSVaishali Kulkarni for (port_id = 0; port_id < max_ports_per_engine; port_id++) {
25514b24e2bSVaishali Kulkarni u16 phys_lines, phys_lines_per_tc;
25614b24e2bSVaishali Kulkarni
25714b24e2bSVaishali Kulkarni if (!port_params[port_id].active)
25814b24e2bSVaishali Kulkarni continue;
25914b24e2bSVaishali Kulkarni
26014b24e2bSVaishali Kulkarni /* Find #lines to divide between the active physical TCs */
26114b24e2bSVaishali Kulkarni phys_lines = port_params[port_id].num_pbf_cmd_lines - PBF_CMDQ_PURE_LB_LINES;
26214b24e2bSVaishali Kulkarni
26314b24e2bSVaishali Kulkarni /* Find #lines per active physical TC */
26414b24e2bSVaishali Kulkarni num_tcs_in_port = 0;
26514b24e2bSVaishali Kulkarni for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++)
26614b24e2bSVaishali Kulkarni if (((port_params[port_id].active_phys_tcs >> tc) & 0x1) == 1)
26714b24e2bSVaishali Kulkarni num_tcs_in_port++;
26814b24e2bSVaishali Kulkarni phys_lines_per_tc = phys_lines / num_tcs_in_port;
26914b24e2bSVaishali Kulkarni
27014b24e2bSVaishali Kulkarni /* Init registers per active TC */
27114b24e2bSVaishali Kulkarni for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) {
27214b24e2bSVaishali Kulkarni if (((port_params[port_id].active_phys_tcs >> tc) & 0x1) == 1) {
27314b24e2bSVaishali Kulkarni voq = PHYS_VOQ(port_id, tc, max_phys_tcs_per_port);
27414b24e2bSVaishali Kulkarni ecore_cmdq_lines_voq_rt_init(p_hwfn, voq, phys_lines_per_tc);
27514b24e2bSVaishali Kulkarni }
27614b24e2bSVaishali Kulkarni }
27714b24e2bSVaishali Kulkarni
27814b24e2bSVaishali Kulkarni /* Init registers for pure LB TC */
27914b24e2bSVaishali Kulkarni ecore_cmdq_lines_voq_rt_init(p_hwfn, LB_VOQ(port_id), PBF_CMDQ_PURE_LB_LINES);
28014b24e2bSVaishali Kulkarni }
28114b24e2bSVaishali Kulkarni }
28214b24e2bSVaishali Kulkarni
28314b24e2bSVaishali Kulkarni /* Prepare runtime init values to allocate guaranteed BTB blocks for the
28414b24e2bSVaishali Kulkarni * specified port. The guaranteed BTB space is divided between the TCs as
28514b24e2bSVaishali Kulkarni * follows (shared space Is currently not used):
28614b24e2bSVaishali Kulkarni * 1. Parameters:
28714b24e2bSVaishali Kulkarni * B - BTB blocks for this port
28814b24e2bSVaishali Kulkarni * C - Number of physical TCs for this port
28914b24e2bSVaishali Kulkarni * 2. Calculation:
29014b24e2bSVaishali Kulkarni * a. 38 blocks (9700B jumbo frame) are allocated for global per port
29114b24e2bSVaishali Kulkarni * headroom.
29214b24e2bSVaishali Kulkarni * b. B = B - 38 (remainder after global headroom allocation).
29314b24e2bSVaishali Kulkarni * c. MAX(38,B/(C+0.7)) blocks are allocated for the pure LB VOQ.
29414b24e2bSVaishali Kulkarni * d. B = B � MAX(38, B/(C+0.7)) (remainder after pure LB allocation).
29514b24e2bSVaishali Kulkarni * e. B/C blocks are allocated for each physical TC.
29614b24e2bSVaishali Kulkarni * Assumptions:
29714b24e2bSVaishali Kulkarni * - MTU is up to 9700 bytes (38 blocks)
29814b24e2bSVaishali Kulkarni * - All TCs are considered symmetrical (same rate and packet size)
29914b24e2bSVaishali Kulkarni * - No optimization for lossy TC (all are considered lossless). Shared space
30014b24e2bSVaishali Kulkarni * is not enabled and allocated for each TC.
30114b24e2bSVaishali Kulkarni */
ecore_btb_blocks_rt_init(struct ecore_hwfn * p_hwfn,u8 max_ports_per_engine,u8 max_phys_tcs_per_port,struct init_qm_port_params port_params[MAX_NUM_PORTS])30214b24e2bSVaishali Kulkarni static void ecore_btb_blocks_rt_init(struct ecore_hwfn *p_hwfn,
30314b24e2bSVaishali Kulkarni u8 max_ports_per_engine,
30414b24e2bSVaishali Kulkarni u8 max_phys_tcs_per_port,
30514b24e2bSVaishali Kulkarni struct init_qm_port_params port_params[MAX_NUM_PORTS])
30614b24e2bSVaishali Kulkarni {
30714b24e2bSVaishali Kulkarni u32 usable_blocks, pure_lb_blocks, phys_blocks;
30814b24e2bSVaishali Kulkarni u8 tc, voq, port_id, num_tcs_in_port;
30914b24e2bSVaishali Kulkarni
31014b24e2bSVaishali Kulkarni for (port_id = 0; port_id < max_ports_per_engine; port_id++) {
31114b24e2bSVaishali Kulkarni if (!port_params[port_id].active)
31214b24e2bSVaishali Kulkarni continue;
31314b24e2bSVaishali Kulkarni
31414b24e2bSVaishali Kulkarni /* Subtract headroom blocks */
31514b24e2bSVaishali Kulkarni usable_blocks = port_params[port_id].num_btb_blocks - BTB_HEADROOM_BLOCKS;
31614b24e2bSVaishali Kulkarni
31714b24e2bSVaishali Kulkarni /* Find blocks per physical TC. use factor to avoid floating
31814b24e2bSVaishali Kulkarni * arithmethic.
31914b24e2bSVaishali Kulkarni */
32014b24e2bSVaishali Kulkarni num_tcs_in_port = 0;
32114b24e2bSVaishali Kulkarni for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++)
32214b24e2bSVaishali Kulkarni if (((port_params[port_id].active_phys_tcs >> tc) & 0x1) == 1)
32314b24e2bSVaishali Kulkarni num_tcs_in_port++;
32414b24e2bSVaishali Kulkarni
32514b24e2bSVaishali Kulkarni pure_lb_blocks = (usable_blocks * BTB_PURE_LB_FACTOR) / (num_tcs_in_port * BTB_PURE_LB_FACTOR + BTB_PURE_LB_RATIO);
32614b24e2bSVaishali Kulkarni pure_lb_blocks = OSAL_MAX_T(u32, BTB_JUMBO_PKT_BLOCKS, pure_lb_blocks / BTB_PURE_LB_FACTOR);
32714b24e2bSVaishali Kulkarni phys_blocks = (usable_blocks - pure_lb_blocks) / num_tcs_in_port;
32814b24e2bSVaishali Kulkarni
32914b24e2bSVaishali Kulkarni /* Init physical TCs */
33014b24e2bSVaishali Kulkarni for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) {
33114b24e2bSVaishali Kulkarni if (((port_params[port_id].active_phys_tcs >> tc) & 0x1) == 1) {
33214b24e2bSVaishali Kulkarni voq = PHYS_VOQ(port_id, tc, max_phys_tcs_per_port);
33314b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, PBF_BTB_GUARANTEED_RT_OFFSET(voq), phys_blocks);
33414b24e2bSVaishali Kulkarni }
33514b24e2bSVaishali Kulkarni }
33614b24e2bSVaishali Kulkarni
33714b24e2bSVaishali Kulkarni /* Init pure LB TC */
33814b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, PBF_BTB_GUARANTEED_RT_OFFSET(LB_VOQ(port_id)), pure_lb_blocks);
33914b24e2bSVaishali Kulkarni }
34014b24e2bSVaishali Kulkarni }
34114b24e2bSVaishali Kulkarni
34214b24e2bSVaishali Kulkarni /* Prepare Tx PQ mapping runtime init values for the specified PF */
ecore_tx_pq_map_rt_init(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u8 port_id,u8 pf_id,u8 max_phys_tcs_per_port,bool is_first_pf,u32 num_pf_cids,u32 num_vf_cids,u16 start_pq,u16 num_pf_pqs,u16 num_vf_pqs,u8 start_vport,u32 base_mem_addr_4kb,struct init_qm_pq_params * pq_params,struct init_qm_vport_params * vport_params)34314b24e2bSVaishali Kulkarni static void ecore_tx_pq_map_rt_init(struct ecore_hwfn *p_hwfn,
34414b24e2bSVaishali Kulkarni struct ecore_ptt *p_ptt,
34514b24e2bSVaishali Kulkarni u8 port_id,
34614b24e2bSVaishali Kulkarni u8 pf_id,
34714b24e2bSVaishali Kulkarni u8 max_phys_tcs_per_port,
34814b24e2bSVaishali Kulkarni bool is_first_pf,
34914b24e2bSVaishali Kulkarni u32 num_pf_cids,
35014b24e2bSVaishali Kulkarni u32 num_vf_cids,
35114b24e2bSVaishali Kulkarni u16 start_pq,
35214b24e2bSVaishali Kulkarni u16 num_pf_pqs,
35314b24e2bSVaishali Kulkarni u16 num_vf_pqs,
35414b24e2bSVaishali Kulkarni u8 start_vport,
35514b24e2bSVaishali Kulkarni u32 base_mem_addr_4kb,
35614b24e2bSVaishali Kulkarni struct init_qm_pq_params *pq_params,
35714b24e2bSVaishali Kulkarni struct init_qm_vport_params *vport_params)
35814b24e2bSVaishali Kulkarni {
35914b24e2bSVaishali Kulkarni /* A bit per Tx PQ indicating if the PQ is associated with a VF */
36014b24e2bSVaishali Kulkarni u32 tx_pq_vf_mask[MAX_QM_TX_QUEUES / QM_PF_QUEUE_GROUP_SIZE] = { 0 };
36114b24e2bSVaishali Kulkarni u32 num_tx_pq_vf_masks = MAX_QM_TX_QUEUES / QM_PF_QUEUE_GROUP_SIZE;
36214b24e2bSVaishali Kulkarni u16 num_pqs, first_pq_group, last_pq_group, i, pq_id, pq_group;
36314b24e2bSVaishali Kulkarni u32 pq_mem_4kb, vport_pq_mem_4kb, mem_addr_4kb;
36414b24e2bSVaishali Kulkarni
36514b24e2bSVaishali Kulkarni num_pqs = num_pf_pqs + num_vf_pqs;
36614b24e2bSVaishali Kulkarni
36714b24e2bSVaishali Kulkarni first_pq_group = start_pq / QM_PF_QUEUE_GROUP_SIZE;
36814b24e2bSVaishali Kulkarni last_pq_group = (start_pq + num_pqs - 1) / QM_PF_QUEUE_GROUP_SIZE;
36914b24e2bSVaishali Kulkarni
37014b24e2bSVaishali Kulkarni pq_mem_4kb = QM_PQ_MEM_4KB(num_pf_cids);
37114b24e2bSVaishali Kulkarni vport_pq_mem_4kb = QM_PQ_MEM_4KB(num_vf_cids);
37214b24e2bSVaishali Kulkarni mem_addr_4kb = base_mem_addr_4kb;
37314b24e2bSVaishali Kulkarni
37414b24e2bSVaishali Kulkarni /* Set mapping from PQ group to PF */
37514b24e2bSVaishali Kulkarni for (pq_group = first_pq_group; pq_group <= last_pq_group; pq_group++)
37614b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_PQTX2PF_0_RT_OFFSET + pq_group, (u32)(pf_id));
37714b24e2bSVaishali Kulkarni
37814b24e2bSVaishali Kulkarni /* Set PQ sizes */
37914b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_0_RT_OFFSET, QM_PQ_SIZE_256B(num_pf_cids));
38014b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_1_RT_OFFSET, QM_PQ_SIZE_256B(num_vf_cids));
38114b24e2bSVaishali Kulkarni
38214b24e2bSVaishali Kulkarni /* Go over all Tx PQs */
38314b24e2bSVaishali Kulkarni for (i = 0, pq_id = start_pq; i < num_pqs; i++, pq_id++) {
38414b24e2bSVaishali Kulkarni u32 max_qm_global_rls = MAX_QM_GLOBAL_RLS;
38514b24e2bSVaishali Kulkarni struct qm_rf_pq_map tx_pq_map;
38614b24e2bSVaishali Kulkarni bool is_vf_pq, rl_valid;
38714b24e2bSVaishali Kulkarni u8 voq, vport_id_in_pf;
38814b24e2bSVaishali Kulkarni u16 first_tx_pq_id;
38914b24e2bSVaishali Kulkarni
39014b24e2bSVaishali Kulkarni voq = VOQ(port_id, pq_params[i].tc_id, max_phys_tcs_per_port);
39114b24e2bSVaishali Kulkarni is_vf_pq = (i >= num_pf_pqs);
39214b24e2bSVaishali Kulkarni rl_valid = pq_params[i].rl_valid && pq_params[i].vport_id < max_qm_global_rls;
39314b24e2bSVaishali Kulkarni
39414b24e2bSVaishali Kulkarni /* Update first Tx PQ of VPORT/TC */
39514b24e2bSVaishali Kulkarni vport_id_in_pf = pq_params[i].vport_id - start_vport;
39614b24e2bSVaishali Kulkarni first_tx_pq_id = vport_params[vport_id_in_pf].first_tx_pq_id[pq_params[i].tc_id];
39714b24e2bSVaishali Kulkarni if (first_tx_pq_id == QM_INVALID_PQ_ID) {
39814b24e2bSVaishali Kulkarni
39914b24e2bSVaishali Kulkarni /* Create new VP PQ */
40014b24e2bSVaishali Kulkarni vport_params[vport_id_in_pf].first_tx_pq_id[pq_params[i].tc_id] = pq_id;
40114b24e2bSVaishali Kulkarni first_tx_pq_id = pq_id;
40214b24e2bSVaishali Kulkarni
40314b24e2bSVaishali Kulkarni /* Map VP PQ to VOQ and PF */
40414b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_WFQVPMAP_RT_OFFSET + first_tx_pq_id, (voq << QM_WFQ_VP_PQ_VOQ_SHIFT) | (pf_id << QM_WFQ_VP_PQ_PF_SHIFT));
40514b24e2bSVaishali Kulkarni }
40614b24e2bSVaishali Kulkarni
40714b24e2bSVaishali Kulkarni /* Check RL ID */
40814b24e2bSVaishali Kulkarni if (pq_params[i].rl_valid && pq_params[i].vport_id >= max_qm_global_rls)
40914b24e2bSVaishali Kulkarni DP_NOTICE(p_hwfn, true, "Invalid VPORT ID for rate limiter configuration\n");
41014b24e2bSVaishali Kulkarni
41114b24e2bSVaishali Kulkarni /* Fill PQ map entry */
41214b24e2bSVaishali Kulkarni OSAL_MEMSET(&tx_pq_map, 0, sizeof(tx_pq_map));
41314b24e2bSVaishali Kulkarni SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_PQ_VALID, 1);
41414b24e2bSVaishali Kulkarni SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_RL_VALID, rl_valid ? 1 : 0);
41514b24e2bSVaishali Kulkarni SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_VP_PQ_ID, first_tx_pq_id);
41614b24e2bSVaishali Kulkarni SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_RL_ID, rl_valid ? pq_params[i].vport_id : 0);
41714b24e2bSVaishali Kulkarni SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_VOQ, voq);
41814b24e2bSVaishali Kulkarni SET_FIELD(tx_pq_map.reg, QM_RF_PQ_MAP_WRR_WEIGHT_GROUP, pq_params[i].wrr_group);
41914b24e2bSVaishali Kulkarni
42014b24e2bSVaishali Kulkarni /* Write PQ map entry to CAM */
42114b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_TXPQMAP_RT_OFFSET + pq_id, *((u32*)&tx_pq_map));
42214b24e2bSVaishali Kulkarni
42314b24e2bSVaishali Kulkarni /* Set base address */
42414b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_BASEADDRTXPQ_RT_OFFSET + pq_id, mem_addr_4kb);
42514b24e2bSVaishali Kulkarni
42614b24e2bSVaishali Kulkarni /* If VF PQ, add indication to PQ VF mask */
42714b24e2bSVaishali Kulkarni if (is_vf_pq) {
42814b24e2bSVaishali Kulkarni tx_pq_vf_mask[pq_id / QM_PF_QUEUE_GROUP_SIZE] |= (1 << (pq_id % QM_PF_QUEUE_GROUP_SIZE));
42914b24e2bSVaishali Kulkarni mem_addr_4kb += vport_pq_mem_4kb;
43014b24e2bSVaishali Kulkarni }
43114b24e2bSVaishali Kulkarni else {
43214b24e2bSVaishali Kulkarni mem_addr_4kb += pq_mem_4kb;
43314b24e2bSVaishali Kulkarni }
43414b24e2bSVaishali Kulkarni }
43514b24e2bSVaishali Kulkarni
43614b24e2bSVaishali Kulkarni /* Store Tx PQ VF mask to size select register */
43714b24e2bSVaishali Kulkarni for (i = 0; i < num_tx_pq_vf_masks; i++)
43814b24e2bSVaishali Kulkarni if (tx_pq_vf_mask[i])
43914b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET + i, tx_pq_vf_mask[i]);
44014b24e2bSVaishali Kulkarni }
44114b24e2bSVaishali Kulkarni
44214b24e2bSVaishali Kulkarni /* Prepare Other PQ mapping runtime init values for the specified PF */
ecore_other_pq_map_rt_init(struct ecore_hwfn * p_hwfn,u8 port_id,u8 pf_id,u32 num_pf_cids,u32 num_tids,u32 base_mem_addr_4kb)44314b24e2bSVaishali Kulkarni static void ecore_other_pq_map_rt_init(struct ecore_hwfn *p_hwfn,
44414b24e2bSVaishali Kulkarni u8 port_id,
44514b24e2bSVaishali Kulkarni u8 pf_id,
44614b24e2bSVaishali Kulkarni u32 num_pf_cids,
44714b24e2bSVaishali Kulkarni u32 num_tids,
44814b24e2bSVaishali Kulkarni u32 base_mem_addr_4kb)
44914b24e2bSVaishali Kulkarni {
45014b24e2bSVaishali Kulkarni u32 pq_size, pq_mem_4kb, mem_addr_4kb;
45114b24e2bSVaishali Kulkarni u16 i, pq_id, pq_group;
45214b24e2bSVaishali Kulkarni
45314b24e2bSVaishali Kulkarni /* A single other PQ group is used in each PF, where PQ group i is used
45414b24e2bSVaishali Kulkarni * in PF i.
45514b24e2bSVaishali Kulkarni */
45614b24e2bSVaishali Kulkarni pq_group = pf_id;
45714b24e2bSVaishali Kulkarni pq_size = num_pf_cids + num_tids;
45814b24e2bSVaishali Kulkarni pq_mem_4kb = QM_PQ_MEM_4KB(pq_size);
45914b24e2bSVaishali Kulkarni mem_addr_4kb = base_mem_addr_4kb;
46014b24e2bSVaishali Kulkarni
46114b24e2bSVaishali Kulkarni /* Map PQ group to PF */
46214b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_PQOTHER2PF_0_RT_OFFSET + pq_group, (u32)(pf_id));
46314b24e2bSVaishali Kulkarni
46414b24e2bSVaishali Kulkarni /* Set PQ sizes */
46514b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_2_RT_OFFSET, QM_PQ_SIZE_256B(pq_size));
46614b24e2bSVaishali Kulkarni
46714b24e2bSVaishali Kulkarni /* Set base address */
46814b24e2bSVaishali Kulkarni for (i = 0, pq_id = pf_id * QM_PF_QUEUE_GROUP_SIZE; i < QM_OTHER_PQS_PER_PF; i++, pq_id++) {
46914b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_BASEADDROTHERPQ_RT_OFFSET + pq_id, mem_addr_4kb);
47014b24e2bSVaishali Kulkarni mem_addr_4kb += pq_mem_4kb;
47114b24e2bSVaishali Kulkarni }
47214b24e2bSVaishali Kulkarni }
47314b24e2bSVaishali Kulkarni
47414b24e2bSVaishali Kulkarni /* Prepare PF WFQ runtime init values for the specified PF.
47514b24e2bSVaishali Kulkarni * Return -1 on error.
47614b24e2bSVaishali Kulkarni */
ecore_pf_wfq_rt_init(struct ecore_hwfn * p_hwfn,u8 port_id,u8 pf_id,u16 pf_wfq,u8 max_phys_tcs_per_port,u16 num_tx_pqs,struct init_qm_pq_params * pq_params)47714b24e2bSVaishali Kulkarni static int ecore_pf_wfq_rt_init(struct ecore_hwfn *p_hwfn,
47814b24e2bSVaishali Kulkarni u8 port_id,
47914b24e2bSVaishali Kulkarni u8 pf_id,
48014b24e2bSVaishali Kulkarni u16 pf_wfq,
48114b24e2bSVaishali Kulkarni u8 max_phys_tcs_per_port,
48214b24e2bSVaishali Kulkarni u16 num_tx_pqs,
48314b24e2bSVaishali Kulkarni struct init_qm_pq_params *pq_params)
48414b24e2bSVaishali Kulkarni {
48514b24e2bSVaishali Kulkarni u32 inc_val, crd_reg_offset;
48614b24e2bSVaishali Kulkarni u8 voq;
48714b24e2bSVaishali Kulkarni u16 i;
48814b24e2bSVaishali Kulkarni
48914b24e2bSVaishali Kulkarni crd_reg_offset = (pf_id < MAX_NUM_PFS_BB ? QM_REG_WFQPFCRD_RT_OFFSET : QM_REG_WFQPFCRD_MSB_RT_OFFSET) + (pf_id % MAX_NUM_PFS_BB);
49014b24e2bSVaishali Kulkarni
49114b24e2bSVaishali Kulkarni inc_val = QM_WFQ_INC_VAL(pf_wfq);
49214b24e2bSVaishali Kulkarni if (!inc_val || inc_val > QM_WFQ_MAX_INC_VAL) {
49314b24e2bSVaishali Kulkarni DP_NOTICE(p_hwfn, true, "Invalid PF WFQ weight configuration\n");
49414b24e2bSVaishali Kulkarni return -1;
49514b24e2bSVaishali Kulkarni }
49614b24e2bSVaishali Kulkarni
49714b24e2bSVaishali Kulkarni for(i = 0; i < num_tx_pqs; i++) {
49814b24e2bSVaishali Kulkarni voq = VOQ(port_id, pq_params[i].tc_id, max_phys_tcs_per_port);
49914b24e2bSVaishali Kulkarni OVERWRITE_RT_REG(p_hwfn, crd_reg_offset + voq * MAX_NUM_PFS_BB, (u32)QM_WFQ_CRD_REG_SIGN_BIT);
50014b24e2bSVaishali Kulkarni }
50114b24e2bSVaishali Kulkarni
50214b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_WFQPFUPPERBOUND_RT_OFFSET + pf_id, QM_WFQ_UPPER_BOUND | (u32)QM_WFQ_CRD_REG_SIGN_BIT);
50314b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_WFQPFWEIGHT_RT_OFFSET + pf_id, inc_val);
50414b24e2bSVaishali Kulkarni
50514b24e2bSVaishali Kulkarni return 0;
50614b24e2bSVaishali Kulkarni }
50714b24e2bSVaishali Kulkarni
50814b24e2bSVaishali Kulkarni /* Prepare PF RL runtime init values for the specified PF.
50914b24e2bSVaishali Kulkarni * Return -1 on error.
51014b24e2bSVaishali Kulkarni */
ecore_pf_rl_rt_init(struct ecore_hwfn * p_hwfn,u8 pf_id,u32 pf_rl)51114b24e2bSVaishali Kulkarni static int ecore_pf_rl_rt_init(struct ecore_hwfn *p_hwfn,
51214b24e2bSVaishali Kulkarni u8 pf_id,
51314b24e2bSVaishali Kulkarni u32 pf_rl)
51414b24e2bSVaishali Kulkarni {
51514b24e2bSVaishali Kulkarni u32 inc_val;
51614b24e2bSVaishali Kulkarni
51714b24e2bSVaishali Kulkarni inc_val = QM_RL_INC_VAL(pf_rl);
51814b24e2bSVaishali Kulkarni if (inc_val > QM_RL_MAX_INC_VAL) {
51914b24e2bSVaishali Kulkarni DP_NOTICE(p_hwfn, true, "Invalid PF rate limit configuration\n");
52014b24e2bSVaishali Kulkarni return -1;
52114b24e2bSVaishali Kulkarni }
52214b24e2bSVaishali Kulkarni
52314b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_RLPFCRD_RT_OFFSET + pf_id, (u32)QM_RL_CRD_REG_SIGN_BIT);
52414b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_RLPFUPPERBOUND_RT_OFFSET + pf_id, QM_RL_UPPER_BOUND | (u32)QM_RL_CRD_REG_SIGN_BIT);
52514b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_RLPFINCVAL_RT_OFFSET + pf_id, inc_val);
52614b24e2bSVaishali Kulkarni
52714b24e2bSVaishali Kulkarni return 0;
52814b24e2bSVaishali Kulkarni }
52914b24e2bSVaishali Kulkarni
53014b24e2bSVaishali Kulkarni /* Prepare VPORT WFQ runtime init values for the specified VPORTs.
53114b24e2bSVaishali Kulkarni * Return -1 on error.
53214b24e2bSVaishali Kulkarni */
ecore_vp_wfq_rt_init(struct ecore_hwfn * p_hwfn,u8 num_vports,struct init_qm_vport_params * vport_params)53314b24e2bSVaishali Kulkarni static int ecore_vp_wfq_rt_init(struct ecore_hwfn *p_hwfn,
53414b24e2bSVaishali Kulkarni u8 num_vports,
53514b24e2bSVaishali Kulkarni struct init_qm_vport_params *vport_params)
53614b24e2bSVaishali Kulkarni {
53714b24e2bSVaishali Kulkarni u16 vport_pq_id;
53814b24e2bSVaishali Kulkarni u32 inc_val;
53914b24e2bSVaishali Kulkarni u8 tc, i;
54014b24e2bSVaishali Kulkarni
54114b24e2bSVaishali Kulkarni /* Go over all PF VPORTs */
54214b24e2bSVaishali Kulkarni for (i = 0; i < num_vports; i++) {
54314b24e2bSVaishali Kulkarni if (!vport_params[i].vport_wfq)
54414b24e2bSVaishali Kulkarni continue;
54514b24e2bSVaishali Kulkarni
54614b24e2bSVaishali Kulkarni inc_val = QM_WFQ_INC_VAL(vport_params[i].vport_wfq);
54714b24e2bSVaishali Kulkarni if (inc_val > QM_WFQ_MAX_INC_VAL) {
54814b24e2bSVaishali Kulkarni DP_NOTICE(p_hwfn, true, "Invalid VPORT WFQ weight configuration\n");
54914b24e2bSVaishali Kulkarni return -1;
55014b24e2bSVaishali Kulkarni }
55114b24e2bSVaishali Kulkarni
55214b24e2bSVaishali Kulkarni /* Each VPORT can have several VPORT PQ IDs for various TCs */
55314b24e2bSVaishali Kulkarni for (tc = 0; tc < NUM_OF_TCS; tc++) {
55414b24e2bSVaishali Kulkarni vport_pq_id = vport_params[i].first_tx_pq_id[tc];
55514b24e2bSVaishali Kulkarni if (vport_pq_id != QM_INVALID_PQ_ID) {
55614b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_WFQVPCRD_RT_OFFSET + vport_pq_id, (u32)QM_WFQ_CRD_REG_SIGN_BIT);
55714b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_WFQVPWEIGHT_RT_OFFSET + vport_pq_id, inc_val);
55814b24e2bSVaishali Kulkarni }
55914b24e2bSVaishali Kulkarni }
56014b24e2bSVaishali Kulkarni }
56114b24e2bSVaishali Kulkarni
56214b24e2bSVaishali Kulkarni return 0;
56314b24e2bSVaishali Kulkarni }
56414b24e2bSVaishali Kulkarni
56514b24e2bSVaishali Kulkarni /* Prepare VPORT RL runtime init values for the specified VPORTs.
56614b24e2bSVaishali Kulkarni * Return -1 on error.
56714b24e2bSVaishali Kulkarni */
ecore_vport_rl_rt_init(struct ecore_hwfn * p_hwfn,u8 start_vport,u8 num_vports,struct init_qm_vport_params * vport_params)56814b24e2bSVaishali Kulkarni static int ecore_vport_rl_rt_init(struct ecore_hwfn *p_hwfn,
56914b24e2bSVaishali Kulkarni u8 start_vport,
57014b24e2bSVaishali Kulkarni u8 num_vports,
57114b24e2bSVaishali Kulkarni struct init_qm_vport_params *vport_params)
57214b24e2bSVaishali Kulkarni {
57314b24e2bSVaishali Kulkarni u8 i, vport_id;
57414b24e2bSVaishali Kulkarni u32 inc_val;
57514b24e2bSVaishali Kulkarni
57614b24e2bSVaishali Kulkarni if (start_vport + num_vports >= MAX_QM_GLOBAL_RLS) {
57714b24e2bSVaishali Kulkarni DP_NOTICE(p_hwfn, true, "Invalid VPORT ID for rate limiter configuration\n");
57814b24e2bSVaishali Kulkarni return -1;
57914b24e2bSVaishali Kulkarni }
58014b24e2bSVaishali Kulkarni
58114b24e2bSVaishali Kulkarni /* Go over all PF VPORTs */
58214b24e2bSVaishali Kulkarni for (i = 0, vport_id = start_vport; i < num_vports; i++, vport_id++) {
58314b24e2bSVaishali Kulkarni inc_val = QM_RL_INC_VAL(vport_params[i].vport_rl);
58414b24e2bSVaishali Kulkarni if (inc_val > QM_RL_MAX_INC_VAL) {
58514b24e2bSVaishali Kulkarni DP_NOTICE(p_hwfn, true, "Invalid VPORT rate-limit configuration\n");
58614b24e2bSVaishali Kulkarni return -1;
58714b24e2bSVaishali Kulkarni }
58814b24e2bSVaishali Kulkarni
58914b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_RLGLBLCRD_RT_OFFSET + vport_id, (u32)QM_RL_CRD_REG_SIGN_BIT);
59014b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_RLGLBLUPPERBOUND_RT_OFFSET + vport_id, QM_RL_UPPER_BOUND | (u32)QM_RL_CRD_REG_SIGN_BIT);
59114b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_RLGLBLINCVAL_RT_OFFSET + vport_id, inc_val);
59214b24e2bSVaishali Kulkarni }
59314b24e2bSVaishali Kulkarni
59414b24e2bSVaishali Kulkarni return 0;
59514b24e2bSVaishali Kulkarni }
59614b24e2bSVaishali Kulkarni
ecore_poll_on_qm_cmd_ready(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt)59714b24e2bSVaishali Kulkarni static bool ecore_poll_on_qm_cmd_ready(struct ecore_hwfn *p_hwfn,
59814b24e2bSVaishali Kulkarni struct ecore_ptt *p_ptt)
59914b24e2bSVaishali Kulkarni {
60014b24e2bSVaishali Kulkarni u32 reg_val, i;
60114b24e2bSVaishali Kulkarni
60214b24e2bSVaishali Kulkarni for (i = 0, reg_val = 0; i < QM_STOP_CMD_MAX_POLL_COUNT && !reg_val; i++) {
60314b24e2bSVaishali Kulkarni OSAL_UDELAY(QM_STOP_CMD_POLL_PERIOD_US);
60414b24e2bSVaishali Kulkarni reg_val = ecore_rd(p_hwfn, p_ptt, QM_REG_SDMCMDREADY);
60514b24e2bSVaishali Kulkarni }
60614b24e2bSVaishali Kulkarni
60714b24e2bSVaishali Kulkarni /* Check if timeout while waiting for SDM command ready */
60814b24e2bSVaishali Kulkarni if (i == QM_STOP_CMD_MAX_POLL_COUNT) {
60914b24e2bSVaishali Kulkarni DP_VERBOSE(p_hwfn, ECORE_MSG_DEBUG, "Timeout when waiting for QM SDM command ready signal\n");
61014b24e2bSVaishali Kulkarni return false;
61114b24e2bSVaishali Kulkarni }
61214b24e2bSVaishali Kulkarni
61314b24e2bSVaishali Kulkarni return true;
61414b24e2bSVaishali Kulkarni }
61514b24e2bSVaishali Kulkarni
ecore_send_qm_cmd(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u32 cmd_addr,u32 cmd_data_lsb,u32 cmd_data_msb)61614b24e2bSVaishali Kulkarni static bool ecore_send_qm_cmd(struct ecore_hwfn *p_hwfn,
61714b24e2bSVaishali Kulkarni struct ecore_ptt *p_ptt,
61814b24e2bSVaishali Kulkarni u32 cmd_addr,
61914b24e2bSVaishali Kulkarni u32 cmd_data_lsb,
62014b24e2bSVaishali Kulkarni u32 cmd_data_msb)
62114b24e2bSVaishali Kulkarni {
62214b24e2bSVaishali Kulkarni if (!ecore_poll_on_qm_cmd_ready(p_hwfn, p_ptt))
62314b24e2bSVaishali Kulkarni return false;
62414b24e2bSVaishali Kulkarni
62514b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, QM_REG_SDMCMDADDR, cmd_addr);
62614b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, QM_REG_SDMCMDDATALSB, cmd_data_lsb);
62714b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, QM_REG_SDMCMDDATAMSB, cmd_data_msb);
62814b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, QM_REG_SDMCMDGO, 1);
62914b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, QM_REG_SDMCMDGO, 0);
63014b24e2bSVaishali Kulkarni
63114b24e2bSVaishali Kulkarni return ecore_poll_on_qm_cmd_ready(p_hwfn, p_ptt);
63214b24e2bSVaishali Kulkarni }
63314b24e2bSVaishali Kulkarni
63414b24e2bSVaishali Kulkarni
63514b24e2bSVaishali Kulkarni /******************** INTERFACE IMPLEMENTATION *********************/
63614b24e2bSVaishali Kulkarni
ecore_qm_pf_mem_size(u8 pf_id,u32 num_pf_cids,u32 num_vf_cids,u32 num_tids,u16 num_pf_pqs,u16 num_vf_pqs)63714b24e2bSVaishali Kulkarni u32 ecore_qm_pf_mem_size(u8 pf_id,
63814b24e2bSVaishali Kulkarni u32 num_pf_cids,
63914b24e2bSVaishali Kulkarni u32 num_vf_cids,
64014b24e2bSVaishali Kulkarni u32 num_tids,
64114b24e2bSVaishali Kulkarni u16 num_pf_pqs,
64214b24e2bSVaishali Kulkarni u16 num_vf_pqs)
64314b24e2bSVaishali Kulkarni {
64414b24e2bSVaishali Kulkarni return QM_PQ_MEM_4KB(num_pf_cids) * num_pf_pqs +
64514b24e2bSVaishali Kulkarni QM_PQ_MEM_4KB(num_vf_cids) * num_vf_pqs +
64614b24e2bSVaishali Kulkarni QM_PQ_MEM_4KB(num_pf_cids + num_tids) * QM_OTHER_PQS_PER_PF;
64714b24e2bSVaishali Kulkarni }
64814b24e2bSVaishali Kulkarni
ecore_qm_common_rt_init(struct ecore_hwfn * p_hwfn,u8 max_ports_per_engine,u8 max_phys_tcs_per_port,bool pf_rl_en,bool pf_wfq_en,bool vport_rl_en,bool vport_wfq_en,struct init_qm_port_params port_params[MAX_NUM_PORTS])64914b24e2bSVaishali Kulkarni int ecore_qm_common_rt_init(struct ecore_hwfn *p_hwfn,
65014b24e2bSVaishali Kulkarni u8 max_ports_per_engine,
65114b24e2bSVaishali Kulkarni u8 max_phys_tcs_per_port,
65214b24e2bSVaishali Kulkarni bool pf_rl_en,
65314b24e2bSVaishali Kulkarni bool pf_wfq_en,
65414b24e2bSVaishali Kulkarni bool vport_rl_en,
65514b24e2bSVaishali Kulkarni bool vport_wfq_en,
65614b24e2bSVaishali Kulkarni struct init_qm_port_params port_params[MAX_NUM_PORTS])
65714b24e2bSVaishali Kulkarni {
65814b24e2bSVaishali Kulkarni u32 mask;
65914b24e2bSVaishali Kulkarni
66014b24e2bSVaishali Kulkarni /* Init AFullOprtnstcCrdMask */
66114b24e2bSVaishali Kulkarni mask = (QM_OPPOR_LINE_VOQ_DEF << QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT) |
66214b24e2bSVaishali Kulkarni (QM_BYTE_CRD_EN << QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT) |
66314b24e2bSVaishali Kulkarni (pf_wfq_en << QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT) |
66414b24e2bSVaishali Kulkarni (vport_wfq_en << QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT) |
66514b24e2bSVaishali Kulkarni (pf_rl_en << QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT) |
66614b24e2bSVaishali Kulkarni (vport_rl_en << QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT) |
66714b24e2bSVaishali Kulkarni (QM_OPPOR_FW_STOP_DEF << QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT) |
66814b24e2bSVaishali Kulkarni (QM_OPPOR_PQ_EMPTY_DEF << QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT);
66914b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET, mask);
67014b24e2bSVaishali Kulkarni
67114b24e2bSVaishali Kulkarni /* Enable/disable PF RL */
67214b24e2bSVaishali Kulkarni ecore_enable_pf_rl(p_hwfn, pf_rl_en);
67314b24e2bSVaishali Kulkarni
67414b24e2bSVaishali Kulkarni /* Enable/disable PF WFQ */
67514b24e2bSVaishali Kulkarni ecore_enable_pf_wfq(p_hwfn, pf_wfq_en);
67614b24e2bSVaishali Kulkarni
67714b24e2bSVaishali Kulkarni /* Enable/disable VPORT RL */
67814b24e2bSVaishali Kulkarni ecore_enable_vport_rl(p_hwfn, vport_rl_en);
67914b24e2bSVaishali Kulkarni
68014b24e2bSVaishali Kulkarni /* Enable/disable VPORT WFQ */
68114b24e2bSVaishali Kulkarni ecore_enable_vport_wfq(p_hwfn, vport_wfq_en);
68214b24e2bSVaishali Kulkarni
68314b24e2bSVaishali Kulkarni /* Init PBF CMDQ line credit */
68414b24e2bSVaishali Kulkarni ecore_cmdq_lines_rt_init(p_hwfn, max_ports_per_engine, max_phys_tcs_per_port, port_params);
68514b24e2bSVaishali Kulkarni
68614b24e2bSVaishali Kulkarni /* Init BTB blocks in PBF */
68714b24e2bSVaishali Kulkarni ecore_btb_blocks_rt_init(p_hwfn, max_ports_per_engine, max_phys_tcs_per_port, port_params);
68814b24e2bSVaishali Kulkarni
68914b24e2bSVaishali Kulkarni return 0;
69014b24e2bSVaishali Kulkarni }
69114b24e2bSVaishali Kulkarni
ecore_qm_pf_rt_init(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u8 port_id,u8 pf_id,u8 max_phys_tcs_per_port,bool is_first_pf,u32 num_pf_cids,u32 num_vf_cids,u32 num_tids,u16 start_pq,u16 num_pf_pqs,u16 num_vf_pqs,u8 start_vport,u8 num_vports,u16 pf_wfq,u32 pf_rl,struct init_qm_pq_params * pq_params,struct init_qm_vport_params * vport_params)69214b24e2bSVaishali Kulkarni int ecore_qm_pf_rt_init(struct ecore_hwfn *p_hwfn,
69314b24e2bSVaishali Kulkarni struct ecore_ptt *p_ptt,
69414b24e2bSVaishali Kulkarni u8 port_id,
69514b24e2bSVaishali Kulkarni u8 pf_id,
69614b24e2bSVaishali Kulkarni u8 max_phys_tcs_per_port,
69714b24e2bSVaishali Kulkarni bool is_first_pf,
69814b24e2bSVaishali Kulkarni u32 num_pf_cids,
69914b24e2bSVaishali Kulkarni u32 num_vf_cids,
70014b24e2bSVaishali Kulkarni u32 num_tids,
70114b24e2bSVaishali Kulkarni u16 start_pq,
70214b24e2bSVaishali Kulkarni u16 num_pf_pqs,
70314b24e2bSVaishali Kulkarni u16 num_vf_pqs,
70414b24e2bSVaishali Kulkarni u8 start_vport,
70514b24e2bSVaishali Kulkarni u8 num_vports,
70614b24e2bSVaishali Kulkarni u16 pf_wfq,
70714b24e2bSVaishali Kulkarni u32 pf_rl,
70814b24e2bSVaishali Kulkarni struct init_qm_pq_params *pq_params,
70914b24e2bSVaishali Kulkarni struct init_qm_vport_params *vport_params)
71014b24e2bSVaishali Kulkarni {
71114b24e2bSVaishali Kulkarni u32 other_mem_size_4kb;
71214b24e2bSVaishali Kulkarni u8 tc, i;
71314b24e2bSVaishali Kulkarni
71414b24e2bSVaishali Kulkarni other_mem_size_4kb = QM_PQ_MEM_4KB(num_pf_cids + num_tids) * QM_OTHER_PQS_PER_PF;
71514b24e2bSVaishali Kulkarni
71614b24e2bSVaishali Kulkarni /* Clear first Tx PQ ID array for each VPORT */
71714b24e2bSVaishali Kulkarni for(i = 0; i < num_vports; i++)
71814b24e2bSVaishali Kulkarni for(tc = 0; tc < NUM_OF_TCS; tc++)
71914b24e2bSVaishali Kulkarni vport_params[i].first_tx_pq_id[tc] = QM_INVALID_PQ_ID;
72014b24e2bSVaishali Kulkarni
72114b24e2bSVaishali Kulkarni /* Map Other PQs (if any) */
72214b24e2bSVaishali Kulkarni #if QM_OTHER_PQS_PER_PF > 0
72314b24e2bSVaishali Kulkarni ecore_other_pq_map_rt_init(p_hwfn, port_id, pf_id, num_pf_cids, num_tids, 0);
72414b24e2bSVaishali Kulkarni #endif
72514b24e2bSVaishali Kulkarni
72614b24e2bSVaishali Kulkarni /* Map Tx PQs */
72714b24e2bSVaishali Kulkarni ecore_tx_pq_map_rt_init(p_hwfn, p_ptt, port_id, pf_id, max_phys_tcs_per_port, is_first_pf, num_pf_cids, num_vf_cids,
72814b24e2bSVaishali Kulkarni start_pq, num_pf_pqs, num_vf_pqs, start_vport, other_mem_size_4kb, pq_params, vport_params);
72914b24e2bSVaishali Kulkarni
73014b24e2bSVaishali Kulkarni /* Init PF WFQ */
73114b24e2bSVaishali Kulkarni if (pf_wfq)
73214b24e2bSVaishali Kulkarni if (ecore_pf_wfq_rt_init(p_hwfn, port_id, pf_id, pf_wfq, max_phys_tcs_per_port, num_pf_pqs + num_vf_pqs, pq_params))
73314b24e2bSVaishali Kulkarni return -1;
73414b24e2bSVaishali Kulkarni
73514b24e2bSVaishali Kulkarni /* Init PF RL */
73614b24e2bSVaishali Kulkarni if (ecore_pf_rl_rt_init(p_hwfn, pf_id, pf_rl))
73714b24e2bSVaishali Kulkarni return -1;
73814b24e2bSVaishali Kulkarni
73914b24e2bSVaishali Kulkarni /* Set VPORT WFQ */
74014b24e2bSVaishali Kulkarni if (ecore_vp_wfq_rt_init(p_hwfn, num_vports, vport_params))
74114b24e2bSVaishali Kulkarni return -1;
74214b24e2bSVaishali Kulkarni
74314b24e2bSVaishali Kulkarni /* Set VPORT RL */
74414b24e2bSVaishali Kulkarni if (ecore_vport_rl_rt_init(p_hwfn, start_vport, num_vports, vport_params))
74514b24e2bSVaishali Kulkarni return -1;
74614b24e2bSVaishali Kulkarni
74714b24e2bSVaishali Kulkarni return 0;
74814b24e2bSVaishali Kulkarni }
74914b24e2bSVaishali Kulkarni
ecore_init_pf_wfq(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u8 pf_id,u16 pf_wfq)75014b24e2bSVaishali Kulkarni int ecore_init_pf_wfq(struct ecore_hwfn *p_hwfn,
75114b24e2bSVaishali Kulkarni struct ecore_ptt *p_ptt,
75214b24e2bSVaishali Kulkarni u8 pf_id,
75314b24e2bSVaishali Kulkarni u16 pf_wfq)
75414b24e2bSVaishali Kulkarni {
75514b24e2bSVaishali Kulkarni u32 inc_val;
75614b24e2bSVaishali Kulkarni
75714b24e2bSVaishali Kulkarni inc_val = QM_WFQ_INC_VAL(pf_wfq);
75814b24e2bSVaishali Kulkarni if (!inc_val || inc_val > QM_WFQ_MAX_INC_VAL) {
75914b24e2bSVaishali Kulkarni DP_NOTICE(p_hwfn, true, "Invalid PF WFQ weight configuration\n");
76014b24e2bSVaishali Kulkarni return -1;
76114b24e2bSVaishali Kulkarni }
76214b24e2bSVaishali Kulkarni
76314b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, QM_REG_WFQPFWEIGHT + pf_id * 4, inc_val);
76414b24e2bSVaishali Kulkarni
76514b24e2bSVaishali Kulkarni return 0;
76614b24e2bSVaishali Kulkarni }
76714b24e2bSVaishali Kulkarni
ecore_init_pf_rl(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u8 pf_id,u32 pf_rl)76814b24e2bSVaishali Kulkarni int ecore_init_pf_rl(struct ecore_hwfn *p_hwfn,
76914b24e2bSVaishali Kulkarni struct ecore_ptt *p_ptt,
77014b24e2bSVaishali Kulkarni u8 pf_id,
77114b24e2bSVaishali Kulkarni u32 pf_rl)
77214b24e2bSVaishali Kulkarni {
77314b24e2bSVaishali Kulkarni u32 inc_val;
77414b24e2bSVaishali Kulkarni
77514b24e2bSVaishali Kulkarni inc_val = QM_RL_INC_VAL(pf_rl);
77614b24e2bSVaishali Kulkarni if (inc_val > QM_RL_MAX_INC_VAL) {
77714b24e2bSVaishali Kulkarni DP_NOTICE(p_hwfn, true, "Invalid PF rate limit configuration\n");
77814b24e2bSVaishali Kulkarni return -1;
77914b24e2bSVaishali Kulkarni }
78014b24e2bSVaishali Kulkarni
78114b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, QM_REG_RLPFCRD + pf_id * 4, (u32)QM_RL_CRD_REG_SIGN_BIT);
78214b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, QM_REG_RLPFINCVAL + pf_id * 4, inc_val);
78314b24e2bSVaishali Kulkarni
78414b24e2bSVaishali Kulkarni return 0;
78514b24e2bSVaishali Kulkarni }
78614b24e2bSVaishali Kulkarni
ecore_init_vport_wfq(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u16 first_tx_pq_id[NUM_OF_TCS],u16 vport_wfq)78714b24e2bSVaishali Kulkarni int ecore_init_vport_wfq(struct ecore_hwfn *p_hwfn,
78814b24e2bSVaishali Kulkarni struct ecore_ptt *p_ptt,
78914b24e2bSVaishali Kulkarni u16 first_tx_pq_id[NUM_OF_TCS],
79014b24e2bSVaishali Kulkarni u16 vport_wfq)
79114b24e2bSVaishali Kulkarni {
79214b24e2bSVaishali Kulkarni u16 vport_pq_id;
79314b24e2bSVaishali Kulkarni u32 inc_val;
79414b24e2bSVaishali Kulkarni u8 tc;
79514b24e2bSVaishali Kulkarni
79614b24e2bSVaishali Kulkarni inc_val = QM_WFQ_INC_VAL(vport_wfq);
79714b24e2bSVaishali Kulkarni if (!inc_val || inc_val > QM_WFQ_MAX_INC_VAL) {
79814b24e2bSVaishali Kulkarni DP_NOTICE(p_hwfn, true, "Invalid VPORT WFQ weight configuration\n");
79914b24e2bSVaishali Kulkarni return -1;
80014b24e2bSVaishali Kulkarni }
80114b24e2bSVaishali Kulkarni
80214b24e2bSVaishali Kulkarni for (tc = 0; tc < NUM_OF_TCS; tc++) {
80314b24e2bSVaishali Kulkarni vport_pq_id = first_tx_pq_id[tc];
80414b24e2bSVaishali Kulkarni if (vport_pq_id != QM_INVALID_PQ_ID) {
80514b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, QM_REG_WFQVPWEIGHT + vport_pq_id * 4, inc_val);
80614b24e2bSVaishali Kulkarni }
80714b24e2bSVaishali Kulkarni }
80814b24e2bSVaishali Kulkarni
80914b24e2bSVaishali Kulkarni return 0;
81014b24e2bSVaishali Kulkarni }
81114b24e2bSVaishali Kulkarni
ecore_init_vport_rl(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u8 vport_id,u32 vport_rl)81214b24e2bSVaishali Kulkarni int ecore_init_vport_rl(struct ecore_hwfn *p_hwfn,
81314b24e2bSVaishali Kulkarni struct ecore_ptt *p_ptt,
81414b24e2bSVaishali Kulkarni u8 vport_id,
81514b24e2bSVaishali Kulkarni u32 vport_rl)
81614b24e2bSVaishali Kulkarni {
81714b24e2bSVaishali Kulkarni u32 inc_val, max_qm_global_rls = MAX_QM_GLOBAL_RLS;
81814b24e2bSVaishali Kulkarni
81914b24e2bSVaishali Kulkarni if (vport_id >= max_qm_global_rls) {
82014b24e2bSVaishali Kulkarni DP_NOTICE(p_hwfn, true, "Invalid VPORT ID for rate limiter configuration\n");
82114b24e2bSVaishali Kulkarni return -1;
82214b24e2bSVaishali Kulkarni }
82314b24e2bSVaishali Kulkarni
82414b24e2bSVaishali Kulkarni inc_val = QM_RL_INC_VAL(vport_rl);
82514b24e2bSVaishali Kulkarni if (inc_val > QM_RL_MAX_INC_VAL) {
82614b24e2bSVaishali Kulkarni DP_NOTICE(p_hwfn, true, "Invalid VPORT rate-limit configuration\n");
82714b24e2bSVaishali Kulkarni return -1;
82814b24e2bSVaishali Kulkarni }
82914b24e2bSVaishali Kulkarni
83014b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, QM_REG_RLGLBLCRD + vport_id * 4, (u32)QM_RL_CRD_REG_SIGN_BIT);
83114b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, QM_REG_RLGLBLINCVAL + vport_id * 4, inc_val);
83214b24e2bSVaishali Kulkarni
83314b24e2bSVaishali Kulkarni return 0;
83414b24e2bSVaishali Kulkarni }
83514b24e2bSVaishali Kulkarni
ecore_send_qm_stop_cmd(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,bool is_release_cmd,bool is_tx_pq,u16 start_pq,u16 num_pqs)83614b24e2bSVaishali Kulkarni bool ecore_send_qm_stop_cmd(struct ecore_hwfn *p_hwfn,
83714b24e2bSVaishali Kulkarni struct ecore_ptt *p_ptt,
83814b24e2bSVaishali Kulkarni bool is_release_cmd,
83914b24e2bSVaishali Kulkarni bool is_tx_pq,
84014b24e2bSVaishali Kulkarni u16 start_pq,
84114b24e2bSVaishali Kulkarni u16 num_pqs)
84214b24e2bSVaishali Kulkarni {
84314b24e2bSVaishali Kulkarni u32 cmd_arr[QM_CMD_STRUCT_SIZE(QM_STOP_CMD)] = {0};
84414b24e2bSVaishali Kulkarni u32 pq_mask = 0, last_pq, pq_id;
84514b24e2bSVaishali Kulkarni
84614b24e2bSVaishali Kulkarni last_pq = start_pq + num_pqs - 1;
84714b24e2bSVaishali Kulkarni
84814b24e2bSVaishali Kulkarni /* Set command's PQ type */
84914b24e2bSVaishali Kulkarni QM_CMD_SET_FIELD(cmd_arr, QM_STOP_CMD, PQ_TYPE, is_tx_pq ? 0 : 1);
85014b24e2bSVaishali Kulkarni
85114b24e2bSVaishali Kulkarni /* Go over requested PQs */
85214b24e2bSVaishali Kulkarni for (pq_id = start_pq; pq_id <= last_pq; pq_id++) {
85314b24e2bSVaishali Kulkarni
85414b24e2bSVaishali Kulkarni /* Set PQ bit in mask (stop command only) */
85514b24e2bSVaishali Kulkarni if (!is_release_cmd)
85614b24e2bSVaishali Kulkarni pq_mask |= (1 << (pq_id % QM_STOP_PQ_MASK_WIDTH));
85714b24e2bSVaishali Kulkarni
85814b24e2bSVaishali Kulkarni /* If last PQ or end of PQ mask, write command */
85914b24e2bSVaishali Kulkarni if ((pq_id == last_pq) || (pq_id % QM_STOP_PQ_MASK_WIDTH == (QM_STOP_PQ_MASK_WIDTH - 1))) {
86014b24e2bSVaishali Kulkarni QM_CMD_SET_FIELD(cmd_arr, QM_STOP_CMD, PAUSE_MASK, pq_mask);
86114b24e2bSVaishali Kulkarni QM_CMD_SET_FIELD(cmd_arr, QM_STOP_CMD, GROUP_ID, pq_id / QM_STOP_PQ_MASK_WIDTH);
86214b24e2bSVaishali Kulkarni if (!ecore_send_qm_cmd(p_hwfn, p_ptt, QM_STOP_CMD_ADDR, cmd_arr[0], cmd_arr[1]))
86314b24e2bSVaishali Kulkarni return false;
86414b24e2bSVaishali Kulkarni pq_mask = 0;
86514b24e2bSVaishali Kulkarni }
86614b24e2bSVaishali Kulkarni }
86714b24e2bSVaishali Kulkarni
86814b24e2bSVaishali Kulkarni return true;
86914b24e2bSVaishali Kulkarni }
87014b24e2bSVaishali Kulkarni
87114b24e2bSVaishali Kulkarni #ifndef UNUSED_HSI_FUNC
87214b24e2bSVaishali Kulkarni
87314b24e2bSVaishali Kulkarni /* NIG: ETS configuration constants */
87414b24e2bSVaishali Kulkarni #define NIG_TX_ETS_CLIENT_OFFSET 4
87514b24e2bSVaishali Kulkarni #define NIG_LB_ETS_CLIENT_OFFSET 1
87614b24e2bSVaishali Kulkarni #define NIG_ETS_MIN_WFQ_BYTES 1600
87714b24e2bSVaishali Kulkarni
87814b24e2bSVaishali Kulkarni /* NIG: ETS constants */
87914b24e2bSVaishali Kulkarni #define NIG_ETS_UP_BOUND(weight,mtu) (2 * ((weight) > (mtu) ? (weight) : (mtu)))
88014b24e2bSVaishali Kulkarni
88114b24e2bSVaishali Kulkarni /* NIG: RL constants */
88214b24e2bSVaishali Kulkarni
88314b24e2bSVaishali Kulkarni /* Byte base type value */
88414b24e2bSVaishali Kulkarni #define NIG_RL_BASE_TYPE 1
88514b24e2bSVaishali Kulkarni
88614b24e2bSVaishali Kulkarni /* Period in us */
88714b24e2bSVaishali Kulkarni #define NIG_RL_PERIOD 1
88814b24e2bSVaishali Kulkarni
88914b24e2bSVaishali Kulkarni /* Period in 25MHz cycles */
89014b24e2bSVaishali Kulkarni #define NIG_RL_PERIOD_CLK_25M (25 * NIG_RL_PERIOD)
89114b24e2bSVaishali Kulkarni
89214b24e2bSVaishali Kulkarni /* Rate in mbps */
89314b24e2bSVaishali Kulkarni #define NIG_RL_INC_VAL(rate) (((rate) * NIG_RL_PERIOD) / 8)
89414b24e2bSVaishali Kulkarni
89514b24e2bSVaishali Kulkarni #define NIG_RL_MAX_VAL(inc_val,mtu) (2 * ((inc_val) > (mtu) ? (inc_val) : (mtu)))
89614b24e2bSVaishali Kulkarni
89714b24e2bSVaishali Kulkarni /* NIG: packet prioritry configuration constants */
89814b24e2bSVaishali Kulkarni #define NIG_PRIORITY_MAP_TC_BITS 4
89914b24e2bSVaishali Kulkarni
90014b24e2bSVaishali Kulkarni
ecore_init_nig_ets(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,struct init_ets_req * req,bool is_lb)90114b24e2bSVaishali Kulkarni void ecore_init_nig_ets(struct ecore_hwfn *p_hwfn,
90214b24e2bSVaishali Kulkarni struct ecore_ptt *p_ptt,
90314b24e2bSVaishali Kulkarni struct init_ets_req* req,
90414b24e2bSVaishali Kulkarni bool is_lb)
90514b24e2bSVaishali Kulkarni {
90614b24e2bSVaishali Kulkarni u32 min_weight, tc_weight_base_addr, tc_weight_addr_diff;
90714b24e2bSVaishali Kulkarni u32 tc_bound_base_addr, tc_bound_addr_diff;
90814b24e2bSVaishali Kulkarni u8 sp_tc_map = 0, wfq_tc_map = 0;
90914b24e2bSVaishali Kulkarni u8 tc, num_tc, tc_client_offset;
91014b24e2bSVaishali Kulkarni
91114b24e2bSVaishali Kulkarni num_tc = is_lb ? NUM_OF_TCS : NUM_OF_PHYS_TCS;
91214b24e2bSVaishali Kulkarni tc_client_offset = is_lb ? NIG_LB_ETS_CLIENT_OFFSET : NIG_TX_ETS_CLIENT_OFFSET;
91314b24e2bSVaishali Kulkarni min_weight = 0xffffffff;
91414b24e2bSVaishali Kulkarni tc_weight_base_addr = is_lb ? NIG_REG_LB_ARB_CREDIT_WEIGHT_0 : NIG_REG_TX_ARB_CREDIT_WEIGHT_0;
91514b24e2bSVaishali Kulkarni tc_weight_addr_diff = is_lb ? NIG_REG_LB_ARB_CREDIT_WEIGHT_1 - NIG_REG_LB_ARB_CREDIT_WEIGHT_0 :
91614b24e2bSVaishali Kulkarni NIG_REG_TX_ARB_CREDIT_WEIGHT_1 - NIG_REG_TX_ARB_CREDIT_WEIGHT_0;
91714b24e2bSVaishali Kulkarni tc_bound_base_addr = is_lb ? NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_0 : NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_0;
91814b24e2bSVaishali Kulkarni tc_bound_addr_diff = is_lb ? NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_1 - NIG_REG_LB_ARB_CREDIT_UPPER_BOUND_0 :
91914b24e2bSVaishali Kulkarni NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_1 - NIG_REG_TX_ARB_CREDIT_UPPER_BOUND_0;
92014b24e2bSVaishali Kulkarni
92114b24e2bSVaishali Kulkarni for (tc = 0; tc < num_tc; tc++) {
92214b24e2bSVaishali Kulkarni struct init_ets_tc_req *tc_req = &req->tc_req[tc];
92314b24e2bSVaishali Kulkarni
92414b24e2bSVaishali Kulkarni /* Update SP map */
92514b24e2bSVaishali Kulkarni if (tc_req->use_sp)
92614b24e2bSVaishali Kulkarni sp_tc_map |= (1 << tc);
92714b24e2bSVaishali Kulkarni
92814b24e2bSVaishali Kulkarni if (!tc_req->use_wfq)
92914b24e2bSVaishali Kulkarni continue;
93014b24e2bSVaishali Kulkarni
93114b24e2bSVaishali Kulkarni /* Update WFQ map */
93214b24e2bSVaishali Kulkarni wfq_tc_map |= (1 << tc);
93314b24e2bSVaishali Kulkarni
93414b24e2bSVaishali Kulkarni /* Find minimal weight */
93514b24e2bSVaishali Kulkarni if (tc_req->weight < min_weight)
93614b24e2bSVaishali Kulkarni min_weight = tc_req->weight;
93714b24e2bSVaishali Kulkarni }
93814b24e2bSVaishali Kulkarni
93914b24e2bSVaishali Kulkarni /* Write SP map */
94014b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, is_lb ? NIG_REG_LB_ARB_CLIENT_IS_STRICT : NIG_REG_TX_ARB_CLIENT_IS_STRICT, (sp_tc_map << tc_client_offset));
94114b24e2bSVaishali Kulkarni
94214b24e2bSVaishali Kulkarni /* Write WFQ map */
94314b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, is_lb ? NIG_REG_LB_ARB_CLIENT_IS_SUBJECT2WFQ : NIG_REG_TX_ARB_CLIENT_IS_SUBJECT2WFQ, (wfq_tc_map << tc_client_offset));
94414b24e2bSVaishali Kulkarni
94514b24e2bSVaishali Kulkarni /* Write WFQ weights */
94614b24e2bSVaishali Kulkarni for (tc = 0; tc < num_tc; tc++, tc_client_offset++) {
94714b24e2bSVaishali Kulkarni struct init_ets_tc_req *tc_req = &req->tc_req[tc];
94814b24e2bSVaishali Kulkarni u32 byte_weight;
94914b24e2bSVaishali Kulkarni
95014b24e2bSVaishali Kulkarni if (!tc_req->use_wfq)
95114b24e2bSVaishali Kulkarni continue;
95214b24e2bSVaishali Kulkarni
95314b24e2bSVaishali Kulkarni /* Translate weight to bytes */
95414b24e2bSVaishali Kulkarni byte_weight = (NIG_ETS_MIN_WFQ_BYTES * tc_req->weight) / min_weight;
95514b24e2bSVaishali Kulkarni
95614b24e2bSVaishali Kulkarni /* Write WFQ weight */
95714b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, tc_weight_base_addr + tc_weight_addr_diff * tc_client_offset, byte_weight);
95814b24e2bSVaishali Kulkarni
95914b24e2bSVaishali Kulkarni /* Write WFQ upper bound */
96014b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, tc_bound_base_addr + tc_bound_addr_diff * tc_client_offset, NIG_ETS_UP_BOUND(byte_weight, req->mtu));
96114b24e2bSVaishali Kulkarni }
96214b24e2bSVaishali Kulkarni }
96314b24e2bSVaishali Kulkarni
ecore_init_nig_lb_rl(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,struct init_nig_lb_rl_req * req)96414b24e2bSVaishali Kulkarni void ecore_init_nig_lb_rl(struct ecore_hwfn *p_hwfn,
96514b24e2bSVaishali Kulkarni struct ecore_ptt *p_ptt,
96614b24e2bSVaishali Kulkarni struct init_nig_lb_rl_req* req)
96714b24e2bSVaishali Kulkarni {
96814b24e2bSVaishali Kulkarni u32 ctrl, inc_val, reg_offset;
96914b24e2bSVaishali Kulkarni u8 tc;
97014b24e2bSVaishali Kulkarni
97114b24e2bSVaishali Kulkarni /* Disable global MAC+LB RL */
97214b24e2bSVaishali Kulkarni ctrl = NIG_RL_BASE_TYPE << NIG_REG_TX_LB_GLBRATELIMIT_CTRL_TX_LB_GLBRATELIMIT_BASE_TYPE_SHIFT;
97314b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, NIG_REG_TX_LB_GLBRATELIMIT_CTRL, ctrl);
97414b24e2bSVaishali Kulkarni
97514b24e2bSVaishali Kulkarni /* Configure and enable global MAC+LB RL */
97614b24e2bSVaishali Kulkarni if (req->lb_mac_rate) {
97714b24e2bSVaishali Kulkarni
97814b24e2bSVaishali Kulkarni /* Configure */
97914b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, NIG_REG_TX_LB_GLBRATELIMIT_INC_PERIOD, NIG_RL_PERIOD_CLK_25M);
98014b24e2bSVaishali Kulkarni inc_val = NIG_RL_INC_VAL(req->lb_mac_rate);
98114b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, NIG_REG_TX_LB_GLBRATELIMIT_INC_VALUE, inc_val);
98214b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, NIG_REG_TX_LB_GLBRATELIMIT_MAX_VALUE, NIG_RL_MAX_VAL(inc_val, req->mtu));
98314b24e2bSVaishali Kulkarni
98414b24e2bSVaishali Kulkarni /* Enable */
98514b24e2bSVaishali Kulkarni ctrl |= 1 << NIG_REG_TX_LB_GLBRATELIMIT_CTRL_TX_LB_GLBRATELIMIT_EN_SHIFT;
98614b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, NIG_REG_TX_LB_GLBRATELIMIT_CTRL, ctrl);
98714b24e2bSVaishali Kulkarni }
98814b24e2bSVaishali Kulkarni
98914b24e2bSVaishali Kulkarni /* Disable global LB-only RL */
99014b24e2bSVaishali Kulkarni ctrl = NIG_RL_BASE_TYPE << NIG_REG_LB_BRBRATELIMIT_CTRL_LB_BRBRATELIMIT_BASE_TYPE_SHIFT;
99114b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_BRBRATELIMIT_CTRL, ctrl);
99214b24e2bSVaishali Kulkarni
99314b24e2bSVaishali Kulkarni /* Configure and enable global LB-only RL */
99414b24e2bSVaishali Kulkarni if (req->lb_rate) {
99514b24e2bSVaishali Kulkarni
99614b24e2bSVaishali Kulkarni /* Configure */
99714b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_BRBRATELIMIT_INC_PERIOD, NIG_RL_PERIOD_CLK_25M);
99814b24e2bSVaishali Kulkarni inc_val = NIG_RL_INC_VAL(req->lb_rate);
99914b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_BRBRATELIMIT_INC_VALUE, inc_val);
100014b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_BRBRATELIMIT_MAX_VALUE, NIG_RL_MAX_VAL(inc_val, req->mtu));
100114b24e2bSVaishali Kulkarni
100214b24e2bSVaishali Kulkarni /* Enable */
100314b24e2bSVaishali Kulkarni ctrl |= 1 << NIG_REG_LB_BRBRATELIMIT_CTRL_LB_BRBRATELIMIT_EN_SHIFT;
100414b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_BRBRATELIMIT_CTRL, ctrl);
100514b24e2bSVaishali Kulkarni }
100614b24e2bSVaishali Kulkarni
100714b24e2bSVaishali Kulkarni /* Per-TC RLs */
100814b24e2bSVaishali Kulkarni for (tc = 0, reg_offset = 0; tc < NUM_OF_PHYS_TCS; tc++, reg_offset += 4) {
100914b24e2bSVaishali Kulkarni
101014b24e2bSVaishali Kulkarni /* Disable TC RL */
101114b24e2bSVaishali Kulkarni ctrl = NIG_RL_BASE_TYPE << NIG_REG_LB_TCRATELIMIT_CTRL_0_LB_TCRATELIMIT_BASE_TYPE_0_SHIFT;
101214b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_TCRATELIMIT_CTRL_0 + reg_offset, ctrl);
101314b24e2bSVaishali Kulkarni
101414b24e2bSVaishali Kulkarni /* Configure and enable TC RL */
101514b24e2bSVaishali Kulkarni if (!req->tc_rate[tc])
101614b24e2bSVaishali Kulkarni continue;
101714b24e2bSVaishali Kulkarni
101814b24e2bSVaishali Kulkarni /* Configure */
101914b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_TCRATELIMIT_INC_PERIOD_0 + reg_offset, NIG_RL_PERIOD_CLK_25M);
102014b24e2bSVaishali Kulkarni inc_val = NIG_RL_INC_VAL(req->tc_rate[tc]);
102114b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_TCRATELIMIT_INC_VALUE_0 + reg_offset, inc_val);
102214b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_TCRATELIMIT_MAX_VALUE_0 + reg_offset, NIG_RL_MAX_VAL(inc_val, req->mtu));
102314b24e2bSVaishali Kulkarni
102414b24e2bSVaishali Kulkarni /* Enable */
102514b24e2bSVaishali Kulkarni ctrl |= 1 << NIG_REG_LB_TCRATELIMIT_CTRL_0_LB_TCRATELIMIT_EN_0_SHIFT;
102614b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, NIG_REG_LB_TCRATELIMIT_CTRL_0 + reg_offset, ctrl);
102714b24e2bSVaishali Kulkarni }
102814b24e2bSVaishali Kulkarni }
102914b24e2bSVaishali Kulkarni
ecore_init_nig_pri_tc_map(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,struct init_nig_pri_tc_map_req * req)103014b24e2bSVaishali Kulkarni void ecore_init_nig_pri_tc_map(struct ecore_hwfn *p_hwfn,
103114b24e2bSVaishali Kulkarni struct ecore_ptt *p_ptt,
103214b24e2bSVaishali Kulkarni struct init_nig_pri_tc_map_req* req)
103314b24e2bSVaishali Kulkarni {
103414b24e2bSVaishali Kulkarni u8 tc_pri_mask[NUM_OF_PHYS_TCS] = { 0 };
103514b24e2bSVaishali Kulkarni u32 pri_tc_mask = 0;
103614b24e2bSVaishali Kulkarni u8 pri, tc;
103714b24e2bSVaishali Kulkarni
103814b24e2bSVaishali Kulkarni for (pri = 0; pri < NUM_OF_VLAN_PRIORITIES; pri++) {
103914b24e2bSVaishali Kulkarni if (!req->pri[pri].valid)
104014b24e2bSVaishali Kulkarni continue;
104114b24e2bSVaishali Kulkarni
104214b24e2bSVaishali Kulkarni pri_tc_mask |= (req->pri[pri].tc_id << (pri * NIG_PRIORITY_MAP_TC_BITS));
104314b24e2bSVaishali Kulkarni tc_pri_mask[req->pri[pri].tc_id] |= (1 << pri);
104414b24e2bSVaishali Kulkarni }
104514b24e2bSVaishali Kulkarni
104614b24e2bSVaishali Kulkarni /* Write priority -> TC mask */
104714b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, NIG_REG_PKT_PRIORITY_TO_TC, pri_tc_mask);
104814b24e2bSVaishali Kulkarni
104914b24e2bSVaishali Kulkarni /* Write TC -> priority mask */
105014b24e2bSVaishali Kulkarni for (tc = 0; tc < NUM_OF_PHYS_TCS; tc++) {
105114b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, NIG_REG_PRIORITY_FOR_TC_0 + tc * 4, tc_pri_mask[tc]);
105214b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, NIG_REG_RX_TC0_PRIORITY_MASK + tc * 4, tc_pri_mask[tc]);
105314b24e2bSVaishali Kulkarni }
105414b24e2bSVaishali Kulkarni }
105514b24e2bSVaishali Kulkarni
105614b24e2bSVaishali Kulkarni #endif /* UNUSED_HSI_FUNC */
105714b24e2bSVaishali Kulkarni
105814b24e2bSVaishali Kulkarni #ifndef UNUSED_HSI_FUNC
105914b24e2bSVaishali Kulkarni
106014b24e2bSVaishali Kulkarni /* PRS: ETS configuration constants */
106114b24e2bSVaishali Kulkarni #define PRS_ETS_MIN_WFQ_BYTES 1600
106214b24e2bSVaishali Kulkarni #define PRS_ETS_UP_BOUND(weight,mtu) (2 * ((weight) > (mtu) ? (weight) : (mtu)))
106314b24e2bSVaishali Kulkarni
106414b24e2bSVaishali Kulkarni
ecore_init_prs_ets(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,struct init_ets_req * req)106514b24e2bSVaishali Kulkarni void ecore_init_prs_ets(struct ecore_hwfn *p_hwfn,
106614b24e2bSVaishali Kulkarni struct ecore_ptt *p_ptt,
106714b24e2bSVaishali Kulkarni struct init_ets_req* req)
106814b24e2bSVaishali Kulkarni {
106914b24e2bSVaishali Kulkarni u32 tc_weight_addr_diff, tc_bound_addr_diff, min_weight = 0xffffffff;
107014b24e2bSVaishali Kulkarni u8 tc, sp_tc_map = 0, wfq_tc_map = 0;
107114b24e2bSVaishali Kulkarni
107214b24e2bSVaishali Kulkarni tc_weight_addr_diff = PRS_REG_ETS_ARB_CREDIT_WEIGHT_1 - PRS_REG_ETS_ARB_CREDIT_WEIGHT_0;
107314b24e2bSVaishali Kulkarni tc_bound_addr_diff = PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_1 - PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_0;
107414b24e2bSVaishali Kulkarni
107514b24e2bSVaishali Kulkarni for (tc = 0; tc < NUM_OF_TCS; tc++) {
107614b24e2bSVaishali Kulkarni struct init_ets_tc_req *tc_req = &req->tc_req[tc];
107714b24e2bSVaishali Kulkarni
107814b24e2bSVaishali Kulkarni /* Update SP map */
107914b24e2bSVaishali Kulkarni if (tc_req->use_sp)
108014b24e2bSVaishali Kulkarni sp_tc_map |= (1 << tc);
108114b24e2bSVaishali Kulkarni
108214b24e2bSVaishali Kulkarni if (!tc_req->use_wfq)
108314b24e2bSVaishali Kulkarni continue;
108414b24e2bSVaishali Kulkarni
108514b24e2bSVaishali Kulkarni /* Update WFQ map */
108614b24e2bSVaishali Kulkarni wfq_tc_map |= (1 << tc);
108714b24e2bSVaishali Kulkarni
108814b24e2bSVaishali Kulkarni /* Find minimal weight */
108914b24e2bSVaishali Kulkarni if (tc_req->weight < min_weight)
109014b24e2bSVaishali Kulkarni min_weight = tc_req->weight;
109114b24e2bSVaishali Kulkarni }
109214b24e2bSVaishali Kulkarni
109314b24e2bSVaishali Kulkarni /* Write SP map */
109414b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, PRS_REG_ETS_ARB_CLIENT_IS_STRICT, sp_tc_map);
109514b24e2bSVaishali Kulkarni
109614b24e2bSVaishali Kulkarni /* Write WFQ map */
109714b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, PRS_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ, wfq_tc_map);
109814b24e2bSVaishali Kulkarni
109914b24e2bSVaishali Kulkarni /* Write WFQ weights */
110014b24e2bSVaishali Kulkarni for (tc = 0; tc < NUM_OF_TCS; tc++) {
110114b24e2bSVaishali Kulkarni struct init_ets_tc_req *tc_req = &req->tc_req[tc];
110214b24e2bSVaishali Kulkarni u32 byte_weight;
110314b24e2bSVaishali Kulkarni
110414b24e2bSVaishali Kulkarni if (!tc_req->use_wfq)
110514b24e2bSVaishali Kulkarni continue;
110614b24e2bSVaishali Kulkarni
110714b24e2bSVaishali Kulkarni /* Translate weight to bytes */
110814b24e2bSVaishali Kulkarni byte_weight = (PRS_ETS_MIN_WFQ_BYTES * tc_req->weight) / min_weight;
110914b24e2bSVaishali Kulkarni
111014b24e2bSVaishali Kulkarni /* Write WFQ weight */
111114b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, PRS_REG_ETS_ARB_CREDIT_WEIGHT_0 + tc * tc_weight_addr_diff, byte_weight);
111214b24e2bSVaishali Kulkarni
111314b24e2bSVaishali Kulkarni /* Write WFQ upper bound */
111414b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, PRS_REG_ETS_ARB_CREDIT_UPPER_BOUND_0 + tc * tc_bound_addr_diff, PRS_ETS_UP_BOUND(byte_weight, req->mtu));
111514b24e2bSVaishali Kulkarni }
111614b24e2bSVaishali Kulkarni }
111714b24e2bSVaishali Kulkarni
111814b24e2bSVaishali Kulkarni #endif /* UNUSED_HSI_FUNC */
111914b24e2bSVaishali Kulkarni #ifndef UNUSED_HSI_FUNC
112014b24e2bSVaishali Kulkarni
112114b24e2bSVaishali Kulkarni /* BRB: RAM configuration constants */
112214b24e2bSVaishali Kulkarni #define BRB_TOTAL_RAM_BLOCKS_BB 4800
112314b24e2bSVaishali Kulkarni #define BRB_TOTAL_RAM_BLOCKS_K2 5632
112414b24e2bSVaishali Kulkarni #define BRB_BLOCK_SIZE 128
112514b24e2bSVaishali Kulkarni #define BRB_MIN_BLOCKS_PER_TC 9
112614b24e2bSVaishali Kulkarni #define BRB_HYST_BYTES 10240
112714b24e2bSVaishali Kulkarni #define BRB_HYST_BLOCKS (BRB_HYST_BYTES / BRB_BLOCK_SIZE)
112814b24e2bSVaishali Kulkarni
112914b24e2bSVaishali Kulkarni /* Temporary big RAM allocation - should be updated */
ecore_init_brb_ram(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,struct init_brb_ram_req * req)113014b24e2bSVaishali Kulkarni void ecore_init_brb_ram(struct ecore_hwfn *p_hwfn,
113114b24e2bSVaishali Kulkarni struct ecore_ptt *p_ptt,
113214b24e2bSVaishali Kulkarni struct init_brb_ram_req* req)
113314b24e2bSVaishali Kulkarni {
113414b24e2bSVaishali Kulkarni u32 tc_headroom_blocks, min_pkt_size_blocks, total_blocks;
113514b24e2bSVaishali Kulkarni u32 active_port_blocks, reg_offset = 0;
113614b24e2bSVaishali Kulkarni u8 port, active_ports = 0;
113714b24e2bSVaishali Kulkarni
113814b24e2bSVaishali Kulkarni tc_headroom_blocks = (u32)DIV_ROUND_UP(req->headroom_per_tc, BRB_BLOCK_SIZE);
113914b24e2bSVaishali Kulkarni min_pkt_size_blocks = (u32)DIV_ROUND_UP(req->min_pkt_size, BRB_BLOCK_SIZE);
114014b24e2bSVaishali Kulkarni total_blocks = ECORE_IS_K2(p_hwfn->p_dev) ? BRB_TOTAL_RAM_BLOCKS_K2 : BRB_TOTAL_RAM_BLOCKS_BB;
114114b24e2bSVaishali Kulkarni
114214b24e2bSVaishali Kulkarni /* Find number of active ports */
114314b24e2bSVaishali Kulkarni for (port = 0; port < MAX_NUM_PORTS; port++)
114414b24e2bSVaishali Kulkarni if (req->num_active_tcs[port])
114514b24e2bSVaishali Kulkarni active_ports++;
114614b24e2bSVaishali Kulkarni
114714b24e2bSVaishali Kulkarni active_port_blocks = (u32)(total_blocks / active_ports);
114814b24e2bSVaishali Kulkarni
114914b24e2bSVaishali Kulkarni for (port = 0; port < req->max_ports_per_engine; port++) {
115014b24e2bSVaishali Kulkarni u32 port_blocks, port_shared_blocks, port_guaranteed_blocks;
115114b24e2bSVaishali Kulkarni u32 full_xoff_th, full_xon_th, pause_xoff_th, pause_xon_th;
115214b24e2bSVaishali Kulkarni u32 tc_guaranteed_blocks;
115314b24e2bSVaishali Kulkarni u8 tc;
115414b24e2bSVaishali Kulkarni
115514b24e2bSVaishali Kulkarni /* Calculate per-port sizes */
115614b24e2bSVaishali Kulkarni tc_guaranteed_blocks = (u32)DIV_ROUND_UP(req->guranteed_per_tc, BRB_BLOCK_SIZE);
115714b24e2bSVaishali Kulkarni port_blocks = req->num_active_tcs[port] ? active_port_blocks : 0;
115814b24e2bSVaishali Kulkarni port_guaranteed_blocks = req->num_active_tcs[port] * tc_guaranteed_blocks;
115914b24e2bSVaishali Kulkarni port_shared_blocks = port_blocks - port_guaranteed_blocks;
116014b24e2bSVaishali Kulkarni full_xoff_th = req->num_active_tcs[port] * BRB_MIN_BLOCKS_PER_TC;
116114b24e2bSVaishali Kulkarni full_xon_th = full_xoff_th + min_pkt_size_blocks;
116214b24e2bSVaishali Kulkarni pause_xoff_th = tc_headroom_blocks;
116314b24e2bSVaishali Kulkarni pause_xon_th = pause_xoff_th + min_pkt_size_blocks;
116414b24e2bSVaishali Kulkarni
116514b24e2bSVaishali Kulkarni /* Init total size per port */
116614b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, BRB_REG_TOTAL_MAC_SIZE + port * 4, port_blocks);
116714b24e2bSVaishali Kulkarni
116814b24e2bSVaishali Kulkarni /* Init shared size per port */
116914b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, BRB_REG_SHARED_HR_AREA + port * 4, port_shared_blocks);
117014b24e2bSVaishali Kulkarni
117114b24e2bSVaishali Kulkarni for (tc = 0; tc < NUM_OF_TCS; tc++, reg_offset += 4) {
117214b24e2bSVaishali Kulkarni /* Clear init values for non-active TCs */
117314b24e2bSVaishali Kulkarni if (tc == req->num_active_tcs[port]) {
117414b24e2bSVaishali Kulkarni tc_guaranteed_blocks = 0;
117514b24e2bSVaishali Kulkarni full_xoff_th = 0;
117614b24e2bSVaishali Kulkarni full_xon_th = 0;
117714b24e2bSVaishali Kulkarni pause_xoff_th = 0;
117814b24e2bSVaishali Kulkarni pause_xon_th = 0;
117914b24e2bSVaishali Kulkarni }
118014b24e2bSVaishali Kulkarni
118114b24e2bSVaishali Kulkarni /* Init guaranteed size per TC */
118214b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, BRB_REG_TC_GUARANTIED_0 + reg_offset, tc_guaranteed_blocks);
118314b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, BRB_REG_MAIN_TC_GUARANTIED_HYST_0 + reg_offset, BRB_HYST_BLOCKS);
118414b24e2bSVaishali Kulkarni
118514b24e2bSVaishali Kulkarni /* Init pause/full thresholds per physical TC - for
118614b24e2bSVaishali Kulkarni * loopback traffic.
118714b24e2bSVaishali Kulkarni */
118814b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, BRB_REG_LB_TC_FULL_XOFF_THRESHOLD_0 + reg_offset, full_xoff_th);
118914b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, BRB_REG_LB_TC_FULL_XON_THRESHOLD_0 + reg_offset, full_xon_th);
119014b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, BRB_REG_LB_TC_PAUSE_XOFF_THRESHOLD_0 + reg_offset, pause_xoff_th);
119114b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, BRB_REG_LB_TC_PAUSE_XON_THRESHOLD_0 + reg_offset, pause_xon_th);
119214b24e2bSVaishali Kulkarni
119314b24e2bSVaishali Kulkarni /* Init pause/full thresholds per physical TC - for
119414b24e2bSVaishali Kulkarni * main traffic.
119514b24e2bSVaishali Kulkarni */
119614b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, BRB_REG_MAIN_TC_FULL_XOFF_THRESHOLD_0 + reg_offset, full_xoff_th);
119714b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, BRB_REG_MAIN_TC_FULL_XON_THRESHOLD_0 + reg_offset, full_xon_th);
119814b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, BRB_REG_MAIN_TC_PAUSE_XOFF_THRESHOLD_0 + reg_offset, pause_xoff_th);
119914b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, BRB_REG_MAIN_TC_PAUSE_XON_THRESHOLD_0 + reg_offset, pause_xon_th);
120014b24e2bSVaishali Kulkarni }
120114b24e2bSVaishali Kulkarni }
120214b24e2bSVaishali Kulkarni }
120314b24e2bSVaishali Kulkarni
120414b24e2bSVaishali Kulkarni #endif /* UNUSED_HSI_FUNC */
120514b24e2bSVaishali Kulkarni #ifndef UNUSED_HSI_FUNC
120614b24e2bSVaishali Kulkarni
120714b24e2bSVaishali Kulkarni /* In MF, should be called once per engine to set EtherType of OuterTag */
ecore_set_engine_mf_ovlan_eth_type(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u32 ethType)120814b24e2bSVaishali Kulkarni void ecore_set_engine_mf_ovlan_eth_type(struct ecore_hwfn *p_hwfn,
120914b24e2bSVaishali Kulkarni struct ecore_ptt *p_ptt, u32 ethType)
121014b24e2bSVaishali Kulkarni {
121114b24e2bSVaishali Kulkarni /* Update PRS register */
121214b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET, ethType);
121314b24e2bSVaishali Kulkarni
121414b24e2bSVaishali Kulkarni /* Update NIG register */
121514b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET, ethType);
121614b24e2bSVaishali Kulkarni
121714b24e2bSVaishali Kulkarni /* Update PBF register */
121814b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET, ethType);
121914b24e2bSVaishali Kulkarni }
122014b24e2bSVaishali Kulkarni
122114b24e2bSVaishali Kulkarni /* In MF, should be called once per port to set EtherType of OuterTag */
ecore_set_port_mf_ovlan_eth_type(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u32 ethType)122214b24e2bSVaishali Kulkarni void ecore_set_port_mf_ovlan_eth_type(struct ecore_hwfn *p_hwfn,
122314b24e2bSVaishali Kulkarni struct ecore_ptt *p_ptt, u32 ethType)
122414b24e2bSVaishali Kulkarni {
122514b24e2bSVaishali Kulkarni /* Update DORQ register */
122614b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET, ethType);
122714b24e2bSVaishali Kulkarni }
122814b24e2bSVaishali Kulkarni
122914b24e2bSVaishali Kulkarni #endif /* UNUSED_HSI_FUNC */
123014b24e2bSVaishali Kulkarni
123114b24e2bSVaishali Kulkarni
123214b24e2bSVaishali Kulkarni #define SET_TUNNEL_TYPE_ENABLE_BIT(var,offset,enable) var = ((var) & ~(1 << (offset))) | ( (enable) ? (1 << (offset)) : 0)
123314b24e2bSVaishali Kulkarni #define PRS_ETH_TUNN_FIC_FORMAT -188897008
123414b24e2bSVaishali Kulkarni
ecore_set_vxlan_dest_port(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u16 dest_port)123514b24e2bSVaishali Kulkarni void ecore_set_vxlan_dest_port(struct ecore_hwfn *p_hwfn,
123614b24e2bSVaishali Kulkarni struct ecore_ptt *p_ptt,
123714b24e2bSVaishali Kulkarni u16 dest_port)
123814b24e2bSVaishali Kulkarni {
123914b24e2bSVaishali Kulkarni /* Update PRS register */
124014b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, PRS_REG_VXLAN_PORT, dest_port);
124114b24e2bSVaishali Kulkarni
124214b24e2bSVaishali Kulkarni /* Update NIG register */
124314b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, NIG_REG_VXLAN_CTRL, dest_port);
124414b24e2bSVaishali Kulkarni
124514b24e2bSVaishali Kulkarni /* Update PBF register */
124614b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, PBF_REG_VXLAN_PORT, dest_port);
124714b24e2bSVaishali Kulkarni }
124814b24e2bSVaishali Kulkarni
ecore_set_vxlan_enable(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,bool vxlan_enable)124914b24e2bSVaishali Kulkarni void ecore_set_vxlan_enable(struct ecore_hwfn *p_hwfn,
125014b24e2bSVaishali Kulkarni struct ecore_ptt *p_ptt,
125114b24e2bSVaishali Kulkarni bool vxlan_enable)
125214b24e2bSVaishali Kulkarni {
125314b24e2bSVaishali Kulkarni u32 reg_val;
125414b24e2bSVaishali Kulkarni
125514b24e2bSVaishali Kulkarni /* Update PRS register */
125614b24e2bSVaishali Kulkarni reg_val = ecore_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
125714b24e2bSVaishali Kulkarni SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT, vxlan_enable);
125814b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
125914b24e2bSVaishali Kulkarni if (reg_val) /* TODO: handle E5 init */
126014b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2, (u32)PRS_ETH_TUNN_FIC_FORMAT);
126114b24e2bSVaishali Kulkarni
126214b24e2bSVaishali Kulkarni /* Update NIG register */
126314b24e2bSVaishali Kulkarni reg_val = ecore_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE);
126414b24e2bSVaishali Kulkarni SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, NIG_REG_ENC_TYPE_ENABLE_VXLAN_ENABLE_SHIFT, vxlan_enable);
126514b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE, reg_val);
126614b24e2bSVaishali Kulkarni
126714b24e2bSVaishali Kulkarni /* Update DORQ register */
126814b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, DORQ_REG_L2_EDPM_TUNNEL_VXLAN_EN, vxlan_enable ? 1 : 0);
126914b24e2bSVaishali Kulkarni }
127014b24e2bSVaishali Kulkarni
ecore_set_gre_enable(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,bool eth_gre_enable,bool ip_gre_enable)127114b24e2bSVaishali Kulkarni void ecore_set_gre_enable(struct ecore_hwfn *p_hwfn,
127214b24e2bSVaishali Kulkarni struct ecore_ptt *p_ptt,
127314b24e2bSVaishali Kulkarni bool eth_gre_enable,
127414b24e2bSVaishali Kulkarni bool ip_gre_enable)
127514b24e2bSVaishali Kulkarni {
127614b24e2bSVaishali Kulkarni u32 reg_val;
127714b24e2bSVaishali Kulkarni
127814b24e2bSVaishali Kulkarni /* Update PRS register */
127914b24e2bSVaishali Kulkarni reg_val = ecore_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
128014b24e2bSVaishali Kulkarni SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT, eth_gre_enable);
128114b24e2bSVaishali Kulkarni SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT, ip_gre_enable);
128214b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
128314b24e2bSVaishali Kulkarni if (reg_val) /* TODO: handle E5 init */
128414b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2, (u32)PRS_ETH_TUNN_FIC_FORMAT);
128514b24e2bSVaishali Kulkarni
128614b24e2bSVaishali Kulkarni /* Update NIG register */
128714b24e2bSVaishali Kulkarni reg_val = ecore_rd(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE);
128814b24e2bSVaishali Kulkarni SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, NIG_REG_ENC_TYPE_ENABLE_ETH_OVER_GRE_ENABLE_SHIFT, eth_gre_enable);
128914b24e2bSVaishali Kulkarni SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, NIG_REG_ENC_TYPE_ENABLE_IP_OVER_GRE_ENABLE_SHIFT, ip_gre_enable);
129014b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, NIG_REG_ENC_TYPE_ENABLE, reg_val);
129114b24e2bSVaishali Kulkarni
129214b24e2bSVaishali Kulkarni /* Update DORQ registers */
129314b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, DORQ_REG_L2_EDPM_TUNNEL_GRE_ETH_EN, eth_gre_enable ? 1 : 0);
129414b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, DORQ_REG_L2_EDPM_TUNNEL_GRE_IP_EN, ip_gre_enable ? 1 : 0);
129514b24e2bSVaishali Kulkarni }
129614b24e2bSVaishali Kulkarni
ecore_set_geneve_dest_port(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u16 dest_port)129714b24e2bSVaishali Kulkarni void ecore_set_geneve_dest_port(struct ecore_hwfn *p_hwfn,
129814b24e2bSVaishali Kulkarni struct ecore_ptt *p_ptt,
129914b24e2bSVaishali Kulkarni u16 dest_port)
130014b24e2bSVaishali Kulkarni
130114b24e2bSVaishali Kulkarni {
130214b24e2bSVaishali Kulkarni /* Update PRS register */
130314b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, PRS_REG_NGE_PORT, dest_port);
130414b24e2bSVaishali Kulkarni
130514b24e2bSVaishali Kulkarni /* Update NIG register */
130614b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, NIG_REG_NGE_PORT, dest_port);
130714b24e2bSVaishali Kulkarni
130814b24e2bSVaishali Kulkarni /* Update PBF register */
130914b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, PBF_REG_NGE_PORT, dest_port);
131014b24e2bSVaishali Kulkarni }
131114b24e2bSVaishali Kulkarni
ecore_set_geneve_enable(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,bool eth_geneve_enable,bool ip_geneve_enable)131214b24e2bSVaishali Kulkarni void ecore_set_geneve_enable(struct ecore_hwfn *p_hwfn,
131314b24e2bSVaishali Kulkarni struct ecore_ptt *p_ptt,
131414b24e2bSVaishali Kulkarni bool eth_geneve_enable,
131514b24e2bSVaishali Kulkarni bool ip_geneve_enable)
131614b24e2bSVaishali Kulkarni {
131714b24e2bSVaishali Kulkarni u32 reg_val;
131814b24e2bSVaishali Kulkarni
131914b24e2bSVaishali Kulkarni /* Update PRS register */
132014b24e2bSVaishali Kulkarni reg_val = ecore_rd(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN);
132114b24e2bSVaishali Kulkarni SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT, eth_geneve_enable);
132214b24e2bSVaishali Kulkarni SET_TUNNEL_TYPE_ENABLE_BIT(reg_val, PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT, ip_geneve_enable);
132314b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, PRS_REG_ENCAPSULATION_TYPE_EN, reg_val);
132414b24e2bSVaishali Kulkarni if (reg_val) /* TODO: handle E5 init */
132514b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, PRS_REG_OUTPUT_FORMAT_4_0_BB_K2, (u32)PRS_ETH_TUNN_FIC_FORMAT);
132614b24e2bSVaishali Kulkarni
132714b24e2bSVaishali Kulkarni /* Update NIG register */
132814b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, NIG_REG_NGE_ETH_ENABLE, eth_geneve_enable ? 1 : 0);
132914b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, NIG_REG_NGE_IP_ENABLE, ip_geneve_enable ? 1 : 0);
133014b24e2bSVaishali Kulkarni
133114b24e2bSVaishali Kulkarni /* EDPM with geneve tunnel not supported in BB */
133214b24e2bSVaishali Kulkarni if (ECORE_IS_BB_B0(p_hwfn->p_dev))
133314b24e2bSVaishali Kulkarni return;
133414b24e2bSVaishali Kulkarni
133514b24e2bSVaishali Kulkarni /* Update DORQ registers */
133614b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, DORQ_REG_L2_EDPM_TUNNEL_NGE_ETH_EN_K2_E5, eth_geneve_enable ? 1 : 0);
133714b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, DORQ_REG_L2_EDPM_TUNNEL_NGE_IP_EN_K2_E5, ip_geneve_enable ? 1 : 0);
133814b24e2bSVaishali Kulkarni }
133914b24e2bSVaishali Kulkarni
134014b24e2bSVaishali Kulkarni #ifndef UNUSED_HSI_FUNC
134114b24e2bSVaishali Kulkarni
134214b24e2bSVaishali Kulkarni #define T_ETH_PACKET_ACTION_GFT_EVENTID 23
134314b24e2bSVaishali Kulkarni #define PARSER_ETH_CONN_GFT_ACTION_CM_HDR 272
134414b24e2bSVaishali Kulkarni #define T_ETH_PACKET_MATCH_RFS_EVENTID 25
134514b24e2bSVaishali Kulkarni #define PARSER_ETH_CONN_CM_HDR 0
134614b24e2bSVaishali Kulkarni #define CAM_LINE_SIZE sizeof(u32)
134714b24e2bSVaishali Kulkarni #define RAM_LINE_SIZE sizeof(u64)
134814b24e2bSVaishali Kulkarni #define REG_SIZE sizeof(u32)
134914b24e2bSVaishali Kulkarni
135014b24e2bSVaishali Kulkarni
ecore_set_rfs_mode_disable(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u16 pf_id)135114b24e2bSVaishali Kulkarni void ecore_set_rfs_mode_disable(struct ecore_hwfn *p_hwfn,
135214b24e2bSVaishali Kulkarni struct ecore_ptt *p_ptt,
135314b24e2bSVaishali Kulkarni u16 pf_id)
135414b24e2bSVaishali Kulkarni {
135514b24e2bSVaishali Kulkarni union gft_cam_line_union cam_line;
135614b24e2bSVaishali Kulkarni struct gft_ram_line ram_line;
135714b24e2bSVaishali Kulkarni u32 i, *ram_line_ptr;
135814b24e2bSVaishali Kulkarni
135914b24e2bSVaishali Kulkarni ram_line_ptr = (u32*)&ram_line;
136014b24e2bSVaishali Kulkarni
136114b24e2bSVaishali Kulkarni /* Stop using gft logic, disable gft search */
136214b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_GFT, 0);
136314b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT, 0x0);
136414b24e2bSVaishali Kulkarni
136514b24e2bSVaishali Kulkarni /* Clean ram & cam for next rfs/gft session*/
136614b24e2bSVaishali Kulkarni
136714b24e2bSVaishali Kulkarni /* Zero camline */
136814b24e2bSVaishali Kulkarni OSAL_MEMSET(&cam_line, 0, sizeof(cam_line));
136914b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE*pf_id, cam_line.cam_line_mapped.camline);
137014b24e2bSVaishali Kulkarni
137114b24e2bSVaishali Kulkarni /* Zero ramline */
137214b24e2bSVaishali Kulkarni OSAL_MEMSET(&ram_line, 0, sizeof(ram_line));
137314b24e2bSVaishali Kulkarni
137414b24e2bSVaishali Kulkarni /* Each iteration write to reg */
137514b24e2bSVaishali Kulkarni for (i = 0; i < RAM_LINE_SIZE / REG_SIZE; i++)
137614b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE*pf_id + i*REG_SIZE, *(ram_line_ptr + i));
137714b24e2bSVaishali Kulkarni }
137814b24e2bSVaishali Kulkarni
137914b24e2bSVaishali Kulkarni
ecore_set_gft_event_id_cm_hdr(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt)138014b24e2bSVaishali Kulkarni void ecore_set_gft_event_id_cm_hdr (struct ecore_hwfn *p_hwfn,
138114b24e2bSVaishali Kulkarni struct ecore_ptt *p_ptt)
138214b24e2bSVaishali Kulkarni {
138314b24e2bSVaishali Kulkarni u32 rfs_cm_hdr_event_id;
138414b24e2bSVaishali Kulkarni
138514b24e2bSVaishali Kulkarni /* Set RFS event ID to be awakened i Tstorm By Prs */
138614b24e2bSVaishali Kulkarni rfs_cm_hdr_event_id = ecore_rd(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT);
138714b24e2bSVaishali Kulkarni rfs_cm_hdr_event_id |= T_ETH_PACKET_ACTION_GFT_EVENTID << PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT;
138814b24e2bSVaishali Kulkarni rfs_cm_hdr_event_id |= PARSER_ETH_CONN_GFT_ACTION_CM_HDR << PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT;
138914b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT, rfs_cm_hdr_event_id);
139014b24e2bSVaishali Kulkarni }
139114b24e2bSVaishali Kulkarni
ecore_set_rfs_mode_enable(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u16 pf_id,bool tcp,bool udp,bool ipv4,bool ipv6)139214b24e2bSVaishali Kulkarni void ecore_set_rfs_mode_enable(struct ecore_hwfn *p_hwfn,
139314b24e2bSVaishali Kulkarni struct ecore_ptt *p_ptt,
139414b24e2bSVaishali Kulkarni u16 pf_id,
139514b24e2bSVaishali Kulkarni bool tcp,
139614b24e2bSVaishali Kulkarni bool udp,
139714b24e2bSVaishali Kulkarni bool ipv4,
139814b24e2bSVaishali Kulkarni bool ipv6)
139914b24e2bSVaishali Kulkarni {
140014b24e2bSVaishali Kulkarni u32 rfs_cm_hdr_event_id, *ram_line_ptr;
140114b24e2bSVaishali Kulkarni union gft_cam_line_union cam_line;
140214b24e2bSVaishali Kulkarni struct gft_ram_line ram_line;
140314b24e2bSVaishali Kulkarni int i;
140414b24e2bSVaishali Kulkarni
140514b24e2bSVaishali Kulkarni rfs_cm_hdr_event_id = ecore_rd(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT);
140614b24e2bSVaishali Kulkarni ram_line_ptr = (u32*)&ram_line;
140714b24e2bSVaishali Kulkarni
140814b24e2bSVaishali Kulkarni if (!ipv6 && !ipv4)
140914b24e2bSVaishali Kulkarni DP_NOTICE(p_hwfn, true, "set_rfs_mode_enable: must accept at least on of - ipv4 or ipv6\n");
141014b24e2bSVaishali Kulkarni if (!tcp && !udp)
141114b24e2bSVaishali Kulkarni DP_NOTICE(p_hwfn, true, "set_rfs_mode_enable: must accept at least on of - udp or tcp\n");
141214b24e2bSVaishali Kulkarni
141314b24e2bSVaishali Kulkarni /* Set RFS event ID to be awakened i Tstorm By Prs */
141414b24e2bSVaishali Kulkarni rfs_cm_hdr_event_id |= T_ETH_PACKET_MATCH_RFS_EVENTID << PRS_REG_CM_HDR_GFT_EVENT_ID_SHIFT;
141514b24e2bSVaishali Kulkarni rfs_cm_hdr_event_id |= PARSER_ETH_CONN_CM_HDR << PRS_REG_CM_HDR_GFT_CM_HDR_SHIFT;
141614b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, PRS_REG_CM_HDR_GFT, rfs_cm_hdr_event_id);
141714b24e2bSVaishali Kulkarni
141814b24e2bSVaishali Kulkarni /* Configure Registers for RFS mode */
141914b24e2bSVaishali Kulkarni
142014b24e2bSVaishali Kulkarni /* Enable gft search */
142114b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, PRS_REG_SEARCH_GFT, 1);
142214b24e2bSVaishali Kulkarni
142314b24e2bSVaishali Kulkarni /* Do not load context only cid in PRS on match. */
142414b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, PRS_REG_LOAD_L2_FILTER, 0);
142514b24e2bSVaishali Kulkarni
142614b24e2bSVaishali Kulkarni /* Cam line is now valid!! */
142714b24e2bSVaishali Kulkarni cam_line.cam_line_mapped.camline = 0;
142814b24e2bSVaishali Kulkarni SET_FIELD(cam_line.cam_line_mapped.camline, GFT_CAM_LINE_MAPPED_VALID, 1);
142914b24e2bSVaishali Kulkarni
143014b24e2bSVaishali Kulkarni /* Filters are per PF!! */
143114b24e2bSVaishali Kulkarni SET_FIELD(cam_line.cam_line_mapped.camline, GFT_CAM_LINE_MAPPED_PF_ID_MASK, GFT_CAM_LINE_MAPPED_PF_ID_MASK_MASK);
143214b24e2bSVaishali Kulkarni SET_FIELD(cam_line.cam_line_mapped.camline, GFT_CAM_LINE_MAPPED_PF_ID, pf_id);
143314b24e2bSVaishali Kulkarni
143414b24e2bSVaishali Kulkarni if (!(tcp && udp)) {
143514b24e2bSVaishali Kulkarni SET_FIELD(cam_line.cam_line_mapped.camline, GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK, GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE_MASK_MASK);
143614b24e2bSVaishali Kulkarni if (tcp)
143714b24e2bSVaishali Kulkarni SET_FIELD(cam_line.cam_line_mapped.camline, GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE, GFT_PROFILE_TCP_PROTOCOL);
143814b24e2bSVaishali Kulkarni else
143914b24e2bSVaishali Kulkarni SET_FIELD(cam_line.cam_line_mapped.camline, GFT_CAM_LINE_MAPPED_UPPER_PROTOCOL_TYPE, GFT_PROFILE_UDP_PROTOCOL);
144014b24e2bSVaishali Kulkarni }
144114b24e2bSVaishali Kulkarni
144214b24e2bSVaishali Kulkarni if (!(ipv4 && ipv6)) {
144314b24e2bSVaishali Kulkarni SET_FIELD(cam_line.cam_line_mapped.camline, GFT_CAM_LINE_MAPPED_IP_VERSION_MASK, 1);
144414b24e2bSVaishali Kulkarni if (ipv4)
144514b24e2bSVaishali Kulkarni SET_FIELD(cam_line.cam_line_mapped.camline, GFT_CAM_LINE_MAPPED_IP_VERSION, GFT_PROFILE_IPV4);
144614b24e2bSVaishali Kulkarni else
144714b24e2bSVaishali Kulkarni SET_FIELD(cam_line.cam_line_mapped.camline, GFT_CAM_LINE_MAPPED_IP_VERSION, GFT_PROFILE_IPV6);
144814b24e2bSVaishali Kulkarni }
144914b24e2bSVaishali Kulkarni
145014b24e2bSVaishali Kulkarni /* Write characteristics to cam */
145114b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE*pf_id, cam_line.cam_line_mapped.camline);
145214b24e2bSVaishali Kulkarni cam_line.cam_line_mapped.camline = ecore_rd(p_hwfn, p_ptt, PRS_REG_GFT_CAM + CAM_LINE_SIZE*pf_id);
145314b24e2bSVaishali Kulkarni
145414b24e2bSVaishali Kulkarni /* Write line to RAM - compare to filter 4 tuple */
145514b24e2bSVaishali Kulkarni ram_line.lo = 0;
145614b24e2bSVaishali Kulkarni ram_line.hi= 0;
145714b24e2bSVaishali Kulkarni SET_FIELD(ram_line.hi, GFT_RAM_LINE_DST_IP, 1);
145814b24e2bSVaishali Kulkarni SET_FIELD(ram_line.hi, GFT_RAM_LINE_SRC_IP, 1);
145914b24e2bSVaishali Kulkarni SET_FIELD(ram_line.hi, GFT_RAM_LINE_OVER_IP_PROTOCOL, 1);
146014b24e2bSVaishali Kulkarni SET_FIELD(ram_line.lo, GFT_RAM_LINE_ETHERTYPE, 1);
146114b24e2bSVaishali Kulkarni SET_FIELD(ram_line.lo, GFT_RAM_LINE_SRC_PORT, 1);
146214b24e2bSVaishali Kulkarni SET_FIELD(ram_line.lo, GFT_RAM_LINE_DST_PORT, 1);
146314b24e2bSVaishali Kulkarni
146414b24e2bSVaishali Kulkarni
146514b24e2bSVaishali Kulkarni /* Each iteration write to reg */
146614b24e2bSVaishali Kulkarni for (i = 0; i < RAM_LINE_SIZE / REG_SIZE; i++)
146714b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE*pf_id + i*REG_SIZE, *(ram_line_ptr + i));
146814b24e2bSVaishali Kulkarni
146914b24e2bSVaishali Kulkarni /* Set default profile so that no filter match will happen */
147014b24e2bSVaishali Kulkarni ram_line.lo = 0xffffffff;
147114b24e2bSVaishali Kulkarni ram_line.hi = 0x3ff;
147214b24e2bSVaishali Kulkarni
147314b24e2bSVaishali Kulkarni for (i = 0; i < RAM_LINE_SIZE / REG_SIZE; i++)
147414b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, PRS_REG_GFT_PROFILE_MASK_RAM + RAM_LINE_SIZE*PRS_GFT_CAM_LINES_NO_MATCH + i*REG_SIZE, *(ram_line_ptr + i));
147514b24e2bSVaishali Kulkarni }
147614b24e2bSVaishali Kulkarni
147714b24e2bSVaishali Kulkarni
147814b24e2bSVaishali Kulkarni #endif /* UNUSED_HSI_FUNC */
147914b24e2bSVaishali Kulkarni
148014b24e2bSVaishali Kulkarni /* Configure VF zone size mode*/
ecore_config_vf_zone_size_mode(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt,u16 mode,bool runtime_init)148114b24e2bSVaishali Kulkarni void ecore_config_vf_zone_size_mode(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt, u16 mode, bool runtime_init)
148214b24e2bSVaishali Kulkarni {
148314b24e2bSVaishali Kulkarni u32 msdm_vf_size_log = MSTORM_VF_ZONE_DEFAULT_SIZE_LOG;
148414b24e2bSVaishali Kulkarni u32 msdm_vf_offset_mask;
148514b24e2bSVaishali Kulkarni
148614b24e2bSVaishali Kulkarni if (mode == VF_ZONE_SIZE_MODE_DOUBLE)
148714b24e2bSVaishali Kulkarni msdm_vf_size_log += 1;
148814b24e2bSVaishali Kulkarni else if (mode == VF_ZONE_SIZE_MODE_QUAD)
148914b24e2bSVaishali Kulkarni msdm_vf_size_log += 2;
149014b24e2bSVaishali Kulkarni
149114b24e2bSVaishali Kulkarni msdm_vf_offset_mask = (1 << msdm_vf_size_log) - 1;
149214b24e2bSVaishali Kulkarni
149314b24e2bSVaishali Kulkarni if (runtime_init) {
149414b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET, msdm_vf_size_log);
149514b24e2bSVaishali Kulkarni STORE_RT_REG(p_hwfn, PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET, msdm_vf_offset_mask);
149614b24e2bSVaishali Kulkarni }
149714b24e2bSVaishali Kulkarni else {
149814b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MSDM_VF_SHIFT_B, msdm_vf_size_log);
149914b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, PGLUE_B_REG_MSDM_OFFSET_MASK_B, msdm_vf_offset_mask);
150014b24e2bSVaishali Kulkarni }
150114b24e2bSVaishali Kulkarni }
150214b24e2bSVaishali Kulkarni
150314b24e2bSVaishali Kulkarni /* Get mstorm statistics for offset by VF zone size mode */
ecore_get_mstorm_queue_stat_offset(struct ecore_hwfn * p_hwfn,u16 stat_cnt_id,u16 vf_zone_size_mode)150414b24e2bSVaishali Kulkarni u32 ecore_get_mstorm_queue_stat_offset(struct ecore_hwfn *p_hwfn, u16 stat_cnt_id, u16 vf_zone_size_mode)
150514b24e2bSVaishali Kulkarni {
150614b24e2bSVaishali Kulkarni u32 offset = MSTORM_QUEUE_STAT_OFFSET(stat_cnt_id);
150714b24e2bSVaishali Kulkarni
150814b24e2bSVaishali Kulkarni if ((vf_zone_size_mode != VF_ZONE_SIZE_MODE_DEFAULT) && (stat_cnt_id > MAX_NUM_PFS)) {
150914b24e2bSVaishali Kulkarni if (vf_zone_size_mode == VF_ZONE_SIZE_MODE_DOUBLE)
151014b24e2bSVaishali Kulkarni offset += (1 << MSTORM_VF_ZONE_DEFAULT_SIZE_LOG) * (stat_cnt_id - MAX_NUM_PFS);
151114b24e2bSVaishali Kulkarni else if (vf_zone_size_mode == VF_ZONE_SIZE_MODE_QUAD)
151214b24e2bSVaishali Kulkarni offset += 3 * (1 << MSTORM_VF_ZONE_DEFAULT_SIZE_LOG) * (stat_cnt_id - MAX_NUM_PFS);
151314b24e2bSVaishali Kulkarni }
151414b24e2bSVaishali Kulkarni
151514b24e2bSVaishali Kulkarni return offset;
151614b24e2bSVaishali Kulkarni }
151714b24e2bSVaishali Kulkarni
151814b24e2bSVaishali Kulkarni /* Get mstorm VF producer offset by VF zone size mode */
ecore_get_mstorm_eth_vf_prods_offset(struct ecore_hwfn * p_hwfn,u8 vf_id,u8 vf_queue_id,u16 vf_zone_size_mode)151914b24e2bSVaishali Kulkarni u32 ecore_get_mstorm_eth_vf_prods_offset(struct ecore_hwfn *p_hwfn, u8 vf_id, u8 vf_queue_id, u16 vf_zone_size_mode)
152014b24e2bSVaishali Kulkarni {
152114b24e2bSVaishali Kulkarni u32 offset = MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id);
152214b24e2bSVaishali Kulkarni
152314b24e2bSVaishali Kulkarni if (vf_zone_size_mode != VF_ZONE_SIZE_MODE_DEFAULT) {
152414b24e2bSVaishali Kulkarni if (vf_zone_size_mode == VF_ZONE_SIZE_MODE_DOUBLE)
152514b24e2bSVaishali Kulkarni offset += (1 << MSTORM_VF_ZONE_DEFAULT_SIZE_LOG) * vf_id;
152614b24e2bSVaishali Kulkarni else if (vf_zone_size_mode == VF_ZONE_SIZE_MODE_QUAD)
152714b24e2bSVaishali Kulkarni offset += 3 * (1 << MSTORM_VF_ZONE_DEFAULT_SIZE_LOG) * vf_id;
152814b24e2bSVaishali Kulkarni }
152914b24e2bSVaishali Kulkarni
153014b24e2bSVaishali Kulkarni return offset;
153114b24e2bSVaishali Kulkarni }
153214b24e2bSVaishali Kulkarni
153314b24e2bSVaishali Kulkarni #ifndef LINUX_REMOVE
153414b24e2bSVaishali Kulkarni #define CRC8_INIT_VALUE 0xFF
153514b24e2bSVaishali Kulkarni #endif
153614b24e2bSVaishali Kulkarni static u8 cdu_crc8_table[CRC8_TABLE_SIZE];
153714b24e2bSVaishali Kulkarni
153814b24e2bSVaishali Kulkarni /* Calculate and return CDU validation byte per connection type/region/cid */
ecore_calc_cdu_validation_byte(struct ecore_hwfn * p_hwfn,u8 conn_type,u8 region,u32 cid)153914b24e2bSVaishali Kulkarni static u8 ecore_calc_cdu_validation_byte(struct ecore_hwfn * p_hwfn, u8 conn_type,
154014b24e2bSVaishali Kulkarni u8 region, u32 cid)
154114b24e2bSVaishali Kulkarni {
154214b24e2bSVaishali Kulkarni const u8 validation_cfg = CDU_VALIDATION_DEFAULT_CFG;
154314b24e2bSVaishali Kulkarni
154414b24e2bSVaishali Kulkarni static u8 crc8_table_valid; /*automatically initialized to 0*/
154514b24e2bSVaishali Kulkarni u8 crc, validation_byte = 0;
154614b24e2bSVaishali Kulkarni u32 validation_string = 0;
154714b24e2bSVaishali Kulkarni u32 data_to_crc;
154814b24e2bSVaishali Kulkarni
154914b24e2bSVaishali Kulkarni if (crc8_table_valid == 0) {
155014b24e2bSVaishali Kulkarni OSAL_CRC8_POPULATE(cdu_crc8_table, 0x07);
155114b24e2bSVaishali Kulkarni crc8_table_valid = 1;
155214b24e2bSVaishali Kulkarni }
155314b24e2bSVaishali Kulkarni
155414b24e2bSVaishali Kulkarni /* The CRC is calculated on the String-to-compress:
155514b24e2bSVaishali Kulkarni * [31:8] = {CID[31:20],CID[11:0]}
155614b24e2bSVaishali Kulkarni * [7:4] = Region
155714b24e2bSVaishali Kulkarni * [3:0] = Type
155814b24e2bSVaishali Kulkarni */
155914b24e2bSVaishali Kulkarni if ((validation_cfg >> CDU_CONTEXT_VALIDATION_CFG_USE_CID) & 1)
156014b24e2bSVaishali Kulkarni validation_string |= (cid & 0xFFF00000) | ((cid & 0xFFF) << 8);
156114b24e2bSVaishali Kulkarni
156214b24e2bSVaishali Kulkarni if ((validation_cfg >> CDU_CONTEXT_VALIDATION_CFG_USE_REGION) & 1)
156314b24e2bSVaishali Kulkarni validation_string |= ((region & 0xF) << 4);
156414b24e2bSVaishali Kulkarni
156514b24e2bSVaishali Kulkarni if ((validation_cfg >> CDU_CONTEXT_VALIDATION_CFG_USE_TYPE) & 1)
156614b24e2bSVaishali Kulkarni validation_string |= (conn_type & 0xF);
156714b24e2bSVaishali Kulkarni
156814b24e2bSVaishali Kulkarni /* Convert to big-endian and calculate CRC8*/
156914b24e2bSVaishali Kulkarni data_to_crc = OSAL_BE32_TO_CPU(validation_string);
157014b24e2bSVaishali Kulkarni
157114b24e2bSVaishali Kulkarni crc = OSAL_CRC8(cdu_crc8_table, (u8 *)&data_to_crc, sizeof(data_to_crc), CRC8_INIT_VALUE);
157214b24e2bSVaishali Kulkarni
157314b24e2bSVaishali Kulkarni /* The validation byte [7:0] is composed:
157414b24e2bSVaishali Kulkarni * for type A validation
157514b24e2bSVaishali Kulkarni * [7] = active configuration bit
157614b24e2bSVaishali Kulkarni * [6:0] = crc[6:0]
157714b24e2bSVaishali Kulkarni *
157814b24e2bSVaishali Kulkarni * for type B validation
157914b24e2bSVaishali Kulkarni * [7] = active configuration bit
158014b24e2bSVaishali Kulkarni * [6:3] = connection_type[3:0]
158114b24e2bSVaishali Kulkarni * [2:0] = crc[2:0]
158214b24e2bSVaishali Kulkarni */
158314b24e2bSVaishali Kulkarni validation_byte |= ((validation_cfg >> CDU_CONTEXT_VALIDATION_CFG_USE_ACTIVE) & 1) << 7;
158414b24e2bSVaishali Kulkarni
158514b24e2bSVaishali Kulkarni if ((validation_cfg >> CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT) & 1)
158614b24e2bSVaishali Kulkarni validation_byte |= ((conn_type & 0xF) << 3) | (crc & 0x7);
158714b24e2bSVaishali Kulkarni else
158814b24e2bSVaishali Kulkarni validation_byte |= crc & 0x7F;
158914b24e2bSVaishali Kulkarni
159014b24e2bSVaishali Kulkarni return validation_byte;
159114b24e2bSVaishali Kulkarni }
159214b24e2bSVaishali Kulkarni
159314b24e2bSVaishali Kulkarni /* Calcualte and set validation bytes for session context */
ecore_calc_session_ctx_validation(struct ecore_hwfn * p_hwfn,void * p_ctx_mem,u16 ctx_size,u8 ctx_type,u32 cid)159414b24e2bSVaishali Kulkarni void ecore_calc_session_ctx_validation(struct ecore_hwfn * p_hwfn, void *p_ctx_mem,
159514b24e2bSVaishali Kulkarni u16 ctx_size, u8 ctx_type, u32 cid)
159614b24e2bSVaishali Kulkarni {
159714b24e2bSVaishali Kulkarni u8 *x_val_ptr, *t_val_ptr, *u_val_ptr, *p_ctx;
159814b24e2bSVaishali Kulkarni
159914b24e2bSVaishali Kulkarni p_ctx = (u8* const)p_ctx_mem;
160014b24e2bSVaishali Kulkarni x_val_ptr = &p_ctx[con_region_offsets[0][ctx_type]];
160114b24e2bSVaishali Kulkarni t_val_ptr = &p_ctx[con_region_offsets[1][ctx_type]];
160214b24e2bSVaishali Kulkarni u_val_ptr = &p_ctx[con_region_offsets[2][ctx_type]];
160314b24e2bSVaishali Kulkarni
160414b24e2bSVaishali Kulkarni OSAL_MEMSET(p_ctx, 0, ctx_size);
160514b24e2bSVaishali Kulkarni
160614b24e2bSVaishali Kulkarni *x_val_ptr = ecore_calc_cdu_validation_byte(p_hwfn, ctx_type, 3, cid);
160714b24e2bSVaishali Kulkarni *t_val_ptr = ecore_calc_cdu_validation_byte(p_hwfn, ctx_type, 4, cid);
160814b24e2bSVaishali Kulkarni *u_val_ptr = ecore_calc_cdu_validation_byte(p_hwfn, ctx_type, 5, cid);
160914b24e2bSVaishali Kulkarni }
161014b24e2bSVaishali Kulkarni
161114b24e2bSVaishali Kulkarni /* Calcualte and set validation bytes for task context */
ecore_calc_task_ctx_validation(struct ecore_hwfn * p_hwfn,void * p_ctx_mem,u16 ctx_size,u8 ctx_type,u32 tid)161214b24e2bSVaishali Kulkarni void ecore_calc_task_ctx_validation(struct ecore_hwfn * p_hwfn, void *p_ctx_mem,
161314b24e2bSVaishali Kulkarni u16 ctx_size, u8 ctx_type, u32 tid)
161414b24e2bSVaishali Kulkarni {
161514b24e2bSVaishali Kulkarni u8 *p_ctx, *region1_val_ptr;
161614b24e2bSVaishali Kulkarni
161714b24e2bSVaishali Kulkarni p_ctx = (u8* const)p_ctx_mem;
161814b24e2bSVaishali Kulkarni region1_val_ptr = &p_ctx[task_region_offsets[0][ctx_type]];
161914b24e2bSVaishali Kulkarni
162014b24e2bSVaishali Kulkarni OSAL_MEMSET(p_ctx, 0, ctx_size);
162114b24e2bSVaishali Kulkarni
162214b24e2bSVaishali Kulkarni *region1_val_ptr = ecore_calc_cdu_validation_byte(p_hwfn, ctx_type,
162314b24e2bSVaishali Kulkarni 1, tid);
162414b24e2bSVaishali Kulkarni }
162514b24e2bSVaishali Kulkarni
162614b24e2bSVaishali Kulkarni /* Memset session context to 0 while preserving validation bytes */
ecore_memset_session_ctx(void * p_ctx_mem,u32 ctx_size,u8 ctx_type)162714b24e2bSVaishali Kulkarni void ecore_memset_session_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type)
162814b24e2bSVaishali Kulkarni {
162914b24e2bSVaishali Kulkarni u8 *x_val_ptr, *t_val_ptr, *u_val_ptr, *p_ctx;
163014b24e2bSVaishali Kulkarni u8 x_val, t_val, u_val;
163114b24e2bSVaishali Kulkarni
163214b24e2bSVaishali Kulkarni p_ctx = (u8* const)p_ctx_mem;
163314b24e2bSVaishali Kulkarni x_val_ptr = &p_ctx[con_region_offsets[0][ctx_type]];
163414b24e2bSVaishali Kulkarni t_val_ptr = &p_ctx[con_region_offsets[1][ctx_type]];
163514b24e2bSVaishali Kulkarni u_val_ptr = &p_ctx[con_region_offsets[2][ctx_type]];
163614b24e2bSVaishali Kulkarni
163714b24e2bSVaishali Kulkarni x_val = *x_val_ptr;
163814b24e2bSVaishali Kulkarni t_val = *t_val_ptr;
163914b24e2bSVaishali Kulkarni u_val = *u_val_ptr;
164014b24e2bSVaishali Kulkarni
164114b24e2bSVaishali Kulkarni OSAL_MEMSET(p_ctx, 0, ctx_size);
164214b24e2bSVaishali Kulkarni
164314b24e2bSVaishali Kulkarni *x_val_ptr = x_val;
164414b24e2bSVaishali Kulkarni *t_val_ptr = t_val;
164514b24e2bSVaishali Kulkarni *u_val_ptr = u_val;
164614b24e2bSVaishali Kulkarni }
164714b24e2bSVaishali Kulkarni
164814b24e2bSVaishali Kulkarni /* Memset task context to 0 while preserving validation bytes */
ecore_memset_task_ctx(void * p_ctx_mem,u32 ctx_size,u8 ctx_type)164914b24e2bSVaishali Kulkarni void ecore_memset_task_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type)
165014b24e2bSVaishali Kulkarni {
165114b24e2bSVaishali Kulkarni u8 *p_ctx, *region1_val_ptr;
165214b24e2bSVaishali Kulkarni u8 region1_val;
165314b24e2bSVaishali Kulkarni
165414b24e2bSVaishali Kulkarni p_ctx = (u8* const)p_ctx_mem;
165514b24e2bSVaishali Kulkarni region1_val_ptr = &p_ctx[task_region_offsets[0][ctx_type]];
165614b24e2bSVaishali Kulkarni
165714b24e2bSVaishali Kulkarni region1_val = *region1_val_ptr;
165814b24e2bSVaishali Kulkarni
165914b24e2bSVaishali Kulkarni OSAL_MEMSET(p_ctx, 0, ctx_size);
166014b24e2bSVaishali Kulkarni
166114b24e2bSVaishali Kulkarni *region1_val_ptr = region1_val;
166214b24e2bSVaishali Kulkarni }
166314b24e2bSVaishali Kulkarni
166414b24e2bSVaishali Kulkarni /* Enable and configure context validation */
ecore_enable_context_validation(struct ecore_hwfn * p_hwfn,struct ecore_ptt * p_ptt)166514b24e2bSVaishali Kulkarni void ecore_enable_context_validation(struct ecore_hwfn * p_hwfn, struct ecore_ptt *p_ptt)
166614b24e2bSVaishali Kulkarni {
166714b24e2bSVaishali Kulkarni u32 ctx_validation;
166814b24e2bSVaishali Kulkarni
166914b24e2bSVaishali Kulkarni /* Enable validation for connection region 3: CCFC_CTX_VALID0[31:24] */
167014b24e2bSVaishali Kulkarni ctx_validation = CDU_VALIDATION_DEFAULT_CFG << 24;
167114b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, CDU_REG_CCFC_CTX_VALID0, ctx_validation);
167214b24e2bSVaishali Kulkarni
167314b24e2bSVaishali Kulkarni /* Enable validation for connection region 5: CCFC_CTX_VALID1[15:8] */
167414b24e2bSVaishali Kulkarni ctx_validation = CDU_VALIDATION_DEFAULT_CFG << 8;
167514b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, CDU_REG_CCFC_CTX_VALID1, ctx_validation);
167614b24e2bSVaishali Kulkarni
167714b24e2bSVaishali Kulkarni /* Enable validation for connection region 1: TCFC_CTX_VALID0[15:8] */
167814b24e2bSVaishali Kulkarni ctx_validation = CDU_VALIDATION_DEFAULT_CFG << 8;
167914b24e2bSVaishali Kulkarni ecore_wr(p_hwfn, p_ptt, CDU_REG_TCFC_CTX_VALID0, ctx_validation);
168014b24e2bSVaishali Kulkarni }
1681