1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, v.1, (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://opensource.org/licenses/CDDL-1.0. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2014-2017 Cavium, Inc. 24 * The contents of this file are subject to the terms of the Common Development 25 * and Distribution License, v.1, (the "License"). 26 27 * You may not use this file except in compliance with the License. 28 29 * You can obtain a copy of the License at available 30 * at http://opensource.org/licenses/CDDL-1.0 31 32 * See the License for the specific language governing permissions and 33 * limitations under the License. 34 */ 35 36 #ifndef __ECORE_HSI_RDMA__ 37 #define __ECORE_HSI_RDMA__ 38 /************************************************************************/ 39 /* Add include to common rdma target for both eCore and protocol rdma driver */ 40 /************************************************************************/ 41 #include "rdma_common.h" 42 43 /* 44 * The roce task context of Mstorm 45 */ 46 struct mstorm_rdma_task_st_ctx 47 { 48 struct regpair temp[4]; 49 }; 50 51 52 /* 53 * rdma function init ramrod data 54 */ 55 struct rdma_close_func_ramrod_data 56 { 57 u8 cnq_start_offset; 58 u8 num_cnqs; 59 u8 vf_id /* This field should be assigned to Virtual Function ID if vf_valid == 1. Otherwise its dont care */; 60 u8 vf_valid; 61 u8 reserved[4]; 62 }; 63 64 65 /* 66 * rdma function init CNQ parameters 67 */ 68 struct rdma_cnq_params 69 { 70 __le16 sb_num /* Status block number used by the queue */; 71 u8 sb_index /* Status block index used by the queue */; 72 u8 num_pbl_pages /* Number of pages in the PBL allocated for this queue */; 73 __le32 reserved; 74 struct regpair pbl_base_addr /* Address to the first entry of the queue PBL */; 75 __le16 queue_zone_num /* Queue Zone ID used for CNQ consumer update */; 76 u8 reserved1[6]; 77 }; 78 79 80 /* 81 * rdma create cq ramrod data 82 */ 83 struct rdma_create_cq_ramrod_data 84 { 85 struct regpair cq_handle; 86 struct regpair pbl_addr; 87 __le32 max_cqes; 88 __le16 pbl_num_pages; 89 __le16 dpi; 90 u8 is_two_level_pbl; 91 u8 cnq_id; 92 u8 pbl_log_page_size; 93 u8 toggle_bit; 94 __le16 int_timeout /* Timeout used for interrupt moderation */; 95 __le16 reserved1; 96 }; 97 98 99 /* 100 * rdma deregister tid ramrod data 101 */ 102 struct rdma_deregister_tid_ramrod_data 103 { 104 __le32 itid; 105 __le32 reserved; 106 }; 107 108 109 /* 110 * rdma destroy cq output params 111 */ 112 struct rdma_destroy_cq_output_params 113 { 114 __le16 cnq_num /* Sequence number of completion notification sent for the cq on the associated CNQ */; 115 __le16 reserved0; 116 __le32 reserved1; 117 }; 118 119 120 /* 121 * rdma destroy cq ramrod data 122 */ 123 struct rdma_destroy_cq_ramrod_data 124 { 125 struct regpair output_params_addr; 126 }; 127 128 129 /* 130 * RDMA slow path EQ cmd IDs 131 */ 132 enum rdma_event_opcode 133 { 134 RDMA_EVENT_UNUSED, 135 RDMA_EVENT_FUNC_INIT, 136 RDMA_EVENT_FUNC_CLOSE, 137 RDMA_EVENT_REGISTER_MR, 138 RDMA_EVENT_DEREGISTER_MR, 139 RDMA_EVENT_CREATE_CQ, 140 RDMA_EVENT_RESIZE_CQ, 141 RDMA_EVENT_DESTROY_CQ, 142 RDMA_EVENT_CREATE_SRQ, 143 RDMA_EVENT_MODIFY_SRQ, 144 RDMA_EVENT_DESTROY_SRQ, 145 MAX_RDMA_EVENT_OPCODE 146 }; 147 148 149 /* 150 * RDMA FW return code for slow path ramrods 151 */ 152 enum rdma_fw_return_code 153 { 154 RDMA_RETURN_OK=0, 155 RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR, 156 RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR, 157 RDMA_RETURN_RESIZE_CQ_ERR, 158 RDMA_RETURN_NIG_DRAIN_REQ, 159 MAX_RDMA_FW_RETURN_CODE 160 }; 161 162 163 /* 164 * rdma function init header 165 */ 166 struct rdma_init_func_hdr 167 { 168 u8 cnq_start_offset /* First RDMA CNQ */; 169 u8 num_cnqs /* Number of CNQs */; 170 u8 cq_ring_mode /* 0 for 32 bit cq producer and consumer counters and 1 for 16 bit */; 171 u8 vf_id /* This field should be assigned to Virtual Function ID if vf_valid == 1. Otherwise its dont care */; 172 u8 vf_valid; 173 u8 reserved[3]; 174 }; 175 176 177 /* 178 * rdma function init ramrod data 179 */ 180 struct rdma_init_func_ramrod_data 181 { 182 struct rdma_init_func_hdr params_header; 183 struct rdma_cnq_params cnq_params[NUM_OF_GLOBAL_QUEUES]; 184 }; 185 186 187 /* 188 * RDMA ramrod command IDs 189 */ 190 enum rdma_ramrod_cmd_id 191 { 192 RDMA_RAMROD_UNUSED, 193 RDMA_RAMROD_FUNC_INIT, 194 RDMA_RAMROD_FUNC_CLOSE, 195 RDMA_RAMROD_REGISTER_MR, 196 RDMA_RAMROD_DEREGISTER_MR, 197 RDMA_RAMROD_CREATE_CQ, 198 RDMA_RAMROD_RESIZE_CQ, 199 RDMA_RAMROD_DESTROY_CQ, 200 RDMA_RAMROD_CREATE_SRQ, 201 RDMA_RAMROD_MODIFY_SRQ, 202 RDMA_RAMROD_DESTROY_SRQ, 203 MAX_RDMA_RAMROD_CMD_ID 204 }; 205 206 207 /* 208 * rdma register tid ramrod data 209 */ 210 struct rdma_register_tid_ramrod_data 211 { 212 __le32 flags; 213 #define RDMA_REGISTER_TID_RAMROD_DATA_MAX_ID_MASK 0x3FFFF 214 #define RDMA_REGISTER_TID_RAMROD_DATA_MAX_ID_SHIFT 0 215 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK 0x1F 216 #define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT 18 217 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK 0x1 218 #define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT 23 219 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK 0x1 220 #define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT 24 221 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK 0x1 222 #define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT 25 223 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK 0x1 224 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT 26 225 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK 0x1 226 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT 27 227 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK 0x1 228 #define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT 28 229 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK 0x1 230 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT 29 231 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK 0x1 232 #define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT 30 233 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK 0x1 234 #define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT 31 235 u8 flags1; 236 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK 0x1F 237 #define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT 0 238 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK 0x7 239 #define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT 5 240 u8 flags2; 241 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK 0x1 /* Bit indicating that this MR is DMA_MR meaning SGEs that use it have the physical address on them */ 242 #define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT 0 243 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK 0x1 /* Bit indicating that this MR has DIF protection enabled. */ 244 #define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT 1 245 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK 0x3F 246 #define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT 2 247 u8 key; 248 u8 length_hi; 249 u8 vf_id /* This field should be assigned to Virtual Function ID if vf_valid == 1. Otherwise its dont care */; 250 u8 vf_valid; 251 __le16 pd; 252 __le32 length_lo /* lower 32 bits of the registered MR length. */; 253 __le32 itid; 254 __le32 reserved2; 255 struct regpair va; 256 struct regpair pbl_base; 257 struct regpair dif_error_addr /* DIF TX IO writes error information to this location when memory region is invalidated. */; 258 struct regpair dif_runt_addr /* DIF RX IO writes runt value to this location when last RDMA Read of the IO has completed. */; 259 __le32 reserved3[2]; 260 }; 261 262 263 /* 264 * rdma resize cq output params 265 */ 266 struct rdma_resize_cq_output_params 267 { 268 __le32 old_cq_cons /* cq consumer value on old PBL */; 269 __le32 old_cq_prod /* cq producer value on old PBL */; 270 }; 271 272 273 /* 274 * rdma resize cq ramrod data 275 */ 276 struct rdma_resize_cq_ramrod_data 277 { 278 u8 flags; 279 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK 0x1 280 #define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT 0 281 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK 0x1 282 #define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT 1 283 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK 0x3F 284 #define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT 2 285 u8 pbl_log_page_size; 286 __le16 pbl_num_pages; 287 __le32 max_cqes; 288 struct regpair pbl_addr; 289 struct regpair output_params_addr; 290 }; 291 292 293 /* 294 * The rdma storm context of Mstorm 295 */ 296 struct rdma_srq_context 297 { 298 struct regpair temp[8]; 299 }; 300 301 302 /* 303 * rdma create qp requester ramrod data 304 */ 305 struct rdma_srq_create_ramrod_data 306 { 307 struct regpair pbl_base_addr /* SRQ PBL base address */; 308 __le16 pages_in_srq_pbl /* Number of pages in PBL */; 309 __le16 pd_id; 310 struct rdma_srq_id srq_id /* SRQ Index */; 311 __le16 page_size /* Page size in SGEs(16 bytes) elements. Supports up to 2M bytes page size */; 312 __le16 reserved1; 313 __le32 reserved2; 314 struct regpair producers_addr /* SRQ PBL base address */; 315 }; 316 317 318 /* 319 * rdma create qp requester ramrod data 320 */ 321 struct rdma_srq_destroy_ramrod_data 322 { 323 struct rdma_srq_id srq_id /* SRQ Index */; 324 __le32 reserved; 325 }; 326 327 328 /* 329 * rdma create qp requester ramrod data 330 */ 331 struct rdma_srq_modify_ramrod_data 332 { 333 struct rdma_srq_id srq_id /* SRQ Index */; 334 __le32 wqe_limit; 335 }; 336 337 338 /* 339 * The rdma task context of Mstorm 340 */ 341 struct ystorm_rdma_task_st_ctx 342 { 343 struct regpair temp[4]; 344 }; 345 346 struct e4_ystorm_rdma_task_ag_ctx 347 { 348 u8 reserved /* cdu_validation */; 349 u8 byte1 /* state */; 350 __le16 msem_ctx_upd_seq /* icid */; 351 u8 flags0; 352 #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 353 #define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 354 #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 355 #define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 356 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 357 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 358 #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1 /* bit2 */ 359 #define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT 6 360 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 361 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 362 u8 flags1; 363 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */ 364 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0 365 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 366 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2 367 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 /* cf2special */ 368 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT 4 369 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 370 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6 371 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 372 #define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7 373 u8 flags2; 374 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 375 #define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0 376 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 377 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1 378 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 379 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2 380 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 381 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3 382 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 383 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4 384 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 385 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5 386 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 387 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6 388 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 389 #define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7 390 u8 key /* byte2 */; 391 __le32 mw_cnt /* reg0 */; 392 u8 ref_cnt_seq /* byte3 */; 393 u8 ctx_upd_seq /* byte4 */; 394 __le16 dif_flags /* word1 */; 395 __le16 tx_ref_count /* word2 */; 396 __le16 last_used_ltid /* word3 */; 397 __le16 parent_mr_lo /* word4 */; 398 __le16 parent_mr_hi /* word5 */; 399 __le32 fbo_lo /* reg1 */; 400 __le32 fbo_hi /* reg2 */; 401 }; 402 403 struct e4_mstorm_rdma_task_ag_ctx 404 { 405 u8 reserved /* cdu_validation */; 406 u8 byte1 /* state */; 407 __le16 icid /* icid */; 408 u8 flags0; 409 #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 410 #define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 411 #define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 412 #define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 413 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 414 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 415 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 416 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6 417 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 418 #define E4_MSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 419 u8 flags1; 420 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */ 421 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0 422 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 423 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2 424 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 /* cf2 */ 425 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 4 426 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 427 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6 428 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 429 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7 430 u8 flags2; 431 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 432 #define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0 433 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 434 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1 435 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 436 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2 437 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 438 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3 439 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 440 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4 441 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 442 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5 443 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 444 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6 445 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 446 #define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7 447 u8 key /* byte2 */; 448 __le32 mw_cnt /* reg0 */; 449 u8 ref_cnt_seq /* byte3 */; 450 u8 ctx_upd_seq /* byte4 */; 451 __le16 dif_flags /* word1 */; 452 __le16 tx_ref_count /* word2 */; 453 __le16 last_used_ltid /* word3 */; 454 __le16 parent_mr_lo /* word4 */; 455 __le16 parent_mr_hi /* word5 */; 456 __le32 fbo_lo /* reg1 */; 457 __le32 fbo_hi /* reg2 */; 458 }; 459 460 /* 461 * The roce task context of Ustorm 462 */ 463 struct ustorm_rdma_task_st_ctx 464 { 465 struct regpair temp[2]; 466 }; 467 468 struct e4_ustorm_rdma_task_ag_ctx 469 { 470 u8 reserved /* cdu_validation */; 471 u8 byte1 /* state */; 472 __le16 icid /* icid */; 473 u8 flags0; 474 #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 475 #define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 476 #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 477 #define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 478 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK 0x1 /* exist_in_qm1 */ 479 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT 5 480 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3 /* timer0cf */ 481 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6 482 u8 flags1; 483 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3 /* timer1cf */ 484 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0 485 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3 /* timer2cf */ 486 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT 2 487 #define E4_USTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 488 #define E4_USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 4 489 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3 /* cf4 */ 490 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6 491 u8 flags2; 492 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1 /* cf0en */ 493 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0 494 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1 /* cf1en */ 495 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT 1 496 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1 /* cf2en */ 497 #define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT 2 498 #define E4_USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 499 #define E4_USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 3 500 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 /* cf4en */ 501 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4 502 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 503 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 5 504 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 505 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 6 506 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 507 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7 508 u8 flags3; 509 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 510 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 0 511 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 512 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1 513 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 514 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 2 515 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 516 #define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3 517 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF /* nibble1 */ 518 #define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4 519 __le32 dif_err_intervals /* reg0 */; 520 __le32 dif_error_1st_interval /* reg1 */; 521 __le32 reg2 /* reg2 */; 522 __le32 dif_runt_value /* reg3 */; 523 __le32 reg4 /* reg4 */; 524 __le32 reg5 /* reg5 */; 525 }; 526 527 /* 528 * RDMA task context 529 */ 530 struct rdma_task_context 531 { 532 struct ystorm_rdma_task_st_ctx ystorm_st_context /* ystorm storm context */; 533 struct e4_ystorm_rdma_task_ag_ctx ystorm_ag_context /* ystorm aggregative context */; 534 struct tdif_task_context tdif_context /* tdif context */; 535 struct e4_mstorm_rdma_task_ag_ctx mstorm_ag_context /* mstorm aggregative context */; 536 struct mstorm_rdma_task_st_ctx mstorm_st_context /* mstorm storm context */; 537 struct rdif_task_context rdif_context /* rdif context */; 538 struct ustorm_rdma_task_st_ctx ustorm_st_context /* ustorm storm context */; 539 struct regpair ustorm_st_padding[2] /* padding */; 540 struct e4_ustorm_rdma_task_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 541 }; 542 543 544 /* 545 * RDMA Tid type enumeration (for register_tid ramrod) 546 */ 547 enum rdma_tid_type 548 { 549 RDMA_TID_REGISTERED_MR, 550 RDMA_TID_FMR, 551 RDMA_TID_MW_TYPE1, 552 RDMA_TID_MW_TYPE2A, 553 MAX_RDMA_TID_TYPE 554 }; 555 556 557 558 559 struct E4XstormRoceConnAgCtxDqExtLdPart 560 { 561 u8 reserved0 /* cdu_validation */; 562 u8 state /* state */; 563 u8 flags0; 564 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 565 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0 566 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK 0x1 /* exist_in_qm1 */ 567 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT 1 568 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK 0x1 /* exist_in_qm2 */ 569 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT 2 570 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 571 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3 572 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK 0x1 /* bit4 */ 573 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT 4 574 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK 0x1 /* cf_array_active */ 575 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT 5 576 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK 0x1 /* bit6 */ 577 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT 6 578 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK 0x1 /* bit7 */ 579 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT 7 580 u8 flags1; 581 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK 0x1 /* bit8 */ 582 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT 0 583 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK 0x1 /* bit9 */ 584 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT 1 585 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1 /* bit10 */ 586 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2 587 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 /* bit11 */ 588 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3 589 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK 0x1 /* bit12 */ 590 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT 4 591 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_MASK 0x1 /* bit13 */ 592 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_SHIFT 5 593 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK 0x1 /* bit14 */ 594 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT 6 595 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1 /* bit15 */ 596 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7 597 u8 flags2; 598 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3 /* timer0cf */ 599 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0 600 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3 /* timer1cf */ 601 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT 2 602 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3 /* timer2cf */ 603 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT 4 604 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3 /* timer_stop_all */ 605 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT 6 606 u8 flags3; 607 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK 0x3 /* cf4 */ 608 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT 0 609 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK 0x3 /* cf5 */ 610 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT 2 611 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK 0x3 /* cf6 */ 612 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT 4 613 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3 /* cf7 */ 614 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT 6 615 u8 flags4; 616 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3 /* cf8 */ 617 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0 618 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3 /* cf9 */ 619 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT 2 620 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3 /* cf10 */ 621 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT 4 622 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3 /* cf11 */ 623 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT 6 624 u8 flags5; 625 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3 /* cf12 */ 626 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0 627 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3 /* cf13 */ 628 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT 2 629 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK 0x3 /* cf14 */ 630 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT 4 631 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3 /* cf15 */ 632 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT 6 633 u8 flags6; 634 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3 /* cf16 */ 635 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0 636 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3 /* cf_array_cf */ 637 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT 2 638 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3 /* cf18 */ 639 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT 4 640 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3 /* cf19 */ 641 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT 6 642 u8 flags7; 643 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3 /* cf20 */ 644 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0 645 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3 /* cf21 */ 646 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT 2 647 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 /* cf22 */ 648 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4 649 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 /* cf0en */ 650 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6 651 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 /* cf1en */ 652 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7 653 u8 flags8; 654 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 /* cf2en */ 655 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0 656 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 /* cf3en */ 657 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1 658 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1 /* cf4en */ 659 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2 660 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1 /* cf5en */ 661 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3 662 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1 /* cf6en */ 663 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4 664 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */ 665 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT 5 666 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 /* cf8en */ 667 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6 668 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 /* cf9en */ 669 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7 670 u8 flags9; 671 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 /* cf10en */ 672 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0 673 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 /* cf11en */ 674 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1 675 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 /* cf12en */ 676 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2 677 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 /* cf13en */ 678 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3 679 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1 /* cf14en */ 680 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4 681 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 /* cf15en */ 682 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5 683 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1 /* cf16en */ 684 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT 6 685 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1 /* cf_array_cf_en */ 686 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT 7 687 u8 flags10; 688 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1 /* cf18en */ 689 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0 690 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1 /* cf19en */ 691 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT 1 692 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1 /* cf20en */ 693 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT 2 694 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1 /* cf21en */ 695 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT 3 696 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 697 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4 698 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1 /* cf23en */ 699 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT 5 700 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1 /* rule0en */ 701 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT 6 702 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1 /* rule1en */ 703 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT 7 704 u8 flags11; 705 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1 /* rule2en */ 706 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0 707 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1 /* rule3en */ 708 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT 1 709 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1 /* rule4en */ 710 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT 2 711 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 /* rule5en */ 712 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3 713 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 /* rule6en */ 714 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4 715 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1 /* rule7en */ 716 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5 717 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 /* rule8en */ 718 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6 719 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 /* rule9en */ 720 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7 721 u8 flags12; 722 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1 /* rule10en */ 723 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0 724 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 /* rule11en */ 725 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1 726 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 /* rule12en */ 727 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2 728 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 /* rule13en */ 729 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3 730 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1 /* rule14en */ 731 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4 732 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 /* rule15en */ 733 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5 734 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1 /* rule16en */ 735 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6 736 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1 /* rule17en */ 737 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7 738 u8 flags13; 739 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 /* rule18en */ 740 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0 741 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 /* rule19en */ 742 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1 743 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 /* rule20en */ 744 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2 745 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 /* rule21en */ 746 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3 747 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 /* rule22en */ 748 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4 749 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 /* rule23en */ 750 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5 751 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 /* rule24en */ 752 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6 753 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 /* rule25en */ 754 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7 755 u8 flags14; 756 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK 0x1 /* bit16 */ 757 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT 0 758 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1 /* bit17 */ 759 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT 1 760 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3 /* bit18 */ 761 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT 2 762 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1 /* bit20 */ 763 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT 4 764 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 765 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5 766 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3 /* cf23 */ 767 #define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT 6 768 u8 byte2 /* byte2 */; 769 __le16 physical_q0 /* physical_q0 */; 770 __le16 word1 /* physical_q1 */; 771 __le16 word2 /* physical_q2 */; 772 __le16 word3 /* word3 */; 773 __le16 word4 /* word4 */; 774 __le16 word5 /* word5 */; 775 __le16 conn_dpi /* conn_dpi */; 776 u8 byte3 /* byte3 */; 777 u8 byte4 /* byte4 */; 778 u8 byte5 /* byte5 */; 779 u8 byte6 /* byte6 */; 780 __le32 reg0 /* reg0 */; 781 __le32 reg1 /* reg1 */; 782 __le32 reg2 /* reg2 */; 783 __le32 snd_nxt_psn /* reg3 */; 784 __le32 reg4 /* reg4 */; 785 }; 786 787 788 struct e4_mstorm_rdma_conn_ag_ctx 789 { 790 u8 byte0 /* cdu_validation */; 791 u8 byte1 /* state */; 792 u8 flags0; 793 #define E4_MSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 794 #define E4_MSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0 795 #define E4_MSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 796 #define E4_MSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 797 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 798 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2 799 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 800 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 801 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 802 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 803 u8 flags1; 804 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 805 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0 806 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 807 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 808 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 809 #define E4_MSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 810 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 811 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3 812 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 813 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4 814 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 815 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5 816 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 817 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6 818 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 819 #define E4_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7 820 __le16 word0 /* word0 */; 821 __le16 word1 /* word1 */; 822 __le32 reg0 /* reg0 */; 823 __le32 reg1 /* reg1 */; 824 }; 825 826 827 828 struct e4_tstorm_rdma_conn_ag_ctx 829 { 830 u8 reserved0 /* cdu_validation */; 831 u8 byte1 /* state */; 832 u8 flags0; 833 #define E4_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 834 #define E4_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 835 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 836 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 837 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 838 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2 839 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 840 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT3_SHIFT 3 841 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 842 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4 843 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 844 #define E4_TSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5 845 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 846 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 6 847 u8 flags1; 848 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 849 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 0 850 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 851 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 2 852 #define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 /* timer_stop_all */ 853 #define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 854 #define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf4 */ 855 #define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 856 u8 flags2; 857 #define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 /* cf5 */ 858 #define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 859 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 860 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 2 861 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 862 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF7_SHIFT 4 863 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 864 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 6 865 u8 flags3; 866 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 867 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 0 868 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 869 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 2 870 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 871 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 4 872 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 873 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 5 874 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 875 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 6 876 #define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 /* cf3en */ 877 #define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 878 u8 flags4; 879 #define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf4en */ 880 #define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 881 #define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 /* cf5en */ 882 #define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 883 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 884 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 2 885 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 886 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF7EN_SHIFT 3 887 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 888 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 4 889 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 890 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 5 891 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 892 #define E4_TSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 6 893 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 894 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 7 895 u8 flags5; 896 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 897 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 0 898 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 899 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1 900 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 901 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2 902 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 903 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3 904 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 905 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4 906 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 907 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5 908 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 909 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6 910 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 911 #define E4_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7 912 __le32 reg0 /* reg0 */; 913 __le32 reg1 /* reg1 */; 914 __le32 reg2 /* reg2 */; 915 __le32 reg3 /* reg3 */; 916 __le32 reg4 /* reg4 */; 917 __le32 reg5 /* reg5 */; 918 __le32 reg6 /* reg6 */; 919 __le32 reg7 /* reg7 */; 920 __le32 reg8 /* reg8 */; 921 u8 byte2 /* byte2 */; 922 u8 byte3 /* byte3 */; 923 __le16 word0 /* word0 */; 924 u8 byte4 /* byte4 */; 925 u8 byte5 /* byte5 */; 926 __le16 word1 /* word1 */; 927 __le16 word2 /* conn_dpi */; 928 __le16 word3 /* word3 */; 929 __le32 reg9 /* reg9 */; 930 __le32 reg10 /* reg10 */; 931 }; 932 933 934 struct e4_tstorm_rdma_task_ag_ctx 935 { 936 u8 byte0 /* cdu_validation */; 937 u8 byte1 /* state */; 938 __le16 word0 /* icid */; 939 u8 flags0; 940 #define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF /* connection_type */ 941 #define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0 942 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 943 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4 944 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 945 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 946 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 947 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6 948 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 949 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 950 u8 flags1; 951 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 952 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0 953 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 954 #define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1 955 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 956 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2 957 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 958 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4 959 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 960 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6 961 u8 flags2; 962 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 963 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0 964 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3 /* cf4 */ 965 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2 966 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3 /* cf5 */ 967 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4 968 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3 /* cf6 */ 969 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6 970 u8 flags3; 971 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3 /* cf7 */ 972 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0 973 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 974 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2 975 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 976 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3 977 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 978 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4 979 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 980 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5 981 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 982 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6 983 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 984 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7 985 u8 flags4; 986 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 987 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0 988 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 989 #define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1 990 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 991 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2 992 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 993 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3 994 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 995 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4 996 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 997 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5 998 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 999 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6 1000 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1001 #define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7 1002 u8 byte2 /* byte2 */; 1003 __le16 word1 /* word1 */; 1004 __le32 reg0 /* reg0 */; 1005 u8 byte3 /* byte3 */; 1006 u8 byte4 /* byte4 */; 1007 __le16 word2 /* word2 */; 1008 __le16 word3 /* word3 */; 1009 __le16 word4 /* word4 */; 1010 __le32 reg1 /* reg1 */; 1011 __le32 reg2 /* reg2 */; 1012 }; 1013 1014 1015 struct e4_ustorm_rdma_conn_ag_ctx 1016 { 1017 u8 reserved /* cdu_validation */; 1018 u8 byte1 /* state */; 1019 u8 flags0; 1020 #define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1021 #define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1022 #define E4_USTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1023 #define E4_USTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 1024 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* timer0cf */ 1025 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2 1026 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1027 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 1028 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1029 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 1030 u8 flags1; 1031 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1032 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0 1033 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 /* cf4 */ 1034 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2 1035 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 /* cf5 */ 1036 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4 1037 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1038 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6 1039 u8 flags2; 1040 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf0en */ 1041 #define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 1042 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1043 #define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 1044 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1045 #define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 1046 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1047 #define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3 1048 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 /* cf4en */ 1049 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4 1050 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 /* cf5en */ 1051 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5 1052 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1053 #define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6 1054 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 /* rule0en */ 1055 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7 1056 u8 flags3; 1057 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1 /* rule1en */ 1058 #define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0 1059 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1060 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1 1061 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1062 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2 1063 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1064 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3 1065 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1066 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4 1067 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1068 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5 1069 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1070 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6 1071 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1072 #define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7 1073 u8 byte2 /* byte2 */; 1074 u8 byte3 /* byte3 */; 1075 __le16 conn_dpi /* conn_dpi */; 1076 __le16 word1 /* word1 */; 1077 __le32 cq_cons /* reg0 */; 1078 __le32 cq_se_prod /* reg1 */; 1079 __le32 cq_prod /* reg2 */; 1080 __le32 reg3 /* reg3 */; 1081 __le16 int_timeout /* word2 */; 1082 __le16 word3 /* word3 */; 1083 }; 1084 1085 1086 1087 struct e4_xstorm_rdma_conn_ag_ctx 1088 { 1089 u8 reserved0 /* cdu_validation */; 1090 u8 state /* state */; 1091 u8 flags0; 1092 #define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1093 #define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1094 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1095 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 1096 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1 /* exist_in_qm2 */ 1097 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2 1098 #define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 1099 #define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 1100 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 1101 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4 1102 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1 /* cf_array_active */ 1103 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5 1104 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT6_MASK 0x1 /* bit6 */ 1105 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT6_SHIFT 6 1106 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT7_MASK 0x1 /* bit7 */ 1107 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT7_SHIFT 7 1108 u8 flags1; 1109 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT8_MASK 0x1 /* bit8 */ 1110 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT8_SHIFT 0 1111 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT9_MASK 0x1 /* bit9 */ 1112 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT9_SHIFT 1 1113 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */ 1114 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT10_SHIFT 2 1115 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 1116 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT11_SHIFT 3 1117 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 1118 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT12_SHIFT 4 1119 #define E4_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit13 */ 1120 #define E4_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 5 1121 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT14_MASK 0x1 /* bit14 */ 1122 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT14_SHIFT 6 1123 #define E4_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 /* bit15 */ 1124 #define E4_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 1125 u8 flags2; 1126 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1127 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 0 1128 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1129 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 2 1130 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1131 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 4 1132 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1133 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 6 1134 u8 flags3; 1135 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 1136 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF4_SHIFT 0 1137 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 1138 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF5_SHIFT 2 1139 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1140 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 4 1141 #define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf7 */ 1142 #define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 1143 u8 flags4; 1144 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1145 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 0 1146 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 1147 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 2 1148 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1149 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 4 1150 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 1151 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF11_SHIFT 6 1152 u8 flags5; 1153 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 1154 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF12_SHIFT 0 1155 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 1156 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF13_SHIFT 2 1157 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 1158 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF14_SHIFT 4 1159 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 1160 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF15_SHIFT 6 1161 u8 flags6; 1162 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */ 1163 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF16_SHIFT 0 1164 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 1165 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF17_SHIFT 2 1166 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 1167 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF18_SHIFT 4 1168 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF19_MASK 0x3 /* cf19 */ 1169 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF19_SHIFT 6 1170 u8 flags7; 1171 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF20_MASK 0x3 /* cf20 */ 1172 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF20_SHIFT 0 1173 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF21_MASK 0x3 /* cf21 */ 1174 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF21_SHIFT 2 1175 #define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 1176 #define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_SHIFT 4 1177 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1178 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 6 1179 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1180 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 7 1181 u8 flags8; 1182 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1183 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 0 1184 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1185 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 1 1186 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 1187 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF4EN_SHIFT 2 1188 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 1189 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF5EN_SHIFT 3 1190 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1191 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 4 1192 #define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */ 1193 #define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 1194 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1195 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 6 1196 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1197 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 7 1198 u8 flags9; 1199 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1200 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 0 1201 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 1202 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF11EN_SHIFT 1 1203 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 1204 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF12EN_SHIFT 2 1205 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 1206 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF13EN_SHIFT 3 1207 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 1208 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF14EN_SHIFT 4 1209 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 1210 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF15EN_SHIFT 5 1211 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */ 1212 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF16EN_SHIFT 6 1213 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 1214 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF17EN_SHIFT 7 1215 u8 flags10; 1216 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 1217 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF18EN_SHIFT 0 1218 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF19EN_MASK 0x1 /* cf19en */ 1219 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF19EN_SHIFT 1 1220 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF20EN_MASK 0x1 /* cf20en */ 1221 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF20EN_SHIFT 2 1222 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF21EN_MASK 0x1 /* cf21en */ 1223 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF21EN_SHIFT 3 1224 #define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 1225 #define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 1226 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 1227 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF23EN_SHIFT 5 1228 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1229 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 6 1230 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1231 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 7 1232 u8 flags11; 1233 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1234 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 0 1235 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1236 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 1 1237 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1238 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 2 1239 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1240 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 3 1241 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1242 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 4 1243 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1244 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 5 1245 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 1246 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 1247 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 1248 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_SHIFT 7 1249 u8 flags12; 1250 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 1251 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_SHIFT 0 1252 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 1253 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_SHIFT 1 1254 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 1255 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 1256 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 1257 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 1258 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 1259 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_SHIFT 4 1260 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 1261 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_SHIFT 5 1262 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 1263 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_SHIFT 6 1264 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 1265 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_SHIFT 7 1266 u8 flags13; 1267 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 1268 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_SHIFT 0 1269 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 1270 #define E4_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_SHIFT 1 1271 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 1272 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 1273 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 1274 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 1275 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 1276 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 1277 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 1278 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 1279 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 1280 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 1281 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 1282 #define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 1283 u8 flags14; 1284 #define E4_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_MASK 0x1 /* bit16 */ 1285 #define E4_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_SHIFT 0 1286 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 1287 #define E4_XSTORM_RDMA_CONN_AG_CTX_BIT17_SHIFT 1 1288 #define E4_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 /* bit18 */ 1289 #define E4_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 1290 #define E4_XSTORM_RDMA_CONN_AG_CTX_RESERVED_MASK 0x1 /* bit20 */ 1291 #define E4_XSTORM_RDMA_CONN_AG_CTX_RESERVED_SHIFT 4 1292 #define E4_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 1293 #define E4_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 1294 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 1295 #define E4_XSTORM_RDMA_CONN_AG_CTX_CF23_SHIFT 6 1296 u8 byte2 /* byte2 */; 1297 __le16 physical_q0 /* physical_q0 */; 1298 __le16 word1 /* physical_q1 */; 1299 __le16 word2 /* physical_q2 */; 1300 __le16 word3 /* word3 */; 1301 __le16 word4 /* word4 */; 1302 __le16 word5 /* word5 */; 1303 __le16 conn_dpi /* conn_dpi */; 1304 u8 byte3 /* byte3 */; 1305 u8 byte4 /* byte4 */; 1306 u8 byte5 /* byte5 */; 1307 u8 byte6 /* byte6 */; 1308 __le32 reg0 /* reg0 */; 1309 __le32 reg1 /* reg1 */; 1310 __le32 reg2 /* reg2 */; 1311 __le32 snd_nxt_psn /* reg3 */; 1312 __le32 reg4 /* reg4 */; 1313 __le32 reg5 /* cf_array0 */; 1314 __le32 reg6 /* cf_array1 */; 1315 }; 1316 1317 1318 struct e4_ystorm_rdma_conn_ag_ctx 1319 { 1320 u8 byte0 /* cdu_validation */; 1321 u8 byte1 /* state */; 1322 u8 flags0; 1323 #define E4_YSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1324 #define E4_YSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0 1325 #define E4_YSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1326 #define E4_YSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 1327 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1328 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2 1329 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1330 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 1331 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1332 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 1333 u8 flags1; 1334 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1335 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0 1336 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1337 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 1338 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1339 #define E4_YSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 1340 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1341 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3 1342 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1343 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4 1344 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1345 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5 1346 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1347 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6 1348 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1349 #define E4_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7 1350 u8 byte2 /* byte2 */; 1351 u8 byte3 /* byte3 */; 1352 __le16 word0 /* word0 */; 1353 __le32 reg0 /* reg0 */; 1354 __le32 reg1 /* reg1 */; 1355 __le16 word1 /* word1 */; 1356 __le16 word2 /* word2 */; 1357 __le16 word3 /* word3 */; 1358 __le16 word4 /* word4 */; 1359 __le32 reg2 /* reg2 */; 1360 __le32 reg3 /* reg3 */; 1361 }; 1362 1363 1364 1365 struct e5_mstorm_rdma_conn_ag_ctx 1366 { 1367 u8 byte0 /* cdu_validation */; 1368 u8 byte1 /* state_and_core_id */; 1369 u8 flags0; 1370 #define E5_MSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1371 #define E5_MSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0 1372 #define E5_MSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1373 #define E5_MSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 1374 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1375 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2 1376 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1377 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 1378 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1379 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 1380 u8 flags1; 1381 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1382 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0 1383 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1384 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 1385 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1386 #define E5_MSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 1387 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1388 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3 1389 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1390 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4 1391 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1392 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5 1393 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1394 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6 1395 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1396 #define E5_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7 1397 __le16 word0 /* word0 */; 1398 __le16 word1 /* word1 */; 1399 __le32 reg0 /* reg0 */; 1400 __le32 reg1 /* reg1 */; 1401 }; 1402 1403 1404 struct e5_mstorm_rdma_task_ag_ctx 1405 { 1406 u8 reserved /* cdu_validation */; 1407 u8 byte1 /* state_and_core_id */; 1408 __le16 icid /* icid */; 1409 u8 flags0; 1410 #define E5_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 1411 #define E5_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 1412 #define E5_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1413 #define E5_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 1414 #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1415 #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 1416 #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 1417 #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6 1418 #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 1419 #define E5_MSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 1420 u8 flags1; 1421 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1422 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0 1423 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1424 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2 1425 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1426 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 4 1427 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1428 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6 1429 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1430 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7 1431 u8 flags2; 1432 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1433 #define E5_MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0 1434 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1435 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1 1436 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1437 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2 1438 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1439 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3 1440 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1441 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4 1442 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1443 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5 1444 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1445 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6 1446 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1447 #define E5_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7 1448 u8 flags3; 1449 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit4 */ 1450 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_SHIFT 0 1451 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_MASK 0x3 /* cf3 */ 1452 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_SHIFT 1 1453 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf4 */ 1454 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_SHIFT 3 1455 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_MASK 0x1 /* cf3en */ 1456 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_SHIFT 5 1457 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf4en */ 1458 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_SHIFT 6 1459 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule7en */ 1460 #define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_SHIFT 7 1461 __le32 mw_cnt /* reg0 */; 1462 u8 key /* byte2 */; 1463 u8 ref_cnt_seq /* byte3 */; 1464 u8 ctx_upd_seq /* byte4 */; 1465 u8 e4_reserved7 /* byte5 */; 1466 __le16 dif_flags /* regpair0 */; 1467 __le16 tx_ref_count /* word2 */; 1468 __le16 last_used_ltid /* word3 */; 1469 __le16 parent_mr_lo /* word4 */; 1470 __le16 parent_mr_hi /* regpair1 */; 1471 __le16 e4_reserved8 /* word6 */; 1472 __le32 fbo_lo /* reg1 */; 1473 }; 1474 1475 1476 struct e5_tstorm_rdma_conn_ag_ctx 1477 { 1478 u8 reserved0 /* cdu_validation */; 1479 u8 byte1 /* state_and_core_id */; 1480 u8 flags0; 1481 #define E5_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1482 #define E5_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1483 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1484 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 1485 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 1486 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2 1487 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 1488 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT3_SHIFT 3 1489 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 1490 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4 1491 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 1492 #define E5_TSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5 1493 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1494 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 6 1495 u8 flags1; 1496 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1497 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 0 1498 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1499 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 2 1500 #define E5_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 /* timer_stop_all */ 1501 #define E5_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 1502 #define E5_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf4 */ 1503 #define E5_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 1504 u8 flags2; 1505 #define E5_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 /* cf5 */ 1506 #define E5_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 1507 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1508 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 2 1509 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 1510 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF7_SHIFT 4 1511 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1512 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 6 1513 u8 flags3; 1514 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 1515 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 0 1516 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1517 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 2 1518 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1519 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 4 1520 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1521 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 5 1522 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1523 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 6 1524 #define E5_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 /* cf3en */ 1525 #define E5_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 1526 u8 flags4; 1527 #define E5_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf4en */ 1528 #define E5_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 1529 #define E5_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 /* cf5en */ 1530 #define E5_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 1531 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1532 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 2 1533 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 1534 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF7EN_SHIFT 3 1535 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1536 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 4 1537 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1538 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 5 1539 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1540 #define E5_TSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 6 1541 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1542 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 7 1543 u8 flags5; 1544 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1545 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 0 1546 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1547 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1 1548 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1549 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2 1550 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1551 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3 1552 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1553 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4 1554 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1555 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5 1556 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1557 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6 1558 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1559 #define E5_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7 1560 u8 flags6; 1561 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit6 */ 1562 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1563 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit7 */ 1564 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1565 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit8 */ 1566 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1567 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf11 */ 1568 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 1569 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf11en */ 1570 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 1571 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule9en */ 1572 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 1573 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule10en */ 1574 #define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 1575 u8 byte2 /* byte2 */; 1576 __le16 word0 /* word0 */; 1577 __le32 reg0 /* reg0 */; 1578 __le32 reg1 /* reg1 */; 1579 __le32 reg2 /* reg2 */; 1580 __le32 reg3 /* reg3 */; 1581 __le32 reg4 /* reg4 */; 1582 __le32 reg5 /* reg5 */; 1583 __le32 reg6 /* reg6 */; 1584 __le32 reg7 /* reg7 */; 1585 __le32 reg8 /* reg8 */; 1586 u8 byte3 /* byte3 */; 1587 u8 byte4 /* byte4 */; 1588 u8 byte5 /* byte5 */; 1589 u8 e4_reserved8 /* byte6 */; 1590 __le16 word1 /* word1 */; 1591 __le16 word2 /* conn_dpi */; 1592 __le32 reg9 /* reg9 */; 1593 __le16 word3 /* word3 */; 1594 __le16 e4_reserved9 /* word4 */; 1595 }; 1596 1597 1598 struct e5_tstorm_rdma_task_ag_ctx 1599 { 1600 u8 byte0 /* cdu_validation */; 1601 u8 byte1 /* state_and_core_id */; 1602 __le16 word0 /* icid */; 1603 u8 flags0; 1604 #define E5_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF /* connection_type */ 1605 #define E5_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0 1606 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1607 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4 1608 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1609 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 1610 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 1611 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6 1612 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 1613 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 1614 u8 flags1; 1615 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 1616 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0 1617 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 1618 #define E5_TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1 1619 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1620 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2 1621 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1622 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4 1623 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1624 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6 1625 u8 flags2; 1626 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1627 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0 1628 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3 /* cf4 */ 1629 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2 1630 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3 /* cf5 */ 1631 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4 1632 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1633 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6 1634 u8 flags3; 1635 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3 /* cf7 */ 1636 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0 1637 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1638 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2 1639 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1640 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3 1641 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1642 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4 1643 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1644 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5 1645 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 1646 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6 1647 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 1648 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7 1649 u8 flags4; 1650 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1651 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0 1652 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 1653 #define E5_TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1 1654 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1655 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2 1656 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1657 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3 1658 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1659 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4 1660 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1661 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5 1662 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1663 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6 1664 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1665 #define E5_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7 1666 u8 byte2 /* byte2 */; 1667 __le16 word1 /* word1 */; 1668 __le32 reg0 /* reg0 */; 1669 u8 byte3 /* regpair0 */; 1670 u8 byte4 /* byte4 */; 1671 __le16 word2 /* word2 */; 1672 __le16 word3 /* word3 */; 1673 __le16 word4 /* word4 */; 1674 __le32 reg1 /* regpair1 */; 1675 __le32 reg2 /* reg2 */; 1676 }; 1677 1678 1679 struct e5_ustorm_rdma_conn_ag_ctx 1680 { 1681 u8 reserved /* cdu_validation */; 1682 u8 byte1 /* state_and_core_id */; 1683 u8 flags0; 1684 #define E5_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1685 #define E5_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1686 #define E5_USTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1687 #define E5_USTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 1688 #define E5_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* timer0cf */ 1689 #define E5_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2 1690 #define E5_USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1691 #define E5_USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 1692 #define E5_USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1693 #define E5_USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 1694 u8 flags1; 1695 #define E5_USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1696 #define E5_USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0 1697 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 /* cf4 */ 1698 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2 1699 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 /* cf5 */ 1700 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4 1701 #define E5_USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1702 #define E5_USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6 1703 u8 flags2; 1704 #define E5_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf0en */ 1705 #define E5_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 1706 #define E5_USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1707 #define E5_USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 1708 #define E5_USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1709 #define E5_USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 1710 #define E5_USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1711 #define E5_USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3 1712 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 /* cf4en */ 1713 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4 1714 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 /* cf5en */ 1715 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5 1716 #define E5_USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1717 #define E5_USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6 1718 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 /* rule0en */ 1719 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7 1720 u8 flags3; 1721 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1 /* rule1en */ 1722 #define E5_USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0 1723 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1724 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1 1725 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1726 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2 1727 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1728 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3 1729 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1730 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4 1731 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1732 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5 1733 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1734 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6 1735 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1736 #define E5_USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7 1737 u8 flags4; 1738 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 1739 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1740 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 1741 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1742 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf7 */ 1743 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1744 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf8 */ 1745 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED4_SHIFT 4 1746 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf7en */ 1747 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED5_SHIFT 6 1748 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf8en */ 1749 #define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED6_SHIFT 7 1750 u8 byte2 /* byte2 */; 1751 __le16 conn_dpi /* conn_dpi */; 1752 __le16 word1 /* word1 */; 1753 __le32 cq_cons /* reg0 */; 1754 __le32 cq_se_prod /* reg1 */; 1755 __le32 cq_prod /* reg2 */; 1756 __le32 reg3 /* reg3 */; 1757 __le16 int_timeout /* word2 */; 1758 __le16 word3 /* word3 */; 1759 }; 1760 1761 1762 struct e5_ustorm_rdma_task_ag_ctx 1763 { 1764 u8 reserved /* cdu_validation */; 1765 u8 byte1 /* state_and_core_id */; 1766 __le16 icid /* icid */; 1767 u8 flags0; 1768 #define E5_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 1769 #define E5_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 1770 #define E5_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1771 #define E5_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 1772 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK 0x1 /* exist_in_qm1 */ 1773 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT 5 1774 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3 /* timer0cf */ 1775 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6 1776 u8 flags1; 1777 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3 /* timer1cf */ 1778 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0 1779 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3 /* timer2cf */ 1780 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT 2 1781 #define E5_USTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1782 #define E5_USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 4 1783 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3 /* dif_error_cf */ 1784 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6 1785 u8 flags2; 1786 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1 /* cf0en */ 1787 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0 1788 #define E5_USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1 /* cf1en */ 1789 #define E5_USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT 1 1790 #define E5_USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1 /* cf2en */ 1791 #define E5_USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT 2 1792 #define E5_USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1793 #define E5_USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 3 1794 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 /* cf4en */ 1795 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4 1796 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1797 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 5 1798 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1799 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 6 1800 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1801 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7 1802 u8 flags3; 1803 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1804 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 0 1805 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1806 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1 1807 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1808 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 2 1809 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1810 #define E5_USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3 1811 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 1812 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_SHIFT 4 1813 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 1814 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_SHIFT 5 1815 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit4 */ 1816 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_SHIFT 6 1817 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_MASK 0x1 /* rule7en */ 1818 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_SHIFT 7 1819 u8 flags4; 1820 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_MASK 0x3 /* cf5 */ 1821 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_SHIFT 0 1822 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf5en */ 1823 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_SHIFT 2 1824 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule8en */ 1825 #define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED7_SHIFT 3 1826 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF /* dif_error_type */ 1827 #define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4 1828 u8 byte2 /* byte2 */; 1829 u8 byte3 /* byte3 */; 1830 u8 e4_reserved8 /* byte4 */; 1831 __le32 dif_err_intervals /* dif_err_intervals */; 1832 __le32 dif_error_1st_interval /* dif_error_1st_interval */; 1833 __le32 reg2 /* reg2 */; 1834 __le32 dif_runt_value /* reg3 */; 1835 __le32 reg4 /* reg4 */; 1836 }; 1837 1838 1839 struct e5_xstorm_rdma_conn_ag_ctx 1840 { 1841 u8 reserved0 /* cdu_validation */; 1842 u8 state_and_core_id /* state_and_core_id */; 1843 u8 flags0; 1844 #define E5_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1845 #define E5_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1846 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1847 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 1848 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1 /* exist_in_qm2 */ 1849 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2 1850 #define E5_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 1851 #define E5_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 1852 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 1853 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4 1854 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1 /* cf_array_active */ 1855 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5 1856 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT6_MASK 0x1 /* bit6 */ 1857 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT6_SHIFT 6 1858 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT7_MASK 0x1 /* bit7 */ 1859 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT7_SHIFT 7 1860 u8 flags1; 1861 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT8_MASK 0x1 /* bit8 */ 1862 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT8_SHIFT 0 1863 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT9_MASK 0x1 /* bit9 */ 1864 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT9_SHIFT 1 1865 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */ 1866 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT10_SHIFT 2 1867 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 1868 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT11_SHIFT 3 1869 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 1870 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT12_SHIFT 4 1871 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 1872 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT13_SHIFT 5 1873 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT14_MASK 0x1 /* bit14 */ 1874 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT14_SHIFT 6 1875 #define E5_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 /* bit15 */ 1876 #define E5_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 1877 u8 flags2; 1878 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1879 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 0 1880 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1881 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 2 1882 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1883 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 4 1884 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1885 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 6 1886 u8 flags3; 1887 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 1888 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF4_SHIFT 0 1889 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 1890 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF5_SHIFT 2 1891 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1892 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 4 1893 #define E5_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf7 */ 1894 #define E5_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 1895 u8 flags4; 1896 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1897 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 0 1898 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 1899 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 2 1900 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1901 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 4 1902 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 1903 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF11_SHIFT 6 1904 u8 flags5; 1905 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 1906 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF12_SHIFT 0 1907 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 1908 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF13_SHIFT 2 1909 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 1910 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF14_SHIFT 4 1911 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 1912 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF15_SHIFT 6 1913 u8 flags6; 1914 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */ 1915 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF16_SHIFT 0 1916 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 1917 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF17_SHIFT 2 1918 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 1919 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF18_SHIFT 4 1920 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF19_MASK 0x3 /* cf19 */ 1921 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF19_SHIFT 6 1922 u8 flags7; 1923 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF20_MASK 0x3 /* cf20 */ 1924 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF20_SHIFT 0 1925 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF21_MASK 0x3 /* cf21 */ 1926 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF21_SHIFT 2 1927 #define E5_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 1928 #define E5_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_SHIFT 4 1929 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1930 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 6 1931 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1932 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 7 1933 u8 flags8; 1934 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1935 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 0 1936 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1937 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 1 1938 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 1939 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF4EN_SHIFT 2 1940 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 1941 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF5EN_SHIFT 3 1942 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1943 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 4 1944 #define E5_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */ 1945 #define E5_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 1946 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1947 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 6 1948 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1949 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 7 1950 u8 flags9; 1951 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1952 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 0 1953 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 1954 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF11EN_SHIFT 1 1955 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 1956 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF12EN_SHIFT 2 1957 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 1958 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF13EN_SHIFT 3 1959 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 1960 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF14EN_SHIFT 4 1961 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 1962 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF15EN_SHIFT 5 1963 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */ 1964 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF16EN_SHIFT 6 1965 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 1966 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF17EN_SHIFT 7 1967 u8 flags10; 1968 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 1969 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF18EN_SHIFT 0 1970 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF19EN_MASK 0x1 /* cf19en */ 1971 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF19EN_SHIFT 1 1972 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF20EN_MASK 0x1 /* cf20en */ 1973 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF20EN_SHIFT 2 1974 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF21EN_MASK 0x1 /* cf21en */ 1975 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF21EN_SHIFT 3 1976 #define E5_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 1977 #define E5_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 1978 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 1979 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF23EN_SHIFT 5 1980 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1981 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 6 1982 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1983 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 7 1984 u8 flags11; 1985 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1986 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 0 1987 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1988 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 1 1989 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1990 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 2 1991 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1992 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 3 1993 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1994 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 4 1995 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1996 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 5 1997 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 1998 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 1999 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 2000 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_SHIFT 7 2001 u8 flags12; 2002 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 2003 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_SHIFT 0 2004 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 2005 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_SHIFT 1 2006 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 2007 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 2008 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 2009 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 2010 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 2011 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_SHIFT 4 2012 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 2013 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_SHIFT 5 2014 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 2015 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_SHIFT 6 2016 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 2017 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_SHIFT 7 2018 u8 flags13; 2019 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 2020 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_SHIFT 0 2021 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 2022 #define E5_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_SHIFT 1 2023 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 2024 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 2025 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 2026 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 2027 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 2028 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 2029 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 2030 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 2031 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 2032 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 2033 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 2034 #define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 2035 u8 flags14; 2036 #define E5_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_MASK 0x1 /* bit16 */ 2037 #define E5_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_SHIFT 0 2038 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 2039 #define E5_XSTORM_RDMA_CONN_AG_CTX_BIT17_SHIFT 1 2040 #define E5_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 /* bit18 */ 2041 #define E5_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 2042 #define E5_XSTORM_RDMA_CONN_AG_CTX_RESERVED_MASK 0x1 /* bit20 */ 2043 #define E5_XSTORM_RDMA_CONN_AG_CTX_RESERVED_SHIFT 4 2044 #define E5_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 2045 #define E5_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 2046 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 2047 #define E5_XSTORM_RDMA_CONN_AG_CTX_CF23_SHIFT 6 2048 u8 byte2 /* byte2 */; 2049 __le16 physical_q0 /* physical_q0 */; 2050 __le16 word1 /* physical_q1 */; 2051 __le16 word2 /* physical_q2 */; 2052 __le16 word3 /* word3 */; 2053 __le16 word4 /* word4 */; 2054 __le16 word5 /* word5 */; 2055 __le16 conn_dpi /* conn_dpi */; 2056 u8 byte3 /* byte3 */; 2057 u8 byte4 /* byte4 */; 2058 u8 byte5 /* byte5 */; 2059 u8 byte6 /* byte6 */; 2060 __le32 reg0 /* reg0 */; 2061 __le32 reg1 /* reg1 */; 2062 __le32 reg2 /* reg2 */; 2063 __le32 snd_nxt_psn /* reg3 */; 2064 __le32 reg4 /* reg4 */; 2065 __le32 reg5 /* cf_array0 */; 2066 __le32 reg6 /* cf_array1 */; 2067 }; 2068 2069 2070 struct e5_ystorm_rdma_conn_ag_ctx 2071 { 2072 u8 byte0 /* cdu_validation */; 2073 u8 byte1 /* state_and_core_id */; 2074 u8 flags0; 2075 #define E5_YSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 2076 #define E5_YSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0 2077 #define E5_YSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2078 #define E5_YSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 2079 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 2080 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2 2081 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 2082 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 2083 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 2084 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 2085 u8 flags1; 2086 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2087 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0 2088 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2089 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 2090 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2091 #define E5_YSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 2092 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2093 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3 2094 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2095 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4 2096 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2097 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5 2098 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2099 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6 2100 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2101 #define E5_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7 2102 u8 byte2 /* byte2 */; 2103 u8 byte3 /* byte3 */; 2104 __le16 word0 /* word0 */; 2105 __le32 reg0 /* reg0 */; 2106 __le32 reg1 /* reg1 */; 2107 __le16 word1 /* word1 */; 2108 __le16 word2 /* word2 */; 2109 __le16 word3 /* word3 */; 2110 __le16 word4 /* word4 */; 2111 __le32 reg2 /* reg2 */; 2112 __le32 reg3 /* reg3 */; 2113 }; 2114 2115 2116 struct e5_ystorm_rdma_task_ag_ctx 2117 { 2118 u8 reserved /* cdu_validation */; 2119 u8 byte1 /* state_and_core_id */; 2120 __le16 msem_ctx_upd_seq /* icid */; 2121 u8 flags0; 2122 #define E5_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 2123 #define E5_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 2124 #define E5_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 2125 #define E5_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 2126 #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2127 #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 2128 #define E5_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1 /* bit2 */ 2129 #define E5_YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT 6 2130 #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 2131 #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 2132 u8 flags1; 2133 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */ 2134 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0 2135 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 2136 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2 2137 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 /* cf2special */ 2138 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT 4 2139 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2140 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6 2141 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2142 #define E5_YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7 2143 u8 flags2; 2144 #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 2145 #define E5_YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0 2146 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2147 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1 2148 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2149 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2 2150 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2151 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3 2152 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2153 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4 2154 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2155 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5 2156 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2157 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6 2158 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 2159 #define E5_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7 2160 u8 flags3; 2161 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit5 */ 2162 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_SHIFT 0 2163 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_MASK 0x3 /* cf3 */ 2164 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_SHIFT 1 2165 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf4 */ 2166 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_SHIFT 3 2167 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_MASK 0x1 /* cf3en */ 2168 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_SHIFT 5 2169 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf4en */ 2170 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_SHIFT 6 2171 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule7en */ 2172 #define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_SHIFT 7 2173 __le32 mw_cnt /* reg0 */; 2174 u8 key /* byte2 */; 2175 u8 ref_cnt_seq /* byte3 */; 2176 u8 ctx_upd_seq /* byte4 */; 2177 u8 e4_reserved7 /* byte5 */; 2178 __le16 dif_flags /* word1 */; 2179 __le16 tx_ref_count /* word2 */; 2180 __le16 last_used_ltid /* word3 */; 2181 __le16 parent_mr_lo /* word4 */; 2182 __le16 parent_mr_hi /* word5 */; 2183 __le16 e4_reserved8 /* word6 */; 2184 __le32 fbo_lo /* reg1 */; 2185 }; 2186 2187 #endif /* __ECORE_HSI_RDMA__ */ 2188