1*14b24e2bSVaishali Kulkarni /* 2*14b24e2bSVaishali Kulkarni * CDDL HEADER START 3*14b24e2bSVaishali Kulkarni * 4*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the 5*14b24e2bSVaishali Kulkarni * Common Development and Distribution License, v.1, (the "License"). 6*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License. 7*14b24e2bSVaishali Kulkarni * 8*14b24e2bSVaishali Kulkarni * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*14b24e2bSVaishali Kulkarni * or http://opensource.org/licenses/CDDL-1.0. 10*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions 11*14b24e2bSVaishali Kulkarni * and limitations under the License. 12*14b24e2bSVaishali Kulkarni * 13*14b24e2bSVaishali Kulkarni * When distributing Covered Code, include this CDDL HEADER in each 14*14b24e2bSVaishali Kulkarni * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*14b24e2bSVaishali Kulkarni * If applicable, add the following below this CDDL HEADER, with the 16*14b24e2bSVaishali Kulkarni * fields enclosed by brackets "[]" replaced with your own identifying 17*14b24e2bSVaishali Kulkarni * information: Portions Copyright [yyyy] [name of copyright owner] 18*14b24e2bSVaishali Kulkarni * 19*14b24e2bSVaishali Kulkarni * CDDL HEADER END 20*14b24e2bSVaishali Kulkarni */ 21*14b24e2bSVaishali Kulkarni 22*14b24e2bSVaishali Kulkarni /* 23*14b24e2bSVaishali Kulkarni * Copyright 2014-2017 Cavium, Inc. 24*14b24e2bSVaishali Kulkarni * The contents of this file are subject to the terms of the Common Development 25*14b24e2bSVaishali Kulkarni * and Distribution License, v.1, (the "License"). 26*14b24e2bSVaishali Kulkarni 27*14b24e2bSVaishali Kulkarni * You may not use this file except in compliance with the License. 28*14b24e2bSVaishali Kulkarni 29*14b24e2bSVaishali Kulkarni * You can obtain a copy of the License at available 30*14b24e2bSVaishali Kulkarni * at http://opensource.org/licenses/CDDL-1.0 31*14b24e2bSVaishali Kulkarni 32*14b24e2bSVaishali Kulkarni * See the License for the specific language governing permissions and 33*14b24e2bSVaishali Kulkarni * limitations under the License. 34*14b24e2bSVaishali Kulkarni */ 35*14b24e2bSVaishali Kulkarni 36*14b24e2bSVaishali Kulkarni /**************************************************************************** 37*14b24e2bSVaishali Kulkarni * 38*14b24e2bSVaishali Kulkarni * Name: mcp_private.h 39*14b24e2bSVaishali Kulkarni * 40*14b24e2bSVaishali Kulkarni * Description: MCP private data. Located in HSI only to provide debug access 41*14b24e2bSVaishali Kulkarni * for diag. 42*14b24e2bSVaishali Kulkarni * 43*14b24e2bSVaishali Kulkarni ****************************************************************************/ 44*14b24e2bSVaishali Kulkarni 45*14b24e2bSVaishali Kulkarni #ifndef MCP_PRIVATE_H 46*14b24e2bSVaishali Kulkarni #define MCP_PRIVATE_H 47*14b24e2bSVaishali Kulkarni 48*14b24e2bSVaishali Kulkarni #if (!defined MFW_SIM) && (!defined RECOVERY) 49*14b24e2bSVaishali Kulkarni #include "eth.h" 50*14b24e2bSVaishali Kulkarni #include "pmm.h" 51*14b24e2bSVaishali Kulkarni #include "ah_eth.h" 52*14b24e2bSVaishali Kulkarni #endif 53*14b24e2bSVaishali Kulkarni #include "mcp_public.h" 54*14b24e2bSVaishali Kulkarni 55*14b24e2bSVaishali Kulkarni typedef enum active_mf_mode { 56*14b24e2bSVaishali Kulkarni MF_MODE_SF = 0, 57*14b24e2bSVaishali Kulkarni MF_MODE_MF_ALLOWED, 58*14b24e2bSVaishali Kulkarni MF_MODE_MF_SWITCH_INDEPENDENT, 59*14b24e2bSVaishali Kulkarni MF_MODE_NIV 60*14b24e2bSVaishali Kulkarni } active_mf_mode_t; 61*14b24e2bSVaishali Kulkarni 62*14b24e2bSVaishali Kulkarni enum ov_current_cfg { 63*14b24e2bSVaishali Kulkarni CURR_CFG_NONE = 0, 64*14b24e2bSVaishali Kulkarni CURR_CFG_OS, 65*14b24e2bSVaishali Kulkarni CURR_CFG_VENDOR_SPEC, 66*14b24e2bSVaishali Kulkarni CURR_CFG_OTHER, 67*14b24e2bSVaishali Kulkarni CURR_CFG_VC_CLP, 68*14b24e2bSVaishali Kulkarni CURR_CFG_CNU, 69*14b24e2bSVaishali Kulkarni CURR_CFG_DCI, 70*14b24e2bSVaishali Kulkarni CURR_CFG_HII, 71*14b24e2bSVaishali Kulkarni }; 72*14b24e2bSVaishali Kulkarni 73*14b24e2bSVaishali Kulkarni struct dci_info_global { 74*14b24e2bSVaishali Kulkarni enum ov_current_cfg current_cfg; 75*14b24e2bSVaishali Kulkarni u8 pci_bus_num; 76*14b24e2bSVaishali Kulkarni u8 boot_progress; 77*14b24e2bSVaishali Kulkarni }; 78*14b24e2bSVaishali Kulkarni 79*14b24e2bSVaishali Kulkarni /* Resource allocation information of one resource */ 80*14b24e2bSVaishali Kulkarni struct resource_info_private { 81*14b24e2bSVaishali Kulkarni u16 size; /* number of allocated resources */ 82*14b24e2bSVaishali Kulkarni u16 offset; /* Offset of the 1st resource */ 83*14b24e2bSVaishali Kulkarni u8 flags; 84*14b24e2bSVaishali Kulkarni }; 85*14b24e2bSVaishali Kulkarni 86*14b24e2bSVaishali Kulkarni /* Cache for resource allocation of one PF */ 87*14b24e2bSVaishali Kulkarni struct res_alloc_cache { 88*14b24e2bSVaishali Kulkarni u8 pf_num; 89*14b24e2bSVaishali Kulkarni struct resource_info_private res[RESOURCE_MAX_NUM]; 90*14b24e2bSVaishali Kulkarni }; 91*14b24e2bSVaishali Kulkarni 92*14b24e2bSVaishali Kulkarni struct pf_sb_t { 93*14b24e2bSVaishali Kulkarni u8 sb_for_pf_size; 94*14b24e2bSVaishali Kulkarni u8 sb_for_pf_offset; 95*14b24e2bSVaishali Kulkarni u8 sb_for_vf_size; 96*14b24e2bSVaishali Kulkarni u8 sb_for_vf_offset; 97*14b24e2bSVaishali Kulkarni }; 98*14b24e2bSVaishali Kulkarni 99*14b24e2bSVaishali Kulkarni /**************************************/ 100*14b24e2bSVaishali Kulkarni /* */ 101*14b24e2bSVaishali Kulkarni /* P R I V A T E G L O B A L */ 102*14b24e2bSVaishali Kulkarni /* */ 103*14b24e2bSVaishali Kulkarni /**************************************/ 104*14b24e2bSVaishali Kulkarni struct private_global { 105*14b24e2bSVaishali Kulkarni active_mf_mode_t mf_mode; /* TBD - require initialization */ 106*14b24e2bSVaishali Kulkarni u32 exp_rom_nvm_addr; 107*14b24e2bSVaishali Kulkarni 108*14b24e2bSVaishali Kulkarni /* The pmm_config structure holds all active phy/link configuration */ 109*14b24e2bSVaishali Kulkarni #ifndef RECOVERY 110*14b24e2bSVaishali Kulkarni #ifdef b900 111*14b24e2bSVaishali Kulkarni struct pmm_config eth_cfg; 112*14b24e2bSVaishali Kulkarni #else 113*14b24e2bSVaishali Kulkarni struct ah_eth eth_cfg; 114*14b24e2bSVaishali Kulkarni #endif 115*14b24e2bSVaishali Kulkarni #endif 116*14b24e2bSVaishali Kulkarni 117*14b24e2bSVaishali Kulkarni u32 lldp_counter; 118*14b24e2bSVaishali Kulkarni 119*14b24e2bSVaishali Kulkarni u32 avs_init_timestamp; 120*14b24e2bSVaishali Kulkarni 121*14b24e2bSVaishali Kulkarni u32 seconds_since_mcp_reset; 122*14b24e2bSVaishali Kulkarni 123*14b24e2bSVaishali Kulkarni u32 last_malloc_dir_used_timestamp; 124*14b24e2bSVaishali Kulkarni #define MAX_USED_DIR_ALLOWED_TIME (3) /* Seconds */ 125*14b24e2bSVaishali Kulkarni 126*14b24e2bSVaishali Kulkarni u32 drv_nvm_state; 127*14b24e2bSVaishali Kulkarni /* Per PF bitmask */ 128*14b24e2bSVaishali Kulkarni #define DRV_NVM_STATE_IN_PROGRESS_MASK (0x0000ffff) 129*14b24e2bSVaishali Kulkarni #define DRV_NVM_STATE_IN_PROGRESS_OFFSET (0) 130*14b24e2bSVaishali Kulkarni 131*14b24e2bSVaishali Kulkarni u32 storm_fw_ver; 132*14b24e2bSVaishali Kulkarni 133*14b24e2bSVaishali Kulkarni /* OneView data*/ 134*14b24e2bSVaishali Kulkarni struct dci_info_global dci_global; 135*14b24e2bSVaishali Kulkarni 136*14b24e2bSVaishali Kulkarni /* Resource allocation cached data */ 137*14b24e2bSVaishali Kulkarni struct res_alloc_cache res_alloc; 138*14b24e2bSVaishali Kulkarni #define G_RES_ALLOC_P (&g_spad.private_data.global.res_alloc) 139*14b24e2bSVaishali Kulkarni u32 resource_max_values[RESOURCE_MAX_NUM]; 140*14b24e2bSVaishali Kulkarni }; 141*14b24e2bSVaishali Kulkarni 142*14b24e2bSVaishali Kulkarni /**************************************/ 143*14b24e2bSVaishali Kulkarni /* */ 144*14b24e2bSVaishali Kulkarni /* P R I V A T E P A T H */ 145*14b24e2bSVaishali Kulkarni /* */ 146*14b24e2bSVaishali Kulkarni /**************************************/ 147*14b24e2bSVaishali Kulkarni struct private_path { 148*14b24e2bSVaishali Kulkarni u32 recovery_countdown; /* Counting down 2 seconds, using TMR3 */ 149*14b24e2bSVaishali Kulkarni #define RECOVERY_MAX_COUNTDOWN_SECONDS 2 150*14b24e2bSVaishali Kulkarni 151*14b24e2bSVaishali Kulkarni u32 drv_load_vars; /* When the seconds_since_mcp_reset gets here */ 152*14b24e2bSVaishali Kulkarni #define DRV_LOAD_TIMEOUT_MASK 0x0000ffff 153*14b24e2bSVaishali Kulkarni #define DRV_LOAD_TIMEOUT_SHIFT 0 154*14b24e2bSVaishali Kulkarni #define DRV_LOAD_NEED_FORCE_MASK 0xffff0000 155*14b24e2bSVaishali Kulkarni #define DRV_LOAD_NEED_FORCE_SHIFT 16 156*14b24e2bSVaishali Kulkarni struct load_rsp_stc drv_load_params; 157*14b24e2bSVaishali Kulkarni }; 158*14b24e2bSVaishali Kulkarni 159*14b24e2bSVaishali Kulkarni 160*14b24e2bSVaishali Kulkarni /**************************************/ 161*14b24e2bSVaishali Kulkarni /* */ 162*14b24e2bSVaishali Kulkarni /* P R I V A T E P O R T */ 163*14b24e2bSVaishali Kulkarni /* */ 164*14b24e2bSVaishali Kulkarni /**************************************/ 165*14b24e2bSVaishali Kulkarni struct drv_port_info_t { 166*14b24e2bSVaishali Kulkarni u32_t port_state; 167*14b24e2bSVaishali Kulkarni #define DRV_STATE_LINK_LOCK_FLAG 0x00000001 168*14b24e2bSVaishali Kulkarni #define DRV_WAIT_DBG_PRN 0x00000002 169*14b24e2bSVaishali Kulkarni 170*14b24e2bSVaishali Kulkarni /* There are maximum 8 PFs per port */ 171*14b24e2bSVaishali Kulkarni #define DRV_STATE_LOADED_MASK 0x0000ff00 172*14b24e2bSVaishali Kulkarni #define DRV_STATE_LOADED_SHIFT 8 173*14b24e2bSVaishali Kulkarni 174*14b24e2bSVaishali Kulkarni #define DRV_STATE_PF_TRANSITION_MASK 0x00ff0000 175*14b24e2bSVaishali Kulkarni #define DRV_STATE_PF_TRANSITION_SHIFT 16 176*14b24e2bSVaishali Kulkarni 177*14b24e2bSVaishali Kulkarni #define DRV_STATE_PF_PHY_INIT_MASK 0xff000000 178*14b24e2bSVaishali Kulkarni #define DRV_STATE_PF_PHY_INIT_SHIFT 24 179*14b24e2bSVaishali Kulkarni }; 180*14b24e2bSVaishali Kulkarni 181*14b24e2bSVaishali Kulkarni typedef enum _lldp_subscriber_e { 182*14b24e2bSVaishali Kulkarni LLDP_SUBSCRIBER_MANDATORY = 0, 183*14b24e2bSVaishali Kulkarni LLDP_SUBSCRIBER_DCBX_IEEE, 184*14b24e2bSVaishali Kulkarni LLDP_SUBSCRIBER_DCBX_CEE, 185*14b24e2bSVaishali Kulkarni LLDP_SUBSCRIBER_EEE, 186*14b24e2bSVaishali Kulkarni LLDP_SUBSCRIBER_DCI, 187*14b24e2bSVaishali Kulkarni MAX_SUBSCRIBERS 188*14b24e2bSVaishali Kulkarni } lldp_subscriber_e; 189*14b24e2bSVaishali Kulkarni 190*14b24e2bSVaishali Kulkarni typedef struct { 191*14b24e2bSVaishali Kulkarni u16 valid; 192*14b24e2bSVaishali Kulkarni u16 type_len; 193*14b24e2bSVaishali Kulkarni #define LLDP_LEN_MASK (0x01ff) 194*14b24e2bSVaishali Kulkarni #define LLDP_LEN_SHIFT (0) 195*14b24e2bSVaishali Kulkarni #define LLDP_TYPE_MASK (0xfe00) 196*14b24e2bSVaishali Kulkarni #define LLDP_TYPE_SHIFT (9) 197*14b24e2bSVaishali Kulkarni u8 *value_p; 198*14b24e2bSVaishali Kulkarni } tlv_s; 199*14b24e2bSVaishali Kulkarni 200*14b24e2bSVaishali Kulkarni typedef u16(*lldp_prepare_tlv_func)(u8 port, lldp_agent_e lldp_agent, u8 *buffer); 201*14b24e2bSVaishali Kulkarni 202*14b24e2bSVaishali Kulkarni typedef struct { 203*14b24e2bSVaishali Kulkarni u16 valid; 204*14b24e2bSVaishali Kulkarni lldp_prepare_tlv_func func; 205*14b24e2bSVaishali Kulkarni } subscriber_callback_send_s; 206*14b24e2bSVaishali Kulkarni 207*14b24e2bSVaishali Kulkarni typedef u8(*lldp_process_func)(u8 port, u8 num, u8 **tlvs); 208*14b24e2bSVaishali Kulkarni 209*14b24e2bSVaishali Kulkarni #define MAX_NUM_SUBTYPES 4 210*14b24e2bSVaishali Kulkarni typedef struct { 211*14b24e2bSVaishali Kulkarni u8 valid; 212*14b24e2bSVaishali Kulkarni u8 oui[3]; 213*14b24e2bSVaishali Kulkarni u8 subtype_list[MAX_NUM_SUBTYPES]; 214*14b24e2bSVaishali Kulkarni u8 num_subtypes; 215*14b24e2bSVaishali Kulkarni lldp_process_func func; 216*14b24e2bSVaishali Kulkarni } subscriber_callback_receive_s; 217*14b24e2bSVaishali Kulkarni 218*14b24e2bSVaishali Kulkarni #define MAX_ETH_HEADER 14 /* TODO: to be extended per requirements */ 219*14b24e2bSVaishali Kulkarni #define MAX_PACKET_SIZE (1516) /* So it can be devided by 4 */ 220*14b24e2bSVaishali Kulkarni #define LLDP_CHASSIS_ID_TLV_LEN 7 221*14b24e2bSVaishali Kulkarni #define LLDP_PORT_ID_TLV_LEN 7 222*14b24e2bSVaishali Kulkarni #define MAX_TLV_BUFFER 128 /* In dwords. 512 in bytes*/ 223*14b24e2bSVaishali Kulkarni typedef struct { 224*14b24e2bSVaishali Kulkarni u16 len; 225*14b24e2bSVaishali Kulkarni u8 header[MAX_ETH_HEADER]; 226*14b24e2bSVaishali Kulkarni } lldp_eth_header_s; 227*14b24e2bSVaishali Kulkarni 228*14b24e2bSVaishali Kulkarni typedef struct { 229*14b24e2bSVaishali Kulkarni struct lldp_config_params_s lldp_config_params; 230*14b24e2bSVaishali Kulkarni u16 lldp_ttl; 231*14b24e2bSVaishali Kulkarni u8 lldp_cur_credit; 232*14b24e2bSVaishali Kulkarni subscriber_callback_send_s subscriber_callback_send[MAX_SUBSCRIBERS]; 233*14b24e2bSVaishali Kulkarni lldp_eth_header_s lldp_eth_header; 234*14b24e2bSVaishali Kulkarni u32 lldp_time_to_send; 235*14b24e2bSVaishali Kulkarni u32 lldp_ttl_expired; 236*14b24e2bSVaishali Kulkarni u32 lldp_sent; 237*14b24e2bSVaishali Kulkarni u8 first_lldp; 238*14b24e2bSVaishali Kulkarni subscriber_callback_receive_s subscriber_callback_receive[MAX_SUBSCRIBERS]; 239*14b24e2bSVaishali Kulkarni } lldp_params_s; 240*14b24e2bSVaishali Kulkarni 241*14b24e2bSVaishali Kulkarni #define MAX_TLVS 20 242*14b24e2bSVaishali Kulkarni typedef struct { 243*14b24e2bSVaishali Kulkarni u8 current_received_tlv_index; 244*14b24e2bSVaishali Kulkarni u8 *received_tlvs[MAX_TLVS]; 245*14b24e2bSVaishali Kulkarni } lldp_receive_data_s; 246*14b24e2bSVaishali Kulkarni 247*14b24e2bSVaishali Kulkarni #define MAX_REGISTERED_TLVS 6 248*14b24e2bSVaishali Kulkarni 249*14b24e2bSVaishali Kulkarni typedef struct { 250*14b24e2bSVaishali Kulkarni u32 config; /* Uses same defines as local config plus some more below*/ 251*14b24e2bSVaishali Kulkarni #define DCBX_MODE_MASK 0x00000010 252*14b24e2bSVaishali Kulkarni #define DCBX_MODE_SHIFT 4 253*14b24e2bSVaishali Kulkarni #define DCBX_MODE_DRIVER 0 254*14b24e2bSVaishali Kulkarni #define DCBX_MODE_DEFAULT 1 255*14b24e2bSVaishali Kulkarni #define DCBX_CHANGED_MASK 0x00000f00 256*14b24e2bSVaishali Kulkarni #define DCBX_CHANGED_SHIFT 8 257*14b24e2bSVaishali Kulkarni #define DCBX_CONTROL_CHANGED_MASK 0x00000100 258*14b24e2bSVaishali Kulkarni #define DCBX_CONTROL_CHANGED_SHIFT 8 259*14b24e2bSVaishali Kulkarni #define DCBX_PFC_CHANGED_MASK 0x00000200 260*14b24e2bSVaishali Kulkarni #define DCBX_PFC_CHANGED_SHIFT 9 261*14b24e2bSVaishali Kulkarni #define DCBX_ETS_CHANGED_MASK 0x00000400 262*14b24e2bSVaishali Kulkarni #define DCBX_ETS_CHANGED_SHIFT 10 263*14b24e2bSVaishali Kulkarni #define DCBX_APP_CHANGED_MASK 0x00000800 264*14b24e2bSVaishali Kulkarni #define DCBX_APP_CHANGED_SHIFT 11 265*14b24e2bSVaishali Kulkarni 266*14b24e2bSVaishali Kulkarni u32 seq_no; 267*14b24e2bSVaishali Kulkarni u32 ack_no; 268*14b24e2bSVaishali Kulkarni u32 received_seq_no; 269*14b24e2bSVaishali Kulkarni u8 tc_map[8]; 270*14b24e2bSVaishali Kulkarni u8 num_used_tcs; 271*14b24e2bSVaishali Kulkarni } dcbx_state_s; 272*14b24e2bSVaishali Kulkarni 273*14b24e2bSVaishali Kulkarni #ifdef CONFIG_HP_DCI_SUPPORT 274*14b24e2bSVaishali Kulkarni struct dci_info_port { 275*14b24e2bSVaishali Kulkarni u32 config; 276*14b24e2bSVaishali Kulkarni #define DCI_PORT_CFG_ENABLE_SHIFT (0) 277*14b24e2bSVaishali Kulkarni #define DCI_PORT_CFG_ENABLE_MASK (1 << DCI_PORT_CFG_ENABLE_SHIFT) 278*14b24e2bSVaishali Kulkarni #define DCI_PORT_CFG_ENABLE_DIAG_SHIFT (1) 279*14b24e2bSVaishali Kulkarni #define DCI_PORT_CFG_ENABLE_DIAG_MASK (1 << DCI_PORT_CFG_ENABLE_DIAG_SHIFT) 280*14b24e2bSVaishali Kulkarni #define DCI_PORT_CFG_DIAG_L_LOOP_SHIFT (2) 281*14b24e2bSVaishali Kulkarni #define DCI_PORT_CFG_DIAG_L_LOOP_MASK (1 << DCI_PORT_CFG_DIAG_L_LOOP_SHIFT) 282*14b24e2bSVaishali Kulkarni #define DCI_PORT_CFG_DIAG_R_LOOP_SHIFT (3) 283*14b24e2bSVaishali Kulkarni #define DCI_PORT_CFG_DIAG_R_LOOP_MASK (1 << DCI_PORT_CFG_DIAG_R_LOOP_SHIFT) 284*14b24e2bSVaishali Kulkarni 285*14b24e2bSVaishali Kulkarni }; 286*14b24e2bSVaishali Kulkarni #endif 287*14b24e2bSVaishali Kulkarni 288*14b24e2bSVaishali Kulkarni struct private_port { 289*14b24e2bSVaishali Kulkarni struct drv_port_info_t port_info; 290*14b24e2bSVaishali Kulkarni active_mf_mode_t mf_mode; 291*14b24e2bSVaishali Kulkarni u32 prev_link_change_count; 292*14b24e2bSVaishali Kulkarni /* LLDP structures */ 293*14b24e2bSVaishali Kulkarni lldp_params_s lldp_params[LLDP_MAX_LLDP_AGENTS]; 294*14b24e2bSVaishali Kulkarni lldp_receive_data_s lldp_receive_data[MAX_SUBSCRIBERS]; 295*14b24e2bSVaishali Kulkarni 296*14b24e2bSVaishali Kulkarni /* DCBX */ 297*14b24e2bSVaishali Kulkarni dcbx_state_s dcbx_state; 298*14b24e2bSVaishali Kulkarni 299*14b24e2bSVaishali Kulkarni u32 net_buffer[MAX_PACKET_SIZE / 4]; /* Buffer to send any packet to network */ 300*14b24e2bSVaishali Kulkarni 301*14b24e2bSVaishali Kulkarni /* time stamp of the end of NIG drain time for the TX drain */ 302*14b24e2bSVaishali Kulkarni u32 nig_drain_end_ts; 303*14b24e2bSVaishali Kulkarni /* time stamp of the end of NIG drain time for the TC pause drain, this timer is used togther for all TC */ 304*14b24e2bSVaishali Kulkarni u32 nig_drain_tc_end_ts; 305*14b24e2bSVaishali Kulkarni u32 tc_drain_en_bitmap; 306*14b24e2bSVaishali Kulkarni u32 recv_lldp_tlvs[LLDP_MAX_LLDP_AGENTS][MAX_TLV_BUFFER]; 307*14b24e2bSVaishali Kulkarni tlv_s lldp_core_tlv_desc[LLDP_MAX_LLDP_AGENTS][MAX_REGISTERED_TLVS]; 308*14b24e2bSVaishali Kulkarni u8 current_core_tlv_num[LLDP_MAX_LLDP_AGENTS]; 309*14b24e2bSVaishali Kulkarni struct mcp_mac lldp_mac; 310*14b24e2bSVaishali Kulkarni #ifdef CONFIG_HP_DCI_SUPPORT 311*14b24e2bSVaishali Kulkarni struct dci_info_port dci_port; 312*14b24e2bSVaishali Kulkarni #endif 313*14b24e2bSVaishali Kulkarni u32 temperature; 314*14b24e2bSVaishali Kulkarni 315*14b24e2bSVaishali Kulkarni }; 316*14b24e2bSVaishali Kulkarni 317*14b24e2bSVaishali Kulkarni /**************************************/ 318*14b24e2bSVaishali Kulkarni /* */ 319*14b24e2bSVaishali Kulkarni /* P R I V A T E F U N C */ 320*14b24e2bSVaishali Kulkarni /* */ 321*14b24e2bSVaishali Kulkarni /**************************************/ 322*14b24e2bSVaishali Kulkarni struct drv_func_info_t { 323*14b24e2bSVaishali Kulkarni u32_t func_state; 324*14b24e2bSVaishali Kulkarni #define DRV_STATE_UNKNOWN 0x00000000 325*14b24e2bSVaishali Kulkarni #define DRV_STATE_UNLOADED 0x00000001 326*14b24e2bSVaishali Kulkarni #define DRV_STATE_D3 0x00000004 327*14b24e2bSVaishali Kulkarni 328*14b24e2bSVaishali Kulkarni #define DRV_STATE_PRESENT_FLAG 0x00000100 329*14b24e2bSVaishali Kulkarni #define DRV_STATE_RUNNING (0x00000002 | DRV_STATE_PRESENT_FLAG) 330*14b24e2bSVaishali Kulkarni 331*14b24e2bSVaishali Kulkarni #define DRV_STATE_NOT_RESPONDING 0x00000003 /* Will result with non-zero value when compared with DRV_STATE_RUNNING or with DRV_STATE_UNLOADED */ 332*14b24e2bSVaishali Kulkarni #define DRV_STATE_BACK_AFTER_TO (DRV_STATE_NOT_RESPONDING | DRV_STATE_PRESENT_FLAG) 333*14b24e2bSVaishali Kulkarni 334*14b24e2bSVaishali Kulkarni #define DRV_STATE_DIAG (0x00000010 | DRV_STATE_PRESENT_FLAG) 335*14b24e2bSVaishali Kulkarni 336*14b24e2bSVaishali Kulkarni #define DRV_STATE_TRANSITION_FLAG 0x00001000 337*14b24e2bSVaishali Kulkarni #define DRV_STATE_LOADING_TRANSITION (DRV_STATE_TRANSITION_FLAG | DRV_STATE_PRESENT_FLAG) 338*14b24e2bSVaishali Kulkarni #define DRV_STATE_UNLOADING_TRANSITION (DRV_STATE_TRANSITION_FLAG | DRV_STATE_PRESENT_FLAG | DRV_STATE_UNLOADED) 339*14b24e2bSVaishali Kulkarni 340*14b24e2bSVaishali Kulkarni u32_t driver_last_activity; 341*14b24e2bSVaishali Kulkarni 342*14b24e2bSVaishali Kulkarni u32_t wol_mac_addr[2]; 343*14b24e2bSVaishali Kulkarni u32_t drv_feature_support; /* See DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_* */ 344*14b24e2bSVaishali Kulkarni 345*14b24e2bSVaishali Kulkarni u8_t unload_wol_param; /* See drv_mb_param */ 346*14b24e2bSVaishali Kulkarni u8_t eswitch_mode; 347*14b24e2bSVaishali Kulkarni }; 348*14b24e2bSVaishali Kulkarni 349*14b24e2bSVaishali Kulkarni struct dci_info_func { 350*14b24e2bSVaishali Kulkarni u8 config; 351*14b24e2bSVaishali Kulkarni #define DCI_FUNC_CFG_FNIC_ENABLE_SHIFT (0) 352*14b24e2bSVaishali Kulkarni #define DCI_FUNC_CFG_FNIC_ENABLE_MASK (1 << DCI_FUNC_CFG_FNIC_ENABLE_SHIFT) 353*14b24e2bSVaishali Kulkarni #define DCI_FUNC_CFG_OS_MTU_OVERRIDE_SHIFT (1) 354*14b24e2bSVaishali Kulkarni #define DCI_FUNC_CFG_OS_MTU_OVERRIDE_MASK (1 << DCI_FUNC_CFG_OS_MTU_OVERRIDE_SHIFT) 355*14b24e2bSVaishali Kulkarni #define DCI_FUNC_CFG_DIAG_WOL_ENABLE_SHIFT (2) 356*14b24e2bSVaishali Kulkarni #define DCI_FUNC_CFG_DIAG_WOL_ENABLE_MASK (1 << DCI_FUNC_CFG_DIAG_WOL_ENABLE_SHIFT) 357*14b24e2bSVaishali Kulkarni 358*14b24e2bSVaishali Kulkarni u8 drv_state; 359*14b24e2bSVaishali Kulkarni u16 fcoe_cvid; 360*14b24e2bSVaishali Kulkarni u8 fcoe_fabric_name[8]; 361*14b24e2bSVaishali Kulkarni }; 362*14b24e2bSVaishali Kulkarni 363*14b24e2bSVaishali Kulkarni struct private_func { 364*14b24e2bSVaishali Kulkarni struct drv_func_info_t func_info; 365*14b24e2bSVaishali Kulkarni u32 init_hw_page; 366*14b24e2bSVaishali Kulkarni u32 num_of_msix; 367*14b24e2bSVaishali Kulkarni struct pf_sb_t sb; 368*14b24e2bSVaishali Kulkarni struct dci_info_func dci_func; 369*14b24e2bSVaishali Kulkarni }; 370*14b24e2bSVaishali Kulkarni 371*14b24e2bSVaishali Kulkarni 372*14b24e2bSVaishali Kulkarni /**************************************/ 373*14b24e2bSVaishali Kulkarni /* */ 374*14b24e2bSVaishali Kulkarni /* P R I V A T E D A T A */ 375*14b24e2bSVaishali Kulkarni /* */ 376*14b24e2bSVaishali Kulkarni /**************************************/ 377*14b24e2bSVaishali Kulkarni struct mcp_private_data { 378*14b24e2bSVaishali Kulkarni /* Basically no need for section offsets here, since this is private data. 379*14b24e2bSVaishali Kulkarni * TBD - should consider adding section offsets if we want diag to parse this correctly !! 380*14b24e2bSVaishali Kulkarni */ 381*14b24e2bSVaishali Kulkarni struct private_global global; 382*14b24e2bSVaishali Kulkarni struct private_path path[MCP_GLOB_PATH_MAX]; 383*14b24e2bSVaishali Kulkarni struct private_port port[MCP_GLOB_PORT_MAX]; 384*14b24e2bSVaishali Kulkarni struct private_func func[MCP_GLOB_FUNC_MAX]; 385*14b24e2bSVaishali Kulkarni 386*14b24e2bSVaishali Kulkarni }; 387*14b24e2bSVaishali Kulkarni #endif /* MCP_PRIVATE_H */ 388