1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #include "rge.h" 27 28 #define REG32(rgep, reg) ((uint32_t *)(rgep->io_regs+(reg))) 29 #define REG16(rgep, reg) ((uint16_t *)(rgep->io_regs+(reg))) 30 #define REG8(rgep, reg) ((uint8_t *)(rgep->io_regs+(reg))) 31 #define PIO_ADDR(rgep, offset) ((void *)(rgep->io_regs+(offset))) 32 33 /* 34 * Patchable globals: 35 * 36 * rge_autorecover 37 * Enables/disables automatic recovery after fault detection 38 */ 39 static uint32_t rge_autorecover = 1; 40 41 /* 42 * globals: 43 */ 44 #define RGE_DBG RGE_DBG_REGS /* debug flag for this code */ 45 static uint32_t rge_watchdog_count = 1 << 5; 46 static uint32_t rge_rx_watchdog_count = 1 << 3; 47 48 /* 49 * Operating register get/set access routines 50 */ 51 52 static uint32_t rge_reg_get32(rge_t *rgep, uintptr_t regno); 53 #pragma inline(rge_reg_get32) 54 55 static uint32_t 56 rge_reg_get32(rge_t *rgep, uintptr_t regno) 57 { 58 RGE_TRACE(("rge_reg_get32($%p, 0x%lx)", 59 (void *)rgep, regno)); 60 61 return (ddi_get32(rgep->io_handle, REG32(rgep, regno))); 62 } 63 64 static void rge_reg_put32(rge_t *rgep, uintptr_t regno, uint32_t data); 65 #pragma inline(rge_reg_put32) 66 67 static void 68 rge_reg_put32(rge_t *rgep, uintptr_t regno, uint32_t data) 69 { 70 RGE_TRACE(("rge_reg_put32($%p, 0x%lx, 0x%x)", 71 (void *)rgep, regno, data)); 72 73 ddi_put32(rgep->io_handle, REG32(rgep, regno), data); 74 } 75 76 static void rge_reg_set32(rge_t *rgep, uintptr_t regno, uint32_t bits); 77 #pragma inline(rge_reg_set32) 78 79 static void 80 rge_reg_set32(rge_t *rgep, uintptr_t regno, uint32_t bits) 81 { 82 uint32_t regval; 83 84 RGE_TRACE(("rge_reg_set32($%p, 0x%lx, 0x%x)", 85 (void *)rgep, regno, bits)); 86 87 regval = rge_reg_get32(rgep, regno); 88 regval |= bits; 89 rge_reg_put32(rgep, regno, regval); 90 } 91 92 static void rge_reg_clr32(rge_t *rgep, uintptr_t regno, uint32_t bits); 93 #pragma inline(rge_reg_clr32) 94 95 static void 96 rge_reg_clr32(rge_t *rgep, uintptr_t regno, uint32_t bits) 97 { 98 uint32_t regval; 99 100 RGE_TRACE(("rge_reg_clr32($%p, 0x%lx, 0x%x)", 101 (void *)rgep, regno, bits)); 102 103 regval = rge_reg_get32(rgep, regno); 104 regval &= ~bits; 105 rge_reg_put32(rgep, regno, regval); 106 } 107 108 static uint16_t rge_reg_get16(rge_t *rgep, uintptr_t regno); 109 #pragma inline(rge_reg_get16) 110 111 static uint16_t 112 rge_reg_get16(rge_t *rgep, uintptr_t regno) 113 { 114 RGE_TRACE(("rge_reg_get16($%p, 0x%lx)", 115 (void *)rgep, regno)); 116 117 return (ddi_get16(rgep->io_handle, REG16(rgep, regno))); 118 } 119 120 static void rge_reg_put16(rge_t *rgep, uintptr_t regno, uint16_t data); 121 #pragma inline(rge_reg_put16) 122 123 static void 124 rge_reg_put16(rge_t *rgep, uintptr_t regno, uint16_t data) 125 { 126 RGE_TRACE(("rge_reg_put16($%p, 0x%lx, 0x%x)", 127 (void *)rgep, regno, data)); 128 129 ddi_put16(rgep->io_handle, REG16(rgep, regno), data); 130 } 131 132 static uint8_t rge_reg_get8(rge_t *rgep, uintptr_t regno); 133 #pragma inline(rge_reg_get8) 134 135 static uint8_t 136 rge_reg_get8(rge_t *rgep, uintptr_t regno) 137 { 138 RGE_TRACE(("rge_reg_get8($%p, 0x%lx)", 139 (void *)rgep, regno)); 140 141 return (ddi_get8(rgep->io_handle, REG8(rgep, regno))); 142 } 143 144 static void rge_reg_put8(rge_t *rgep, uintptr_t regno, uint8_t data); 145 #pragma inline(rge_reg_put8) 146 147 static void 148 rge_reg_put8(rge_t *rgep, uintptr_t regno, uint8_t data) 149 { 150 RGE_TRACE(("rge_reg_put8($%p, 0x%lx, 0x%x)", 151 (void *)rgep, regno, data)); 152 153 ddi_put8(rgep->io_handle, REG8(rgep, regno), data); 154 } 155 156 static void rge_reg_set8(rge_t *rgep, uintptr_t regno, uint8_t bits); 157 #pragma inline(rge_reg_set8) 158 159 static void 160 rge_reg_set8(rge_t *rgep, uintptr_t regno, uint8_t bits) 161 { 162 uint8_t regval; 163 164 RGE_TRACE(("rge_reg_set8($%p, 0x%lx, 0x%x)", 165 (void *)rgep, regno, bits)); 166 167 regval = rge_reg_get8(rgep, regno); 168 regval |= bits; 169 rge_reg_put8(rgep, regno, regval); 170 } 171 172 static void rge_reg_clr8(rge_t *rgep, uintptr_t regno, uint8_t bits); 173 #pragma inline(rge_reg_clr8) 174 175 static void 176 rge_reg_clr8(rge_t *rgep, uintptr_t regno, uint8_t bits) 177 { 178 uint8_t regval; 179 180 RGE_TRACE(("rge_reg_clr8($%p, 0x%lx, 0x%x)", 181 (void *)rgep, regno, bits)); 182 183 regval = rge_reg_get8(rgep, regno); 184 regval &= ~bits; 185 rge_reg_put8(rgep, regno, regval); 186 } 187 188 uint16_t rge_mii_get16(rge_t *rgep, uintptr_t mii); 189 #pragma no_inline(rge_mii_get16) 190 191 uint16_t 192 rge_mii_get16(rge_t *rgep, uintptr_t mii) 193 { 194 uint32_t regval; 195 uint32_t val32; 196 uint32_t i; 197 198 regval = (mii & PHY_REG_MASK) << PHY_REG_SHIFT; 199 rge_reg_put32(rgep, PHY_ACCESS_REG, regval); 200 201 /* 202 * Waiting for PHY reading OK 203 */ 204 for (i = 0; i < PHY_RESET_LOOP; i++) { 205 drv_usecwait(1000); 206 val32 = rge_reg_get32(rgep, PHY_ACCESS_REG); 207 if (val32 & PHY_ACCESS_WR_FLAG) 208 return ((uint16_t)(val32 & 0xffff)); 209 } 210 211 RGE_REPORT((rgep, "rge_mii_get16(0x%x) fail, val = %x", mii, val32)); 212 return ((uint16_t)~0u); 213 } 214 215 void rge_mii_put16(rge_t *rgep, uintptr_t mii, uint16_t data); 216 #pragma no_inline(rge_mii_put16) 217 218 void 219 rge_mii_put16(rge_t *rgep, uintptr_t mii, uint16_t data) 220 { 221 uint32_t regval; 222 uint32_t val32; 223 uint32_t i; 224 225 regval = (mii & PHY_REG_MASK) << PHY_REG_SHIFT; 226 regval |= data & PHY_DATA_MASK; 227 regval |= PHY_ACCESS_WR_FLAG; 228 rge_reg_put32(rgep, PHY_ACCESS_REG, regval); 229 230 /* 231 * Waiting for PHY writing OK 232 */ 233 for (i = 0; i < PHY_RESET_LOOP; i++) { 234 drv_usecwait(1000); 235 val32 = rge_reg_get32(rgep, PHY_ACCESS_REG); 236 if (!(val32 & PHY_ACCESS_WR_FLAG)) 237 return; 238 } 239 RGE_REPORT((rgep, "rge_mii_put16(0x%lx, 0x%x) fail", 240 mii, data)); 241 } 242 243 void rge_ephy_put16(rge_t *rgep, uintptr_t emii, uint16_t data); 244 #pragma no_inline(rge_ephy_put16) 245 246 void 247 rge_ephy_put16(rge_t *rgep, uintptr_t emii, uint16_t data) 248 { 249 uint32_t regval; 250 uint32_t val32; 251 uint32_t i; 252 253 regval = (emii & EPHY_REG_MASK) << EPHY_REG_SHIFT; 254 regval |= data & EPHY_DATA_MASK; 255 regval |= EPHY_ACCESS_WR_FLAG; 256 rge_reg_put32(rgep, EPHY_ACCESS_REG, regval); 257 258 /* 259 * Waiting for PHY writing OK 260 */ 261 for (i = 0; i < PHY_RESET_LOOP; i++) { 262 drv_usecwait(1000); 263 val32 = rge_reg_get32(rgep, EPHY_ACCESS_REG); 264 if (!(val32 & EPHY_ACCESS_WR_FLAG)) 265 return; 266 } 267 RGE_REPORT((rgep, "rge_ephy_put16(0x%lx, 0x%x) fail", 268 emii, data)); 269 } 270 271 /* 272 * Atomically shift a 32-bit word left, returning 273 * the value it had *before* the shift was applied 274 */ 275 static uint32_t rge_atomic_shl32(uint32_t *sp, uint_t count); 276 #pragma inline(rge_mii_put16) 277 278 static uint32_t 279 rge_atomic_shl32(uint32_t *sp, uint_t count) 280 { 281 uint32_t oldval; 282 uint32_t newval; 283 284 /* ATOMICALLY */ 285 do { 286 oldval = *sp; 287 newval = oldval << count; 288 } while (cas32(sp, oldval, newval) != oldval); 289 290 return (oldval); 291 } 292 293 /* 294 * PHY operation routines 295 */ 296 #if RGE_DEBUGGING 297 298 void 299 rge_phydump(rge_t *rgep) 300 { 301 uint16_t regs[32]; 302 int i; 303 304 ASSERT(mutex_owned(rgep->genlock)); 305 306 for (i = 0; i < 32; ++i) { 307 regs[i] = rge_mii_get16(rgep, i); 308 } 309 310 for (i = 0; i < 32; i += 8) 311 RGE_DEBUG(("rge_phydump: " 312 "0x%04x %04x %04x %04x %04x %04x %04x %04x", 313 regs[i+0], regs[i+1], regs[i+2], regs[i+3], 314 regs[i+4], regs[i+5], regs[i+6], regs[i+7])); 315 } 316 317 #endif /* RGE_DEBUGGING */ 318 319 static void 320 rge_phy_check(rge_t *rgep) 321 { 322 uint16_t gig_ctl; 323 324 if (rgep->param_link_up == LINK_STATE_DOWN) { 325 /* 326 * RTL8169S/8110S PHY has the "PCS bug". Need reset PHY 327 * every 15 seconds whin link down & advertise is 1000. 328 */ 329 if (rgep->chipid.phy_ver == PHY_VER_S) { 330 gig_ctl = rge_mii_get16(rgep, MII_1000BASE_T_CONTROL); 331 if (gig_ctl & MII_1000BT_CTL_ADV_FDX) { 332 rgep->link_down_count++; 333 if (rgep->link_down_count > 15) { 334 (void) rge_phy_reset(rgep); 335 rgep->stats.phy_reset++; 336 rgep->link_down_count = 0; 337 } 338 } 339 } 340 } else { 341 rgep->link_down_count = 0; 342 } 343 } 344 345 /* 346 * Basic low-level function to reset the PHY. 347 * Doesn't incorporate any special-case workarounds. 348 * 349 * Returns TRUE on success, FALSE if the RESET bit doesn't clear 350 */ 351 boolean_t 352 rge_phy_reset(rge_t *rgep) 353 { 354 uint16_t control; 355 uint_t count; 356 357 /* 358 * Set the PHY RESET bit, then wait up to 5 ms for it to self-clear 359 */ 360 control = rge_mii_get16(rgep, MII_CONTROL); 361 rge_mii_put16(rgep, MII_CONTROL, control | MII_CONTROL_RESET); 362 for (count = 0; count < 5; count++) { 363 drv_usecwait(100); 364 control = rge_mii_get16(rgep, MII_CONTROL); 365 if (BIC(control, MII_CONTROL_RESET)) 366 return (B_TRUE); 367 } 368 369 RGE_REPORT((rgep, "rge_phy_reset: FAILED, control now 0x%x", control)); 370 return (B_FALSE); 371 } 372 373 /* 374 * Synchronise the PHY's speed/duplex/autonegotiation capabilities 375 * and advertisements with the required settings as specified by the various 376 * param_* variables that can be poked via the NDD interface. 377 * 378 * We always reset the PHY and reprogram *all* the relevant registers, 379 * not just those changed. This should cause the link to go down, and then 380 * back up again once the link is stable and autonegotiation (if enabled) 381 * is complete. We should get a link state change interrupt somewhere along 382 * the way ... 383 * 384 * NOTE: <genlock> must already be held by the caller 385 */ 386 void 387 rge_phy_update(rge_t *rgep) 388 { 389 boolean_t adv_autoneg; 390 boolean_t adv_pause; 391 boolean_t adv_asym_pause; 392 boolean_t adv_1000fdx; 393 boolean_t adv_1000hdx; 394 boolean_t adv_100fdx; 395 boolean_t adv_100hdx; 396 boolean_t adv_10fdx; 397 boolean_t adv_10hdx; 398 399 uint16_t control; 400 uint16_t gigctrl; 401 uint16_t anar; 402 403 ASSERT(mutex_owned(rgep->genlock)); 404 405 RGE_DEBUG(("rge_phy_update: autoneg %d " 406 "pause %d asym_pause %d " 407 "1000fdx %d 1000hdx %d " 408 "100fdx %d 100hdx %d " 409 "10fdx %d 10hdx %d ", 410 rgep->param_adv_autoneg, 411 rgep->param_adv_pause, rgep->param_adv_asym_pause, 412 rgep->param_adv_1000fdx, rgep->param_adv_1000hdx, 413 rgep->param_adv_100fdx, rgep->param_adv_100hdx, 414 rgep->param_adv_10fdx, rgep->param_adv_10hdx)); 415 416 control = gigctrl = anar = 0; 417 418 /* 419 * PHY settings are normally based on the param_* variables, 420 * but if any loopback mode is in effect, that takes precedence. 421 * 422 * RGE supports MAC-internal loopback, PHY-internal loopback, 423 * and External loopback at a variety of speeds (with a special 424 * cable). In all cases, autoneg is turned OFF, full-duplex 425 * is turned ON, and the speed/mastership is forced. 426 */ 427 switch (rgep->param_loop_mode) { 428 case RGE_LOOP_NONE: 429 default: 430 adv_autoneg = rgep->param_adv_autoneg; 431 adv_pause = rgep->param_adv_pause; 432 adv_asym_pause = rgep->param_adv_asym_pause; 433 adv_1000fdx = rgep->param_adv_1000fdx; 434 adv_1000hdx = rgep->param_adv_1000hdx; 435 adv_100fdx = rgep->param_adv_100fdx; 436 adv_100hdx = rgep->param_adv_100hdx; 437 adv_10fdx = rgep->param_adv_10fdx; 438 adv_10hdx = rgep->param_adv_10hdx; 439 break; 440 441 case RGE_LOOP_INTERNAL_PHY: 442 case RGE_LOOP_INTERNAL_MAC: 443 adv_autoneg = adv_pause = adv_asym_pause = B_FALSE; 444 adv_1000fdx = adv_100fdx = adv_10fdx = B_FALSE; 445 adv_1000hdx = adv_100hdx = adv_10hdx = B_FALSE; 446 rgep->param_link_duplex = LINK_DUPLEX_FULL; 447 448 switch (rgep->param_loop_mode) { 449 case RGE_LOOP_INTERNAL_PHY: 450 if (rgep->chipid.mac_ver != MAC_VER_8101E) { 451 rgep->param_link_speed = 1000; 452 adv_1000fdx = B_TRUE; 453 } else { 454 rgep->param_link_speed = 100; 455 adv_100fdx = B_TRUE; 456 } 457 control = MII_CONTROL_LOOPBACK; 458 break; 459 460 case RGE_LOOP_INTERNAL_MAC: 461 if (rgep->chipid.mac_ver != MAC_VER_8101E) { 462 rgep->param_link_speed = 1000; 463 adv_1000fdx = B_TRUE; 464 } else { 465 rgep->param_link_speed = 100; 466 adv_100fdx = B_TRUE; 467 break; 468 } 469 } 470 471 RGE_DEBUG(("rge_phy_update: autoneg %d " 472 "pause %d asym_pause %d " 473 "1000fdx %d 1000hdx %d " 474 "100fdx %d 100hdx %d " 475 "10fdx %d 10hdx %d ", 476 adv_autoneg, 477 adv_pause, adv_asym_pause, 478 adv_1000fdx, adv_1000hdx, 479 adv_100fdx, adv_100hdx, 480 adv_10fdx, adv_10hdx)); 481 482 /* 483 * We should have at least one technology capability set; 484 * if not, we select a default of 1000Mb/s full-duplex 485 */ 486 if (!adv_1000fdx && !adv_100fdx && !adv_10fdx && 487 !adv_1000hdx && !adv_100hdx && !adv_10hdx) { 488 if (rgep->chipid.mac_ver != MAC_VER_8101E) 489 adv_1000fdx = B_TRUE; 490 } else { 491 adv_1000fdx = B_FALSE; 492 adv_100fdx = B_TRUE; 493 } 494 } 495 496 /* 497 * Now transform the adv_* variables into the proper settings 498 * of the PHY registers ... 499 * 500 * If autonegotiation is (now) enabled, we want to trigger 501 * a new autonegotiation cycle once the PHY has been 502 * programmed with the capabilities to be advertised. 503 * 504 * RTL8169/8110 doesn't support 1000Mb/s half-duplex. 505 */ 506 if (adv_autoneg) 507 control |= MII_CONTROL_ANE|MII_CONTROL_RSAN; 508 509 if (adv_1000fdx) 510 control |= MII_CONTROL_1GB|MII_CONTROL_FDUPLEX; 511 else if (adv_1000hdx) 512 control |= MII_CONTROL_1GB; 513 else if (adv_100fdx) 514 control |= MII_CONTROL_100MB|MII_CONTROL_FDUPLEX; 515 else if (adv_100hdx) 516 control |= MII_CONTROL_100MB; 517 else if (adv_10fdx) 518 control |= MII_CONTROL_FDUPLEX; 519 else if (adv_10hdx) 520 control |= 0; 521 else 522 { _NOTE(EMPTY); } /* Can't get here anyway ... */ 523 524 if (adv_1000fdx) { 525 gigctrl |= MII_1000BT_CTL_ADV_FDX; 526 /* 527 * Chipset limitation: need set other capabilities to true 528 */ 529 if (rgep->chipid.is_pcie) 530 adv_1000hdx = B_TRUE; 531 adv_100fdx = B_TRUE; 532 adv_100hdx = B_TRUE; 533 adv_10fdx = B_TRUE; 534 adv_10hdx = B_TRUE; 535 } 536 537 if (adv_1000hdx) 538 gigctrl |= MII_1000BT_CTL_ADV_HDX; 539 540 if (adv_100fdx) 541 anar |= MII_ABILITY_100BASE_TX_FD; 542 if (adv_100hdx) 543 anar |= MII_ABILITY_100BASE_TX; 544 if (adv_10fdx) 545 anar |= MII_ABILITY_10BASE_T_FD; 546 if (adv_10hdx) 547 anar |= MII_ABILITY_10BASE_T; 548 549 if (adv_pause) 550 anar |= MII_ABILITY_PAUSE; 551 if (adv_asym_pause) 552 anar |= MII_ABILITY_ASMPAUSE; 553 554 /* 555 * Munge in any other fixed bits we require ... 556 */ 557 anar |= MII_AN_SELECTOR_8023; 558 559 /* 560 * Restart the PHY and write the new values. Note the 561 * time, so that we can say whether subsequent link state 562 * changes can be attributed to our reprogramming the PHY 563 */ 564 rge_phy_init(rgep); 565 if (rgep->chipid.mac_ver == MAC_VER_8168B_B || 566 rgep->chipid.mac_ver == MAC_VER_8168B_C) { 567 /* power up PHY for RTL8168B chipset */ 568 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 569 rge_mii_put16(rgep, PHY_0E_REG, 0x0000); 570 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 571 } 572 rge_mii_put16(rgep, MII_AN_ADVERT, anar); 573 rge_mii_put16(rgep, MII_1000BASE_T_CONTROL, gigctrl); 574 rge_mii_put16(rgep, MII_CONTROL, control); 575 576 RGE_DEBUG(("rge_phy_update: anar <- 0x%x", anar)); 577 RGE_DEBUG(("rge_phy_update: control <- 0x%x", control)); 578 RGE_DEBUG(("rge_phy_update: gigctrl <- 0x%x", gigctrl)); 579 } 580 581 void rge_phy_init(rge_t *rgep); 582 #pragma no_inline(rge_phy_init) 583 584 void 585 rge_phy_init(rge_t *rgep) 586 { 587 rgep->phy_mii_addr = 1; 588 589 /* 590 * Below phy config steps are copied from the Programming Guide 591 * (there's no detail comments for these steps.) 592 */ 593 switch (rgep->chipid.mac_ver) { 594 case MAC_VER_8169S_D: 595 case MAC_VER_8169S_E : 596 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 597 rge_mii_put16(rgep, PHY_15_REG, 0x1000); 598 rge_mii_put16(rgep, PHY_18_REG, 0x65c7); 599 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000); 600 rge_mii_put16(rgep, PHY_ID_REG_2, 0x00a1); 601 rge_mii_put16(rgep, PHY_ID_REG_1, 0x0008); 602 rge_mii_put16(rgep, PHY_BMSR_REG, 0x1020); 603 rge_mii_put16(rgep, PHY_BMCR_REG, 0x1000); 604 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0800); 605 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000); 606 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7000); 607 rge_mii_put16(rgep, PHY_ID_REG_2, 0xff41); 608 rge_mii_put16(rgep, PHY_ID_REG_1, 0xde60); 609 rge_mii_put16(rgep, PHY_BMSR_REG, 0x0140); 610 rge_mii_put16(rgep, PHY_BMCR_REG, 0x0077); 611 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7800); 612 rge_mii_put16(rgep, PHY_ANAR_REG, 0x7000); 613 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa000); 614 rge_mii_put16(rgep, PHY_ID_REG_2, 0xdf01); 615 rge_mii_put16(rgep, PHY_ID_REG_1, 0xdf20); 616 rge_mii_put16(rgep, PHY_BMSR_REG, 0xff95); 617 rge_mii_put16(rgep, PHY_BMCR_REG, 0xfa00); 618 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa800); 619 rge_mii_put16(rgep, PHY_ANAR_REG, 0xa000); 620 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb000); 621 rge_mii_put16(rgep, PHY_ID_REG_2, 0xff41); 622 rge_mii_put16(rgep, PHY_ID_REG_1, 0xde20); 623 rge_mii_put16(rgep, PHY_BMSR_REG, 0x0140); 624 rge_mii_put16(rgep, PHY_BMCR_REG, 0x00bb); 625 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb800); 626 rge_mii_put16(rgep, PHY_ANAR_REG, 0xb000); 627 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf000); 628 rge_mii_put16(rgep, PHY_ID_REG_2, 0xdf01); 629 rge_mii_put16(rgep, PHY_ID_REG_1, 0xdf20); 630 rge_mii_put16(rgep, PHY_BMSR_REG, 0xff95); 631 rge_mii_put16(rgep, PHY_BMCR_REG, 0xbf00); 632 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf800); 633 rge_mii_put16(rgep, PHY_ANAR_REG, 0xf000); 634 rge_mii_put16(rgep, PHY_ANAR_REG, 0x0000); 635 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 636 rge_mii_put16(rgep, PHY_0B_REG, 0x0000); 637 break; 638 639 case MAC_VER_8169SB: 640 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 641 rge_mii_put16(rgep, PHY_1B_REG, 0xD41E); 642 rge_mii_put16(rgep, PHY_0E_REG, 0x7bff); 643 rge_mii_put16(rgep, PHY_GBCR_REG, GBCR_DEFAULT); 644 rge_mii_put16(rgep, PHY_1F_REG, 0x0002); 645 rge_mii_put16(rgep, PHY_BMSR_REG, 0x90D0); 646 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 647 break; 648 649 case MAC_VER_8169SC: 650 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 651 rge_mii_put16(rgep, PHY_ANER_REG, 0x0078); 652 rge_mii_put16(rgep, PHY_ANNPRR_REG, 0x05dc); 653 rge_mii_put16(rgep, PHY_GBCR_REG, 0x2672); 654 rge_mii_put16(rgep, PHY_GBSR_REG, 0x6a14); 655 rge_mii_put16(rgep, PHY_0B_REG, 0x7cb0); 656 rge_mii_put16(rgep, PHY_0C_REG, 0xdb80); 657 rge_mii_put16(rgep, PHY_1B_REG, 0xc414); 658 rge_mii_put16(rgep, PHY_1C_REG, 0xef03); 659 rge_mii_put16(rgep, PHY_1D_REG, 0x3dc8); 660 rge_mii_put16(rgep, PHY_1F_REG, 0x0003); 661 rge_mii_put16(rgep, PHY_13_REG, 0x0600); 662 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 663 break; 664 665 case MAC_VER_8168: 666 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 667 rge_mii_put16(rgep, PHY_ANER_REG, 0x00aa); 668 rge_mii_put16(rgep, PHY_ANNPTR_REG, 0x3173); 669 rge_mii_put16(rgep, PHY_ANNPRR_REG, 0x08fc); 670 rge_mii_put16(rgep, PHY_GBCR_REG, 0xe2d0); 671 rge_mii_put16(rgep, PHY_0B_REG, 0x941a); 672 rge_mii_put16(rgep, PHY_18_REG, 0x65fe); 673 rge_mii_put16(rgep, PHY_1C_REG, 0x1e02); 674 rge_mii_put16(rgep, PHY_1F_REG, 0x0002); 675 rge_mii_put16(rgep, PHY_ANNPTR_REG, 0x103e); 676 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 677 break; 678 679 case MAC_VER_8168B_B: 680 case MAC_VER_8168B_C: 681 rge_mii_put16(rgep, PHY_1F_REG, 0x0001); 682 rge_mii_put16(rgep, PHY_0B_REG, 0x94b0); 683 rge_mii_put16(rgep, PHY_1B_REG, 0xc416); 684 rge_mii_put16(rgep, PHY_1F_REG, 0x0003); 685 rge_mii_put16(rgep, PHY_12_REG, 0x6096); 686 rge_mii_put16(rgep, PHY_1F_REG, 0x0000); 687 break; 688 } 689 } 690 691 void rge_chip_ident(rge_t *rgep); 692 #pragma no_inline(rge_chip_ident) 693 694 void 695 rge_chip_ident(rge_t *rgep) 696 { 697 chip_id_t *chip = &rgep->chipid; 698 uint32_t val32; 699 uint16_t val16; 700 701 /* 702 * Read and record MAC version 703 */ 704 val32 = rge_reg_get32(rgep, TX_CONFIG_REG); 705 val32 &= HW_VERSION_ID_0 | HW_VERSION_ID_1; 706 chip->mac_ver = val32; 707 chip->is_pcie = pci_lcap_locate(rgep->cfg_handle, 708 PCI_CAP_ID_PCI_E, &val16) == DDI_SUCCESS; 709 710 /* 711 * Read and record PHY version 712 */ 713 val16 = rge_mii_get16(rgep, PHY_ID_REG_2); 714 val16 &= PHY_VER_MASK; 715 chip->phy_ver = val16; 716 717 /* set pci latency timer */ 718 if (chip->mac_ver == MAC_VER_8169 || 719 chip->mac_ver == MAC_VER_8169S_D || 720 chip->mac_ver == MAC_VER_8169S_E || 721 chip->mac_ver == MAC_VER_8169SC) 722 pci_config_put8(rgep->cfg_handle, PCI_CONF_LATENCY_TIMER, 0x40); 723 724 if (chip->mac_ver == MAC_VER_8169SC) { 725 val16 = rge_reg_get16(rgep, RT_CONFIG_1_REG); 726 val16 &= 0x0300; 727 if (val16 == 0x1) /* 66Mhz PCI */ 728 rge_reg_put32(rgep, 0x7c, 0x000700ff); 729 else if (val16 == 0x0) /* 33Mhz PCI */ 730 rge_reg_put32(rgep, 0x7c, 0x0007ff00); 731 } 732 733 /* 734 * PCIE chipset require the Rx buffer start address must be 735 * 8-byte alignment and the Rx buffer size must be multiple of 8. 736 * We'll just use bcopy in receive procedure for the PCIE chipset. 737 */ 738 if (chip->is_pcie) { 739 rgep->chip_flags |= CHIP_FLAG_FORCE_BCOPY; 740 if (rgep->default_mtu > ETHERMTU) { 741 rge_notice(rgep, "Jumbo packets not supported " 742 "for this PCIE chipset"); 743 rgep->default_mtu = ETHERMTU; 744 } 745 } 746 if (rgep->chip_flags & CHIP_FLAG_FORCE_BCOPY) 747 rgep->head_room = 0; 748 else 749 rgep->head_room = RGE_HEADROOM; 750 751 /* 752 * Initialize other variables. 753 */ 754 if (rgep->default_mtu < ETHERMTU || rgep->default_mtu > RGE_JUMBO_MTU) 755 rgep->default_mtu = ETHERMTU; 756 if (rgep->default_mtu > ETHERMTU) { 757 rgep->rxbuf_size = RGE_BUFF_SIZE_JUMBO; 758 rgep->txbuf_size = RGE_BUFF_SIZE_JUMBO; 759 rgep->ethmax_size = RGE_JUMBO_SIZE; 760 } else { 761 rgep->rxbuf_size = RGE_BUFF_SIZE_STD; 762 rgep->txbuf_size = RGE_BUFF_SIZE_STD; 763 rgep->ethmax_size = ETHERMAX; 764 } 765 chip->rxconfig = RX_CONFIG_DEFAULT; 766 chip->txconfig = TX_CONFIG_DEFAULT; 767 768 /* interval to update statistics for polling mode */ 769 rgep->tick_delta = drv_usectohz(1000*1000/CLK_TICK); 770 771 /* ensure we are not in polling mode */ 772 rgep->curr_tick = ddi_get_lbolt() - 2*rgep->tick_delta; 773 RGE_TRACE(("%s: MAC version = %x, PHY version = %x", 774 rgep->ifname, chip->mac_ver, chip->phy_ver)); 775 } 776 777 /* 778 * Perform first-stage chip (re-)initialisation, using only config-space 779 * accesses: 780 * 781 * + Read the vendor/device/revision/subsystem/cache-line-size registers, 782 * returning the data in the structure pointed to by <idp>. 783 * + Enable Memory Space accesses. 784 * + Enable Bus Mastering according. 785 */ 786 void rge_chip_cfg_init(rge_t *rgep, chip_id_t *cidp); 787 #pragma no_inline(rge_chip_cfg_init) 788 789 void 790 rge_chip_cfg_init(rge_t *rgep, chip_id_t *cidp) 791 { 792 ddi_acc_handle_t handle; 793 uint16_t commd; 794 795 handle = rgep->cfg_handle; 796 797 /* 798 * Save PCI cache line size and subsystem vendor ID 799 */ 800 cidp->command = pci_config_get16(handle, PCI_CONF_COMM); 801 cidp->vendor = pci_config_get16(handle, PCI_CONF_VENID); 802 cidp->device = pci_config_get16(handle, PCI_CONF_DEVID); 803 cidp->subven = pci_config_get16(handle, PCI_CONF_SUBVENID); 804 cidp->subdev = pci_config_get16(handle, PCI_CONF_SUBSYSID); 805 cidp->revision = pci_config_get8(handle, PCI_CONF_REVID); 806 cidp->clsize = pci_config_get8(handle, PCI_CONF_CACHE_LINESZ); 807 cidp->latency = pci_config_get8(handle, PCI_CONF_LATENCY_TIMER); 808 809 /* 810 * Turn on Master Enable (DMA) and IO Enable bits. 811 * Enable PCI Memory Space accesses 812 */ 813 commd = cidp->command; 814 commd |= PCI_COMM_ME | PCI_COMM_MAE | PCI_COMM_IO; 815 pci_config_put16(handle, PCI_CONF_COMM, commd); 816 817 RGE_DEBUG(("rge_chip_cfg_init: vendor 0x%x device 0x%x revision 0x%x", 818 cidp->vendor, cidp->device, cidp->revision)); 819 RGE_DEBUG(("rge_chip_cfg_init: subven 0x%x subdev 0x%x", 820 cidp->subven, cidp->subdev)); 821 RGE_DEBUG(("rge_chip_cfg_init: clsize %d latency %d command 0x%x", 822 cidp->clsize, cidp->latency, cidp->command)); 823 } 824 825 int rge_chip_reset(rge_t *rgep); 826 #pragma no_inline(rge_chip_reset) 827 828 int 829 rge_chip_reset(rge_t *rgep) 830 { 831 int i; 832 uint8_t val8; 833 834 /* 835 * Chip should be in STOP state 836 */ 837 rge_reg_clr8(rgep, RT_COMMAND_REG, 838 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 839 840 /* 841 * Disable interrupt 842 */ 843 rgep->int_mask = INT_MASK_NONE; 844 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 845 846 /* 847 * Clear pended interrupt 848 */ 849 rge_reg_put16(rgep, INT_STATUS_REG, INT_MASK_ALL); 850 851 /* 852 * Reset chip 853 */ 854 rge_reg_set8(rgep, RT_COMMAND_REG, RT_COMMAND_RESET); 855 856 /* 857 * Wait for reset success 858 */ 859 for (i = 0; i < CHIP_RESET_LOOP; i++) { 860 drv_usecwait(10); 861 val8 = rge_reg_get8(rgep, RT_COMMAND_REG); 862 if (!(val8 & RT_COMMAND_RESET)) { 863 rgep->rge_chip_state = RGE_CHIP_RESET; 864 return (0); 865 } 866 } 867 RGE_REPORT((rgep, "rge_chip_reset fail.")); 868 return (-1); 869 } 870 871 void rge_chip_init(rge_t *rgep); 872 #pragma no_inline(rge_chip_init) 873 874 void 875 rge_chip_init(rge_t *rgep) 876 { 877 uint32_t val32; 878 uint32_t val16; 879 uint32_t *hashp; 880 chip_id_t *chip = &rgep->chipid; 881 882 /* 883 * Increase the threshold voltage of RX sensitivity 884 */ 885 if (chip->mac_ver == MAC_VER_8168B_B || 886 chip->mac_ver == MAC_VER_8168B_C || 887 chip->mac_ver == MAC_VER_8101E || 888 chip->mac_ver == MAC_VER_8101E_C) { 889 rge_ephy_put16(rgep, 0x01, 0x1bd3); 890 } 891 892 if (chip->mac_ver == MAC_VER_8168 || 893 chip->mac_ver == MAC_VER_8168B_B) { 894 val16 = rge_reg_get8(rgep, PHY_STATUS_REG); 895 val16 = 0x12<<8 | val16; 896 rge_reg_put16(rgep, PHY_STATUS_REG, val16); 897 rge_reg_put32(rgep, RT_CSI_DATA_REG, 0x00021c01); 898 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f088); 899 rge_reg_put32(rgep, RT_CSI_DATA_REG, 0x00004000); 900 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f0b0); 901 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x0000f068); 902 val32 = rge_reg_get32(rgep, RT_CSI_DATA_REG); 903 val32 |= 0x7000; 904 val32 &= 0xffff5fff; 905 rge_reg_put32(rgep, RT_CSI_DATA_REG, val32); 906 rge_reg_put32(rgep, RT_CSI_ACCESS_REG, 0x8000f068); 907 } 908 909 /* 910 * Config MII register 911 */ 912 rgep->param_link_up = LINK_STATE_DOWN; 913 rge_phy_update(rgep); 914 915 /* 916 * Enable Rx checksum offload. 917 * Then for vlan support, we must enable receive vlan de-tagging. 918 * Otherwise, there'll be checksum error. 919 */ 920 val16 = rge_reg_get16(rgep, CPLUS_COMMAND_REG); 921 val16 |= RX_CKSM_OFFLOAD | RX_VLAN_DETAG; 922 if (chip->mac_ver == MAC_VER_8169S_D) { 923 val16 |= CPLUS_BIT14 | MUL_PCI_RW_ENABLE; 924 rge_reg_put8(rgep, RESV_82_REG, 0x01); 925 } 926 if (chip->mac_ver == MAC_VER_8169S_E || 927 chip->mac_ver == MAC_VER_8169SC) { 928 val16 |= MUL_PCI_RW_ENABLE; 929 } 930 rge_reg_put16(rgep, CPLUS_COMMAND_REG, val16 & (~0x03)); 931 932 /* 933 * Start transmit/receive before set tx/rx configuration register 934 */ 935 if (!chip->is_pcie) 936 rge_reg_set8(rgep, RT_COMMAND_REG, 937 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 938 939 /* 940 * Set dump tally counter register 941 */ 942 val32 = rgep->dma_area_stats.cookie.dmac_laddress >> 32; 943 rge_reg_put32(rgep, DUMP_COUNTER_REG_1, val32); 944 val32 = rge_reg_get32(rgep, DUMP_COUNTER_REG_0); 945 val32 &= DUMP_COUNTER_REG_RESV; 946 val32 |= rgep->dma_area_stats.cookie.dmac_laddress; 947 rge_reg_put32(rgep, DUMP_COUNTER_REG_0, val32); 948 949 /* 950 * Change to config register write enable mode 951 */ 952 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 953 954 /* 955 * Set Tx/Rx maximum packet size 956 */ 957 if (rgep->default_mtu > ETHERMTU) { 958 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_JUMBO); 959 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_JUMBO); 960 } else if (rgep->chipid.mac_ver != MAC_VER_8101E) { 961 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_STD); 962 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_STD); 963 } else { 964 rge_reg_put8(rgep, TX_MAX_PKTSIZE_REG, TX_PKTSIZE_STD_8101E); 965 rge_reg_put16(rgep, RX_MAX_PKTSIZE_REG, RX_PKTSIZE_STD_8101E); 966 } 967 968 /* 969 * Set receive configuration register 970 */ 971 val32 = rge_reg_get32(rgep, RX_CONFIG_REG); 972 val32 &= RX_CONFIG_REG_RESV; 973 if (rgep->promisc) 974 val32 |= RX_ACCEPT_ALL_PKT; 975 rge_reg_put32(rgep, RX_CONFIG_REG, val32 | chip->rxconfig); 976 977 /* 978 * Set transmit configuration register 979 */ 980 val32 = rge_reg_get32(rgep, TX_CONFIG_REG); 981 val32 &= TX_CONFIG_REG_RESV; 982 rge_reg_put32(rgep, TX_CONFIG_REG, val32 | chip->txconfig); 983 984 /* 985 * Set Tx/Rx descriptor register 986 */ 987 val32 = rgep->tx_desc.cookie.dmac_laddress; 988 rge_reg_put32(rgep, NORMAL_TX_RING_ADDR_LO_REG, val32); 989 val32 = rgep->tx_desc.cookie.dmac_laddress >> 32; 990 rge_reg_put32(rgep, NORMAL_TX_RING_ADDR_HI_REG, val32); 991 rge_reg_put32(rgep, HIGH_TX_RING_ADDR_LO_REG, 0); 992 rge_reg_put32(rgep, HIGH_TX_RING_ADDR_HI_REG, 0); 993 val32 = rgep->rx_desc.cookie.dmac_laddress; 994 rge_reg_put32(rgep, RX_RING_ADDR_LO_REG, val32); 995 val32 = rgep->rx_desc.cookie.dmac_laddress >> 32; 996 rge_reg_put32(rgep, RX_RING_ADDR_HI_REG, val32); 997 998 /* 999 * Suggested setting from Realtek 1000 */ 1001 if (rgep->chipid.mac_ver != MAC_VER_8101E) 1002 rge_reg_put16(rgep, RESV_E2_REG, 0x282a); 1003 else 1004 rge_reg_put16(rgep, RESV_E2_REG, 0x0000); 1005 1006 /* 1007 * Set multicast register 1008 */ 1009 hashp = (uint32_t *)rgep->mcast_hash; 1010 if (rgep->promisc) { 1011 rge_reg_put32(rgep, MULTICAST_0_REG, ~0U); 1012 rge_reg_put32(rgep, MULTICAST_4_REG, ~0U); 1013 } else { 1014 rge_reg_put32(rgep, MULTICAST_0_REG, RGE_BSWAP_32(hashp[0])); 1015 rge_reg_put32(rgep, MULTICAST_4_REG, RGE_BSWAP_32(hashp[1])); 1016 } 1017 1018 /* 1019 * Msic register setting: 1020 * -- Missed packet counter: clear it 1021 * -- TimerInt Register 1022 * -- Timer count register 1023 */ 1024 rge_reg_put32(rgep, RX_PKT_MISS_COUNT_REG, 0); 1025 rge_reg_put32(rgep, TIMER_INT_REG, TIMER_INT_NONE); 1026 rge_reg_put32(rgep, TIMER_COUNT_REG, 0); 1027 1028 /* 1029 * disable the Unicast Wakeup Frame capability 1030 */ 1031 rge_reg_clr8(rgep, RT_CONFIG_5_REG, RT_UNI_WAKE_FRAME); 1032 1033 /* 1034 * Return to normal network/host communication mode 1035 */ 1036 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1037 drv_usecwait(20); 1038 } 1039 1040 /* 1041 * rge_chip_start() -- start the chip transmitting and/or receiving, 1042 * including enabling interrupts 1043 */ 1044 void rge_chip_start(rge_t *rgep); 1045 #pragma no_inline(rge_chip_start) 1046 1047 void 1048 rge_chip_start(rge_t *rgep) 1049 { 1050 /* 1051 * Clear statistics 1052 */ 1053 bzero(&rgep->stats, sizeof (rge_stats_t)); 1054 DMA_ZERO(rgep->dma_area_stats); 1055 1056 /* 1057 * Start transmit/receive 1058 */ 1059 rge_reg_set8(rgep, RT_COMMAND_REG, 1060 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1061 1062 /* 1063 * Enable interrupt 1064 */ 1065 rgep->int_mask = RGE_INT_MASK; 1066 if (rgep->chipid.is_pcie) { 1067 rgep->int_mask |= NO_TXDESC_INT; 1068 } 1069 rgep->rx_fifo_ovf = 0; 1070 rgep->int_mask |= RX_FIFO_OVERFLOW_INT; 1071 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 1072 1073 /* 1074 * All done! 1075 */ 1076 rgep->rge_chip_state = RGE_CHIP_RUNNING; 1077 } 1078 1079 /* 1080 * rge_chip_stop() -- stop board receiving 1081 * 1082 * Since this function is also invoked by rge_quiesce(), it 1083 * must not block; also, no tracing or logging takes place 1084 * when invoked by rge_quiesce(). 1085 */ 1086 void rge_chip_stop(rge_t *rgep, boolean_t fault); 1087 #pragma no_inline(rge_chip_stop) 1088 1089 void 1090 rge_chip_stop(rge_t *rgep, boolean_t fault) 1091 { 1092 /* 1093 * Disable interrupt 1094 */ 1095 rgep->int_mask = INT_MASK_NONE; 1096 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 1097 1098 /* 1099 * Clear pended interrupt 1100 */ 1101 if (!rgep->suspended) { 1102 rge_reg_put16(rgep, INT_STATUS_REG, INT_MASK_ALL); 1103 } 1104 1105 /* 1106 * Stop the board and disable transmit/receive 1107 */ 1108 rge_reg_clr8(rgep, RT_COMMAND_REG, 1109 RT_COMMAND_RX_ENABLE | RT_COMMAND_TX_ENABLE); 1110 1111 if (fault) 1112 rgep->rge_chip_state = RGE_CHIP_FAULT; 1113 else 1114 rgep->rge_chip_state = RGE_CHIP_STOPPED; 1115 } 1116 1117 /* 1118 * rge_get_mac_addr() -- get the MAC address on NIC 1119 */ 1120 static void rge_get_mac_addr(rge_t *rgep); 1121 #pragma inline(rge_get_mac_addr) 1122 1123 static void 1124 rge_get_mac_addr(rge_t *rgep) 1125 { 1126 uint8_t *macaddr = rgep->netaddr; 1127 uint32_t val32; 1128 1129 /* 1130 * Read first 4-byte of mac address 1131 */ 1132 val32 = rge_reg_get32(rgep, ID_0_REG); 1133 macaddr[0] = val32 & 0xff; 1134 val32 = val32 >> 8; 1135 macaddr[1] = val32 & 0xff; 1136 val32 = val32 >> 8; 1137 macaddr[2] = val32 & 0xff; 1138 val32 = val32 >> 8; 1139 macaddr[3] = val32 & 0xff; 1140 1141 /* 1142 * Read last 2-byte of mac address 1143 */ 1144 val32 = rge_reg_get32(rgep, ID_4_REG); 1145 macaddr[4] = val32 & 0xff; 1146 val32 = val32 >> 8; 1147 macaddr[5] = val32 & 0xff; 1148 } 1149 1150 static void rge_set_mac_addr(rge_t *rgep); 1151 #pragma inline(rge_set_mac_addr) 1152 1153 static void 1154 rge_set_mac_addr(rge_t *rgep) 1155 { 1156 uint8_t *p = rgep->netaddr; 1157 uint32_t val32; 1158 1159 /* 1160 * Change to config register write enable mode 1161 */ 1162 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1163 1164 /* 1165 * Get first 4 bytes of mac address 1166 */ 1167 val32 = p[3]; 1168 val32 = val32 << 8; 1169 val32 |= p[2]; 1170 val32 = val32 << 8; 1171 val32 |= p[1]; 1172 val32 = val32 << 8; 1173 val32 |= p[0]; 1174 1175 /* 1176 * Set first 4 bytes of mac address 1177 */ 1178 rge_reg_put32(rgep, ID_0_REG, val32); 1179 1180 /* 1181 * Get last 2 bytes of mac address 1182 */ 1183 val32 = p[5]; 1184 val32 = val32 << 8; 1185 val32 |= p[4]; 1186 1187 /* 1188 * Set last 2 bytes of mac address 1189 */ 1190 val32 |= rge_reg_get32(rgep, ID_4_REG) & ~0xffff; 1191 rge_reg_put32(rgep, ID_4_REG, val32); 1192 1193 /* 1194 * Return to normal network/host communication mode 1195 */ 1196 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1197 } 1198 1199 static void rge_set_multi_addr(rge_t *rgep); 1200 #pragma inline(rge_set_multi_addr) 1201 1202 static void 1203 rge_set_multi_addr(rge_t *rgep) 1204 { 1205 uint32_t *hashp; 1206 1207 hashp = (uint32_t *)rgep->mcast_hash; 1208 1209 /* 1210 * Change to config register write enable mode 1211 */ 1212 if (rgep->chipid.mac_ver == MAC_VER_8169SC) { 1213 rge_reg_set8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1214 } 1215 if (rgep->promisc) { 1216 rge_reg_put32(rgep, MULTICAST_0_REG, ~0U); 1217 rge_reg_put32(rgep, MULTICAST_4_REG, ~0U); 1218 } else { 1219 rge_reg_put32(rgep, MULTICAST_0_REG, RGE_BSWAP_32(hashp[0])); 1220 rge_reg_put32(rgep, MULTICAST_4_REG, RGE_BSWAP_32(hashp[1])); 1221 } 1222 1223 /* 1224 * Return to normal network/host communication mode 1225 */ 1226 if (rgep->chipid.mac_ver == MAC_VER_8169SC) { 1227 rge_reg_clr8(rgep, RT_93c46_COMMOND_REG, RT_93c46_MODE_CONFIG); 1228 } 1229 } 1230 1231 static void rge_set_promisc(rge_t *rgep); 1232 #pragma inline(rge_set_promisc) 1233 1234 static void 1235 rge_set_promisc(rge_t *rgep) 1236 { 1237 if (rgep->promisc) 1238 rge_reg_set32(rgep, RX_CONFIG_REG, RX_ACCEPT_ALL_PKT); 1239 else 1240 rge_reg_clr32(rgep, RX_CONFIG_REG, RX_ACCEPT_ALL_PKT); 1241 } 1242 1243 /* 1244 * rge_chip_sync() -- program the chip with the unicast MAC address, 1245 * the multicast hash table, the required level of promiscuity, and 1246 * the current loopback mode ... 1247 */ 1248 void rge_chip_sync(rge_t *rgep, enum rge_sync_op todo); 1249 #pragma no_inline(rge_chip_sync) 1250 1251 void 1252 rge_chip_sync(rge_t *rgep, enum rge_sync_op todo) 1253 { 1254 switch (todo) { 1255 case RGE_GET_MAC: 1256 rge_get_mac_addr(rgep); 1257 break; 1258 case RGE_SET_MAC: 1259 /* Reprogram the unicast MAC address(es) ... */ 1260 rge_set_mac_addr(rgep); 1261 break; 1262 case RGE_SET_MUL: 1263 /* Reprogram the hashed multicast address table ... */ 1264 rge_set_multi_addr(rgep); 1265 break; 1266 case RGE_SET_PROMISC: 1267 /* Set or clear the PROMISCUOUS mode bit */ 1268 rge_set_multi_addr(rgep); 1269 rge_set_promisc(rgep); 1270 break; 1271 default: 1272 break; 1273 } 1274 } 1275 1276 void rge_chip_blank(void *arg, time_t ticks, uint_t count, int flag); 1277 #pragma no_inline(rge_chip_blank) 1278 1279 /* ARGSUSED */ 1280 void 1281 rge_chip_blank(void *arg, time_t ticks, uint_t count, int flag) 1282 { 1283 _NOTE(ARGUNUSED(arg, ticks, count)); 1284 } 1285 1286 void rge_tx_trigger(rge_t *rgep); 1287 #pragma no_inline(rge_tx_trigger) 1288 1289 void 1290 rge_tx_trigger(rge_t *rgep) 1291 { 1292 rge_reg_put8(rgep, TX_RINGS_POLL_REG, NORMAL_TX_RING_POLL); 1293 } 1294 1295 void rge_hw_stats_dump(rge_t *rgep); 1296 #pragma no_inline(rge_tx_trigger) 1297 1298 void 1299 rge_hw_stats_dump(rge_t *rgep) 1300 { 1301 int i = 0; 1302 uint32_t regval = 0; 1303 1304 if (rgep->rge_mac_state == RGE_MAC_STOPPED) 1305 return; 1306 1307 regval = rge_reg_get32(rgep, DUMP_COUNTER_REG_0); 1308 while (regval & DUMP_START) { 1309 drv_usecwait(100); 1310 if (++i > STATS_DUMP_LOOP) { 1311 RGE_DEBUG(("rge h/w statistics dump fail!")); 1312 rgep->rge_chip_state = RGE_CHIP_ERROR; 1313 return; 1314 } 1315 regval = rge_reg_get32(rgep, DUMP_COUNTER_REG_0); 1316 } 1317 DMA_SYNC(rgep->dma_area_stats, DDI_DMA_SYNC_FORKERNEL); 1318 1319 /* 1320 * Start H/W statistics dump for RTL8169 chip 1321 */ 1322 rge_reg_set32(rgep, DUMP_COUNTER_REG_0, DUMP_START); 1323 } 1324 1325 /* 1326 * ========== Hardware interrupt handler ========== 1327 */ 1328 1329 #undef RGE_DBG 1330 #define RGE_DBG RGE_DBG_INT /* debug flag for this code */ 1331 1332 static void rge_wake_factotum(rge_t *rgep); 1333 #pragma inline(rge_wake_factotum) 1334 1335 static void 1336 rge_wake_factotum(rge_t *rgep) 1337 { 1338 if (rgep->factotum_flag == 0) { 1339 rgep->factotum_flag = 1; 1340 (void) ddi_intr_trigger_softint(rgep->factotum_hdl, NULL); 1341 } 1342 } 1343 1344 /* 1345 * rge_intr() -- handle chip interrupts 1346 */ 1347 uint_t rge_intr(caddr_t arg1, caddr_t arg2); 1348 #pragma no_inline(rge_intr) 1349 1350 uint_t 1351 rge_intr(caddr_t arg1, caddr_t arg2) 1352 { 1353 rge_t *rgep = (rge_t *)arg1; 1354 uint16_t int_status; 1355 clock_t now; 1356 uint32_t tx_pkts; 1357 uint32_t rx_pkts; 1358 uint32_t poll_rate; 1359 uint32_t opt_pkts; 1360 uint32_t opt_intrs; 1361 boolean_t update_int_mask = B_FALSE; 1362 uint32_t itimer; 1363 1364 _NOTE(ARGUNUSED(arg2)) 1365 1366 mutex_enter(rgep->genlock); 1367 1368 if (rgep->suspended) { 1369 mutex_exit(rgep->genlock); 1370 return (DDI_INTR_UNCLAIMED); 1371 } 1372 1373 /* 1374 * Was this interrupt caused by our device... 1375 */ 1376 int_status = rge_reg_get16(rgep, INT_STATUS_REG); 1377 if (!(int_status & rgep->int_mask)) { 1378 mutex_exit(rgep->genlock); 1379 return (DDI_INTR_UNCLAIMED); 1380 /* indicate it wasn't our interrupt */ 1381 } 1382 rgep->stats.intr++; 1383 1384 /* 1385 * Clear interrupt 1386 * For PCIE chipset, we need disable interrupt first. 1387 */ 1388 if (rgep->chipid.is_pcie) { 1389 rge_reg_put16(rgep, INT_MASK_REG, INT_MASK_NONE); 1390 update_int_mask = B_TRUE; 1391 } 1392 rge_reg_put16(rgep, INT_STATUS_REG, int_status); 1393 1394 /* 1395 * Calculate optimal polling interval 1396 */ 1397 now = ddi_get_lbolt(); 1398 if (now - rgep->curr_tick >= rgep->tick_delta && 1399 (rgep->param_link_speed == RGE_SPEED_1000M || 1400 rgep->param_link_speed == RGE_SPEED_100M)) { 1401 /* number of rx and tx packets in the last tick */ 1402 tx_pkts = rgep->stats.opackets - rgep->last_opackets; 1403 rx_pkts = rgep->stats.rpackets - rgep->last_rpackets; 1404 1405 rgep->last_opackets = rgep->stats.opackets; 1406 rgep->last_rpackets = rgep->stats.rpackets; 1407 1408 /* restore interrupt mask */ 1409 rgep->int_mask |= TX_OK_INT | RX_OK_INT; 1410 if (rgep->chipid.is_pcie) { 1411 rgep->int_mask |= NO_TXDESC_INT; 1412 } 1413 1414 /* optimal number of packets in a tick */ 1415 if (rgep->param_link_speed == RGE_SPEED_1000M) { 1416 opt_pkts = (1000*1000*1000/8)/ETHERMTU/CLK_TICK; 1417 } else { 1418 opt_pkts = (100*1000*1000/8)/ETHERMTU/CLK_TICK; 1419 } 1420 1421 /* 1422 * calculate polling interval based on rx and tx packets 1423 * in the last tick 1424 */ 1425 poll_rate = 0; 1426 if (now - rgep->curr_tick < 2*rgep->tick_delta) { 1427 opt_intrs = opt_pkts/TX_COALESC; 1428 if (tx_pkts > opt_intrs) { 1429 poll_rate = max(tx_pkts/TX_COALESC, opt_intrs); 1430 rgep->int_mask &= ~(TX_OK_INT | NO_TXDESC_INT); 1431 } 1432 1433 opt_intrs = opt_pkts/RX_COALESC; 1434 if (rx_pkts > opt_intrs) { 1435 opt_intrs = max(rx_pkts/RX_COALESC, opt_intrs); 1436 poll_rate = max(opt_intrs, poll_rate); 1437 rgep->int_mask &= ~RX_OK_INT; 1438 } 1439 /* ensure poll_rate reasonable */ 1440 poll_rate = min(poll_rate, opt_pkts*4); 1441 } 1442 1443 if (poll_rate) { 1444 /* move to polling mode */ 1445 if (rgep->chipid.is_pcie) { 1446 itimer = (TIMER_CLK_PCIE/CLK_TICK)/poll_rate; 1447 } else { 1448 itimer = (TIMER_CLK_PCI/CLK_TICK)/poll_rate; 1449 } 1450 } else { 1451 /* move to normal mode */ 1452 itimer = 0; 1453 } 1454 RGE_DEBUG(("%s: poll: itimer:%d int_mask:0x%x", 1455 __func__, itimer, rgep->int_mask)); 1456 rge_reg_put32(rgep, TIMER_INT_REG, itimer); 1457 1458 /* update timestamp for statistics */ 1459 rgep->curr_tick = now; 1460 1461 /* reset timer */ 1462 int_status |= TIME_OUT_INT; 1463 1464 update_int_mask = B_TRUE; 1465 } 1466 1467 if (int_status & TIME_OUT_INT) { 1468 rge_reg_put32(rgep, TIMER_COUNT_REG, 0); 1469 } 1470 1471 /* flush post writes */ 1472 (void) rge_reg_get16(rgep, INT_STATUS_REG); 1473 1474 /* 1475 * Cable link change interrupt 1476 */ 1477 if (int_status & LINK_CHANGE_INT) { 1478 rge_chip_cyclic(rgep); 1479 } 1480 1481 if (int_status & RX_FIFO_OVERFLOW_INT) { 1482 /* start rx watchdog timeout detection */ 1483 rgep->rx_fifo_ovf = 1; 1484 if (rgep->int_mask & RX_FIFO_OVERFLOW_INT) { 1485 rgep->int_mask &= ~RX_FIFO_OVERFLOW_INT; 1486 update_int_mask = B_TRUE; 1487 } 1488 } else if (int_status & RGE_RX_INT) { 1489 /* stop rx watchdog timeout detection */ 1490 rgep->rx_fifo_ovf = 0; 1491 if ((rgep->int_mask & RX_FIFO_OVERFLOW_INT) == 0) { 1492 rgep->int_mask |= RX_FIFO_OVERFLOW_INT; 1493 update_int_mask = B_TRUE; 1494 } 1495 } 1496 1497 mutex_exit(rgep->genlock); 1498 1499 /* 1500 * Receive interrupt 1501 */ 1502 if (int_status & RGE_RX_INT) 1503 rge_receive(rgep); 1504 1505 /* 1506 * Transmit interrupt 1507 */ 1508 if (int_status & TX_ERR_INT) { 1509 RGE_REPORT((rgep, "tx error happened, resetting the chip ")); 1510 mutex_enter(rgep->genlock); 1511 rgep->rge_chip_state = RGE_CHIP_ERROR; 1512 mutex_exit(rgep->genlock); 1513 } else if ((rgep->chipid.is_pcie && (int_status & NO_TXDESC_INT)) || 1514 ((int_status & TX_OK_INT) && rgep->tx_free < RGE_SEND_SLOTS/8)) { 1515 (void) ddi_intr_trigger_softint(rgep->resched_hdl, NULL); 1516 } 1517 1518 /* 1519 * System error interrupt 1520 */ 1521 if (int_status & SYS_ERR_INT) { 1522 RGE_REPORT((rgep, "sys error happened, resetting the chip ")); 1523 mutex_enter(rgep->genlock); 1524 rgep->rge_chip_state = RGE_CHIP_ERROR; 1525 mutex_exit(rgep->genlock); 1526 } 1527 1528 /* 1529 * Re-enable interrupt for PCIE chipset or install new int_mask 1530 */ 1531 if (update_int_mask) 1532 rge_reg_put16(rgep, INT_MASK_REG, rgep->int_mask); 1533 1534 return (DDI_INTR_CLAIMED); /* indicate it was our interrupt */ 1535 } 1536 1537 /* 1538 * ========== Factotum, implemented as a softint handler ========== 1539 */ 1540 1541 #undef RGE_DBG 1542 #define RGE_DBG RGE_DBG_FACT /* debug flag for this code */ 1543 1544 static boolean_t rge_factotum_link_check(rge_t *rgep); 1545 #pragma no_inline(rge_factotum_link_check) 1546 1547 static boolean_t 1548 rge_factotum_link_check(rge_t *rgep) 1549 { 1550 uint8_t media_status; 1551 int32_t link; 1552 1553 media_status = rge_reg_get8(rgep, PHY_STATUS_REG); 1554 link = (media_status & PHY_STATUS_LINK_UP) ? 1555 LINK_STATE_UP : LINK_STATE_DOWN; 1556 if (rgep->param_link_up != link) { 1557 /* 1558 * Link change. 1559 */ 1560 rgep->param_link_up = link; 1561 1562 if (link == LINK_STATE_UP) { 1563 if (media_status & PHY_STATUS_1000MF) { 1564 rgep->param_link_speed = RGE_SPEED_1000M; 1565 rgep->param_link_duplex = LINK_DUPLEX_FULL; 1566 } else { 1567 rgep->param_link_speed = 1568 (media_status & PHY_STATUS_100M) ? 1569 RGE_SPEED_100M : RGE_SPEED_10M; 1570 rgep->param_link_duplex = 1571 (media_status & PHY_STATUS_DUPLEX_FULL) ? 1572 LINK_DUPLEX_FULL : LINK_DUPLEX_HALF; 1573 } 1574 } 1575 return (B_TRUE); 1576 } 1577 return (B_FALSE); 1578 } 1579 1580 /* 1581 * Factotum routine to check for Tx stall, using the 'watchdog' counter 1582 */ 1583 static boolean_t rge_factotum_stall_check(rge_t *rgep); 1584 #pragma no_inline(rge_factotum_stall_check) 1585 1586 static boolean_t 1587 rge_factotum_stall_check(rge_t *rgep) 1588 { 1589 uint32_t dogval; 1590 1591 ASSERT(mutex_owned(rgep->genlock)); 1592 1593 /* 1594 * Specific check for RX stall ... 1595 */ 1596 rgep->rx_fifo_ovf <<= 1; 1597 if (rgep->rx_fifo_ovf > rge_rx_watchdog_count) { 1598 RGE_REPORT((rgep, "rx_hang detected")); 1599 return (B_TRUE); 1600 } 1601 1602 /* 1603 * Specific check for Tx stall ... 1604 * 1605 * The 'watchdog' counter is incremented whenever a packet 1606 * is queued, reset to 1 when some (but not all) buffers 1607 * are reclaimed, reset to 0 (disabled) when all buffers 1608 * are reclaimed, and shifted left here. If it exceeds the 1609 * threshold value, the chip is assumed to have stalled and 1610 * is put into the ERROR state. The factotum will then reset 1611 * it on the next pass. 1612 * 1613 * All of which should ensure that we don't get into a state 1614 * where packets are left pending indefinitely! 1615 */ 1616 if (rgep->resched_needed) 1617 (void) ddi_intr_trigger_softint(rgep->resched_hdl, NULL); 1618 dogval = rge_atomic_shl32(&rgep->watchdog, 1); 1619 if (dogval < rge_watchdog_count) 1620 return (B_FALSE); 1621 1622 RGE_REPORT((rgep, "Tx stall detected, watchdog code 0x%x", dogval)); 1623 return (B_TRUE); 1624 1625 } 1626 1627 /* 1628 * The factotum is woken up when there's something to do that we'd rather 1629 * not do from inside a hardware interrupt handler or high-level cyclic. 1630 * Its two main tasks are: 1631 * reset & restart the chip after an error 1632 * check the link status whenever necessary 1633 */ 1634 uint_t rge_chip_factotum(caddr_t arg1, caddr_t arg2); 1635 #pragma no_inline(rge_chip_factotum) 1636 1637 uint_t 1638 rge_chip_factotum(caddr_t arg1, caddr_t arg2) 1639 { 1640 rge_t *rgep; 1641 uint_t result; 1642 boolean_t error; 1643 boolean_t linkchg; 1644 1645 rgep = (rge_t *)arg1; 1646 _NOTE(ARGUNUSED(arg2)) 1647 1648 if (rgep->factotum_flag == 0) 1649 return (DDI_INTR_UNCLAIMED); 1650 1651 rgep->factotum_flag = 0; 1652 result = DDI_INTR_CLAIMED; 1653 error = B_FALSE; 1654 linkchg = B_FALSE; 1655 1656 mutex_enter(rgep->genlock); 1657 switch (rgep->rge_chip_state) { 1658 default: 1659 break; 1660 1661 case RGE_CHIP_RUNNING: 1662 linkchg = rge_factotum_link_check(rgep); 1663 error = rge_factotum_stall_check(rgep); 1664 break; 1665 1666 case RGE_CHIP_ERROR: 1667 error = B_TRUE; 1668 break; 1669 1670 case RGE_CHIP_FAULT: 1671 /* 1672 * Fault detected, time to reset ... 1673 */ 1674 if (rge_autorecover) { 1675 RGE_REPORT((rgep, "automatic recovery activated")); 1676 rge_restart(rgep); 1677 } 1678 break; 1679 } 1680 1681 /* 1682 * If an error is detected, stop the chip now, marking it as 1683 * faulty, so that it will be reset next time through ... 1684 */ 1685 if (error) 1686 rge_chip_stop(rgep, B_TRUE); 1687 mutex_exit(rgep->genlock); 1688 1689 /* 1690 * If the link state changed, tell the world about it. 1691 * Note: can't do this while still holding the mutex. 1692 */ 1693 if (linkchg) 1694 mac_link_update(rgep->mh, rgep->param_link_up); 1695 1696 return (result); 1697 } 1698 1699 /* 1700 * High-level cyclic handler 1701 * 1702 * This routine schedules a (low-level) softint callback to the 1703 * factotum, and prods the chip to update the status block (which 1704 * will cause a hardware interrupt when complete). 1705 */ 1706 void rge_chip_cyclic(void *arg); 1707 #pragma no_inline(rge_chip_cyclic) 1708 1709 void 1710 rge_chip_cyclic(void *arg) 1711 { 1712 rge_t *rgep; 1713 1714 rgep = arg; 1715 1716 switch (rgep->rge_chip_state) { 1717 default: 1718 return; 1719 1720 case RGE_CHIP_RUNNING: 1721 rge_phy_check(rgep); 1722 if (rgep->tx_free < RGE_SEND_SLOTS) 1723 rge_send_recycle(rgep); 1724 break; 1725 1726 case RGE_CHIP_FAULT: 1727 case RGE_CHIP_ERROR: 1728 break; 1729 } 1730 1731 rge_wake_factotum(rgep); 1732 } 1733 1734 1735 /* 1736 * ========== Ioctl subfunctions ========== 1737 */ 1738 1739 #undef RGE_DBG 1740 #define RGE_DBG RGE_DBG_PPIO /* debug flag for this code */ 1741 1742 #if RGE_DEBUGGING || RGE_DO_PPIO 1743 1744 static void rge_chip_peek_cfg(rge_t *rgep, rge_peekpoke_t *ppd); 1745 #pragma no_inline(rge_chip_peek_cfg) 1746 1747 static void 1748 rge_chip_peek_cfg(rge_t *rgep, rge_peekpoke_t *ppd) 1749 { 1750 uint64_t regval; 1751 uint64_t regno; 1752 1753 RGE_TRACE(("rge_chip_peek_cfg($%p, $%p)", 1754 (void *)rgep, (void *)ppd)); 1755 1756 regno = ppd->pp_acc_offset; 1757 1758 switch (ppd->pp_acc_size) { 1759 case 1: 1760 regval = pci_config_get8(rgep->cfg_handle, regno); 1761 break; 1762 1763 case 2: 1764 regval = pci_config_get16(rgep->cfg_handle, regno); 1765 break; 1766 1767 case 4: 1768 regval = pci_config_get32(rgep->cfg_handle, regno); 1769 break; 1770 1771 case 8: 1772 regval = pci_config_get64(rgep->cfg_handle, regno); 1773 break; 1774 } 1775 1776 ppd->pp_acc_data = regval; 1777 } 1778 1779 static void rge_chip_poke_cfg(rge_t *rgep, rge_peekpoke_t *ppd); 1780 #pragma no_inline(rge_chip_poke_cfg) 1781 1782 static void 1783 rge_chip_poke_cfg(rge_t *rgep, rge_peekpoke_t *ppd) 1784 { 1785 uint64_t regval; 1786 uint64_t regno; 1787 1788 RGE_TRACE(("rge_chip_poke_cfg($%p, $%p)", 1789 (void *)rgep, (void *)ppd)); 1790 1791 regno = ppd->pp_acc_offset; 1792 regval = ppd->pp_acc_data; 1793 1794 switch (ppd->pp_acc_size) { 1795 case 1: 1796 pci_config_put8(rgep->cfg_handle, regno, regval); 1797 break; 1798 1799 case 2: 1800 pci_config_put16(rgep->cfg_handle, regno, regval); 1801 break; 1802 1803 case 4: 1804 pci_config_put32(rgep->cfg_handle, regno, regval); 1805 break; 1806 1807 case 8: 1808 pci_config_put64(rgep->cfg_handle, regno, regval); 1809 break; 1810 } 1811 } 1812 1813 static void rge_chip_peek_reg(rge_t *rgep, rge_peekpoke_t *ppd); 1814 #pragma no_inline(rge_chip_peek_reg) 1815 1816 static void 1817 rge_chip_peek_reg(rge_t *rgep, rge_peekpoke_t *ppd) 1818 { 1819 uint64_t regval; 1820 void *regaddr; 1821 1822 RGE_TRACE(("rge_chip_peek_reg($%p, $%p)", 1823 (void *)rgep, (void *)ppd)); 1824 1825 regaddr = PIO_ADDR(rgep, ppd->pp_acc_offset); 1826 1827 switch (ppd->pp_acc_size) { 1828 case 1: 1829 regval = ddi_get8(rgep->io_handle, regaddr); 1830 break; 1831 1832 case 2: 1833 regval = ddi_get16(rgep->io_handle, regaddr); 1834 break; 1835 1836 case 4: 1837 regval = ddi_get32(rgep->io_handle, regaddr); 1838 break; 1839 1840 case 8: 1841 regval = ddi_get64(rgep->io_handle, regaddr); 1842 break; 1843 } 1844 1845 ppd->pp_acc_data = regval; 1846 } 1847 1848 static void rge_chip_poke_reg(rge_t *rgep, rge_peekpoke_t *ppd); 1849 #pragma no_inline(rge_chip_peek_reg) 1850 1851 static void 1852 rge_chip_poke_reg(rge_t *rgep, rge_peekpoke_t *ppd) 1853 { 1854 uint64_t regval; 1855 void *regaddr; 1856 1857 RGE_TRACE(("rge_chip_poke_reg($%p, $%p)", 1858 (void *)rgep, (void *)ppd)); 1859 1860 regaddr = PIO_ADDR(rgep, ppd->pp_acc_offset); 1861 regval = ppd->pp_acc_data; 1862 1863 switch (ppd->pp_acc_size) { 1864 case 1: 1865 ddi_put8(rgep->io_handle, regaddr, regval); 1866 break; 1867 1868 case 2: 1869 ddi_put16(rgep->io_handle, regaddr, regval); 1870 break; 1871 1872 case 4: 1873 ddi_put32(rgep->io_handle, regaddr, regval); 1874 break; 1875 1876 case 8: 1877 ddi_put64(rgep->io_handle, regaddr, regval); 1878 break; 1879 } 1880 } 1881 1882 static void rge_chip_peek_mii(rge_t *rgep, rge_peekpoke_t *ppd); 1883 #pragma no_inline(rge_chip_peek_mii) 1884 1885 static void 1886 rge_chip_peek_mii(rge_t *rgep, rge_peekpoke_t *ppd) 1887 { 1888 RGE_TRACE(("rge_chip_peek_mii($%p, $%p)", 1889 (void *)rgep, (void *)ppd)); 1890 1891 ppd->pp_acc_data = rge_mii_get16(rgep, ppd->pp_acc_offset/2); 1892 } 1893 1894 static void rge_chip_poke_mii(rge_t *rgep, rge_peekpoke_t *ppd); 1895 #pragma no_inline(rge_chip_poke_mii) 1896 1897 static void 1898 rge_chip_poke_mii(rge_t *rgep, rge_peekpoke_t *ppd) 1899 { 1900 RGE_TRACE(("rge_chip_poke_mii($%p, $%p)", 1901 (void *)rgep, (void *)ppd)); 1902 1903 rge_mii_put16(rgep, ppd->pp_acc_offset/2, ppd->pp_acc_data); 1904 } 1905 1906 static void rge_chip_peek_mem(rge_t *rgep, rge_peekpoke_t *ppd); 1907 #pragma no_inline(rge_chip_peek_mem) 1908 1909 static void 1910 rge_chip_peek_mem(rge_t *rgep, rge_peekpoke_t *ppd) 1911 { 1912 uint64_t regval; 1913 void *vaddr; 1914 1915 RGE_TRACE(("rge_chip_peek_rge($%p, $%p)", 1916 (void *)rgep, (void *)ppd)); 1917 1918 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 1919 1920 switch (ppd->pp_acc_size) { 1921 case 1: 1922 regval = *(uint8_t *)vaddr; 1923 break; 1924 1925 case 2: 1926 regval = *(uint16_t *)vaddr; 1927 break; 1928 1929 case 4: 1930 regval = *(uint32_t *)vaddr; 1931 break; 1932 1933 case 8: 1934 regval = *(uint64_t *)vaddr; 1935 break; 1936 } 1937 1938 RGE_DEBUG(("rge_chip_peek_mem($%p, $%p) peeked 0x%llx from $%p", 1939 (void *)rgep, (void *)ppd, regval, vaddr)); 1940 1941 ppd->pp_acc_data = regval; 1942 } 1943 1944 static void rge_chip_poke_mem(rge_t *rgep, rge_peekpoke_t *ppd); 1945 #pragma no_inline(rge_chip_poke_mem) 1946 1947 static void 1948 rge_chip_poke_mem(rge_t *rgep, rge_peekpoke_t *ppd) 1949 { 1950 uint64_t regval; 1951 void *vaddr; 1952 1953 RGE_TRACE(("rge_chip_poke_mem($%p, $%p)", 1954 (void *)rgep, (void *)ppd)); 1955 1956 vaddr = (void *)(uintptr_t)ppd->pp_acc_offset; 1957 regval = ppd->pp_acc_data; 1958 1959 RGE_DEBUG(("rge_chip_poke_mem($%p, $%p) poking 0x%llx at $%p", 1960 (void *)rgep, (void *)ppd, regval, vaddr)); 1961 1962 switch (ppd->pp_acc_size) { 1963 case 1: 1964 *(uint8_t *)vaddr = (uint8_t)regval; 1965 break; 1966 1967 case 2: 1968 *(uint16_t *)vaddr = (uint16_t)regval; 1969 break; 1970 1971 case 4: 1972 *(uint32_t *)vaddr = (uint32_t)regval; 1973 break; 1974 1975 case 8: 1976 *(uint64_t *)vaddr = (uint64_t)regval; 1977 break; 1978 } 1979 } 1980 1981 static enum ioc_reply rge_pp_ioctl(rge_t *rgep, int cmd, mblk_t *mp, 1982 struct iocblk *iocp); 1983 #pragma no_inline(rge_pp_ioctl) 1984 1985 static enum ioc_reply 1986 rge_pp_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp) 1987 { 1988 void (*ppfn)(rge_t *rgep, rge_peekpoke_t *ppd); 1989 rge_peekpoke_t *ppd; 1990 dma_area_t *areap; 1991 uint64_t sizemask; 1992 uint64_t mem_va; 1993 uint64_t maxoff; 1994 boolean_t peek; 1995 1996 switch (cmd) { 1997 default: 1998 /* NOTREACHED */ 1999 rge_error(rgep, "rge_pp_ioctl: invalid cmd 0x%x", cmd); 2000 return (IOC_INVAL); 2001 2002 case RGE_PEEK: 2003 peek = B_TRUE; 2004 break; 2005 2006 case RGE_POKE: 2007 peek = B_FALSE; 2008 break; 2009 } 2010 2011 /* 2012 * Validate format of ioctl 2013 */ 2014 if (iocp->ioc_count != sizeof (rge_peekpoke_t)) 2015 return (IOC_INVAL); 2016 if (mp->b_cont == NULL) 2017 return (IOC_INVAL); 2018 ppd = (rge_peekpoke_t *)mp->b_cont->b_rptr; 2019 2020 /* 2021 * Validate request parameters 2022 */ 2023 switch (ppd->pp_acc_space) { 2024 default: 2025 return (IOC_INVAL); 2026 2027 case RGE_PP_SPACE_CFG: 2028 /* 2029 * Config space 2030 */ 2031 sizemask = 8|4|2|1; 2032 mem_va = 0; 2033 maxoff = PCI_CONF_HDR_SIZE; 2034 ppfn = peek ? rge_chip_peek_cfg : rge_chip_poke_cfg; 2035 break; 2036 2037 case RGE_PP_SPACE_REG: 2038 /* 2039 * Memory-mapped I/O space 2040 */ 2041 sizemask = 8|4|2|1; 2042 mem_va = 0; 2043 maxoff = RGE_REGISTER_MAX; 2044 ppfn = peek ? rge_chip_peek_reg : rge_chip_poke_reg; 2045 break; 2046 2047 case RGE_PP_SPACE_MII: 2048 /* 2049 * PHY's MII registers 2050 * NB: all PHY registers are two bytes, but the 2051 * addresses increment in ones (word addressing). 2052 * So we scale the address here, then undo the 2053 * transformation inside the peek/poke functions. 2054 */ 2055 ppd->pp_acc_offset *= 2; 2056 sizemask = 2; 2057 mem_va = 0; 2058 maxoff = (MII_MAXREG+1)*2; 2059 ppfn = peek ? rge_chip_peek_mii : rge_chip_poke_mii; 2060 break; 2061 2062 case RGE_PP_SPACE_RGE: 2063 /* 2064 * RGE data structure! 2065 */ 2066 sizemask = 8|4|2|1; 2067 mem_va = (uintptr_t)rgep; 2068 maxoff = sizeof (*rgep); 2069 ppfn = peek ? rge_chip_peek_mem : rge_chip_poke_mem; 2070 break; 2071 2072 case RGE_PP_SPACE_STATISTICS: 2073 case RGE_PP_SPACE_TXDESC: 2074 case RGE_PP_SPACE_TXBUFF: 2075 case RGE_PP_SPACE_RXDESC: 2076 case RGE_PP_SPACE_RXBUFF: 2077 /* 2078 * Various DMA_AREAs 2079 */ 2080 switch (ppd->pp_acc_space) { 2081 case RGE_PP_SPACE_TXDESC: 2082 areap = &rgep->dma_area_txdesc; 2083 break; 2084 case RGE_PP_SPACE_RXDESC: 2085 areap = &rgep->dma_area_rxdesc; 2086 break; 2087 case RGE_PP_SPACE_STATISTICS: 2088 areap = &rgep->dma_area_stats; 2089 break; 2090 } 2091 2092 sizemask = 8|4|2|1; 2093 mem_va = (uintptr_t)areap->mem_va; 2094 maxoff = areap->alength; 2095 ppfn = peek ? rge_chip_peek_mem : rge_chip_poke_mem; 2096 break; 2097 } 2098 2099 switch (ppd->pp_acc_size) { 2100 default: 2101 return (IOC_INVAL); 2102 2103 case 8: 2104 case 4: 2105 case 2: 2106 case 1: 2107 if ((ppd->pp_acc_size & sizemask) == 0) 2108 return (IOC_INVAL); 2109 break; 2110 } 2111 2112 if ((ppd->pp_acc_offset % ppd->pp_acc_size) != 0) 2113 return (IOC_INVAL); 2114 2115 if (ppd->pp_acc_offset >= maxoff) 2116 return (IOC_INVAL); 2117 2118 if (ppd->pp_acc_offset+ppd->pp_acc_size > maxoff) 2119 return (IOC_INVAL); 2120 2121 /* 2122 * All OK - go do it! 2123 */ 2124 ppd->pp_acc_offset += mem_va; 2125 (*ppfn)(rgep, ppd); 2126 return (peek ? IOC_REPLY : IOC_ACK); 2127 } 2128 2129 static enum ioc_reply rge_diag_ioctl(rge_t *rgep, int cmd, mblk_t *mp, 2130 struct iocblk *iocp); 2131 #pragma no_inline(rge_diag_ioctl) 2132 2133 static enum ioc_reply 2134 rge_diag_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp) 2135 { 2136 ASSERT(mutex_owned(rgep->genlock)); 2137 2138 switch (cmd) { 2139 default: 2140 /* NOTREACHED */ 2141 rge_error(rgep, "rge_diag_ioctl: invalid cmd 0x%x", cmd); 2142 return (IOC_INVAL); 2143 2144 case RGE_DIAG: 2145 /* 2146 * Currently a no-op 2147 */ 2148 return (IOC_ACK); 2149 2150 case RGE_PEEK: 2151 case RGE_POKE: 2152 return (rge_pp_ioctl(rgep, cmd, mp, iocp)); 2153 2154 case RGE_PHY_RESET: 2155 return (IOC_RESTART_ACK); 2156 2157 case RGE_SOFT_RESET: 2158 case RGE_HARD_RESET: 2159 /* 2160 * Reset and reinitialise the 570x hardware 2161 */ 2162 rge_restart(rgep); 2163 return (IOC_ACK); 2164 } 2165 2166 /* NOTREACHED */ 2167 } 2168 2169 #endif /* RGE_DEBUGGING || RGE_DO_PPIO */ 2170 2171 static enum ioc_reply rge_mii_ioctl(rge_t *rgep, int cmd, mblk_t *mp, 2172 struct iocblk *iocp); 2173 #pragma no_inline(rge_mii_ioctl) 2174 2175 static enum ioc_reply 2176 rge_mii_ioctl(rge_t *rgep, int cmd, mblk_t *mp, struct iocblk *iocp) 2177 { 2178 struct rge_mii_rw *miirwp; 2179 2180 /* 2181 * Validate format of ioctl 2182 */ 2183 if (iocp->ioc_count != sizeof (struct rge_mii_rw)) 2184 return (IOC_INVAL); 2185 if (mp->b_cont == NULL) 2186 return (IOC_INVAL); 2187 miirwp = (struct rge_mii_rw *)mp->b_cont->b_rptr; 2188 2189 /* 2190 * Validate request parameters ... 2191 */ 2192 if (miirwp->mii_reg > MII_MAXREG) 2193 return (IOC_INVAL); 2194 2195 switch (cmd) { 2196 default: 2197 /* NOTREACHED */ 2198 rge_error(rgep, "rge_mii_ioctl: invalid cmd 0x%x", cmd); 2199 return (IOC_INVAL); 2200 2201 case RGE_MII_READ: 2202 miirwp->mii_data = rge_mii_get16(rgep, miirwp->mii_reg); 2203 return (IOC_REPLY); 2204 2205 case RGE_MII_WRITE: 2206 rge_mii_put16(rgep, miirwp->mii_reg, miirwp->mii_data); 2207 return (IOC_ACK); 2208 } 2209 2210 /* NOTREACHED */ 2211 } 2212 2213 enum ioc_reply rge_chip_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp, 2214 struct iocblk *iocp); 2215 #pragma no_inline(rge_chip_ioctl) 2216 2217 enum ioc_reply 2218 rge_chip_ioctl(rge_t *rgep, queue_t *wq, mblk_t *mp, struct iocblk *iocp) 2219 { 2220 int cmd; 2221 2222 RGE_TRACE(("rge_chip_ioctl($%p, $%p, $%p, $%p)", 2223 (void *)rgep, (void *)wq, (void *)mp, (void *)iocp)); 2224 2225 ASSERT(mutex_owned(rgep->genlock)); 2226 2227 cmd = iocp->ioc_cmd; 2228 switch (cmd) { 2229 default: 2230 /* NOTREACHED */ 2231 rge_error(rgep, "rge_chip_ioctl: invalid cmd 0x%x", cmd); 2232 return (IOC_INVAL); 2233 2234 case RGE_DIAG: 2235 case RGE_PEEK: 2236 case RGE_POKE: 2237 case RGE_PHY_RESET: 2238 case RGE_SOFT_RESET: 2239 case RGE_HARD_RESET: 2240 #if RGE_DEBUGGING || RGE_DO_PPIO 2241 return (rge_diag_ioctl(rgep, cmd, mp, iocp)); 2242 #else 2243 return (IOC_INVAL); 2244 #endif /* RGE_DEBUGGING || RGE_DO_PPIO */ 2245 2246 case RGE_MII_READ: 2247 case RGE_MII_WRITE: 2248 return (rge_mii_ioctl(rgep, cmd, mp, iocp)); 2249 2250 } 2251 2252 /* NOTREACHED */ 2253 } 2254