1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * AHCI (Advanced Host Controller Interface) SATA HBA Driver 29 * 30 * Power Management Support 31 * ------------------------ 32 * 33 * At the moment, the ahci driver only implements suspend/resume to 34 * support Suspend to RAM on X86 feature. Device power management isn't 35 * implemented, link power management is disabled, and hot plug isn't 36 * allowed during the period from suspend to resume. 37 * 38 * For s/r support, the ahci driver only need to implement DDI_SUSPEND 39 * and DDI_RESUME entries, and don't need to take care of new requests 40 * sent down after suspend because the target driver (sd) has already 41 * handled these conditions, and blocked these requests. For the detailed 42 * information, please check with sdopen, sdclose and sdioctl routines. 43 * 44 */ 45 46 #include <sys/note.h> 47 #include <sys/scsi/scsi.h> 48 #include <sys/pci.h> 49 #include <sys/disp.h> 50 #include <sys/sata/sata_hba.h> 51 #include <sys/sata/adapters/ahci/ahcireg.h> 52 #include <sys/sata/adapters/ahci/ahcivar.h> 53 54 /* 55 * This is the string displayed by modinfo, etc. 56 * Make sure you keep the version ID up to date! 57 */ 58 static char ahci_ident[] = "ahci driver"; 59 60 /* 61 * Function prototypes for driver entry points 62 */ 63 static int ahci_attach(dev_info_t *, ddi_attach_cmd_t); 64 static int ahci_detach(dev_info_t *, ddi_detach_cmd_t); 65 static int ahci_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 66 static int ahci_quiesce(dev_info_t *); 67 68 /* 69 * Function prototypes for SATA Framework interfaces 70 */ 71 static int ahci_register_sata_hba_tran(ahci_ctl_t *, uint32_t); 72 static int ahci_unregister_sata_hba_tran(ahci_ctl_t *); 73 74 static int ahci_tran_probe_port(dev_info_t *, sata_device_t *); 75 static int ahci_tran_start(dev_info_t *, sata_pkt_t *spkt); 76 static int ahci_tran_abort(dev_info_t *, sata_pkt_t *, int); 77 static int ahci_tran_reset_dport(dev_info_t *, sata_device_t *); 78 static int ahci_tran_hotplug_port_activate(dev_info_t *, sata_device_t *); 79 static int ahci_tran_hotplug_port_deactivate(dev_info_t *, sata_device_t *); 80 #if defined(__lock_lint) 81 static int ahci_selftest(dev_info_t *, sata_device_t *); 82 #endif 83 84 /* 85 * Local function prototypes 86 */ 87 static int ahci_alloc_ports_state(ahci_ctl_t *); 88 static void ahci_dealloc_ports_state(ahci_ctl_t *); 89 static int ahci_alloc_port_state(ahci_ctl_t *, uint8_t); 90 static void ahci_dealloc_port_state(ahci_ctl_t *, uint8_t); 91 static int ahci_alloc_rcvd_fis(ahci_ctl_t *, ahci_port_t *, uint8_t); 92 static void ahci_dealloc_rcvd_fis(ahci_port_t *); 93 static int ahci_alloc_cmd_list(ahci_ctl_t *, ahci_port_t *, uint8_t); 94 static void ahci_dealloc_cmd_list(ahci_ctl_t *, ahci_port_t *); 95 static int ahci_alloc_cmd_tables(ahci_ctl_t *, ahci_port_t *); 96 static void ahci_dealloc_cmd_tables(ahci_ctl_t *, ahci_port_t *); 97 98 static int ahci_initialize_controller(ahci_ctl_t *); 99 static void ahci_uninitialize_controller(ahci_ctl_t *); 100 static int ahci_initialize_port(ahci_ctl_t *, ahci_port_t *, uint8_t); 101 static int ahci_config_space_init(ahci_ctl_t *); 102 103 static void ahci_disable_interface_pm(ahci_ctl_t *, uint8_t); 104 static int ahci_start_port(ahci_ctl_t *, ahci_port_t *, uint8_t); 105 static void ahci_find_dev_signature(ahci_ctl_t *, ahci_port_t *, uint8_t); 106 static void ahci_update_sata_registers(ahci_ctl_t *, uint8_t, sata_device_t *); 107 static int ahci_deliver_satapkt(ahci_ctl_t *, ahci_port_t *, 108 uint8_t, sata_pkt_t *); 109 static int ahci_do_sync_start(ahci_ctl_t *, ahci_port_t *, 110 uint8_t, sata_pkt_t *); 111 static int ahci_claim_free_slot(ahci_ctl_t *, ahci_port_t *, int); 112 static void ahci_copy_err_cnxt(sata_cmd_t *, ahci_fis_d2h_register_t *); 113 static void ahci_copy_ncq_err_page(sata_cmd_t *, 114 struct sata_ncq_error_recovery_page *); 115 static void ahci_copy_out_regs(sata_cmd_t *, ahci_fis_d2h_register_t *); 116 117 static int ahci_software_reset(ahci_ctl_t *, ahci_port_t *, uint8_t); 118 static int ahci_hba_reset(ahci_ctl_t *); 119 static int ahci_port_reset(ahci_ctl_t *, ahci_port_t *, uint8_t); 120 static void ahci_reject_all_abort_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 121 static int ahci_reset_device_reject_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 122 static int ahci_reset_port_reject_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 123 static int ahci_reset_hba_reject_pkts(ahci_ctl_t *); 124 static int ahci_put_port_into_notrunning_state(ahci_ctl_t *, ahci_port_t *, 125 uint8_t); 126 static int ahci_restart_port_wait_till_ready(ahci_ctl_t *, ahci_port_t *, 127 uint8_t, int, int *); 128 static void ahci_mop_commands(ahci_ctl_t *, ahci_port_t *, uint32_t, 129 uint32_t, uint32_t, uint32_t, uint32_t); 130 static uint32_t ahci_get_rdlogext_data(ahci_ctl_t *, ahci_port_t *, uint8_t); 131 static void ahci_get_rqsense_data(ahci_ctl_t *, ahci_port_t *, 132 uint8_t, sata_pkt_t *); 133 static void ahci_fatal_error_recovery_handler(ahci_ctl_t *, ahci_port_t *, 134 uint8_t, uint32_t); 135 static void ahci_timeout_pkts(ahci_ctl_t *, ahci_port_t *, 136 uint8_t, uint32_t); 137 static void ahci_events_handler(void *); 138 static void ahci_watchdog_handler(ahci_ctl_t *); 139 140 static uint_t ahci_intr(caddr_t, caddr_t); 141 static void ahci_port_intr(ahci_ctl_t *, ahci_port_t *, uint8_t); 142 static int ahci_add_legacy_intrs(ahci_ctl_t *); 143 static int ahci_add_msi_intrs(ahci_ctl_t *); 144 static void ahci_rem_intrs(ahci_ctl_t *); 145 static void ahci_enable_all_intrs(ahci_ctl_t *); 146 static void ahci_disable_all_intrs(ahci_ctl_t *); 147 static void ahci_enable_port_intrs(ahci_ctl_t *, uint8_t); 148 static void ahci_disable_port_intrs(ahci_ctl_t *, uint8_t); 149 150 static int ahci_intr_cmd_cmplt(ahci_ctl_t *, ahci_port_t *, uint8_t); 151 static int ahci_intr_set_device_bits(ahci_ctl_t *, ahci_port_t *, uint8_t); 152 static int ahci_intr_port_connect_change(ahci_ctl_t *, ahci_port_t *, uint8_t); 153 static int ahci_intr_device_mechanical_presence_status(ahci_ctl_t *, 154 ahci_port_t *, uint8_t); 155 static int ahci_intr_phyrdy_change(ahci_ctl_t *, ahci_port_t *, uint8_t); 156 static int ahci_intr_non_fatal_error(ahci_ctl_t *, ahci_port_t *, 157 uint8_t, uint32_t); 158 static int ahci_intr_fatal_error(ahci_ctl_t *, ahci_port_t *, 159 uint8_t, uint32_t); 160 static int ahci_intr_cold_port_detect(ahci_ctl_t *, ahci_port_t *, uint8_t); 161 162 static int ahci_get_num_implemented_ports(uint32_t); 163 static void ahci_log_fatal_error_message(ahci_ctl_t *, uint8_t port, 164 uint32_t); 165 static void ahci_log_serror_message(ahci_ctl_t *, uint8_t, uint32_t, int); 166 #if AHCI_DEBUG 167 static void ahci_log(ahci_ctl_t *, uint_t, char *, ...); 168 #endif 169 170 171 /* 172 * DMA attributes for the data buffer 173 * 174 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 175 * does not support 64-bit addressing 176 */ 177 static ddi_dma_attr_t buffer_dma_attr = { 178 DMA_ATTR_V0, /* dma_attr_version */ 179 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 180 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 181 0x3fffffull, /* dma_attr_count_max i.e. for one cookie */ 182 0x2ull, /* dma_attr_align: word aligned */ 183 1, /* dma_attr_burstsizes */ 184 1, /* dma_attr_minxfer */ 185 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 186 0xffffffffull, /* dma_attr_seg */ 187 AHCI_PRDT_NUMBER, /* dma_attr_sgllen */ 188 512, /* dma_attr_granular */ 189 0, /* dma_attr_flags */ 190 }; 191 192 /* 193 * DMA attributes for the rcvd FIS 194 * 195 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 196 * does not support 64-bit addressing 197 */ 198 static ddi_dma_attr_t rcvd_fis_dma_attr = { 199 DMA_ATTR_V0, /* dma_attr_version */ 200 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 201 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 202 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 203 0x100ull, /* dma_attr_align: 256-byte aligned */ 204 1, /* dma_attr_burstsizes */ 205 1, /* dma_attr_minxfer */ 206 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 207 0xffffffffull, /* dma_attr_seg */ 208 1, /* dma_attr_sgllen */ 209 1, /* dma_attr_granular */ 210 0, /* dma_attr_flags */ 211 }; 212 213 /* 214 * DMA attributes for the command list 215 * 216 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 217 * does not support 64-bit addressing 218 */ 219 static ddi_dma_attr_t cmd_list_dma_attr = { 220 DMA_ATTR_V0, /* dma_attr_version */ 221 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 222 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 223 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 224 0x400ull, /* dma_attr_align: 1K-byte aligned */ 225 1, /* dma_attr_burstsizes */ 226 1, /* dma_attr_minxfer */ 227 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 228 0xffffffffull, /* dma_attr_seg */ 229 1, /* dma_attr_sgllen */ 230 1, /* dma_attr_granular */ 231 0, /* dma_attr_flags */ 232 }; 233 234 /* 235 * DMA attributes for cmd tables 236 * 237 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 238 * does not support 64-bit addressing 239 */ 240 static ddi_dma_attr_t cmd_table_dma_attr = { 241 DMA_ATTR_V0, /* dma_attr_version */ 242 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 243 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 244 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 245 0x80ull, /* dma_attr_align: 128-byte aligned */ 246 1, /* dma_attr_burstsizes */ 247 1, /* dma_attr_minxfer */ 248 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 249 0xffffffffull, /* dma_attr_seg */ 250 1, /* dma_attr_sgllen */ 251 1, /* dma_attr_granular */ 252 0, /* dma_attr_flags */ 253 }; 254 255 256 /* Device access attributes */ 257 static ddi_device_acc_attr_t accattr = { 258 DDI_DEVICE_ATTR_V0, 259 DDI_STRUCTURE_LE_ACC, 260 DDI_STRICTORDER_ACC 261 }; 262 263 264 static struct dev_ops ahcictl_dev_ops = { 265 DEVO_REV, /* devo_rev */ 266 0, /* refcnt */ 267 ahci_getinfo, /* info */ 268 nulldev, /* identify */ 269 nulldev, /* probe */ 270 ahci_attach, /* attach */ 271 ahci_detach, /* detach */ 272 nodev, /* no reset */ 273 (struct cb_ops *)0, /* driver operations */ 274 NULL, /* bus operations */ 275 NULL, /* power */ 276 ahci_quiesce, /* quiesce */ 277 }; 278 279 static sata_tran_hotplug_ops_t ahci_tran_hotplug_ops = { 280 SATA_TRAN_HOTPLUG_OPS_REV_1, 281 ahci_tran_hotplug_port_activate, 282 ahci_tran_hotplug_port_deactivate 283 }; 284 285 extern struct mod_ops mod_driverops; 286 287 static struct modldrv modldrv = { 288 &mod_driverops, /* driverops */ 289 ahci_ident, /* short description */ 290 &ahcictl_dev_ops, /* driver ops */ 291 }; 292 293 static struct modlinkage modlinkage = { 294 MODREV_1, 295 &modldrv, 296 NULL 297 }; 298 299 static int ahci_watchdog_timeout = 5; /* 5 seconds */ 300 static int ahci_watchdog_tick; 301 302 static size_t ahci_cmd_table_size; 303 304 /* The number of Physical Region Descriptor Table(PRDT) in Command Table */ 305 int ahci_dma_prdt_number = AHCI_PRDT_NUMBER; 306 307 /* 308 * AHCI MSI tunable: 309 * 310 * MSI will be enabled in phase 2. 311 */ 312 boolean_t ahci_msi_enabled = B_FALSE; 313 314 #if AHCI_DEBUG 315 uint32_t ahci_debug_flags = 0; 316 317 /* The following is needed for ahci_log() */ 318 static kmutex_t ahci_log_mutex; 319 static char ahci_log_buf[512]; 320 #endif 321 322 /* Opaque state pointer initialized by ddi_soft_state_init() */ 323 static void *ahci_statep = NULL; 324 325 /* 326 * ahci module initialization. 327 */ 328 int 329 _init(void) 330 { 331 int ret; 332 333 ret = ddi_soft_state_init(&ahci_statep, sizeof (ahci_ctl_t), 0); 334 if (ret != 0) { 335 goto err_out; 336 } 337 338 #if AHCI_DEBUG 339 mutex_init(&ahci_log_mutex, NULL, MUTEX_DRIVER, NULL); 340 #endif 341 342 if ((ret = sata_hba_init(&modlinkage)) != 0) { 343 #if AHCI_DEBUG 344 mutex_destroy(&ahci_log_mutex); 345 #endif 346 ddi_soft_state_fini(&ahci_statep); 347 goto err_out; 348 } 349 350 ret = mod_install(&modlinkage); 351 if (ret != 0) { 352 sata_hba_fini(&modlinkage); 353 #if AHCI_DEBUG 354 mutex_destroy(&ahci_log_mutex); 355 #endif 356 ddi_soft_state_fini(&ahci_statep); 357 goto err_out; 358 } 359 360 /* watchdog tick */ 361 ahci_watchdog_tick = drv_usectohz( 362 (clock_t)ahci_watchdog_timeout * 1000000); 363 return (ret); 364 365 err_out: 366 cmn_err(CE_WARN, "!ahci: Module init failed"); 367 return (ret); 368 } 369 370 /* 371 * ahci module uninitialize. 372 */ 373 int 374 _fini(void) 375 { 376 int ret; 377 378 ret = mod_remove(&modlinkage); 379 if (ret != 0) { 380 return (ret); 381 } 382 383 /* Remove the resources allocated in _init(). */ 384 sata_hba_fini(&modlinkage); 385 #if AHCI_DEBUG 386 mutex_destroy(&ahci_log_mutex); 387 #endif 388 ddi_soft_state_fini(&ahci_statep); 389 390 return (ret); 391 } 392 393 /* 394 * _info entry point 395 */ 396 int 397 _info(struct modinfo *modinfop) 398 { 399 return (mod_info(&modlinkage, modinfop)); 400 } 401 402 /* 403 * The attach entry point for dev_ops. 404 */ 405 static int 406 ahci_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 407 { 408 ahci_ctl_t *ahci_ctlp; 409 int instance = ddi_get_instance(dip); 410 int status; 411 int attach_state; 412 uint32_t cap_status, ahci_version; 413 int intr_types; 414 int i; 415 pci_regspec_t *regs; 416 int regs_length; 417 int rnumber; 418 #if AHCI_DEBUG 419 int speed; 420 #endif 421 422 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, NULL, "ahci_attach enter"); 423 424 switch (cmd) { 425 case DDI_ATTACH: 426 break; 427 428 case DDI_RESUME: 429 430 /* 431 * During DDI_RESUME, the hardware state of the device 432 * (power may have been removed from the device) must be 433 * restored, allow pending requests to continue, and 434 * service new requests. 435 */ 436 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 437 mutex_enter(&ahci_ctlp->ahcictl_mutex); 438 439 /* Restart watch thread */ 440 if (ahci_ctlp->ahcictl_timeout_id == 0) 441 ahci_ctlp->ahcictl_timeout_id = timeout( 442 (void (*)(void *))ahci_watchdog_handler, 443 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 444 445 mutex_exit(&ahci_ctlp->ahcictl_mutex); 446 447 /* 448 * Re-initialize the controller and enable the interrupts and 449 * restart all the ports. 450 * 451 * Note that so far we don't support hot-plug during 452 * suspend/resume. 453 */ 454 if (ahci_initialize_controller(ahci_ctlp) != AHCI_SUCCESS) { 455 AHCIDBG0(AHCIDBG_ERRS|AHCIDBG_PM, ahci_ctlp, 456 "Failed to initialize the controller " 457 "during DDI_RESUME"); 458 return (DDI_FAILURE); 459 } 460 461 mutex_enter(&ahci_ctlp->ahcictl_mutex); 462 ahci_ctlp->ahcictl_flags &= ~ AHCI_SUSPEND; 463 mutex_exit(&ahci_ctlp->ahcictl_mutex); 464 465 return (DDI_SUCCESS); 466 467 default: 468 return (DDI_FAILURE); 469 } 470 471 attach_state = AHCI_ATTACH_STATE_NONE; 472 473 /* Allocate soft state */ 474 status = ddi_soft_state_zalloc(ahci_statep, instance); 475 if (status != DDI_SUCCESS) { 476 cmn_err(CE_WARN, "!ahci%d: Cannot allocate soft state", 477 instance); 478 goto err_out; 479 } 480 481 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 482 ahci_ctlp->ahcictl_flags |= AHCI_ATTACH; 483 ahci_ctlp->ahcictl_dip = dip; 484 485 /* Initialize the cport/port mapping */ 486 for (i = 0; i < AHCI_MAX_PORTS; i++) { 487 ahci_ctlp->ahcictl_port_to_cport[i] = 0xff; 488 ahci_ctlp->ahcictl_cport_to_port[i] = 0xff; 489 } 490 491 attach_state |= AHCI_ATTACH_STATE_STATEP_ALLOC; 492 493 /* 494 * Now map the AHCI base address; which includes global 495 * registers and port control registers 496 * 497 * According to the spec, the AHCI Base Address is BAR5, 498 * but BAR0-BAR4 are optional, so we need to check which 499 * rnumber is used for BAR5. 500 */ 501 502 /* 503 * search through DDI "reg" property for the AHCI register set 504 */ 505 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 506 DDI_PROP_DONTPASS, "reg", (int **)®s, 507 (uint_t *)®s_length) != DDI_PROP_SUCCESS) { 508 cmn_err(CE_WARN, "!ahci%d: Cannot lookup reg property", 509 instance); 510 goto err_out; 511 } 512 513 /* AHCI Base Address is located at 0x24 offset */ 514 for (rnumber = 0; rnumber < regs_length; ++rnumber) { 515 if ((regs[rnumber].pci_phys_hi & PCI_REG_REG_M) 516 == AHCI_PCI_RNUM) 517 break; 518 } 519 520 ddi_prop_free(regs); 521 522 if (rnumber == regs_length) { 523 cmn_err(CE_WARN, "!ahci%d: Cannot find AHCI register set", 524 instance); 525 goto err_out; 526 } 527 528 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "rnumber = %d", rnumber); 529 530 status = ddi_regs_map_setup(dip, 531 rnumber, 532 (caddr_t *)&ahci_ctlp->ahcictl_ahci_addr, 533 0, 534 0, 535 &accattr, 536 &ahci_ctlp->ahcictl_ahci_acc_handle); 537 if (status != DDI_SUCCESS) { 538 cmn_err(CE_WARN, "!ahci%d: Cannot map register space", 539 instance); 540 goto err_out; 541 } 542 543 attach_state |= AHCI_ATTACH_STATE_REG_MAP; 544 545 /* Get the AHCI version information */ 546 ahci_version = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 547 (uint32_t *)AHCI_GLOBAL_VS(ahci_ctlp)); 548 549 cmn_err(CE_NOTE, "!ahci%d: hba AHCI version = %x.%x", instance, 550 (ahci_version & 0xffff0000) >> 16, 551 ((ahci_version & 0x0000ff00) >> 4 | 552 (ahci_version & 0x000000ff))); 553 554 /* We don't support controllers whose versions are lower than 1.0 */ 555 if (!(ahci_version & 0xffff0000)) { 556 cmn_err(CE_WARN, "ahci%d: Don't support AHCI HBA with lower " 557 "than version 1.0", instance); 558 goto err_out; 559 } 560 561 /* Get the HBA capabilities information */ 562 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 563 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 564 565 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba capabilites = 0x%x", 566 cap_status); 567 568 #if AHCI_DEBUG 569 /* Get the interface speed supported by the HBA */ 570 speed = (cap_status & AHCI_HBA_CAP_ISS) >> AHCI_HBA_CAP_ISS_SHIFT; 571 if (speed == 0x01) { 572 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 573 "hba interface speed support: Gen 1 (1.5Gbps)"); 574 } else if (speed == 0x10) { 575 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 576 "hba interface speed support: Gen 2 (3 Gbps)"); 577 } else if (speed == 0x11) { 578 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 579 "hba interface speed support: Gen 3 (6 Gbps)"); 580 } 581 #endif 582 583 /* Get the number of command slots supported by the HBA */ 584 ahci_ctlp->ahcictl_num_cmd_slots = 585 ((cap_status & AHCI_HBA_CAP_NCS) >> 586 AHCI_HBA_CAP_NCS_SHIFT) + 1; 587 588 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba number of cmd slots: %d", 589 ahci_ctlp->ahcictl_num_cmd_slots); 590 591 /* Get the bit map which indicates ports implemented by the HBA */ 592 ahci_ctlp->ahcictl_ports_implemented = 593 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 594 (uint32_t *)AHCI_GLOBAL_PI(ahci_ctlp)); 595 596 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba implementation of ports: 0x%x", 597 ahci_ctlp->ahcictl_ports_implemented); 598 599 /* 600 * According to the AHCI spec, CAP.NP should indicate the maximum 601 * number of ports supported by the HBA silicon, but we found 602 * this value of ICH8 chipset only indicates the number of ports 603 * implemented (exposed) by it. Therefore, the driver should calculate 604 * the potential maximum value by checking PI register, and use 605 * the maximum of this value and CAP.NP. 606 */ 607 ahci_ctlp->ahcictl_num_ports = max( 608 (cap_status & AHCI_HBA_CAP_NP) + 1, 609 ddi_fls(ahci_ctlp->ahcictl_ports_implemented)); 610 611 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba number of ports: %d", 612 ahci_ctlp->ahcictl_num_ports); 613 614 /* Get the number of implemented ports by the HBA */ 615 ahci_ctlp->ahcictl_num_implemented_ports = 616 ahci_get_num_implemented_ports( 617 ahci_ctlp->ahcictl_ports_implemented); 618 619 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 620 "hba number of implemented ports: %d", 621 ahci_ctlp->ahcictl_num_implemented_ports); 622 623 /* Check whether HBA supports 64bit DMA addressing */ 624 if (!(cap_status & AHCI_HBA_CAP_S64A)) { 625 ahci_ctlp->ahcictl_cap |= AHCI_CAP_32BIT_DMA; 626 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 627 "hba does not support 64-bit addressing"); 628 } 629 630 if (pci_config_setup(dip, &ahci_ctlp->ahcictl_pci_conf_handle) 631 != DDI_SUCCESS) { 632 cmn_err(CE_WARN, "!ahci%d: Cannot set up pci configure space", 633 instance); 634 goto err_out; 635 } 636 637 attach_state |= AHCI_ATTACH_STATE_PCICFG_SETUP; 638 639 /* Check the pci configuration space, and set caps */ 640 if (ahci_config_space_init(ahci_ctlp) == AHCI_FAILURE) { 641 cmn_err(CE_WARN, "!ahci%d: ahci_config_space_init failed", 642 instance); 643 goto err_out; 644 } 645 646 /* 647 * Disable the whole controller interrupts before adding 648 * interrupt handlers(s). 649 */ 650 ahci_disable_all_intrs(ahci_ctlp); 651 652 /* Get supported interrupt types */ 653 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) { 654 cmn_err(CE_WARN, "!ahci%d: ddi_intr_get_supported_types failed", 655 instance); 656 goto err_out; 657 } 658 659 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 660 "ddi_intr_get_supported_types() returned: 0x%x", 661 intr_types); 662 663 if (ahci_msi_enabled && (intr_types & DDI_INTR_TYPE_MSI)) { 664 /* 665 * Try MSI first, but fall back to FIXED if failed 666 */ 667 if (ahci_add_msi_intrs(ahci_ctlp) == DDI_SUCCESS) { 668 ahci_ctlp->ahcictl_intr_type = DDI_INTR_TYPE_MSI; 669 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 670 "Using MSI interrupt type"); 671 goto intr_done; 672 } 673 674 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 675 "MSI registration failed, " 676 "trying FIXED interrupts"); 677 } 678 679 if (intr_types & DDI_INTR_TYPE_FIXED) { 680 if (ahci_add_legacy_intrs(ahci_ctlp) == DDI_SUCCESS) { 681 ahci_ctlp->ahcictl_intr_type = DDI_INTR_TYPE_FIXED; 682 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 683 "Using FIXED interrupt type"); 684 goto intr_done; 685 } 686 687 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 688 "FIXED interrupt registration failed"); 689 } 690 691 cmn_err(CE_WARN, "!ahci%d: Interrupt registration failed", instance); 692 693 goto err_out; 694 695 intr_done: 696 697 attach_state |= AHCI_ATTACH_STATE_INTR_ADDED; 698 699 /* Initialize the controller mutex */ 700 mutex_init(&ahci_ctlp->ahcictl_mutex, NULL, MUTEX_DRIVER, 701 (void *)(uintptr_t)ahci_ctlp->ahcictl_intr_pri); 702 703 attach_state |= AHCI_ATTACH_STATE_MUTEX_INIT; 704 705 if (ahci_dma_prdt_number < AHCI_MIN_PRDT_NUMBER) { 706 ahci_dma_prdt_number = AHCI_MIN_PRDT_NUMBER; 707 } else if (ahci_dma_prdt_number > AHCI_MAX_PRDT_NUMBER) { 708 ahci_dma_prdt_number = AHCI_MAX_PRDT_NUMBER; 709 } 710 711 ahci_cmd_table_size = (sizeof (ahci_cmd_table_t) + 712 (ahci_dma_prdt_number - AHCI_PRDT_NUMBER) * 713 sizeof (ahci_prdt_item_t)); 714 715 AHCIDBG2(AHCIDBG_INIT, ahci_ctlp, 716 "ahci_attach: ahci_dma_prdt_number set by user is 0x%x," 717 " ahci_cmd_table_size is 0x%x", 718 ahci_dma_prdt_number, ahci_cmd_table_size); 719 720 if (ahci_dma_prdt_number != AHCI_PRDT_NUMBER) 721 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_sgllen = 722 ahci_dma_prdt_number; 723 724 ahci_ctlp->ahcictl_buffer_dma_attr = buffer_dma_attr; 725 ahci_ctlp->ahcictl_rcvd_fis_dma_attr = rcvd_fis_dma_attr; 726 ahci_ctlp->ahcictl_cmd_list_dma_attr = cmd_list_dma_attr; 727 ahci_ctlp->ahcictl_cmd_table_dma_attr = cmd_table_dma_attr; 728 729 if (ahci_ctlp->ahcictl_cap & AHCI_CAP_32BIT_DMA) { 730 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_addr_hi = 731 0xffffffffull; 732 ahci_ctlp->ahcictl_rcvd_fis_dma_attr.dma_attr_addr_hi = 733 0xffffffffull; 734 ahci_ctlp->ahcictl_cmd_list_dma_attr.dma_attr_addr_hi = 735 0xffffffffull; 736 ahci_ctlp->ahcictl_cmd_table_dma_attr.dma_attr_addr_hi = 737 0xffffffffull; 738 } 739 740 /* Allocate the ports structure */ 741 status = ahci_alloc_ports_state(ahci_ctlp); 742 if (status != AHCI_SUCCESS) { 743 cmn_err(CE_WARN, "!ahci%d: Cannot allocate ports structure", 744 instance); 745 goto err_out; 746 } 747 748 attach_state |= AHCI_ATTACH_STATE_PORT_ALLOC; 749 750 /* 751 * A taskq is created for dealing with events 752 */ 753 if ((ahci_ctlp->ahcictl_event_taskq = ddi_taskq_create(dip, 754 "ahci_event_handle_taskq", 1, TASKQ_DEFAULTPRI, 0)) == NULL) { 755 cmn_err(CE_WARN, "!ahci%d: ddi_taskq_create failed for event " 756 "handle", instance); 757 goto err_out; 758 } 759 760 attach_state |= AHCI_ATTACH_STATE_ERR_RECV_TASKQ; 761 762 /* 763 * Initialize the controller and ports. 764 */ 765 status = ahci_initialize_controller(ahci_ctlp); 766 if (status != AHCI_SUCCESS) { 767 cmn_err(CE_WARN, "!ahci%d: HBA initialization failed", 768 instance); 769 goto err_out; 770 } 771 772 attach_state |= AHCI_ATTACH_STATE_HW_INIT; 773 774 /* Start one thread to check packet timeouts */ 775 ahci_ctlp->ahcictl_timeout_id = timeout( 776 (void (*)(void *))ahci_watchdog_handler, 777 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 778 779 attach_state |= AHCI_ATTACH_STATE_TIMEOUT_ENABLED; 780 781 if (ahci_register_sata_hba_tran(ahci_ctlp, cap_status)) { 782 cmn_err(CE_WARN, "!ahci%d: sata hba tran registration failed", 783 instance); 784 goto err_out; 785 } 786 787 ahci_ctlp->ahcictl_flags &= ~AHCI_ATTACH; 788 789 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, "ahci_attach success!"); 790 791 return (DDI_SUCCESS); 792 793 err_out: 794 if (attach_state & AHCI_ATTACH_STATE_TIMEOUT_ENABLED) { 795 mutex_enter(&ahci_ctlp->ahcictl_mutex); 796 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 797 ahci_ctlp->ahcictl_timeout_id = 0; 798 mutex_exit(&ahci_ctlp->ahcictl_mutex); 799 } 800 801 if (attach_state & AHCI_ATTACH_STATE_HW_INIT) { 802 ahci_uninitialize_controller(ahci_ctlp); 803 } 804 805 if (attach_state & AHCI_ATTACH_STATE_ERR_RECV_TASKQ) { 806 ddi_taskq_destroy(ahci_ctlp->ahcictl_event_taskq); 807 } 808 809 if (attach_state & AHCI_ATTACH_STATE_PORT_ALLOC) { 810 ahci_dealloc_ports_state(ahci_ctlp); 811 } 812 813 if (attach_state & AHCI_ATTACH_STATE_MUTEX_INIT) { 814 mutex_destroy(&ahci_ctlp->ahcictl_mutex); 815 } 816 817 if (attach_state & AHCI_ATTACH_STATE_INTR_ADDED) { 818 ahci_rem_intrs(ahci_ctlp); 819 } 820 821 if (attach_state & AHCI_ATTACH_STATE_PCICFG_SETUP) { 822 pci_config_teardown(&ahci_ctlp->ahcictl_pci_conf_handle); 823 } 824 825 if (attach_state & AHCI_ATTACH_STATE_REG_MAP) { 826 ddi_regs_map_free(&ahci_ctlp->ahcictl_ahci_acc_handle); 827 } 828 829 if (attach_state & AHCI_ATTACH_STATE_STATEP_ALLOC) { 830 ddi_soft_state_free(ahci_statep, instance); 831 } 832 833 return (DDI_FAILURE); 834 } 835 836 /* 837 * The detach entry point for dev_ops. 838 */ 839 static int 840 ahci_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 841 { 842 ahci_ctl_t *ahci_ctlp; 843 int instance; 844 int ret; 845 846 instance = ddi_get_instance(dip); 847 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 848 849 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_detach enter"); 850 851 switch (cmd) { 852 case DDI_DETACH: 853 854 /* disable the interrupts for an uninterrupted detach */ 855 mutex_enter(&ahci_ctlp->ahcictl_mutex); 856 ahci_disable_all_intrs(ahci_ctlp); 857 mutex_exit(&ahci_ctlp->ahcictl_mutex); 858 859 /* unregister from the sata framework. */ 860 ret = ahci_unregister_sata_hba_tran(ahci_ctlp); 861 if (ret != AHCI_SUCCESS) { 862 mutex_enter(&ahci_ctlp->ahcictl_mutex); 863 ahci_enable_all_intrs(ahci_ctlp); 864 mutex_exit(&ahci_ctlp->ahcictl_mutex); 865 return (DDI_FAILURE); 866 } 867 868 mutex_enter(&ahci_ctlp->ahcictl_mutex); 869 870 /* stop the watchdog handler */ 871 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 872 ahci_ctlp->ahcictl_timeout_id = 0; 873 874 mutex_exit(&ahci_ctlp->ahcictl_mutex); 875 876 /* uninitialize the controller */ 877 ahci_uninitialize_controller(ahci_ctlp); 878 879 /* remove the interrupts */ 880 ahci_rem_intrs(ahci_ctlp); 881 882 /* destroy the taskq */ 883 ddi_taskq_destroy(ahci_ctlp->ahcictl_event_taskq); 884 885 /* deallocate the ports structures */ 886 ahci_dealloc_ports_state(ahci_ctlp); 887 888 /* destroy mutex */ 889 mutex_destroy(&ahci_ctlp->ahcictl_mutex); 890 891 /* teardown the pci config */ 892 pci_config_teardown(&ahci_ctlp->ahcictl_pci_conf_handle); 893 894 /* remove the reg maps. */ 895 ddi_regs_map_free(&ahci_ctlp->ahcictl_ahci_acc_handle); 896 897 /* free the soft state. */ 898 ddi_soft_state_free(ahci_statep, instance); 899 900 return (DDI_SUCCESS); 901 902 case DDI_SUSPEND: 903 904 /* 905 * The steps associated with suspension must include putting 906 * the underlying device into a quiescent state so that it 907 * will not generate interrupts or modify or access memory. 908 */ 909 mutex_enter(&ahci_ctlp->ahcictl_mutex); 910 if (ahci_ctlp->ahcictl_flags & AHCI_SUSPEND) { 911 mutex_exit(&ahci_ctlp->ahcictl_mutex); 912 return (DDI_SUCCESS); 913 } 914 915 ahci_ctlp->ahcictl_flags |= AHCI_SUSPEND; 916 917 /* stop the watchdog handler */ 918 if (ahci_ctlp->ahcictl_timeout_id) { 919 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 920 ahci_ctlp->ahcictl_timeout_id = 0; 921 } 922 923 mutex_exit(&ahci_ctlp->ahcictl_mutex); 924 925 /* 926 * drain the taskq 927 */ 928 ddi_taskq_wait(ahci_ctlp->ahcictl_event_taskq); 929 930 /* 931 * Disable the interrupts and stop all the ports. 932 */ 933 ahci_uninitialize_controller(ahci_ctlp); 934 935 return (DDI_SUCCESS); 936 937 default: 938 return (DDI_FAILURE); 939 } 940 } 941 942 /* 943 * The info entry point for dev_ops. 944 * 945 */ 946 static int 947 ahci_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd, 948 void *arg, void **result) 949 { 950 #ifndef __lock_lint 951 _NOTE(ARGUNUSED(dip)) 952 #endif /* __lock_lint */ 953 954 ahci_ctl_t *ahci_ctlp; 955 int instance; 956 dev_t dev; 957 958 dev = (dev_t)arg; 959 instance = getminor(dev); 960 961 switch (infocmd) { 962 case DDI_INFO_DEVT2DEVINFO: 963 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 964 if (ahci_ctlp != NULL) { 965 *result = ahci_ctlp->ahcictl_dip; 966 return (DDI_SUCCESS); 967 } else { 968 *result = NULL; 969 return (DDI_FAILURE); 970 } 971 case DDI_INFO_DEVT2INSTANCE: 972 *(int *)result = instance; 973 break; 974 default: 975 break; 976 } 977 978 return (DDI_SUCCESS); 979 } 980 981 /* 982 * Registers the ahci with sata framework. 983 */ 984 static int 985 ahci_register_sata_hba_tran(ahci_ctl_t *ahci_ctlp, uint32_t cap_status) 986 { 987 struct sata_hba_tran *sata_hba_tran; 988 989 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 990 "ahci_register_sata_hba_tran enter"); 991 992 mutex_enter(&ahci_ctlp->ahcictl_mutex); 993 994 /* Allocate memory for the sata_hba_tran */ 995 sata_hba_tran = kmem_zalloc(sizeof (sata_hba_tran_t), KM_SLEEP); 996 997 sata_hba_tran->sata_tran_hba_rev = SATA_TRAN_HBA_REV_2; 998 sata_hba_tran->sata_tran_hba_dip = ahci_ctlp->ahcictl_dip; 999 sata_hba_tran->sata_tran_hba_dma_attr = 1000 &ahci_ctlp->ahcictl_buffer_dma_attr; 1001 1002 /* Report the number of implemented ports */ 1003 sata_hba_tran->sata_tran_hba_num_cports = 1004 ahci_ctlp->ahcictl_num_implemented_ports; 1005 1006 /* Support ATAPI device */ 1007 sata_hba_tran->sata_tran_hba_features_support = SATA_CTLF_ATAPI; 1008 1009 /* Get the data transfer capability for PIO command by the HBA */ 1010 if (cap_status & AHCI_HBA_CAP_PMD) { 1011 ahci_ctlp->ahcictl_cap |= AHCI_CAP_PIO_MDRQ; 1012 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "HBA supports multiple " 1013 "DRQ block data transfer for PIO command protocol"); 1014 } 1015 1016 /* 1017 * According to the AHCI spec, the ATA/ATAPI-7 queued feature set 1018 * is not supported by AHCI (including the READ QUEUED (EXT), WRITE 1019 * QUEUED (EXT), and SERVICE commands). Queued operations are 1020 * supported in AHCI using the READ FPDMA QUEUED and WRITE FPDMA 1021 * QUEUED commands when the HBA and device support native command 1022 * queuing(NCQ). 1023 * 1024 * SATA_CTLF_NCQ will be set to sata_tran_hba_features_support if the 1025 * CAP register of the HBA indicates NCQ is supported. 1026 * 1027 * SATA_CTLF_NCQ cannot be set if AHCI_CAP_NO_MCMDLIST_NONQUEUE is 1028 * set because the previous register content of PxCI can be re-written 1029 * in the register write. 1030 */ 1031 if ((cap_status & AHCI_HBA_CAP_SNCQ) && 1032 !(ahci_ctlp->ahcictl_cap & AHCI_CAP_NO_MCMDLIST_NONQUEUE)) { 1033 sata_hba_tran->sata_tran_hba_features_support |= SATA_CTLF_NCQ; 1034 ahci_ctlp->ahcictl_cap |= AHCI_CAP_NCQ; 1035 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "HBA supports Native " 1036 "Command Queuing"); 1037 } 1038 1039 /* Report the number of command slots */ 1040 sata_hba_tran->sata_tran_hba_qdepth = ahci_ctlp->ahcictl_num_cmd_slots; 1041 1042 sata_hba_tran->sata_tran_probe_port = ahci_tran_probe_port; 1043 sata_hba_tran->sata_tran_start = ahci_tran_start; 1044 sata_hba_tran->sata_tran_abort = ahci_tran_abort; 1045 sata_hba_tran->sata_tran_reset_dport = ahci_tran_reset_dport; 1046 sata_hba_tran->sata_tran_hotplug_ops = &ahci_tran_hotplug_ops; 1047 #ifdef __lock_lint 1048 sata_hba_tran->sata_tran_selftest = ahci_selftest; 1049 #endif 1050 /* 1051 * When SATA framework adds support for pwrmgt the 1052 * pwrmgt_ops needs to be updated 1053 */ 1054 sata_hba_tran->sata_tran_pwrmgt_ops = NULL; 1055 sata_hba_tran->sata_tran_ioctl = NULL; 1056 1057 ahci_ctlp->ahcictl_sata_hba_tran = sata_hba_tran; 1058 1059 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1060 1061 /* Attach it to SATA framework */ 1062 if (sata_hba_attach(ahci_ctlp->ahcictl_dip, sata_hba_tran, DDI_ATTACH) 1063 != DDI_SUCCESS) { 1064 kmem_free((void *)sata_hba_tran, sizeof (sata_hba_tran_t)); 1065 mutex_enter(&ahci_ctlp->ahcictl_mutex); 1066 ahci_ctlp->ahcictl_sata_hba_tran = NULL; 1067 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1068 return (AHCI_FAILURE); 1069 } 1070 1071 return (AHCI_SUCCESS); 1072 } 1073 1074 /* 1075 * Unregisters the ahci with sata framework. 1076 */ 1077 static int 1078 ahci_unregister_sata_hba_tran(ahci_ctl_t *ahci_ctlp) 1079 { 1080 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, 1081 "ahci_unregister_sata_hba_tran enter"); 1082 1083 /* Detach from the SATA framework. */ 1084 if (sata_hba_detach(ahci_ctlp->ahcictl_dip, DDI_DETACH) != 1085 DDI_SUCCESS) { 1086 return (AHCI_FAILURE); 1087 } 1088 1089 /* Deallocate sata_hba_tran. */ 1090 kmem_free((void *)ahci_ctlp->ahcictl_sata_hba_tran, 1091 sizeof (sata_hba_tran_t)); 1092 1093 mutex_enter(&ahci_ctlp->ahcictl_mutex); 1094 ahci_ctlp->ahcictl_sata_hba_tran = NULL; 1095 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1096 1097 return (AHCI_SUCCESS); 1098 } 1099 1100 /* 1101 * ahci_tran_probe_port is called by SATA framework. It returns port state, 1102 * port status registers and an attached device type via sata_device 1103 * structure. 1104 * 1105 * We return the cached information from a previous hardware probe. The 1106 * actual hardware probing itself was done either from within 1107 * ahci_initialize_controller() during the driver attach or from a phy 1108 * ready change interrupt handler. 1109 */ 1110 static int 1111 ahci_tran_probe_port(dev_info_t *dip, sata_device_t *sd) 1112 { 1113 ahci_ctl_t *ahci_ctlp; 1114 ahci_port_t *ahci_portp; 1115 uint8_t cport = sd->satadev_addr.cport; 1116 #if AHCI_DEBUG 1117 uint8_t pmport = sd->satadev_addr.pmport; 1118 uint8_t qual = sd->satadev_addr.qual; 1119 #endif 1120 uint8_t device_type; 1121 uint32_t port_state; 1122 uint8_t port; 1123 1124 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1125 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1126 1127 AHCIDBG3(AHCIDBG_ENTRY, ahci_ctlp, 1128 "ahci_tran_probe_port enter: cport: %d, " 1129 "pmport: %d, qual: %d", cport, pmport, qual); 1130 1131 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1132 1133 mutex_enter(&ahci_portp->ahciport_mutex); 1134 1135 port_state = ahci_portp->ahciport_port_state; 1136 switch (port_state) { 1137 1138 case SATA_PSTATE_FAILED: 1139 sd->satadev_state = SATA_PSTATE_FAILED; 1140 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1141 "ahci_tran_probe_port: port %d PORT FAILED", port); 1142 goto out; 1143 1144 case SATA_PSTATE_SHUTDOWN: 1145 sd->satadev_state = SATA_PSTATE_SHUTDOWN; 1146 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1147 "ahci_tran_probe_port: port %d PORT SHUTDOWN", port); 1148 goto out; 1149 1150 case SATA_PSTATE_PWROFF: 1151 sd->satadev_state = SATA_PSTATE_PWROFF; 1152 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1153 "ahci_tran_probe_port: port %d PORT PWROFF", port); 1154 goto out; 1155 1156 case SATA_PSTATE_PWRON: 1157 sd->satadev_state = SATA_PSTATE_PWRON; 1158 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1159 "ahci_tran_probe_port: port %d PORT PWRON", port); 1160 break; 1161 1162 default: 1163 sd->satadev_state = port_state; 1164 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 1165 "ahci_tran_probe_port: port %d PORT NORMAL %x", 1166 port, port_state); 1167 break; 1168 } 1169 1170 device_type = ahci_portp->ahciport_device_type; 1171 1172 switch (device_type) { 1173 1174 case SATA_DTYPE_ATADISK: 1175 sd->satadev_type = SATA_DTYPE_ATADISK; 1176 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1177 "ahci_tran_probe_port: port %d DISK found", port); 1178 break; 1179 1180 case SATA_DTYPE_ATAPICD: 1181 sd->satadev_type = SATA_DTYPE_ATAPICD; 1182 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1183 "ahci_tran_probe_port: port %d ATAPI found", port); 1184 break; 1185 1186 case SATA_DTYPE_PMULT: 1187 sd->satadev_type = SATA_DTYPE_PMULT; 1188 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1189 "ahci_tran_probe_port: port %d Port Multiplier found", 1190 port); 1191 break; 1192 1193 case SATA_DTYPE_UNKNOWN: 1194 sd->satadev_type = SATA_DTYPE_UNKNOWN; 1195 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1196 "ahci_tran_probe_port: port %d Unknown device found", port); 1197 break; 1198 1199 default: 1200 /* we don't support any other device types */ 1201 sd->satadev_type = SATA_DTYPE_NONE; 1202 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1203 "ahci_tran_probe_port: port %d No device found", port); 1204 break; 1205 } 1206 1207 out: 1208 ahci_update_sata_registers(ahci_ctlp, port, sd); 1209 mutex_exit(&ahci_portp->ahciport_mutex); 1210 1211 return (SATA_SUCCESS); 1212 } 1213 1214 /* 1215 * There are four operation modes in sata framework: 1216 * SATA_OPMODE_INTERRUPTS 1217 * SATA_OPMODE_POLLING 1218 * SATA_OPMODE_ASYNCH 1219 * SATA_OPMODE_SYNCH 1220 * 1221 * Their combined meanings as following: 1222 * 1223 * SATA_OPMODE_SYNCH 1224 * The command has to be completed before sata_tran_start functions returns. 1225 * Either interrupts or polling could be used - it's up to the driver. 1226 * Mode used currently for internal, sata-module initiated operations. 1227 * 1228 * SATA_OPMODE_SYNCH | SATA_OPMODE_INTERRUPTS 1229 * It is the same as the one above. 1230 * 1231 * SATA_OPMODE_SYNCH | SATA_OPMODE_POLLING 1232 * The command has to be completed before sata_tran_start function returns. 1233 * No interrupt used, polling only. This should be the mode used for scsi 1234 * packets with FLAG_NOINTR. 1235 * 1236 * SATA_OPMODE_ASYNCH | SATA_OPMODE_INTERRUPTS 1237 * The command may be queued (callback function specified). Interrupts could 1238 * be used. It's normal operation mode. 1239 */ 1240 /* 1241 * Called by sata framework to transport a sata packet down stream. 1242 */ 1243 static int 1244 ahci_tran_start(dev_info_t *dip, sata_pkt_t *spkt) 1245 { 1246 ahci_ctl_t *ahci_ctlp; 1247 ahci_port_t *ahci_portp; 1248 uint8_t cport = spkt->satapkt_device.satadev_addr.cport; 1249 uint8_t port; 1250 1251 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1252 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1253 1254 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, 1255 "ahci_tran_start enter: cport %d satapkt 0x%p", 1256 cport, (void *)spkt); 1257 1258 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1259 1260 mutex_enter(&ahci_portp->ahciport_mutex); 1261 1262 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 1263 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 1264 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 1265 /* 1266 * In case the targer driver would send the packet before 1267 * sata framework can have the opportunity to process those 1268 * event reports. 1269 */ 1270 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1271 spkt->satapkt_device.satadev_state = 1272 ahci_portp->ahciport_port_state; 1273 ahci_update_sata_registers(ahci_ctlp, port, 1274 &spkt->satapkt_device); 1275 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1276 "ahci_tran_start returning PORT_ERROR while " 1277 "port in FAILED/SHUTDOWN/PWROFF state: " 1278 "port: %d", port); 1279 mutex_exit(&ahci_portp->ahciport_mutex); 1280 return (SATA_TRAN_PORT_ERROR); 1281 } 1282 1283 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 1284 /* 1285 * ahci_intr_phyrdy_change() may have rendered it to 1286 * SATA_DTYPE_NONE. 1287 */ 1288 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1289 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE; 1290 spkt->satapkt_device.satadev_state = 1291 ahci_portp->ahciport_port_state; 1292 ahci_update_sata_registers(ahci_ctlp, port, 1293 &spkt->satapkt_device); 1294 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1295 "ahci_tran_start returning PORT_ERROR while " 1296 "no device attached: port: %d", port); 1297 mutex_exit(&ahci_portp->ahciport_mutex); 1298 return (SATA_TRAN_PORT_ERROR); 1299 } 1300 1301 /* 1302 * SATA HBA driver should remember that a device was reset and it 1303 * is supposed to reject any packets which do not specify either 1304 * SATA_IGNORE_DEV_RESET_STATE or SATA_CLEAR_DEV_RESET_STATE. 1305 * 1306 * This is to prevent a race condition when a device was arbitrarily 1307 * reset by the HBA driver (and lost it's setting) and a target 1308 * driver sending some commands to a device before the sata framework 1309 * has a chance to restore the device setting (such as cache enable/ 1310 * disable or other resettable stuff). 1311 */ 1312 if (spkt->satapkt_cmd.satacmd_flags.sata_clear_dev_reset) { 1313 ahci_portp->ahciport_reset_in_progress = 0; 1314 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1315 "ahci_tran_start clearing the " 1316 "reset_in_progress for port: %d", port); 1317 } 1318 1319 if (ahci_portp->ahciport_reset_in_progress && 1320 ! spkt->satapkt_cmd.satacmd_flags.sata_ignore_dev_reset && 1321 ! ddi_in_panic()) { 1322 spkt->satapkt_reason = SATA_PKT_BUSY; 1323 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1324 "ahci_tran_start returning BUSY while " 1325 "reset in progress: port: %d", port); 1326 mutex_exit(&ahci_portp->ahciport_mutex); 1327 return (SATA_TRAN_BUSY); 1328 } 1329 1330 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 1331 spkt->satapkt_reason = SATA_PKT_BUSY; 1332 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1333 "ahci_tran_start returning BUSY while " 1334 "mopping in progress: port: %d", port); 1335 mutex_exit(&ahci_portp->ahciport_mutex); 1336 return (SATA_TRAN_BUSY); 1337 } 1338 1339 if (spkt->satapkt_op_mode & 1340 (SATA_OPMODE_SYNCH | SATA_OPMODE_POLLING)) { 1341 /* 1342 * If a SYNC command to be executed in interrupt context, 1343 * bounce it back to sata module. 1344 */ 1345 if (!(spkt->satapkt_op_mode & SATA_OPMODE_POLLING) && 1346 servicing_interrupt()) { 1347 spkt->satapkt_reason = SATA_PKT_BUSY; 1348 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1349 "ahci_tran_start returning BUSY while " 1350 "sending SYNC mode under interrupt context: " 1351 "port : %d", port); 1352 mutex_exit(&ahci_portp->ahciport_mutex); 1353 return (SATA_TRAN_BUSY); 1354 } 1355 1356 /* We need to do the sync start now */ 1357 if (ahci_do_sync_start(ahci_ctlp, ahci_portp, port, 1358 spkt) == AHCI_FAILURE) { 1359 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_tran_start " 1360 "return QUEUE_FULL: port %d", port); 1361 mutex_exit(&ahci_portp->ahciport_mutex); 1362 return (SATA_TRAN_QUEUE_FULL); 1363 } 1364 } else { 1365 /* Async start, using interrupt */ 1366 if (ahci_deliver_satapkt(ahci_ctlp, ahci_portp, port, spkt) 1367 == AHCI_FAILURE) { 1368 spkt->satapkt_reason = SATA_PKT_QUEUE_FULL; 1369 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_tran_start " 1370 "returning QUEUE_FULL: port %d", port); 1371 mutex_exit(&ahci_portp->ahciport_mutex); 1372 return (SATA_TRAN_QUEUE_FULL); 1373 } 1374 } 1375 1376 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_tran_start " 1377 "sata tran accepted: port %d", port); 1378 1379 mutex_exit(&ahci_portp->ahciport_mutex); 1380 return (SATA_TRAN_ACCEPTED); 1381 } 1382 1383 /* 1384 * SATA_OPMODE_SYNCH flag is set 1385 * 1386 * If SATA_OPMODE_POLLING flag is set, then we must poll the command 1387 * without interrupt, otherwise we can still use the interrupt. 1388 * 1389 * WARNING!!! ahciport_mutex should be acquired before the function 1390 * is called. 1391 */ 1392 static int 1393 ahci_do_sync_start(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 1394 uint8_t port, sata_pkt_t *spkt) 1395 { 1396 int pkt_timeout_ticks; 1397 uint32_t timeout_tags; 1398 int rval; 1399 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 1400 1401 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, "ahci_do_sync_start enter: " 1402 "port %d spkt 0x%p", port, spkt); 1403 1404 if (spkt->satapkt_op_mode & SATA_OPMODE_POLLING) { 1405 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_POLLING; 1406 if ((rval = ahci_deliver_satapkt(ahci_ctlp, ahci_portp, 1407 port, spkt)) == AHCI_FAILURE) { 1408 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_POLLING; 1409 return (rval); 1410 } 1411 1412 pkt_timeout_ticks = 1413 drv_usectohz((clock_t)spkt->satapkt_time * 1000000); 1414 1415 while (spkt->satapkt_reason == SATA_PKT_BUSY) { 1416 mutex_exit(&ahci_portp->ahciport_mutex); 1417 1418 /* Simulate the interrupt */ 1419 ahci_port_intr(ahci_ctlp, ahci_portp, port); 1420 1421 drv_usecwait(AHCI_1MS_USECS); 1422 1423 mutex_enter(&ahci_portp->ahciport_mutex); 1424 pkt_timeout_ticks -= AHCI_1MS_TICKS; 1425 if (pkt_timeout_ticks < 0) { 1426 cmn_err(CE_WARN, "!ahci%d: ahci_do_sync_start " 1427 "port %d satapkt 0x%p timed out\n", 1428 instance, port, (void *)spkt); 1429 timeout_tags = (0x1 << rval); 1430 mutex_exit(&ahci_portp->ahciport_mutex); 1431 ahci_timeout_pkts(ahci_ctlp, ahci_portp, 1432 port, timeout_tags); 1433 mutex_enter(&ahci_portp->ahciport_mutex); 1434 } 1435 } 1436 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_POLLING; 1437 return (AHCI_SUCCESS); 1438 1439 } else { 1440 if ((rval = ahci_deliver_satapkt(ahci_ctlp, ahci_portp, 1441 port, spkt)) == AHCI_FAILURE) 1442 return (rval); 1443 1444 #if AHCI_DEBUG 1445 /* 1446 * Note that the driver always uses the slot 0 to deliver 1447 * REQUEST SENSE or READ LOG EXT command 1448 */ 1449 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1450 ASSERT(rval == 0); 1451 #endif 1452 1453 while (spkt->satapkt_reason == SATA_PKT_BUSY) 1454 cv_wait(&ahci_portp->ahciport_cv, 1455 &ahci_portp->ahciport_mutex); 1456 1457 return (AHCI_SUCCESS); 1458 } 1459 } 1460 1461 #define SENDUP_PACKET(ahci_portp, satapkt, reason) \ 1462 if (satapkt) { \ 1463 satapkt->satapkt_reason = reason; \ 1464 /* \ 1465 * We set the satapkt_reason in both sync and \ 1466 * non-sync cases. \ 1467 */ \ 1468 } \ 1469 if (satapkt && \ 1470 ! (satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) && \ 1471 satapkt->satapkt_comp) { \ 1472 mutex_exit(&ahci_portp->ahciport_mutex); \ 1473 (*satapkt->satapkt_comp)(satapkt); \ 1474 mutex_enter(&ahci_portp->ahciport_mutex); \ 1475 } else { \ 1476 if (satapkt && \ 1477 (satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) && \ 1478 ! (satapkt->satapkt_op_mode & SATA_OPMODE_POLLING)) \ 1479 cv_signal(&ahci_portp->ahciport_cv); \ 1480 } 1481 1482 /* 1483 * Searches for and claims a free command slot. 1484 * 1485 * Returns: 1486 * 1487 * AHCI_FAILURE if failed 1488 * 1. if no empty slot left 1489 * 2. non-queued command requested while queued command(s) is outstanding 1490 * 3. queued command requested whild non-queued command(s) is outstanding 1491 * 4. HBA doesn't support multiple-use of command list while already a 1492 * non-queued command is oustanding 1493 * 1494 * claimed slot number if succeeded 1495 * 1496 * NOTE: it will always return slot 0 during error recovery process for 1497 * REQUEST SENSE or READ LOG EXT command to simplify the algorithm. 1498 * 1499 * WARNING!!! ahciport_mutex should be acquired before the function 1500 * is called. 1501 */ 1502 static int 1503 ahci_claim_free_slot(ahci_ctl_t *ahci_ctlp, 1504 ahci_port_t *ahci_portp, int command_type) 1505 { 1506 uint32_t free_slots; 1507 int slot; 1508 1509 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, "ahci_claim_free_slot enter " 1510 "ahciport_pending_tags = 0x%x " 1511 "ahciport_pending_ncq_tags = 0x%x", 1512 ahci_portp->ahciport_pending_tags, 1513 ahci_portp->ahciport_pending_ncq_tags); 1514 1515 /* 1516 * According to the AHCI spec, system software is responsible to 1517 * ensure that queued and non-queued commands are not mixed in 1518 * the command list. 1519 */ 1520 if (command_type == AHCI_NON_NCQ_CMD) { 1521 /* Non-NCQ command request */ 1522 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1523 AHCIDBG0(AHCIDBG_INFO|AHCIDBG_NCQ, ahci_ctlp, 1524 "ahci_claim_free_slot: there is still pending " 1525 "queued command(s) in the command list, " 1526 "so no available slot for the non-queued " 1527 "command"); 1528 return (AHCI_FAILURE); 1529 } 1530 if ((ahci_ctlp->ahcictl_cap & AHCI_CAP_NO_MCMDLIST_NONQUEUE) && 1531 NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1532 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 1533 "ahci_claim_free_slot: HBA cannot support multiple-" 1534 "use of the command list for non-queued commands"); 1535 return (AHCI_FAILURE); 1536 } 1537 free_slots = (~ahci_portp->ahciport_pending_tags) & 1538 AHCI_SLOT_MASK(ahci_ctlp); 1539 } else if (command_type == AHCI_NCQ_CMD) { 1540 /* NCQ command request */ 1541 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1542 AHCIDBG0(AHCIDBG_INFO|AHCIDBG_NCQ, ahci_ctlp, 1543 "ahci_claim_free_slot: there is still pending " 1544 "non-queued command(s) in the command list, " 1545 "so no available slot for the queued command"); 1546 return (AHCI_FAILURE); 1547 } 1548 free_slots = (~ahci_portp->ahciport_pending_ncq_tags) & 1549 AHCI_NCQ_SLOT_MASK(ahci_portp); 1550 } else if (command_type == AHCI_ERR_RETRI_CMD) { 1551 /* Error retrieval command request */ 1552 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 1553 "ahci_claim_free_slot: slot 0 is allocated for REQUEST " 1554 "SENSE or READ LOG EXT command"); 1555 slot = 0; 1556 goto out; 1557 } 1558 1559 slot = ddi_ffs(free_slots) - 1; 1560 if (slot == -1) { 1561 AHCIDBG0(AHCIDBG_VERBOSE, ahci_ctlp, 1562 "ahci_claim_free_slot: no empty slots"); 1563 return (AHCI_FAILURE); 1564 } 1565 1566 /* 1567 * According to the AHCI spec, to allow a simple mechanism for the 1568 * HBA to map command list slots to queue entries, software must 1569 * match the tag number it uses to the slot it is placing the command 1570 * in. For example, if a queued command is placed in slot 5, the tag 1571 * for that command must be 5. 1572 */ 1573 if (command_type == AHCI_NCQ_CMD) { 1574 ahci_portp->ahciport_pending_ncq_tags |= (0x1 << slot); 1575 } 1576 1577 ahci_portp->ahciport_pending_tags |= (0x1 << slot); 1578 1579 out: 1580 AHCIDBG1(AHCIDBG_VERBOSE, ahci_ctlp, 1581 "ahci_claim_free_slot: found slot: 0x%x", slot); 1582 1583 return (slot); 1584 } 1585 1586 /* 1587 * Builds the Command Table for the sata packet and delivers it to controller. 1588 * 1589 * Returns: 1590 * slot number if we can obtain a slot successfully 1591 * otherwise, return AHCI_FAILURE 1592 * 1593 * WARNING!!! ahciport_mutex should be acquired before the function is called. 1594 */ 1595 static int 1596 ahci_deliver_satapkt(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 1597 uint8_t port, sata_pkt_t *spkt) 1598 { 1599 int cmd_slot; 1600 sata_cmd_t *scmd; 1601 ahci_fis_h2d_register_t *h2d_register_fisp; 1602 ahci_cmd_table_t *cmd_table; 1603 ahci_cmd_header_t *cmd_header; 1604 int ncookies; 1605 int i; 1606 int command_type = AHCI_NON_NCQ_CMD; 1607 int ncq_qdepth; 1608 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 1609 #if AHCI_DEBUG 1610 uint32_t *ptr; 1611 uint8_t *ptr2; 1612 #endif 1613 1614 spkt->satapkt_reason = SATA_PKT_BUSY; 1615 1616 scmd = &spkt->satapkt_cmd; 1617 1618 /* Check if the command is a NCQ command */ 1619 if (scmd->satacmd_cmd_reg == SATAC_READ_FPDMA_QUEUED || 1620 scmd->satacmd_cmd_reg == SATAC_WRITE_FPDMA_QUEUED) { 1621 command_type = AHCI_NCQ_CMD; 1622 1623 /* 1624 * When NCQ is support, system software must determine the 1625 * maximum tag allowed by the device and the HBA, and it 1626 * must use a value not beyond of the lower bound of the two. 1627 * 1628 * Sata module is going to calculate the qdepth and send 1629 * down to HBA driver via sata_cmd. 1630 */ 1631 ncq_qdepth = scmd->satacmd_flags.sata_max_queue_depth + 1; 1632 1633 /* 1634 * At the moment, the driver doesn't support the dynamic 1635 * setting of the maximum ncq depth, and the value can be 1636 * set either during the attach or after hot-plug insertion. 1637 */ 1638 if (ahci_portp->ahciport_max_ncq_tags == 0) { 1639 ahci_portp->ahciport_max_ncq_tags = ncq_qdepth; 1640 AHCIDBG2(AHCIDBG_NCQ, ahci_ctlp, 1641 "ahci_deliver_satapkt: port %d the max tags for " 1642 "NCQ command is %d", port, ncq_qdepth); 1643 } else { 1644 if (ncq_qdepth != ahci_portp->ahciport_max_ncq_tags) { 1645 cmn_err(CE_WARN, "!ahci%d: ahci_deliver_satapkt" 1646 " port %d the max tag for NCQ command is " 1647 "requested to change from %d to %d, at the" 1648 " moment the driver doesn't support the " 1649 "dynamic change so it's going to " 1650 "still use the previous tag value", 1651 instance, port, 1652 ahci_portp->ahciport_max_ncq_tags, 1653 ncq_qdepth); 1654 } 1655 } 1656 } 1657 1658 /* Check if the command is an error retrieval command */ 1659 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1660 command_type = AHCI_ERR_RETRI_CMD; 1661 1662 /* Check if there is an empty command slot */ 1663 cmd_slot = ahci_claim_free_slot(ahci_ctlp, ahci_portp, command_type); 1664 if (cmd_slot == AHCI_FAILURE) { 1665 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "no free command slot"); 1666 return (AHCI_FAILURE); 1667 } 1668 1669 AHCIDBG4(AHCIDBG_ENTRY|AHCIDBG_INFO, ahci_ctlp, 1670 "ahci_deliver_satapkt enter: cmd_reg: 0x%x, cmd_slot: 0x%x, " 1671 "port: %d, satapkt: 0x%p", scmd->satacmd_cmd_reg, 1672 cmd_slot, port, (void *)spkt); 1673 1674 cmd_table = ahci_portp->ahciport_cmd_tables[cmd_slot]; 1675 bzero((void *)cmd_table, ahci_cmd_table_size); 1676 1677 /* For data transfer operations, it is the H2D Register FIS */ 1678 h2d_register_fisp = 1679 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 1680 1681 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 1682 if ((spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_PMPORT) || 1683 (spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_DPMPORT)) { 1684 SET_FIS_PMP(h2d_register_fisp, 1685 spkt->satapkt_device.satadev_addr.pmport); 1686 } 1687 1688 SET_FIS_CDMDEVCTL(h2d_register_fisp, 1); 1689 SET_FIS_COMMAND(h2d_register_fisp, scmd->satacmd_cmd_reg); 1690 SET_FIS_FEATURES(h2d_register_fisp, scmd->satacmd_features_reg); 1691 SET_FIS_SECTOR_COUNT(h2d_register_fisp, scmd->satacmd_sec_count_lsb); 1692 1693 switch (scmd->satacmd_addr_type) { 1694 1695 case 0: 1696 /* 1697 * satacmd_addr_type will be 0 for the commands below: 1698 * ATAPI command 1699 * SATAC_IDLE_IM 1700 * SATAC_STANDBY_IM 1701 * SATAC_DOWNLOAD_MICROCODE 1702 * SATAC_FLUSH_CACHE 1703 * SATAC_SET_FEATURES 1704 * SATAC_SMART 1705 * SATAC_ID_PACKET_DEVICE 1706 * SATAC_ID_DEVICE 1707 */ 1708 /* FALLTHRU */ 1709 1710 case ATA_ADDR_LBA: 1711 /* FALLTHRU */ 1712 1713 case ATA_ADDR_LBA28: 1714 /* LBA[7:0] */ 1715 SET_FIS_SECTOR(h2d_register_fisp, scmd->satacmd_lba_low_lsb); 1716 1717 /* LBA[15:8] */ 1718 SET_FIS_CYL_LOW(h2d_register_fisp, scmd->satacmd_lba_mid_lsb); 1719 1720 /* LBA[23:16] */ 1721 SET_FIS_CYL_HI(h2d_register_fisp, scmd->satacmd_lba_high_lsb); 1722 1723 /* LBA [27:24] (also called dev_head) */ 1724 SET_FIS_DEV_HEAD(h2d_register_fisp, scmd->satacmd_device_reg); 1725 1726 break; 1727 1728 case ATA_ADDR_LBA48: 1729 /* LBA[7:0] */ 1730 SET_FIS_SECTOR(h2d_register_fisp, scmd->satacmd_lba_low_lsb); 1731 1732 /* LBA[15:8] */ 1733 SET_FIS_CYL_LOW(h2d_register_fisp, scmd->satacmd_lba_mid_lsb); 1734 1735 /* LBA[23:16] */ 1736 SET_FIS_CYL_HI(h2d_register_fisp, scmd->satacmd_lba_high_lsb); 1737 1738 /* LBA [31:24] */ 1739 SET_FIS_SECTOR_EXP(h2d_register_fisp, 1740 scmd->satacmd_lba_low_msb); 1741 1742 /* LBA [39:32] */ 1743 SET_FIS_CYL_LOW_EXP(h2d_register_fisp, 1744 scmd->satacmd_lba_mid_msb); 1745 1746 /* LBA [47:40] */ 1747 SET_FIS_CYL_HI_EXP(h2d_register_fisp, 1748 scmd->satacmd_lba_high_msb); 1749 1750 /* Set dev_head */ 1751 SET_FIS_DEV_HEAD(h2d_register_fisp, 1752 scmd->satacmd_device_reg); 1753 1754 /* Set the extended sector count and features */ 1755 SET_FIS_SECTOR_COUNT_EXP(h2d_register_fisp, 1756 scmd->satacmd_sec_count_msb); 1757 SET_FIS_FEATURES_EXP(h2d_register_fisp, 1758 scmd->satacmd_features_reg_ext); 1759 break; 1760 } 1761 1762 /* 1763 * For NCQ command (READ/WRITE FPDMA QUEUED), sector count 7:0 is 1764 * filled into features field, and sector count 8:15 is filled into 1765 * features (exp) field. TAG is filled into sector field. 1766 */ 1767 if (command_type == AHCI_NCQ_CMD) { 1768 SET_FIS_FEATURES(h2d_register_fisp, 1769 scmd->satacmd_sec_count_lsb); 1770 SET_FIS_FEATURES_EXP(h2d_register_fisp, 1771 scmd->satacmd_sec_count_msb); 1772 1773 SET_FIS_SECTOR_COUNT(h2d_register_fisp, 1774 (cmd_slot << SATA_TAG_QUEUING_SHIFT)); 1775 } 1776 1777 ncookies = scmd->satacmd_num_dma_cookies; 1778 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 1779 "ncookies = 0x%x, ahci_dma_prdt_number = 0x%x", 1780 ncookies, ahci_dma_prdt_number); 1781 1782 ASSERT(ncookies <= ahci_dma_prdt_number); 1783 1784 /* *** now fill the scatter gather list ******* */ 1785 for (i = 0; i < ncookies; i++) { 1786 cmd_table->ahcict_prdt[i].ahcipi_data_base_addr = 1787 scmd->satacmd_dma_cookie_list[i]._dmu._dmac_la[0]; 1788 cmd_table->ahcict_prdt[i].ahcipi_data_base_addr_upper = 1789 scmd->satacmd_dma_cookie_list[i]._dmu._dmac_la[1]; 1790 cmd_table->ahcict_prdt[i].ahcipi_descr_info = 1791 scmd->satacmd_dma_cookie_list[i].dmac_size - 1; 1792 } 1793 1794 /* The ACMD field is filled in for ATAPI command */ 1795 if (scmd->satacmd_cmd_reg == SATAC_PACKET) { 1796 bcopy(scmd->satacmd_acdb, cmd_table->ahcict_atapi_cmd, 1797 SATA_ATAPI_MAX_CDB_LEN); 1798 } 1799 1800 /* Set Command Header in Command List */ 1801 cmd_header = &ahci_portp->ahciport_cmd_list[cmd_slot]; 1802 BZERO_DESCR_INFO(cmd_header); 1803 BZERO_PRD_BYTE_COUNT(cmd_header); 1804 1805 /* Set the number of entries in the PRD table */ 1806 SET_PRD_TABLE_LENGTH(cmd_header, ncookies); 1807 1808 /* Set the length of the command in the CFIS area */ 1809 SET_COMMAND_FIS_LENGTH(cmd_header, AHCI_H2D_REGISTER_FIS_LENGTH); 1810 1811 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "command data direction is " 1812 "sata_data_direction = 0x%x", 1813 scmd->satacmd_flags.sata_data_direction); 1814 1815 /* Set A bit if it is an ATAPI command */ 1816 if (scmd->satacmd_cmd_reg == SATAC_PACKET) 1817 SET_ATAPI(cmd_header, AHCI_CMDHEAD_ATAPI); 1818 1819 /* Set W bit if data is going to the device */ 1820 if (scmd->satacmd_flags.sata_data_direction == SATA_DIR_WRITE) 1821 SET_WRITE(cmd_header, AHCI_CMDHEAD_DATA_WRITE); 1822 1823 /* 1824 * Set the prefetchable bit - this bit is only valid if the PRDTL 1825 * field is non-zero or the ATAPI 'A' bit is set in the command 1826 * header. This bit cannot be set when using native command 1827 * queuing commands or when using FIS-based switching with a Port 1828 * multiplier. 1829 */ 1830 if (command_type != AHCI_NCQ_CMD) 1831 SET_PREFETCHABLE(cmd_header, AHCI_CMDHEAD_PREFETCHABLE); 1832 1833 /* Now remember the sata packet in ahciport_slot_pkts[]. */ 1834 if (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1835 ahci_portp->ahciport_slot_pkts[cmd_slot] = spkt; 1836 1837 /* 1838 * We are overloading satapkt_hba_driver_private with 1839 * watched_cycle count. 1840 */ 1841 spkt->satapkt_hba_driver_private = (void *)(intptr_t)0; 1842 1843 #if AHCI_DEBUG 1844 /* Dump the command header and table */ 1845 AHCIDBG0(AHCIDBG_COMMAND, ahci_ctlp, "\n"); 1846 AHCIDBG3(AHCIDBG_COMMAND, ahci_ctlp, 1847 "Command header&table for spkt 0x%p cmd_reg 0x%x port %d", 1848 spkt, scmd->satacmd_cmd_reg, port); 1849 ptr = (uint32_t *)cmd_header; 1850 AHCIDBG4(AHCIDBG_COMMAND, ahci_ctlp, 1851 " Command Header:%8x %8x %8x %8x", 1852 ptr[0], ptr[1], ptr[2], ptr[3]); 1853 1854 /* Dump the H2D register FIS */ 1855 ptr = (uint32_t *)h2d_register_fisp; 1856 AHCIDBG4(AHCIDBG_COMMAND, ahci_ctlp, 1857 " Command FIS: %8x %8x %8x %8x", 1858 ptr[0], ptr[1], ptr[2], ptr[3]); 1859 1860 /* Dump the ACMD register FIS */ 1861 ptr2 = (uint8_t *)&(cmd_table->ahcict_atapi_cmd); 1862 for (i = 0; i < SATA_ATAPI_MAX_CDB_LEN/8; i++) 1863 if (ahci_debug_flags & AHCIDBG_COMMAND) 1864 ahci_log(ahci_ctlp, CE_WARN, 1865 " ATAPI command: %2x %2x %2x %2x " 1866 "%2x %2x %2x %2x", 1867 ptr2[8 * i], ptr2[8 * i + 1], 1868 ptr2[8 * i + 2], ptr2[8 * i + 3], 1869 ptr2[8 * i + 4], ptr2[8 * i + 5], 1870 ptr2[8 * i + 6], ptr2[8 * i + 7]); 1871 1872 /* Dump the PRDT */ 1873 for (i = 0; i < ncookies; i++) { 1874 ptr = (uint32_t *)&(cmd_table->ahcict_prdt[i]); 1875 AHCIDBG5(AHCIDBG_COMMAND, ahci_ctlp, 1876 " Cookie %d: %8x %8x %8x %8x", 1877 i, ptr[0], ptr[1], ptr[2], ptr[3]); 1878 } 1879 #endif 1880 1881 (void) ddi_dma_sync( 1882 ahci_portp->ahciport_cmd_tables_dma_handle[cmd_slot], 1883 0, 1884 ahci_cmd_table_size, 1885 DDI_DMA_SYNC_FORDEV); 1886 1887 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 1888 cmd_slot * sizeof (ahci_cmd_header_t), 1889 sizeof (ahci_cmd_header_t), 1890 DDI_DMA_SYNC_FORDEV); 1891 1892 /* Set the corresponding bit in the PxSACT.DS for queued command */ 1893 if (command_type == AHCI_NCQ_CMD) { 1894 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 1895 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port), 1896 (0x1 << cmd_slot)); 1897 } 1898 1899 /* Indicate to the HBA that a command is active. */ 1900 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 1901 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 1902 (0x1 << cmd_slot)); 1903 1904 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_deliver_satapkt " 1905 "exit: port %d", port); 1906 1907 return (cmd_slot); 1908 } 1909 1910 /* 1911 * Called by the sata framework to abort the previously sent packet(s). 1912 * 1913 * Reset device to abort commands. 1914 */ 1915 static int 1916 ahci_tran_abort(dev_info_t *dip, sata_pkt_t *spkt, int flag) 1917 { 1918 ahci_ctl_t *ahci_ctlp; 1919 ahci_port_t *ahci_portp; 1920 uint32_t slot_status = 0; 1921 uint32_t aborted_tags = 0; 1922 uint32_t finished_tags = 0; 1923 uint8_t cport = spkt->satapkt_device.satadev_addr.cport; 1924 uint8_t port; 1925 int tmp_slot; 1926 int instance = ddi_get_instance(dip); 1927 1928 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 1929 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1930 1931 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 1932 "ahci_tran_abort enter: port %d", port); 1933 1934 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1935 mutex_enter(&ahci_portp->ahciport_mutex); 1936 1937 /* 1938 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 1939 * commands are being mopped, therefore there is nothing else to do 1940 */ 1941 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 1942 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1943 "ahci_tran_abort: port %d is in " 1944 "mopping process, so just return directly ", port); 1945 mutex_exit(&ahci_portp->ahciport_mutex); 1946 return (SATA_SUCCESS); 1947 } 1948 1949 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 1950 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 1951 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 1952 /* 1953 * In case the targer driver would send the request before 1954 * sata framework can have the opportunity to process those 1955 * event reports. 1956 */ 1957 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1958 spkt->satapkt_device.satadev_state = 1959 ahci_portp->ahciport_port_state; 1960 ahci_update_sata_registers(ahci_ctlp, port, 1961 &spkt->satapkt_device); 1962 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1963 "ahci_tran_abort returning SATA_FAILURE while " 1964 "port in FAILED/SHUTDOWN/PWROFF state: " 1965 "port: %d", port); 1966 mutex_exit(&ahci_portp->ahciport_mutex); 1967 return (SATA_FAILURE); 1968 } 1969 1970 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 1971 /* 1972 * ahci_intr_phyrdy_change() may have rendered it to 1973 * AHCI_PORT_TYPE_NODEV. 1974 */ 1975 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1976 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE; 1977 spkt->satapkt_device.satadev_state = 1978 ahci_portp->ahciport_port_state; 1979 ahci_update_sata_registers(ahci_ctlp, port, 1980 &spkt->satapkt_device); 1981 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1982 "ahci_tran_abort returning SATA_FAILURE while " 1983 "no device attached: port: %d", port); 1984 mutex_exit(&ahci_portp->ahciport_mutex); 1985 return (SATA_FAILURE); 1986 } 1987 1988 if (flag == SATA_ABORT_ALL_PACKETS) { 1989 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 1990 aborted_tags = ahci_portp->ahciport_pending_tags; 1991 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 1992 aborted_tags = ahci_portp->ahciport_pending_ncq_tags; 1993 1994 cmn_err(CE_NOTE, "!ahci%d: ahci port %d abort all packets", 1995 instance, port); 1996 } else { 1997 aborted_tags = 0xffffffff; 1998 /* 1999 * Aborting one specific packet, first search the 2000 * ahciport_slot_pkts[] list for matching spkt. 2001 */ 2002 for (tmp_slot = 0; 2003 tmp_slot < ahci_ctlp->ahcictl_num_cmd_slots; tmp_slot++) { 2004 if (ahci_portp->ahciport_slot_pkts[tmp_slot] == spkt) { 2005 aborted_tags = (0x1 << tmp_slot); 2006 break; 2007 } 2008 } 2009 2010 if (aborted_tags == 0xffffffff) { 2011 /* request packet is not on the pending list */ 2012 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 2013 "Cannot find the aborting pkt 0x%p on the " 2014 "pending list", (void *)spkt); 2015 ahci_update_sata_registers(ahci_ctlp, port, 2016 &spkt->satapkt_device); 2017 mutex_exit(&ahci_portp->ahciport_mutex); 2018 return (SATA_FAILURE); 2019 } 2020 cmn_err(CE_NOTE, "!ahci%d: ahci port %d abort satapkt 0x%p", 2021 instance, port, (void *)spkt); 2022 } 2023 2024 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2025 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2026 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2027 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2028 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2029 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2030 2031 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2032 ahci_portp->ahciport_mop_in_progress++; 2033 2034 /* 2035 * To abort the packet(s), first we are trying to clear PxCMD.ST 2036 * to stop the port, and if the port can be stopped 2037 * successfully with PxTFD.STS.BSY and PxTFD.STS.DRQ cleared to '0', 2038 * then we just send back the aborted packet(s) with ABORTED flag 2039 * and then restart the port by setting PxCMD.ST and PxCMD.FRE. 2040 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then we 2041 * perform a COMRESET. 2042 */ 2043 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, 2044 ahci_portp, port, NULL, NULL); 2045 2046 /* 2047 * Compute which have finished and which need to be retried. 2048 * 2049 * The finished tags are ahciport_pending_tags/ahciport_pending_ncq_tags 2050 * minus the slot_status. The aborted_tags has to be deducted by 2051 * finished_tags since we can't possibly abort a tag which had finished 2052 * already. 2053 */ 2054 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2055 finished_tags = ahci_portp->ahciport_pending_tags & 2056 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2057 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2058 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2059 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2060 2061 aborted_tags &= ~finished_tags; 2062 2063 ahci_mop_commands(ahci_ctlp, 2064 ahci_portp, 2065 slot_status, 2066 0, /* failed tags */ 2067 0, /* timeout tags */ 2068 aborted_tags, 2069 0); /* reset tags */ 2070 2071 ahci_update_sata_registers(ahci_ctlp, port, &spkt->satapkt_device); 2072 mutex_exit(&ahci_portp->ahciport_mutex); 2073 2074 return (SATA_SUCCESS); 2075 } 2076 2077 /* 2078 * Used to do device reset and reject all the pending packets on a device 2079 * during the reset operation. 2080 * 2081 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2082 */ 2083 static int 2084 ahci_reset_device_reject_pkts(ahci_ctl_t *ahci_ctlp, 2085 ahci_port_t *ahci_portp, uint8_t port) 2086 { 2087 uint32_t slot_status = 0; 2088 uint32_t reset_tags = 0; 2089 uint32_t finished_tags = 0; 2090 sata_device_t sdevice; 2091 int ret; 2092 2093 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2094 "ahci_reset_device_reject_pkts on port: %d", port); 2095 2096 /* 2097 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 2098 * commands are being mopped, therefore there is nothing else to do 2099 */ 2100 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2101 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2102 "ahci_reset_device_reject_pkts: port %d is in " 2103 "mopping process, so return directly ", port); 2104 return (SATA_SUCCESS); 2105 } 2106 2107 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2108 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2109 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2110 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2111 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2112 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2113 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2114 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2115 } 2116 2117 if (ahci_software_reset(ahci_ctlp, ahci_portp, port) 2118 != AHCI_SUCCESS) { 2119 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2120 "Try to do a port reset after software " 2121 "reset failed", port); 2122 ret = ahci_port_reset(ahci_ctlp, ahci_portp, port); 2123 if (ret != AHCI_SUCCESS) { 2124 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2125 "ahci_reset_device_reject_pkts: port %d " 2126 "failed", port); 2127 return (SATA_FAILURE); 2128 } 2129 } 2130 /* Set the reset in progress flag */ 2131 ahci_portp->ahciport_reset_in_progress = 1; 2132 2133 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2134 ahci_portp->ahciport_mop_in_progress++; 2135 2136 /* Indicate to the framework that a reset has happened */ 2137 bzero((void *)&sdevice, sizeof (sata_device_t)); 2138 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 2139 sdevice.satadev_addr.pmport = 0; 2140 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 2141 2142 sdevice.satadev_state = SATA_DSTATE_RESET | 2143 SATA_DSTATE_PWR_ACTIVE; 2144 mutex_exit(&ahci_portp->ahciport_mutex); 2145 sata_hba_event_notify( 2146 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 2147 &sdevice, 2148 SATA_EVNT_DEVICE_RESET); 2149 mutex_enter(&ahci_portp->ahciport_mutex); 2150 2151 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 2152 "port %d sending event up: SATA_EVNT_RESET", port); 2153 2154 /* Next try to mop the pending commands */ 2155 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2156 finished_tags = ahci_portp->ahciport_pending_tags & 2157 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2158 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2159 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2160 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2161 2162 reset_tags &= ~finished_tags; 2163 2164 ahci_mop_commands(ahci_ctlp, 2165 ahci_portp, 2166 slot_status, 2167 0, /* failed tags */ 2168 0, /* timeout tags */ 2169 0, /* aborted tags */ 2170 reset_tags); /* reset tags */ 2171 2172 return (SATA_SUCCESS); 2173 } 2174 2175 /* 2176 * Used to do port reset and reject all the pending packets on a port during 2177 * the reset operation. 2178 * 2179 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2180 */ 2181 static int 2182 ahci_reset_port_reject_pkts(ahci_ctl_t *ahci_ctlp, 2183 ahci_port_t *ahci_portp, uint8_t port) 2184 { 2185 uint32_t slot_status = 0; 2186 uint32_t reset_tags = 0; 2187 uint32_t finished_tags = 0; 2188 2189 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2190 "ahci_reset_port_reject_pkts on port: %d", port); 2191 2192 /* 2193 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 2194 * commands are being mopped, therefore there is nothing else to do 2195 */ 2196 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2197 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2198 "ahci_reset_port_reject_pkts: port %d is in " 2199 "mopping process, so return directly ", port); 2200 return (SATA_SUCCESS); 2201 } 2202 2203 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2204 ahci_portp->ahciport_mop_in_progress++; 2205 2206 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2207 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2208 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2209 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2210 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2211 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2212 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2213 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2214 } 2215 2216 if (ahci_restart_port_wait_till_ready(ahci_ctlp, 2217 ahci_portp, port, AHCI_PORT_RESET|AHCI_RESET_NO_EVENTS_UP, 2218 NULL) != AHCI_SUCCESS) 2219 return (SATA_FAILURE); 2220 2221 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2222 finished_tags = ahci_portp->ahciport_pending_tags & 2223 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2224 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2225 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2226 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2227 2228 reset_tags &= ~finished_tags; 2229 2230 ahci_mop_commands(ahci_ctlp, 2231 ahci_portp, 2232 slot_status, 2233 0, /* failed tags */ 2234 0, /* timeout tags */ 2235 0, /* aborted tags */ 2236 reset_tags); /* reset tags */ 2237 2238 return (SATA_SUCCESS); 2239 } 2240 2241 /* 2242 * Used to do hba reset and reject all the pending packets on all ports 2243 * during the reset operation. 2244 */ 2245 static int 2246 ahci_reset_hba_reject_pkts(ahci_ctl_t *ahci_ctlp) 2247 { 2248 ahci_port_t *ahci_portp; 2249 uint32_t slot_status[AHCI_MAX_PORTS]; 2250 uint32_t reset_tags[AHCI_MAX_PORTS]; 2251 uint32_t finished_tags[AHCI_MAX_PORTS]; 2252 uint8_t port; 2253 int ret = SATA_SUCCESS; 2254 2255 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, 2256 "ahci_reset_hba_reject_pkts enter"); 2257 2258 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2259 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2260 continue; 2261 } 2262 2263 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2264 2265 mutex_enter(&ahci_portp->ahciport_mutex); 2266 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2267 slot_status[port] = ddi_get32( 2268 ahci_ctlp->ahcictl_ahci_acc_handle, 2269 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2270 reset_tags[port] = slot_status[port] & 2271 AHCI_SLOT_MASK(ahci_ctlp); 2272 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2273 slot_status[port] = ddi_get32( 2274 ahci_ctlp->ahcictl_ahci_acc_handle, 2275 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2276 reset_tags[port] = slot_status[port] & 2277 AHCI_NCQ_SLOT_MASK(ahci_portp); 2278 } 2279 mutex_exit(&ahci_portp->ahciport_mutex); 2280 } 2281 2282 if (ahci_hba_reset(ahci_ctlp) != AHCI_SUCCESS) { 2283 ret = SATA_FAILURE; 2284 goto out; 2285 } 2286 2287 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2288 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2289 continue; 2290 } 2291 2292 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2293 2294 mutex_enter(&ahci_portp->ahciport_mutex); 2295 /* 2296 * To prevent recursive enter to ahci_mop_commands, we need 2297 * check AHCI_PORT_FLAG_MOPPING flag. 2298 */ 2299 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2300 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2301 "ahci_reset_hba_reject_pkts: port %d is in " 2302 "mopping process, so return directly ", port); 2303 mutex_exit(&ahci_portp->ahciport_mutex); 2304 continue; 2305 } 2306 2307 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2308 ahci_portp->ahciport_mop_in_progress++; 2309 2310 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2311 finished_tags[port] = 2312 ahci_portp->ahciport_pending_tags & 2313 ~slot_status[port] & AHCI_SLOT_MASK(ahci_ctlp); 2314 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2315 finished_tags[port] = 2316 ahci_portp->ahciport_pending_ncq_tags & 2317 ~slot_status[port] & AHCI_NCQ_SLOT_MASK(ahci_portp); 2318 2319 reset_tags[port] &= ~finished_tags[port]; 2320 2321 ahci_mop_commands(ahci_ctlp, 2322 ahci_portp, 2323 slot_status[port], 2324 0, /* failed tags */ 2325 0, /* timeout tags */ 2326 0, /* aborted tags */ 2327 reset_tags[port]); /* reset tags */ 2328 mutex_exit(&ahci_portp->ahciport_mutex); 2329 } 2330 out: 2331 return (ret); 2332 } 2333 2334 /* 2335 * Called by sata framework to reset a port(s) or device. 2336 */ 2337 static int 2338 ahci_tran_reset_dport(dev_info_t *dip, sata_device_t *sd) 2339 { 2340 ahci_ctl_t *ahci_ctlp; 2341 ahci_port_t *ahci_portp; 2342 uint8_t cport = sd->satadev_addr.cport; 2343 uint8_t port; 2344 int ret = SATA_SUCCESS; 2345 int instance = ddi_get_instance(dip); 2346 2347 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 2348 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2349 2350 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2351 "ahci_tran_reset_port enter: cport: %d", cport); 2352 2353 switch (sd->satadev_addr.qual) { 2354 case SATA_ADDR_CPORT: 2355 /* Port reset */ 2356 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2357 cmn_err(CE_NOTE, "!ahci%d: ahci_tran_reset_dport port %d " 2358 "reset port", instance, port); 2359 2360 mutex_enter(&ahci_portp->ahciport_mutex); 2361 ret = ahci_reset_port_reject_pkts(ahci_ctlp, ahci_portp, port); 2362 mutex_exit(&ahci_portp->ahciport_mutex); 2363 2364 break; 2365 2366 case SATA_ADDR_DCPORT: 2367 /* Device reset */ 2368 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2369 cmn_err(CE_NOTE, "!ahci%d: ahci_tran_reset_dport port %d " 2370 "reset device", instance, port); 2371 2372 mutex_enter(&ahci_portp->ahciport_mutex); 2373 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 2374 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 2375 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 2376 /* 2377 * In case the targer driver would send the request 2378 * before sata framework can have the opportunity to 2379 * process those event reports. 2380 */ 2381 sd->satadev_state = ahci_portp->ahciport_port_state; 2382 ahci_update_sata_registers(ahci_ctlp, port, sd); 2383 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2384 "ahci_tran_reset_dport returning SATA_FAILURE " 2385 "while port in FAILED/SHUTDOWN/PWROFF state: " 2386 "port: %d", port); 2387 mutex_exit(&ahci_portp->ahciport_mutex); 2388 ret = SATA_FAILURE; 2389 break; 2390 } 2391 2392 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2393 /* 2394 * ahci_intr_phyrdy_change() may have rendered it to 2395 * AHCI_PORT_TYPE_NODEV. 2396 */ 2397 sd->satadev_type = SATA_DTYPE_NONE; 2398 sd->satadev_state = ahci_portp->ahciport_port_state; 2399 ahci_update_sata_registers(ahci_ctlp, port, sd); 2400 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2401 "ahci_tran_reset_dport returning SATA_FAILURE " 2402 "while no device attached: port: %d", port); 2403 mutex_exit(&ahci_portp->ahciport_mutex); 2404 ret = SATA_FAILURE; 2405 break; 2406 } 2407 2408 ret = ahci_reset_device_reject_pkts(ahci_ctlp, 2409 ahci_portp, port); 2410 mutex_exit(&ahci_portp->ahciport_mutex); 2411 break; 2412 2413 case SATA_ADDR_CNTRL: 2414 /* Reset the whole controller */ 2415 cmn_err(CE_NOTE, "!ahci%d: ahci_tran_reset_dport port %d " 2416 "reset the whole hba", instance, port); 2417 ret = ahci_reset_hba_reject_pkts(ahci_ctlp); 2418 break; 2419 2420 case SATA_ADDR_PMPORT: 2421 case SATA_ADDR_DPMPORT: 2422 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 2423 "ahci_tran_reset_dport: port multiplier will be " 2424 "supported later"); 2425 /* FALLTHRU */ 2426 default: 2427 ret = SATA_FAILURE; 2428 } 2429 2430 return (ret); 2431 } 2432 2433 /* 2434 * Called by sata framework to activate a port as part of hotplug. 2435 * (cfgadm -c connect satax/y) 2436 * Note: Not port-mult aware. 2437 */ 2438 static int 2439 ahci_tran_hotplug_port_activate(dev_info_t *dip, sata_device_t *satadev) 2440 { 2441 ahci_ctl_t *ahci_ctlp; 2442 ahci_port_t *ahci_portp; 2443 uint8_t cport = satadev->satadev_addr.cport; 2444 uint8_t port; 2445 int instance = ddi_get_instance(dip); 2446 2447 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 2448 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2449 2450 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2451 "ahci_tran_hotplug_port_activate cport %d enter", cport); 2452 2453 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2454 2455 mutex_enter(&ahci_portp->ahciport_mutex); 2456 ahci_enable_port_intrs(ahci_ctlp, port); 2457 cmn_err(CE_NOTE, "!ahci%d: ahci port %d is activated", instance, port); 2458 2459 /* 2460 * Reset the port so that the PHY communication would be re-established. 2461 * But this reset is an internal operation and the sata module doesn't 2462 * need to know about it. Moreover, the port with a device attached will 2463 * be started too. 2464 */ 2465 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, 2466 ahci_portp, port, 2467 AHCI_PORT_RESET|AHCI_RESET_NO_EVENTS_UP, 2468 NULL); 2469 2470 /* 2471 * Need to check the link status and device status of the port 2472 * and consider raising power if the port was in D3 state 2473 */ 2474 ahci_portp->ahciport_port_state |= SATA_PSTATE_PWRON; 2475 ahci_portp->ahciport_port_state &= ~SATA_PSTATE_PWROFF; 2476 ahci_portp->ahciport_port_state &= ~SATA_PSTATE_SHUTDOWN; 2477 2478 satadev->satadev_state = ahci_portp->ahciport_port_state; 2479 2480 ahci_update_sata_registers(ahci_ctlp, port, satadev); 2481 2482 mutex_exit(&ahci_portp->ahciport_mutex); 2483 return (SATA_SUCCESS); 2484 } 2485 2486 /* 2487 * Called by sata framework to deactivate a port as part of hotplug. 2488 * (cfgadm -c disconnect satax/y) 2489 * Note: Not port-mult aware. 2490 */ 2491 static int 2492 ahci_tran_hotplug_port_deactivate(dev_info_t *dip, sata_device_t *satadev) 2493 { 2494 ahci_ctl_t *ahci_ctlp; 2495 ahci_port_t *ahci_portp; 2496 uint8_t cport = satadev->satadev_addr.cport; 2497 uint8_t port; 2498 uint32_t port_scontrol; 2499 int instance = ddi_get_instance(dip); 2500 2501 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 2502 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2503 2504 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2505 "ahci_tran_hotplug_port_deactivate cport %d enter", cport); 2506 2507 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2508 2509 mutex_enter(&ahci_portp->ahciport_mutex); 2510 cmn_err(CE_NOTE, "!ahci%d: ahci port %d is deactivated", 2511 instance, port); 2512 2513 /* Disable the interrupts on the port */ 2514 ahci_disable_port_intrs(ahci_ctlp, port); 2515 2516 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2517 goto phy_offline; 2518 } 2519 2520 /* First to abort all the pending commands */ 2521 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port); 2522 2523 /* Then stop the port */ 2524 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 2525 ahci_portp, port); 2526 2527 /* Next put the PHY offline */ 2528 2529 phy_offline: 2530 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2531 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 2532 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_DISABLE); 2533 2534 /* Update ahciport_port_state */ 2535 ahci_portp->ahciport_port_state = SATA_PSTATE_SHUTDOWN; 2536 satadev->satadev_state = ahci_portp->ahciport_port_state; 2537 2538 ahci_update_sata_registers(ahci_ctlp, port, satadev); 2539 2540 mutex_exit(&ahci_portp->ahciport_mutex); 2541 return (SATA_SUCCESS); 2542 } 2543 2544 /* 2545 * To be used to mark all the outstanding pkts with SATA_PKT_ABORTED 2546 * when a device is unplugged or a port is deactivated. 2547 * 2548 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2549 */ 2550 static void 2551 ahci_reject_all_abort_pkts(ahci_ctl_t *ahci_ctlp, 2552 ahci_port_t *ahci_portp, uint8_t port) 2553 { 2554 uint32_t slot_status = 0; 2555 uint32_t abort_tags = 0; 2556 2557 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 2558 "ahci_reject_all_abort_pkts on port: %d", port); 2559 2560 /* 2561 * When AHCI_PORT_FLAG_MOPPING is set, we need to check whether a 2562 * REQUEST SENSE command or READ LOG EXT command is delivered to HBA 2563 * to get the error data, if yes when the device is removed, the 2564 * command needs to be aborted too. 2565 */ 2566 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2567 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 2568 slot_status = 0x1; 2569 abort_tags = 0x1; 2570 goto out; 2571 } else { 2572 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2573 "ahci_reject_all_abort_pkts return directly " 2574 "port %d no needs to reject any outstanding " 2575 "commands", port); 2576 return; 2577 } 2578 } 2579 2580 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2581 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2582 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2583 abort_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2584 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2585 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2586 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2587 abort_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2588 } 2589 2590 out: 2591 /* No need to do mop when there is no outstanding commands */ 2592 if (slot_status != 0) { 2593 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2594 ahci_portp->ahciport_mop_in_progress++; 2595 2596 ahci_mop_commands(ahci_ctlp, 2597 ahci_portp, 2598 slot_status, 2599 0, /* failed tags */ 2600 0, /* timeout tags */ 2601 abort_tags, /* aborting tags */ 2602 0); /* reset tags */ 2603 } 2604 } 2605 2606 #if defined(__lock_lint) 2607 static int 2608 ahci_selftest(dev_info_t *dip, sata_device_t *device) 2609 { 2610 return (SATA_SUCCESS); 2611 } 2612 #endif 2613 2614 /* 2615 * Allocate the ports structure, only called by ahci_attach 2616 */ 2617 static int 2618 ahci_alloc_ports_state(ahci_ctl_t *ahci_ctlp) 2619 { 2620 int port, cport = 0; 2621 2622 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2623 "ahci_alloc_ports_state enter"); 2624 2625 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2626 2627 /* Allocate structures only for the implemented ports */ 2628 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2629 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2630 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2631 "hba port %d not implemented", port); 2632 continue; 2633 } 2634 2635 ahci_ctlp->ahcictl_cport_to_port[cport] = (uint8_t)port; 2636 ahci_ctlp->ahcictl_port_to_cport[port] = 2637 (uint8_t)cport++; 2638 2639 if (ahci_alloc_port_state(ahci_ctlp, port) != AHCI_SUCCESS) { 2640 goto err_out; 2641 } 2642 } 2643 2644 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2645 return (AHCI_SUCCESS); 2646 2647 err_out: 2648 for (port--; port >= 0; port--) { 2649 if (AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2650 ahci_dealloc_port_state(ahci_ctlp, port); 2651 } 2652 } 2653 2654 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2655 return (AHCI_FAILURE); 2656 } 2657 2658 /* 2659 * Reverse of ahci_alloc_ports_state(), only called by ahci_detach 2660 */ 2661 static void 2662 ahci_dealloc_ports_state(ahci_ctl_t *ahci_ctlp) 2663 { 2664 int port; 2665 2666 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2667 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2668 /* if this port is implemented by the HBA */ 2669 if (AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) 2670 ahci_dealloc_port_state(ahci_ctlp, port); 2671 } 2672 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2673 } 2674 2675 /* 2676 * Initialize the controller and all ports. And then try to start the ports 2677 * if there are devices attached. 2678 * 2679 * This routine can be called from three seperate cases: DDI_ATTACH, 2680 * PM_LEVEL_D0 and DDI_RESUME. The DDI_ATTACH case is different from 2681 * other two cases; device signature probing are attempted only during 2682 * DDI_ATTACH case. 2683 * 2684 * WARNING!!! Disable the whole controller's interrupts before calling and 2685 * the interrupts will be enabled upon successfully return. 2686 */ 2687 static int 2688 ahci_initialize_controller(ahci_ctl_t *ahci_ctlp) 2689 { 2690 ahci_port_t *ahci_portp; 2691 uint32_t ghc_control; 2692 int port; 2693 2694 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2695 "ahci_initialize_controller enter"); 2696 2697 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2698 2699 /* 2700 * Indicate that system software is AHCI aware by setting 2701 * GHC.AE to 1 2702 */ 2703 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2704 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 2705 2706 ghc_control |= AHCI_HBA_GHC_AE; 2707 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2708 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), 2709 ghc_control); 2710 2711 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2712 2713 /* Initialize the implemented ports and structures */ 2714 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2715 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2716 continue; 2717 } 2718 2719 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2720 mutex_enter(&ahci_portp->ahciport_mutex); 2721 2722 /* 2723 * Ensure that the controller is not in the running state 2724 * by checking every implemented port's PxCMD register 2725 */ 2726 if (ahci_initialize_port(ahci_ctlp, ahci_portp, port) 2727 != AHCI_SUCCESS) { 2728 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2729 "ahci_initialize_controller: failed to " 2730 "initialize port %d", port); 2731 /* 2732 * Set the port state to SATA_PSTATE_FAILED if 2733 * failed to initialize it. 2734 */ 2735 ahci_portp->ahciport_port_state = SATA_PSTATE_FAILED; 2736 } 2737 2738 mutex_exit(&ahci_portp->ahciport_mutex); 2739 } 2740 2741 /* Enable the whole controller interrupts */ 2742 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2743 ahci_enable_all_intrs(ahci_ctlp); 2744 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2745 2746 return (AHCI_SUCCESS); 2747 } 2748 2749 /* 2750 * Reverse of ahci_initialize_controller() 2751 * 2752 * We only need to stop the ports and disable the interrupt. 2753 */ 2754 static void 2755 ahci_uninitialize_controller(ahci_ctl_t *ahci_ctlp) 2756 { 2757 ahci_port_t *ahci_portp; 2758 int port; 2759 2760 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2761 "ahci_uninitialize_controller enter"); 2762 2763 /* disable all the interrupts. */ 2764 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2765 ahci_disable_all_intrs(ahci_ctlp); 2766 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2767 2768 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2769 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2770 continue; 2771 } 2772 2773 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2774 2775 /* Stop the port by clearing PxCMD.ST */ 2776 mutex_enter(&ahci_portp->ahciport_mutex); 2777 2778 /* 2779 * Here we must disable the port interrupt because 2780 * ahci_disable_all_intrs only clear GHC.IE, and IS 2781 * register will be still set if PxIE is enabled. 2782 * When ahci shares one IRQ with other drivers, the 2783 * intr handler may claim the intr mistakenly. 2784 */ 2785 ahci_disable_port_intrs(ahci_ctlp, port); 2786 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 2787 ahci_portp, port); 2788 mutex_exit(&ahci_portp->ahciport_mutex); 2789 } 2790 } 2791 2792 /* 2793 * The routine is to initialize the port. First put the port in NOTRunning 2794 * state, then enable port interrupt and clear Serror register. And under 2795 * AHCI_ATTACH case, find device signature and then try to start the port. 2796 * 2797 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2798 */ 2799 static int 2800 ahci_initialize_port(ahci_ctl_t *ahci_ctlp, 2801 ahci_port_t *ahci_portp, uint8_t port) 2802 { 2803 uint32_t port_cmd_status; 2804 2805 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2806 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 2807 2808 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2809 "ahci_initialize_port: port %d " 2810 "port_cmd_status = 0x%x", port, port_cmd_status); 2811 /* 2812 * Check whether the port is in NotRunning state, if not, 2813 * put the port in NotRunning state 2814 */ 2815 if (!(port_cmd_status & 2816 (AHCI_CMD_STATUS_ST | 2817 AHCI_CMD_STATUS_CR | 2818 AHCI_CMD_STATUS_FRE | 2819 AHCI_CMD_STATUS_FR))) { 2820 2821 goto next; 2822 } 2823 2824 if (ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 2825 port, AHCI_RESET_NO_EVENTS_UP|AHCI_PORT_INIT, NULL) != AHCI_SUCCESS) 2826 return (AHCI_FAILURE); 2827 2828 next: 2829 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2830 "port %d is in NotRunning state now", port); 2831 2832 /* 2833 * At the time being, only probe ports/devices and get the types of 2834 * attached devices during DDI_ATTACH. In fact, the device can be 2835 * changed during power state changes, but at the time being, we 2836 * don't support the situation. 2837 */ 2838 if (ahci_ctlp->ahcictl_flags & AHCI_ATTACH) { 2839 /* Try to get the device signature */ 2840 ahci_find_dev_signature(ahci_ctlp, ahci_portp, port); 2841 } else { 2842 2843 /* 2844 * During the resume, we need to set the PxCLB, PxCLBU, PxFB 2845 * and PxFBU registers in case these registers were cleared 2846 * during the suspend. 2847 */ 2848 AHCIDBG1(AHCIDBG_PM, ahci_ctlp, 2849 "ahci_initialize_port: port %d " 2850 "reset the port during resume", port); 2851 (void) ahci_port_reset(ahci_ctlp, ahci_portp, port); 2852 2853 AHCIDBG1(AHCIDBG_PM, ahci_ctlp, 2854 "ahci_initialize_port: port %d " 2855 "set PxCLB, PxCLBU, PxFB and PxFBU " 2856 "during resume", port); 2857 2858 /* Config Port Received FIS Base Address */ 2859 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 2860 (uint64_t *)AHCI_PORT_PxFB(ahci_ctlp, port), 2861 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_laddress); 2862 2863 /* Config Port Command List Base Address */ 2864 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 2865 (uint64_t *)AHCI_PORT_PxCLB(ahci_ctlp, port), 2866 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_laddress); 2867 } 2868 2869 /* Disable the interface power management */ 2870 ahci_disable_interface_pm(ahci_ctlp, port); 2871 2872 /* Return directly if no device connected */ 2873 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2874 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2875 "No device connected to port %d", port); 2876 goto out; 2877 } 2878 2879 /* Try to start the port */ 2880 if (ahci_start_port(ahci_ctlp, ahci_portp, port) 2881 != AHCI_SUCCESS) { 2882 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2883 "failed to start port %d", port); 2884 return (AHCI_FAILURE); 2885 } 2886 out: 2887 /* Enable port interrupts */ 2888 ahci_enable_port_intrs(ahci_ctlp, port); 2889 2890 return (AHCI_SUCCESS); 2891 } 2892 2893 /* 2894 * Figure out which chip and set flag for VT8251; Also check 2895 * the power management capability. 2896 */ 2897 static int 2898 ahci_config_space_init(ahci_ctl_t *ahci_ctlp) 2899 { 2900 ushort_t venid, devid; 2901 ushort_t caps_ptr, cap_count, cap; 2902 #if AHCI_DEBUG 2903 ushort_t pmcap, pmcsr; 2904 #endif 2905 uint8_t revision; 2906 2907 venid = pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle, 2908 PCI_CONF_VENID); 2909 2910 devid = pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle, 2911 PCI_CONF_DEVID); 2912 2913 /* 2914 * Modify dma_attr_align of ahcictl_buffer_dma_attr. For VT8251, those 2915 * controllers with 0x00 revision id work on 4-byte aligned buffer, 2916 * which is a bug and was fixed after 0x00 revision id controllers. 2917 * 2918 * Moreover, VT8251 cannot use multiple command slots in the command 2919 * list for non-queued commands because the previous register content 2920 * of PxCI can be re-written in the register write, so a flag will be 2921 * set to record this defect - AHCI_CAP_NO_MCMDLIST_NONQUEUE. 2922 */ 2923 if (venid == VIA_VENID) { 2924 revision = pci_config_get8(ahci_ctlp->ahcictl_pci_conf_handle, 2925 PCI_CONF_REVID); 2926 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2927 "revision id = 0x%x", revision); 2928 if (revision == 0x00) { 2929 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_align = 0x4; 2930 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2931 "change ddi_attr_align to 0x4"); 2932 } 2933 2934 ahci_ctlp->ahcictl_cap = AHCI_CAP_NO_MCMDLIST_NONQUEUE; 2935 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2936 "VT8251 cannot use multiple command lists for " 2937 "non-queued commands"); 2938 } 2939 2940 /* 2941 * ATI SB600 (1002,4380) doesn't support 64-bit DMA addressing though it 2942 * declares support, so we need to set AHCI_CAP_32BIT_DMA flag to force 2943 * 32-bit DMA. 2944 */ 2945 if (venid == 0x1002 && devid == 0x4380) { 2946 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2947 "ATI SB600 cannot do 64-bit DMA though CAP indicates " 2948 "support, so force it to use 32-bit DMA"); 2949 ahci_ctlp->ahcictl_cap |= AHCI_CAP_32BIT_DMA; 2950 } 2951 2952 /* 2953 * Check if capabilities list is supported and if so, 2954 * get initial capabilities pointer and clear bits 0,1. 2955 */ 2956 if (pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle, 2957 PCI_CONF_STAT) & PCI_STAT_CAP) { 2958 caps_ptr = P2ALIGN(pci_config_get8( 2959 ahci_ctlp->ahcictl_pci_conf_handle, 2960 PCI_CONF_CAP_PTR), 4); 2961 } else { 2962 caps_ptr = PCI_CAP_NEXT_PTR_NULL; 2963 } 2964 2965 /* 2966 * Walk capabilities if supported. 2967 */ 2968 for (cap_count = 0; caps_ptr != PCI_CAP_NEXT_PTR_NULL; ) { 2969 2970 /* 2971 * Check that we haven't exceeded the maximum number of 2972 * capabilities and that the pointer is in a valid range. 2973 */ 2974 if (++cap_count > PCI_CAP_MAX_PTR) { 2975 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 2976 "too many device capabilities"); 2977 return (AHCI_FAILURE); 2978 } 2979 if (caps_ptr < PCI_CAP_PTR_OFF) { 2980 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2981 "capabilities pointer 0x%x out of range", 2982 caps_ptr); 2983 return (AHCI_FAILURE); 2984 } 2985 2986 /* 2987 * Get next capability and check that it is valid. 2988 * For now, we only support power management. 2989 */ 2990 cap = pci_config_get8(ahci_ctlp->ahcictl_pci_conf_handle, 2991 caps_ptr); 2992 switch (cap) { 2993 case PCI_CAP_ID_PM: 2994 2995 /* power management supported */ 2996 ahci_ctlp->ahcictl_cap |= AHCI_CAP_PM; 2997 2998 /* Save PMCSR offset */ 2999 ahci_ctlp->ahcictl_pmcsr_offset = caps_ptr + PCI_PMCSR; 3000 3001 #if AHCI_DEBUG 3002 pmcap = pci_config_get16( 3003 ahci_ctlp->ahcictl_pci_conf_handle, 3004 caps_ptr + PCI_PMCAP); 3005 pmcsr = pci_config_get16( 3006 ahci_ctlp->ahcictl_pci_conf_handle, 3007 ahci_ctlp->ahcictl_pmcsr_offset); 3008 AHCIDBG2(AHCIDBG_PM, ahci_ctlp, 3009 "Power Management capability found PCI_PMCAP " 3010 "= 0x%x PCI_PMCSR = 0x%x", pmcap, pmcsr); 3011 if ((pmcap & 0x3) == 0x3) 3012 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3013 "PCI Power Management Interface " 3014 "spec 1.2 compliant"); 3015 #endif 3016 break; 3017 3018 case PCI_CAP_ID_MSI: 3019 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, "MSI capability found"); 3020 break; 3021 3022 case PCI_CAP_ID_PCIX: 3023 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3024 "PCI-X capability found"); 3025 break; 3026 3027 case PCI_CAP_ID_PCI_E: 3028 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3029 "PCI Express capability found"); 3030 break; 3031 3032 case PCI_CAP_ID_MSI_X: 3033 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3034 "MSI-X capability found"); 3035 break; 3036 3037 case PCI_CAP_ID_SATA: 3038 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3039 "SATA capability found"); 3040 break; 3041 3042 case PCI_CAP_ID_VS: 3043 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3044 "Vendor Specific capability found"); 3045 break; 3046 3047 default: 3048 AHCIDBG1(AHCIDBG_PM, ahci_ctlp, 3049 "unrecognized capability 0x%x", cap); 3050 break; 3051 } 3052 3053 /* 3054 * Get next capabilities pointer and clear bits 0,1. 3055 */ 3056 caps_ptr = P2ALIGN(pci_config_get8( 3057 ahci_ctlp->ahcictl_pci_conf_handle, 3058 (caps_ptr + PCI_CAP_NEXT_PTR)), 4); 3059 } 3060 3061 return (AHCI_SUCCESS); 3062 } 3063 3064 /* 3065 * AHCI device reset ...; a single device on one of the ports is reset, 3066 * but the HBA and physical communication remain intact. This is the 3067 * least intrusive. 3068 * 3069 * When issuing a software reset sequence, there should not be other 3070 * commands in the command list, so we will first clear and then re-set 3071 * PxCMD.ST to clear PxCI. And before issuing the software reset, 3072 * the port must be idle and PxTFD.STS.BSY and PxTFD.STS.DRQ must be 3073 * cleared unless command list override (PxCMD.CLO) is supported. 3074 * 3075 * WARNING!!! ahciport_mutex should be acquired and PxCMD.FRE should be 3076 * set before the function is called. 3077 */ 3078 static int 3079 ahci_software_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 3080 uint8_t port) 3081 { 3082 ahci_fis_h2d_register_t *h2d_register_fisp; 3083 ahci_cmd_table_t *cmd_table; 3084 ahci_cmd_header_t *cmd_header; 3085 uint32_t port_cmd_status, port_cmd_issue, port_task_file; 3086 int slot, loop_count; 3087 3088 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 3089 "Port %d device resetting", port); 3090 3091 /* First clear PxCMD.ST */ 3092 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 3093 ahci_portp, port); 3094 3095 /* Then re-set PxCMD.ST */ 3096 (void) ahci_start_port(ahci_ctlp, ahci_portp, port); 3097 3098 /* Check PxTFD.STS.BSY and PxTFD.STS.DRQ */ 3099 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3100 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3101 3102 if (port_task_file & AHCI_TFD_STS_BSY || 3103 port_task_file & AHCI_TFD_STS_DRQ) { 3104 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3105 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3106 if (!(port_cmd_status & AHCI_CMD_STATUS_CLO)) { 3107 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 3108 "PxTFD.STS.BSY or PxTFD.STS.DRQ is still set, " 3109 "but PxCMD.CLO isn't supported, so a port " 3110 "reset is needed."); 3111 return (AHCI_FAILURE); 3112 } 3113 } 3114 3115 slot = ahci_claim_free_slot(ahci_ctlp, ahci_portp, AHCI_NON_NCQ_CMD); 3116 if (slot == AHCI_FAILURE) { 3117 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 3118 "ahci_software_reset: no free slot"); 3119 return (AHCI_FAILURE); 3120 } 3121 3122 /* Now send the first H2D Register FIS with SRST set to 1 */ 3123 cmd_table = ahci_portp->ahciport_cmd_tables[slot]; 3124 bzero((void *)cmd_table, ahci_cmd_table_size); 3125 3126 h2d_register_fisp = 3127 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 3128 3129 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 3130 SET_FIS_PMP(h2d_register_fisp, AHCI_PORTMULT_CONTROL_PORT); 3131 SET_FIS_DEVCTL(h2d_register_fisp, SATA_DEVCTL_SRST); 3132 3133 /* Set Command Header in Command List */ 3134 cmd_header = &ahci_portp->ahciport_cmd_list[slot]; 3135 BZERO_DESCR_INFO(cmd_header); 3136 BZERO_PRD_BYTE_COUNT(cmd_header); 3137 SET_COMMAND_FIS_LENGTH(cmd_header, 5); 3138 3139 SET_CLEAR_BUSY_UPON_R_OK(cmd_header, 1); 3140 SET_RESET(cmd_header, 1); 3141 SET_WRITE(cmd_header, 1); 3142 3143 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_tables_dma_handle[slot], 3144 0, 3145 ahci_cmd_table_size, 3146 DDI_DMA_SYNC_FORDEV); 3147 3148 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 3149 slot * sizeof (ahci_cmd_header_t), 3150 sizeof (ahci_cmd_header_t), 3151 DDI_DMA_SYNC_FORDEV); 3152 3153 /* Indicate to the HBA that a command is active. */ 3154 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3155 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 3156 (0x1 << slot)); 3157 3158 loop_count = 0; 3159 3160 /* Loop till the first command is finished */ 3161 do { 3162 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3163 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 3164 3165 /* We are effectively timing out after 1 sec. */ 3166 if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) { 3167 break; 3168 } 3169 /* Wait for 10 millisec */ 3170 delay(AHCI_10MS_TICKS); 3171 } while (port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp) & (0x1 << slot)); 3172 3173 AHCIDBG3(AHCIDBG_POLL_LOOP, ahci_ctlp, 3174 "ahci_software_reset: 1st loop count: %d, " 3175 "port_cmd_issue = 0x%x, slot = 0x%x", 3176 loop_count, port_cmd_issue, slot); 3177 3178 CLEAR_BIT(ahci_portp->ahciport_pending_tags, slot); 3179 3180 /* Now send the second H2D Register FIS with SRST cleard to zero */ 3181 cmd_table = ahci_portp->ahciport_cmd_tables[slot]; 3182 bzero((void *)cmd_table, ahci_cmd_table_size); 3183 3184 h2d_register_fisp = 3185 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 3186 3187 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 3188 SET_FIS_PMP(h2d_register_fisp, AHCI_PORTMULT_CONTROL_PORT); 3189 3190 /* Set Command Header in Command List */ 3191 cmd_header = &ahci_portp->ahciport_cmd_list[slot]; 3192 BZERO_DESCR_INFO(cmd_header); 3193 BZERO_PRD_BYTE_COUNT(cmd_header); 3194 SET_COMMAND_FIS_LENGTH(cmd_header, 5); 3195 3196 SET_WRITE(cmd_header, 1); 3197 3198 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_tables_dma_handle[slot], 3199 0, 3200 ahci_cmd_table_size, 3201 DDI_DMA_SYNC_FORDEV); 3202 3203 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 3204 slot * sizeof (ahci_cmd_header_t), 3205 sizeof (ahci_cmd_header_t), 3206 DDI_DMA_SYNC_FORDEV); 3207 3208 /* Indicate to the HBA that a command is active. */ 3209 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3210 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 3211 (0x1 << slot)); 3212 3213 loop_count = 0; 3214 3215 /* Loop till the second command is finished */ 3216 do { 3217 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3218 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 3219 3220 /* We are effectively timing out after 1 sec. */ 3221 if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) { 3222 break; 3223 } 3224 /* Wait for 10 millisec */ 3225 delay(AHCI_10MS_TICKS); 3226 } while (port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp) & (0x1 << slot)); 3227 3228 AHCIDBG3(AHCIDBG_POLL_LOOP, ahci_ctlp, 3229 "ahci_software_reset: 2nd loop count: %d, " 3230 "port_cmd_issue = 0x%x, slot = 0x%x", 3231 loop_count, port_cmd_issue, slot); 3232 3233 CLEAR_BIT(ahci_portp->ahciport_pending_tags, slot); 3234 3235 return (AHCI_SUCCESS); 3236 } 3237 3238 /* 3239 * AHCI port reset ...; the physical communication between the HBA and device 3240 * on a port are disabled. This is more intrusive. 3241 * 3242 * When an HBA or port reset occurs, Phy communication is going to 3243 * be re-established with the device through a COMRESET followed by the 3244 * normal out-of-band communication sequence defined in Serial ATA. AT 3245 * the end of reset, the device, if working properly, will send a D2H 3246 * Register FIS, which contains the device signature. When the HBA receives 3247 * this FIS, it updates PxTFD.STS and PxTFD.ERR register fields, and updates 3248 * the PxSIG register with the signature. 3249 * 3250 * Staggered spin-up is an optional feature in SATA II, and it enables an HBA 3251 * to individually spin-up attached devices. Please refer to chapter 10.9 of 3252 * AHCI 1.0 spec. 3253 */ 3254 /* 3255 * WARNING!!! ahciport_mutex should be acquired, and PxCMD.ST should be also 3256 * cleared before the function is called. 3257 */ 3258 static int 3259 ahci_port_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 3260 { 3261 uint32_t cap_status, port_cmd_status; 3262 uint32_t port_scontrol, port_sstatus; 3263 uint32_t port_intr_status, port_task_file; 3264 #if AHCI_DEBUG 3265 uint32_t port_signature; 3266 #endif 3267 int loop_count; 3268 int rval = AHCI_SUCCESS; 3269 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 3270 3271 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 3272 "Port %d port resetting...", port); 3273 ahci_portp->ahciport_port_state = 0; 3274 3275 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3276 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 3277 3278 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3279 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3280 3281 if (cap_status & AHCI_HBA_CAP_SSS) { 3282 /* 3283 * HBA support staggered spin-up, if the port has 3284 * not spin up yet, then force it to do spin-up 3285 */ 3286 if (!(port_cmd_status & AHCI_CMD_STATUS_SUD)) { 3287 if (!(ahci_portp->ahciport_flags 3288 & AHCI_PORT_FLAG_SPINUP)) { 3289 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 3290 "Port %d PxCMD.SUD is zero, force " 3291 "it to do spin-up", port); 3292 ahci_portp->ahciport_flags |= 3293 AHCI_PORT_FLAG_SPINUP; 3294 } 3295 } 3296 } else { 3297 /* 3298 * HBA doesn't support stagger spin-up, force it 3299 * to do normal COMRESET 3300 */ 3301 if (ahci_portp->ahciport_flags & 3302 AHCI_PORT_FLAG_SPINUP) { 3303 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3304 "HBA does not support staggered spin-up " 3305 "force it to do normal COMRESET"); 3306 ahci_portp->ahciport_flags &= 3307 ~AHCI_PORT_FLAG_SPINUP; 3308 } 3309 } 3310 3311 if (!(ahci_portp->ahciport_flags & AHCI_PORT_FLAG_SPINUP)) { 3312 /* Do normal COMRESET */ 3313 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3314 "ahci_port_reset: do normal COMRESET", port); 3315 3316 /* 3317 * According to the spec, SUD bit should be set here, 3318 * but JMicron JMB363 doesn't follow it, so remove 3319 * the assertion, and just print a debug message. 3320 */ 3321 #if AHCI_DEBUG 3322 if (!(port_cmd_status & AHCI_CMD_STATUS_SUD)) 3323 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3324 "port %d SUD bit not set", port) 3325 #endif 3326 3327 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3328 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3329 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_COMRESET); 3330 3331 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3332 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 3333 port_scontrol); 3334 3335 /* Enable PxCMD.FRE to read device */ 3336 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3337 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3338 port_cmd_status|AHCI_CMD_STATUS_FRE); 3339 3340 /* 3341 * Give time for COMRESET to percolate, according to the AHCI 3342 * spec, software shall wait at least 1 millisecond before 3343 * clearing PxSCTL.DET 3344 */ 3345 delay(AHCI_1MS_TICKS*2); 3346 3347 /* Fetch the SCONTROL again and rewrite the DET part with 0 */ 3348 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3349 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3350 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_NOACTION); 3351 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3352 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 3353 port_scontrol); 3354 } else { 3355 /* Do staggered spin-up */ 3356 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3357 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3358 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_NOACTION); 3359 3360 /* PxSCTL.DET must be 0 */ 3361 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3362 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 3363 port_scontrol); 3364 3365 port_cmd_status &= ~AHCI_CMD_STATUS_SUD; 3366 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3367 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3368 port_cmd_status); 3369 3370 /* 0 -> 1 edge */ 3371 delay(AHCI_1MS_TICKS*2); 3372 3373 /* Set PxCMD.SUD to 1 */ 3374 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3375 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3376 port_cmd_status |= AHCI_CMD_STATUS_SUD; 3377 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3378 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3379 port_cmd_status); 3380 3381 /* Enable PxCMD.FRE to read device */ 3382 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3383 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3384 port_cmd_status|AHCI_CMD_STATUS_FRE); 3385 } 3386 3387 /* 3388 * The port enters P:StartComm state, and HBA tells link layer to 3389 * start communication, which involves sending COMRESET to device. 3390 * And the HBA resets PxTFD.STS to 7Fh. 3391 * 3392 * When a COMINIT is received from the device, then the port enters 3393 * P:ComInit state. And HBA sets PxTFD.STS to FFh or 80h. HBA sets 3394 * PxSSTS.DET to 1h to indicate a device is detected but communication 3395 * is not yet established. HBA sets PxSERR.DIAG.X to '1' to indicate 3396 * a COMINIT has been received. 3397 */ 3398 /* 3399 * The DET field is valid only if IPM field indicates 3400 * that the interface is in active state. 3401 */ 3402 loop_count = 0; 3403 do { 3404 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3405 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 3406 3407 if (SSTATUS_GET_IPM(port_sstatus) != SSTATUS_IPM_ACTIVE) { 3408 /* 3409 * If the interface is not active, the DET field 3410 * is considered not accurate. So we want to 3411 * continue looping. 3412 */ 3413 SSTATUS_SET_DET(port_sstatus, SSTATUS_DET_NODEV); 3414 } 3415 3416 if (loop_count++ > AHCI_POLLRATE_PORT_SSTATUS) { 3417 /* 3418 * We are effectively timing out after 0.1 sec. 3419 */ 3420 break; 3421 } 3422 3423 /* Wait for 10 millisec */ 3424 delay(AHCI_10MS_TICKS); 3425 } while (SSTATUS_GET_DET(port_sstatus) != SSTATUS_DET_DEVPRE_PHYCOM); 3426 3427 AHCIDBG3(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 3428 "ahci_port_reset: 1st loop count: %d, " 3429 "port_sstatus = 0x%x port %d", 3430 loop_count, port_sstatus, port); 3431 3432 if ((SSTATUS_GET_IPM(port_sstatus) != SSTATUS_IPM_ACTIVE) || 3433 (SSTATUS_GET_DET(port_sstatus) != SSTATUS_DET_DEVPRE_PHYCOM)) { 3434 /* 3435 * Either the port is not active or there 3436 * is no device present. 3437 */ 3438 ahci_portp->ahciport_device_type = SATA_DTYPE_NONE; 3439 goto out; 3440 } 3441 3442 /* Now we can make sure there is a device connected to the port */ 3443 port_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3444 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port)); 3445 3446 /* a COMINIT signal is supposed to be received */ 3447 if (!(port_intr_status & AHCI_INTR_STATUS_PCS)) { 3448 cmn_err(CE_WARN, "!ahci%d: ahci_port_reset port %d " 3449 "COMINIT signal from the device not received", 3450 instance, port); 3451 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 3452 rval = AHCI_FAILURE; 3453 goto out; 3454 } 3455 3456 /* 3457 * According to the spec, when PxSCTL.DET is set to 0h, upon 3458 * receiving a COMINIT from the attached device, PxTFD.STS.BSY 3459 * shall be set to '1' by the HBA. 3460 * 3461 * However, we found JMicron JMB363 doesn't follow this, so 3462 * remove this check, and just print a debug message. 3463 */ 3464 #if AHCI_DEBUG 3465 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3466 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3467 if (!(port_task_file & AHCI_TFD_STS_BSY)) { 3468 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_port_reset: " 3469 "port %d BSY bit is not set after COMINIT signal " 3470 "is received", port); 3471 } 3472 #endif 3473 3474 /* 3475 * PxSERR.DIAG.X has to be cleared in order to update PxTFD with 3476 * the D2H FIS received by HBA. 3477 */ 3478 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3479 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 3480 SERROR_EXCHANGED_ERR); 3481 3482 /* 3483 * Next check whether COMRESET is completed successfully 3484 */ 3485 loop_count = 0; 3486 do { 3487 port_task_file = 3488 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3489 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3490 3491 /* 3492 * The Error bit '1' means COMRESET is finished successfully 3493 * The device hardware has been initialized and the power-up 3494 * diagnostics successfully completed. 3495 */ 3496 if (((port_task_file & AHCI_TFD_ERR_MASK) 3497 >> AHCI_TFD_ERR_SHIFT) == 0x1) { 3498 #if AHCI_DEBUG 3499 port_signature = ddi_get32( 3500 ahci_ctlp->ahcictl_ahci_acc_handle, 3501 (uint32_t *)AHCI_PORT_PxSIG(ahci_ctlp, port)); 3502 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 3503 "COMRESET success, D2H register FIS " 3504 "post to received FIS structure " 3505 "port %d signature = 0x%x", 3506 port, port_signature); 3507 #endif 3508 goto out_check; 3509 } 3510 3511 if (loop_count++ > AHCI_POLLRATE_PORT_TFD_ERROR) { 3512 /* 3513 * We are effectively timing out after 11 sec. 3514 */ 3515 break; 3516 } 3517 3518 /* Wait for 10 millisec */ 3519 delay(AHCI_10MS_TICKS); 3520 } while (((port_task_file & AHCI_TFD_ERR_MASK) 3521 >> AHCI_TFD_ERR_SHIFT) != 0x1); 3522 3523 AHCIDBG3(AHCIDBG_ERRS, ahci_ctlp, "ahci_port_reset: 2nd loop " 3524 "count: %d, port_task_file = 0x%x port %d", 3525 loop_count, port_task_file, port); 3526 3527 cmn_err(CE_WARN, "!ahci%d: ahci_port_reset port %d the device hardware " 3528 "has been initialized and the power-up diagnostics failed", 3529 instance, port); 3530 3531 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 3532 rval = AHCI_FAILURE; 3533 3534 out: 3535 /* Clear port serror register for the port */ 3536 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3537 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 3538 AHCI_SERROR_CLEAR_ALL); 3539 3540 return (rval); 3541 3542 out_check: 3543 /* 3544 * Check device status, if keep busy or COMRESET error 3545 * do device reset to patch some SATA disks' issue 3546 * 3547 * For VT8251, sometimes need to do the device reset 3548 */ 3549 if ((port_task_file & AHCI_TFD_STS_BSY) || 3550 (port_task_file & AHCI_TFD_STS_DRQ)) { 3551 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "port %d keep BSY/DRQ set " 3552 "need to do device reset", port); 3553 3554 (void) ahci_software_reset(ahci_ctlp, ahci_portp, port); 3555 3556 port_task_file = 3557 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3558 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3559 3560 if (port_task_file & AHCI_TFD_STS_BSY || 3561 port_task_file & AHCI_TFD_STS_DRQ) { 3562 cmn_err(CE_WARN, "!ahci%d: ahci_port_reset: port %d " 3563 "BSY/DRQ still set after device reset " 3564 "port_task_file = 0x%x", instance, 3565 port, port_task_file); 3566 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 3567 rval = AHCI_FAILURE; 3568 } 3569 } 3570 3571 goto out; 3572 } 3573 3574 /* 3575 * AHCI HBA reset ...; the entire HBA is reset, and all ports are disabled. 3576 * This is the most intrusive. 3577 * 3578 * When an HBA reset occurs, Phy communication will be re-established with 3579 * the device through a COMRESET followed by the normal out-of-band 3580 * communication sequence defined in Serial ATA. AT the end of reset, the 3581 * device, if working properly, will send a D2H Register FIS, which contains 3582 * the device signature. When the HBA receives this FIS, it updates PxTFD.STS 3583 * and PxTFD.ERR register fields, and updates the PxSIG register with the 3584 * signature. 3585 * 3586 * Remember to set GHC.AE to 1 before calling ahci_hba_reset. 3587 */ 3588 static int 3589 ahci_hba_reset(ahci_ctl_t *ahci_ctlp) 3590 { 3591 ahci_port_t *ahci_portp; 3592 uint32_t ghc_control; 3593 uint8_t port; 3594 int loop_count; 3595 int rval = AHCI_SUCCESS; 3596 3597 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, "HBA resetting"); 3598 3599 mutex_enter(&ahci_ctlp->ahcictl_mutex); 3600 3601 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3602 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3603 3604 /* Setting GHC.HR to 1, remember GHC.AE is already set to 1 before */ 3605 ghc_control |= AHCI_HBA_GHC_HR; 3606 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3607 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 3608 3609 /* 3610 * Wait until HBA Reset complete or timeout 3611 */ 3612 loop_count = 0; 3613 do { 3614 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3615 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3616 3617 if (loop_count++ > AHCI_POLLRATE_HBA_RESET) { 3618 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 3619 "ahci hba reset is timing out, " 3620 "ghc_control = 0x%x", ghc_control); 3621 /* We are effectively timing out after 1 sec. */ 3622 break; 3623 } 3624 3625 /* Wait for 10 millisec */ 3626 delay(AHCI_10MS_TICKS); 3627 } while (ghc_control & AHCI_HBA_GHC_HR); 3628 3629 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 3630 "ahci_hba_reset: 1st loop count: %d, " 3631 "ghc_control = 0x%x", loop_count, ghc_control); 3632 3633 if (ghc_control & AHCI_HBA_GHC_HR) { 3634 /* The hba is not reset for some reasons */ 3635 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3636 "hba reset failed: HBA in a hung or locked state"); 3637 mutex_exit(&ahci_ctlp->ahcictl_mutex); 3638 return (AHCI_FAILURE); 3639 } 3640 3641 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 3642 /* Only check implemented ports */ 3643 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 3644 continue; 3645 } 3646 3647 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 3648 mutex_enter(&ahci_portp->ahciport_mutex); 3649 3650 if (ahci_port_reset(ahci_ctlp, ahci_portp, port) 3651 != AHCI_SUCCESS) { 3652 rval = AHCI_FAILURE; 3653 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3654 "ahci_hba_reset: port %d failed", port); 3655 } 3656 3657 mutex_exit(&ahci_portp->ahciport_mutex); 3658 } 3659 3660 /* 3661 * Indicate that system software is AHCI aware by setting 3662 * GHC.AE to 1 3663 */ 3664 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3665 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3666 3667 ghc_control |= AHCI_HBA_GHC_AE; 3668 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3669 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 3670 3671 mutex_exit(&ahci_ctlp->ahcictl_mutex); 3672 3673 return (rval); 3674 } 3675 3676 /* 3677 * This routine is only called from AHCI_ATTACH or phyrdy change 3678 * case. It first calls port reset to initialize port, probe port and probe 3679 * device, then try to read PxSIG register to find the type of device 3680 * attached to the port. 3681 * 3682 * WARNING!!! ahciport_mutex should be acquired before the function 3683 * is called. And the port interrupt is disabled. 3684 */ 3685 static void 3686 ahci_find_dev_signature(ahci_ctl_t *ahci_ctlp, 3687 ahci_port_t *ahci_portp, uint8_t port) 3688 { 3689 uint32_t signature; 3690 3691 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 3692 "ahci_find_dev_signature enter: port %d", port); 3693 3694 ahci_portp->ahciport_device_type = SATA_DTYPE_UNKNOWN; 3695 3696 /* Call port reset to check link status and get device signature */ 3697 (void) ahci_port_reset(ahci_ctlp, ahci_portp, port); 3698 3699 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 3700 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3701 "ahci_find_dev_signature: No device is found " 3702 "at port %d", port); 3703 return; 3704 } 3705 3706 /* Check the port state */ 3707 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED) { 3708 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 3709 "ahci_find_dev_signature: port %d state 0x%x", 3710 port, ahci_portp->ahciport_port_state); 3711 return; 3712 } 3713 3714 signature = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3715 (uint32_t *)AHCI_PORT_PxSIG(ahci_ctlp, port)); 3716 3717 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_INFO, ahci_ctlp, 3718 "ahci_find_dev_signature: port %d signature = 0x%x", 3719 port, signature); 3720 3721 switch (signature) { 3722 3723 case AHCI_SIGNATURE_DISK: 3724 ahci_portp->ahciport_device_type = SATA_DTYPE_ATADISK; 3725 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3726 "Disk is found at port: %d", port); 3727 break; 3728 3729 case AHCI_SIGNATURE_ATAPI: 3730 ahci_portp->ahciport_device_type = SATA_DTYPE_ATAPICD; 3731 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3732 "ATAPI device is found at port: %d", port); 3733 break; 3734 3735 case AHCI_SIGNATURE_PORT_MULTIPLIER: 3736 ahci_portp->ahciport_device_type = SATA_DTYPE_PMULT; 3737 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3738 "Port Multiplier is found at port: %d", port); 3739 break; 3740 3741 default: 3742 ahci_portp->ahciport_device_type = SATA_DTYPE_UNKNOWN; 3743 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3744 "Unknown device is found at port: %d", port); 3745 } 3746 } 3747 3748 /* 3749 * According to the spec, to reliably detect hot plug removals, software 3750 * must disable interface power management. Software should perform the 3751 * following initialization on a port after a device is attached: 3752 * Set PxSCTL.IPM to 3h to disable interface state transitions 3753 * Set PxCMD.ALPE to '0' to disable aggressive power management 3754 * Disable device initiated interface power management by SET FEATURE 3755 * 3756 * We can ignore the last item because by default the feature is disabled 3757 */ 3758 static void 3759 ahci_disable_interface_pm(ahci_ctl_t *ahci_ctlp, uint8_t port) 3760 { 3761 uint32_t port_scontrol, port_cmd_status; 3762 3763 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3764 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3765 SCONTROL_SET_IPM(port_scontrol, SCONTROL_IPM_DISABLE_BOTH); 3766 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3767 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), port_scontrol); 3768 3769 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3770 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3771 port_cmd_status &= ~AHCI_CMD_STATUS_ALPE; 3772 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3773 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), port_cmd_status); 3774 } 3775 3776 /* 3777 * Start the port - set PxCMD.ST to 1, if PxCMD.FRE is not set 3778 * to 1, then set it firstly. 3779 * 3780 * Each port contains two major DMA engines. One DMA engine walks through 3781 * the command list, and is controlled by PxCMD.ST. The second DMA engine 3782 * copies received FISes into system memory, and is controlled by PxCMD.FRE. 3783 * 3784 * Software shall not set PxCMD.ST to '1' until it verifies that PxCMD.CR 3785 * is '0' and has set PxCMD.FRE is '1'. And software shall not clear 3786 * PxCMD.FRE while PxCMD.ST or PxCMD.CR is set '1'. 3787 * 3788 * Software shall not set PxCMD.ST to '1' unless a functional device is 3789 * present on the port(as determined by PxTFD.STS.BSY = '0', 3790 * PxTFD.STS.DRQ = '0', and PxSSTS.DET = 3h). 3791 * 3792 * WARNING!!! ahciport_mutex should be acquired before the function 3793 * is called. 3794 */ 3795 static int 3796 ahci_start_port(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 3797 { 3798 uint32_t port_cmd_status; 3799 3800 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, "ahci_start_port: %d enter", port); 3801 3802 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED) { 3803 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port failed " 3804 "the state for port %d is 0x%x", 3805 port, ahci_portp->ahciport_port_state); 3806 return (AHCI_FAILURE); 3807 } 3808 3809 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 3810 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port failed " 3811 "no device is attached at port %d", port); 3812 return (AHCI_FAILURE); 3813 } 3814 3815 /* First to set PxCMD.FRE before setting PxCMD.ST. */ 3816 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3817 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3818 3819 if (!(port_cmd_status & AHCI_CMD_STATUS_FRE)) { 3820 port_cmd_status |= AHCI_CMD_STATUS_FRE; 3821 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3822 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3823 port_cmd_status); 3824 } 3825 3826 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3827 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3828 3829 port_cmd_status |= AHCI_CMD_STATUS_ST; 3830 3831 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3832 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3833 port_cmd_status); 3834 3835 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_STARTED; 3836 3837 return (AHCI_SUCCESS); 3838 } 3839 3840 /* 3841 * Allocate the ahci_port_t including Received FIS and Command List. 3842 * The argument - port is the physical port number, and not logical 3843 * port number seen by the SATA framework. 3844 * 3845 * WARNING!!! ahcictl_mutex should be acquired before the function 3846 * is called. 3847 */ 3848 static int 3849 ahci_alloc_port_state(ahci_ctl_t *ahci_ctlp, uint8_t port) 3850 { 3851 ahci_port_t *ahci_portp; 3852 3853 ahci_portp = 3854 (ahci_port_t *)kmem_zalloc(sizeof (ahci_port_t), KM_SLEEP); 3855 3856 ahci_ctlp->ahcictl_ports[port] = ahci_portp; 3857 ahci_portp->ahciport_port_num = port; 3858 3859 /* Intialize the port condition variable */ 3860 cv_init(&ahci_portp->ahciport_cv, NULL, CV_DRIVER, NULL); 3861 3862 /* Initialize the port mutex */ 3863 mutex_init(&ahci_portp->ahciport_mutex, NULL, MUTEX_DRIVER, 3864 (void *)(uintptr_t)ahci_ctlp->ahcictl_intr_pri); 3865 3866 mutex_enter(&ahci_portp->ahciport_mutex); 3867 3868 /* 3869 * Allocate memory for received FIS structure and 3870 * command list for this port 3871 */ 3872 if (ahci_alloc_rcvd_fis(ahci_ctlp, ahci_portp, port) != AHCI_SUCCESS) { 3873 goto err_case1; 3874 } 3875 3876 if (ahci_alloc_cmd_list(ahci_ctlp, ahci_portp, port) != AHCI_SUCCESS) { 3877 goto err_case2; 3878 } 3879 3880 ahci_portp->ahciport_event_args = 3881 kmem_zalloc(sizeof (ahci_event_arg_t), KM_SLEEP); 3882 3883 if (ahci_portp->ahciport_event_args == NULL) 3884 goto err_case3; 3885 3886 mutex_exit(&ahci_portp->ahciport_mutex); 3887 3888 return (AHCI_SUCCESS); 3889 3890 err_case3: 3891 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp); 3892 3893 err_case2: 3894 ahci_dealloc_rcvd_fis(ahci_portp); 3895 3896 err_case1: 3897 mutex_exit(&ahci_portp->ahciport_mutex); 3898 mutex_destroy(&ahci_portp->ahciport_mutex); 3899 cv_destroy(&ahci_portp->ahciport_cv); 3900 3901 kmem_free(ahci_portp, sizeof (ahci_port_t)); 3902 3903 return (AHCI_FAILURE); 3904 } 3905 3906 /* 3907 * Reverse of ahci_dealloc_port_state(). 3908 * 3909 * WARNING!!! ahcictl_mutex should be acquired before the function 3910 * is called. 3911 */ 3912 static void 3913 ahci_dealloc_port_state(ahci_ctl_t *ahci_ctlp, uint8_t port) 3914 { 3915 ahci_port_t *ahci_portp = ahci_ctlp->ahcictl_ports[port]; 3916 3917 ASSERT(ahci_portp != NULL); 3918 3919 mutex_enter(&ahci_portp->ahciport_mutex); 3920 kmem_free(ahci_portp->ahciport_event_args, sizeof (ahci_event_arg_t)); 3921 ahci_portp->ahciport_event_args = NULL; 3922 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp); 3923 ahci_dealloc_rcvd_fis(ahci_portp); 3924 mutex_exit(&ahci_portp->ahciport_mutex); 3925 3926 mutex_destroy(&ahci_portp->ahciport_mutex); 3927 cv_destroy(&ahci_portp->ahciport_cv); 3928 3929 kmem_free(ahci_portp, sizeof (ahci_port_t)); 3930 3931 ahci_ctlp->ahcictl_ports[port] = NULL; 3932 } 3933 3934 /* 3935 * Allocates memory for the Received FIS Structure 3936 * 3937 * WARNING!!! ahciport_mutex should be acquired before the function 3938 * is called. 3939 */ 3940 static int 3941 ahci_alloc_rcvd_fis(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 3942 uint8_t port) 3943 { 3944 size_t rcvd_fis_size; 3945 size_t ret_len; 3946 uint_t cookie_count; 3947 3948 rcvd_fis_size = sizeof (ahci_rcvd_fis_t); 3949 3950 /* allocate rcvd FIS dma handle. */ 3951 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 3952 &ahci_ctlp->ahcictl_rcvd_fis_dma_attr, 3953 DDI_DMA_SLEEP, 3954 NULL, 3955 &ahci_portp->ahciport_rcvd_fis_dma_handle) != 3956 DDI_SUCCESS) { 3957 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3958 "rcvd FIS dma handle alloc failed"); 3959 3960 return (AHCI_FAILURE); 3961 } 3962 3963 if (ddi_dma_mem_alloc(ahci_portp->ahciport_rcvd_fis_dma_handle, 3964 rcvd_fis_size, 3965 &accattr, 3966 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 3967 DDI_DMA_SLEEP, 3968 NULL, 3969 (caddr_t *)&ahci_portp->ahciport_rcvd_fis, 3970 &ret_len, 3971 &ahci_portp->ahciport_rcvd_fis_acc_handle) != NULL) { 3972 3973 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3974 "rcvd FIS dma mem alloc fail"); 3975 /* error.. free the dma handle. */ 3976 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 3977 return (AHCI_FAILURE); 3978 } 3979 3980 if (ddi_dma_addr_bind_handle(ahci_portp->ahciport_rcvd_fis_dma_handle, 3981 NULL, 3982 (caddr_t)ahci_portp->ahciport_rcvd_fis, 3983 rcvd_fis_size, 3984 DDI_DMA_CONSISTENT, 3985 DDI_DMA_SLEEP, 3986 NULL, 3987 &ahci_portp->ahciport_rcvd_fis_dma_cookie, 3988 &cookie_count) != DDI_DMA_MAPPED) { 3989 3990 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3991 "rcvd FIS dma handle bind fail"); 3992 /* error.. free the dma handle & free the memory. */ 3993 ddi_dma_mem_free(&ahci_portp->ahciport_rcvd_fis_acc_handle); 3994 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 3995 return (AHCI_FAILURE); 3996 } 3997 3998 bzero((void *)ahci_portp->ahciport_rcvd_fis, rcvd_fis_size); 3999 4000 /* Config Port Received FIS Base Address */ 4001 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 4002 (uint64_t *)AHCI_PORT_PxFB(ahci_ctlp, port), 4003 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_laddress); 4004 4005 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "64-bit, dma address: 0x%llx", 4006 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_laddress); 4007 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "32-bit, dma address: 0x%x", 4008 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_address); 4009 4010 return (AHCI_SUCCESS); 4011 } 4012 4013 /* 4014 * Deallocates the Received FIS Structure 4015 * 4016 * WARNING!!! ahciport_mutex should be acquired before the function 4017 * is called. 4018 */ 4019 static void 4020 ahci_dealloc_rcvd_fis(ahci_port_t *ahci_portp) 4021 { 4022 /* Unbind the cmd list dma handle first. */ 4023 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_rcvd_fis_dma_handle); 4024 4025 /* Then free the underlying memory. */ 4026 ddi_dma_mem_free(&ahci_portp->ahciport_rcvd_fis_acc_handle); 4027 4028 /* Now free the handle itself. */ 4029 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 4030 } 4031 4032 /* 4033 * Allocates memory for the Command List, which contains up to 32 entries. 4034 * Each entry contains a command header, which is a 32-byte structure that 4035 * includes the pointer to the command table. 4036 * 4037 * WARNING!!! ahciport_mutex should be acquired before the function 4038 * is called. 4039 */ 4040 static int 4041 ahci_alloc_cmd_list(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 4042 uint8_t port) 4043 { 4044 size_t cmd_list_size; 4045 size_t ret_len; 4046 uint_t cookie_count; 4047 4048 cmd_list_size = 4049 ahci_ctlp->ahcictl_num_cmd_slots * sizeof (ahci_cmd_header_t); 4050 4051 /* allocate cmd list dma handle. */ 4052 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 4053 &ahci_ctlp->ahcictl_cmd_list_dma_attr, 4054 DDI_DMA_SLEEP, 4055 NULL, 4056 &ahci_portp->ahciport_cmd_list_dma_handle) != DDI_SUCCESS) { 4057 4058 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4059 "cmd list dma handle alloc failed"); 4060 return (AHCI_FAILURE); 4061 } 4062 4063 if (ddi_dma_mem_alloc(ahci_portp->ahciport_cmd_list_dma_handle, 4064 cmd_list_size, 4065 &accattr, 4066 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 4067 DDI_DMA_SLEEP, 4068 NULL, 4069 (caddr_t *)&ahci_portp->ahciport_cmd_list, 4070 &ret_len, 4071 &ahci_portp->ahciport_cmd_list_acc_handle) != NULL) { 4072 4073 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4074 "cmd list dma mem alloc fail"); 4075 /* error.. free the dma handle. */ 4076 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4077 return (AHCI_FAILURE); 4078 } 4079 4080 if (ddi_dma_addr_bind_handle(ahci_portp->ahciport_cmd_list_dma_handle, 4081 NULL, 4082 (caddr_t)ahci_portp->ahciport_cmd_list, 4083 cmd_list_size, 4084 DDI_DMA_CONSISTENT, 4085 DDI_DMA_SLEEP, 4086 NULL, 4087 &ahci_portp->ahciport_cmd_list_dma_cookie, 4088 &cookie_count) != DDI_DMA_MAPPED) { 4089 4090 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4091 "cmd list dma handle bind fail"); 4092 /* error.. free the dma handle & free the memory. */ 4093 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 4094 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4095 return (AHCI_FAILURE); 4096 } 4097 4098 bzero((void *)ahci_portp->ahciport_cmd_list, cmd_list_size); 4099 4100 /* Config Port Command List Base Address */ 4101 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 4102 (uint64_t *)AHCI_PORT_PxCLB(ahci_ctlp, port), 4103 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_laddress); 4104 4105 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "64-bit, dma address: 0x%llx", 4106 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_laddress); 4107 4108 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "32-bit, dma address: 0x%x", 4109 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_address); 4110 4111 if (ahci_alloc_cmd_tables(ahci_ctlp, ahci_portp) != AHCI_SUCCESS) { 4112 goto err_out; 4113 } 4114 4115 return (AHCI_SUCCESS); 4116 4117 err_out: 4118 /* Unbind the cmd list dma handle first. */ 4119 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_cmd_list_dma_handle); 4120 4121 /* Then free the underlying memory. */ 4122 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 4123 4124 /* Now free the handle itself. */ 4125 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4126 4127 return (AHCI_FAILURE); 4128 } 4129 4130 /* 4131 * Deallocates the Command List 4132 * 4133 * WARNING!!! ahciport_mutex should be acquired before the function 4134 * is called. 4135 */ 4136 static void 4137 ahci_dealloc_cmd_list(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 4138 { 4139 /* First dealloc command table */ 4140 ahci_dealloc_cmd_tables(ahci_ctlp, ahci_portp); 4141 4142 /* Unbind the cmd list dma handle first. */ 4143 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_cmd_list_dma_handle); 4144 4145 /* Then free the underlying memory. */ 4146 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 4147 4148 /* Now free the handle itself. */ 4149 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4150 } 4151 4152 /* 4153 * Allocates memory for all Command Tables, which contains Command FIS, 4154 * ATAPI Command and Physical Region Descriptor Table. 4155 * 4156 * WARNING!!! ahciport_mutex should be acquired before the function 4157 * is called. 4158 */ 4159 static int 4160 ahci_alloc_cmd_tables(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 4161 { 4162 size_t ret_len; 4163 ddi_dma_cookie_t cmd_table_dma_cookie; 4164 uint_t cookie_count; 4165 int slot; 4166 4167 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 4168 "ahci_alloc_cmd_tables: port %d enter", 4169 ahci_portp->ahciport_port_num); 4170 4171 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) { 4172 /* Allocate cmd table dma handle. */ 4173 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 4174 &ahci_ctlp->ahcictl_cmd_table_dma_attr, 4175 DDI_DMA_SLEEP, 4176 NULL, 4177 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]) != 4178 DDI_SUCCESS) { 4179 4180 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4181 "cmd table dma handle alloc failed"); 4182 4183 goto err_out; 4184 } 4185 4186 if (ddi_dma_mem_alloc( 4187 ahci_portp->ahciport_cmd_tables_dma_handle[slot], 4188 ahci_cmd_table_size, 4189 &accattr, 4190 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 4191 DDI_DMA_SLEEP, 4192 NULL, 4193 (caddr_t *)&ahci_portp->ahciport_cmd_tables[slot], 4194 &ret_len, 4195 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]) != 4196 NULL) { 4197 4198 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4199 "cmd table dma mem alloc fail"); 4200 4201 /* error.. free the dma handle. */ 4202 ddi_dma_free_handle( 4203 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4204 goto err_out; 4205 } 4206 4207 if (ddi_dma_addr_bind_handle( 4208 ahci_portp->ahciport_cmd_tables_dma_handle[slot], 4209 NULL, 4210 (caddr_t)ahci_portp->ahciport_cmd_tables[slot], 4211 ahci_cmd_table_size, 4212 DDI_DMA_CONSISTENT, 4213 DDI_DMA_SLEEP, 4214 NULL, 4215 &cmd_table_dma_cookie, 4216 &cookie_count) != DDI_DMA_MAPPED) { 4217 4218 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4219 "cmd table dma handle bind fail"); 4220 /* error.. free the dma handle & free the memory. */ 4221 ddi_dma_mem_free( 4222 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 4223 ddi_dma_free_handle( 4224 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4225 goto err_out; 4226 } 4227 4228 bzero((void *)ahci_portp->ahciport_cmd_tables[slot], 4229 ahci_cmd_table_size); 4230 4231 /* Config Port Command Table Base Address */ 4232 SET_COMMAND_TABLE_BASE_ADDR( 4233 (&ahci_portp->ahciport_cmd_list[slot]), 4234 cmd_table_dma_cookie.dmac_laddress & 0xffffffffull); 4235 4236 #ifndef __lock_lint 4237 SET_COMMAND_TABLE_BASE_ADDR_UPPER( 4238 (&ahci_portp->ahciport_cmd_list[slot]), 4239 cmd_table_dma_cookie.dmac_laddress >> 32); 4240 #endif 4241 } 4242 4243 return (AHCI_SUCCESS); 4244 err_out: 4245 4246 for (slot--; slot >= 0; slot--) { 4247 /* Unbind the cmd table dma handle first */ 4248 (void) ddi_dma_unbind_handle( 4249 ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4250 4251 /* Then free the underlying memory */ 4252 ddi_dma_mem_free( 4253 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 4254 4255 /* Now free the handle itself */ 4256 ddi_dma_free_handle( 4257 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4258 } 4259 4260 return (AHCI_FAILURE); 4261 } 4262 4263 /* 4264 * Deallocates memory for all Command Tables. 4265 * 4266 * WARNING!!! ahciport_mutex should be acquired before the function 4267 * is called. 4268 */ 4269 static void 4270 ahci_dealloc_cmd_tables(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 4271 { 4272 int slot; 4273 4274 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 4275 "ahci_dealloc_cmd_tables: %d enter", 4276 ahci_portp->ahciport_port_num); 4277 4278 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) { 4279 /* Unbind the cmd table dma handle first. */ 4280 (void) ddi_dma_unbind_handle( 4281 ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4282 4283 /* Then free the underlying memory. */ 4284 ddi_dma_mem_free( 4285 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 4286 4287 /* Now free the handle itself. */ 4288 ddi_dma_free_handle( 4289 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4290 } 4291 } 4292 4293 /* 4294 * WARNING!!! ahciport_mutex should be acquired before the function 4295 * is called. 4296 */ 4297 static void 4298 ahci_update_sata_registers(ahci_ctl_t *ahci_ctlp, uint8_t port, 4299 sata_device_t *sd) 4300 { 4301 sd->satadev_scr.sstatus = 4302 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4303 (uint32_t *)(AHCI_PORT_PxSSTS(ahci_ctlp, port))); 4304 sd->satadev_scr.serror = 4305 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4306 (uint32_t *)(AHCI_PORT_PxSERR(ahci_ctlp, port))); 4307 sd->satadev_scr.scontrol = 4308 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4309 (uint32_t *)(AHCI_PORT_PxSCTL(ahci_ctlp, port))); 4310 sd->satadev_scr.sactive = 4311 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4312 (uint32_t *)(AHCI_PORT_PxSACT(ahci_ctlp, port))); 4313 } 4314 4315 /* 4316 * For poll mode, ahci_port_intr will be called to emulate the interrupt 4317 */ 4318 static void 4319 ahci_port_intr(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 4320 { 4321 uint32_t port_intr_status; 4322 uint32_t port_intr_enable; 4323 4324 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4325 "ahci_port_intr enter: port %d", port); 4326 4327 mutex_enter(&ahci_portp->ahciport_mutex); 4328 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_POLLING) { 4329 /* For SATA_OPMODE_POLLING commands */ 4330 port_intr_enable = 4331 (AHCI_INTR_STATUS_DHRS | 4332 AHCI_INTR_STATUS_PSS | 4333 AHCI_INTR_STATUS_SDBS | 4334 AHCI_INTR_STATUS_UFS | 4335 AHCI_INTR_STATUS_PCS | 4336 AHCI_INTR_STATUS_PRCS | 4337 AHCI_INTR_STATUS_OFS | 4338 AHCI_INTR_STATUS_INFS | 4339 AHCI_INTR_STATUS_IFS | 4340 AHCI_INTR_STATUS_HBDS | 4341 AHCI_INTR_STATUS_HBFS | 4342 AHCI_INTR_STATUS_TFES); 4343 mutex_exit(&ahci_portp->ahciport_mutex); 4344 goto next; 4345 } 4346 mutex_exit(&ahci_portp->ahciport_mutex); 4347 4348 /* 4349 * port_intr_enable indicates that the corresponding interrrupt 4350 * reporting is enabled. 4351 */ 4352 port_intr_enable = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4353 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port)); 4354 next: 4355 /* 4356 * port_intr_stats indicates that the corresponding interrupt 4357 * condition is active. 4358 */ 4359 port_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4360 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port)); 4361 4362 AHCIDBG3(AHCIDBG_INTR, ahci_ctlp, 4363 "ahci_port_intr: port %d, port_intr_status = 0x%x, " 4364 "port_intr_enable = 0x%x", 4365 port, port_intr_status, port_intr_enable); 4366 4367 port_intr_status &= port_intr_enable; 4368 4369 /* First clear the port interrupts status */ 4370 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4371 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port), 4372 port_intr_status); 4373 4374 /* Check the completed non-queued commands */ 4375 if (port_intr_status & (AHCI_INTR_STATUS_DHRS | 4376 AHCI_INTR_STATUS_PSS)) { 4377 (void) ahci_intr_cmd_cmplt(ahci_ctlp, 4378 ahci_portp, port); 4379 } 4380 4381 /* Check the completed queued commands */ 4382 if (port_intr_status & AHCI_INTR_STATUS_SDBS) { 4383 (void) ahci_intr_set_device_bits(ahci_ctlp, 4384 ahci_portp, port); 4385 } 4386 4387 /* Check the port connect change status interrupt bit */ 4388 if (port_intr_status & AHCI_INTR_STATUS_PCS) { 4389 (void) ahci_intr_port_connect_change(ahci_ctlp, 4390 ahci_portp, port); 4391 } 4392 4393 /* Check the device mechanical presence status interrupt bit */ 4394 if (port_intr_status & AHCI_INTR_STATUS_DMPS) { 4395 (void) ahci_intr_device_mechanical_presence_status( 4396 ahci_ctlp, ahci_portp, port); 4397 } 4398 4399 /* Check the PhyRdy change status interrupt bit */ 4400 if (port_intr_status & AHCI_INTR_STATUS_PRCS) { 4401 (void) ahci_intr_phyrdy_change(ahci_ctlp, ahci_portp, 4402 port); 4403 } 4404 4405 /* 4406 * Check the non-fatal error interrupt bits, there are three 4407 * kinds of non-fatal errors at the time being: 4408 * 4409 * PxIS.UFS - Unknown FIS Error 4410 * PxIS.OFS - Overflow Error 4411 * PxIS.INFS - Interface Non-Fatal Error 4412 * 4413 * For these non-fatal errors, the HBA can continue to operate, 4414 * so the driver just log the error messages. 4415 */ 4416 if (port_intr_status & (AHCI_INTR_STATUS_UFS | 4417 AHCI_INTR_STATUS_OFS | 4418 AHCI_INTR_STATUS_INFS)) { 4419 (void) ahci_intr_non_fatal_error(ahci_ctlp, ahci_portp, 4420 port, port_intr_status); 4421 } 4422 4423 /* 4424 * Check the fatal error interrupt bits, there are four kinds 4425 * of fatal errors for AHCI controllers: 4426 * 4427 * PxIS.HBFS - Host Bus Fatal Error 4428 * PxIS.HBDS - Host Bus Data Error 4429 * PxIS.IFS - Interface Fatal Error 4430 * PxIS.TFES - Task File Error 4431 * 4432 * The fatal error means the HBA can not recover from it by 4433 * itself, and it will try to abort the transfer, and the software 4434 * must intervene to restart the port. 4435 */ 4436 if (port_intr_status & (AHCI_INTR_STATUS_IFS | 4437 AHCI_INTR_STATUS_HBDS | 4438 AHCI_INTR_STATUS_HBFS | 4439 AHCI_INTR_STATUS_TFES)) 4440 (void) ahci_intr_fatal_error(ahci_ctlp, ahci_portp, 4441 port, port_intr_status); 4442 4443 /* Check the cold port detect interrupt bit */ 4444 if (port_intr_status & AHCI_INTR_STATUS_CPDS) { 4445 (void) ahci_intr_cold_port_detect(ahci_ctlp, ahci_portp, port); 4446 } 4447 4448 /* Second clear the corresponding bit in IS.IPS */ 4449 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4450 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp), (0x1 << port)); 4451 } 4452 4453 /* 4454 * Interrupt service handler 4455 */ 4456 static uint_t 4457 ahci_intr(caddr_t arg1, caddr_t arg2) 4458 { 4459 #ifndef __lock_lint 4460 _NOTE(ARGUNUSED(arg2)) 4461 #endif 4462 /* LINTED */ 4463 ahci_ctl_t *ahci_ctlp = (ahci_ctl_t *)arg1; 4464 ahci_port_t *ahci_portp; 4465 int32_t global_intr_status; 4466 uint8_t port; 4467 4468 /* 4469 * global_intr_status indicates that the corresponding port has 4470 * an interrupt pending. 4471 */ 4472 global_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4473 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp)); 4474 4475 if (!(global_intr_status & ahci_ctlp->ahcictl_ports_implemented)) { 4476 /* The interrupt is not ours */ 4477 return (DDI_INTR_UNCLAIMED); 4478 } 4479 4480 /* Loop for all the ports */ 4481 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 4482 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 4483 continue; 4484 } 4485 if (!((0x1 << port) & global_intr_status)) { 4486 continue; 4487 } 4488 4489 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 4490 4491 /* Call ahci_port_intr */ 4492 ahci_port_intr(ahci_ctlp, ahci_portp, port); 4493 } 4494 4495 return (DDI_INTR_CLAIMED); 4496 } 4497 4498 /* 4499 * For non-queued commands, when the corresponding bit in the PxCI register 4500 * is cleared, it means the command is completed successfully. And according 4501 * to the HBA state machine, there are three conditions which possibly will 4502 * try to clear the PxCI register bit. 4503 * 1. Receive one D2H Register FIS which is with 'I' bit set 4504 * 2. Update PIO Setup FIS 4505 * 3. Transmit a command and receive R_OK if CTBA.C is set (software reset) 4506 * 4507 * Process completed non-queued commands when the interrupt status bit - 4508 * AHCI_INTR_STATUS_DHRS or AHCI_INTR_STATUS_PSS is set. 4509 * 4510 * AHCI_INTR_STATUS_DHRS means a D2H Register FIS has been received 4511 * with the 'I' bit set. And the following commands will send thus 4512 * FIS with 'I' bit set upon the successful completion: 4513 * 1. Non-data commands 4514 * 2. DMA data-in command 4515 * 3. DMA data-out command 4516 * 4. PIO data-out command 4517 * 5. PACKET non-data commands 4518 * 6. PACKET PIO data-in command 4519 * 7. PACKET PIO data-out command 4520 * 8. PACKET DMA data-in command 4521 * 9. PACKET DMA data-out command 4522 * 4523 * AHCI_INTR_STATUS_PSS means a PIO Setup FIS has been received 4524 * with the 'I' bit set. And the following commands will send this 4525 * FIS upon the successful completion: 4526 * 1. PIO data-in command 4527 */ 4528 static int 4529 ahci_intr_cmd_cmplt(ahci_ctl_t *ahci_ctlp, 4530 ahci_port_t *ahci_portp, uint8_t port) 4531 { 4532 uint32_t port_cmd_issue = 0; 4533 uint32_t finished_tags; 4534 int finished_slot; 4535 sata_pkt_t *satapkt; 4536 ahci_fis_d2h_register_t *rcvd_fisp; 4537 4538 mutex_enter(&ahci_portp->ahciport_mutex); 4539 4540 if (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && 4541 !NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 4542 /* 4543 * Spurious interrupt. Nothing to be done. 4544 */ 4545 mutex_exit(&ahci_portp->ahciport_mutex); 4546 return (AHCI_SUCCESS); 4547 } 4548 4549 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4550 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 4551 4552 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 4553 /* Slot 0 is always used during error recovery */ 4554 finished_tags = 0x1 & ~port_cmd_issue; 4555 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 4556 "ahci_intr_cmd_cmplt: port %d the sata pkt for error " 4557 "retrieval is finished, and finished_tags = 0x%x", 4558 port, finished_tags); 4559 } else { 4560 finished_tags = ahci_portp->ahciport_pending_tags & 4561 ~port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp); 4562 } 4563 4564 AHCIDBG3(AHCIDBG_INTR, ahci_ctlp, 4565 "ahci_intr_cmd_cmplt: pending_tags = 0x%x, " 4566 "port_cmd_issue = 0x%x finished_tags = 0x%x", 4567 ahci_portp->ahciport_pending_tags, port_cmd_issue, 4568 finished_tags); 4569 4570 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && 4571 (finished_tags == 0x1)) { 4572 satapkt = ahci_portp->ahciport_err_retri_pkt; 4573 ASSERT(satapkt != NULL); 4574 4575 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4576 "ahci_intr_cmd_cmplt: sending up pkt 0x%p " 4577 "with SATA_PKT_COMPLETED", (void *)satapkt); 4578 4579 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 4580 goto out; 4581 } 4582 4583 while (finished_tags) { 4584 finished_slot = ddi_ffs(finished_tags) - 1; 4585 if (finished_slot == -1) { 4586 goto out; 4587 } 4588 4589 satapkt = ahci_portp->ahciport_slot_pkts[finished_slot]; 4590 ASSERT(satapkt != NULL); 4591 4592 /* 4593 * For SATAC_SMART command with SATA_SMART_RETURN_STATUS 4594 * feature, sata_special_regs flag will be set, and the 4595 * driver should copy the status and the other corresponding 4596 * register values in the D2H Register FIS received (It's 4597 * working on Non-data protocol) from the device back to 4598 * the sata_cmd. 4599 * 4600 * For every AHCI port, there is only one Received FIS 4601 * structure, which contains the FISes received from the 4602 * device, So we're trying to copy the content of D2H 4603 * Register FIS in the Received FIS structure back to 4604 * the sata_cmd. 4605 */ 4606 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) { 4607 rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis-> 4608 ahcirf_d2h_register_fis); 4609 satapkt->satapkt_cmd.satacmd_status_reg = 4610 GET_RFIS_STATUS(rcvd_fisp); 4611 ahci_copy_out_regs(&satapkt->satapkt_cmd, rcvd_fisp); 4612 } 4613 4614 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4615 "ahci_intr_cmd_cmplt: sending up pkt 0x%p " 4616 "with SATA_PKT_COMPLETED", (void *)satapkt); 4617 4618 CLEAR_BIT(ahci_portp->ahciport_pending_tags, finished_slot); 4619 CLEAR_BIT(finished_tags, finished_slot); 4620 ahci_portp->ahciport_slot_pkts[finished_slot] = NULL; 4621 4622 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 4623 } 4624 out: 4625 AHCIDBG1(AHCIDBG_PKTCOMP, ahci_ctlp, 4626 "ahci_intr_cmd_cmplt: pending_tags = 0x%x", 4627 ahci_portp->ahciport_pending_tags); 4628 4629 mutex_exit(&ahci_portp->ahciport_mutex); 4630 4631 return (AHCI_SUCCESS); 4632 } 4633 4634 /* 4635 * AHCI_INTR_STATUS_SDBS means a Set Device Bits FIS has been received 4636 * with the 'I' bit set and has been copied into system memory. It will 4637 * be sent under the following situations: 4638 * 4639 * 1. NCQ command is completed 4640 * 2. Asynchronous notification 4641 * 4642 * The completion of NCQ commands (READ/WRITE FPDMA QUEUED) is performed 4643 * via the Set Device Bits FIS. When such event is generated, the software 4644 * needs to read PxSACT register and compares the current value to the 4645 * list of commands previously issue by software. ahciport_pending_ncq_tags 4646 * keeps the tags of previously issued commands. 4647 * 4648 * Asynchronous Notification is a feature in SATA II, which allows an 4649 * ATAPI device to send a signal to the host when media is inserted or 4650 * removed and avoids polling the device for media changes. The signal 4651 * sent to the host is a Set Device Bits FIS with the 'I' and 'N' bits 4652 * set to '1'. At the moment, it's not supported yet. 4653 */ 4654 static int 4655 ahci_intr_set_device_bits(ahci_ctl_t *ahci_ctlp, 4656 ahci_port_t *ahci_portp, uint8_t port) 4657 { 4658 uint32_t port_sactive; 4659 uint32_t port_cmd_issue; 4660 uint32_t issued_tags; 4661 int issued_slot; 4662 uint32_t finished_tags; 4663 int finished_slot; 4664 sata_pkt_t *satapkt; 4665 4666 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4667 "ahci_intr_set_device_bits enter: port %d", port); 4668 4669 mutex_enter(&ahci_portp->ahciport_mutex); 4670 if (!NCQ_CMD_IN_PROGRESS(ahci_portp)) { 4671 mutex_exit(&ahci_portp->ahciport_mutex); 4672 return (AHCI_SUCCESS); 4673 } 4674 4675 /* 4676 * First the handler got which commands are finished by checking 4677 * PxSACT register 4678 */ 4679 port_sactive = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4680 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 4681 4682 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 4683 ~port_sactive & AHCI_NCQ_SLOT_MASK(ahci_portp); 4684 4685 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4686 "ahci_intr_set_device_bits: port %d pending_ncq_tags = 0x%x " 4687 "port_sactive = 0x%x", port, 4688 ahci_portp->ahciport_pending_ncq_tags, port_sactive); 4689 4690 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4691 "ahci_intr_set_device_bits: finished_tags = 0x%x", finished_tags); 4692 4693 /* 4694 * For NCQ commands, the software can determine which command has 4695 * already been transmitted to the device by checking PxCI register. 4696 */ 4697 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4698 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 4699 4700 issued_tags = ahci_portp->ahciport_pending_tags & 4701 ~port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp); 4702 4703 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4704 "ahci_intr_set_device_bits: port %d pending_tags = 0x%x " 4705 "port_cmd_issue = 0x%x", port, 4706 ahci_portp->ahciport_pending_tags, port_cmd_issue); 4707 4708 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4709 "ahci_intr_set_device_bits: issued_tags = 0x%x", issued_tags); 4710 4711 /* 4712 * Clear ahciport_pending_tags bit when the corresponding command 4713 * is already sent down to the device. 4714 */ 4715 while (issued_tags) { 4716 issued_slot = ddi_ffs(issued_tags) - 1; 4717 if (issued_slot == -1) { 4718 goto next; 4719 } 4720 CLEAR_BIT(ahci_portp->ahciport_pending_tags, issued_slot); 4721 CLEAR_BIT(issued_tags, issued_slot); 4722 } 4723 4724 next: 4725 while (finished_tags) { 4726 finished_slot = ddi_ffs(finished_tags) - 1; 4727 if (finished_slot == -1) { 4728 goto out; 4729 } 4730 4731 /* The command is certainly transmitted to the device */ 4732 ASSERT(!(ahci_portp->ahciport_pending_tags & 4733 (0x1 << finished_slot))); 4734 4735 satapkt = ahci_portp->ahciport_slot_pkts[finished_slot]; 4736 ASSERT(satapkt != NULL); 4737 4738 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4739 "ahci_intr_set_device_bits: sending up pkt 0x%p " 4740 "with SATA_PKT_COMPLETED", (void *)satapkt); 4741 4742 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, finished_slot); 4743 CLEAR_BIT(finished_tags, finished_slot); 4744 ahci_portp->ahciport_slot_pkts[finished_slot] = NULL; 4745 4746 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 4747 } 4748 out: 4749 AHCIDBG3(AHCIDBG_PKTCOMP|AHCIDBG_NCQ, ahci_ctlp, 4750 "ahci_intr_set_device_bits: port %d " 4751 "pending_ncq_tags = 0x%x pending_tags = 0x%x", 4752 port, ahci_portp->ahciport_pending_ncq_tags, 4753 ahci_portp->ahciport_pending_tags); 4754 4755 mutex_exit(&ahci_portp->ahciport_mutex); 4756 4757 return (AHCI_SUCCESS); 4758 } 4759 4760 /* 4761 * 1=Change in Current Connect Status. 0=No change in Current Connect Status. 4762 * This bit reflects the state of PxSERR.DIAG.X. This bit is only cleared 4763 * when PxSERR.DIAG.X is cleared. When PxSERR.DIAG.X is set to one, it 4764 * indicates a COMINIT signal was received. 4765 * 4766 * Hot plug insertion is detected by reception of a COMINIT signal from the 4767 * device. On reception of unsolicited COMINIT, the HBA shall generate a 4768 * COMRESET. If the COMINIT is in responce to a COMRESET, then the HBA shall 4769 * begin the normal communication negotiation sequence as outlined in the 4770 * Serial ATA 1.0a specification. When a COMRESET is sent to the device the 4771 * PxSSTS.DET field shall be cleared to 0h. When a COMINIT is received, the 4772 * PxSSTS.DET field shall be set to 1h. When the communication negotiation 4773 * sequence is complete and PhyRdy is true the PxSSTS.DET field shall be set 4774 * to 3h. Therefore, at the moment the ahci driver is going to check PhyRdy 4775 * to handle hot plug insertion. In this interrupt handler, just do nothing 4776 * but print some log message and clear the bit. 4777 */ 4778 static int 4779 ahci_intr_port_connect_change(ahci_ctl_t *ahci_ctlp, 4780 ahci_port_t *ahci_portp, uint8_t port) 4781 { 4782 #if AHCI_DEBUG 4783 uint32_t port_serror; 4784 #endif 4785 4786 mutex_enter(&ahci_portp->ahciport_mutex); 4787 4788 #if AHCI_DEBUG 4789 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4790 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 4791 4792 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4793 "ahci_intr_port_connect_change: port %d, " 4794 "port_serror = 0x%x", port, port_serror); 4795 #endif 4796 4797 /* Clear PxSERR.DIAG.X to clear the interrupt bit */ 4798 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4799 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 4800 SERROR_EXCHANGED_ERR); 4801 4802 mutex_exit(&ahci_portp->ahciport_mutex); 4803 4804 return (AHCI_SUCCESS); 4805 } 4806 4807 /* 4808 * Hot Plug Operation for platforms that support Mechanical Presence 4809 * Switches. 4810 * 4811 * When set, it indicates that a mechanical presence switch attached to this 4812 * port has been opened or closed, which may lead to a change in the connection 4813 * state of the device. This bit is only valid if both CAP.SMPS and PxCMD.MPSP 4814 * are set to '1'. 4815 * 4816 * At the moment, this interrupt is not needed and disabled and we just log 4817 * the debug message. 4818 */ 4819 static int 4820 ahci_intr_device_mechanical_presence_status(ahci_ctl_t *ahci_ctlp, 4821 ahci_port_t *ahci_portp, uint8_t port) 4822 { 4823 uint32_t cap_status, port_cmd_status; 4824 4825 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4826 "ahci_intr_device_mechanical_presence_status enter, " 4827 "port %d", port); 4828 4829 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4830 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 4831 4832 mutex_enter(&ahci_portp->ahciport_mutex); 4833 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4834 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 4835 4836 if (!(cap_status & AHCI_HBA_CAP_SMPS) || 4837 !(port_cmd_status & AHCI_CMD_STATUS_MPSP)) { 4838 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4839 "CAP.SMPS or PxCMD.MPSP is not set, so just ignore " 4840 "the interrupt: cap_status = 0x%x, " 4841 "port_cmd_status = 0x%x", cap_status, port_cmd_status); 4842 mutex_exit(&ahci_portp->ahciport_mutex); 4843 4844 return (AHCI_SUCCESS); 4845 } 4846 4847 #if AHCI_DEBUG 4848 if (port_cmd_status & AHCI_CMD_STATUS_MPSS) { 4849 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4850 "The mechanical presence switch is open: " 4851 "port %d, port_cmd_status = 0x%x", 4852 port, port_cmd_status); 4853 } else { 4854 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4855 "The mechanical presence switch is close: " 4856 "port %d, port_cmd_status = 0x%x", 4857 port, port_cmd_status); 4858 } 4859 #endif 4860 4861 mutex_exit(&ahci_portp->ahciport_mutex); 4862 4863 return (AHCI_SUCCESS); 4864 } 4865 4866 /* 4867 * Native Hot Plug Support. 4868 * 4869 * When set, it indicates that the internal PHYRDY signal changed state. 4870 * This bit reflects the state of PxSERR.DIAG.N. 4871 * 4872 * There are three kinds of conditions to generate this interrupt event: 4873 * 1. a device is inserted 4874 * 2. a device is disconnected 4875 * 3. when the link enters/exits a Partial or Slumber interface power 4876 * management state 4877 * 4878 * If inteface power management is enabled for a port, the PxSERR.DIAG.N 4879 * bit may be set due to the link entering the Partial or Slumber power 4880 * management state, rather than due to a hot plug insertion or removal 4881 * event. So far, the interface power management is disabled, so the 4882 * driver can reliably get removal detection notification via the 4883 * PxSERR.DIAG.N bit. 4884 */ 4885 static int 4886 ahci_intr_phyrdy_change(ahci_ctl_t *ahci_ctlp, 4887 ahci_port_t *ahci_portp, uint8_t port) 4888 { 4889 uint32_t port_sstatus = 0; /* No dev present & PHY not established. */ 4890 sata_device_t sdevice; 4891 int dev_exists_now = 0; 4892 int dev_existed_previously = 0; 4893 4894 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4895 "ahci_intr_phyrdy_change enter, port %d", port); 4896 4897 /* Clear PxSERR.DIAG.N to clear the interrupt bit */ 4898 mutex_enter(&ahci_portp->ahciport_mutex); 4899 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4900 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 4901 SERROR_PHY_RDY_CHG); 4902 mutex_exit(&ahci_portp->ahciport_mutex); 4903 4904 mutex_enter(&ahci_ctlp->ahcictl_mutex); 4905 if ((ahci_ctlp->ahcictl_sata_hba_tran == NULL) || 4906 (ahci_portp == NULL)) { 4907 /* The whole controller setup is not yet done. */ 4908 mutex_exit(&ahci_ctlp->ahcictl_mutex); 4909 return (AHCI_SUCCESS); 4910 } 4911 mutex_exit(&ahci_ctlp->ahcictl_mutex); 4912 4913 mutex_enter(&ahci_portp->ahciport_mutex); 4914 4915 /* SStatus tells the presence of device. */ 4916 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4917 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 4918 4919 if (SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_PHYCOM) { 4920 dev_exists_now = 1; 4921 } 4922 4923 if (ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) { 4924 dev_existed_previously = 1; 4925 } 4926 4927 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_NODEV) { 4928 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_NODEV; 4929 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 4930 "ahci_intr_phyrdy_change: port %d " 4931 "AHCI_PORT_FLAG_NODEV is cleared", port); 4932 if (dev_exists_now == 0) 4933 dev_existed_previously = 1; 4934 } 4935 4936 bzero((void *)&sdevice, sizeof (sata_device_t)); 4937 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 4938 sdevice.satadev_addr.qual = SATA_ADDR_CPORT; 4939 sdevice.satadev_addr.pmport = 0; 4940 sdevice.satadev_state = SATA_PSTATE_PWRON; 4941 ahci_portp->ahciport_port_state = SATA_PSTATE_PWRON; 4942 4943 if (dev_exists_now) { 4944 if (dev_existed_previously) { 4945 /* Things are fine now. The loss was temporary. */ 4946 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 4947 "ahci_intr_phyrdy_change port %d " 4948 "device link lost/established", port); 4949 4950 mutex_exit(&ahci_portp->ahciport_mutex); 4951 sata_hba_event_notify( 4952 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 4953 &sdevice, 4954 SATA_EVNT_LINK_LOST|SATA_EVNT_LINK_ESTABLISHED); 4955 mutex_enter(&ahci_portp->ahciport_mutex); 4956 4957 } else { 4958 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 4959 "ahci_intr_phyrdy_change: port %d " 4960 "device link established", port); 4961 4962 /* A new device has been detected. */ 4963 ahci_find_dev_signature(ahci_ctlp, ahci_portp, port); 4964 4965 /* Try to start the port */ 4966 if (ahci_start_port(ahci_ctlp, ahci_portp, port) 4967 != AHCI_SUCCESS) { 4968 sdevice.satadev_state |= SATA_PSTATE_FAILED; 4969 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 4970 "ahci_intr_phyrdy_change: port %d failed " 4971 "at start port", port); 4972 } 4973 4974 /* Clear the max queue depth for inserted device */ 4975 ahci_portp->ahciport_max_ncq_tags = 0; 4976 4977 mutex_exit(&ahci_portp->ahciport_mutex); 4978 sata_hba_event_notify( 4979 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 4980 &sdevice, 4981 SATA_EVNT_LINK_ESTABLISHED); 4982 mutex_enter(&ahci_portp->ahciport_mutex); 4983 4984 } 4985 } else { /* No device exists now */ 4986 4987 if (dev_existed_previously) { 4988 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 4989 "ahci_intr_phyrdy_change: port %d " 4990 "device link lost", port); 4991 4992 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port); 4993 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 4994 ahci_portp, port); 4995 4996 /* An existing device is lost. */ 4997 ahci_portp->ahciport_device_type = SATA_DTYPE_NONE; 4998 4999 mutex_exit(&ahci_portp->ahciport_mutex); 5000 sata_hba_event_notify( 5001 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5002 &sdevice, 5003 SATA_EVNT_LINK_LOST); 5004 mutex_enter(&ahci_portp->ahciport_mutex); 5005 } 5006 } 5007 5008 mutex_exit(&ahci_portp->ahciport_mutex); 5009 5010 return (AHCI_SUCCESS); 5011 } 5012 5013 /* 5014 * PxIS.UFS - Unknown FIS Error 5015 * 5016 * This interrupt event means an unknown FIS was received and has been 5017 * copied into system memory. An unknown FIS is not considered an illegal 5018 * FIS, unless the length received is more than 64 bytes. If an unknown 5019 * FIS arrives with length <= 64 bytes, it is posted and the HBA continues 5020 * normal operation. If the unknown FIS is more than 64 bytes, then it 5021 * won't be posted to memory and PxSERR.ERR.P will be set, which is then 5022 * a fatal error. 5023 * 5024 * PxIS.OFS - Overflow Error 5025 * 5026 * Command list overflow is defined as software building a command table 5027 * that has fewer total bytes than the transaction given to the device. 5028 * On device writes, the HBA will run out of data, and on reads, there 5029 * will be no room to put the data. 5030 * 5031 * For an overflow on data read, either PIO or DMA, the HBA will set 5032 * PxIS.OFS, and the HBA will do a best effort to continue, and it's a 5033 * non-fatal error when the HBA can continues. Sometimes, it will cause 5034 * a fatal error and need the software to do something. 5035 * 5036 * For an overflow on data write, setting PxIS.OFS is optional for both 5037 * DMA and PIO, and it's a fatal error, and a COMRESET is required by 5038 * software to clean up from this serious error. 5039 * 5040 * PxIS.INFS - Interface Non-Fatal Error 5041 * 5042 * This interrupt event indicates that the HBA encountered an error on 5043 * the Serial ATA interface but was able to continue operation. The kind 5044 * of error usually occurred during a non-Data FIS, and under this condition 5045 * the FIS will be re-transmitted by HBA automatically. 5046 * 5047 * When the FMA is implemented, there should be a stat structure to 5048 * record how many every kind of error happens. 5049 */ 5050 static int 5051 ahci_intr_non_fatal_error(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 5052 uint8_t port, uint32_t intr_status) 5053 { 5054 uint32_t port_serror; 5055 #if AHCI_DEBUG 5056 uint32_t port_cmd_status; 5057 uint32_t port_cmd_issue; 5058 uint32_t port_sactive; 5059 int current_slot; 5060 uint32_t current_tags; 5061 sata_pkt_t *satapkt; 5062 #endif 5063 5064 mutex_enter(&ahci_portp->ahciport_mutex); 5065 5066 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5067 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 5068 5069 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ENTRY|AHCIDBG_ERRS, ahci_ctlp, 5070 "ahci_intr_non_fatal_error: port %d, " 5071 "port_serror = 0x%x", port, port_serror); 5072 5073 ahci_log_serror_message(ahci_ctlp, port, port_serror, 1); 5074 5075 if (intr_status & AHCI_INTR_STATUS_UFS) { 5076 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 5077 "ahci port %d has unknown FIS error", port); 5078 5079 /* Clear the interrupt bit by clearing PxSERR.DIAG.F */ 5080 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5081 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 5082 SERROR_FIS_TYPE); 5083 } 5084 5085 #if AHCI_DEBUG 5086 if (intr_status & AHCI_INTR_STATUS_OFS) { 5087 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5088 "ahci port %d has overflow error", port); 5089 } 5090 5091 if (intr_status & AHCI_INTR_STATUS_INFS) { 5092 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5093 "ahci port %d has interface non fatal error", port); 5094 } 5095 5096 /* 5097 * Record the error occurred command's slot. 5098 */ 5099 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 5100 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 5101 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5102 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5103 5104 current_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 5105 AHCI_CMD_STATUS_CCS_SHIFT; 5106 5107 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 5108 satapkt = ahci_portp->ahciport_err_retri_pkt; 5109 ASSERT(satapkt != NULL); 5110 ASSERT(current_slot == 0); 5111 } else { 5112 satapkt = ahci_portp->ahciport_slot_pkts[current_slot]; 5113 } 5114 5115 if (satapkt != NULL) { 5116 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5117 "ahci_intr_non_fatal_error: pending_tags = 0x%x " 5118 "cmd 0x%x", ahci_portp->ahciport_pending_tags, 5119 satapkt->satapkt_cmd.satacmd_cmd_reg); 5120 5121 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5122 "ahci_intr_non_fatal_error: port %d, " 5123 "satapkt 0x%p is being processed when error occurs", 5124 port, (void *)satapkt); 5125 } 5126 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 5127 /* 5128 * For queued command, list those command which have already 5129 * been transmitted to the device and still not completed. 5130 */ 5131 port_sactive = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5132 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 5133 5134 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5135 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 5136 5137 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_NCQ|AHCIDBG_ERRS, ahci_ctlp, 5138 "ahci_intr_non_fatal_error: pending_ncq_tags = 0x%x " 5139 "port_sactive = 0x%x port_cmd_issue = 0x%x", 5140 ahci_portp->ahciport_pending_ncq_tags, 5141 port_sactive, port_cmd_issue); 5142 5143 current_tags = ahci_portp->ahciport_pending_ncq_tags & 5144 port_sactive & ~port_cmd_issue & 5145 AHCI_NCQ_SLOT_MASK(ahci_portp); 5146 5147 while (current_tags) { 5148 current_slot = ddi_ffs(current_tags) - 1; 5149 if (current_slot == -1) { 5150 goto out; 5151 } 5152 5153 satapkt = ahci_portp->ahciport_slot_pkts[current_slot]; 5154 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_NCQ|AHCIDBG_ERRS, 5155 ahci_ctlp, "ahci_intr_non_fatal_error: " 5156 "port %d, satapkt 0x%p is outstanding when " 5157 "error occurs", port, (void *)satapkt); 5158 } 5159 } 5160 out: 5161 #endif 5162 mutex_exit(&ahci_portp->ahciport_mutex); 5163 5164 return (AHCI_SUCCESS); 5165 } 5166 5167 /* 5168 * According to the AHCI spec, the error types include system memory 5169 * errors, interface errors, port multiplier errors, device errors, 5170 * command list overflow, command list underflow, native command 5171 * queuing tag errors and pio data transfer errors. 5172 * 5173 * System memory errors such as target abort, master abort, and parity 5174 * may cause the host to stop, and they are serious errors and needed 5175 * to be recovered with software intervention. When system software 5176 * has given a pointer to the HBA that doesn't exist in physical memory, 5177 * a master/target abort error occurs, and PxIS.HBFS will be set. A 5178 * data error such as CRC or parity occurs, the HBA aborts the transfer 5179 * (if necessary) and PxIS.HBDS will be set. 5180 * 5181 * Interface errors are errors that occur due to electrical issues on 5182 * the interface, or protocol miscommunication between the device and 5183 * HBA, and the respective PxSERR register bit will be set. And PxIS.IFS 5184 * (fatal) or PxIS.INFS (non-fatal) will be set. The conditions that 5185 * causes PxIS.IFS/PxIS.INFS to be set are 5186 * 1. in PxSERR.ERR, P bit is set to '1' 5187 * 2. in PxSERR.DIAG, C or H bit is set to '1' 5188 * 3. PhyRdy drop unexpectly, N bit is set to '1' 5189 * If the error occurred during a non-data FIS, the FIS must be 5190 * retransmitted, and the error is non-fatal and PxIS.INFS is set. If 5191 * the error occurred during a data FIS, the transfer will stop, so 5192 * the error is fatal and PxIS.IFS is set. 5193 * 5194 * When a FIS arrives that updates the taskfile, the HBA checks to see 5195 * if PxTFD.STS.ERR is set. If yes, PxIS.TFES will be set and the HBA 5196 * stops processing any more commands. 5197 * 5198 * Command list overflow is defined as software building a command table 5199 * that has fewer total bytes than the transaction given to the device. 5200 * On device writes, the HBA will run out of data, and on reads, there 5201 * will be no room to put the data. For an overflow on data read, either 5202 * PIO or DMA, the HBA will set PxIS.OFS, and it's a non-fatal error. 5203 * For an overflow on data write, setting PxIS.OFS is optional for both 5204 * DMA and PIO, and a COMRESET is required by software to clean up from 5205 * this serious error. 5206 * 5207 * Command list underflow is defined as software building a command 5208 * table that has more total bytes than the transaction given to the 5209 * device. For data writes, both PIO and DMA, the device will detect 5210 * an error and end the transfer. And these errors are most likely going 5211 * to be fatal errors that will cause the port to be restarted. For 5212 * data reads, the HBA updates its PRD byte count, and may be 5213 * able to continue normally, but is not required to. And The HBA is 5214 * not required to detect underflow conditions for native command 5215 * queuing command. 5216 * 5217 * The HBA does not actively check incoming DMA Setup FISes to ensure 5218 * that the PxSACT register bit for that slot is set. Existing error 5219 * mechanisms, such as host bus failure, or bad protocol, are used to 5220 * recover from this case. 5221 * 5222 * In accordance with Serial ATA 1.0a, DATA FISes prior to the final 5223 * DATA FIS must be an integral number of Dwords. If the HBA receives 5224 * a request which is not an integral number of Dwords, the HBA 5225 * set PxSERR.ERR.P to '1', set PxIS.IFS to '1' and stop running until 5226 * software restarts the port. And the HBA ensures that the size 5227 * of the DATA FIS received during a PIO command matches the size in 5228 * the Transfer Cound field of the preceding PIO Setup FIS, if not, the 5229 * HBA sets PxSERR.ERR.P to '1', set PxIS.IFS to '1', and then 5230 * stop running until software restarts the port. 5231 */ 5232 /* 5233 * the fatal errors include PxIS.IFS, PxIS.HBDS, PxIS.HBFS and PxIS.TFES. 5234 * 5235 * PxIS.IFS indicates that the hba encountered an error on the serial ata 5236 * interface which caused the transfer to stop. 5237 * 5238 * PxIS.HBDS indicates that the hba encountered a data error 5239 * (uncorrectable ecc/parity) when reading from or writing to system memory. 5240 * 5241 * PxIS.HBFS indicates that the hba encountered a host bus error that it 5242 * cannot recover from, such as a bad software pointer. 5243 * 5244 * PxIS.TFES is set whenever the status register is updated by the device 5245 * and the error bit (bit 0) is set. 5246 */ 5247 static int 5248 ahci_intr_fatal_error(ahci_ctl_t *ahci_ctlp, 5249 ahci_port_t *ahci_portp, uint8_t port, uint32_t intr_status) 5250 { 5251 uint32_t port_cmd_status; 5252 uint32_t port_serror; 5253 uint32_t task_file_status; 5254 int failed_slot; 5255 sata_pkt_t *spkt = NULL; 5256 uint8_t err_byte; 5257 ahci_event_arg_t *args; 5258 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 5259 5260 mutex_enter(&ahci_portp->ahciport_mutex); 5261 5262 /* 5263 * ahci_intr_phyrdy_change() may have rendered it to 5264 * SATA_DTYPE_NONE. 5265 */ 5266 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 5267 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 5268 "ahci_intr_fatal_error: port %d no device attached, " 5269 "and just return without doing anything", port); 5270 goto out0; 5271 } 5272 5273 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 5274 /* 5275 * Read PxCMD.CCS to determine the slot that the HBA 5276 * was processing when the error occurred. 5277 */ 5278 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5279 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5280 failed_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 5281 AHCI_CMD_STATUS_CCS_SHIFT; 5282 5283 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 5284 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5285 "ahci_intr_fatal_error: spkt 0x%p is being processed when " 5286 "fatal error occurred for port %d", spkt, port); 5287 5288 if (intr_status & AHCI_INTR_STATUS_TFES) { 5289 task_file_status = ddi_get32( 5290 ahci_ctlp->ahcictl_ahci_acc_handle, 5291 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 5292 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5293 "ahci_intr_fatal_error: port %d " 5294 "task_file_status = 0x%x", port, task_file_status); 5295 5296 err_byte = (task_file_status & AHCI_TFD_ERR_MASK) 5297 >> AHCI_TFD_ERR_SHIFT; 5298 5299 /* 5300 * Won't emit the error message if it is an IDENTIFY 5301 * DEVICE command sent to an ATAPI device. 5302 */ 5303 if ((spkt != NULL) && 5304 (spkt->satapkt_cmd.satacmd_cmd_reg == 5305 SATAC_ID_DEVICE) && 5306 (err_byte == SATA_ERROR_ABORT)) 5307 goto out1; 5308 5309 /* 5310 * Won't emit the error message if it is an ATAPI PACKET 5311 * command 5312 */ 5313 if ((spkt != NULL) && 5314 (spkt->satapkt_cmd.satacmd_cmd_reg == SATAC_PACKET)) 5315 goto out1; 5316 } 5317 } 5318 5319 ahci_log_fatal_error_message(ahci_ctlp, port, intr_status); 5320 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5321 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 5322 ahci_log_serror_message(ahci_ctlp, port, port_serror, 0); 5323 out1: 5324 /* Prepare the argument for the taskq */ 5325 args = ahci_portp->ahciport_event_args; 5326 args->ahciea_ctlp = (void *)ahci_ctlp; 5327 args->ahciea_portp = (void *)ahci_portp; 5328 args->ahciea_event = intr_status; 5329 5330 /* Start the taskq to handle error recovery */ 5331 if ((ddi_taskq_dispatch(ahci_ctlp->ahcictl_event_taskq, 5332 ahci_events_handler, 5333 (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) { 5334 cmn_err(CE_WARN, "!ahci%d: ahci start taskq for event handler " 5335 "failed", instance); 5336 } 5337 out0: 5338 mutex_exit(&ahci_portp->ahciport_mutex); 5339 5340 return (AHCI_SUCCESS); 5341 } 5342 5343 /* 5344 * Hot Plug Operation for platforms that support Cold Presence Detect. 5345 * 5346 * When set, a device status has changed as detected by the cold presence 5347 * detect logic. This bit can either be set due to a non-connected port 5348 * receiving a device, or a connected port having its device removed. 5349 * This bit is only valid if the port supports cold presence detect as 5350 * indicated by PxCMD.CPD set to '1'. 5351 * 5352 * At the moment, this interrupt is not needed and disabled and we just 5353 * log the debug message. 5354 */ 5355 static int 5356 ahci_intr_cold_port_detect(ahci_ctl_t *ahci_ctlp, 5357 ahci_port_t *ahci_portp, uint8_t port) 5358 { 5359 uint32_t port_cmd_status; 5360 sata_device_t sdevice; 5361 5362 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5363 "ahci_intr_cold_port_detect enter, port %d", port); 5364 5365 mutex_enter(&ahci_portp->ahciport_mutex); 5366 5367 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5368 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5369 if (!(port_cmd_status & AHCI_CMD_STATUS_CPD)) { 5370 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5371 "port %d does not support cold presence detect, so " 5372 "we just ignore this interrupt", port); 5373 mutex_exit(&ahci_portp->ahciport_mutex); 5374 return (AHCI_SUCCESS); 5375 } 5376 5377 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5378 "port %d device status has changed", port); 5379 5380 bzero((void *)&sdevice, sizeof (sata_device_t)); 5381 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 5382 sdevice.satadev_addr.qual = SATA_ADDR_CPORT; 5383 sdevice.satadev_addr.pmport = 0; 5384 sdevice.satadev_state = SATA_PSTATE_PWRON; 5385 5386 if (port_cmd_status & AHCI_CMD_STATUS_CPS) { 5387 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5388 "port %d: a device is hot plugged", port); 5389 mutex_exit(&ahci_portp->ahciport_mutex); 5390 sata_hba_event_notify( 5391 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5392 &sdevice, 5393 SATA_EVNT_DEVICE_ATTACHED); 5394 mutex_enter(&ahci_portp->ahciport_mutex); 5395 5396 } else { 5397 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5398 "port %d: a device is hot unplugged", port); 5399 mutex_exit(&ahci_portp->ahciport_mutex); 5400 sata_hba_event_notify( 5401 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5402 &sdevice, 5403 SATA_EVNT_DEVICE_DETACHED); 5404 mutex_enter(&ahci_portp->ahciport_mutex); 5405 } 5406 5407 mutex_exit(&ahci_portp->ahciport_mutex); 5408 5409 return (AHCI_SUCCESS); 5410 } 5411 5412 /* 5413 * Enable the interrupts for a particular port. 5414 * 5415 * WARNING!!! ahciport_mutex should be acquired before the function 5416 * is called. 5417 */ 5418 static void 5419 ahci_enable_port_intrs(ahci_ctl_t *ahci_ctlp, uint8_t port) 5420 { 5421 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5422 "ahci_enable_port_intrs enter, port %d", port); 5423 5424 /* 5425 * Clear port interrupt status before enabling interrupt 5426 */ 5427 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5428 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port), 5429 AHCI_PORT_INTR_MASK); 5430 5431 /* 5432 * Clear the pending bit from IS.IPS 5433 */ 5434 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5435 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp), (1 << port)); 5436 5437 /* 5438 * Enable the following interrupts: 5439 * Device to Host Register FIS Interrupt (DHRS) 5440 * PIO Setup FIS Interrupt (PSS) 5441 * Set Device Bits Interrupt (SDBS) 5442 * Unknown FIS Interrupt (UFS) 5443 * Port Connect Change Status (PCS) 5444 * PhyRdy Change Status (PRCS) 5445 * Overflow Status (OFS) 5446 * Interface Non-fatal Error Status (INFS) 5447 * Interface Fatal Error Status (IFS) 5448 * Host Bus Data Error Status (HBDS) 5449 * Host Bus Fatal Error Status (HBFS) 5450 * Task File Error Status (TFES) 5451 */ 5452 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5453 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), 5454 (AHCI_INTR_STATUS_DHRS | 5455 AHCI_INTR_STATUS_PSS | 5456 AHCI_INTR_STATUS_SDBS | 5457 AHCI_INTR_STATUS_UFS | 5458 AHCI_INTR_STATUS_DPS | 5459 AHCI_INTR_STATUS_PCS | 5460 AHCI_INTR_STATUS_PRCS | 5461 AHCI_INTR_STATUS_OFS | 5462 AHCI_INTR_STATUS_INFS | 5463 AHCI_INTR_STATUS_IFS | 5464 AHCI_INTR_STATUS_HBDS | 5465 AHCI_INTR_STATUS_HBFS | 5466 AHCI_INTR_STATUS_TFES)); 5467 } 5468 5469 /* 5470 * Enable interrupts for all the ports. 5471 * 5472 * WARNING!!! ahcictl_mutex should be acquired before the function 5473 * is called. 5474 */ 5475 static void 5476 ahci_enable_all_intrs(ahci_ctl_t *ahci_ctlp) 5477 { 5478 uint32_t ghc_control; 5479 5480 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_enable_all_intrs enter"); 5481 5482 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5483 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 5484 5485 ghc_control |= AHCI_HBA_GHC_IE; 5486 5487 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5488 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 5489 } 5490 5491 /* 5492 * Disable interrupts for a particular port. 5493 * 5494 * WARNING!!! ahciport_mutex should be acquired before the function 5495 * is called. 5496 */ 5497 static void 5498 ahci_disable_port_intrs(ahci_ctl_t *ahci_ctlp, uint8_t port) 5499 { 5500 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5501 "ahci_disable_port_intrs enter, port %d", port); 5502 5503 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5504 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), 0); 5505 } 5506 5507 /* 5508 * Disable interrupts for the whole HBA. 5509 * 5510 * The global bit is cleared, then all interrupt sources from all 5511 * ports are disabled. 5512 * 5513 * WARNING!!! ahcictl_mutex should be acquired before the function 5514 * is called. 5515 */ 5516 static void 5517 ahci_disable_all_intrs(ahci_ctl_t *ahci_ctlp) 5518 { 5519 uint32_t ghc_control; 5520 5521 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_disable_all_intrs enter"); 5522 5523 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5524 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 5525 5526 ghc_control &= ~ AHCI_HBA_GHC_IE; 5527 5528 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5529 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 5530 } 5531 5532 /* 5533 * Handle INTx and legacy interrupts. 5534 */ 5535 static int 5536 ahci_add_legacy_intrs(ahci_ctl_t *ahci_ctlp) 5537 { 5538 dev_info_t *dip = ahci_ctlp->ahcictl_dip; 5539 int actual, count = 0; 5540 int x, y, rc, inum = 0; 5541 5542 AHCIDBG0(AHCIDBG_ENTRY|AHCIDBG_INIT, ahci_ctlp, 5543 "ahci_add_legacy_intrs enter"); 5544 5545 /* get number of interrupts. */ 5546 rc = ddi_intr_get_nintrs(dip, DDI_INTR_TYPE_FIXED, &count); 5547 if ((rc != DDI_SUCCESS) || (count == 0)) { 5548 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5549 "ddi_intr_get_nintrs() failed, " 5550 "rc %d count %d\n", rc, count); 5551 return (DDI_FAILURE); 5552 } 5553 5554 /* Allocate an array of interrupt handles. */ 5555 ahci_ctlp->ahcictl_intr_size = count * sizeof (ddi_intr_handle_t); 5556 ahci_ctlp->ahcictl_intr_htable = 5557 kmem_zalloc(ahci_ctlp->ahcictl_intr_size, KM_SLEEP); 5558 5559 /* call ddi_intr_alloc(). */ 5560 rc = ddi_intr_alloc(dip, ahci_ctlp->ahcictl_intr_htable, 5561 DDI_INTR_TYPE_FIXED, 5562 inum, count, &actual, DDI_INTR_ALLOC_STRICT); 5563 5564 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5565 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5566 "ddi_intr_alloc() failed, rc %d\n", rc); 5567 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5568 ahci_ctlp->ahcictl_intr_size); 5569 return (DDI_FAILURE); 5570 } 5571 5572 if (actual < count) { 5573 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5574 "Requested: %d, Received: %d", count, actual); 5575 5576 for (x = 0; x < actual; x++) { 5577 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5578 } 5579 5580 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5581 ahci_ctlp->ahcictl_intr_size); 5582 return (DDI_FAILURE); 5583 } 5584 5585 ahci_ctlp->ahcictl_intr_cnt = actual; 5586 5587 /* Get intr priority. */ 5588 if (ddi_intr_get_pri(ahci_ctlp->ahcictl_intr_htable[0], 5589 &ahci_ctlp->ahcictl_intr_pri) != DDI_SUCCESS) { 5590 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5591 "ddi_intr_get_pri() failed"); 5592 5593 for (x = 0; x < actual; x++) { 5594 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5595 } 5596 5597 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5598 ahci_ctlp->ahcictl_intr_size); 5599 return (DDI_FAILURE); 5600 } 5601 5602 /* Test for high level interrupt. */ 5603 if (ahci_ctlp->ahcictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 5604 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5605 "ahci_add_legacy_intrs: Hi level intr not supported"); 5606 5607 for (x = 0; x < actual; x++) { 5608 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5609 } 5610 5611 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5612 sizeof (ddi_intr_handle_t)); 5613 5614 return (DDI_FAILURE); 5615 } 5616 5617 /* Call ddi_intr_add_handler(). */ 5618 for (x = 0; x < actual; x++) { 5619 if (ddi_intr_add_handler(ahci_ctlp->ahcictl_intr_htable[x], 5620 ahci_intr, (caddr_t)ahci_ctlp, NULL) != DDI_SUCCESS) { 5621 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5622 "ddi_intr_add_handler() failed"); 5623 5624 for (y = 0; y < actual; y++) { 5625 (void) ddi_intr_free( 5626 ahci_ctlp->ahcictl_intr_htable[y]); 5627 } 5628 5629 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5630 ahci_ctlp->ahcictl_intr_size); 5631 return (DDI_FAILURE); 5632 } 5633 } 5634 5635 /* Call ddi_intr_enable() for legacy interrupts. */ 5636 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5637 (void) ddi_intr_enable(ahci_ctlp->ahcictl_intr_htable[x]); 5638 } 5639 5640 return (DDI_SUCCESS); 5641 } 5642 5643 /* 5644 * Handle MSI interrupts. 5645 */ 5646 static int 5647 ahci_add_msi_intrs(ahci_ctl_t *ahci_ctlp) 5648 { 5649 dev_info_t *dip = ahci_ctlp->ahcictl_dip; 5650 int count, avail, actual; 5651 int x, y, rc, inum = 0; 5652 5653 AHCIDBG0(AHCIDBG_ENTRY|AHCIDBG_INIT, ahci_ctlp, 5654 "ahci_add_msi_intrs enter"); 5655 5656 /* get number of interrupts. */ 5657 rc = ddi_intr_get_nintrs(dip, DDI_INTR_TYPE_MSI, &count); 5658 if ((rc != DDI_SUCCESS) || (count == 0)) { 5659 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5660 "ddi_intr_get_nintrs() failed, " 5661 "rc %d count %d\n", rc, count); 5662 return (DDI_FAILURE); 5663 } 5664 5665 /* get number of available interrupts. */ 5666 rc = ddi_intr_get_navail(dip, DDI_INTR_TYPE_MSI, &avail); 5667 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5668 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5669 "ddi_intr_get_navail() failed, " 5670 "rc %d avail %d\n", rc, avail); 5671 return (DDI_FAILURE); 5672 } 5673 5674 #if AHCI_DEBUG 5675 if (avail < count) { 5676 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5677 "ddi_intr_get_nvail returned %d, navail() returned %d", 5678 count, avail); 5679 } 5680 #endif 5681 5682 /* Allocate an array of interrupt handles. */ 5683 ahci_ctlp->ahcictl_intr_size = count * sizeof (ddi_intr_handle_t); 5684 ahci_ctlp->ahcictl_intr_htable = 5685 kmem_alloc(ahci_ctlp->ahcictl_intr_size, KM_SLEEP); 5686 5687 /* call ddi_intr_alloc(). */ 5688 rc = ddi_intr_alloc(dip, ahci_ctlp->ahcictl_intr_htable, 5689 DDI_INTR_TYPE_MSI, inum, count, &actual, DDI_INTR_ALLOC_NORMAL); 5690 5691 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5692 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5693 "ddi_intr_alloc() failed, rc %d\n", rc); 5694 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5695 ahci_ctlp->ahcictl_intr_size); 5696 return (DDI_FAILURE); 5697 } 5698 5699 /* use interrupt count returned */ 5700 #if AHCI_DEBUG 5701 if (actual < count) { 5702 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5703 "Requested: %d, Received: %d", count, actual); 5704 } 5705 #endif 5706 5707 ahci_ctlp->ahcictl_intr_cnt = actual; 5708 5709 /* 5710 * Get priority for first msi, assume remaining are all the same. 5711 */ 5712 if (ddi_intr_get_pri(ahci_ctlp->ahcictl_intr_htable[0], 5713 &ahci_ctlp->ahcictl_intr_pri) != DDI_SUCCESS) { 5714 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5715 "ddi_intr_get_pri() failed"); 5716 5717 /* Free already allocated intr. */ 5718 for (y = 0; y < actual; y++) { 5719 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[y]); 5720 } 5721 5722 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5723 ahci_ctlp->ahcictl_intr_size); 5724 return (DDI_FAILURE); 5725 } 5726 5727 /* Test for high level interrupt. */ 5728 if (ahci_ctlp->ahcictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 5729 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5730 "ahci_add_msi_intrs: Hi level intr not supported"); 5731 5732 /* Free already allocated intr. */ 5733 for (y = 0; y < actual; y++) { 5734 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[y]); 5735 } 5736 5737 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5738 sizeof (ddi_intr_handle_t)); 5739 5740 return (DDI_FAILURE); 5741 } 5742 5743 /* Call ddi_intr_add_handler(). */ 5744 for (x = 0; x < actual; x++) { 5745 if (ddi_intr_add_handler(ahci_ctlp->ahcictl_intr_htable[x], 5746 ahci_intr, (caddr_t)ahci_ctlp, NULL) != DDI_SUCCESS) { 5747 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5748 "ddi_intr_add_handler() failed"); 5749 5750 /* Free already allocated intr. */ 5751 for (y = 0; y < actual; y++) { 5752 (void) ddi_intr_free( 5753 ahci_ctlp->ahcictl_intr_htable[y]); 5754 } 5755 5756 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5757 ahci_ctlp->ahcictl_intr_size); 5758 return (DDI_FAILURE); 5759 } 5760 } 5761 5762 5763 (void) ddi_intr_get_cap(ahci_ctlp->ahcictl_intr_htable[0], 5764 &ahci_ctlp->ahcictl_intr_cap); 5765 5766 if (ahci_ctlp->ahcictl_intr_cap & DDI_INTR_FLAG_BLOCK) { 5767 /* Call ddi_intr_block_enable() for MSI. */ 5768 (void) ddi_intr_block_enable(ahci_ctlp->ahcictl_intr_htable, 5769 ahci_ctlp->ahcictl_intr_cnt); 5770 } else { 5771 /* Call ddi_intr_enable() for MSI non block enable. */ 5772 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5773 (void) ddi_intr_enable( 5774 ahci_ctlp->ahcictl_intr_htable[x]); 5775 } 5776 } 5777 5778 return (DDI_SUCCESS); 5779 } 5780 5781 /* 5782 * Removes the registered interrupts irrespective of whether they 5783 * were legacy or MSI. 5784 * 5785 * WARNING!!! The controller interrupts must be disabled before calling 5786 * this routine. 5787 */ 5788 static void 5789 ahci_rem_intrs(ahci_ctl_t *ahci_ctlp) 5790 { 5791 int x; 5792 5793 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_rem_intrs entered"); 5794 5795 /* Disable all interrupts. */ 5796 if ((ahci_ctlp->ahcictl_intr_type == DDI_INTR_TYPE_MSI) && 5797 (ahci_ctlp->ahcictl_intr_cap & DDI_INTR_FLAG_BLOCK)) { 5798 /* Call ddi_intr_block_disable(). */ 5799 (void) ddi_intr_block_disable(ahci_ctlp->ahcictl_intr_htable, 5800 ahci_ctlp->ahcictl_intr_cnt); 5801 } else { 5802 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5803 (void) ddi_intr_disable( 5804 ahci_ctlp->ahcictl_intr_htable[x]); 5805 } 5806 } 5807 5808 /* Call ddi_intr_remove_handler(). */ 5809 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5810 (void) ddi_intr_remove_handler( 5811 ahci_ctlp->ahcictl_intr_htable[x]); 5812 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5813 } 5814 5815 kmem_free(ahci_ctlp->ahcictl_intr_htable, ahci_ctlp->ahcictl_intr_size); 5816 } 5817 5818 /* 5819 * This routine tries to put port into P:NotRunning state by clearing 5820 * PxCMD.ST. HBA will clear PxCI to 0h, PxSACT to 0h, PxCMD.CCS to 0h 5821 * and PxCMD.CR to '0'. 5822 * 5823 * WARNING!!! ahciport_mutex should be acquired before the function 5824 * is called. 5825 */ 5826 static int 5827 ahci_put_port_into_notrunning_state(ahci_ctl_t *ahci_ctlp, 5828 ahci_port_t *ahci_portp, uint8_t port) 5829 { 5830 uint32_t port_cmd_status; 5831 int loop_count; 5832 5833 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5834 "ahci_put_port_into_notrunning_state enter: port %d", port); 5835 5836 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5837 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5838 5839 port_cmd_status &= ~AHCI_CMD_STATUS_ST; 5840 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5841 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), port_cmd_status); 5842 5843 /* Wait until PxCMD.CR is cleared */ 5844 loop_count = 0; 5845 do { 5846 port_cmd_status = 5847 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5848 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5849 5850 if (loop_count++ > AHCI_POLLRATE_PORT_IDLE) { 5851 AHCIDBG2(AHCIDBG_INIT, ahci_ctlp, 5852 "clearing port %d CMD.CR timeout, " 5853 "port_cmd_status = 0x%x", port, 5854 port_cmd_status); 5855 /* 5856 * We are effectively timing out after 0.5 sec. 5857 * This value is specified in AHCI spec. 5858 */ 5859 break; 5860 } 5861 5862 /* Wait for 10 millisec */ 5863 drv_usecwait(10000); 5864 } while (port_cmd_status & AHCI_CMD_STATUS_CR); 5865 5866 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_STARTED; 5867 5868 if (port_cmd_status & AHCI_CMD_STATUS_CR) { 5869 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 5870 "ahci_put_port_into_notrunning_state: failed to clear " 5871 "PxCMD.CR to '0' after loop count: %d, and " 5872 "port_cmd_status = 0x%x", loop_count, port_cmd_status); 5873 return (AHCI_FAILURE); 5874 } else { 5875 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 5876 "ahci_put_port_into_notrunning_state: succeeded to clear " 5877 "PxCMD.CR to '0' after loop count: %d, and " 5878 "port_cmd_status = 0x%x", loop_count, port_cmd_status); 5879 return (AHCI_SUCCESS); 5880 } 5881 } 5882 5883 /* 5884 * First clear PxCMD.ST, and then check PxTFD. If both PxTFD.STS.BSY 5885 * and PxTFD.STS.DRQ cleared to '0', it means the device is in a 5886 * stable state, then set PxCMD.ST to '1' to start the port directly. 5887 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then issue a 5888 * COMRESET to the device to put it in an idle state. 5889 * 5890 * The fifth argument returns whether the port reset is involved during 5891 * the process. 5892 * 5893 * The routine will be called under six scenarios: 5894 * 1. Initialize the port 5895 * 2. To abort the packet(s) 5896 * 3. To reset the port 5897 * 4. To activate the port 5898 * 5. Fatal error recovery 5899 * 6. To abort the timeout packet(s) 5900 * 5901 * WARNING!!! ahciport_mutex should be acquired before the function 5902 * is called. And ahciport_mutex will be released before the reset 5903 * event is reported to sata module by calling sata_hba_event_notify, 5904 * and then be acquired again later. 5905 * 5906 * NOTES!!! During this procedure, PxSERR register will be cleared, and 5907 * according to the spec, the clearance of three bits will also clear 5908 * three interrupt status bits. 5909 * 1. PxSERR.DIAG.F will clear PxIS.UFS 5910 * 2. PxSERR.DIAG.X will clear PxIS.PCS 5911 * 3. PxSERR.DIAG.N will clear PxIS.PRCS 5912 * 5913 * Among these three interrupt events, the driver needs to take care of 5914 * PxIS.PRCS, which is the hot plug event. When the driver found out 5915 * a device was unplugged, it will call the interrupt handler. 5916 */ 5917 static int 5918 ahci_restart_port_wait_till_ready(ahci_ctl_t *ahci_ctlp, 5919 ahci_port_t *ahci_portp, uint8_t port, int flag, int *reset_flag) 5920 { 5921 uint32_t port_sstatus; 5922 uint32_t task_file_status; 5923 sata_device_t sdevice; 5924 int rval; 5925 int dev_exists_begin = 0; 5926 int dev_exists_end = 0; 5927 5928 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5929 "ahci_restart_port_wait_till_ready: port %d enter", port); 5930 5931 if ((flag != AHCI_PORT_INIT) && 5932 (ahci_portp->ahciport_device_type != SATA_DTYPE_NONE)) 5933 dev_exists_begin = 1; 5934 5935 /* First clear PxCMD.ST */ 5936 rval = ahci_put_port_into_notrunning_state(ahci_ctlp, ahci_portp, 5937 port); 5938 if (rval != AHCI_SUCCESS) 5939 /* 5940 * If PxCMD.CR does not clear within a reasonable time, it 5941 * may assume the interface is in a hung condition and may 5942 * continue with issuing the port reset. 5943 */ 5944 goto reset; 5945 5946 /* Then clear PxSERR */ 5947 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5948 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 5949 AHCI_SERROR_CLEAR_ALL); 5950 5951 /* Then get PxTFD */ 5952 task_file_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5953 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 5954 5955 /* 5956 * Check whether the device is in a stable status, if yes, 5957 * then start the port directly. However for ahci_tran_dport_reset, 5958 * we may have to perform a port reset. 5959 */ 5960 if (!(task_file_status & (AHCI_TFD_STS_BSY | AHCI_TFD_STS_DRQ)) && 5961 !(flag & AHCI_PORT_RESET)) 5962 goto out; 5963 5964 reset: 5965 /* 5966 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then issue 5967 * a COMRESET to the device 5968 */ 5969 rval = ahci_port_reset(ahci_ctlp, ahci_portp, port); 5970 5971 if (reset_flag != NULL) 5972 *reset_flag = 1; 5973 5974 /* Indicate to the framework that a reset has happened. */ 5975 if ((ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) && 5976 !(flag & AHCI_RESET_NO_EVENTS_UP)) { 5977 /* Set the reset in progress flag */ 5978 ahci_portp->ahciport_reset_in_progress = 1; 5979 5980 bzero((void *)&sdevice, sizeof (sata_device_t)); 5981 sdevice.satadev_addr.cport = 5982 ahci_ctlp->ahcictl_port_to_cport[port]; 5983 sdevice.satadev_addr.pmport = 0; 5984 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 5985 5986 sdevice.satadev_state = SATA_DSTATE_RESET | 5987 SATA_DSTATE_PWR_ACTIVE; 5988 if (ahci_ctlp->ahcictl_sata_hba_tran) { 5989 mutex_exit(&ahci_portp->ahciport_mutex); 5990 sata_hba_event_notify( 5991 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5992 &sdevice, 5993 SATA_EVNT_DEVICE_RESET); 5994 mutex_enter(&ahci_portp->ahciport_mutex); 5995 } 5996 5997 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 5998 "port %d sending event up: SATA_EVNT_RESET", port); 5999 } else { 6000 ahci_portp->ahciport_reset_in_progress = 0; 6001 } 6002 6003 out: 6004 /* Start the port if not in initialization phase */ 6005 if (flag & AHCI_PORT_INIT) 6006 return (rval); 6007 6008 (void) ahci_start_port(ahci_ctlp, ahci_portp, port); 6009 6010 /* SStatus tells the presence of device. */ 6011 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6012 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 6013 6014 if (SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_PHYCOM) { 6015 dev_exists_end = 1; 6016 ASSERT(ahci_portp->ahciport_device_type != SATA_DTYPE_NONE); 6017 } 6018 6019 /* Check whether a hot plug event happened */ 6020 if (dev_exists_begin == 1 && dev_exists_end == 0) { 6021 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6022 "ahci_restart_port_wait_till_ready: port %d " 6023 "device is removed", port); 6024 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_NODEV; 6025 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6026 "ahci_restart_port_wait_till_ready: port %d " 6027 "AHCI_PORT_FLAG_NODEV flag is set", port); 6028 mutex_exit(&ahci_portp->ahciport_mutex); 6029 (void) ahci_intr_phyrdy_change(ahci_ctlp, ahci_portp, port); 6030 mutex_enter(&ahci_portp->ahciport_mutex); 6031 } 6032 6033 return (rval); 6034 } 6035 6036 /* 6037 * This routine may be called under four scenarios: 6038 * a) do the recovery from fatal error 6039 * b) or we need to timeout some commands 6040 * c) or we need to abort some commands 6041 * d) or we need reset device/port/controller 6042 * 6043 * In all these scenarios, we need to send any pending unfinished 6044 * commands up to sata framework. 6045 * 6046 * WARNING!!! ahciport_mutex should be acquired before the function is called. 6047 */ 6048 static void 6049 ahci_mop_commands(ahci_ctl_t *ahci_ctlp, 6050 ahci_port_t *ahci_portp, 6051 uint32_t slot_status, 6052 uint32_t failed_tags, 6053 uint32_t timeout_tags, 6054 uint32_t aborted_tags, 6055 uint32_t reset_tags) 6056 { 6057 uint32_t finished_tags = 0; 6058 uint32_t unfinished_tags = 0; 6059 int tmp_slot; 6060 sata_pkt_t *satapkt; 6061 int ncq_cmd_in_progress = 0; 6062 int err_retri_cmd_in_progress = 0; 6063 6064 AHCIDBG2(AHCIDBG_ERRS|AHCIDBG_ENTRY, ahci_ctlp, 6065 "ahci_mop_commands entered: port: %d slot_status: 0x%x", 6066 ahci_portp->ahciport_port_num, slot_status); 6067 6068 AHCIDBG4(AHCIDBG_ERRS|AHCIDBG_ENTRY, ahci_ctlp, 6069 "ahci_mop_commands: failed_tags: 0x%x, " 6070 "timeout_tags: 0x%x aborted_tags: 0x%x, " 6071 "reset_tags: 0x%x", failed_tags, 6072 timeout_tags, aborted_tags, reset_tags); 6073 6074 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6075 finished_tags = ahci_portp->ahciport_pending_tags & 6076 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 6077 6078 unfinished_tags = slot_status & 6079 AHCI_SLOT_MASK(ahci_ctlp) & 6080 ~failed_tags & 6081 ~aborted_tags & 6082 ~reset_tags & 6083 ~timeout_tags; 6084 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6085 ncq_cmd_in_progress = 1; 6086 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 6087 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 6088 6089 unfinished_tags = slot_status & 6090 AHCI_NCQ_SLOT_MASK(ahci_portp) & 6091 ~failed_tags & 6092 ~aborted_tags & 6093 ~reset_tags & 6094 ~timeout_tags; 6095 } else if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6096 6097 /* 6098 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT is 6099 * set, it means REQUEST SENSE or READ LOG EXT command doesn't 6100 * complete successfully due to one of the following three 6101 * conditions: 6102 * 6103 * 1. Fatal error - failed_tags includes its slot 6104 * 2. Timed out - timeout_tags includes its slot 6105 * 3. Aborted when hot unplug - aborted_tags includes its 6106 * slot 6107 * 6108 * Please note that the command is always sent down in Slot 0 6109 */ 6110 err_retri_cmd_in_progress = 1; 6111 AHCIDBG1(AHCIDBG_ERRS|AHCIDBG_NCQ, ahci_ctlp, 6112 "ahci_mop_commands is called for port %d while " 6113 "REQUEST SENSE or READ LOG EXT for error retrieval " 6114 "is being executed", ahci_portp->ahciport_port_num); 6115 ASSERT(ahci_portp->ahciport_mop_in_progress > 1); 6116 ASSERT(slot_status == 0x1); 6117 } 6118 6119 /* Send up finished packets with SATA_PKT_COMPLETED */ 6120 while (finished_tags) { 6121 tmp_slot = ddi_ffs(finished_tags) - 1; 6122 if (tmp_slot == -1) { 6123 break; 6124 } 6125 6126 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6127 ASSERT(satapkt != NULL); 6128 6129 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_mop_commands: " 6130 "sending up pkt 0x%p with SATA_PKT_COMPLETED", 6131 (void *)satapkt); 6132 6133 /* 6134 * Cannot fetch the return register content since the port 6135 * was restarted, so the corresponding tag will be set to 6136 * aborted tags. 6137 */ 6138 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) { 6139 CLEAR_BIT(finished_tags, tmp_slot); 6140 aborted_tags |= tmp_slot; 6141 continue; 6142 } 6143 6144 if (ncq_cmd_in_progress) 6145 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6146 tmp_slot); 6147 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6148 CLEAR_BIT(finished_tags, tmp_slot); 6149 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6150 6151 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 6152 } 6153 6154 /* Send up failed packets with SATA_PKT_DEV_ERROR. */ 6155 while (failed_tags) { 6156 if (err_retri_cmd_in_progress) { 6157 satapkt = ahci_portp->ahciport_err_retri_pkt; 6158 ASSERT(satapkt != NULL); 6159 ASSERT(failed_tags == 0x1); 6160 6161 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6162 "sending up pkt 0x%p with SATA_PKT_DEV_ERROR", 6163 (void *)satapkt); 6164 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_DEV_ERROR); 6165 break; 6166 } 6167 6168 tmp_slot = ddi_ffs(failed_tags) - 1; 6169 if (tmp_slot == -1) { 6170 break; 6171 } 6172 6173 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6174 ASSERT(satapkt != NULL); 6175 6176 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6177 "sending up pkt 0x%p with SATA_PKT_DEV_ERROR", 6178 (void *)satapkt); 6179 6180 if (ncq_cmd_in_progress) 6181 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6182 tmp_slot); 6183 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6184 CLEAR_BIT(failed_tags, tmp_slot); 6185 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6186 6187 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_DEV_ERROR); 6188 } 6189 6190 /* Send up timeout packets with SATA_PKT_TIMEOUT. */ 6191 while (timeout_tags) { 6192 if (err_retri_cmd_in_progress) { 6193 satapkt = ahci_portp->ahciport_err_retri_pkt; 6194 ASSERT(satapkt != NULL); 6195 ASSERT(timeout_tags == 0x1); 6196 6197 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6198 "sending up pkt 0x%p with SATA_PKT_TIMEOUT", 6199 (void *)satapkt); 6200 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_TIMEOUT); 6201 break; 6202 } 6203 6204 tmp_slot = ddi_ffs(timeout_tags) - 1; 6205 if (tmp_slot == -1) { 6206 break; 6207 } 6208 6209 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6210 ASSERT(satapkt != NULL); 6211 6212 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6213 "sending up pkt 0x%p with SATA_PKT_TIMEOUT", 6214 (void *)satapkt); 6215 6216 if (ncq_cmd_in_progress) 6217 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6218 tmp_slot); 6219 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6220 CLEAR_BIT(timeout_tags, tmp_slot); 6221 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6222 6223 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_TIMEOUT); 6224 } 6225 6226 /* Send up aborted packets with SATA_PKT_ABORTED */ 6227 while (aborted_tags) { 6228 if (err_retri_cmd_in_progress) { 6229 satapkt = ahci_portp->ahciport_err_retri_pkt; 6230 ASSERT(satapkt != NULL); 6231 ASSERT(aborted_tags == 0x1); 6232 6233 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6234 "sending up pkt 0x%p with SATA_PKT_ABORTED", 6235 (void *)satapkt); 6236 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_ABORTED); 6237 break; 6238 } 6239 6240 tmp_slot = ddi_ffs(aborted_tags) - 1; 6241 if (tmp_slot == -1) { 6242 break; 6243 } 6244 6245 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6246 ASSERT(satapkt != NULL); 6247 6248 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6249 "sending up pkt 0x%p with SATA_PKT_ABORTED", 6250 (void *)satapkt); 6251 6252 if (ncq_cmd_in_progress) 6253 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6254 tmp_slot); 6255 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6256 CLEAR_BIT(aborted_tags, tmp_slot); 6257 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6258 6259 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_ABORTED); 6260 } 6261 6262 /* Send up reset packets with SATA_PKT_RESET. */ 6263 while (reset_tags) { 6264 tmp_slot = ddi_ffs(reset_tags) - 1; 6265 if (tmp_slot == -1) { 6266 break; 6267 } 6268 6269 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6270 ASSERT(satapkt != NULL); 6271 6272 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6273 "sending up pkt 0x%p with SATA_PKT_RESET", 6274 (void *)satapkt); 6275 6276 if (ncq_cmd_in_progress) 6277 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6278 tmp_slot); 6279 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6280 CLEAR_BIT(reset_tags, tmp_slot); 6281 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6282 6283 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_RESET); 6284 } 6285 6286 /* Send up unfinished packets with SATA_PKT_RESET */ 6287 while (unfinished_tags) { 6288 tmp_slot = ddi_ffs(unfinished_tags) - 1; 6289 if (tmp_slot == -1) { 6290 break; 6291 } 6292 6293 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6294 ASSERT(satapkt != NULL); 6295 6296 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6297 "sending up pkt 0x%p with SATA_PKT_RESET", 6298 (void *)satapkt); 6299 6300 if (ncq_cmd_in_progress) 6301 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6302 tmp_slot); 6303 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6304 CLEAR_BIT(unfinished_tags, tmp_slot); 6305 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6306 6307 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_RESET); 6308 } 6309 6310 ahci_portp->ahciport_mop_in_progress--; 6311 ASSERT(ahci_portp->ahciport_mop_in_progress >= 0); 6312 6313 if (ahci_portp->ahciport_mop_in_progress == 0) 6314 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_MOPPING; 6315 } 6316 6317 /* 6318 * This routine is going to first request a READ LOG EXT sata pkt from sata 6319 * module, and then deliver it to the HBA to get the ncq failure context. 6320 * The return value is the exactly failed tags. 6321 */ 6322 static uint32_t 6323 ahci_get_rdlogext_data(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 6324 uint8_t port) 6325 { 6326 sata_device_t sdevice; 6327 sata_pkt_t *rdlog_spkt, *spkt; 6328 ddi_dma_handle_t buf_dma_handle; 6329 int loop_count; 6330 int rval; 6331 int failed_slot; 6332 uint32_t failed_tags = 0; 6333 struct sata_ncq_error_recovery_page *ncq_err_page; 6334 6335 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_NCQ, ahci_ctlp, 6336 "ahci_get_rdlogext_data enter: port %d", port); 6337 6338 /* Prepare the sdevice data */ 6339 bzero((void *)&sdevice, sizeof (sata_device_t)); 6340 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 6341 6342 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 6343 sdevice.satadev_addr.pmport = 0; 6344 6345 /* 6346 * Call the sata hba interface to get a rdlog spkt 6347 */ 6348 loop_count = 0; 6349 loop: 6350 rdlog_spkt = sata_get_error_retrieval_pkt(ahci_ctlp->ahcictl_dip, 6351 &sdevice, SATA_ERR_RETR_PKT_TYPE_NCQ); 6352 if (rdlog_spkt == NULL) { 6353 if (loop_count++ < AHCI_POLLRATE_GET_SPKT) { 6354 /* Sleep for a while */ 6355 delay(AHCI_10MS_TICKS); 6356 goto loop; 6357 } 6358 /* Timed out after 1s */ 6359 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6360 "failed to get rdlog spkt for port %d", port); 6361 return (failed_tags); 6362 } 6363 6364 ASSERT(rdlog_spkt->satapkt_op_mode & SATA_OPMODE_SYNCH); 6365 6366 /* 6367 * This flag is used to handle the specific error recovery when the 6368 * READ LOG EXT command gets a failure (fatal error or time-out). 6369 */ 6370 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_RDLOGEXT; 6371 6372 /* 6373 * This start is not supposed to fail because after port is restarted, 6374 * the whole command list is empty. 6375 */ 6376 ahci_portp->ahciport_err_retri_pkt = rdlog_spkt; 6377 (void) ahci_do_sync_start(ahci_ctlp, ahci_portp, port, rdlog_spkt); 6378 ahci_portp->ahciport_err_retri_pkt = NULL; 6379 6380 /* Remove the flag after READ LOG EXT command is completed */ 6381 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_RDLOGEXT; 6382 6383 if (rdlog_spkt->satapkt_reason == SATA_PKT_COMPLETED) { 6384 /* Update the request log data */ 6385 buf_dma_handle = *(ddi_dma_handle_t *) 6386 (rdlog_spkt->satapkt_cmd.satacmd_err_ret_buf_handle); 6387 rval = ddi_dma_sync(buf_dma_handle, 0, 0, 6388 DDI_DMA_SYNC_FORKERNEL); 6389 if (rval == DDI_SUCCESS) { 6390 ncq_err_page = 6391 (struct sata_ncq_error_recovery_page *)rdlog_spkt-> 6392 satapkt_cmd.satacmd_bp->b_un.b_addr; 6393 6394 /* Get the failed tag */ 6395 failed_slot = ncq_err_page->ncq_tag; 6396 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6397 "ahci_get_rdlogext_data: port %d " 6398 "failed slot %d", port, failed_slot); 6399 if (failed_slot & NQ) { 6400 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 6401 "the failed slot is not a valid tag"); 6402 goto out; 6403 } 6404 6405 failed_slot &= NCQ_TAG_MASK; 6406 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 6407 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6408 "ahci_get_rdlogext_data: failed spkt 0x%p", 6409 (void *)spkt); 6410 if (spkt == NULL) { 6411 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 6412 "the failed slot spkt is NULL") 6413 goto out; 6414 } 6415 6416 failed_tags = 0x1 << failed_slot; 6417 6418 /* Fill out the error context */ 6419 ahci_copy_ncq_err_page(&spkt->satapkt_cmd, 6420 ncq_err_page); 6421 ahci_update_sata_registers(ahci_ctlp, port, 6422 &spkt->satapkt_device); 6423 } 6424 } 6425 out: 6426 sata_free_error_retrieval_pkt(rdlog_spkt); 6427 6428 return (failed_tags); 6429 } 6430 6431 /* 6432 * This routine is going to first request a REQUEST SENSE sata pkt from sata 6433 * module, and then deliver it to the HBA to get the sense data and copy 6434 * the sense data back to the orignal failed sata pkt, and free the REQUEST 6435 * SENSE sata pkt later. 6436 */ 6437 static void 6438 ahci_get_rqsense_data(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 6439 uint8_t port, sata_pkt_t *spkt) 6440 { 6441 sata_device_t sdevice; 6442 sata_pkt_t *rs_spkt; 6443 sata_cmd_t *sata_cmd; 6444 ddi_dma_handle_t buf_dma_handle; 6445 int loop_count; 6446 #if AHCI_DEBUG 6447 struct scsi_extended_sense *rqsense; 6448 #endif 6449 6450 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 6451 "ahci_get_rqsense_data enter: port %d", port); 6452 6453 /* Prepare the sdevice data */ 6454 bzero((void *)&sdevice, sizeof (sata_device_t)); 6455 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 6456 6457 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 6458 sdevice.satadev_addr.pmport = 0; 6459 6460 sata_cmd = &spkt->satapkt_cmd; 6461 6462 /* 6463 * Call the sata hba interface to get a rs spkt 6464 */ 6465 loop_count = 0; 6466 loop: 6467 rs_spkt = sata_get_error_retrieval_pkt(ahci_ctlp->ahcictl_dip, 6468 &sdevice, SATA_ERR_RETR_PKT_TYPE_ATAPI); 6469 if (rs_spkt == NULL) { 6470 if (loop_count++ < AHCI_POLLRATE_GET_SPKT) { 6471 /* Sleep for a while */ 6472 delay(AHCI_10MS_TICKS); 6473 goto loop; 6474 6475 } 6476 /* Timed out after 1s */ 6477 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6478 "failed to get rs spkt for port %d", port); 6479 return; 6480 } 6481 6482 ASSERT(rs_spkt->satapkt_op_mode & SATA_OPMODE_SYNCH); 6483 6484 /* 6485 * This flag is used to handle the specific error recovery when the 6486 * REQUEST SENSE command gets a faiure (fatal error or time-out). 6487 */ 6488 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_RQSENSE; 6489 6490 /* 6491 * This start is not supposed to fail because after port is restarted, 6492 * the whole command list is empty. 6493 */ 6494 ahci_portp->ahciport_err_retri_pkt = rs_spkt; 6495 (void) ahci_do_sync_start(ahci_ctlp, ahci_portp, port, rs_spkt); 6496 ahci_portp->ahciport_err_retri_pkt = NULL; 6497 6498 /* Remove the flag after REQUEST SENSE command is completed */ 6499 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_RQSENSE; 6500 6501 if (rs_spkt->satapkt_reason == SATA_PKT_COMPLETED) { 6502 /* Update the request sense data */ 6503 buf_dma_handle = *(ddi_dma_handle_t *) 6504 (rs_spkt->satapkt_cmd.satacmd_err_ret_buf_handle); 6505 (void) ddi_dma_sync(buf_dma_handle, 0, 0, 6506 DDI_DMA_SYNC_FORKERNEL); 6507 /* Copy the request sense data */ 6508 bcopy(rs_spkt-> 6509 satapkt_cmd.satacmd_bp->b_un.b_addr, 6510 &sata_cmd->satacmd_rqsense, 6511 SATA_ATAPI_MIN_RQSENSE_LEN); 6512 #if AHCI_DEBUG 6513 rqsense = (struct scsi_extended_sense *) 6514 sata_cmd->satacmd_rqsense; 6515 6516 /* Dump the sense data */ 6517 AHCIDBG0(AHCIDBG_SENSEDATA, ahci_ctlp, "\n"); 6518 AHCIDBG2(AHCIDBG_SENSEDATA, ahci_ctlp, 6519 "Sense data for satapkt %p ATAPI cmd 0x%x", 6520 spkt, sata_cmd->satacmd_acdb[0]); 6521 AHCIDBG5(AHCIDBG_SENSEDATA, ahci_ctlp, 6522 " es_code 0x%x es_class 0x%x " 6523 "es_key 0x%x es_add_code 0x%x " 6524 "es_qual_code 0x%x", 6525 rqsense->es_code, rqsense->es_class, 6526 rqsense->es_key, rqsense->es_add_code, 6527 rqsense->es_qual_code); 6528 #endif 6529 } 6530 6531 sata_free_error_retrieval_pkt(rs_spkt); 6532 } 6533 6534 /* 6535 * Fatal errors will cause the HBA to enter the ERR: Fatal state. To recover, 6536 * the port must be restarted. When the HBA detects thus error, it may try 6537 * to abort a transfer. And if the transfer was aborted, the device is 6538 * expected to send a D2H Register FIS with PxTFD.STS.ERR set to '1' and both 6539 * PxTFD.STS.BSY and PxTFD.STS.DRQ cleared to '0'. Then system software knows 6540 * that the device is in a stable status and transfers may be restarted without 6541 * issuing a COMRESET to the device. If PxTFD.STS.BSY or PxTFD.STS.DRQ is set, 6542 * then the software will send the COMRESET to do the port reset. 6543 * 6544 * Software should perform the appropriate error recovery actions based on 6545 * whether non-queued commands were being issued or natived command queuing 6546 * commands were being issued. 6547 * 6548 * And software will complete the command that had the error with error mark 6549 * to higher level software. 6550 * 6551 * Fatal errors include the following: 6552 * PxIS.IFS - Interface Fatal Error Status 6553 * PxIS.HBDS - Host Bus Data Error Status 6554 * PxIS.HBFS - Host Bus Fatal Error Status 6555 * PxIS.TFES - Task File Error Status 6556 * 6557 * WARNING!!! ahciport_mutex should be acquired before the function is called. 6558 */ 6559 static void 6560 ahci_fatal_error_recovery_handler(ahci_ctl_t *ahci_ctlp, 6561 ahci_port_t *ahci_portp, uint8_t port, uint32_t intr_status) 6562 { 6563 uint32_t port_cmd_status; 6564 uint32_t slot_status = 0; 6565 uint32_t failed_tags = 0; 6566 int failed_slot; 6567 int reset_flag = 0; 6568 ahci_fis_d2h_register_t *ahci_rcvd_fisp; 6569 sata_cmd_t *sata_cmd = NULL; 6570 sata_pkt_t *spkt = NULL; 6571 6572 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 6573 "ahci_fatal_error_recovery_handler enter: port %d", port); 6574 6575 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 6576 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6577 6578 /* Read PxCI to see which commands are still outstanding */ 6579 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6580 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 6581 6582 /* 6583 * Read PxCMD.CCS to determine the slot that the HBA 6584 * was processing when the error occurred. 6585 */ 6586 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6587 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 6588 failed_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 6589 AHCI_CMD_STATUS_CCS_SHIFT; 6590 6591 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6592 spkt = ahci_portp->ahciport_err_retri_pkt; 6593 ASSERT(spkt != NULL); 6594 } else { 6595 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 6596 if (spkt == NULL) { 6597 /* May happen when interface errors occur? */ 6598 goto next; 6599 } 6600 } 6601 6602 sata_cmd = &spkt->satapkt_cmd; 6603 6604 /* Fill out the status and error registers for PxIS.TFES */ 6605 if (intr_status & AHCI_INTR_STATUS_TFES) { 6606 ahci_rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis-> 6607 ahcirf_d2h_register_fis); 6608 6609 /* Copy the error context back to the sata_cmd */ 6610 ahci_copy_err_cnxt(sata_cmd, ahci_rcvd_fisp); 6611 } 6612 6613 /* The failed command must be one of the outstanding commands */ 6614 failed_tags = 0x1 << failed_slot; 6615 ASSERT(failed_tags & slot_status); 6616 6617 /* Update the sata registers, especially PxSERR register */ 6618 ahci_update_sata_registers(ahci_ctlp, port, 6619 &spkt->satapkt_device); 6620 6621 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6622 /* Read PxSACT to see which commands are still outstanding */ 6623 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6624 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 6625 } 6626 next: 6627 6628 #if AHCI_DEBUG 6629 /* 6630 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT flag is 6631 * set, it means a fatal error happened after REQUEST SENSE command 6632 * or READ LOG EXT command is delivered to the HBA during the error 6633 * recovery process. At this time, the only outstanding command is 6634 * supposed to be REQUEST SENSE command or READ LOG EXT command. 6635 */ 6636 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6637 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6638 "ahci_fatal_error_recovery_handler: port %d REQUEST SENSE " 6639 "command or READ LOG EXT command for error data retrieval " 6640 "failed", port); 6641 ASSERT(slot_status == 0x1); 6642 ASSERT(failed_slot == 0x1); 6643 ASSERT(spkt->satapkt_cmd.satacmd_acdb[0] == 6644 SCMD_REQUEST_SENSE || 6645 spkt->satapkt_cmd.satacmd_cmd_reg == 6646 SATAC_READ_LOG_EXT); 6647 } 6648 #endif 6649 6650 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 6651 ahci_portp->ahciport_mop_in_progress++; 6652 6653 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 6654 port, NULL, &reset_flag); 6655 6656 /* 6657 * Won't retrieve error information: 6658 * 1. Port reset was involved to recover 6659 * 2. Device is gone 6660 * 3. IDENTIFY DEVICE command sent to ATAPI device 6661 * 4. REQUEST SENSE or READ LOG EXT command during error recovery 6662 */ 6663 if (reset_flag || 6664 ahci_portp->ahciport_device_type == SATA_DTYPE_NONE || 6665 spkt && spkt->satapkt_cmd.satacmd_cmd_reg == SATAC_ID_DEVICE || 6666 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 6667 goto out; 6668 6669 /* 6670 * Deliver READ LOG EXT to gather information about the error when 6671 * a COMRESET has not been performed as part of the error recovery 6672 * during NCQ command processing. 6673 */ 6674 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6675 failed_tags = ahci_get_rdlogext_data(ahci_ctlp, 6676 ahci_portp, port); 6677 goto out; 6678 } 6679 6680 /* 6681 * Deliver REQUEST SENSE for ATAPI command to gather information about 6682 * the error when a COMRESET has not been performed as part of the 6683 * error recovery. 6684 */ 6685 if (spkt && ahci_portp->ahciport_device_type == SATA_DTYPE_ATAPICD) 6686 ahci_get_rqsense_data(ahci_ctlp, ahci_portp, port, spkt); 6687 out: 6688 AHCIDBG5(AHCIDBG_ERRS, ahci_ctlp, 6689 "ahci_fatal_error_recovery_handler: port %d interface error " 6690 "occurred slot_status = 0x%x, pending_tags = 0x%x, " 6691 "pending_ncq_tags = 0x%x failed_tags = 0x%x", 6692 port, slot_status, ahci_portp->ahciport_pending_tags, 6693 ahci_portp->ahciport_pending_ncq_tags, failed_tags); 6694 6695 ahci_mop_commands(ahci_ctlp, 6696 ahci_portp, 6697 slot_status, 6698 failed_tags, /* failed tags */ 6699 0, /* timeout tags */ 6700 0, /* aborted tags */ 6701 0); /* reset tags */ 6702 } 6703 6704 /* 6705 * Handle events - fatal error recovery 6706 */ 6707 static void 6708 ahci_events_handler(void *args) 6709 { 6710 ahci_event_arg_t *ahci_event_arg; 6711 ahci_ctl_t *ahci_ctlp; 6712 ahci_port_t *ahci_portp; 6713 uint32_t event; 6714 uint8_t port; 6715 6716 ahci_event_arg = (ahci_event_arg_t *)args; 6717 6718 ahci_ctlp = ahci_event_arg->ahciea_ctlp; 6719 ahci_portp = ahci_event_arg->ahciea_portp; 6720 event = ahci_event_arg->ahciea_event; 6721 port = ahci_portp->ahciport_port_num; 6722 6723 AHCIDBG2(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 6724 "ahci_events_handler enter: port %d intr_status = 0x%x", 6725 port, event); 6726 6727 mutex_enter(&ahci_portp->ahciport_mutex); 6728 6729 /* 6730 * ahci_intr_phyrdy_change() may have rendered it to 6731 * SATA_DTYPE_NONE. 6732 */ 6733 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 6734 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 6735 "ahci_events_handler: port %d no device attached, " 6736 "and just return without doing anything", port); 6737 goto out; 6738 } 6739 6740 if (event & (AHCI_INTR_STATUS_IFS | 6741 AHCI_INTR_STATUS_HBDS | 6742 AHCI_INTR_STATUS_HBFS | 6743 AHCI_INTR_STATUS_TFES)) 6744 ahci_fatal_error_recovery_handler(ahci_ctlp, ahci_portp, 6745 port, event); 6746 6747 out: 6748 mutex_exit(&ahci_portp->ahciport_mutex); 6749 } 6750 6751 /* 6752 * ahci_watchdog_handler() and ahci_do_sync_start will call us if they 6753 * detect there are some commands which are timed out. 6754 */ 6755 static void 6756 ahci_timeout_pkts(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 6757 uint8_t port, uint32_t tmp_timeout_tags) 6758 { 6759 uint32_t slot_status = 0; 6760 uint32_t finished_tags = 0; 6761 uint32_t timeout_tags = 0; 6762 6763 AHCIDBG1(AHCIDBG_TIMEOUT|AHCIDBG_ENTRY, ahci_ctlp, 6764 "ahci_timeout_pkts enter: port %d", port); 6765 6766 mutex_enter(&ahci_portp->ahciport_mutex); 6767 6768 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 6769 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6770 /* Read PxCI to see which commands are still outstanding */ 6771 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6772 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 6773 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6774 /* Read PxSACT to see which commands are still outstanding */ 6775 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6776 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 6777 } 6778 6779 #if AHCI_DEBUG 6780 /* 6781 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT flag is 6782 * set, it means a fatal error happened after REQUEST SENSE command 6783 * or READ LOG EXT command is delivered to the HBA during the error 6784 * recovery process. At this time, the only outstanding command is 6785 * supposed to be REQUEST SENSE command or READ LOG EXT command. 6786 */ 6787 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6788 AHCIDBG4(AHCIDBG_ERRS|AHCIDBG_TIMEOUT, ahci_ctlp, 6789 "ahci_timeout_pkts called while REQUEST SENSE " 6790 "command or READ LOG EXT command for error recovery " 6791 "timed out timeout_tags = 0x%x, slot_status = 0x%x, " 6792 "pending_tags = 0x%x, pending_ncq_tags = 0x%x", 6793 tmp_timeout_tags, slot_status, 6794 ahci_portp->ahciport_pending_tags, 6795 ahci_portp->ahciport_pending_ncq_tags); 6796 ASSERT(slot_status == 0x1); 6797 } 6798 #endif 6799 6800 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 6801 ahci_portp->ahciport_mop_in_progress++; 6802 6803 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 6804 port, NULL, NULL); 6805 6806 /* 6807 * Re-identify timeout tags because some previously checked commands 6808 * could already complete. 6809 */ 6810 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6811 finished_tags = ahci_portp->ahciport_pending_tags & 6812 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 6813 timeout_tags = tmp_timeout_tags & ~finished_tags; 6814 6815 AHCIDBG5(AHCIDBG_TIMEOUT, ahci_ctlp, 6816 "ahci_timeout_pkts: port %d, finished_tags = 0x%x, " 6817 "timeout_tags = 0x%x, port_cmd_issue = 0x%x, " 6818 "pending_tags = 0x%x ", 6819 port, finished_tags, timeout_tags, 6820 slot_status, ahci_portp->ahciport_pending_tags); 6821 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6822 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 6823 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 6824 timeout_tags = tmp_timeout_tags & ~finished_tags; 6825 6826 AHCIDBG5(AHCIDBG_TIMEOUT|AHCIDBG_NCQ, ahci_ctlp, 6827 "ahci_timeout_pkts: port %d, finished_tags = 0x%x, " 6828 "timeout_tags = 0x%x, port_sactive = 0x%x, " 6829 "pending_ncq_tags = 0x%x ", 6830 port, finished_tags, timeout_tags, 6831 slot_status, ahci_portp->ahciport_pending_ncq_tags); 6832 } else if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6833 timeout_tags = tmp_timeout_tags; 6834 } 6835 6836 ahci_mop_commands(ahci_ctlp, 6837 ahci_portp, 6838 slot_status, 6839 0, /* failed tags */ 6840 timeout_tags, /* timeout tags */ 6841 0, /* aborted tags */ 6842 0); /* reset tags */ 6843 6844 mutex_exit(&ahci_portp->ahciport_mutex); 6845 } 6846 6847 /* 6848 * Watchdog handler kicks in every 5 seconds to timeout any commands pending 6849 * for long time. 6850 */ 6851 static void 6852 ahci_watchdog_handler(ahci_ctl_t *ahci_ctlp) 6853 { 6854 ahci_port_t *ahci_portp; 6855 sata_pkt_t *spkt; 6856 uint32_t pending_tags; 6857 uint32_t timeout_tags; 6858 uint32_t port_cmd_status; 6859 uint32_t port_sactive; 6860 uint8_t port; 6861 int tmp_slot; 6862 int current_slot; 6863 uint32_t current_tags; 6864 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 6865 /* max number of cycles this packet should survive */ 6866 int max_life_cycles; 6867 6868 /* how many cycles this packet survived so far */ 6869 int watched_cycles; 6870 6871 mutex_enter(&ahci_ctlp->ahcictl_mutex); 6872 6873 AHCIDBG0(AHCIDBG_TIMEOUT|AHCIDBG_ENTRY, ahci_ctlp, 6874 "ahci_watchdog_handler entered"); 6875 6876 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 6877 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 6878 continue; 6879 } 6880 6881 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 6882 6883 mutex_enter(&ahci_portp->ahciport_mutex); 6884 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 6885 mutex_exit(&ahci_portp->ahciport_mutex); 6886 continue; 6887 } 6888 6889 /* Skip the check for those ports in error recovery */ 6890 if ((ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) && 6891 !(ERR_RETRI_CMD_IN_PROGRESS(ahci_portp))) { 6892 mutex_exit(&ahci_portp->ahciport_mutex); 6893 continue; 6894 } 6895 6896 pending_tags = 0; 6897 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6898 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 6899 6900 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6901 current_slot = 0; 6902 pending_tags = 0x1; 6903 } else if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6904 current_slot = 6905 (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 6906 AHCI_CMD_STATUS_CCS_SHIFT; 6907 pending_tags = ahci_portp->ahciport_pending_tags; 6908 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6909 port_sactive = ddi_get32( 6910 ahci_ctlp->ahcictl_ahci_acc_handle, 6911 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 6912 current_tags = port_sactive & 6913 ~port_cmd_status & 6914 AHCI_NCQ_SLOT_MASK(ahci_portp); 6915 pending_tags = ahci_portp->ahciport_pending_ncq_tags; 6916 } 6917 6918 timeout_tags = 0; 6919 while (pending_tags) { 6920 tmp_slot = ddi_ffs(pending_tags) - 1; 6921 if (tmp_slot == -1) { 6922 break; 6923 } 6924 6925 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 6926 spkt = ahci_portp->ahciport_err_retri_pkt; 6927 else 6928 spkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6929 6930 if ((spkt != NULL) && spkt->satapkt_time && 6931 !(spkt->satapkt_op_mode & SATA_OPMODE_POLLING)) { 6932 /* 6933 * We are overloading satapkt_hba_driver_private 6934 * with watched_cycle count. 6935 * 6936 * If a packet has survived for more than it's 6937 * max life cycles, it is a candidate for time 6938 * out. 6939 */ 6940 watched_cycles = (int)(intptr_t) 6941 spkt->satapkt_hba_driver_private; 6942 watched_cycles++; 6943 max_life_cycles = (spkt->satapkt_time + 6944 ahci_watchdog_timeout - 1) / 6945 ahci_watchdog_timeout; 6946 6947 spkt->satapkt_hba_driver_private = 6948 (void *)(intptr_t)watched_cycles; 6949 6950 if (watched_cycles <= max_life_cycles) 6951 goto next; 6952 6953 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6954 "the current slot is %d", current_slot); 6955 /* 6956 * We need to check whether the HBA has 6957 * begun to execute the command, if not, 6958 * then re-set the timer of the command. 6959 */ 6960 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) && 6961 (tmp_slot != current_slot) || 6962 NCQ_CMD_IN_PROGRESS(ahci_portp) && 6963 ((0x1 << tmp_slot) & current_tags)) { 6964 spkt->satapkt_hba_driver_private = 6965 (void *)(intptr_t)0; 6966 } else { 6967 timeout_tags |= (0x1 << tmp_slot); 6968 cmn_err(CE_WARN, "!ahci%d: watchdog " 6969 "port %d satapkt 0x%p timed out\n", 6970 instance, port, (void *)spkt); 6971 } 6972 } 6973 next: 6974 CLEAR_BIT(pending_tags, tmp_slot); 6975 } 6976 6977 if (timeout_tags) { 6978 mutex_exit(&ahci_portp->ahciport_mutex); 6979 mutex_exit(&ahci_ctlp->ahcictl_mutex); 6980 ahci_timeout_pkts(ahci_ctlp, ahci_portp, 6981 port, timeout_tags); 6982 mutex_enter(&ahci_ctlp->ahcictl_mutex); 6983 mutex_enter(&ahci_portp->ahciport_mutex); 6984 } 6985 6986 mutex_exit(&ahci_portp->ahciport_mutex); 6987 } 6988 6989 /* Re-install the watchdog timeout handler */ 6990 if (ahci_ctlp->ahcictl_timeout_id != 0) { 6991 ahci_ctlp->ahcictl_timeout_id = 6992 timeout((void (*)(void *))ahci_watchdog_handler, 6993 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 6994 } 6995 6996 mutex_exit(&ahci_ctlp->ahcictl_mutex); 6997 } 6998 6999 /* 7000 * Fill the error context into sata_cmd for non-queued command error. 7001 */ 7002 static void 7003 ahci_copy_err_cnxt(sata_cmd_t *scmd, ahci_fis_d2h_register_t *rfisp) 7004 { 7005 scmd->satacmd_status_reg = GET_RFIS_STATUS(rfisp); 7006 scmd->satacmd_error_reg = GET_RFIS_ERROR(rfisp); 7007 scmd->satacmd_sec_count_lsb = GET_RFIS_SECTOR_COUNT(rfisp); 7008 scmd->satacmd_lba_low_lsb = GET_RFIS_CYL_LOW(rfisp); 7009 scmd->satacmd_lba_mid_lsb = GET_RFIS_CYL_MID(rfisp); 7010 scmd->satacmd_lba_high_lsb = GET_RFIS_CYL_HI(rfisp); 7011 scmd->satacmd_device_reg = GET_RFIS_DEV_HEAD(rfisp); 7012 7013 if (scmd->satacmd_addr_type == ATA_ADDR_LBA48) { 7014 scmd->satacmd_sec_count_msb = GET_RFIS_SECTOR_COUNT_EXP(rfisp); 7015 scmd->satacmd_lba_low_msb = GET_RFIS_CYL_LOW_EXP(rfisp); 7016 scmd->satacmd_lba_mid_msb = GET_RFIS_CYL_MID_EXP(rfisp); 7017 scmd->satacmd_lba_high_msb = GET_RFIS_CYL_HI_EXP(rfisp); 7018 } 7019 } 7020 7021 /* 7022 * Fill the ncq error page into sata_cmd for queued command error. 7023 */ 7024 static void 7025 ahci_copy_ncq_err_page(sata_cmd_t *scmd, 7026 struct sata_ncq_error_recovery_page *ncq_err_page) 7027 { 7028 scmd->satacmd_sec_count_msb = ncq_err_page->ncq_sector_count_ext; 7029 scmd->satacmd_sec_count_lsb = ncq_err_page->ncq_sector_count; 7030 scmd->satacmd_lba_low_msb = ncq_err_page->ncq_sector_number_ext; 7031 scmd->satacmd_lba_low_lsb = ncq_err_page->ncq_sector_number; 7032 scmd->satacmd_lba_mid_msb = ncq_err_page->ncq_cyl_low_ext; 7033 scmd->satacmd_lba_mid_lsb = ncq_err_page->ncq_cyl_low; 7034 scmd->satacmd_lba_high_msb = ncq_err_page->ncq_cyl_high_ext; 7035 scmd->satacmd_lba_high_lsb = ncq_err_page->ncq_cyl_high; 7036 scmd->satacmd_device_reg = ncq_err_page->ncq_dev_head; 7037 scmd->satacmd_status_reg = ncq_err_page->ncq_status; 7038 scmd->satacmd_error_reg = ncq_err_page->ncq_error; 7039 } 7040 7041 /* 7042 * Put the respective register value to sata_cmd_t for satacmd_flags. 7043 */ 7044 static void 7045 ahci_copy_out_regs(sata_cmd_t *scmd, ahci_fis_d2h_register_t *rfisp) 7046 { 7047 if (scmd->satacmd_flags.sata_copy_out_sec_count_msb) 7048 scmd->satacmd_sec_count_msb = GET_RFIS_SECTOR_COUNT_EXP(rfisp); 7049 if (scmd->satacmd_flags.sata_copy_out_lba_low_msb) 7050 scmd->satacmd_lba_low_msb = GET_RFIS_CYL_LOW_EXP(rfisp); 7051 if (scmd->satacmd_flags.sata_copy_out_lba_mid_msb) 7052 scmd->satacmd_lba_mid_msb = GET_RFIS_CYL_MID_EXP(rfisp); 7053 if (scmd->satacmd_flags.sata_copy_out_lba_high_msb) 7054 scmd->satacmd_lba_high_msb = GET_RFIS_CYL_HI_EXP(rfisp); 7055 if (scmd->satacmd_flags.sata_copy_out_sec_count_lsb) 7056 scmd->satacmd_sec_count_lsb = GET_RFIS_SECTOR_COUNT(rfisp); 7057 if (scmd->satacmd_flags.sata_copy_out_lba_low_lsb) 7058 scmd->satacmd_lba_low_lsb = GET_RFIS_CYL_LOW(rfisp); 7059 if (scmd->satacmd_flags.sata_copy_out_lba_mid_lsb) 7060 scmd->satacmd_lba_mid_lsb = GET_RFIS_CYL_MID(rfisp); 7061 if (scmd->satacmd_flags.sata_copy_out_lba_high_lsb) 7062 scmd->satacmd_lba_high_lsb = GET_RFIS_CYL_HI(rfisp); 7063 if (scmd->satacmd_flags.sata_copy_out_device_reg) 7064 scmd->satacmd_device_reg = GET_RFIS_DEV_HEAD(rfisp); 7065 if (scmd->satacmd_flags.sata_copy_out_error_reg) 7066 scmd->satacmd_error_reg = GET_RFIS_ERROR(rfisp); 7067 } 7068 7069 static void 7070 ahci_log_fatal_error_message(ahci_ctl_t *ahci_ctlp, uint8_t port, 7071 uint32_t intr_status) 7072 { 7073 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 7074 7075 if (intr_status & AHCI_INTR_STATUS_IFS) 7076 cmn_err(CE_WARN, "ahci%d: ahci port %d has interface fatal " 7077 "error", instance, port); 7078 7079 if (intr_status & AHCI_INTR_STATUS_HBDS) 7080 cmn_err(CE_WARN, "ahci%d: ahci port %d has bus data error", 7081 instance, port); 7082 7083 if (intr_status & AHCI_INTR_STATUS_HBFS) 7084 cmn_err(CE_WARN, "ahci%d: ahci port %d has bus fatal error", 7085 instance, port); 7086 7087 if (intr_status & AHCI_INTR_STATUS_TFES) 7088 cmn_err(CE_WARN, "ahci%d: ahci port %d has task file error", 7089 instance, port); 7090 7091 cmn_err(CE_WARN, "ahci%d: ahci port %d is trying to do error " 7092 "recovery", instance, port); 7093 } 7094 7095 /* 7096 * Dump the serror message to the log. 7097 */ 7098 static void 7099 ahci_log_serror_message(ahci_ctl_t *ahci_ctlp, uint8_t port, 7100 uint32_t port_serror, int debug_only) 7101 { 7102 static char err_buf[512]; 7103 static char err_msg_header[16]; 7104 char *err_msg = err_buf; 7105 7106 *err_buf = '\0'; 7107 *err_msg_header = '\0'; 7108 7109 if (port_serror & SERROR_DATA_ERR_FIXED) { 7110 err_msg = strcat(err_msg, 7111 "\tRecovered Data Integrity Error (I)\n"); 7112 } 7113 7114 if (port_serror & SERROR_COMM_ERR_FIXED) { 7115 err_msg = strcat(err_msg, 7116 "\tRecovered Communication Error (M)\n"); 7117 } 7118 7119 if (port_serror & SERROR_DATA_ERR) { 7120 err_msg = strcat(err_msg, 7121 "\tTransient Data Integrity Error (T)\n"); 7122 } 7123 7124 if (port_serror & SERROR_PERSISTENT_ERR) { 7125 err_msg = strcat(err_msg, 7126 "\tPersistent Communication or Data Integrity Error (C)\n"); 7127 } 7128 7129 if (port_serror & SERROR_PROTOCOL_ERR) { 7130 err_msg = strcat(err_msg, "\tProtocol Error (P)\n"); 7131 } 7132 7133 if (port_serror & SERROR_INT_ERR) { 7134 err_msg = strcat(err_msg, "\tInternal Error (E)\n"); 7135 } 7136 7137 if (port_serror & SERROR_PHY_RDY_CHG) { 7138 err_msg = strcat(err_msg, "\tPhyRdy Change (N)\n"); 7139 } 7140 7141 if (port_serror & SERROR_PHY_INT_ERR) { 7142 err_msg = strcat(err_msg, "\tPhy Internal Error (I)\n"); 7143 } 7144 7145 if (port_serror & SERROR_COMM_WAKE) { 7146 err_msg = strcat(err_msg, "\tComm Wake (W)\n"); 7147 } 7148 7149 if (port_serror & SERROR_10B_TO_8B_ERR) { 7150 err_msg = strcat(err_msg, "\t10B to 8B Decode Error (B)\n"); 7151 } 7152 7153 if (port_serror & SERROR_DISPARITY_ERR) { 7154 err_msg = strcat(err_msg, "\tDisparity Error (D)\n"); 7155 } 7156 7157 if (port_serror & SERROR_CRC_ERR) { 7158 err_msg = strcat(err_msg, "\tCRC Error (C)\n"); 7159 } 7160 7161 if (port_serror & SERROR_HANDSHAKE_ERR) { 7162 err_msg = strcat(err_msg, "\tHandshake Error (H)\n"); 7163 } 7164 7165 if (port_serror & SERROR_LINK_SEQ_ERR) { 7166 err_msg = strcat(err_msg, "\tLink Sequence Error (S)\n"); 7167 } 7168 7169 if (port_serror & SERROR_TRANS_ERR) { 7170 err_msg = strcat(err_msg, 7171 "\tTransport state transition error (T)\n"); 7172 } 7173 7174 if (port_serror & SERROR_FIS_TYPE) { 7175 err_msg = strcat(err_msg, "\tUnknown FIS Type (F)\n"); 7176 } 7177 7178 if (port_serror & SERROR_EXCHANGED_ERR) { 7179 err_msg = strcat(err_msg, "\tExchanged (X)\n"); 7180 } 7181 7182 if (err_msg == NULL) 7183 return; 7184 7185 if (debug_only) { 7186 (void) sprintf(err_msg_header, "port %d", port); 7187 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, err_msg_header); 7188 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, err_msg); 7189 } else if (ahci_ctlp) { 7190 cmn_err(CE_WARN, "ahci%d: %s %s", 7191 ddi_get_instance(ahci_ctlp->ahcictl_dip), 7192 err_msg_header, err_msg); 7193 } else { 7194 cmn_err(CE_WARN, "ahci: %s %s", err_msg_header, err_msg); 7195 } 7196 } 7197 7198 /* 7199 * This routine is to calculate the total number of ports implemented 7200 * by the HBA. 7201 */ 7202 static int 7203 ahci_get_num_implemented_ports(uint32_t ports_implemented) 7204 { 7205 uint8_t i; 7206 int num = 0; 7207 7208 for (i = 0; i < AHCI_MAX_PORTS; i++) { 7209 if (((uint32_t)0x1 << i) & ports_implemented) 7210 num++; 7211 } 7212 7213 return (num); 7214 } 7215 7216 #if AHCI_DEBUG 7217 static void 7218 ahci_log(ahci_ctl_t *ahci_ctlp, uint_t level, char *fmt, ...) 7219 { 7220 static char name[16]; 7221 va_list ap; 7222 7223 mutex_enter(&ahci_log_mutex); 7224 7225 va_start(ap, fmt); 7226 if (ahci_ctlp) { 7227 (void) sprintf(name, "ahci%d: ", 7228 ddi_get_instance(ahci_ctlp->ahcictl_dip)); 7229 } else { 7230 (void) sprintf(name, "ahci: "); 7231 } 7232 7233 (void) vsprintf(ahci_log_buf, fmt, ap); 7234 va_end(ap); 7235 7236 cmn_err(level, "%s%s", name, ahci_log_buf); 7237 7238 mutex_exit(&ahci_log_mutex); 7239 } 7240 #endif 7241 7242 /* 7243 * quiesce(9E) entry point. 7244 * 7245 * This function is called when the system is single-threaded at high 7246 * PIL with preemption disabled. Therefore, this function must not be 7247 * blocked. 7248 * 7249 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 7250 * DDI_FAILURE indicates an error condition and should almost never happen. 7251 */ 7252 static int 7253 ahci_quiesce(dev_info_t *dip) 7254 { 7255 ahci_ctl_t *ahci_ctlp; 7256 ahci_port_t *ahci_portp; 7257 int instance, port; 7258 7259 instance = ddi_get_instance(dip); 7260 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 7261 7262 if (ahci_ctlp == NULL) 7263 return (DDI_FAILURE); 7264 7265 #if AHCI_DEBUG 7266 ahci_debug_flags = 0; 7267 #endif 7268 7269 /* disable all the interrupts. */ 7270 ahci_disable_all_intrs(ahci_ctlp); 7271 7272 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 7273 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 7274 continue; 7275 } 7276 7277 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 7278 7279 /* 7280 * Stop the port by clearing PxCMD.ST 7281 * 7282 * Here we must disable the port interrupt because 7283 * ahci_disable_all_intrs only clear GHC.IE, and IS 7284 * register will be still set if PxIE is enabled. 7285 * When ahci shares one IRQ with other drivers, the 7286 * intr handler may claim the intr mistakenly. 7287 */ 7288 ahci_disable_port_intrs(ahci_ctlp, port); 7289 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 7290 ahci_portp, port); 7291 } 7292 7293 return (DDI_SUCCESS); 7294 } 7295