1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * AHCI (Advanced Host Controller Interface) SATA HBA Driver 31 * 32 * Power Management Support 33 * ------------------------ 34 * 35 * At the moment, the ahci driver only implements suspend/resume to 36 * support Suspend to RAM on X86 feature. Device power management isn't 37 * implemented, link power management is disabled, and hot plug isn't 38 * allowed during the period from suspend to resume. 39 * 40 * For s/r support, the ahci driver only need to implement DDI_SUSPEND 41 * and DDI_RESUME entries, and don't need to take care of new requests 42 * sent down after suspend because the target driver (sd) has already 43 * handled these conditions, and blocked these requests. For the detailed 44 * information, please check with sdopen, sdclose and sdioctl routines. 45 * 46 */ 47 48 #include <sys/note.h> 49 #include <sys/scsi/scsi.h> 50 #include <sys/pci.h> 51 #include <sys/sata/sata_hba.h> 52 #include <sys/sata/adapters/ahci/ahcireg.h> 53 #include <sys/sata/adapters/ahci/ahcivar.h> 54 55 /* 56 * Function prototypes for driver entry points 57 */ 58 static int ahci_attach(dev_info_t *, ddi_attach_cmd_t); 59 static int ahci_detach(dev_info_t *, ddi_detach_cmd_t); 60 static int ahci_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 61 62 /* 63 * Function prototypes for SATA Framework interfaces 64 */ 65 static int ahci_register_sata_hba_tran(ahci_ctl_t *, uint32_t); 66 static int ahci_unregister_sata_hba_tran(ahci_ctl_t *); 67 68 static int ahci_tran_probe_port(dev_info_t *, sata_device_t *); 69 static int ahci_tran_start(dev_info_t *, sata_pkt_t *spkt); 70 static int ahci_tran_abort(dev_info_t *, sata_pkt_t *, int); 71 static int ahci_tran_reset_dport(dev_info_t *, sata_device_t *); 72 static int ahci_tran_hotplug_port_activate(dev_info_t *, sata_device_t *); 73 static int ahci_tran_hotplug_port_deactivate(dev_info_t *, sata_device_t *); 74 #if defined(__lock_lint) 75 static int ahci_selftest(dev_info_t *, sata_device_t *); 76 #endif 77 78 /* 79 * Local function prototypes 80 */ 81 static int ahci_alloc_ports_state(ahci_ctl_t *); 82 static void ahci_dealloc_ports_state(ahci_ctl_t *); 83 static int ahci_alloc_port_state(ahci_ctl_t *, uint8_t); 84 static void ahci_dealloc_port_state(ahci_ctl_t *, uint8_t); 85 static int ahci_alloc_rcvd_fis(ahci_ctl_t *, ahci_port_t *, uint8_t); 86 static void ahci_dealloc_rcvd_fis(ahci_port_t *); 87 static int ahci_alloc_cmd_list(ahci_ctl_t *, ahci_port_t *, uint8_t); 88 static void ahci_dealloc_cmd_list(ahci_ctl_t *, ahci_port_t *); 89 static int ahci_alloc_cmd_tables(ahci_ctl_t *, ahci_port_t *); 90 static void ahci_dealloc_cmd_tables(ahci_ctl_t *, ahci_port_t *); 91 92 static int ahci_initialize_controller(ahci_ctl_t *); 93 static void ahci_uninitialize_controller(ahci_ctl_t *); 94 static int ahci_initialize_port(ahci_ctl_t *, ahci_port_t *, uint8_t); 95 static int ahci_config_space_init(ahci_ctl_t *); 96 97 static void ahci_disable_interface_pm(ahci_ctl_t *, uint8_t); 98 static int ahci_start_port(ahci_ctl_t *, ahci_port_t *, uint8_t); 99 static void ahci_find_dev_signature(ahci_ctl_t *, ahci_port_t *, uint8_t); 100 static void ahci_update_sata_registers(ahci_ctl_t *, uint8_t, sata_device_t *); 101 static int ahci_deliver_satapkt(ahci_ctl_t *, ahci_port_t *, 102 uint8_t, sata_pkt_t *); 103 static int ahci_do_sync_start(ahci_ctl_t *, ahci_port_t *, 104 uint8_t, sata_pkt_t *); 105 static int ahci_claim_free_slot(ahci_ctl_t *, ahci_port_t *, int); 106 static void ahci_copy_err_cnxt(sata_cmd_t *, ahci_fis_d2h_register_t *); 107 static void ahci_copy_ncq_err_page(sata_cmd_t *, 108 struct sata_ncq_error_recovery_page *); 109 static void ahci_copy_out_regs(sata_cmd_t *, ahci_fis_d2h_register_t *); 110 111 static int ahci_software_reset(ahci_ctl_t *, ahci_port_t *, uint8_t); 112 static int ahci_hba_reset(ahci_ctl_t *); 113 static int ahci_port_reset(ahci_ctl_t *, ahci_port_t *, uint8_t); 114 static void ahci_reject_all_abort_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 115 static int ahci_reset_device_reject_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 116 static int ahci_reset_port_reject_pkts(ahci_ctl_t *, ahci_port_t *, uint8_t); 117 static int ahci_reset_hba_reject_pkts(ahci_ctl_t *); 118 static int ahci_put_port_into_notrunning_state(ahci_ctl_t *, ahci_port_t *, 119 uint8_t); 120 static int ahci_restart_port_wait_till_ready(ahci_ctl_t *, ahci_port_t *, 121 uint8_t, int, int *); 122 static void ahci_mop_commands(ahci_ctl_t *, ahci_port_t *, uint32_t, 123 uint32_t, uint32_t, uint32_t, uint32_t); 124 static uint32_t ahci_get_rdlogext_data(ahci_ctl_t *, ahci_port_t *, uint8_t); 125 static void ahci_get_rqsense_data(ahci_ctl_t *, ahci_port_t *, 126 uint8_t, sata_pkt_t *); 127 static void ahci_fatal_error_recovery_handler(ahci_ctl_t *, ahci_port_t *, 128 uint8_t, uint32_t); 129 static void ahci_timeout_pkts(ahci_ctl_t *, ahci_port_t *, 130 uint8_t, uint32_t); 131 static void ahci_events_handler(void *); 132 static void ahci_watchdog_handler(ahci_ctl_t *); 133 134 static uint_t ahci_intr(caddr_t, caddr_t); 135 static void ahci_port_intr(ahci_ctl_t *, ahci_port_t *, uint8_t); 136 static int ahci_add_legacy_intrs(ahci_ctl_t *); 137 static int ahci_add_msi_intrs(ahci_ctl_t *); 138 static void ahci_rem_intrs(ahci_ctl_t *); 139 static void ahci_enable_all_intrs(ahci_ctl_t *); 140 static void ahci_disable_all_intrs(ahci_ctl_t *); 141 static void ahci_enable_port_intrs(ahci_ctl_t *, uint8_t); 142 static void ahci_disable_port_intrs(ahci_ctl_t *, uint8_t); 143 144 static int ahci_intr_cmd_cmplt(ahci_ctl_t *, ahci_port_t *, uint8_t); 145 static int ahci_intr_set_device_bits(ahci_ctl_t *, ahci_port_t *, uint8_t); 146 static int ahci_intr_port_connect_change(ahci_ctl_t *, ahci_port_t *, uint8_t); 147 static int ahci_intr_device_mechanical_presence_status(ahci_ctl_t *, 148 ahci_port_t *, uint8_t); 149 static int ahci_intr_phyrdy_change(ahci_ctl_t *, ahci_port_t *, uint8_t); 150 static int ahci_intr_non_fatal_error(ahci_ctl_t *, ahci_port_t *, 151 uint8_t, uint32_t); 152 static int ahci_intr_fatal_error(ahci_ctl_t *, ahci_port_t *, 153 uint8_t, uint32_t); 154 static int ahci_intr_cold_port_detect(ahci_ctl_t *, ahci_port_t *, uint8_t); 155 156 static int ahci_get_num_implemented_ports(uint32_t); 157 static void ahci_log_fatal_error_message(ahci_ctl_t *, uint8_t port, 158 uint32_t); 159 static void ahci_log_serror_message(ahci_ctl_t *, uint8_t, uint32_t, int); 160 #if AHCI_DEBUG 161 static void ahci_log(ahci_ctl_t *, uint_t, char *, ...); 162 #endif 163 164 165 /* 166 * DMA attributes for the data buffer 167 * 168 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 169 * does not support 64-bit addressing 170 */ 171 static ddi_dma_attr_t buffer_dma_attr = { 172 DMA_ATTR_V0, /* dma_attr_version */ 173 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 174 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 175 0x3fffffull, /* dma_attr_count_max i.e. for one cookie */ 176 0x2ull, /* dma_attr_align: word aligned */ 177 1, /* dma_attr_burstsizes */ 178 1, /* dma_attr_minxfer */ 179 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 180 0xffffffffull, /* dma_attr_seg */ 181 AHCI_PRDT_NUMBER, /* dma_attr_sgllen */ 182 512, /* dma_attr_granular */ 183 0, /* dma_attr_flags */ 184 }; 185 186 /* 187 * DMA attributes for the rcvd FIS 188 * 189 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 190 * does not support 64-bit addressing 191 */ 192 static ddi_dma_attr_t rcvd_fis_dma_attr = { 193 DMA_ATTR_V0, /* dma_attr_version */ 194 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 195 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 196 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 197 0x100ull, /* dma_attr_align: 256-byte aligned */ 198 1, /* dma_attr_burstsizes */ 199 1, /* dma_attr_minxfer */ 200 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 201 0xffffffffull, /* dma_attr_seg */ 202 1, /* dma_attr_sgllen */ 203 1, /* dma_attr_granular */ 204 0, /* dma_attr_flags */ 205 }; 206 207 /* 208 * DMA attributes for the command list 209 * 210 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 211 * does not support 64-bit addressing 212 */ 213 static ddi_dma_attr_t cmd_list_dma_attr = { 214 DMA_ATTR_V0, /* dma_attr_version */ 215 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 216 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 217 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 218 0x400ull, /* dma_attr_align: 1K-byte aligned */ 219 1, /* dma_attr_burstsizes */ 220 1, /* dma_attr_minxfer */ 221 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 222 0xffffffffull, /* dma_attr_seg */ 223 1, /* dma_attr_sgllen */ 224 1, /* dma_attr_granular */ 225 0, /* dma_attr_flags */ 226 }; 227 228 /* 229 * DMA attributes for cmd tables 230 * 231 * dma_attr_addr_hi will be changed to 0xffffffffull if the HBA 232 * does not support 64-bit addressing 233 */ 234 static ddi_dma_attr_t cmd_table_dma_attr = { 235 DMA_ATTR_V0, /* dma_attr_version */ 236 0x0ull, /* dma_attr_addr_lo: lowest bus address */ 237 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 238 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 239 0x80ull, /* dma_attr_align: 128-byte aligned */ 240 1, /* dma_attr_burstsizes */ 241 1, /* dma_attr_minxfer */ 242 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 243 0xffffffffull, /* dma_attr_seg */ 244 1, /* dma_attr_sgllen */ 245 1, /* dma_attr_granular */ 246 0, /* dma_attr_flags */ 247 }; 248 249 250 /* Device access attributes */ 251 static ddi_device_acc_attr_t accattr = { 252 DDI_DEVICE_ATTR_V0, 253 DDI_STRUCTURE_LE_ACC, 254 DDI_STRICTORDER_ACC 255 }; 256 257 258 static struct dev_ops ahcictl_dev_ops = { 259 DEVO_REV, /* devo_rev */ 260 0, /* refcnt */ 261 ahci_getinfo, /* info */ 262 nulldev, /* identify */ 263 nulldev, /* probe */ 264 ahci_attach, /* attach */ 265 ahci_detach, /* detach */ 266 nodev, /* no reset */ 267 (struct cb_ops *)0, /* driver operations */ 268 NULL, /* bus operations */ 269 NULL /* power */ 270 }; 271 272 static sata_tran_hotplug_ops_t ahci_tran_hotplug_ops = { 273 SATA_TRAN_HOTPLUG_OPS_REV_1, 274 ahci_tran_hotplug_port_activate, 275 ahci_tran_hotplug_port_deactivate 276 }; 277 278 extern struct mod_ops mod_driverops; 279 280 static struct modldrv modldrv = { 281 &mod_driverops, /* driverops */ 282 "ahci driver %I%", 283 &ahcictl_dev_ops, /* driver ops */ 284 }; 285 286 static struct modlinkage modlinkage = { 287 MODREV_1, 288 &modldrv, 289 NULL 290 }; 291 292 static int ahci_watchdog_timeout = 5; /* 5 seconds */ 293 static int ahci_watchdog_tick; 294 295 static size_t ahci_cmd_table_size; 296 297 /* The number of Physical Region Descriptor Table(PRDT) in Command Table */ 298 int ahci_dma_prdt_number = AHCI_PRDT_NUMBER; 299 300 /* 301 * AHCI MSI tunable: 302 * 303 * MSI will be enabled in phase 2. 304 */ 305 boolean_t ahci_msi_enabled = B_FALSE; 306 307 #if AHCI_DEBUG 308 uint32_t ahci_debug_flags = 0; 309 310 /* The following is needed for ahci_log() */ 311 static kmutex_t ahci_log_mutex; 312 static char ahci_log_buf[512]; 313 #endif 314 315 /* Opaque state pointer initialized by ddi_soft_state_init() */ 316 static void *ahci_statep = NULL; 317 318 /* 319 * ahci module initialization. 320 */ 321 int 322 _init(void) 323 { 324 int ret; 325 326 ret = ddi_soft_state_init(&ahci_statep, sizeof (ahci_ctl_t), 0); 327 if (ret != 0) { 328 goto err_out; 329 } 330 331 #if AHCI_DEBUG 332 mutex_init(&ahci_log_mutex, NULL, MUTEX_DRIVER, NULL); 333 #endif 334 335 if ((ret = sata_hba_init(&modlinkage)) != 0) { 336 #if AHCI_DEBUG 337 mutex_destroy(&ahci_log_mutex); 338 #endif 339 ddi_soft_state_fini(&ahci_statep); 340 goto err_out; 341 } 342 343 ret = mod_install(&modlinkage); 344 if (ret != 0) { 345 sata_hba_fini(&modlinkage); 346 #if AHCI_DEBUG 347 mutex_destroy(&ahci_log_mutex); 348 #endif 349 ddi_soft_state_fini(&ahci_statep); 350 goto err_out; 351 } 352 353 /* watchdog tick */ 354 ahci_watchdog_tick = drv_usectohz( 355 (clock_t)ahci_watchdog_timeout * 1000000); 356 return (ret); 357 358 err_out: 359 cmn_err(CE_WARN, "!ahci: Module init failed"); 360 return (ret); 361 } 362 363 /* 364 * ahci module uninitialize. 365 */ 366 int 367 _fini(void) 368 { 369 int ret; 370 371 ret = mod_remove(&modlinkage); 372 if (ret != 0) { 373 return (ret); 374 } 375 376 /* Remove the resources allocated in _init(). */ 377 sata_hba_fini(&modlinkage); 378 #if AHCI_DEBUG 379 mutex_destroy(&ahci_log_mutex); 380 #endif 381 ddi_soft_state_fini(&ahci_statep); 382 383 return (ret); 384 } 385 386 /* 387 * _info entry point 388 */ 389 int 390 _info(struct modinfo *modinfop) 391 { 392 return (mod_info(&modlinkage, modinfop)); 393 } 394 395 /* 396 * The attach entry point for dev_ops. 397 */ 398 static int 399 ahci_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 400 { 401 ahci_ctl_t *ahci_ctlp; 402 int instance = ddi_get_instance(dip); 403 int status; 404 int attach_state; 405 uint32_t cap_status, ahci_version; 406 int intr_types; 407 int i; 408 pci_regspec_t *regs; 409 int regs_length; 410 int rnumber; 411 #if AHCI_DEBUG 412 int speed; 413 #endif 414 415 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, NULL, "ahci_attach enter"); 416 417 switch (cmd) { 418 case DDI_ATTACH: 419 break; 420 421 case DDI_RESUME: 422 423 /* 424 * During DDI_RESUME, the hardware state of the device 425 * (power may have been removed from the device) must be 426 * restored, allow pending requests to continue, and 427 * service new requests. 428 */ 429 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 430 mutex_enter(&ahci_ctlp->ahcictl_mutex); 431 432 /* Restart watch thread */ 433 if (ahci_ctlp->ahcictl_timeout_id == 0) 434 ahci_ctlp->ahcictl_timeout_id = timeout( 435 (void (*)(void *))ahci_watchdog_handler, 436 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 437 438 mutex_exit(&ahci_ctlp->ahcictl_mutex); 439 440 /* 441 * Re-initialize the controller and enable the interrupts and 442 * restart all the ports. 443 * 444 * Note that so far we don't support hot-plug during 445 * suspend/resume. 446 */ 447 if (ahci_initialize_controller(ahci_ctlp) != AHCI_SUCCESS) { 448 AHCIDBG0(AHCIDBG_ERRS|AHCIDBG_PM, ahci_ctlp, 449 "Failed to initialize the controller " 450 "during DDI_RESUME"); 451 return (DDI_FAILURE); 452 } 453 454 mutex_enter(&ahci_ctlp->ahcictl_mutex); 455 ahci_ctlp->ahcictl_flags &= ~ AHCI_SUSPEND; 456 mutex_exit(&ahci_ctlp->ahcictl_mutex); 457 458 return (DDI_SUCCESS); 459 460 default: 461 return (DDI_FAILURE); 462 } 463 464 attach_state = AHCI_ATTACH_STATE_NONE; 465 466 /* Allocate soft state */ 467 status = ddi_soft_state_zalloc(ahci_statep, instance); 468 if (status != DDI_SUCCESS) { 469 cmn_err(CE_WARN, "!ahci%d: Cannot allocate soft state", 470 instance); 471 goto err_out; 472 } 473 474 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 475 ahci_ctlp->ahcictl_flags |= AHCI_ATTACH; 476 ahci_ctlp->ahcictl_dip = dip; 477 478 /* Initialize the cport/port mapping */ 479 for (i = 0; i < AHCI_MAX_PORTS; i++) { 480 ahci_ctlp->ahcictl_port_to_cport[i] = 0xff; 481 ahci_ctlp->ahcictl_cport_to_port[i] = 0xff; 482 } 483 484 attach_state |= AHCI_ATTACH_STATE_STATEP_ALLOC; 485 486 /* 487 * Now map the AHCI base address; which includes global 488 * registers and port control registers 489 * 490 * According to the spec, the AHCI Base Address is BAR5, 491 * but BAR0-BAR4 are optional, so we need to check which 492 * rnumber is used for BAR5. 493 */ 494 495 /* 496 * search through DDI "reg" property for the AHCI register set 497 */ 498 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 499 DDI_PROP_DONTPASS, "reg", (int **)®s, 500 (uint_t *)®s_length) != DDI_PROP_SUCCESS) { 501 cmn_err(CE_WARN, "!ahci%d: Cannot lookup reg property", 502 instance); 503 goto err_out; 504 } 505 506 /* AHCI Base Address is located at 0x24 offset */ 507 for (rnumber = 0; rnumber < regs_length; ++rnumber) { 508 if ((regs[rnumber].pci_phys_hi & PCI_REG_REG_M) 509 == AHCI_PCI_RNUM) 510 break; 511 } 512 513 ddi_prop_free(regs); 514 515 if (rnumber == regs_length) { 516 cmn_err(CE_WARN, "!ahci%d: Cannot find AHCI register set", 517 instance); 518 goto err_out; 519 } 520 521 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "rnumber = %d", rnumber); 522 523 status = ddi_regs_map_setup(dip, 524 rnumber, 525 (caddr_t *)&ahci_ctlp->ahcictl_ahci_addr, 526 0, 527 0, 528 &accattr, 529 &ahci_ctlp->ahcictl_ahci_acc_handle); 530 if (status != DDI_SUCCESS) { 531 cmn_err(CE_WARN, "!ahci%d: Cannot map register space", 532 instance); 533 goto err_out; 534 } 535 536 attach_state |= AHCI_ATTACH_STATE_REG_MAP; 537 538 /* Get the AHCI version information */ 539 ahci_version = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 540 (uint32_t *)AHCI_GLOBAL_VS(ahci_ctlp)); 541 542 cmn_err(CE_NOTE, "!ahci%d: hba AHCI version = %x.%x", instance, 543 (ahci_version & 0xffff0000) >> 16, 544 ((ahci_version & 0x0000ff00) >> 4 | 545 (ahci_version & 0x000000ff))); 546 547 /* We don't support controllers whose versions are lower than 1.0 */ 548 if (!(ahci_version & 0xffff0000)) { 549 cmn_err(CE_WARN, "ahci%d: Don't support AHCI HBA with lower " 550 "than version 1.0", instance); 551 goto err_out; 552 } 553 554 /* Get the HBA capabilities information */ 555 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 556 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 557 558 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba capabilites = 0x%x", 559 cap_status); 560 561 #if AHCI_DEBUG 562 /* Get the interface speed supported by the HBA */ 563 speed = (cap_status & AHCI_HBA_CAP_ISS) >> AHCI_HBA_CAP_ISS_SHIFT; 564 if (speed == 0x01) { 565 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 566 "hba interface speed support: Gen 1 (1.5Gbps)"); 567 } else if (speed == 0x10) { 568 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 569 "hba interface speed support: Gen 2 (3 Gbps)"); 570 } else if (speed == 0x11) { 571 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 572 "hba interface speed support: Gen 3 (6 Gbps)"); 573 } 574 #endif 575 576 /* Get the number of command slots supported by the HBA */ 577 ahci_ctlp->ahcictl_num_cmd_slots = 578 ((cap_status & AHCI_HBA_CAP_NCS) >> 579 AHCI_HBA_CAP_NCS_SHIFT) + 1; 580 581 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba number of cmd slots: %d", 582 ahci_ctlp->ahcictl_num_cmd_slots); 583 584 /* Get the bit map which indicates ports implemented by the HBA */ 585 ahci_ctlp->ahcictl_ports_implemented = 586 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 587 (uint32_t *)AHCI_GLOBAL_PI(ahci_ctlp)); 588 589 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba implementation of ports: 0x%x", 590 ahci_ctlp->ahcictl_ports_implemented); 591 592 /* 593 * According to the AHCI spec, CAP.NP should indicate the maximum 594 * number of ports supported by the HBA silicon, but we found 595 * this value of ICH8 chipset only indicates the number of ports 596 * implemented (exposed) by it. Therefore, the driver should calculate 597 * the potential maximum value by checking PI register, and use 598 * the maximum of this value and CAP.NP. 599 */ 600 ahci_ctlp->ahcictl_num_ports = max( 601 (cap_status & AHCI_HBA_CAP_NP) + 1, 602 ddi_fls(ahci_ctlp->ahcictl_ports_implemented)); 603 604 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "hba number of ports: %d", 605 ahci_ctlp->ahcictl_num_ports); 606 607 /* Get the number of implemented ports by the HBA */ 608 ahci_ctlp->ahcictl_num_implemented_ports = 609 ahci_get_num_implemented_ports( 610 ahci_ctlp->ahcictl_ports_implemented); 611 612 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 613 "hba number of implemented ports: %d", 614 ahci_ctlp->ahcictl_num_implemented_ports); 615 616 /* Check whether HBA supports 64bit DMA addressing */ 617 if (!(cap_status & AHCI_HBA_CAP_S64A)) { 618 ahci_ctlp->ahcictl_cap |= AHCI_CAP_32BIT_DMA; 619 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 620 "hba does not support 64-bit addressing"); 621 } 622 623 if (pci_config_setup(dip, &ahci_ctlp->ahcictl_pci_conf_handle) 624 != DDI_SUCCESS) { 625 cmn_err(CE_WARN, "!ahci%d: Cannot set up pci configure space", 626 instance); 627 goto err_out; 628 } 629 630 attach_state |= AHCI_ATTACH_STATE_PCICFG_SETUP; 631 632 /* Check the pci configuration space, and set caps */ 633 if (ahci_config_space_init(ahci_ctlp) == AHCI_FAILURE) { 634 cmn_err(CE_WARN, "!ahci%d: ahci_config_space_init failed", 635 instance); 636 goto err_out; 637 } 638 639 /* 640 * Disable the whole controller interrupts before adding 641 * interrupt handlers(s). 642 */ 643 ahci_disable_all_intrs(ahci_ctlp); 644 645 /* Get supported interrupt types */ 646 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) { 647 cmn_err(CE_WARN, "!ahci%d: ddi_intr_get_supported_types failed", 648 instance); 649 goto err_out; 650 } 651 652 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 653 "ddi_intr_get_supported_types() returned: 0x%x", 654 intr_types); 655 656 if (ahci_msi_enabled && (intr_types & DDI_INTR_TYPE_MSI)) { 657 /* 658 * Try MSI first, but fall back to FIXED if failed 659 */ 660 if (ahci_add_msi_intrs(ahci_ctlp) == DDI_SUCCESS) { 661 ahci_ctlp->ahcictl_intr_type = DDI_INTR_TYPE_MSI; 662 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 663 "Using MSI interrupt type"); 664 goto intr_done; 665 } 666 667 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 668 "MSI registration failed, " 669 "trying FIXED interrupts"); 670 } 671 672 if (intr_types & DDI_INTR_TYPE_FIXED) { 673 if (ahci_add_legacy_intrs(ahci_ctlp) == DDI_SUCCESS) { 674 ahci_ctlp->ahcictl_intr_type = DDI_INTR_TYPE_FIXED; 675 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 676 "Using FIXED interrupt type"); 677 goto intr_done; 678 } 679 680 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_INTR, ahci_ctlp, 681 "FIXED interrupt registration failed"); 682 } 683 684 cmn_err(CE_WARN, "!ahci%d: Interrupt registration failed", instance); 685 686 goto err_out; 687 688 intr_done: 689 690 attach_state |= AHCI_ATTACH_STATE_INTR_ADDED; 691 692 /* Initialize the controller mutex */ 693 mutex_init(&ahci_ctlp->ahcictl_mutex, NULL, MUTEX_DRIVER, 694 (void *)(uintptr_t)ahci_ctlp->ahcictl_intr_pri); 695 696 attach_state |= AHCI_ATTACH_STATE_MUTEX_INIT; 697 698 if (ahci_dma_prdt_number < AHCI_MIN_PRDT_NUMBER) { 699 ahci_dma_prdt_number = AHCI_MIN_PRDT_NUMBER; 700 } else if (ahci_dma_prdt_number > AHCI_MAX_PRDT_NUMBER) { 701 ahci_dma_prdt_number = AHCI_MAX_PRDT_NUMBER; 702 } 703 704 ahci_cmd_table_size = (sizeof (ahci_cmd_table_t) + 705 (ahci_dma_prdt_number - AHCI_PRDT_NUMBER) * 706 sizeof (ahci_prdt_item_t)); 707 708 AHCIDBG2(AHCIDBG_INIT, ahci_ctlp, 709 "ahci_attach: ahci_dma_prdt_number set by user is 0x%x," 710 " ahci_cmd_table_size is 0x%x", 711 ahci_dma_prdt_number, ahci_cmd_table_size); 712 713 if (ahci_dma_prdt_number != AHCI_PRDT_NUMBER) 714 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_sgllen = 715 ahci_dma_prdt_number; 716 717 ahci_ctlp->ahcictl_buffer_dma_attr = buffer_dma_attr; 718 ahci_ctlp->ahcictl_rcvd_fis_dma_attr = rcvd_fis_dma_attr; 719 ahci_ctlp->ahcictl_cmd_list_dma_attr = cmd_list_dma_attr; 720 ahci_ctlp->ahcictl_cmd_table_dma_attr = cmd_table_dma_attr; 721 722 if (ahci_ctlp->ahcictl_cap & AHCI_CAP_32BIT_DMA) { 723 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_addr_hi = 724 0xffffffffull; 725 ahci_ctlp->ahcictl_rcvd_fis_dma_attr.dma_attr_addr_hi = 726 0xffffffffull; 727 ahci_ctlp->ahcictl_cmd_list_dma_attr.dma_attr_addr_hi = 728 0xffffffffull; 729 ahci_ctlp->ahcictl_cmd_table_dma_attr.dma_attr_addr_hi = 730 0xffffffffull; 731 } 732 733 /* Allocate the ports structure */ 734 status = ahci_alloc_ports_state(ahci_ctlp); 735 if (status != AHCI_SUCCESS) { 736 cmn_err(CE_WARN, "!ahci%d: Cannot allocate ports structure", 737 instance); 738 goto err_out; 739 } 740 741 attach_state |= AHCI_ATTACH_STATE_PORT_ALLOC; 742 743 /* 744 * A taskq is created for dealing with events 745 */ 746 if ((ahci_ctlp->ahcictl_event_taskq = ddi_taskq_create(dip, 747 "ahci_event_handle_taskq", 1, TASKQ_DEFAULTPRI, 0)) == NULL) { 748 cmn_err(CE_WARN, "!ahci%d: ddi_taskq_create failed for event " 749 "handle", instance); 750 goto err_out; 751 } 752 753 attach_state |= AHCI_ATTACH_STATE_ERR_RECV_TASKQ; 754 755 /* 756 * Initialize the controller and ports. 757 */ 758 status = ahci_initialize_controller(ahci_ctlp); 759 if (status != AHCI_SUCCESS) { 760 cmn_err(CE_WARN, "!ahci%d: HBA initialization failed", 761 instance); 762 goto err_out; 763 } 764 765 attach_state |= AHCI_ATTACH_STATE_HW_INIT; 766 767 /* Start one thread to check packet timeouts */ 768 ahci_ctlp->ahcictl_timeout_id = timeout( 769 (void (*)(void *))ahci_watchdog_handler, 770 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 771 772 attach_state |= AHCI_ATTACH_STATE_TIMEOUT_ENABLED; 773 774 if (ahci_register_sata_hba_tran(ahci_ctlp, cap_status)) { 775 cmn_err(CE_WARN, "!ahci%d: sata hba tran registration failed", 776 instance); 777 goto err_out; 778 } 779 780 ahci_ctlp->ahcictl_flags &= ~AHCI_ATTACH; 781 782 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, "ahci_attach success!"); 783 784 return (DDI_SUCCESS); 785 786 err_out: 787 if (attach_state & AHCI_ATTACH_STATE_TIMEOUT_ENABLED) { 788 mutex_enter(&ahci_ctlp->ahcictl_mutex); 789 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 790 ahci_ctlp->ahcictl_timeout_id = 0; 791 mutex_exit(&ahci_ctlp->ahcictl_mutex); 792 } 793 794 if (attach_state & AHCI_ATTACH_STATE_HW_INIT) { 795 ahci_uninitialize_controller(ahci_ctlp); 796 } 797 798 if (attach_state & AHCI_ATTACH_STATE_ERR_RECV_TASKQ) { 799 ddi_taskq_destroy(ahci_ctlp->ahcictl_event_taskq); 800 } 801 802 if (attach_state & AHCI_ATTACH_STATE_PORT_ALLOC) { 803 ahci_dealloc_ports_state(ahci_ctlp); 804 } 805 806 if (attach_state & AHCI_ATTACH_STATE_MUTEX_INIT) { 807 mutex_destroy(&ahci_ctlp->ahcictl_mutex); 808 } 809 810 if (attach_state & AHCI_ATTACH_STATE_INTR_ADDED) { 811 ahci_rem_intrs(ahci_ctlp); 812 } 813 814 if (attach_state & AHCI_ATTACH_STATE_PCICFG_SETUP) { 815 pci_config_teardown(&ahci_ctlp->ahcictl_pci_conf_handle); 816 } 817 818 if (attach_state & AHCI_ATTACH_STATE_REG_MAP) { 819 ddi_regs_map_free(&ahci_ctlp->ahcictl_ahci_acc_handle); 820 } 821 822 if (attach_state & AHCI_ATTACH_STATE_STATEP_ALLOC) { 823 ddi_soft_state_free(ahci_statep, instance); 824 } 825 826 return (DDI_FAILURE); 827 } 828 829 /* 830 * The detach entry point for dev_ops. 831 */ 832 static int 833 ahci_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 834 { 835 ahci_ctl_t *ahci_ctlp; 836 int instance; 837 int ret; 838 839 instance = ddi_get_instance(dip); 840 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 841 842 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_detach enter"); 843 844 switch (cmd) { 845 case DDI_DETACH: 846 847 /* disable the interrupts for an uninterrupted detach */ 848 mutex_enter(&ahci_ctlp->ahcictl_mutex); 849 ahci_disable_all_intrs(ahci_ctlp); 850 mutex_exit(&ahci_ctlp->ahcictl_mutex); 851 852 /* unregister from the sata framework. */ 853 ret = ahci_unregister_sata_hba_tran(ahci_ctlp); 854 if (ret != AHCI_SUCCESS) { 855 mutex_enter(&ahci_ctlp->ahcictl_mutex); 856 ahci_enable_all_intrs(ahci_ctlp); 857 mutex_exit(&ahci_ctlp->ahcictl_mutex); 858 return (DDI_FAILURE); 859 } 860 861 mutex_enter(&ahci_ctlp->ahcictl_mutex); 862 863 /* stop the watchdog handler */ 864 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 865 ahci_ctlp->ahcictl_timeout_id = 0; 866 867 mutex_exit(&ahci_ctlp->ahcictl_mutex); 868 869 /* uninitialize the controller */ 870 ahci_uninitialize_controller(ahci_ctlp); 871 872 /* remove the interrupts */ 873 ahci_rem_intrs(ahci_ctlp); 874 875 /* destroy the taskq */ 876 ddi_taskq_destroy(ahci_ctlp->ahcictl_event_taskq); 877 878 /* deallocate the ports structures */ 879 ahci_dealloc_ports_state(ahci_ctlp); 880 881 /* destroy mutex */ 882 mutex_destroy(&ahci_ctlp->ahcictl_mutex); 883 884 /* teardown the pci config */ 885 pci_config_teardown(&ahci_ctlp->ahcictl_pci_conf_handle); 886 887 /* remove the reg maps. */ 888 ddi_regs_map_free(&ahci_ctlp->ahcictl_ahci_acc_handle); 889 890 /* free the soft state. */ 891 ddi_soft_state_free(ahci_statep, instance); 892 893 return (DDI_SUCCESS); 894 895 case DDI_SUSPEND: 896 897 /* 898 * The steps associated with suspension must include putting 899 * the underlying device into a quiescent state so that it 900 * will not generate interrupts or modify or access memory. 901 */ 902 mutex_enter(&ahci_ctlp->ahcictl_mutex); 903 if (ahci_ctlp->ahcictl_flags & AHCI_SUSPEND) { 904 mutex_exit(&ahci_ctlp->ahcictl_mutex); 905 return (DDI_SUCCESS); 906 } 907 908 ahci_ctlp->ahcictl_flags |= AHCI_SUSPEND; 909 910 /* stop the watchdog handler */ 911 if (ahci_ctlp->ahcictl_timeout_id) { 912 (void) untimeout(ahci_ctlp->ahcictl_timeout_id); 913 ahci_ctlp->ahcictl_timeout_id = 0; 914 } 915 916 mutex_exit(&ahci_ctlp->ahcictl_mutex); 917 918 /* 919 * drain the taskq 920 */ 921 ddi_taskq_wait(ahci_ctlp->ahcictl_event_taskq); 922 923 /* 924 * Disable the interrupts and stop all the ports. 925 */ 926 ahci_uninitialize_controller(ahci_ctlp); 927 928 return (DDI_SUCCESS); 929 930 default: 931 return (DDI_FAILURE); 932 } 933 } 934 935 /* 936 * The info entry point for dev_ops. 937 * 938 */ 939 static int 940 ahci_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd, 941 void *arg, void **result) 942 { 943 #ifndef __lock_lint 944 _NOTE(ARGUNUSED(dip)) 945 #endif /* __lock_lint */ 946 947 ahci_ctl_t *ahci_ctlp; 948 int instance; 949 dev_t dev; 950 951 dev = (dev_t)arg; 952 instance = getminor(dev); 953 954 switch (infocmd) { 955 case DDI_INFO_DEVT2DEVINFO: 956 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 957 if (ahci_ctlp != NULL) { 958 *result = ahci_ctlp->ahcictl_dip; 959 return (DDI_SUCCESS); 960 } else { 961 *result = NULL; 962 return (DDI_FAILURE); 963 } 964 case DDI_INFO_DEVT2INSTANCE: 965 *(int *)result = instance; 966 break; 967 default: 968 break; 969 } 970 971 return (DDI_SUCCESS); 972 } 973 974 /* 975 * Registers the ahci with sata framework. 976 */ 977 static int 978 ahci_register_sata_hba_tran(ahci_ctl_t *ahci_ctlp, uint32_t cap_status) 979 { 980 struct sata_hba_tran *sata_hba_tran; 981 982 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 983 "ahci_register_sata_hba_tran enter"); 984 985 mutex_enter(&ahci_ctlp->ahcictl_mutex); 986 987 /* Allocate memory for the sata_hba_tran */ 988 sata_hba_tran = kmem_zalloc(sizeof (sata_hba_tran_t), KM_SLEEP); 989 990 sata_hba_tran->sata_tran_hba_rev = SATA_TRAN_HBA_REV_2; 991 sata_hba_tran->sata_tran_hba_dip = ahci_ctlp->ahcictl_dip; 992 sata_hba_tran->sata_tran_hba_dma_attr = 993 &ahci_ctlp->ahcictl_buffer_dma_attr; 994 995 /* Report the number of implemented ports */ 996 sata_hba_tran->sata_tran_hba_num_cports = 997 ahci_ctlp->ahcictl_num_implemented_ports; 998 999 /* Support ATAPI device */ 1000 sata_hba_tran->sata_tran_hba_features_support = SATA_CTLF_ATAPI; 1001 1002 /* Get the data transfer capability for PIO command by the HBA */ 1003 if (cap_status & AHCI_HBA_CAP_PMD) { 1004 ahci_ctlp->ahcictl_cap |= AHCI_CAP_PIO_MDRQ; 1005 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "HBA supports multiple " 1006 "DRQ block data transfer for PIO command protocol"); 1007 } 1008 1009 /* 1010 * According to the AHCI spec, the ATA/ATAPI-7 queued feature set 1011 * is not supported by AHCI (including the READ QUEUED (EXT), WRITE 1012 * QUEUED (EXT), and SERVICE commands). Queued operations are 1013 * supported in AHCI using the READ FPDMA QUEUED and WRITE FPDMA 1014 * QUEUED commands when the HBA and device support native command 1015 * queuing(NCQ). 1016 * 1017 * SATA_CTLF_NCQ will be set to sata_tran_hba_features_support if the 1018 * CAP register of the HBA indicates NCQ is supported. 1019 * 1020 * SATA_CTLF_NCQ cannot be set if AHCI_CAP_NO_MCMDLIST_NONQUEUE is 1021 * set because the previous register content of PxCI can be re-written 1022 * in the register write. 1023 */ 1024 if ((cap_status & AHCI_HBA_CAP_SNCQ) && 1025 !(ahci_ctlp->ahcictl_cap & AHCI_CAP_NO_MCMDLIST_NONQUEUE)) { 1026 sata_hba_tran->sata_tran_hba_features_support |= SATA_CTLF_NCQ; 1027 ahci_ctlp->ahcictl_cap |= AHCI_CAP_NCQ; 1028 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "HBA supports Native " 1029 "Command Queuing"); 1030 } 1031 1032 /* Report the number of command slots */ 1033 sata_hba_tran->sata_tran_hba_qdepth = ahci_ctlp->ahcictl_num_cmd_slots; 1034 1035 sata_hba_tran->sata_tran_probe_port = ahci_tran_probe_port; 1036 sata_hba_tran->sata_tran_start = ahci_tran_start; 1037 sata_hba_tran->sata_tran_abort = ahci_tran_abort; 1038 sata_hba_tran->sata_tran_reset_dport = ahci_tran_reset_dport; 1039 sata_hba_tran->sata_tran_hotplug_ops = &ahci_tran_hotplug_ops; 1040 #ifdef __lock_lint 1041 sata_hba_tran->sata_tran_selftest = ahci_selftest; 1042 #endif 1043 /* 1044 * When SATA framework adds support for pwrmgt the 1045 * pwrmgt_ops needs to be updated 1046 */ 1047 sata_hba_tran->sata_tran_pwrmgt_ops = NULL; 1048 sata_hba_tran->sata_tran_ioctl = NULL; 1049 1050 ahci_ctlp->ahcictl_sata_hba_tran = sata_hba_tran; 1051 1052 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1053 1054 /* Attach it to SATA framework */ 1055 if (sata_hba_attach(ahci_ctlp->ahcictl_dip, sata_hba_tran, DDI_ATTACH) 1056 != DDI_SUCCESS) { 1057 kmem_free((void *)sata_hba_tran, sizeof (sata_hba_tran_t)); 1058 mutex_enter(&ahci_ctlp->ahcictl_mutex); 1059 ahci_ctlp->ahcictl_sata_hba_tran = NULL; 1060 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1061 return (AHCI_FAILURE); 1062 } 1063 1064 return (AHCI_SUCCESS); 1065 } 1066 1067 /* 1068 * Unregisters the ahci with sata framework. 1069 */ 1070 static int 1071 ahci_unregister_sata_hba_tran(ahci_ctl_t *ahci_ctlp) 1072 { 1073 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, 1074 "ahci_unregister_sata_hba_tran enter"); 1075 1076 /* Detach from the SATA framework. */ 1077 if (sata_hba_detach(ahci_ctlp->ahcictl_dip, DDI_DETACH) != 1078 DDI_SUCCESS) { 1079 return (AHCI_FAILURE); 1080 } 1081 1082 /* Deallocate sata_hba_tran. */ 1083 kmem_free((void *)ahci_ctlp->ahcictl_sata_hba_tran, 1084 sizeof (sata_hba_tran_t)); 1085 1086 mutex_enter(&ahci_ctlp->ahcictl_mutex); 1087 ahci_ctlp->ahcictl_sata_hba_tran = NULL; 1088 mutex_exit(&ahci_ctlp->ahcictl_mutex); 1089 1090 return (AHCI_SUCCESS); 1091 } 1092 1093 /* 1094 * ahci_tran_probe_port is called by SATA framework. It returns port state, 1095 * port status registers and an attached device type via sata_device 1096 * structure. 1097 * 1098 * We return the cached information from a previous hardware probe. The 1099 * actual hardware probing itself was done either from within 1100 * ahci_initialize_controller() during the driver attach or from a phy 1101 * ready change interrupt handler. 1102 */ 1103 static int 1104 ahci_tran_probe_port(dev_info_t *dip, sata_device_t *sd) 1105 { 1106 ahci_ctl_t *ahci_ctlp; 1107 ahci_port_t *ahci_portp; 1108 uint8_t cport = sd->satadev_addr.cport; 1109 #if AHCI_DEBUG 1110 uint8_t pmport = sd->satadev_addr.pmport; 1111 uint8_t qual = sd->satadev_addr.qual; 1112 #endif 1113 uint8_t device_type; 1114 uint32_t port_state; 1115 uint8_t port; 1116 1117 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1118 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1119 1120 AHCIDBG3(AHCIDBG_ENTRY, ahci_ctlp, 1121 "ahci_tran_probe_port enter: cport: %d, " 1122 "pmport: %d, qual: %d", cport, pmport, qual); 1123 1124 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1125 1126 mutex_enter(&ahci_portp->ahciport_mutex); 1127 1128 port_state = ahci_portp->ahciport_port_state; 1129 switch (port_state) { 1130 1131 case SATA_PSTATE_FAILED: 1132 sd->satadev_state = SATA_PSTATE_FAILED; 1133 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1134 "ahci_tran_probe_port: port %d PORT FAILED", port); 1135 goto out; 1136 1137 case SATA_PSTATE_SHUTDOWN: 1138 sd->satadev_state = SATA_PSTATE_SHUTDOWN; 1139 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1140 "ahci_tran_probe_port: port %d PORT SHUTDOWN", port); 1141 goto out; 1142 1143 case SATA_PSTATE_PWROFF: 1144 sd->satadev_state = SATA_PSTATE_PWROFF; 1145 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1146 "ahci_tran_probe_port: port %d PORT PWROFF", port); 1147 goto out; 1148 1149 case SATA_PSTATE_PWRON: 1150 sd->satadev_state = SATA_PSTATE_PWRON; 1151 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1152 "ahci_tran_probe_port: port %d PORT PWRON", port); 1153 break; 1154 1155 default: 1156 sd->satadev_state = port_state; 1157 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 1158 "ahci_tran_probe_port: port %d PORT NORMAL %x", 1159 port, port_state); 1160 break; 1161 } 1162 1163 device_type = ahci_portp->ahciport_device_type; 1164 1165 switch (device_type) { 1166 1167 case SATA_DTYPE_ATADISK: 1168 sd->satadev_type = SATA_DTYPE_ATADISK; 1169 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1170 "ahci_tran_probe_port: port %d DISK found", port); 1171 break; 1172 1173 case SATA_DTYPE_ATAPICD: 1174 sd->satadev_type = SATA_DTYPE_ATAPICD; 1175 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1176 "ahci_tran_probe_port: port %d ATAPI found", port); 1177 break; 1178 1179 case SATA_DTYPE_PMULT: 1180 sd->satadev_type = SATA_DTYPE_PMULT; 1181 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1182 "ahci_tran_probe_port: port %d Port Multiplier found", 1183 port); 1184 break; 1185 1186 case SATA_DTYPE_UNKNOWN: 1187 sd->satadev_type = SATA_DTYPE_UNKNOWN; 1188 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1189 "ahci_tran_probe_port: port %d Unknown device found", port); 1190 break; 1191 1192 default: 1193 /* we don't support any other device types */ 1194 sd->satadev_type = SATA_DTYPE_NONE; 1195 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1196 "ahci_tran_probe_port: port %d No device found", port); 1197 break; 1198 } 1199 1200 out: 1201 ahci_update_sata_registers(ahci_ctlp, port, sd); 1202 mutex_exit(&ahci_portp->ahciport_mutex); 1203 1204 return (SATA_SUCCESS); 1205 } 1206 1207 /* 1208 * There are four operation modes in sata framework: 1209 * SATA_OPMODE_INTERRUPTS 1210 * SATA_OPMODE_POLLING 1211 * SATA_OPMODE_ASYNCH 1212 * SATA_OPMODE_SYNCH 1213 * 1214 * Their combined meanings as following: 1215 * 1216 * SATA_OPMODE_SYNCH 1217 * The command has to be completed before sata_tran_start functions returns. 1218 * Either interrupts or polling could be used - it's up to the driver. 1219 * Mode used currently for internal, sata-module initiated operations. 1220 * 1221 * SATA_OPMODE_SYNCH | SATA_OPMODE_INTERRUPTS 1222 * It is the same as the one above. 1223 * 1224 * SATA_OPMODE_SYNCH | SATA_OPMODE_POLLING 1225 * The command has to be completed before sata_tran_start function returns. 1226 * No interrupt used, polling only. This should be the mode used for scsi 1227 * packets with FLAG_NOINTR. 1228 * 1229 * SATA_OPMODE_ASYNCH | SATA_OPMODE_INTERRUPTS 1230 * The command may be queued (callback function specified). Interrupts could 1231 * be used. It's normal operation mode. 1232 */ 1233 /* 1234 * Called by sata framework to transport a sata packet down stream. 1235 */ 1236 static int 1237 ahci_tran_start(dev_info_t *dip, sata_pkt_t *spkt) 1238 { 1239 ahci_ctl_t *ahci_ctlp; 1240 ahci_port_t *ahci_portp; 1241 uint8_t cport = spkt->satapkt_device.satadev_addr.cport; 1242 uint8_t port; 1243 1244 ahci_ctlp = ddi_get_soft_state(ahci_statep, ddi_get_instance(dip)); 1245 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1246 1247 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, 1248 "ahci_tran_start enter: cport %d satapkt 0x%p", 1249 cport, (void *)spkt); 1250 1251 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1252 1253 mutex_enter(&ahci_portp->ahciport_mutex); 1254 1255 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 1256 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 1257 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 1258 /* 1259 * In case the targer driver would send the packet before 1260 * sata framework can have the opportunity to process those 1261 * event reports. 1262 */ 1263 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1264 spkt->satapkt_device.satadev_state = 1265 ahci_portp->ahciport_port_state; 1266 ahci_update_sata_registers(ahci_ctlp, port, 1267 &spkt->satapkt_device); 1268 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1269 "ahci_tran_start returning PORT_ERROR while " 1270 "port in FAILED/SHUTDOWN/PWROFF state: " 1271 "port: %d", port); 1272 mutex_exit(&ahci_portp->ahciport_mutex); 1273 return (SATA_TRAN_PORT_ERROR); 1274 } 1275 1276 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 1277 /* 1278 * ahci_intr_phyrdy_change() may have rendered it to 1279 * SATA_DTYPE_NONE. 1280 */ 1281 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1282 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE; 1283 spkt->satapkt_device.satadev_state = 1284 ahci_portp->ahciport_port_state; 1285 ahci_update_sata_registers(ahci_ctlp, port, 1286 &spkt->satapkt_device); 1287 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1288 "ahci_tran_start returning PORT_ERROR while " 1289 "no device attached: port: %d", port); 1290 mutex_exit(&ahci_portp->ahciport_mutex); 1291 return (SATA_TRAN_PORT_ERROR); 1292 } 1293 1294 /* 1295 * SATA HBA driver should remember that a device was reset and it 1296 * is supposed to reject any packets which do not specify either 1297 * SATA_IGNORE_DEV_RESET_STATE or SATA_CLEAR_DEV_RESET_STATE. 1298 * 1299 * This is to prevent a race condition when a device was arbitrarily 1300 * reset by the HBA driver (and lost it's setting) and a target 1301 * driver sending some commands to a device before the sata framework 1302 * has a chance to restore the device setting (such as cache enable/ 1303 * disable or other resettable stuff). 1304 */ 1305 if (spkt->satapkt_cmd.satacmd_flags.sata_clear_dev_reset) { 1306 ahci_portp->ahciport_reset_in_progress = 0; 1307 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1308 "ahci_tran_start clearing the " 1309 "reset_in_progress for port: %d", port); 1310 } 1311 1312 if (ahci_portp->ahciport_reset_in_progress && 1313 ! spkt->satapkt_cmd.satacmd_flags.sata_ignore_dev_reset && 1314 ! ddi_in_panic()) { 1315 spkt->satapkt_reason = SATA_PKT_BUSY; 1316 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1317 "ahci_tran_start returning BUSY while " 1318 "reset in progress: port: %d", port); 1319 mutex_exit(&ahci_portp->ahciport_mutex); 1320 return (SATA_TRAN_BUSY); 1321 } 1322 1323 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 1324 spkt->satapkt_reason = SATA_PKT_BUSY; 1325 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1326 "ahci_tran_start returning BUSY while " 1327 "mopping in progress: port: %d", port); 1328 mutex_exit(&ahci_portp->ahciport_mutex); 1329 return (SATA_TRAN_BUSY); 1330 } 1331 1332 if (spkt->satapkt_op_mode & 1333 (SATA_OPMODE_SYNCH | SATA_OPMODE_POLLING)) { 1334 /* We need to do the sync start now */ 1335 if (ahci_do_sync_start(ahci_ctlp, ahci_portp, port, 1336 spkt) == AHCI_FAILURE) { 1337 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_tran_start " 1338 "return QUEUE_FULL: port %d", port); 1339 mutex_exit(&ahci_portp->ahciport_mutex); 1340 return (SATA_TRAN_QUEUE_FULL); 1341 } 1342 } else { 1343 /* Async start, using interrupt */ 1344 if (ahci_deliver_satapkt(ahci_ctlp, ahci_portp, port, spkt) 1345 == AHCI_FAILURE) { 1346 spkt->satapkt_reason = SATA_PKT_QUEUE_FULL; 1347 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_tran_start " 1348 "returning QUEUE_FULL: port %d", port); 1349 mutex_exit(&ahci_portp->ahciport_mutex); 1350 return (SATA_TRAN_QUEUE_FULL); 1351 } 1352 } 1353 1354 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_tran_start " 1355 "sata tran accepted: port %d", port); 1356 1357 mutex_exit(&ahci_portp->ahciport_mutex); 1358 return (SATA_TRAN_ACCEPTED); 1359 } 1360 1361 /* 1362 * SATA_OPMODE_SYNCH flag is set 1363 * 1364 * If SATA_OPMODE_POLLING flag is set, then we must poll the command 1365 * without interrupt, otherwise we can still use the interrupt. 1366 * 1367 * WARNING!!! ahciport_mutex should be acquired before the function 1368 * is called. 1369 */ 1370 static int 1371 ahci_do_sync_start(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 1372 uint8_t port, sata_pkt_t *spkt) 1373 { 1374 int pkt_timeout_ticks; 1375 uint32_t timeout_tags; 1376 int rval; 1377 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 1378 1379 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, "ahci_do_sync_start enter: " 1380 "port %d spkt 0x%p", port, spkt); 1381 1382 if (spkt->satapkt_op_mode & SATA_OPMODE_POLLING) { 1383 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_POLLING; 1384 if ((rval = ahci_deliver_satapkt(ahci_ctlp, ahci_portp, 1385 port, spkt)) == AHCI_FAILURE) { 1386 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_POLLING; 1387 return (rval); 1388 } 1389 1390 pkt_timeout_ticks = 1391 drv_usectohz((clock_t)spkt->satapkt_time * 1000000); 1392 1393 while (spkt->satapkt_reason == SATA_PKT_BUSY) { 1394 mutex_exit(&ahci_portp->ahciport_mutex); 1395 1396 /* Simulate the interrupt */ 1397 ahci_port_intr(ahci_ctlp, ahci_portp, port); 1398 1399 drv_usecwait(AHCI_1MS_USECS); 1400 1401 mutex_enter(&ahci_portp->ahciport_mutex); 1402 pkt_timeout_ticks -= AHCI_1MS_TICKS; 1403 if (pkt_timeout_ticks < 0) { 1404 cmn_err(CE_WARN, "!ahci%d: ahci_do_sync_start " 1405 "port %d satapkt 0x%p timed out\n", 1406 instance, port, (void *)spkt); 1407 timeout_tags = (0x1 << rval); 1408 mutex_exit(&ahci_portp->ahciport_mutex); 1409 ahci_timeout_pkts(ahci_ctlp, ahci_portp, 1410 port, timeout_tags); 1411 mutex_enter(&ahci_portp->ahciport_mutex); 1412 } 1413 } 1414 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_POLLING; 1415 return (AHCI_SUCCESS); 1416 1417 } else { 1418 if ((rval = ahci_deliver_satapkt(ahci_ctlp, ahci_portp, 1419 port, spkt)) == AHCI_FAILURE) 1420 return (rval); 1421 1422 #if AHCI_DEBUG 1423 /* 1424 * Note that the driver always uses the slot 0 to deliver 1425 * REQUEST SENSE or READ LOG EXT command 1426 */ 1427 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1428 ASSERT(rval == 0); 1429 #endif 1430 1431 while (spkt->satapkt_reason == SATA_PKT_BUSY) 1432 cv_wait(&ahci_portp->ahciport_cv, 1433 &ahci_portp->ahciport_mutex); 1434 1435 return (AHCI_SUCCESS); 1436 } 1437 } 1438 1439 #define SENDUP_PACKET(ahci_portp, satapkt, reason) \ 1440 if (satapkt) { \ 1441 satapkt->satapkt_reason = reason; \ 1442 /* \ 1443 * We set the satapkt_reason in both sync and \ 1444 * non-sync cases. \ 1445 */ \ 1446 } \ 1447 if (satapkt && \ 1448 ! (satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) && \ 1449 satapkt->satapkt_comp) { \ 1450 mutex_exit(&ahci_portp->ahciport_mutex); \ 1451 (*satapkt->satapkt_comp)(satapkt); \ 1452 mutex_enter(&ahci_portp->ahciport_mutex); \ 1453 } else { \ 1454 if (satapkt && \ 1455 (satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) && \ 1456 ! (satapkt->satapkt_op_mode & SATA_OPMODE_POLLING)) \ 1457 cv_signal(&ahci_portp->ahciport_cv); \ 1458 } 1459 1460 /* 1461 * Searches for and claims a free command slot. 1462 * 1463 * Returns: 1464 * 1465 * AHCI_FAILURE if failed 1466 * 1. if no empty slot left 1467 * 2. non-queued command requested while queued command(s) is outstanding 1468 * 3. queued command requested whild non-queued command(s) is outstanding 1469 * 4. HBA doesn't support multiple-use of command list while already a 1470 * non-queued command is oustanding 1471 * 1472 * claimed slot number if succeeded 1473 * 1474 * NOTE: it will always return slot 0 during error recovery process for 1475 * REQUEST SENSE or READ LOG EXT command to simplify the algorithm. 1476 * 1477 * WARNING!!! ahciport_mutex should be acquired before the function 1478 * is called. 1479 */ 1480 static int 1481 ahci_claim_free_slot(ahci_ctl_t *ahci_ctlp, 1482 ahci_port_t *ahci_portp, int command_type) 1483 { 1484 uint32_t free_slots; 1485 int slot; 1486 1487 AHCIDBG2(AHCIDBG_ENTRY, ahci_ctlp, "ahci_claim_free_slot enter " 1488 "ahciport_pending_tags = 0x%x " 1489 "ahciport_pending_ncq_tags = 0x%x", 1490 ahci_portp->ahciport_pending_tags, 1491 ahci_portp->ahciport_pending_ncq_tags); 1492 1493 /* 1494 * According to the AHCI spec, system software is responsible to 1495 * ensure that queued and non-queued commands are not mixed in 1496 * the command list. 1497 */ 1498 if (command_type == AHCI_NON_NCQ_CMD) { 1499 /* Non-NCQ command request */ 1500 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1501 AHCIDBG0(AHCIDBG_INFO|AHCIDBG_NCQ, ahci_ctlp, 1502 "ahci_claim_free_slot: there is still pending " 1503 "queued command(s) in the command list, " 1504 "so no available slot for the non-queued " 1505 "command"); 1506 return (AHCI_FAILURE); 1507 } 1508 if ((ahci_ctlp->ahcictl_cap & AHCI_CAP_NO_MCMDLIST_NONQUEUE) && 1509 NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1510 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 1511 "ahci_claim_free_slot: HBA cannot support multiple-" 1512 "use of the command list for non-queued commands"); 1513 return (AHCI_FAILURE); 1514 } 1515 free_slots = (~ahci_portp->ahciport_pending_tags) & 1516 AHCI_SLOT_MASK(ahci_ctlp); 1517 } else if (command_type == AHCI_NCQ_CMD) { 1518 /* NCQ command request */ 1519 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 1520 AHCIDBG0(AHCIDBG_INFO|AHCIDBG_NCQ, ahci_ctlp, 1521 "ahci_claim_free_slot: there is still pending " 1522 "non-queued command(s) in the command list, " 1523 "so no available slot for the queued command"); 1524 return (AHCI_FAILURE); 1525 } 1526 free_slots = (~ahci_portp->ahciport_pending_ncq_tags) & 1527 AHCI_NCQ_SLOT_MASK(ahci_portp); 1528 } else if (command_type == AHCI_ERR_RETRI_CMD) { 1529 /* Error retrieval command request */ 1530 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 1531 "ahci_claim_free_slot: slot 0 is allocated for REQUEST " 1532 "SENSE or READ LOG EXT command"); 1533 slot = 0; 1534 goto out; 1535 } 1536 1537 slot = ddi_ffs(free_slots) - 1; 1538 if (slot == -1) { 1539 AHCIDBG0(AHCIDBG_VERBOSE, ahci_ctlp, 1540 "ahci_claim_free_slot: no empty slots"); 1541 return (AHCI_FAILURE); 1542 } 1543 1544 /* 1545 * According to the AHCI spec, to allow a simple mechanism for the 1546 * HBA to map command list slots to queue entries, software must 1547 * match the tag number it uses to the slot it is placing the command 1548 * in. For example, if a queued command is placed in slot 5, the tag 1549 * for that command must be 5. 1550 */ 1551 if (command_type == AHCI_NCQ_CMD) { 1552 ahci_portp->ahciport_pending_ncq_tags |= (0x1 << slot); 1553 } 1554 1555 ahci_portp->ahciport_pending_tags |= (0x1 << slot); 1556 1557 out: 1558 AHCIDBG1(AHCIDBG_VERBOSE, ahci_ctlp, 1559 "ahci_claim_free_slot: found slot: 0x%x", slot); 1560 1561 return (slot); 1562 } 1563 1564 /* 1565 * Builds the Command Table for the sata packet and delivers it to controller. 1566 * 1567 * Returns: 1568 * slot number if we can obtain a slot successfully 1569 * otherwise, return AHCI_FAILURE 1570 * 1571 * WARNING!!! ahciport_mutex should be acquired before the function is called. 1572 */ 1573 static int 1574 ahci_deliver_satapkt(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 1575 uint8_t port, sata_pkt_t *spkt) 1576 { 1577 int cmd_slot; 1578 sata_cmd_t *scmd; 1579 ahci_fis_h2d_register_t *h2d_register_fisp; 1580 ahci_cmd_table_t *cmd_table; 1581 ahci_cmd_header_t *cmd_header; 1582 int ncookies; 1583 int i; 1584 int command_type = AHCI_NON_NCQ_CMD; 1585 int ncq_qdepth; 1586 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 1587 #if AHCI_DEBUG 1588 uint32_t *ptr; 1589 uint8_t *ptr2; 1590 #endif 1591 1592 spkt->satapkt_reason = SATA_PKT_BUSY; 1593 1594 scmd = &spkt->satapkt_cmd; 1595 1596 /* Check if the command is a NCQ command */ 1597 if (scmd->satacmd_cmd_reg == SATAC_READ_FPDMA_QUEUED || 1598 scmd->satacmd_cmd_reg == SATAC_WRITE_FPDMA_QUEUED) { 1599 command_type = AHCI_NCQ_CMD; 1600 1601 /* 1602 * When NCQ is support, system software must determine the 1603 * maximum tag allowed by the device and the HBA, and it 1604 * must use a value not beyond of the lower bound of the two. 1605 * 1606 * Sata module is going to calculate the qdepth and send 1607 * down to HBA driver via sata_cmd. 1608 */ 1609 ncq_qdepth = scmd->satacmd_flags.sata_max_queue_depth + 1; 1610 1611 /* 1612 * At the moment, the driver doesn't support the dynamic 1613 * setting of the maximum ncq depth, and the value can be 1614 * set either during the attach or after hot-plug insertion. 1615 */ 1616 if (ahci_portp->ahciport_max_ncq_tags == 0) { 1617 ahci_portp->ahciport_max_ncq_tags = ncq_qdepth; 1618 AHCIDBG2(AHCIDBG_NCQ, ahci_ctlp, 1619 "ahci_deliver_satapkt: port %d the max tags for " 1620 "NCQ command is %d", port, ncq_qdepth); 1621 } else { 1622 if (ncq_qdepth != ahci_portp->ahciport_max_ncq_tags) { 1623 cmn_err(CE_WARN, "!ahci%d: ahci_deliver_satapkt" 1624 " port %d the max tag for NCQ command is " 1625 "requested to change from %d to %d, at the" 1626 " moment the driver doesn't support the " 1627 "dynamic change so it's going to " 1628 "still use the previous tag value", 1629 instance, port, 1630 ahci_portp->ahciport_max_ncq_tags, 1631 ncq_qdepth); 1632 } 1633 } 1634 } 1635 1636 /* Check if the command is an error retrieval command */ 1637 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1638 command_type = AHCI_ERR_RETRI_CMD; 1639 1640 /* Check if there is an empty command slot */ 1641 cmd_slot = ahci_claim_free_slot(ahci_ctlp, ahci_portp, command_type); 1642 if (cmd_slot == AHCI_FAILURE) { 1643 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, "no free command slot"); 1644 return (AHCI_FAILURE); 1645 } 1646 1647 AHCIDBG4(AHCIDBG_ENTRY|AHCIDBG_INFO, ahci_ctlp, 1648 "ahci_deliver_satapkt enter: cmd_reg: 0x%x, cmd_slot: 0x%x, " 1649 "port: %d, satapkt: 0x%p", scmd->satacmd_cmd_reg, 1650 cmd_slot, port, (void *)spkt); 1651 1652 cmd_table = ahci_portp->ahciport_cmd_tables[cmd_slot]; 1653 bzero((void *)cmd_table, ahci_cmd_table_size); 1654 1655 /* For data transfer operations, it is the H2D Register FIS */ 1656 h2d_register_fisp = 1657 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 1658 1659 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 1660 if ((spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_PMPORT) || 1661 (spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_DPMPORT)) { 1662 SET_FIS_PMP(h2d_register_fisp, 1663 spkt->satapkt_device.satadev_addr.pmport); 1664 } 1665 1666 SET_FIS_CDMDEVCTL(h2d_register_fisp, 1); 1667 SET_FIS_COMMAND(h2d_register_fisp, scmd->satacmd_cmd_reg); 1668 SET_FIS_FEATURES(h2d_register_fisp, scmd->satacmd_features_reg); 1669 SET_FIS_SECTOR_COUNT(h2d_register_fisp, scmd->satacmd_sec_count_lsb); 1670 1671 switch (scmd->satacmd_addr_type) { 1672 1673 case 0: 1674 /* 1675 * satacmd_addr_type will be 0 for the commands below: 1676 * ATAPI command 1677 * SATAC_IDLE_IM 1678 * SATAC_STANDBY_IM 1679 * SATAC_DOWNLOAD_MICROCODE 1680 * SATAC_FLUSH_CACHE 1681 * SATAC_SET_FEATURES 1682 * SATAC_SMART 1683 * SATAC_ID_PACKET_DEVICE 1684 * SATAC_ID_DEVICE 1685 */ 1686 /* FALLTHRU */ 1687 1688 case ATA_ADDR_LBA: 1689 /* FALLTHRU */ 1690 1691 case ATA_ADDR_LBA28: 1692 /* LBA[7:0] */ 1693 SET_FIS_SECTOR(h2d_register_fisp, scmd->satacmd_lba_low_lsb); 1694 1695 /* LBA[15:8] */ 1696 SET_FIS_CYL_LOW(h2d_register_fisp, scmd->satacmd_lba_mid_lsb); 1697 1698 /* LBA[23:16] */ 1699 SET_FIS_CYL_HI(h2d_register_fisp, scmd->satacmd_lba_high_lsb); 1700 1701 /* LBA [27:24] (also called dev_head) */ 1702 SET_FIS_DEV_HEAD(h2d_register_fisp, scmd->satacmd_device_reg); 1703 1704 break; 1705 1706 case ATA_ADDR_LBA48: 1707 /* LBA[7:0] */ 1708 SET_FIS_SECTOR(h2d_register_fisp, scmd->satacmd_lba_low_lsb); 1709 1710 /* LBA[15:8] */ 1711 SET_FIS_CYL_LOW(h2d_register_fisp, scmd->satacmd_lba_mid_lsb); 1712 1713 /* LBA[23:16] */ 1714 SET_FIS_CYL_HI(h2d_register_fisp, scmd->satacmd_lba_high_lsb); 1715 1716 /* LBA [31:24] */ 1717 SET_FIS_SECTOR_EXP(h2d_register_fisp, 1718 scmd->satacmd_lba_low_msb); 1719 1720 /* LBA [39:32] */ 1721 SET_FIS_CYL_LOW_EXP(h2d_register_fisp, 1722 scmd->satacmd_lba_mid_msb); 1723 1724 /* LBA [47:40] */ 1725 SET_FIS_CYL_HI_EXP(h2d_register_fisp, 1726 scmd->satacmd_lba_high_msb); 1727 1728 /* Set dev_head */ 1729 SET_FIS_DEV_HEAD(h2d_register_fisp, 1730 scmd->satacmd_device_reg); 1731 1732 /* Set the extended sector count and features */ 1733 SET_FIS_SECTOR_COUNT_EXP(h2d_register_fisp, 1734 scmd->satacmd_sec_count_msb); 1735 SET_FIS_FEATURES_EXP(h2d_register_fisp, 1736 scmd->satacmd_features_reg_ext); 1737 break; 1738 } 1739 1740 /* 1741 * For NCQ command (READ/WRITE FPDMA QUEUED), sector count 7:0 is 1742 * filled into features field, and sector count 8:15 is filled into 1743 * features (exp) field. TAG is filled into sector field. 1744 */ 1745 if (command_type == AHCI_NCQ_CMD) { 1746 SET_FIS_FEATURES(h2d_register_fisp, 1747 scmd->satacmd_sec_count_lsb); 1748 SET_FIS_FEATURES_EXP(h2d_register_fisp, 1749 scmd->satacmd_sec_count_msb); 1750 1751 SET_FIS_SECTOR_COUNT(h2d_register_fisp, 1752 (cmd_slot << SATA_TAG_QUEUING_SHIFT)); 1753 } 1754 1755 ncookies = scmd->satacmd_num_dma_cookies; 1756 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 1757 "ncookies = 0x%x, ahci_dma_prdt_number = 0x%x", 1758 ncookies, ahci_dma_prdt_number); 1759 1760 ASSERT(ncookies <= ahci_dma_prdt_number); 1761 1762 /* *** now fill the scatter gather list ******* */ 1763 for (i = 0; i < ncookies; i++) { 1764 cmd_table->ahcict_prdt[i].ahcipi_data_base_addr = 1765 scmd->satacmd_dma_cookie_list[i]._dmu._dmac_la[0]; 1766 cmd_table->ahcict_prdt[i].ahcipi_data_base_addr_upper = 1767 scmd->satacmd_dma_cookie_list[i]._dmu._dmac_la[1]; 1768 cmd_table->ahcict_prdt[i].ahcipi_descr_info = 1769 scmd->satacmd_dma_cookie_list[i].dmac_size - 1; 1770 } 1771 1772 /* The ACMD field is filled in for ATAPI command */ 1773 if (scmd->satacmd_cmd_reg == SATAC_PACKET) { 1774 bcopy(scmd->satacmd_acdb, cmd_table->ahcict_atapi_cmd, 1775 SATA_ATAPI_MAX_CDB_LEN); 1776 } 1777 1778 /* Set Command Header in Command List */ 1779 cmd_header = &ahci_portp->ahciport_cmd_list[cmd_slot]; 1780 BZERO_DESCR_INFO(cmd_header); 1781 BZERO_PRD_BYTE_COUNT(cmd_header); 1782 1783 /* Set the number of entries in the PRD table */ 1784 SET_PRD_TABLE_LENGTH(cmd_header, ncookies); 1785 1786 /* Set the length of the command in the CFIS area */ 1787 SET_COMMAND_FIS_LENGTH(cmd_header, AHCI_H2D_REGISTER_FIS_LENGTH); 1788 1789 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "command data direction is " 1790 "sata_data_direction = 0x%x", 1791 scmd->satacmd_flags.sata_data_direction); 1792 1793 /* Set A bit if it is an ATAPI command */ 1794 if (scmd->satacmd_cmd_reg == SATAC_PACKET) 1795 SET_ATAPI(cmd_header, AHCI_CMDHEAD_ATAPI); 1796 1797 /* Set W bit if data is going to the device */ 1798 if (scmd->satacmd_flags.sata_data_direction == SATA_DIR_WRITE) 1799 SET_WRITE(cmd_header, AHCI_CMDHEAD_DATA_WRITE); 1800 1801 /* 1802 * Set the prefetchable bit - this bit is only valid if the PRDTL 1803 * field is non-zero or the ATAPI 'A' bit is set in the command 1804 * header. This bit cannot be set when using native command 1805 * queuing commands or when using FIS-based switching with a Port 1806 * multiplier. 1807 */ 1808 if (command_type != AHCI_NCQ_CMD) 1809 SET_PREFETCHABLE(cmd_header, AHCI_CMDHEAD_PREFETCHABLE); 1810 1811 /* Now remember the sata packet in ahciport_slot_pkts[]. */ 1812 if (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 1813 ahci_portp->ahciport_slot_pkts[cmd_slot] = spkt; 1814 1815 /* 1816 * We are overloading satapkt_hba_driver_private with 1817 * watched_cycle count. 1818 */ 1819 spkt->satapkt_hba_driver_private = (void *)(intptr_t)0; 1820 1821 #if AHCI_DEBUG 1822 /* Dump the command header and table */ 1823 AHCIDBG0(AHCIDBG_COMMAND, ahci_ctlp, "\n"); 1824 AHCIDBG3(AHCIDBG_COMMAND, ahci_ctlp, 1825 "Command header&table for spkt 0x%p cmd_reg 0x%x port %d", 1826 spkt, scmd->satacmd_cmd_reg, port); 1827 ptr = (uint32_t *)cmd_header; 1828 AHCIDBG4(AHCIDBG_COMMAND, ahci_ctlp, 1829 " Command Header:%8x %8x %8x %8x", 1830 ptr[0], ptr[1], ptr[2], ptr[3]); 1831 1832 /* Dump the H2D register FIS */ 1833 ptr = (uint32_t *)h2d_register_fisp; 1834 AHCIDBG4(AHCIDBG_COMMAND, ahci_ctlp, 1835 " Command FIS: %8x %8x %8x %8x", 1836 ptr[0], ptr[1], ptr[2], ptr[3]); 1837 1838 /* Dump the ACMD register FIS */ 1839 ptr2 = (uint8_t *)&(cmd_table->ahcict_atapi_cmd); 1840 for (i = 0; i < SATA_ATAPI_MAX_CDB_LEN/8; i++) 1841 if (ahci_debug_flags & AHCIDBG_COMMAND) 1842 ahci_log(ahci_ctlp, CE_WARN, 1843 " ATAPI command: %2x %2x %2x %2x " 1844 "%2x %2x %2x %2x", 1845 ptr2[8 * i], ptr2[8 * i + 1], 1846 ptr2[8 * i + 2], ptr2[8 * i + 3], 1847 ptr2[8 * i + 4], ptr2[8 * i + 5], 1848 ptr2[8 * i + 6], ptr2[8 * i + 7]); 1849 1850 /* Dump the PRDT */ 1851 for (i = 0; i < ncookies; i++) { 1852 ptr = (uint32_t *)&(cmd_table->ahcict_prdt[i]); 1853 AHCIDBG5(AHCIDBG_COMMAND, ahci_ctlp, 1854 " Cookie %d: %8x %8x %8x %8x", 1855 i, ptr[0], ptr[1], ptr[2], ptr[3]); 1856 } 1857 #endif 1858 1859 (void) ddi_dma_sync( 1860 ahci_portp->ahciport_cmd_tables_dma_handle[cmd_slot], 1861 0, 1862 ahci_cmd_table_size, 1863 DDI_DMA_SYNC_FORDEV); 1864 1865 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 1866 cmd_slot * sizeof (ahci_cmd_header_t), 1867 sizeof (ahci_cmd_header_t), 1868 DDI_DMA_SYNC_FORDEV); 1869 1870 /* Set the corresponding bit in the PxSACT.DS for queued command */ 1871 if (command_type == AHCI_NCQ_CMD) { 1872 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 1873 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port), 1874 (0x1 << cmd_slot)); 1875 } 1876 1877 /* Indicate to the HBA that a command is active. */ 1878 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 1879 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 1880 (0x1 << cmd_slot)); 1881 1882 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_deliver_satapkt " 1883 "exit: port %d", port); 1884 1885 return (cmd_slot); 1886 } 1887 1888 /* 1889 * Called by the sata framework to abort the previously sent packet(s). 1890 * 1891 * Reset device to abort commands. 1892 */ 1893 static int 1894 ahci_tran_abort(dev_info_t *dip, sata_pkt_t *spkt, int flag) 1895 { 1896 ahci_ctl_t *ahci_ctlp; 1897 ahci_port_t *ahci_portp; 1898 uint32_t slot_status = 0; 1899 uint32_t aborted_tags = 0; 1900 uint32_t finished_tags = 0; 1901 uint8_t cport = spkt->satapkt_device.satadev_addr.cport; 1902 uint8_t port; 1903 int tmp_slot; 1904 int instance = ddi_get_instance(dip); 1905 1906 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 1907 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 1908 1909 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 1910 "ahci_tran_abort enter: port %d", port); 1911 1912 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 1913 mutex_enter(&ahci_portp->ahciport_mutex); 1914 1915 /* 1916 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 1917 * commands are being mopped, therefore there is nothing else to do 1918 */ 1919 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 1920 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1921 "ahci_tran_abort: port %d is in " 1922 "mopping process, so just return directly ", port); 1923 mutex_exit(&ahci_portp->ahciport_mutex); 1924 return (SATA_SUCCESS); 1925 } 1926 1927 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 1928 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 1929 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 1930 /* 1931 * In case the targer driver would send the request before 1932 * sata framework can have the opportunity to process those 1933 * event reports. 1934 */ 1935 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1936 spkt->satapkt_device.satadev_state = 1937 ahci_portp->ahciport_port_state; 1938 ahci_update_sata_registers(ahci_ctlp, port, 1939 &spkt->satapkt_device); 1940 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1941 "ahci_tran_abort returning SATA_FAILURE while " 1942 "port in FAILED/SHUTDOWN/PWROFF state: " 1943 "port: %d", port); 1944 mutex_exit(&ahci_portp->ahciport_mutex); 1945 return (SATA_FAILURE); 1946 } 1947 1948 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 1949 /* 1950 * ahci_intr_phyrdy_change() may have rendered it to 1951 * AHCI_PORT_TYPE_NODEV. 1952 */ 1953 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1954 spkt->satapkt_device.satadev_type = SATA_DTYPE_NONE; 1955 spkt->satapkt_device.satadev_state = 1956 ahci_portp->ahciport_port_state; 1957 ahci_update_sata_registers(ahci_ctlp, port, 1958 &spkt->satapkt_device); 1959 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 1960 "ahci_tran_abort returning SATA_FAILURE while " 1961 "no device attached: port: %d", port); 1962 mutex_exit(&ahci_portp->ahciport_mutex); 1963 return (SATA_FAILURE); 1964 } 1965 1966 if (flag == SATA_ABORT_ALL_PACKETS) { 1967 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 1968 aborted_tags = ahci_portp->ahciport_pending_tags; 1969 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 1970 aborted_tags = ahci_portp->ahciport_pending_ncq_tags; 1971 1972 cmn_err(CE_NOTE, "!ahci%d: ahci port %d abort all packets", 1973 instance, port); 1974 } else { 1975 aborted_tags = 0xffffffff; 1976 /* 1977 * Aborting one specific packet, first search the 1978 * ahciport_slot_pkts[] list for matching spkt. 1979 */ 1980 for (tmp_slot = 0; 1981 tmp_slot < ahci_ctlp->ahcictl_num_cmd_slots; tmp_slot++) { 1982 if (ahci_portp->ahciport_slot_pkts[tmp_slot] == spkt) { 1983 aborted_tags = (0x1 << tmp_slot); 1984 break; 1985 } 1986 } 1987 1988 if (aborted_tags == 0xffffffff) { 1989 /* request packet is not on the pending list */ 1990 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 1991 "Cannot find the aborting pkt 0x%p on the " 1992 "pending list", (void *)spkt); 1993 ahci_update_sata_registers(ahci_ctlp, port, 1994 &spkt->satapkt_device); 1995 mutex_exit(&ahci_portp->ahciport_mutex); 1996 return (SATA_FAILURE); 1997 } 1998 cmn_err(CE_NOTE, "!ahci%d: ahci port %d abort satapkt 0x%p", 1999 instance, port, (void *)spkt); 2000 } 2001 2002 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2003 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2004 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2005 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2006 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2007 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2008 2009 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2010 ahci_portp->ahciport_mop_in_progress++; 2011 2012 /* 2013 * To abort the packet(s), first we are trying to clear PxCMD.ST 2014 * to stop the port, and if the port can be stopped 2015 * successfully with PxTFD.STS.BSY and PxTFD.STS.DRQ cleared to '0', 2016 * then we just send back the aborted packet(s) with ABORTED flag 2017 * and then restart the port by setting PxCMD.ST and PxCMD.FRE. 2018 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then we 2019 * perform a COMRESET. 2020 */ 2021 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, 2022 ahci_portp, port, NULL, NULL); 2023 2024 /* 2025 * Compute which have finished and which need to be retried. 2026 * 2027 * The finished tags are ahciport_pending_tags/ahciport_pending_ncq_tags 2028 * minus the slot_status. The aborted_tags has to be deducted by 2029 * finished_tags since we can't possibly abort a tag which had finished 2030 * already. 2031 */ 2032 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2033 finished_tags = ahci_portp->ahciport_pending_tags & 2034 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2035 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2036 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2037 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2038 2039 aborted_tags &= ~finished_tags; 2040 2041 ahci_mop_commands(ahci_ctlp, 2042 ahci_portp, 2043 slot_status, 2044 0, /* failed tags */ 2045 0, /* timeout tags */ 2046 aborted_tags, 2047 0); /* reset tags */ 2048 2049 ahci_update_sata_registers(ahci_ctlp, port, &spkt->satapkt_device); 2050 mutex_exit(&ahci_portp->ahciport_mutex); 2051 2052 return (SATA_SUCCESS); 2053 } 2054 2055 /* 2056 * Used to do device reset and reject all the pending packets on a device 2057 * during the reset operation. 2058 * 2059 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2060 */ 2061 static int 2062 ahci_reset_device_reject_pkts(ahci_ctl_t *ahci_ctlp, 2063 ahci_port_t *ahci_portp, uint8_t port) 2064 { 2065 uint32_t slot_status = 0; 2066 uint32_t reset_tags = 0; 2067 uint32_t finished_tags = 0; 2068 sata_device_t sdevice; 2069 int ret; 2070 2071 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2072 "ahci_reset_device_reject_pkts on port: %d", port); 2073 2074 /* 2075 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 2076 * commands are being mopped, therefore there is nothing else to do 2077 */ 2078 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2079 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2080 "ahci_reset_device_reject_pkts: port %d is in " 2081 "mopping process, so return directly ", port); 2082 return (SATA_SUCCESS); 2083 } 2084 2085 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2086 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2087 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2088 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2089 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2090 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2091 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2092 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2093 } 2094 2095 if (ahci_software_reset(ahci_ctlp, ahci_portp, port) 2096 != AHCI_SUCCESS) { 2097 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2098 "Try to do a port reset after software " 2099 "reset failed", port); 2100 ret = ahci_port_reset(ahci_ctlp, ahci_portp, port); 2101 if (ret != AHCI_SUCCESS) { 2102 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2103 "ahci_reset_device_reject_pkts: port %d " 2104 "failed", port); 2105 return (SATA_FAILURE); 2106 } 2107 } 2108 /* Set the reset in progress flag */ 2109 ahci_portp->ahciport_reset_in_progress = 1; 2110 2111 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2112 ahci_portp->ahciport_mop_in_progress++; 2113 2114 /* Indicate to the framework that a reset has happened */ 2115 bzero((void *)&sdevice, sizeof (sata_device_t)); 2116 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 2117 sdevice.satadev_addr.pmport = 0; 2118 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 2119 2120 sdevice.satadev_state = SATA_DSTATE_RESET | 2121 SATA_DSTATE_PWR_ACTIVE; 2122 mutex_exit(&ahci_portp->ahciport_mutex); 2123 sata_hba_event_notify( 2124 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 2125 &sdevice, 2126 SATA_EVNT_DEVICE_RESET); 2127 mutex_enter(&ahci_portp->ahciport_mutex); 2128 2129 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 2130 "port %d sending event up: SATA_EVNT_RESET", port); 2131 2132 /* Next try to mop the pending commands */ 2133 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2134 finished_tags = ahci_portp->ahciport_pending_tags & 2135 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2136 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2137 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2138 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2139 2140 reset_tags &= ~finished_tags; 2141 2142 ahci_mop_commands(ahci_ctlp, 2143 ahci_portp, 2144 slot_status, 2145 0, /* failed tags */ 2146 0, /* timeout tags */ 2147 0, /* aborted tags */ 2148 reset_tags); /* reset tags */ 2149 2150 return (SATA_SUCCESS); 2151 } 2152 2153 /* 2154 * Used to do port reset and reject all the pending packets on a port during 2155 * the reset operation. 2156 * 2157 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2158 */ 2159 static int 2160 ahci_reset_port_reject_pkts(ahci_ctl_t *ahci_ctlp, 2161 ahci_port_t *ahci_portp, uint8_t port) 2162 { 2163 uint32_t slot_status = 0; 2164 uint32_t reset_tags = 0; 2165 uint32_t finished_tags = 0; 2166 2167 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2168 "ahci_reset_port_reject_pkts on port: %d", port); 2169 2170 /* 2171 * If AHCI_PORT_FLAG_MOPPING flag is set, it means all the pending 2172 * commands are being mopped, therefore there is nothing else to do 2173 */ 2174 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2175 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2176 "ahci_reset_port_reject_pkts: port %d is in " 2177 "mopping process, so return directly ", port); 2178 return (SATA_SUCCESS); 2179 } 2180 2181 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2182 ahci_portp->ahciport_mop_in_progress++; 2183 2184 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2185 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2186 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2187 reset_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2188 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2189 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2190 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2191 reset_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2192 } 2193 2194 if (ahci_restart_port_wait_till_ready(ahci_ctlp, 2195 ahci_portp, port, AHCI_PORT_RESET|AHCI_RESET_NO_EVENTS_UP, 2196 NULL) != AHCI_SUCCESS) 2197 return (SATA_FAILURE); 2198 2199 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2200 finished_tags = ahci_portp->ahciport_pending_tags & 2201 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2202 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2203 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 2204 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2205 2206 reset_tags &= ~finished_tags; 2207 2208 ahci_mop_commands(ahci_ctlp, 2209 ahci_portp, 2210 slot_status, 2211 0, /* failed tags */ 2212 0, /* timeout tags */ 2213 0, /* aborted tags */ 2214 reset_tags); /* reset tags */ 2215 2216 return (SATA_SUCCESS); 2217 } 2218 2219 /* 2220 * Used to do hba reset and reject all the pending packets on all ports 2221 * during the reset operation. 2222 */ 2223 static int 2224 ahci_reset_hba_reject_pkts(ahci_ctl_t *ahci_ctlp) 2225 { 2226 ahci_port_t *ahci_portp; 2227 uint32_t slot_status[AHCI_MAX_PORTS]; 2228 uint32_t reset_tags[AHCI_MAX_PORTS]; 2229 uint32_t finished_tags[AHCI_MAX_PORTS]; 2230 uint8_t port; 2231 int ret = SATA_SUCCESS; 2232 2233 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, 2234 "ahci_reset_hba_reject_pkts enter"); 2235 2236 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2237 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2238 continue; 2239 } 2240 2241 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2242 2243 mutex_enter(&ahci_portp->ahciport_mutex); 2244 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2245 slot_status[port] = ddi_get32( 2246 ahci_ctlp->ahcictl_ahci_acc_handle, 2247 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2248 reset_tags[port] = slot_status[port] & 2249 AHCI_SLOT_MASK(ahci_ctlp); 2250 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2251 slot_status[port] = ddi_get32( 2252 ahci_ctlp->ahcictl_ahci_acc_handle, 2253 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2254 reset_tags[port] = slot_status[port] & 2255 AHCI_NCQ_SLOT_MASK(ahci_portp); 2256 } 2257 mutex_exit(&ahci_portp->ahciport_mutex); 2258 } 2259 2260 if (ahci_hba_reset(ahci_ctlp) != AHCI_SUCCESS) { 2261 ret = SATA_FAILURE; 2262 goto out; 2263 } 2264 2265 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2266 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2267 continue; 2268 } 2269 2270 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2271 2272 mutex_enter(&ahci_portp->ahciport_mutex); 2273 /* 2274 * To prevent recursive enter to ahci_mop_commands, we need 2275 * check AHCI_PORT_FLAG_MOPPING flag. 2276 */ 2277 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2278 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2279 "ahci_reset_hba_reject_pkts: port %d is in " 2280 "mopping process, so return directly ", port); 2281 mutex_exit(&ahci_portp->ahciport_mutex); 2282 continue; 2283 } 2284 2285 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2286 ahci_portp->ahciport_mop_in_progress++; 2287 2288 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) 2289 finished_tags[port] = 2290 ahci_portp->ahciport_pending_tags & 2291 ~slot_status[port] & AHCI_SLOT_MASK(ahci_ctlp); 2292 else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) 2293 finished_tags[port] = 2294 ahci_portp->ahciport_pending_ncq_tags & 2295 ~slot_status[port] & AHCI_NCQ_SLOT_MASK(ahci_portp); 2296 2297 reset_tags[port] &= ~finished_tags[port]; 2298 2299 ahci_mop_commands(ahci_ctlp, 2300 ahci_portp, 2301 slot_status[port], 2302 0, /* failed tags */ 2303 0, /* timeout tags */ 2304 0, /* aborted tags */ 2305 reset_tags[port]); /* reset tags */ 2306 mutex_exit(&ahci_portp->ahciport_mutex); 2307 } 2308 out: 2309 return (ret); 2310 } 2311 2312 /* 2313 * Called by sata framework to reset a port(s) or device. 2314 */ 2315 static int 2316 ahci_tran_reset_dport(dev_info_t *dip, sata_device_t *sd) 2317 { 2318 ahci_ctl_t *ahci_ctlp; 2319 ahci_port_t *ahci_portp; 2320 uint8_t cport = sd->satadev_addr.cport; 2321 uint8_t port; 2322 int ret = SATA_SUCCESS; 2323 int instance = ddi_get_instance(dip); 2324 2325 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 2326 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2327 2328 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2329 "ahci_tran_reset_port enter: cport: %d", cport); 2330 2331 switch (sd->satadev_addr.qual) { 2332 case SATA_ADDR_CPORT: 2333 /* Port reset */ 2334 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2335 cmn_err(CE_NOTE, "!ahci%d: ahci_tran_reset_dport port %d " 2336 "reset port", instance, port); 2337 2338 mutex_enter(&ahci_portp->ahciport_mutex); 2339 ret = ahci_reset_port_reject_pkts(ahci_ctlp, ahci_portp, port); 2340 mutex_exit(&ahci_portp->ahciport_mutex); 2341 2342 break; 2343 2344 case SATA_ADDR_DCPORT: 2345 /* Device reset */ 2346 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2347 cmn_err(CE_NOTE, "!ahci%d: ahci_tran_reset_dport port %d " 2348 "reset device", instance, port); 2349 2350 mutex_enter(&ahci_portp->ahciport_mutex); 2351 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED | 2352 ahci_portp->ahciport_port_state & SATA_PSTATE_SHUTDOWN | 2353 ahci_portp->ahciport_port_state & SATA_PSTATE_PWROFF) { 2354 /* 2355 * In case the targer driver would send the request 2356 * before sata framework can have the opportunity to 2357 * process those event reports. 2358 */ 2359 sd->satadev_state = ahci_portp->ahciport_port_state; 2360 ahci_update_sata_registers(ahci_ctlp, port, sd); 2361 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2362 "ahci_tran_reset_dport returning SATA_FAILURE " 2363 "while port in FAILED/SHUTDOWN/PWROFF state: " 2364 "port: %d", port); 2365 mutex_exit(&ahci_portp->ahciport_mutex); 2366 ret = SATA_FAILURE; 2367 break; 2368 } 2369 2370 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2371 /* 2372 * ahci_intr_phyrdy_change() may have rendered it to 2373 * AHCI_PORT_TYPE_NODEV. 2374 */ 2375 sd->satadev_type = SATA_DTYPE_NONE; 2376 sd->satadev_state = ahci_portp->ahciport_port_state; 2377 ahci_update_sata_registers(ahci_ctlp, port, sd); 2378 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2379 "ahci_tran_reset_dport returning SATA_FAILURE " 2380 "while no device attached: port: %d", port); 2381 mutex_exit(&ahci_portp->ahciport_mutex); 2382 ret = SATA_FAILURE; 2383 break; 2384 } 2385 2386 ret = ahci_reset_device_reject_pkts(ahci_ctlp, 2387 ahci_portp, port); 2388 mutex_exit(&ahci_portp->ahciport_mutex); 2389 break; 2390 2391 case SATA_ADDR_CNTRL: 2392 /* Reset the whole controller */ 2393 cmn_err(CE_NOTE, "!ahci%d: ahci_tran_reset_dport port %d " 2394 "reset the whole hba", instance, port); 2395 ret = ahci_reset_hba_reject_pkts(ahci_ctlp); 2396 break; 2397 2398 case SATA_ADDR_PMPORT: 2399 case SATA_ADDR_DPMPORT: 2400 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 2401 "ahci_tran_reset_dport: port multiplier will be " 2402 "supported later"); 2403 /* FALLTHRU */ 2404 default: 2405 ret = SATA_FAILURE; 2406 } 2407 2408 return (ret); 2409 } 2410 2411 /* 2412 * Called by sata framework to activate a port as part of hotplug. 2413 * (cfgadm -c connect satax/y) 2414 * Note: Not port-mult aware. 2415 */ 2416 static int 2417 ahci_tran_hotplug_port_activate(dev_info_t *dip, sata_device_t *satadev) 2418 { 2419 ahci_ctl_t *ahci_ctlp; 2420 ahci_port_t *ahci_portp; 2421 uint8_t cport = satadev->satadev_addr.cport; 2422 uint8_t port; 2423 int instance = ddi_get_instance(dip); 2424 2425 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 2426 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2427 2428 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2429 "ahci_tran_hotplug_port_activate cport %d enter", cport); 2430 2431 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2432 2433 mutex_enter(&ahci_portp->ahciport_mutex); 2434 ahci_enable_port_intrs(ahci_ctlp, port); 2435 cmn_err(CE_NOTE, "!ahci%d: ahci port %d is activated", instance, port); 2436 2437 /* 2438 * Reset the port so that the PHY communication would be re-established. 2439 * But this reset is an internal operation and the sata module doesn't 2440 * need to know about it. Moreover, the port with a device attached will 2441 * be started too. 2442 */ 2443 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, 2444 ahci_portp, port, 2445 AHCI_PORT_RESET|AHCI_RESET_NO_EVENTS_UP, 2446 NULL); 2447 2448 /* 2449 * Need to check the link status and device status of the port 2450 * and consider raising power if the port was in D3 state 2451 */ 2452 ahci_portp->ahciport_port_state |= SATA_PSTATE_PWRON; 2453 ahci_portp->ahciport_port_state &= ~SATA_PSTATE_PWROFF; 2454 ahci_portp->ahciport_port_state &= ~SATA_PSTATE_SHUTDOWN; 2455 2456 satadev->satadev_state = ahci_portp->ahciport_port_state; 2457 2458 ahci_update_sata_registers(ahci_ctlp, port, satadev); 2459 2460 mutex_exit(&ahci_portp->ahciport_mutex); 2461 return (SATA_SUCCESS); 2462 } 2463 2464 /* 2465 * Called by sata framework to deactivate a port as part of hotplug. 2466 * (cfgadm -c disconnect satax/y) 2467 * Note: Not port-mult aware. 2468 */ 2469 static int 2470 ahci_tran_hotplug_port_deactivate(dev_info_t *dip, sata_device_t *satadev) 2471 { 2472 ahci_ctl_t *ahci_ctlp; 2473 ahci_port_t *ahci_portp; 2474 uint8_t cport = satadev->satadev_addr.cport; 2475 uint8_t port; 2476 uint32_t port_scontrol; 2477 int instance = ddi_get_instance(dip); 2478 2479 ahci_ctlp = ddi_get_soft_state(ahci_statep, instance); 2480 port = ahci_ctlp->ahcictl_cport_to_port[cport]; 2481 2482 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 2483 "ahci_tran_hotplug_port_deactivate cport %d enter", cport); 2484 2485 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2486 2487 mutex_enter(&ahci_portp->ahciport_mutex); 2488 cmn_err(CE_NOTE, "!ahci%d: ahci port %d is deactivated", 2489 instance, port); 2490 2491 /* Disable the interrupts on the port */ 2492 ahci_disable_port_intrs(ahci_ctlp, port); 2493 2494 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2495 goto phy_offline; 2496 } 2497 2498 /* First to abort all the pending commands */ 2499 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port); 2500 2501 /* Then stop the port */ 2502 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 2503 ahci_portp, port); 2504 2505 /* Next put the PHY offline */ 2506 2507 phy_offline: 2508 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2509 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 2510 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_DISABLE); 2511 2512 /* Update ahciport_port_state */ 2513 ahci_portp->ahciport_port_state = SATA_PSTATE_SHUTDOWN; 2514 satadev->satadev_state = ahci_portp->ahciport_port_state; 2515 2516 ahci_update_sata_registers(ahci_ctlp, port, satadev); 2517 2518 mutex_exit(&ahci_portp->ahciport_mutex); 2519 return (SATA_SUCCESS); 2520 } 2521 2522 /* 2523 * To be used to mark all the outstanding pkts with SATA_PKT_ABORTED 2524 * when a device is unplugged or a port is deactivated. 2525 * 2526 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2527 */ 2528 static void 2529 ahci_reject_all_abort_pkts(ahci_ctl_t *ahci_ctlp, 2530 ahci_port_t *ahci_portp, uint8_t port) 2531 { 2532 uint32_t slot_status = 0; 2533 uint32_t abort_tags = 0; 2534 2535 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 2536 "ahci_reject_all_abort_pkts on port: %d", port); 2537 2538 /* 2539 * When AHCI_PORT_FLAG_MOPPING is set, we need to check whether a 2540 * REQUEST SENSE command or READ LOG EXT command is delivered to HBA 2541 * to get the error data, if yes when the device is removed, the 2542 * command needs to be aborted too. 2543 */ 2544 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) { 2545 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 2546 slot_status = 0x1; 2547 abort_tags = 0x1; 2548 goto out; 2549 } else { 2550 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2551 "ahci_reject_all_abort_pkts return directly " 2552 "port %d no needs to reject any outstanding " 2553 "commands", port); 2554 return; 2555 } 2556 } 2557 2558 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2559 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2560 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 2561 abort_tags = slot_status & AHCI_SLOT_MASK(ahci_ctlp); 2562 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 2563 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2564 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 2565 abort_tags = slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 2566 } 2567 2568 out: 2569 /* No need to do mop when there is no outstanding commands */ 2570 if (slot_status != 0) { 2571 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 2572 ahci_portp->ahciport_mop_in_progress++; 2573 2574 ahci_mop_commands(ahci_ctlp, 2575 ahci_portp, 2576 slot_status, 2577 0, /* failed tags */ 2578 0, /* timeout tags */ 2579 abort_tags, /* aborting tags */ 2580 0); /* reset tags */ 2581 } 2582 } 2583 2584 #if defined(__lock_lint) 2585 static int 2586 ahci_selftest(dev_info_t *dip, sata_device_t *device) 2587 { 2588 return (SATA_SUCCESS); 2589 } 2590 #endif 2591 2592 /* 2593 * Allocate the ports structure, only called by ahci_attach 2594 */ 2595 static int 2596 ahci_alloc_ports_state(ahci_ctl_t *ahci_ctlp) 2597 { 2598 int port, cport; 2599 2600 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2601 "ahci_alloc_ports_state enter"); 2602 2603 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2604 2605 /* Allocate structures only for the implemented ports */ 2606 for (port = 0, cport = 0; port < ahci_ctlp->ahcictl_num_ports; 2607 port++, cport++) { 2608 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2609 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2610 "hba port %d not implemented", port); 2611 continue; 2612 } 2613 2614 ahci_ctlp->ahcictl_cport_to_port[cport] = (uint8_t)port; 2615 ahci_ctlp->ahcictl_port_to_cport[port] = (uint8_t)cport; 2616 2617 if (ahci_alloc_port_state(ahci_ctlp, port) != AHCI_SUCCESS) { 2618 goto err_out; 2619 } 2620 } 2621 2622 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2623 return (AHCI_SUCCESS); 2624 2625 err_out: 2626 for (port--; port >= 0; port--) { 2627 if (AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2628 ahci_dealloc_port_state(ahci_ctlp, port); 2629 } 2630 } 2631 2632 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2633 return (AHCI_FAILURE); 2634 } 2635 2636 /* 2637 * Reverse of ahci_alloc_ports_state(), only called by ahci_detach 2638 */ 2639 static void 2640 ahci_dealloc_ports_state(ahci_ctl_t *ahci_ctlp) 2641 { 2642 int port; 2643 2644 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2645 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2646 /* if this port is implemented by the HBA */ 2647 if (AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) 2648 ahci_dealloc_port_state(ahci_ctlp, port); 2649 } 2650 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2651 } 2652 2653 /* 2654 * Initialize the controller and all ports. And then try to start the ports 2655 * if there are devices attached. 2656 * 2657 * This routine can be called from three seperate cases: DDI_ATTACH, 2658 * PM_LEVEL_D0 and DDI_RESUME. The DDI_ATTACH case is different from 2659 * other two cases; device signature probing are attempted only during 2660 * DDI_ATTACH case. 2661 * 2662 * WARNING!!! Disable the whole controller's interrupts before calling and 2663 * the interrupts will be enabled upon successfully return. 2664 */ 2665 static int 2666 ahci_initialize_controller(ahci_ctl_t *ahci_ctlp) 2667 { 2668 ahci_port_t *ahci_portp; 2669 uint32_t ghc_control; 2670 int port; 2671 2672 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2673 "ahci_initialize_controller enter"); 2674 2675 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2676 2677 /* 2678 * Indicate that system software is AHCI aware by setting 2679 * GHC.AE to 1 2680 */ 2681 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2682 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 2683 2684 ghc_control |= AHCI_HBA_GHC_AE; 2685 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 2686 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), 2687 ghc_control); 2688 2689 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2690 2691 /* Initialize the implemented ports and structures */ 2692 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2693 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2694 continue; 2695 } 2696 2697 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2698 mutex_enter(&ahci_portp->ahciport_mutex); 2699 2700 /* 2701 * Ensure that the controller is not in the running state 2702 * by checking every implemented port's PxCMD register 2703 */ 2704 if (ahci_initialize_port(ahci_ctlp, ahci_portp, port) 2705 != AHCI_SUCCESS) { 2706 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2707 "ahci_initialize_controller: failed to " 2708 "initialize port %d", port); 2709 /* 2710 * Set the port state to SATA_PSTATE_FAILED if 2711 * failed to initialize it. 2712 */ 2713 ahci_portp->ahciport_port_state = SATA_PSTATE_FAILED; 2714 } 2715 2716 mutex_exit(&ahci_portp->ahciport_mutex); 2717 } 2718 2719 /* Enable the whole controller interrupts */ 2720 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2721 ahci_enable_all_intrs(ahci_ctlp); 2722 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2723 2724 return (AHCI_SUCCESS); 2725 } 2726 2727 /* 2728 * Reverse of ahci_initialize_controller() 2729 * 2730 * We only need to stop the ports and disable the interrupt. 2731 */ 2732 static void 2733 ahci_uninitialize_controller(ahci_ctl_t *ahci_ctlp) 2734 { 2735 ahci_port_t *ahci_portp; 2736 int port; 2737 2738 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2739 "ahci_uninitialize_controller enter"); 2740 2741 /* disable all the interrupts. */ 2742 mutex_enter(&ahci_ctlp->ahcictl_mutex); 2743 ahci_disable_all_intrs(ahci_ctlp); 2744 mutex_exit(&ahci_ctlp->ahcictl_mutex); 2745 2746 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 2747 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 2748 continue; 2749 } 2750 2751 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 2752 2753 /* Stop the port by clearing PxCMD.ST */ 2754 mutex_enter(&ahci_portp->ahciport_mutex); 2755 2756 /* 2757 * Here we must disable the port interrupt because 2758 * ahci_disable_all_intrs only clear GHC.IE, and IS 2759 * register will be still set if PxIE is enabled. 2760 * When ahci shares one IRQ with other drivers, the 2761 * intr handler may claim the intr mistakenly. 2762 */ 2763 ahci_disable_port_intrs(ahci_ctlp, port); 2764 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 2765 ahci_portp, port); 2766 mutex_exit(&ahci_portp->ahciport_mutex); 2767 } 2768 } 2769 2770 /* 2771 * The routine is to initialize the port. First put the port in NOTRunning 2772 * state, then enable port interrupt and clear Serror register. And under 2773 * AHCI_ATTACH case, find device signature and then try to start the port. 2774 * 2775 * WARNING!!! ahciport_mutex should be acquired before the function is called. 2776 */ 2777 static int 2778 ahci_initialize_port(ahci_ctl_t *ahci_ctlp, 2779 ahci_port_t *ahci_portp, uint8_t port) 2780 { 2781 uint32_t port_cmd_status; 2782 2783 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 2784 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 2785 2786 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 2787 "ahci_initialize_port: port %d " 2788 "port_cmd_status = 0x%x", port, port_cmd_status); 2789 /* 2790 * Check whether the port is in NotRunning state, if not, 2791 * put the port in NotRunning state 2792 */ 2793 if (!(port_cmd_status & 2794 (AHCI_CMD_STATUS_ST | 2795 AHCI_CMD_STATUS_CR | 2796 AHCI_CMD_STATUS_FRE | 2797 AHCI_CMD_STATUS_FR))) { 2798 2799 goto next; 2800 } 2801 2802 if (ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 2803 port, AHCI_RESET_NO_EVENTS_UP|AHCI_PORT_INIT, NULL) != AHCI_SUCCESS) 2804 return (AHCI_FAILURE); 2805 2806 next: 2807 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2808 "port %d is in NotRunning state now", port); 2809 2810 /* 2811 * At the time being, only probe ports/devices and get the types of 2812 * attached devices during DDI_ATTACH. In fact, the device can be 2813 * changed during power state changes, but at the time being, we 2814 * don't support the situation. 2815 */ 2816 if (ahci_ctlp->ahcictl_flags & AHCI_ATTACH) { 2817 /* Try to get the device signature */ 2818 ahci_find_dev_signature(ahci_ctlp, ahci_portp, port); 2819 } else { 2820 2821 /* 2822 * During the resume, we need to set the PxCLB, PxCLBU, PxFB 2823 * and PxFBU registers in case these registers were cleared 2824 * during the suspend. 2825 */ 2826 AHCIDBG1(AHCIDBG_PM, ahci_ctlp, 2827 "ahci_initialize_port: port %d " 2828 "reset the port during resume", port); 2829 (void) ahci_port_reset(ahci_ctlp, ahci_portp, port); 2830 2831 AHCIDBG1(AHCIDBG_PM, ahci_ctlp, 2832 "ahci_initialize_port: port %d " 2833 "set PxCLB, PxCLBU, PxFB and PxFBU " 2834 "during resume", port); 2835 2836 /* Config Port Received FIS Base Address */ 2837 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 2838 (uint64_t *)AHCI_PORT_PxFB(ahci_ctlp, port), 2839 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_laddress); 2840 2841 /* Config Port Command List Base Address */ 2842 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 2843 (uint64_t *)AHCI_PORT_PxCLB(ahci_ctlp, port), 2844 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_laddress); 2845 } 2846 2847 /* Disable the interface power management */ 2848 ahci_disable_interface_pm(ahci_ctlp, port); 2849 2850 /* Return directly if no device connected */ 2851 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 2852 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2853 "No device connected to port %d", port); 2854 goto out; 2855 } 2856 2857 /* Try to start the port */ 2858 if (ahci_start_port(ahci_ctlp, ahci_portp, port) 2859 != AHCI_SUCCESS) { 2860 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2861 "failed to start port %d", port); 2862 return (AHCI_FAILURE); 2863 } 2864 out: 2865 /* Enable port interrupts */ 2866 ahci_enable_port_intrs(ahci_ctlp, port); 2867 2868 return (AHCI_SUCCESS); 2869 } 2870 2871 /* 2872 * Figure out which chip and set flag for VT8251; Also check 2873 * the power management capability. 2874 */ 2875 static int 2876 ahci_config_space_init(ahci_ctl_t *ahci_ctlp) 2877 { 2878 ushort_t venid, devid; 2879 ushort_t caps_ptr, cap_count, cap; 2880 #if AHCI_DEBUG 2881 ushort_t pmcap, pmcsr; 2882 #endif 2883 uint8_t revision; 2884 2885 venid = pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle, 2886 PCI_CONF_VENID); 2887 2888 devid = pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle, 2889 PCI_CONF_DEVID); 2890 2891 /* 2892 * Modify dma_attr_align of ahcictl_buffer_dma_attr. For VT8251, those 2893 * controllers with 0x00 revision id work on 4-byte aligned buffer, 2894 * which is a bug and was fixed after 0x00 revision id controllers. 2895 * 2896 * Moreover, VT8251 cannot use multiple command slots in the command 2897 * list for non-queued commands because the previous register content 2898 * of PxCI can be re-written in the register write, so a flag will be 2899 * set to record this defect - AHCI_CAP_NO_MCMDLIST_NONQUEUE. 2900 */ 2901 if (venid == VIA_VENID) { 2902 revision = pci_config_get8(ahci_ctlp->ahcictl_pci_conf_handle, 2903 PCI_CONF_REVID); 2904 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 2905 "revision id = 0x%x", revision); 2906 if (revision == 0x00) { 2907 ahci_ctlp->ahcictl_buffer_dma_attr.dma_attr_align = 0x4; 2908 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2909 "change ddi_attr_align to 0x4"); 2910 } 2911 2912 ahci_ctlp->ahcictl_cap = AHCI_CAP_NO_MCMDLIST_NONQUEUE; 2913 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2914 "VT8251 cannot use multiple command lists for " 2915 "non-queued commands"); 2916 } 2917 2918 /* 2919 * ATI SB600 (1002,4380) doesn't support 64-bit DMA addressing though it 2920 * declares support, so we need to set AHCI_CAP_32BIT_DMA flag to force 2921 * 32-bit DMA. 2922 */ 2923 if (venid == 0x1002 && devid == 0x4380) { 2924 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 2925 "ATI SB600 cannot do 64-bit DMA though CAP indicates " 2926 "support, so force it to use 32-bit DMA"); 2927 ahci_ctlp->ahcictl_cap |= AHCI_CAP_32BIT_DMA; 2928 } 2929 2930 /* 2931 * Check if capabilities list is supported and if so, 2932 * get initial capabilities pointer and clear bits 0,1. 2933 */ 2934 if (pci_config_get16(ahci_ctlp->ahcictl_pci_conf_handle, 2935 PCI_CONF_STAT) & PCI_STAT_CAP) { 2936 caps_ptr = P2ALIGN(pci_config_get8( 2937 ahci_ctlp->ahcictl_pci_conf_handle, 2938 PCI_CONF_CAP_PTR), 4); 2939 } else { 2940 caps_ptr = PCI_CAP_NEXT_PTR_NULL; 2941 } 2942 2943 /* 2944 * Walk capabilities if supported. 2945 */ 2946 for (cap_count = 0; caps_ptr != PCI_CAP_NEXT_PTR_NULL; ) { 2947 2948 /* 2949 * Check that we haven't exceeded the maximum number of 2950 * capabilities and that the pointer is in a valid range. 2951 */ 2952 if (++cap_count > PCI_CAP_MAX_PTR) { 2953 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 2954 "too many device capabilities"); 2955 return (AHCI_FAILURE); 2956 } 2957 if (caps_ptr < PCI_CAP_PTR_OFF) { 2958 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 2959 "capabilities pointer 0x%x out of range", 2960 caps_ptr); 2961 return (AHCI_FAILURE); 2962 } 2963 2964 /* 2965 * Get next capability and check that it is valid. 2966 * For now, we only support power management. 2967 */ 2968 cap = pci_config_get8(ahci_ctlp->ahcictl_pci_conf_handle, 2969 caps_ptr); 2970 switch (cap) { 2971 case PCI_CAP_ID_PM: 2972 2973 /* power management supported */ 2974 ahci_ctlp->ahcictl_cap |= AHCI_CAP_PM; 2975 2976 /* Save PMCSR offset */ 2977 ahci_ctlp->ahcictl_pmcsr_offset = caps_ptr + PCI_PMCSR; 2978 2979 #if AHCI_DEBUG 2980 pmcap = pci_config_get16( 2981 ahci_ctlp->ahcictl_pci_conf_handle, 2982 caps_ptr + PCI_PMCAP); 2983 pmcsr = pci_config_get16( 2984 ahci_ctlp->ahcictl_pci_conf_handle, 2985 ahci_ctlp->ahcictl_pmcsr_offset); 2986 AHCIDBG2(AHCIDBG_PM, ahci_ctlp, 2987 "Power Management capability found PCI_PMCAP " 2988 "= 0x%x PCI_PMCSR = 0x%x", pmcap, pmcsr); 2989 if ((pmcap & 0x3) == 0x3) 2990 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 2991 "PCI Power Management Interface " 2992 "spec 1.2 compliant"); 2993 #endif 2994 break; 2995 2996 case PCI_CAP_ID_MSI: 2997 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, "MSI capability found"); 2998 break; 2999 3000 case PCI_CAP_ID_PCIX: 3001 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3002 "PCI-X capability found"); 3003 break; 3004 3005 case PCI_CAP_ID_PCI_E: 3006 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3007 "PCI Express capability found"); 3008 break; 3009 3010 case PCI_CAP_ID_MSI_X: 3011 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3012 "MSI-X capability found"); 3013 break; 3014 3015 case PCI_CAP_ID_SATA: 3016 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3017 "SATA capability found"); 3018 break; 3019 3020 case PCI_CAP_ID_VS: 3021 AHCIDBG0(AHCIDBG_PM, ahci_ctlp, 3022 "Vendor Specific capability found"); 3023 break; 3024 3025 default: 3026 AHCIDBG1(AHCIDBG_PM, ahci_ctlp, 3027 "unrecognized capability 0x%x", cap); 3028 break; 3029 } 3030 3031 /* 3032 * Get next capabilities pointer and clear bits 0,1. 3033 */ 3034 caps_ptr = P2ALIGN(pci_config_get8( 3035 ahci_ctlp->ahcictl_pci_conf_handle, 3036 (caps_ptr + PCI_CAP_NEXT_PTR)), 4); 3037 } 3038 3039 return (AHCI_SUCCESS); 3040 } 3041 3042 /* 3043 * AHCI device reset ...; a single device on one of the ports is reset, 3044 * but the HBA and physical communication remain intact. This is the 3045 * least intrusive. 3046 * 3047 * When issuing a software reset sequence, there should not be other 3048 * commands in the command list, so we will first clear and then re-set 3049 * PxCMD.ST to clear PxCI. And before issuing the software reset, 3050 * the port must be idle and PxTFD.STS.BSY and PxTFD.STS.DRQ must be 3051 * cleared. 3052 * 3053 * WARNING!!! ahciport_mutex should be acquired and PxCMD.FRE should be 3054 * set before the function is called. 3055 */ 3056 static int 3057 ahci_software_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 3058 uint8_t port) 3059 { 3060 ahci_fis_h2d_register_t *h2d_register_fisp; 3061 ahci_cmd_table_t *cmd_table; 3062 ahci_cmd_header_t *cmd_header; 3063 uint32_t port_cmd_status, port_cmd_issue, port_task_file; 3064 int slot, loop_count; 3065 3066 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 3067 "Port %d device resetting", port); 3068 3069 /* First to clear PxCMD.ST */ 3070 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3071 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3072 3073 port_cmd_status &= ~AHCI_CMD_STATUS_ST; 3074 3075 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3076 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3077 port_cmd_status|AHCI_CMD_STATUS_ST); 3078 3079 /* And then to re-set PxCMD.ST */ 3080 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3081 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3082 3083 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3084 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3085 port_cmd_status|AHCI_CMD_STATUS_ST); 3086 3087 /* Check PxTFD.STS.BSY and PxTFD.STS.DRQ */ 3088 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3089 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3090 3091 if (port_task_file & AHCI_TFD_STS_BSY || 3092 port_task_file & AHCI_TFD_STS_DRQ) { 3093 if (!(port_cmd_status & AHCI_CMD_STATUS_CLO)) { 3094 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 3095 "PxTFD.STS.BSY or PxTFD.STS.DRQ is still set, " 3096 "but PxCMD.CLO isn't supported, so a port " 3097 "reset is needed."); 3098 return (AHCI_FAILURE); 3099 } 3100 } 3101 3102 slot = ahci_claim_free_slot(ahci_ctlp, ahci_portp, AHCI_NON_NCQ_CMD); 3103 if (slot == AHCI_FAILURE) { 3104 AHCIDBG0(AHCIDBG_INFO, ahci_ctlp, 3105 "ahci_software_reset: no free slot"); 3106 return (AHCI_FAILURE); 3107 } 3108 3109 /* Now send the first R2H FIS with SRST set to 1 */ 3110 cmd_table = ahci_portp->ahciport_cmd_tables[slot]; 3111 bzero((void *)cmd_table, ahci_cmd_table_size); 3112 3113 h2d_register_fisp = 3114 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 3115 3116 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 3117 SET_FIS_PMP(h2d_register_fisp, AHCI_PORTMULT_CONTROL_PORT); 3118 SET_FIS_DEVCTL(h2d_register_fisp, SATA_DEVCTL_SRST); 3119 3120 /* Set Command Header in Command List */ 3121 cmd_header = &ahci_portp->ahciport_cmd_list[slot]; 3122 BZERO_DESCR_INFO(cmd_header); 3123 BZERO_PRD_BYTE_COUNT(cmd_header); 3124 SET_COMMAND_FIS_LENGTH(cmd_header, 5); 3125 3126 SET_CLEAR_BUSY_UPON_R_OK(cmd_header, 1); 3127 SET_RESET(cmd_header, 1); 3128 SET_WRITE(cmd_header, 1); 3129 3130 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_tables_dma_handle[slot], 3131 0, 3132 ahci_cmd_table_size, 3133 DDI_DMA_SYNC_FORDEV); 3134 3135 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 3136 slot * sizeof (ahci_cmd_header_t), 3137 sizeof (ahci_cmd_header_t), 3138 DDI_DMA_SYNC_FORDEV); 3139 3140 /* Indicate to the HBA that a command is active. */ 3141 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3142 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 3143 (0x1 << slot)); 3144 3145 loop_count = 0; 3146 3147 /* Loop till the first command is finished */ 3148 do { 3149 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3150 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 3151 3152 if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) { 3153 /* We are effectively timing out after 0.1 sec. */ 3154 break; 3155 } 3156 /* Wait for 10 millisec */ 3157 delay(AHCI_10MS_TICKS); 3158 } while (port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp) & (0x1 << slot)); 3159 3160 AHCIDBG3(AHCIDBG_POLL_LOOP, ahci_ctlp, 3161 "ahci_software_reset: 1st loop count: %d, " 3162 "port_cmd_issue = 0x%x, slot = 0x%x", 3163 loop_count, port_cmd_issue, slot); 3164 3165 CLEAR_BIT(ahci_portp->ahciport_pending_tags, slot); 3166 ahci_portp->ahciport_slot_pkts[slot] = NULL; 3167 3168 /* Now send the second R2H FIS with SRST cleard to zero */ 3169 cmd_table = ahci_portp->ahciport_cmd_tables[slot]; 3170 bzero((void *)cmd_table, ahci_cmd_table_size); 3171 3172 h2d_register_fisp = 3173 &(cmd_table->ahcict_command_fis.ahcifc_fis.ahcifc_h2d_register); 3174 3175 SET_FIS_TYPE(h2d_register_fisp, AHCI_H2D_REGISTER_FIS_TYPE); 3176 SET_FIS_PMP(h2d_register_fisp, AHCI_PORTMULT_CONTROL_PORT); 3177 3178 /* Set Command Header in Command List */ 3179 cmd_header = &ahci_portp->ahciport_cmd_list[slot]; 3180 BZERO_DESCR_INFO(cmd_header); 3181 BZERO_PRD_BYTE_COUNT(cmd_header); 3182 SET_COMMAND_FIS_LENGTH(cmd_header, 5); 3183 3184 SET_WRITE(cmd_header, 1); 3185 3186 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_tables_dma_handle[slot], 3187 0, 3188 ahci_cmd_table_size, 3189 DDI_DMA_SYNC_FORDEV); 3190 3191 (void) ddi_dma_sync(ahci_portp->ahciport_cmd_list_dma_handle, 3192 slot * sizeof (ahci_cmd_header_t), 3193 sizeof (ahci_cmd_header_t), 3194 DDI_DMA_SYNC_FORDEV); 3195 3196 /* Indicate to the HBA that a command is active. */ 3197 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3198 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port), 3199 (0x1 << slot)); 3200 3201 loop_count = 0; 3202 3203 /* Loop till the second command is finished */ 3204 do { 3205 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3206 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 3207 3208 if (loop_count++ > AHCI_POLLRATE_PORT_SOFTRESET) { 3209 /* We are effectively timing out after 0.1 sec. */ 3210 break; 3211 } 3212 /* Wait for 10 millisec */ 3213 delay(AHCI_10MS_TICKS); 3214 } while (port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp) & (0x1 << slot)); 3215 3216 AHCIDBG3(AHCIDBG_POLL_LOOP, ahci_ctlp, 3217 "ahci_software_reset: 2nd loop count: %d, " 3218 "port_cmd_issue = 0x%x, slot = 0x%x", 3219 loop_count, port_cmd_issue, slot); 3220 3221 CLEAR_BIT(ahci_portp->ahciport_pending_tags, slot); 3222 ahci_portp->ahciport_slot_pkts[slot] = NULL; 3223 3224 return (AHCI_SUCCESS); 3225 } 3226 3227 /* 3228 * AHCI port reset ...; the physical communication between the HBA and device 3229 * on a port are disabled. This is more intrusive. 3230 * 3231 * When an HBA or port reset occurs, Phy communication is going to 3232 * be re-established with the device through a COMRESET followed by the 3233 * normal out-of-band communication sequence defined in Serial ATA. AT 3234 * the end of reset, the device, if working properly, will send a D2H 3235 * Register FIS, which contains the device signature. When the HBA receives 3236 * this FIS, it updates PxTFD.STS and PxTFD.ERR register fields, and updates 3237 * the PxSIG register with the signature. 3238 * 3239 * Staggered spin-up is an optional feature in SATA II, and it enables an HBA 3240 * to individually spin-up attached devices. Please refer to chapter 10.9 of 3241 * AHCI 1.0 spec. 3242 */ 3243 /* 3244 * WARNING!!! ahciport_mutex should be acquired, and PxCMD.ST should be also 3245 * cleared before the function is called. 3246 */ 3247 static int 3248 ahci_port_reset(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 3249 { 3250 uint32_t cap_status, port_cmd_status; 3251 uint32_t port_scontrol, port_sstatus; 3252 uint32_t port_intr_status, port_task_file; 3253 #if AHCI_DEBUG 3254 uint32_t port_signature; 3255 #endif 3256 int loop_count; 3257 int rval = AHCI_SUCCESS; 3258 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 3259 3260 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 3261 "Port %d port resetting...", port); 3262 ahci_portp->ahciport_port_state = 0; 3263 3264 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3265 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 3266 3267 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3268 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3269 3270 if (cap_status & AHCI_HBA_CAP_SSS) { 3271 /* 3272 * HBA support staggered spin-up, if the port has 3273 * not spin up yet, then force it to do spin-up 3274 */ 3275 if (!(port_cmd_status & AHCI_CMD_STATUS_SUD)) { 3276 if (!(ahci_portp->ahciport_flags 3277 & AHCI_PORT_FLAG_SPINUP)) { 3278 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 3279 "Port %d PxCMD.SUD is zero, force " 3280 "it to do spin-up", port); 3281 ahci_portp->ahciport_flags |= 3282 AHCI_PORT_FLAG_SPINUP; 3283 } 3284 } 3285 } else { 3286 /* 3287 * HBA doesn't support stagger spin-up, force it 3288 * to do normal COMRESET 3289 */ 3290 if (ahci_portp->ahciport_flags & 3291 AHCI_PORT_FLAG_SPINUP) { 3292 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3293 "HBA does not support staggered spin-up " 3294 "force it to do normal COMRESET"); 3295 ahci_portp->ahciport_flags &= 3296 ~AHCI_PORT_FLAG_SPINUP; 3297 } 3298 } 3299 3300 if (!(ahci_portp->ahciport_flags & AHCI_PORT_FLAG_SPINUP)) { 3301 /* Do normal COMRESET */ 3302 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3303 "ahci_port_reset: do normal COMRESET", port); 3304 3305 /* 3306 * According to the spec, SUD bit should be set here, 3307 * but JMicron JMB363 doesn't follow it, so remove 3308 * the assertion, and just print a debug message. 3309 */ 3310 #if AHCI_DEBUG 3311 if (!(port_cmd_status & AHCI_CMD_STATUS_SUD)) 3312 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3313 "port %d SUD bit not set", port) 3314 #endif 3315 3316 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3317 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3318 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_COMRESET); 3319 3320 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3321 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 3322 port_scontrol); 3323 3324 /* Enable PxCMD.FRE to read device */ 3325 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3326 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3327 port_cmd_status|AHCI_CMD_STATUS_FRE); 3328 3329 /* 3330 * Give time for COMRESET to percolate, according to the AHCI 3331 * spec, software shall wait at least 1 millisecond before 3332 * clearing PxSCTL.DET 3333 */ 3334 delay(AHCI_1MS_TICKS*2); 3335 3336 /* Fetch the SCONTROL again and rewrite the DET part with 0 */ 3337 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3338 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3339 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_NOACTION); 3340 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3341 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 3342 port_scontrol); 3343 } else { 3344 /* Do staggered spin-up */ 3345 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3346 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3347 SCONTROL_SET_DET(port_scontrol, SCONTROL_DET_NOACTION); 3348 3349 /* PxSCTL.DET must be 0 */ 3350 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3351 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), 3352 port_scontrol); 3353 3354 port_cmd_status &= ~AHCI_CMD_STATUS_SUD; 3355 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3356 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3357 port_cmd_status); 3358 3359 /* 0 -> 1 edge */ 3360 delay(AHCI_1MS_TICKS*2); 3361 3362 /* Set PxCMD.SUD to 1 */ 3363 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3364 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3365 port_cmd_status |= AHCI_CMD_STATUS_SUD; 3366 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3367 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3368 port_cmd_status); 3369 3370 /* Enable PxCMD.FRE to read device */ 3371 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3372 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3373 port_cmd_status|AHCI_CMD_STATUS_FRE); 3374 } 3375 3376 /* 3377 * The port enters P:StartComm state, and HBA tells link layer to 3378 * start communication, which involves sending COMRESET to device. 3379 * And the HBA resets PxTFD.STS to 7Fh. 3380 * 3381 * When a COMINIT is received from the device, then the port enters 3382 * P:ComInit state. And HBA sets PxTFD.STS to FFh or 80h. HBA sets 3383 * PxSSTS.DET to 1h to indicate a device is detected but communication 3384 * is not yet established. HBA sets PxSERR.DIAG.X to '1' to indicate 3385 * a COMINIT has been received. 3386 */ 3387 /* 3388 * The DET field is valid only if IPM field indicates 3389 * that the interface is in active state. 3390 */ 3391 loop_count = 0; 3392 do { 3393 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3394 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 3395 3396 if (SSTATUS_GET_IPM(port_sstatus) != SSTATUS_IPM_ACTIVE) { 3397 /* 3398 * If the interface is not active, the DET field 3399 * is considered not accurate. So we want to 3400 * continue looping. 3401 */ 3402 SSTATUS_SET_DET(port_sstatus, SSTATUS_DET_NODEV); 3403 } 3404 3405 if (loop_count++ > AHCI_POLLRATE_PORT_SSTATUS) { 3406 /* 3407 * We are effectively timing out after 0.1 sec. 3408 */ 3409 break; 3410 } 3411 3412 /* Wait for 10 millisec */ 3413 delay(AHCI_10MS_TICKS); 3414 } while (SSTATUS_GET_DET(port_sstatus) != SSTATUS_DET_DEVPRE_PHYCOM); 3415 3416 AHCIDBG3(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 3417 "ahci_port_reset: 1st loop count: %d, " 3418 "port_sstatus = 0x%x port %d", 3419 loop_count, port_sstatus, port); 3420 3421 if ((SSTATUS_GET_IPM(port_sstatus) != SSTATUS_IPM_ACTIVE) || 3422 (SSTATUS_GET_DET(port_sstatus) != SSTATUS_DET_DEVPRE_PHYCOM)) { 3423 /* 3424 * Either the port is not active or there 3425 * is no device present. 3426 */ 3427 ahci_portp->ahciport_device_type = SATA_DTYPE_NONE; 3428 goto out; 3429 } 3430 3431 /* Now we can make sure there is a device connected to the port */ 3432 port_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3433 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port)); 3434 3435 /* a COMINIT signal is supposed to be received */ 3436 if (!(port_intr_status & AHCI_INTR_STATUS_PCS)) { 3437 cmn_err(CE_WARN, "!ahci%d: ahci_port_reset port %d " 3438 "COMINIT signal from the device not received", 3439 instance, port); 3440 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 3441 rval = AHCI_FAILURE; 3442 goto out; 3443 } 3444 3445 /* 3446 * According to the spec, when PxSCTL.DET is set to 0h, upon 3447 * receiving a COMINIT from the attached device, PxTFD.STS.BSY 3448 * shall be set to '1' by the HBA. 3449 * 3450 * However, we found JMicron JMB363 doesn't follow this, so 3451 * remove this check, and just print a debug message. 3452 */ 3453 #if AHCI_DEBUG 3454 port_task_file = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3455 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3456 if (!(port_task_file & AHCI_TFD_STS_BSY)) { 3457 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_port_reset: " 3458 "port %d BSY bit is not set after COMINIT signal " 3459 "is received", port); 3460 } 3461 #endif 3462 3463 /* 3464 * PxSERR.DIAG.X has to be cleared in order to update PxTFD with 3465 * the D2H FIS received by HBA. 3466 */ 3467 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3468 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 3469 SERROR_EXCHANGED_ERR); 3470 3471 /* 3472 * Next check whether COMRESET is completed successfully 3473 */ 3474 loop_count = 0; 3475 do { 3476 port_task_file = 3477 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3478 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3479 3480 /* 3481 * The Error bit '1' means COMRESET is finished successfully 3482 * The device hardware has been initialized and the power-up 3483 * diagnostics successfully completed. 3484 */ 3485 if (((port_task_file & AHCI_TFD_ERR_MASK) 3486 >> AHCI_TFD_ERR_SHIFT) == 0x1) { 3487 #if AHCI_DEBUG 3488 port_signature = ddi_get32( 3489 ahci_ctlp->ahcictl_ahci_acc_handle, 3490 (uint32_t *)AHCI_PORT_PxSIG(ahci_ctlp, port)); 3491 AHCIDBG2(AHCIDBG_INFO, ahci_ctlp, 3492 "COMRESET success, D2H register FIS " 3493 "post to received FIS structure " 3494 "port %d signature = 0x%x", 3495 port, port_signature); 3496 #endif 3497 goto out_check; 3498 } 3499 3500 if (loop_count++ > AHCI_POLLRATE_PORT_TFD_ERROR) { 3501 /* 3502 * We are effectively timing out after 11 sec. 3503 */ 3504 break; 3505 } 3506 3507 /* Wait for 10 millisec */ 3508 delay(AHCI_10MS_TICKS); 3509 } while (((port_task_file & AHCI_TFD_ERR_MASK) 3510 >> AHCI_TFD_ERR_SHIFT) != 0x1); 3511 3512 AHCIDBG3(AHCIDBG_ERRS, ahci_ctlp, "ahci_port_reset: 2nd loop " 3513 "count: %d, port_task_file = 0x%x port %d", 3514 loop_count, port_task_file, port); 3515 3516 cmn_err(CE_WARN, "!ahci%d: ahci_port_reset port %d the device hardware " 3517 "has been initialized and the power-up diagnostics failed", 3518 instance, port); 3519 3520 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 3521 rval = AHCI_FAILURE; 3522 3523 out: 3524 /* Clear port serror register for the port */ 3525 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3526 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 3527 AHCI_SERROR_CLEAR_ALL); 3528 3529 return (rval); 3530 3531 out_check: 3532 /* 3533 * Check device status, if keep busy or COMRESET error 3534 * do device reset to patch some SATA disks' issue 3535 * 3536 * For VT8251, sometimes need to do the device reset 3537 */ 3538 if ((port_task_file & AHCI_TFD_STS_BSY) || 3539 (port_task_file & AHCI_TFD_STS_DRQ)) { 3540 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "port %d keep BSY/DRQ set " 3541 "need to do device reset", port); 3542 3543 (void) ahci_software_reset(ahci_ctlp, ahci_portp, port); 3544 3545 port_task_file = 3546 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3547 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 3548 3549 if (port_task_file & AHCI_TFD_STS_BSY || 3550 port_task_file & AHCI_TFD_STS_DRQ) { 3551 cmn_err(CE_WARN, "!ahci%d: ahci_port_reset: port %d " 3552 "BSY/DRQ still set after device reset " 3553 "port_task_file = 0x%x", instance, 3554 port, port_task_file); 3555 ahci_portp->ahciport_port_state |= SATA_PSTATE_FAILED; 3556 rval = AHCI_FAILURE; 3557 } 3558 } 3559 3560 goto out; 3561 } 3562 3563 /* 3564 * AHCI HBA reset ...; the entire HBA is reset, and all ports are disabled. 3565 * This is the most intrusive. 3566 * 3567 * When an HBA reset occurs, Phy communication will be re-established with 3568 * the device through a COMRESET followed by the normal out-of-band 3569 * communication sequence defined in Serial ATA. AT the end of reset, the 3570 * device, if working properly, will send a D2H Register FIS, which contains 3571 * the device signature. When the HBA receives this FIS, it updates PxTFD.STS 3572 * and PxTFD.ERR register fields, and updates the PxSIG register with the 3573 * signature. 3574 * 3575 * Remember to set GHC.AE to 1 before calling ahci_hba_reset. 3576 */ 3577 static int 3578 ahci_hba_reset(ahci_ctl_t *ahci_ctlp) 3579 { 3580 ahci_port_t *ahci_portp; 3581 uint32_t ghc_control; 3582 uint8_t port; 3583 int loop_count; 3584 int rval = AHCI_SUCCESS; 3585 3586 AHCIDBG0(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, "HBA resetting"); 3587 3588 mutex_enter(&ahci_ctlp->ahcictl_mutex); 3589 3590 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3591 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3592 3593 /* Setting GHC.HR to 1, remember GHC.AE is already set to 1 before */ 3594 ghc_control |= AHCI_HBA_GHC_HR; 3595 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3596 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 3597 3598 /* 3599 * Wait until HBA Reset complete or timeout 3600 */ 3601 loop_count = 0; 3602 do { 3603 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3604 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3605 3606 if (loop_count++ > AHCI_POLLRATE_HBA_RESET) { 3607 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, 3608 "ahci hba reset is timing out, " 3609 "ghc_control = 0x%x", ghc_control); 3610 /* We are effectively timing out after 1 sec. */ 3611 break; 3612 } 3613 3614 /* Wait for 10 millisec */ 3615 delay(AHCI_10MS_TICKS); 3616 } while (ghc_control & AHCI_HBA_GHC_HR); 3617 3618 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 3619 "ahci_hba_reset: 1st loop count: %d, " 3620 "ghc_control = 0x%x", loop_count, ghc_control); 3621 3622 if (ghc_control & AHCI_HBA_GHC_HR) { 3623 /* The hba is not reset for some reasons */ 3624 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3625 "hba reset failed: HBA in a hung or locked state"); 3626 mutex_exit(&ahci_ctlp->ahcictl_mutex); 3627 return (AHCI_FAILURE); 3628 } 3629 3630 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 3631 /* Only check implemented ports */ 3632 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 3633 continue; 3634 } 3635 3636 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 3637 mutex_enter(&ahci_portp->ahciport_mutex); 3638 3639 if (ahci_port_reset(ahci_ctlp, ahci_portp, port) 3640 != AHCI_SUCCESS) { 3641 rval = AHCI_FAILURE; 3642 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 3643 "ahci_hba_reset: port %d failed", port); 3644 } 3645 3646 mutex_exit(&ahci_portp->ahciport_mutex); 3647 } 3648 3649 /* 3650 * Indicate that system software is AHCI aware by setting 3651 * GHC.AE to 1 3652 */ 3653 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3654 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 3655 3656 ghc_control |= AHCI_HBA_GHC_AE; 3657 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3658 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 3659 3660 mutex_exit(&ahci_ctlp->ahcictl_mutex); 3661 3662 return (rval); 3663 } 3664 3665 /* 3666 * This routine is only called from AHCI_ATTACH or phyrdy change 3667 * case. It first calls port reset to initialize port, probe port and probe 3668 * device, then try to read PxSIG register to find the type of device 3669 * attached to the port. 3670 * 3671 * WARNING!!! ahciport_mutex should be acquired before the function 3672 * is called. And the port interrupt is disabled. 3673 */ 3674 static void 3675 ahci_find_dev_signature(ahci_ctl_t *ahci_ctlp, 3676 ahci_port_t *ahci_portp, uint8_t port) 3677 { 3678 uint32_t signature; 3679 3680 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 3681 "ahci_find_dev_signature enter: port %d", port); 3682 3683 ahci_portp->ahciport_device_type = SATA_DTYPE_UNKNOWN; 3684 3685 /* Call port reset to check link status and get device signature */ 3686 (void) ahci_port_reset(ahci_ctlp, ahci_portp, port); 3687 3688 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 3689 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3690 "ahci_find_dev_signature: No device is found " 3691 "at port %d", port); 3692 return; 3693 } 3694 3695 /* Check the port state */ 3696 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED) { 3697 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 3698 "ahci_find_dev_signature: port %d state 0x%x", 3699 port, ahci_portp->ahciport_port_state); 3700 return; 3701 } 3702 3703 signature = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3704 (uint32_t *)AHCI_PORT_PxSIG(ahci_ctlp, port)); 3705 3706 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_INFO, ahci_ctlp, 3707 "ahci_find_dev_signature: port %d signature = 0x%x", 3708 port, signature); 3709 3710 switch (signature) { 3711 3712 case AHCI_SIGNATURE_DISK: 3713 ahci_portp->ahciport_device_type = SATA_DTYPE_ATADISK; 3714 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3715 "Disk is found at port: %d", port); 3716 break; 3717 3718 case AHCI_SIGNATURE_ATAPI: 3719 ahci_portp->ahciport_device_type = SATA_DTYPE_ATAPICD; 3720 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3721 "ATAPI device is found at port: %d", port); 3722 break; 3723 3724 case AHCI_SIGNATURE_PORT_MULTIPLIER: 3725 ahci_portp->ahciport_device_type = SATA_DTYPE_PMULT; 3726 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3727 "Port Multiplier is found at port: %d", port); 3728 break; 3729 3730 default: 3731 ahci_portp->ahciport_device_type = SATA_DTYPE_UNKNOWN; 3732 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, 3733 "Unknown device is found at port: %d", port); 3734 } 3735 } 3736 3737 /* 3738 * According to the spec, to reliably detect hot plug removals, software 3739 * must disable interface power management. Software should perform the 3740 * following initialization on a port after a device is attached: 3741 * Set PxSCTL.IPM to 3h to disable interface state transitions 3742 * Set PxCMD.ALPE to '0' to disable aggressive power management 3743 * Disable device initiated interface power management by SET FEATURE 3744 * 3745 * We can ignore the last item because by default the feature is disabled 3746 */ 3747 static void 3748 ahci_disable_interface_pm(ahci_ctl_t *ahci_ctlp, uint8_t port) 3749 { 3750 uint32_t port_scontrol, port_cmd_status; 3751 3752 port_scontrol = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3753 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port)); 3754 SCONTROL_SET_IPM(port_scontrol, SCONTROL_IPM_DISABLE_BOTH); 3755 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3756 (uint32_t *)AHCI_PORT_PxSCTL(ahci_ctlp, port), port_scontrol); 3757 3758 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3759 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3760 port_cmd_status &= ~AHCI_CMD_STATUS_ALPE; 3761 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3762 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), port_cmd_status); 3763 } 3764 3765 /* 3766 * Start the port - set PxCMD.ST to 1, if PxCMD.FRE is not set 3767 * to 1, then set it firstly. 3768 * 3769 * Each port contains two major DMA engines. One DMA engine walks through 3770 * the command list, and is controlled by PxCMD.ST. The second DMA engine 3771 * copies received FISes into system memory, and is controlled by PxCMD.FRE. 3772 * 3773 * Software shall not set PxCMD.ST to '1' until it verifies that PxCMD.CR 3774 * is '0' and has set PxCMD.FRE is '1'. And software shall not clear 3775 * PxCMD.FRE while PxCMD.ST or PxCMD.CR is set '1'. 3776 * 3777 * Software shall not set PxCMD.ST to '1' unless a functional device is 3778 * present on the port(as determined by PxTFD.STS.BSY = '0', 3779 * PxTFD.STS.DRQ = '0', and PxSSTS.DET = 3h). 3780 * 3781 * WARNING!!! ahciport_mutex should be acquired before the function 3782 * is called. 3783 */ 3784 static int 3785 ahci_start_port(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 3786 { 3787 uint32_t port_cmd_status; 3788 3789 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, "ahci_start_port: %d enter", port); 3790 3791 if (ahci_portp->ahciport_port_state & SATA_PSTATE_FAILED) { 3792 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port failed " 3793 "the state for port %d is 0x%x", 3794 port, ahci_portp->ahciport_port_state); 3795 return (AHCI_FAILURE); 3796 } 3797 3798 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 3799 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_start_port failed " 3800 "no device is attached at port %d", port); 3801 return (AHCI_FAILURE); 3802 } 3803 3804 /* First to set PxCMD.FRE before setting PxCMD.ST. */ 3805 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3806 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3807 3808 if (!(port_cmd_status & AHCI_CMD_STATUS_FRE)) { 3809 port_cmd_status |= AHCI_CMD_STATUS_FRE; 3810 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3811 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3812 port_cmd_status); 3813 } 3814 3815 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 3816 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 3817 3818 port_cmd_status |= AHCI_CMD_STATUS_ST; 3819 3820 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 3821 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), 3822 port_cmd_status); 3823 3824 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_STARTED; 3825 3826 return (AHCI_SUCCESS); 3827 } 3828 3829 /* 3830 * Allocate the ahci_port_t including Received FIS and Command List. 3831 * The argument - port is the physical port number, and not logical 3832 * port number seen by the SATA framework. 3833 * 3834 * WARNING!!! ahcictl_mutex should be acquired before the function 3835 * is called. 3836 */ 3837 static int 3838 ahci_alloc_port_state(ahci_ctl_t *ahci_ctlp, uint8_t port) 3839 { 3840 ahci_port_t *ahci_portp; 3841 3842 ahci_portp = 3843 (ahci_port_t *)kmem_zalloc(sizeof (ahci_port_t), KM_SLEEP); 3844 3845 ahci_ctlp->ahcictl_ports[port] = ahci_portp; 3846 ahci_portp->ahciport_port_num = port; 3847 3848 /* Intialize the port condition variable */ 3849 cv_init(&ahci_portp->ahciport_cv, NULL, CV_DRIVER, NULL); 3850 3851 /* Initialize the port mutex */ 3852 mutex_init(&ahci_portp->ahciport_mutex, NULL, MUTEX_DRIVER, 3853 (void *)(uintptr_t)ahci_ctlp->ahcictl_intr_pri); 3854 3855 mutex_enter(&ahci_portp->ahciport_mutex); 3856 3857 /* 3858 * Allocate memory for received FIS structure and 3859 * command list for this port 3860 */ 3861 if (ahci_alloc_rcvd_fis(ahci_ctlp, ahci_portp, port) != AHCI_SUCCESS) { 3862 goto err_case1; 3863 } 3864 3865 if (ahci_alloc_cmd_list(ahci_ctlp, ahci_portp, port) != AHCI_SUCCESS) { 3866 goto err_case2; 3867 } 3868 3869 ahci_portp->ahciport_event_args = 3870 kmem_zalloc(sizeof (ahci_event_arg_t), KM_SLEEP); 3871 3872 if (ahci_portp->ahciport_event_args == NULL) 3873 goto err_case3; 3874 3875 mutex_exit(&ahci_portp->ahciport_mutex); 3876 3877 return (AHCI_SUCCESS); 3878 3879 err_case3: 3880 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp); 3881 3882 err_case2: 3883 ahci_dealloc_rcvd_fis(ahci_portp); 3884 3885 err_case1: 3886 mutex_exit(&ahci_portp->ahciport_mutex); 3887 mutex_destroy(&ahci_portp->ahciport_mutex); 3888 cv_destroy(&ahci_portp->ahciport_cv); 3889 3890 kmem_free(ahci_portp, sizeof (ahci_port_t)); 3891 3892 return (AHCI_FAILURE); 3893 } 3894 3895 /* 3896 * Reverse of ahci_dealloc_port_state(). 3897 * 3898 * WARNING!!! ahcictl_mutex should be acquired before the function 3899 * is called. 3900 */ 3901 static void 3902 ahci_dealloc_port_state(ahci_ctl_t *ahci_ctlp, uint8_t port) 3903 { 3904 ahci_port_t *ahci_portp = ahci_ctlp->ahcictl_ports[port]; 3905 3906 ASSERT(ahci_portp != NULL); 3907 3908 mutex_enter(&ahci_portp->ahciport_mutex); 3909 kmem_free(ahci_portp->ahciport_event_args, sizeof (ahci_event_arg_t)); 3910 ahci_portp->ahciport_event_args = NULL; 3911 ahci_dealloc_cmd_list(ahci_ctlp, ahci_portp); 3912 ahci_dealloc_rcvd_fis(ahci_portp); 3913 mutex_exit(&ahci_portp->ahciport_mutex); 3914 3915 mutex_destroy(&ahci_portp->ahciport_mutex); 3916 cv_destroy(&ahci_portp->ahciport_cv); 3917 3918 kmem_free(ahci_portp, sizeof (ahci_port_t)); 3919 3920 ahci_ctlp->ahcictl_ports[port] = NULL; 3921 } 3922 3923 /* 3924 * Allocates memory for the Received FIS Structure 3925 * 3926 * WARNING!!! ahciport_mutex should be acquired before the function 3927 * is called. 3928 */ 3929 static int 3930 ahci_alloc_rcvd_fis(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 3931 uint8_t port) 3932 { 3933 size_t rcvd_fis_size; 3934 size_t ret_len; 3935 uint_t cookie_count; 3936 3937 rcvd_fis_size = sizeof (ahci_rcvd_fis_t); 3938 3939 /* allocate rcvd FIS dma handle. */ 3940 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 3941 &ahci_ctlp->ahcictl_rcvd_fis_dma_attr, 3942 DDI_DMA_SLEEP, 3943 NULL, 3944 &ahci_portp->ahciport_rcvd_fis_dma_handle) != 3945 DDI_SUCCESS) { 3946 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3947 "rcvd FIS dma handle alloc failed"); 3948 3949 return (AHCI_FAILURE); 3950 } 3951 3952 if (ddi_dma_mem_alloc(ahci_portp->ahciport_rcvd_fis_dma_handle, 3953 rcvd_fis_size, 3954 &accattr, 3955 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 3956 DDI_DMA_SLEEP, 3957 NULL, 3958 (caddr_t *)&ahci_portp->ahciport_rcvd_fis, 3959 &ret_len, 3960 &ahci_portp->ahciport_rcvd_fis_acc_handle) != NULL) { 3961 3962 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3963 "rcvd FIS dma mem alloc fail"); 3964 /* error.. free the dma handle. */ 3965 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 3966 return (AHCI_FAILURE); 3967 } 3968 3969 if (ddi_dma_addr_bind_handle(ahci_portp->ahciport_rcvd_fis_dma_handle, 3970 NULL, 3971 (caddr_t)ahci_portp->ahciport_rcvd_fis, 3972 rcvd_fis_size, 3973 DDI_DMA_CONSISTENT, 3974 DDI_DMA_SLEEP, 3975 NULL, 3976 &ahci_portp->ahciport_rcvd_fis_dma_cookie, 3977 &cookie_count) != DDI_DMA_MAPPED) { 3978 3979 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 3980 "rcvd FIS dma handle bind fail"); 3981 /* error.. free the dma handle & free the memory. */ 3982 ddi_dma_mem_free(&ahci_portp->ahciport_rcvd_fis_acc_handle); 3983 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 3984 return (AHCI_FAILURE); 3985 } 3986 3987 bzero((void *)ahci_portp->ahciport_rcvd_fis, rcvd_fis_size); 3988 3989 /* Config Port Received FIS Base Address */ 3990 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 3991 (uint64_t *)AHCI_PORT_PxFB(ahci_ctlp, port), 3992 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_laddress); 3993 3994 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "64-bit, dma address: 0x%llx", 3995 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_laddress); 3996 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "32-bit, dma address: 0x%x", 3997 ahci_portp->ahciport_rcvd_fis_dma_cookie.dmac_address); 3998 3999 return (AHCI_SUCCESS); 4000 } 4001 4002 /* 4003 * Deallocates the Received FIS Structure 4004 * 4005 * WARNING!!! ahciport_mutex should be acquired before the function 4006 * is called. 4007 */ 4008 static void 4009 ahci_dealloc_rcvd_fis(ahci_port_t *ahci_portp) 4010 { 4011 /* Unbind the cmd list dma handle first. */ 4012 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_rcvd_fis_dma_handle); 4013 4014 /* Then free the underlying memory. */ 4015 ddi_dma_mem_free(&ahci_portp->ahciport_rcvd_fis_acc_handle); 4016 4017 /* Now free the handle itself. */ 4018 ddi_dma_free_handle(&ahci_portp->ahciport_rcvd_fis_dma_handle); 4019 } 4020 4021 /* 4022 * Allocates memory for the Command List, which contains up to 32 entries. 4023 * Each entry contains a command header, which is a 32-byte structure that 4024 * includes the pointer to the command table. 4025 * 4026 * WARNING!!! ahciport_mutex should be acquired before the function 4027 * is called. 4028 */ 4029 static int 4030 ahci_alloc_cmd_list(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 4031 uint8_t port) 4032 { 4033 size_t cmd_list_size; 4034 size_t ret_len; 4035 uint_t cookie_count; 4036 4037 cmd_list_size = 4038 ahci_ctlp->ahcictl_num_cmd_slots * sizeof (ahci_cmd_header_t); 4039 4040 /* allocate cmd list dma handle. */ 4041 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 4042 &ahci_ctlp->ahcictl_cmd_list_dma_attr, 4043 DDI_DMA_SLEEP, 4044 NULL, 4045 &ahci_portp->ahciport_cmd_list_dma_handle) != DDI_SUCCESS) { 4046 4047 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4048 "cmd list dma handle alloc failed"); 4049 return (AHCI_FAILURE); 4050 } 4051 4052 if (ddi_dma_mem_alloc(ahci_portp->ahciport_cmd_list_dma_handle, 4053 cmd_list_size, 4054 &accattr, 4055 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 4056 DDI_DMA_SLEEP, 4057 NULL, 4058 (caddr_t *)&ahci_portp->ahciport_cmd_list, 4059 &ret_len, 4060 &ahci_portp->ahciport_cmd_list_acc_handle) != NULL) { 4061 4062 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4063 "cmd list dma mem alloc fail"); 4064 /* error.. free the dma handle. */ 4065 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4066 return (AHCI_FAILURE); 4067 } 4068 4069 if (ddi_dma_addr_bind_handle(ahci_portp->ahciport_cmd_list_dma_handle, 4070 NULL, 4071 (caddr_t)ahci_portp->ahciport_cmd_list, 4072 cmd_list_size, 4073 DDI_DMA_CONSISTENT, 4074 DDI_DMA_SLEEP, 4075 NULL, 4076 &ahci_portp->ahciport_cmd_list_dma_cookie, 4077 &cookie_count) != DDI_DMA_MAPPED) { 4078 4079 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4080 "cmd list dma handle bind fail"); 4081 /* error.. free the dma handle & free the memory. */ 4082 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 4083 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4084 return (AHCI_FAILURE); 4085 } 4086 4087 bzero((void *)ahci_portp->ahciport_cmd_list, cmd_list_size); 4088 4089 /* Config Port Command List Base Address */ 4090 ddi_put64(ahci_ctlp->ahcictl_ahci_acc_handle, 4091 (uint64_t *)AHCI_PORT_PxCLB(ahci_ctlp, port), 4092 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_laddress); 4093 4094 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "64-bit, dma address: 0x%llx", 4095 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_laddress); 4096 4097 AHCIDBG1(AHCIDBG_INIT, ahci_ctlp, "32-bit, dma address: 0x%x", 4098 ahci_portp->ahciport_cmd_list_dma_cookie.dmac_address); 4099 4100 if (ahci_alloc_cmd_tables(ahci_ctlp, ahci_portp) != AHCI_SUCCESS) { 4101 goto err_out; 4102 } 4103 4104 return (AHCI_SUCCESS); 4105 4106 err_out: 4107 /* Unbind the cmd list dma handle first. */ 4108 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_cmd_list_dma_handle); 4109 4110 /* Then free the underlying memory. */ 4111 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 4112 4113 /* Now free the handle itself. */ 4114 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4115 4116 return (AHCI_FAILURE); 4117 } 4118 4119 /* 4120 * Deallocates the Command List 4121 * 4122 * WARNING!!! ahciport_mutex should be acquired before the function 4123 * is called. 4124 */ 4125 static void 4126 ahci_dealloc_cmd_list(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 4127 { 4128 /* First dealloc command table */ 4129 ahci_dealloc_cmd_tables(ahci_ctlp, ahci_portp); 4130 4131 /* Unbind the cmd list dma handle first. */ 4132 (void) ddi_dma_unbind_handle(ahci_portp->ahciport_cmd_list_dma_handle); 4133 4134 /* Then free the underlying memory. */ 4135 ddi_dma_mem_free(&ahci_portp->ahciport_cmd_list_acc_handle); 4136 4137 /* Now free the handle itself. */ 4138 ddi_dma_free_handle(&ahci_portp->ahciport_cmd_list_dma_handle); 4139 } 4140 4141 /* 4142 * Allocates memory for all Command Tables, which contains Command FIS, 4143 * ATAPI Command and Physical Region Descriptor Table. 4144 * 4145 * WARNING!!! ahciport_mutex should be acquired before the function 4146 * is called. 4147 */ 4148 static int 4149 ahci_alloc_cmd_tables(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 4150 { 4151 size_t ret_len; 4152 ddi_dma_cookie_t cmd_table_dma_cookie; 4153 uint_t cookie_count; 4154 int slot; 4155 4156 AHCIDBG1(AHCIDBG_INIT|AHCIDBG_ENTRY, ahci_ctlp, 4157 "ahci_alloc_cmd_tables: port %d enter", 4158 ahci_portp->ahciport_port_num); 4159 4160 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) { 4161 /* Allocate cmd table dma handle. */ 4162 if (ddi_dma_alloc_handle(ahci_ctlp->ahcictl_dip, 4163 &ahci_ctlp->ahcictl_cmd_table_dma_attr, 4164 DDI_DMA_SLEEP, 4165 NULL, 4166 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]) != 4167 DDI_SUCCESS) { 4168 4169 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4170 "cmd table dma handle alloc failed"); 4171 4172 goto err_out; 4173 } 4174 4175 if (ddi_dma_mem_alloc( 4176 ahci_portp->ahciport_cmd_tables_dma_handle[slot], 4177 ahci_cmd_table_size, 4178 &accattr, 4179 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 4180 DDI_DMA_SLEEP, 4181 NULL, 4182 (caddr_t *)&ahci_portp->ahciport_cmd_tables[slot], 4183 &ret_len, 4184 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]) != 4185 NULL) { 4186 4187 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4188 "cmd table dma mem alloc fail"); 4189 4190 /* error.. free the dma handle. */ 4191 ddi_dma_free_handle( 4192 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4193 goto err_out; 4194 } 4195 4196 if (ddi_dma_addr_bind_handle( 4197 ahci_portp->ahciport_cmd_tables_dma_handle[slot], 4198 NULL, 4199 (caddr_t)ahci_portp->ahciport_cmd_tables[slot], 4200 ahci_cmd_table_size, 4201 DDI_DMA_CONSISTENT, 4202 DDI_DMA_SLEEP, 4203 NULL, 4204 &cmd_table_dma_cookie, 4205 &cookie_count) != DDI_DMA_MAPPED) { 4206 4207 AHCIDBG0(AHCIDBG_INIT, ahci_ctlp, 4208 "cmd table dma handle bind fail"); 4209 /* error.. free the dma handle & free the memory. */ 4210 ddi_dma_mem_free( 4211 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 4212 ddi_dma_free_handle( 4213 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4214 goto err_out; 4215 } 4216 4217 bzero((void *)ahci_portp->ahciport_cmd_tables[slot], 4218 ahci_cmd_table_size); 4219 4220 /* Config Port Command Table Base Address */ 4221 SET_COMMAND_TABLE_BASE_ADDR( 4222 (&ahci_portp->ahciport_cmd_list[slot]), 4223 cmd_table_dma_cookie.dmac_laddress & 0xffffffffull); 4224 4225 #ifndef __lock_lint 4226 SET_COMMAND_TABLE_BASE_ADDR_UPPER( 4227 (&ahci_portp->ahciport_cmd_list[slot]), 4228 cmd_table_dma_cookie.dmac_laddress >> 32); 4229 #endif 4230 } 4231 4232 return (AHCI_SUCCESS); 4233 err_out: 4234 4235 for (slot--; slot >= 0; slot--) { 4236 /* Unbind the cmd table dma handle first */ 4237 (void) ddi_dma_unbind_handle( 4238 ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4239 4240 /* Then free the underlying memory */ 4241 ddi_dma_mem_free( 4242 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 4243 4244 /* Now free the handle itself */ 4245 ddi_dma_free_handle( 4246 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4247 } 4248 4249 return (AHCI_FAILURE); 4250 } 4251 4252 /* 4253 * Deallocates memory for all Command Tables. 4254 * 4255 * WARNING!!! ahciport_mutex should be acquired before the function 4256 * is called. 4257 */ 4258 static void 4259 ahci_dealloc_cmd_tables(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp) 4260 { 4261 int slot; 4262 4263 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 4264 "ahci_dealloc_cmd_tables: %d enter", 4265 ahci_portp->ahciport_port_num); 4266 4267 for (slot = 0; slot < ahci_ctlp->ahcictl_num_cmd_slots; slot++) { 4268 /* Unbind the cmd table dma handle first. */ 4269 (void) ddi_dma_unbind_handle( 4270 ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4271 4272 /* Then free the underlying memory. */ 4273 ddi_dma_mem_free( 4274 &ahci_portp->ahciport_cmd_tables_acc_handle[slot]); 4275 4276 /* Now free the handle itself. */ 4277 ddi_dma_free_handle( 4278 &ahci_portp->ahciport_cmd_tables_dma_handle[slot]); 4279 } 4280 } 4281 4282 /* 4283 * WARNING!!! ahciport_mutex should be acquired before the function 4284 * is called. 4285 */ 4286 static void 4287 ahci_update_sata_registers(ahci_ctl_t *ahci_ctlp, uint8_t port, 4288 sata_device_t *sd) 4289 { 4290 sd->satadev_scr.sstatus = 4291 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4292 (uint32_t *)(AHCI_PORT_PxSSTS(ahci_ctlp, port))); 4293 sd->satadev_scr.serror = 4294 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4295 (uint32_t *)(AHCI_PORT_PxSERR(ahci_ctlp, port))); 4296 sd->satadev_scr.scontrol = 4297 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4298 (uint32_t *)(AHCI_PORT_PxSCTL(ahci_ctlp, port))); 4299 sd->satadev_scr.sactive = 4300 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4301 (uint32_t *)(AHCI_PORT_PxSACT(ahci_ctlp, port))); 4302 } 4303 4304 /* 4305 * For poll mode, ahci_port_intr will be called to emulate the interrupt 4306 */ 4307 static void 4308 ahci_port_intr(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, uint8_t port) 4309 { 4310 uint32_t port_intr_status; 4311 uint32_t port_intr_enable; 4312 4313 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4314 "ahci_port_intr enter: port %d", port); 4315 4316 mutex_enter(&ahci_portp->ahciport_mutex); 4317 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_POLLING) { 4318 /* For SATA_OPMODE_POLLING commands */ 4319 port_intr_enable = 4320 (AHCI_INTR_STATUS_DHRS | 4321 AHCI_INTR_STATUS_PSS | 4322 AHCI_INTR_STATUS_SDBS | 4323 AHCI_INTR_STATUS_UFS | 4324 AHCI_INTR_STATUS_PCS | 4325 AHCI_INTR_STATUS_PRCS | 4326 AHCI_INTR_STATUS_OFS | 4327 AHCI_INTR_STATUS_INFS | 4328 AHCI_INTR_STATUS_IFS | 4329 AHCI_INTR_STATUS_HBDS | 4330 AHCI_INTR_STATUS_HBFS | 4331 AHCI_INTR_STATUS_TFES); 4332 mutex_exit(&ahci_portp->ahciport_mutex); 4333 goto next; 4334 } 4335 mutex_exit(&ahci_portp->ahciport_mutex); 4336 4337 /* 4338 * port_intr_enable indicates that the corresponding interrrupt 4339 * reporting is enabled. 4340 */ 4341 port_intr_enable = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4342 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port)); 4343 next: 4344 /* 4345 * port_intr_stats indicates that the corresponding interrupt 4346 * condition is active. 4347 */ 4348 port_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4349 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port)); 4350 4351 AHCIDBG3(AHCIDBG_INTR, ahci_ctlp, 4352 "ahci_port_intr: port %d, port_intr_status = 0x%x, " 4353 "port_intr_enable = 0x%x", 4354 port, port_intr_status, port_intr_enable); 4355 4356 port_intr_status &= port_intr_enable; 4357 4358 /* First clear the port interrupts status */ 4359 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4360 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port), 4361 port_intr_status); 4362 4363 /* Check the completed non-queued commands */ 4364 if (port_intr_status & (AHCI_INTR_STATUS_DHRS | 4365 AHCI_INTR_STATUS_PSS)) { 4366 (void) ahci_intr_cmd_cmplt(ahci_ctlp, 4367 ahci_portp, port); 4368 } 4369 4370 /* Check the completed queued commands */ 4371 if (port_intr_status & AHCI_INTR_STATUS_SDBS) { 4372 (void) ahci_intr_set_device_bits(ahci_ctlp, 4373 ahci_portp, port); 4374 } 4375 4376 /* Check the port connect change status interrupt bit */ 4377 if (port_intr_status & AHCI_INTR_STATUS_PCS) { 4378 (void) ahci_intr_port_connect_change(ahci_ctlp, 4379 ahci_portp, port); 4380 } 4381 4382 /* Check the device mechanical presence status interrupt bit */ 4383 if (port_intr_status & AHCI_INTR_STATUS_DMPS) { 4384 (void) ahci_intr_device_mechanical_presence_status( 4385 ahci_ctlp, ahci_portp, port); 4386 } 4387 4388 /* Check the PhyRdy change status interrupt bit */ 4389 if (port_intr_status & AHCI_INTR_STATUS_PRCS) { 4390 (void) ahci_intr_phyrdy_change(ahci_ctlp, ahci_portp, 4391 port); 4392 } 4393 4394 /* 4395 * Check the non-fatal error interrupt bits, there are three 4396 * kinds of non-fatal errors at the time being: 4397 * 4398 * PxIS.UFS - Unknown FIS Error 4399 * PxIS.OFS - Overflow Error 4400 * PxIS.INFS - Interface Non-Fatal Error 4401 * 4402 * For these non-fatal errors, the HBA can continue to operate, 4403 * so the driver just log the error messages. 4404 */ 4405 if (port_intr_status & (AHCI_INTR_STATUS_UFS | 4406 AHCI_INTR_STATUS_OFS | 4407 AHCI_INTR_STATUS_INFS)) { 4408 (void) ahci_intr_non_fatal_error(ahci_ctlp, ahci_portp, 4409 port, port_intr_status); 4410 } 4411 4412 /* 4413 * Check the fatal error interrupt bits, there are four kinds 4414 * of fatal errors for AHCI controllers: 4415 * 4416 * PxIS.HBFS - Host Bus Fatal Error 4417 * PxIS.HBDS - Host Bus Data Error 4418 * PxIS.IFS - Interface Fatal Error 4419 * PxIS.TFES - Task File Error 4420 * 4421 * The fatal error means the HBA can not recover from it by 4422 * itself, and it will try to abort the transfer, and the software 4423 * must intervene to restart the port. 4424 */ 4425 if (port_intr_status & (AHCI_INTR_STATUS_IFS | 4426 AHCI_INTR_STATUS_HBDS | 4427 AHCI_INTR_STATUS_HBFS | 4428 AHCI_INTR_STATUS_TFES)) 4429 (void) ahci_intr_fatal_error(ahci_ctlp, ahci_portp, 4430 port, port_intr_status); 4431 4432 /* Check the cold port detect interrupt bit */ 4433 if (port_intr_status & AHCI_INTR_STATUS_CPDS) { 4434 (void) ahci_intr_cold_port_detect(ahci_ctlp, ahci_portp, port); 4435 } 4436 4437 /* Second clear the corresponding bit in IS.IPS */ 4438 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4439 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp), (0x1 << port)); 4440 } 4441 4442 /* 4443 * Interrupt service handler 4444 */ 4445 static uint_t 4446 ahci_intr(caddr_t arg1, caddr_t arg2) 4447 { 4448 #ifndef __lock_lint 4449 _NOTE(ARGUNUSED(arg2)) 4450 #endif 4451 /* LINTED */ 4452 ahci_ctl_t *ahci_ctlp = (ahci_ctl_t *)arg1; 4453 ahci_port_t *ahci_portp; 4454 int32_t global_intr_status; 4455 uint8_t port; 4456 4457 /* 4458 * global_intr_status indicates that the corresponding port has 4459 * an interrupt pending. 4460 */ 4461 global_intr_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4462 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp)); 4463 4464 if (!(global_intr_status & ahci_ctlp->ahcictl_ports_implemented)) { 4465 /* The interrupt is not ours */ 4466 return (DDI_INTR_UNCLAIMED); 4467 } 4468 4469 /* Loop for all the ports */ 4470 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 4471 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 4472 continue; 4473 } 4474 if (!((0x1 << port) & global_intr_status)) { 4475 continue; 4476 } 4477 4478 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 4479 4480 /* Call ahci_port_intr */ 4481 ahci_port_intr(ahci_ctlp, ahci_portp, port); 4482 } 4483 4484 return (DDI_INTR_CLAIMED); 4485 } 4486 4487 /* 4488 * For non-queued commands, when the corresponding bit in the PxCI register 4489 * is cleared, it means the command is completed successfully. And according 4490 * to the HBA state machine, there are three conditions which possibly will 4491 * try to clear the PxCI register bit. 4492 * 1. Receive one D2H Register FIS which is with 'I' bit set 4493 * 2. Update PIO Setup FIS 4494 * 3. Transmit a command and receive R_OK if CTBA.C is set (software reset) 4495 * 4496 * Process completed non-queued commands when the interrupt status bit - 4497 * AHCI_INTR_STATUS_DHRS or AHCI_INTR_STATUS_PSS is set. 4498 * 4499 * AHCI_INTR_STATUS_DHRS means a D2H Register FIS has been received 4500 * with the 'I' bit set. And the following commands will send thus 4501 * FIS with 'I' bit set upon the successful completion: 4502 * 1. Non-data commands 4503 * 2. DMA data-in command 4504 * 3. DMA data-out command 4505 * 4. PIO data-out command 4506 * 5. PACKET non-data commands 4507 * 6. PACKET PIO data-in command 4508 * 7. PACKET PIO data-out command 4509 * 8. PACKET DMA data-in command 4510 * 9. PACKET DMA data-out command 4511 * 4512 * AHCI_INTR_STATUS_PSS means a PIO Setup FIS has been received 4513 * with the 'I' bit set. And the following commands will send this 4514 * FIS upon the successful completion: 4515 * 1. PIO data-in command 4516 */ 4517 static int 4518 ahci_intr_cmd_cmplt(ahci_ctl_t *ahci_ctlp, 4519 ahci_port_t *ahci_portp, uint8_t port) 4520 { 4521 uint32_t port_cmd_issue = 0; 4522 uint32_t finished_tags; 4523 int finished_slot; 4524 sata_pkt_t *satapkt; 4525 ahci_fis_d2h_register_t *rcvd_fisp; 4526 4527 mutex_enter(&ahci_portp->ahciport_mutex); 4528 4529 if (!ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && 4530 !NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 4531 /* 4532 * Spurious interrupt. Nothing to be done. 4533 */ 4534 mutex_exit(&ahci_portp->ahciport_mutex); 4535 return (AHCI_SUCCESS); 4536 } 4537 4538 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4539 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 4540 4541 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 4542 /* Slot 0 is always used during error recovery */ 4543 finished_tags = 0x1 & ~port_cmd_issue; 4544 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 4545 "ahci_intr_cmd_cmplt: port %d the sata pkt for error " 4546 "retrieval is finished, and finished_tags = 0x%x", 4547 port, finished_tags); 4548 } else { 4549 finished_tags = ahci_portp->ahciport_pending_tags & 4550 ~port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp); 4551 } 4552 4553 AHCIDBG3(AHCIDBG_INTR, ahci_ctlp, 4554 "ahci_intr_cmd_cmplt: pending_tags = 0x%x, " 4555 "port_cmd_issue = 0x%x finished_tags = 0x%x", 4556 ahci_portp->ahciport_pending_tags, port_cmd_issue, 4557 finished_tags); 4558 4559 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp) && 4560 (finished_tags == 0x1)) { 4561 satapkt = ahci_portp->ahciport_err_retri_pkt; 4562 ASSERT(satapkt != NULL); 4563 4564 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4565 "ahci_intr_cmd_cmplt: sending up pkt 0x%p " 4566 "with SATA_PKT_COMPLETED", (void *)satapkt); 4567 4568 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 4569 goto out; 4570 } 4571 4572 while (finished_tags) { 4573 finished_slot = ddi_ffs(finished_tags) - 1; 4574 if (finished_slot == -1) { 4575 goto out; 4576 } 4577 4578 satapkt = ahci_portp->ahciport_slot_pkts[finished_slot]; 4579 ASSERT(satapkt != NULL); 4580 4581 /* 4582 * For SATAC_SMART command with SATA_SMART_RETURN_STATUS 4583 * feature, sata_special_regs flag will be set, and the 4584 * driver should copy the status and the other corresponding 4585 * register values in the D2H Register FIS received (It's 4586 * working on Non-data protocol) from the device back to 4587 * the sata_cmd. 4588 * 4589 * For every AHCI port, there is only one Received FIS 4590 * structure, which contains the FISes received from the 4591 * device, So we're trying to copy the content of D2H 4592 * Register FIS in the Received FIS structure back to 4593 * the sata_cmd. 4594 */ 4595 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) { 4596 rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis-> 4597 ahcirf_d2h_register_fis); 4598 satapkt->satapkt_cmd.satacmd_status_reg = 4599 GET_RFIS_STATUS(rcvd_fisp); 4600 ahci_copy_out_regs(&satapkt->satapkt_cmd, rcvd_fisp); 4601 } 4602 4603 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 4604 "ahci_intr_cmd_cmplt: sending up pkt 0x%p " 4605 "with SATA_PKT_COMPLETED", (void *)satapkt); 4606 4607 CLEAR_BIT(ahci_portp->ahciport_pending_tags, finished_slot); 4608 CLEAR_BIT(finished_tags, finished_slot); 4609 ahci_portp->ahciport_slot_pkts[finished_slot] = NULL; 4610 4611 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 4612 } 4613 out: 4614 AHCIDBG1(AHCIDBG_PKTCOMP, ahci_ctlp, 4615 "ahci_intr_cmd_cmplt: pending_tags = 0x%x", 4616 ahci_portp->ahciport_pending_tags); 4617 4618 mutex_exit(&ahci_portp->ahciport_mutex); 4619 4620 return (AHCI_SUCCESS); 4621 } 4622 4623 /* 4624 * AHCI_INTR_STATUS_SDBS means a Set Device Bits FIS has been received 4625 * with the 'I' bit set and has been copied into system memory. It will 4626 * be sent under the following situations: 4627 * 4628 * 1. NCQ command is completed 4629 * 2. Asynchronous notification 4630 * 4631 * The completion of NCQ commands (READ/WRITE FPDMA QUEUED) is performed 4632 * via the Set Device Bits FIS. When such event is generated, the software 4633 * needs to read PxSACT register and compares the current value to the 4634 * list of commands previously issue by software. ahciport_pending_ncq_tags 4635 * keeps the tags of previously issued commands. 4636 * 4637 * Asynchronous Notification is a feature in SATA II, which allows an 4638 * ATAPI device to send a signal to the host when media is inserted or 4639 * removed and avoids polling the device for media changes. The signal 4640 * sent to the host is a Set Device Bits FIS with the 'I' and 'N' bits 4641 * set to '1'. At the moment, it's not supported yet. 4642 */ 4643 static int 4644 ahci_intr_set_device_bits(ahci_ctl_t *ahci_ctlp, 4645 ahci_port_t *ahci_portp, uint8_t port) 4646 { 4647 uint32_t port_sactive; 4648 uint32_t port_cmd_issue; 4649 uint32_t issued_tags; 4650 int issued_slot; 4651 uint32_t finished_tags; 4652 int finished_slot; 4653 sata_pkt_t *satapkt; 4654 4655 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4656 "ahci_intr_set_device_bits enter: port %d", port); 4657 4658 mutex_enter(&ahci_portp->ahciport_mutex); 4659 if (!NCQ_CMD_IN_PROGRESS(ahci_portp)) { 4660 mutex_exit(&ahci_portp->ahciport_mutex); 4661 return (AHCI_SUCCESS); 4662 } 4663 4664 /* 4665 * First the handler got which commands are finished by checking 4666 * PxSACT register 4667 */ 4668 port_sactive = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4669 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 4670 4671 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 4672 ~port_sactive & AHCI_NCQ_SLOT_MASK(ahci_portp); 4673 4674 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4675 "ahci_intr_set_device_bits: port %d pending_ncq_tags = 0x%x " 4676 "port_sactive = 0x%x", port, 4677 ahci_portp->ahciport_pending_ncq_tags, port_sactive); 4678 4679 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4680 "ahci_intr_set_device_bits: finished_tags = 0x%x", finished_tags); 4681 4682 /* 4683 * For NCQ commands, the software can determine which command has 4684 * already been transmitted to the device by checking PxCI register. 4685 */ 4686 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4687 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 4688 4689 issued_tags = ahci_portp->ahciport_pending_tags & 4690 ~port_cmd_issue & AHCI_SLOT_MASK(ahci_ctlp); 4691 4692 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4693 "ahci_intr_set_device_bits: port %d pending_tags = 0x%x " 4694 "port_cmd_issue = 0x%x", port, 4695 ahci_portp->ahciport_pending_tags, port_cmd_issue); 4696 4697 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4698 "ahci_intr_set_device_bits: issued_tags = 0x%x", issued_tags); 4699 4700 /* 4701 * Clear ahciport_pending_tags bit when the corresponding command 4702 * is already sent down to the device. 4703 */ 4704 while (issued_tags) { 4705 issued_slot = ddi_ffs(issued_tags) - 1; 4706 if (issued_slot == -1) { 4707 goto next; 4708 } 4709 CLEAR_BIT(ahci_portp->ahciport_pending_tags, issued_slot); 4710 CLEAR_BIT(issued_tags, issued_slot); 4711 } 4712 4713 next: 4714 while (finished_tags) { 4715 finished_slot = ddi_ffs(finished_tags) - 1; 4716 if (finished_slot == -1) { 4717 goto out; 4718 } 4719 4720 /* The command is certainly transmitted to the device */ 4721 ASSERT(!(ahci_portp->ahciport_pending_tags & 4722 (0x1 << finished_slot))); 4723 4724 satapkt = ahci_portp->ahciport_slot_pkts[finished_slot]; 4725 ASSERT(satapkt != NULL); 4726 4727 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_NCQ, ahci_ctlp, 4728 "ahci_intr_set_device_bits: sending up pkt 0x%p " 4729 "with SATA_PKT_COMPLETED", (void *)satapkt); 4730 4731 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, finished_slot); 4732 CLEAR_BIT(finished_tags, finished_slot); 4733 ahci_portp->ahciport_slot_pkts[finished_slot] = NULL; 4734 4735 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 4736 } 4737 out: 4738 AHCIDBG3(AHCIDBG_PKTCOMP|AHCIDBG_NCQ, ahci_ctlp, 4739 "ahci_intr_set_device_bits: port %d " 4740 "pending_ncq_tags = 0x%x pending_tags = 0x%x", 4741 port, ahci_portp->ahciport_pending_ncq_tags, 4742 ahci_portp->ahciport_pending_tags); 4743 4744 mutex_exit(&ahci_portp->ahciport_mutex); 4745 4746 return (AHCI_SUCCESS); 4747 } 4748 4749 /* 4750 * 1=Change in Current Connect Status. 0=No change in Current Connect Status. 4751 * This bit reflects the state of PxSERR.DIAG.X. This bit is only cleared 4752 * when PxSERR.DIAG.X is cleared. When PxSERR.DIAG.X is set to one, it 4753 * indicates a COMINIT signal was received. 4754 * 4755 * Hot plug insertion is detected by reception of a COMINIT signal from the 4756 * device. On reception of unsolicited COMINIT, the HBA shall generate a 4757 * COMRESET. If the COMINIT is in responce to a COMRESET, then the HBA shall 4758 * begin the normal communication negotiation sequence as outlined in the 4759 * Serial ATA 1.0a specification. When a COMRESET is sent to the device the 4760 * PxSSTS.DET field shall be cleared to 0h. When a COMINIT is received, the 4761 * PxSSTS.DET field shall be set to 1h. When the communication negotiation 4762 * sequence is complete and PhyRdy is true the PxSSTS.DET field shall be set 4763 * to 3h. Therefore, at the moment the ahci driver is going to check PhyRdy 4764 * to handle hot plug insertion. In this interrupt handler, just do nothing 4765 * but print some log message and clear the bit. 4766 */ 4767 static int 4768 ahci_intr_port_connect_change(ahci_ctl_t *ahci_ctlp, 4769 ahci_port_t *ahci_portp, uint8_t port) 4770 { 4771 #if AHCI_DEBUG 4772 uint32_t port_serror; 4773 #endif 4774 4775 mutex_enter(&ahci_portp->ahciport_mutex); 4776 4777 #if AHCI_DEBUG 4778 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4779 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 4780 4781 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4782 "ahci_intr_port_connect_change: port %d, " 4783 "port_serror = 0x%x", port, port_serror); 4784 #endif 4785 4786 /* Clear PxSERR.DIAG.X to clear the interrupt bit */ 4787 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4788 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 4789 SERROR_EXCHANGED_ERR); 4790 4791 mutex_exit(&ahci_portp->ahciport_mutex); 4792 4793 return (AHCI_SUCCESS); 4794 } 4795 4796 /* 4797 * Hot Plug Operation for platforms that support Mechanical Presence 4798 * Switches. 4799 * 4800 * When set, it indicates that a mechanical presence switch attached to this 4801 * port has been opened or closed, which may lead to a change in the connection 4802 * state of the device. This bit is only valid if both CAP.SMPS and PxCMD.MPSP 4803 * are set to '1'. 4804 * 4805 * At the moment, this interrupt is not needed and disabled and we just log 4806 * the debug message. 4807 */ 4808 static int 4809 ahci_intr_device_mechanical_presence_status(ahci_ctl_t *ahci_ctlp, 4810 ahci_port_t *ahci_portp, uint8_t port) 4811 { 4812 uint32_t cap_status, port_cmd_status; 4813 4814 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4815 "ahci_intr_device_mechanical_presence_status enter, " 4816 "port %d", port); 4817 4818 cap_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4819 (uint32_t *)AHCI_GLOBAL_CAP(ahci_ctlp)); 4820 4821 mutex_enter(&ahci_portp->ahciport_mutex); 4822 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4823 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 4824 4825 if (!(cap_status & AHCI_HBA_CAP_SMPS) || 4826 !(port_cmd_status & AHCI_CMD_STATUS_MPSP)) { 4827 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4828 "CAP.SMPS or PxCMD.MPSP is not set, so just ignore " 4829 "the interrupt: cap_status = 0x%x, " 4830 "port_cmd_status = 0x%x", cap_status, port_cmd_status); 4831 mutex_exit(&ahci_portp->ahciport_mutex); 4832 4833 return (AHCI_SUCCESS); 4834 } 4835 4836 #if AHCI_DEBUG 4837 if (port_cmd_status & AHCI_CMD_STATUS_MPSS) { 4838 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4839 "The mechanical presence switch is open: " 4840 "port %d, port_cmd_status = 0x%x", 4841 port, port_cmd_status); 4842 } else { 4843 AHCIDBG2(AHCIDBG_INTR, ahci_ctlp, 4844 "The mechanical presence switch is close: " 4845 "port %d, port_cmd_status = 0x%x", 4846 port, port_cmd_status); 4847 } 4848 #endif 4849 4850 mutex_exit(&ahci_portp->ahciport_mutex); 4851 4852 return (AHCI_SUCCESS); 4853 } 4854 4855 /* 4856 * Native Hot Plug Support. 4857 * 4858 * When set, it indicates that the internal PHYRDY signal changed state. 4859 * This bit reflects the state of PxSERR.DIAG.N. 4860 * 4861 * There are three kinds of conditions to generate this interrupt event: 4862 * 1. a device is inserted 4863 * 2. a device is disconnected 4864 * 3. when the link enters/exits a Partial or Slumber interface power 4865 * management state 4866 * 4867 * If inteface power management is enabled for a port, the PxSERR.DIAG.N 4868 * bit may be set due to the link entering the Partial or Slumber power 4869 * management state, rather than due to a hot plug insertion or removal 4870 * event. So far, the interface power management is disabled, so the 4871 * driver can reliably get removal detection notification via the 4872 * PxSERR.DIAG.N bit. 4873 */ 4874 static int 4875 ahci_intr_phyrdy_change(ahci_ctl_t *ahci_ctlp, 4876 ahci_port_t *ahci_portp, uint8_t port) 4877 { 4878 uint32_t port_sstatus = 0; /* No dev present & PHY not established. */ 4879 sata_device_t sdevice; 4880 int dev_exists_now = 0; 4881 int dev_existed_previously = 0; 4882 4883 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ENTRY, ahci_ctlp, 4884 "ahci_intr_phyrdy_change enter, port %d", port); 4885 4886 /* Clear PxSERR.DIAG.N to clear the interrupt bit */ 4887 mutex_enter(&ahci_portp->ahciport_mutex); 4888 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 4889 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 4890 SERROR_PHY_RDY_CHG); 4891 mutex_exit(&ahci_portp->ahciport_mutex); 4892 4893 mutex_enter(&ahci_ctlp->ahcictl_mutex); 4894 if ((ahci_ctlp->ahcictl_sata_hba_tran == NULL) || 4895 (ahci_portp == NULL)) { 4896 /* The whole controller setup is not yet done. */ 4897 mutex_exit(&ahci_ctlp->ahcictl_mutex); 4898 return (AHCI_SUCCESS); 4899 } 4900 mutex_exit(&ahci_ctlp->ahcictl_mutex); 4901 4902 mutex_enter(&ahci_portp->ahciport_mutex); 4903 4904 /* SStatus tells the presence of device. */ 4905 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 4906 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 4907 4908 if (SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_PHYCOM) { 4909 dev_exists_now = 1; 4910 } 4911 4912 if (ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) { 4913 dev_existed_previously = 1; 4914 } 4915 4916 if (ahci_portp->ahciport_flags & AHCI_PORT_FLAG_NODEV) { 4917 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_NODEV; 4918 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 4919 "ahci_intr_phyrdy_change: port %d " 4920 "AHCI_PORT_FLAG_NODEV is cleared", port); 4921 if (dev_exists_now == 0) 4922 dev_existed_previously = 1; 4923 } 4924 4925 bzero((void *)&sdevice, sizeof (sata_device_t)); 4926 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 4927 sdevice.satadev_addr.qual = SATA_ADDR_CPORT; 4928 sdevice.satadev_addr.pmport = 0; 4929 sdevice.satadev_state = SATA_PSTATE_PWRON; 4930 ahci_portp->ahciport_port_state = SATA_PSTATE_PWRON; 4931 4932 if (dev_exists_now) { 4933 if (dev_existed_previously) { 4934 /* Things are fine now. The loss was temporary. */ 4935 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 4936 "ahci_intr_phyrdy_change port %d " 4937 "device link lost/established", port); 4938 4939 mutex_exit(&ahci_portp->ahciport_mutex); 4940 sata_hba_event_notify( 4941 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 4942 &sdevice, 4943 SATA_EVNT_LINK_LOST|SATA_EVNT_LINK_ESTABLISHED); 4944 mutex_enter(&ahci_portp->ahciport_mutex); 4945 4946 } else { 4947 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 4948 "ahci_intr_phyrdy_change: port %d " 4949 "device link established", port); 4950 4951 /* A new device has been detected. */ 4952 ahci_find_dev_signature(ahci_ctlp, ahci_portp, port); 4953 4954 /* Try to start the port */ 4955 if (ahci_start_port(ahci_ctlp, ahci_portp, port) 4956 != AHCI_SUCCESS) { 4957 sdevice.satadev_state |= SATA_PSTATE_FAILED; 4958 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 4959 "ahci_intr_phyrdy_change: port %d failed " 4960 "at start port", port); 4961 } 4962 4963 /* Clear the max queue depth for inserted device */ 4964 ahci_portp->ahciport_max_ncq_tags = 0; 4965 4966 mutex_exit(&ahci_portp->ahciport_mutex); 4967 sata_hba_event_notify( 4968 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 4969 &sdevice, 4970 SATA_EVNT_LINK_ESTABLISHED); 4971 mutex_enter(&ahci_portp->ahciport_mutex); 4972 4973 } 4974 } else { /* No device exists now */ 4975 4976 if (dev_existed_previously) { 4977 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 4978 "ahci_intr_phyrdy_change: port %d " 4979 "device link lost", port); 4980 4981 ahci_reject_all_abort_pkts(ahci_ctlp, ahci_portp, port); 4982 (void) ahci_put_port_into_notrunning_state(ahci_ctlp, 4983 ahci_portp, port); 4984 4985 /* An existing device is lost. */ 4986 ahci_portp->ahciport_device_type = SATA_DTYPE_NONE; 4987 4988 mutex_exit(&ahci_portp->ahciport_mutex); 4989 sata_hba_event_notify( 4990 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 4991 &sdevice, 4992 SATA_EVNT_LINK_LOST); 4993 mutex_enter(&ahci_portp->ahciport_mutex); 4994 } 4995 } 4996 4997 mutex_exit(&ahci_portp->ahciport_mutex); 4998 4999 return (AHCI_SUCCESS); 5000 } 5001 5002 /* 5003 * PxIS.UFS - Unknown FIS Error 5004 * 5005 * This interrupt event means an unknown FIS was received and has been 5006 * copied into system memory. An unknown FIS is not considered an illegal 5007 * FIS, unless the length received is more than 64 bytes. If an unknown 5008 * FIS arrives with length <= 64 bytes, it is posted and the HBA continues 5009 * normal operation. If the unknown FIS is more than 64 bytes, then it 5010 * won't be posted to memory and PxSERR.ERR.P will be set, which is then 5011 * a fatal error. 5012 * 5013 * PxIS.OFS - Overflow Error 5014 * 5015 * Command list overflow is defined as software building a command table 5016 * that has fewer total bytes than the transaction given to the device. 5017 * On device writes, the HBA will run out of data, and on reads, there 5018 * will be no room to put the data. 5019 * 5020 * For an overflow on data read, either PIO or DMA, the HBA will set 5021 * PxIS.OFS, and the HBA will do a best effort to continue, and it's a 5022 * non-fatal error when the HBA can continues. Sometimes, it will cause 5023 * a fatal error and need the software to do something. 5024 * 5025 * For an overflow on data write, setting PxIS.OFS is optional for both 5026 * DMA and PIO, and it's a fatal error, and a COMRESET is required by 5027 * software to clean up from this serious error. 5028 * 5029 * PxIS.INFS - Interface Non-Fatal Error 5030 * 5031 * This interrupt event indicates that the HBA encountered an error on 5032 * the Serial ATA interface but was able to continue operation. The kind 5033 * of error usually occurred during a non-Data FIS, and under this condition 5034 * the FIS will be re-transmitted by HBA automatically. 5035 * 5036 * When the FMA is implemented, there should be a stat structure to 5037 * record how many every kind of error happens. 5038 */ 5039 static int 5040 ahci_intr_non_fatal_error(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 5041 uint8_t port, uint32_t intr_status) 5042 { 5043 uint32_t port_serror; 5044 #if AHCI_DEBUG 5045 uint32_t port_cmd_status; 5046 uint32_t port_cmd_issue; 5047 uint32_t port_sactive; 5048 int current_slot; 5049 uint32_t current_tags; 5050 sata_pkt_t *satapkt; 5051 #endif 5052 5053 mutex_enter(&ahci_portp->ahciport_mutex); 5054 5055 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5056 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 5057 5058 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ENTRY|AHCIDBG_ERRS, ahci_ctlp, 5059 "ahci_intr_non_fatal_error: port %d, " 5060 "port_serror = 0x%x", port, port_serror); 5061 5062 ahci_log_serror_message(ahci_ctlp, port, port_serror, 1); 5063 5064 if (intr_status & AHCI_INTR_STATUS_UFS) { 5065 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 5066 "ahci port %d has unknown FIS error", port); 5067 5068 /* Clear the interrupt bit by clearing PxSERR.DIAG.F */ 5069 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5070 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 5071 SERROR_FIS_TYPE); 5072 } 5073 5074 #if AHCI_DEBUG 5075 if (intr_status & AHCI_INTR_STATUS_OFS) { 5076 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5077 "ahci port %d has overflow error", port); 5078 } 5079 5080 if (intr_status & AHCI_INTR_STATUS_INFS) { 5081 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5082 "ahci port %d has interface non fatal error", port); 5083 } 5084 5085 /* 5086 * Record the error occurred command's slot. 5087 */ 5088 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 5089 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 5090 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5091 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5092 5093 current_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 5094 AHCI_CMD_STATUS_CCS_SHIFT; 5095 5096 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 5097 satapkt = ahci_portp->ahciport_err_retri_pkt; 5098 ASSERT(satapkt != NULL); 5099 ASSERT(current_slot == 0); 5100 } else { 5101 satapkt = ahci_portp->ahciport_slot_pkts[current_slot]; 5102 } 5103 5104 if (satapkt != NULL) { 5105 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5106 "ahci_intr_non_fatal_error: pending_tags = 0x%x " 5107 "cmd 0x%x", ahci_portp->ahciport_pending_tags, 5108 satapkt->satapkt_cmd.satacmd_cmd_reg); 5109 5110 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5111 "ahci_intr_non_fatal_error: port %d, " 5112 "satapkt 0x%p is being processed when error occurs", 5113 port, (void *)satapkt); 5114 } 5115 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 5116 /* 5117 * For queued command, list those command which have already 5118 * been transmitted to the device and still not completed. 5119 */ 5120 port_sactive = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5121 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 5122 5123 port_cmd_issue = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5124 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 5125 5126 AHCIDBG3(AHCIDBG_INTR|AHCIDBG_NCQ|AHCIDBG_ERRS, ahci_ctlp, 5127 "ahci_intr_non_fatal_error: pending_ncq_tags = 0x%x " 5128 "port_sactive = 0x%x port_cmd_issue = 0x%x", 5129 ahci_portp->ahciport_pending_ncq_tags, 5130 port_sactive, port_cmd_issue); 5131 5132 current_tags = ahci_portp->ahciport_pending_ncq_tags & 5133 port_sactive & ~port_cmd_issue & 5134 AHCI_NCQ_SLOT_MASK(ahci_portp); 5135 5136 while (current_tags) { 5137 current_slot = ddi_ffs(current_tags) - 1; 5138 if (current_slot == -1) { 5139 goto out; 5140 } 5141 5142 satapkt = ahci_portp->ahciport_slot_pkts[current_slot]; 5143 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_NCQ|AHCIDBG_ERRS, 5144 ahci_ctlp, "ahci_intr_non_fatal_error: " 5145 "port %d, satapkt 0x%p is outstanding when " 5146 "error occurs", port, (void *)satapkt); 5147 } 5148 } 5149 out: 5150 #endif 5151 mutex_exit(&ahci_portp->ahciport_mutex); 5152 5153 return (AHCI_SUCCESS); 5154 } 5155 5156 /* 5157 * According to the AHCI spec, the error types include system memory 5158 * errors, interface errors, port multiplier errors, device errors, 5159 * command list overflow, command list underflow, native command 5160 * queuing tag errors and pio data transfer errors. 5161 * 5162 * System memory errors such as target abort, master abort, and parity 5163 * may cause the host to stop, and they are serious errors and needed 5164 * to be recovered with software intervention. When system software 5165 * has given a pointer to the HBA that doesn't exist in physical memory, 5166 * a master/target abort error occurs, and PxIS.HBFS will be set. A 5167 * data error such as CRC or parity occurs, the HBA aborts the transfer 5168 * (if necessary) and PxIS.HBDS will be set. 5169 * 5170 * Interface errors are errors that occur due to electrical issues on 5171 * the interface, or protocol miscommunication between the device and 5172 * HBA, and the respective PxSERR register bit will be set. And PxIS.IFS 5173 * (fatal) or PxIS.INFS (non-fatal) will be set. The conditions that 5174 * causes PxIS.IFS/PxIS.INFS to be set are 5175 * 1. in PxSERR.ERR, P bit is set to '1' 5176 * 2. in PxSERR.DIAG, C or H bit is set to '1' 5177 * 3. PhyRdy drop unexpectly, N bit is set to '1' 5178 * If the error occurred during a non-data FIS, the FIS must be 5179 * retransmitted, and the error is non-fatal and PxIS.INFS is set. If 5180 * the error occurred during a data FIS, the transfer will stop, so 5181 * the error is fatal and PxIS.IFS is set. 5182 * 5183 * When a FIS arrives that updates the taskfile, the HBA checks to see 5184 * if PxTFD.STS.ERR is set. If yes, PxIS.TFES will be set and the HBA 5185 * stops processing any more commands. 5186 * 5187 * Command list overflow is defined as software building a command table 5188 * that has fewer total bytes than the transaction given to the device. 5189 * On device writes, the HBA will run out of data, and on reads, there 5190 * will be no room to put the data. For an overflow on data read, either 5191 * PIO or DMA, the HBA will set PxIS.OFS, and it's a non-fatal error. 5192 * For an overflow on data write, setting PxIS.OFS is optional for both 5193 * DMA and PIO, and a COMRESET is required by software to clean up from 5194 * this serious error. 5195 * 5196 * Command list underflow is defined as software building a command 5197 * table that has more total bytes than the transaction given to the 5198 * device. For data writes, both PIO and DMA, the device will detect 5199 * an error and end the transfer. And these errors are most likely going 5200 * to be fatal errors that will cause the port to be restarted. For 5201 * data reads, the HBA updates its PRD byte count, and may be 5202 * able to continue normally, but is not required to. And The HBA is 5203 * not required to detect underflow conditions for native command 5204 * queuing command. 5205 * 5206 * The HBA does not actively check incoming DMA Setup FISes to ensure 5207 * that the PxSACT register bit for that slot is set. Existing error 5208 * mechanisms, such as host bus failure, or bad protocol, are used to 5209 * recover from this case. 5210 * 5211 * In accordance with Serial ATA 1.0a, DATA FISes prior to the final 5212 * DATA FIS must be an integral number of Dwords. If the HBA receives 5213 * a request which is not an integral number of Dwords, the HBA 5214 * set PxSERR.ERR.P to '1', set PxIS.IFS to '1' and stop running until 5215 * software restarts the port. And the HBA ensures that the size 5216 * of the DATA FIS received during a PIO command matches the size in 5217 * the Transfer Cound field of the preceding PIO Setup FIS, if not, the 5218 * HBA sets PxSERR.ERR.P to '1', set PxIS.IFS to '1', and then 5219 * stop running until software restarts the port. 5220 */ 5221 /* 5222 * the fatal errors include PxIS.IFS, PxIS.HBDS, PxIS.HBFS and PxIS.TFES. 5223 * 5224 * PxIS.IFS indicates that the hba encountered an error on the serial ata 5225 * interface which caused the transfer to stop. 5226 * 5227 * PxIS.HBDS indicates that the hba encountered a data error 5228 * (uncorrectable ecc/parity) when reading from or writing to system memory. 5229 * 5230 * PxIS.HBFS indicates that the hba encountered a host bus error that it 5231 * cannot recover from, such as a bad software pointer. 5232 * 5233 * PxIS.TFES is set whenever the status register is updated by the device 5234 * and the error bit (bit 0) is set. 5235 */ 5236 static int 5237 ahci_intr_fatal_error(ahci_ctl_t *ahci_ctlp, 5238 ahci_port_t *ahci_portp, uint8_t port, uint32_t intr_status) 5239 { 5240 uint32_t port_cmd_status; 5241 uint32_t port_serror; 5242 uint32_t task_file_status; 5243 int failed_slot; 5244 sata_pkt_t *spkt = NULL; 5245 uint8_t err_byte; 5246 ahci_event_arg_t *args; 5247 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 5248 5249 mutex_enter(&ahci_portp->ahciport_mutex); 5250 5251 /* 5252 * ahci_intr_phyrdy_change() may have rendered it to 5253 * SATA_DTYPE_NONE. 5254 */ 5255 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 5256 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 5257 "ahci_intr_fatal_error: port %d no device attached, " 5258 "and just return without doing anything", port); 5259 goto out0; 5260 } 5261 5262 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 5263 /* 5264 * Read PxCMD.CCS to determine the slot that the HBA 5265 * was processing when the error occurred. 5266 */ 5267 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5268 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5269 failed_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 5270 AHCI_CMD_STATUS_CCS_SHIFT; 5271 5272 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 5273 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5274 "ahci_intr_fatal_error: spkt 0x%p is being processed when " 5275 "fatal error occurred for port %d", spkt, port); 5276 5277 if (intr_status & AHCI_INTR_STATUS_TFES) { 5278 task_file_status = ddi_get32( 5279 ahci_ctlp->ahcictl_ahci_acc_handle, 5280 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 5281 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_ERRS, ahci_ctlp, 5282 "ahci_intr_fatal_error: port %d " 5283 "task_file_status = 0x%x", port, task_file_status); 5284 5285 err_byte = (task_file_status & AHCI_TFD_ERR_MASK) 5286 >> AHCI_TFD_ERR_SHIFT; 5287 5288 /* 5289 * Won't emit the error message if it is an IDENTIFY 5290 * DEVICE command sent to an ATAPI device. 5291 */ 5292 if ((spkt != NULL) && 5293 (spkt->satapkt_cmd.satacmd_cmd_reg == 5294 SATAC_ID_DEVICE) && 5295 (err_byte == SATA_ERROR_ABORT)) 5296 goto out1; 5297 5298 /* 5299 * Won't emit the error message if it is an ATAPI PACKET 5300 * command 5301 */ 5302 if ((spkt != NULL) && 5303 (spkt->satapkt_cmd.satacmd_cmd_reg == SATAC_PACKET)) 5304 goto out1; 5305 } 5306 } 5307 5308 ahci_log_fatal_error_message(ahci_ctlp, port, intr_status); 5309 port_serror = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5310 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port)); 5311 ahci_log_serror_message(ahci_ctlp, port, port_serror, 0); 5312 out1: 5313 /* Prepare the argument for the taskq */ 5314 args = ahci_portp->ahciport_event_args; 5315 args->ahciea_ctlp = (void *)ahci_ctlp; 5316 args->ahciea_portp = (void *)ahci_portp; 5317 args->ahciea_event = intr_status; 5318 5319 /* Start the taskq to handle error recovery */ 5320 if ((ddi_taskq_dispatch(ahci_ctlp->ahcictl_event_taskq, 5321 ahci_events_handler, 5322 (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) { 5323 cmn_err(CE_WARN, "!ahci%d: ahci start taskq for event handler " 5324 "failed", instance); 5325 } 5326 out0: 5327 mutex_exit(&ahci_portp->ahciport_mutex); 5328 5329 return (AHCI_SUCCESS); 5330 } 5331 5332 /* 5333 * Hot Plug Operation for platforms that support Cold Presence Detect. 5334 * 5335 * When set, a device status has changed as detected by the cold presence 5336 * detect logic. This bit can either be set due to a non-connected port 5337 * receiving a device, or a connected port having its device removed. 5338 * This bit is only valid if the port supports cold presence detect as 5339 * indicated by PxCMD.CPD set to '1'. 5340 * 5341 * At the moment, this interrupt is not needed and disabled and we just 5342 * log the debug message. 5343 */ 5344 static int 5345 ahci_intr_cold_port_detect(ahci_ctl_t *ahci_ctlp, 5346 ahci_port_t *ahci_portp, uint8_t port) 5347 { 5348 uint32_t port_cmd_status; 5349 sata_device_t sdevice; 5350 5351 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5352 "ahci_intr_cold_port_detect enter, port %d", port); 5353 5354 mutex_enter(&ahci_portp->ahciport_mutex); 5355 5356 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5357 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5358 if (!(port_cmd_status & AHCI_CMD_STATUS_CPD)) { 5359 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5360 "port %d does not support cold presence detect, so " 5361 "we just ignore this interrupt", port); 5362 mutex_exit(&ahci_portp->ahciport_mutex); 5363 return (AHCI_SUCCESS); 5364 } 5365 5366 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5367 "port %d device status has changed", port); 5368 5369 bzero((void *)&sdevice, sizeof (sata_device_t)); 5370 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 5371 sdevice.satadev_addr.qual = SATA_ADDR_CPORT; 5372 sdevice.satadev_addr.pmport = 0; 5373 sdevice.satadev_state = SATA_PSTATE_PWRON; 5374 5375 if (port_cmd_status & AHCI_CMD_STATUS_CPS) { 5376 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5377 "port %d: a device is hot plugged", port); 5378 mutex_exit(&ahci_portp->ahciport_mutex); 5379 sata_hba_event_notify( 5380 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5381 &sdevice, 5382 SATA_EVNT_DEVICE_ATTACHED); 5383 mutex_enter(&ahci_portp->ahciport_mutex); 5384 5385 } else { 5386 AHCIDBG1(AHCIDBG_INTR, ahci_ctlp, 5387 "port %d: a device is hot unplugged", port); 5388 mutex_exit(&ahci_portp->ahciport_mutex); 5389 sata_hba_event_notify( 5390 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5391 &sdevice, 5392 SATA_EVNT_DEVICE_DETACHED); 5393 mutex_enter(&ahci_portp->ahciport_mutex); 5394 } 5395 5396 mutex_exit(&ahci_portp->ahciport_mutex); 5397 5398 return (AHCI_SUCCESS); 5399 } 5400 5401 /* 5402 * Enable the interrupts for a particular port. 5403 * 5404 * WARNING!!! ahciport_mutex should be acquired before the function 5405 * is called. 5406 */ 5407 static void 5408 ahci_enable_port_intrs(ahci_ctl_t *ahci_ctlp, uint8_t port) 5409 { 5410 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5411 "ahci_enable_port_intrs enter, port %d", port); 5412 5413 /* 5414 * Clear port interrupt status before enabling interrupt 5415 */ 5416 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5417 (uint32_t *)AHCI_PORT_PxIS(ahci_ctlp, port), 5418 AHCI_PORT_INTR_MASK); 5419 5420 /* 5421 * Clear the pending bit from IS.IPS 5422 */ 5423 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5424 (uint32_t *)AHCI_GLOBAL_IS(ahci_ctlp), (1 << port)); 5425 5426 /* 5427 * Enable the following interrupts: 5428 * Device to Host Register FIS Interrupt (DHRS) 5429 * PIO Setup FIS Interrupt (PSS) 5430 * Set Device Bits Interrupt (SDBS) 5431 * Unknown FIS Interrupt (UFS) 5432 * Port Connect Change Status (PCS) 5433 * PhyRdy Change Status (PRCS) 5434 * Overflow Status (OFS) 5435 * Interface Non-fatal Error Status (INFS) 5436 * Interface Fatal Error Status (IFS) 5437 * Host Bus Data Error Status (HBDS) 5438 * Host Bus Fatal Error Status (HBFS) 5439 * Task File Error Status (TFES) 5440 */ 5441 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5442 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), 5443 (AHCI_INTR_STATUS_DHRS | 5444 AHCI_INTR_STATUS_PSS | 5445 AHCI_INTR_STATUS_SDBS | 5446 AHCI_INTR_STATUS_UFS | 5447 AHCI_INTR_STATUS_DPS | 5448 AHCI_INTR_STATUS_PCS | 5449 AHCI_INTR_STATUS_PRCS | 5450 AHCI_INTR_STATUS_OFS | 5451 AHCI_INTR_STATUS_INFS | 5452 AHCI_INTR_STATUS_IFS | 5453 AHCI_INTR_STATUS_HBDS | 5454 AHCI_INTR_STATUS_HBFS | 5455 AHCI_INTR_STATUS_TFES)); 5456 } 5457 5458 /* 5459 * Enable interrupts for all the ports. 5460 * 5461 * WARNING!!! ahcictl_mutex should be acquired before the function 5462 * is called. 5463 */ 5464 static void 5465 ahci_enable_all_intrs(ahci_ctl_t *ahci_ctlp) 5466 { 5467 uint32_t ghc_control; 5468 5469 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_enable_all_intrs enter"); 5470 5471 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5472 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 5473 5474 ghc_control |= AHCI_HBA_GHC_IE; 5475 5476 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5477 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 5478 } 5479 5480 /* 5481 * Disable interrupts for a particular port. 5482 * 5483 * WARNING!!! ahciport_mutex should be acquired before the function 5484 * is called. 5485 */ 5486 static void 5487 ahci_disable_port_intrs(ahci_ctl_t *ahci_ctlp, uint8_t port) 5488 { 5489 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5490 "ahci_disable_port_intrs enter, port %d", port); 5491 5492 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5493 (uint32_t *)AHCI_PORT_PxIE(ahci_ctlp, port), 0); 5494 } 5495 5496 /* 5497 * Disable interrupts for the whole HBA. 5498 * 5499 * The global bit is cleared, then all interrupt sources from all 5500 * ports are disabled. 5501 * 5502 * WARNING!!! ahcictl_mutex should be acquired before the function 5503 * is called. 5504 */ 5505 static void 5506 ahci_disable_all_intrs(ahci_ctl_t *ahci_ctlp) 5507 { 5508 uint32_t ghc_control; 5509 5510 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_disable_all_intrs enter"); 5511 5512 ghc_control = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5513 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp)); 5514 5515 ghc_control &= ~ AHCI_HBA_GHC_IE; 5516 5517 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5518 (uint32_t *)AHCI_GLOBAL_GHC(ahci_ctlp), ghc_control); 5519 } 5520 5521 /* 5522 * Handle INTx and legacy interrupts. 5523 */ 5524 static int 5525 ahci_add_legacy_intrs(ahci_ctl_t *ahci_ctlp) 5526 { 5527 dev_info_t *dip = ahci_ctlp->ahcictl_dip; 5528 int actual, count = 0; 5529 int x, y, rc, inum = 0; 5530 5531 AHCIDBG0(AHCIDBG_ENTRY|AHCIDBG_INIT, ahci_ctlp, 5532 "ahci_add_legacy_intrs enter"); 5533 5534 /* get number of interrupts. */ 5535 rc = ddi_intr_get_nintrs(dip, DDI_INTR_TYPE_FIXED, &count); 5536 if ((rc != DDI_SUCCESS) || (count == 0)) { 5537 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5538 "ddi_intr_get_nintrs() failed, " 5539 "rc %d count %d\n", rc, count); 5540 return (DDI_FAILURE); 5541 } 5542 5543 /* Allocate an array of interrupt handles. */ 5544 ahci_ctlp->ahcictl_intr_size = count * sizeof (ddi_intr_handle_t); 5545 ahci_ctlp->ahcictl_intr_htable = 5546 kmem_zalloc(ahci_ctlp->ahcictl_intr_size, KM_SLEEP); 5547 5548 /* call ddi_intr_alloc(). */ 5549 rc = ddi_intr_alloc(dip, ahci_ctlp->ahcictl_intr_htable, 5550 DDI_INTR_TYPE_FIXED, 5551 inum, count, &actual, DDI_INTR_ALLOC_STRICT); 5552 5553 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5554 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5555 "ddi_intr_alloc() failed, rc %d\n", rc); 5556 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5557 ahci_ctlp->ahcictl_intr_size); 5558 return (DDI_FAILURE); 5559 } 5560 5561 if (actual < count) { 5562 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5563 "Requested: %d, Received: %d", count, actual); 5564 5565 for (x = 0; x < actual; x++) { 5566 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5567 } 5568 5569 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5570 ahci_ctlp->ahcictl_intr_size); 5571 return (DDI_FAILURE); 5572 } 5573 5574 ahci_ctlp->ahcictl_intr_cnt = actual; 5575 5576 /* Get intr priority. */ 5577 if (ddi_intr_get_pri(ahci_ctlp->ahcictl_intr_htable[0], 5578 &ahci_ctlp->ahcictl_intr_pri) != DDI_SUCCESS) { 5579 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5580 "ddi_intr_get_pri() failed"); 5581 5582 for (x = 0; x < actual; x++) { 5583 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5584 } 5585 5586 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5587 ahci_ctlp->ahcictl_intr_size); 5588 return (DDI_FAILURE); 5589 } 5590 5591 /* Test for high level interrupt. */ 5592 if (ahci_ctlp->ahcictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 5593 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5594 "ahci_add_legacy_intrs: Hi level intr not supported"); 5595 5596 for (x = 0; x < actual; x++) { 5597 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5598 } 5599 5600 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5601 sizeof (ddi_intr_handle_t)); 5602 5603 return (DDI_FAILURE); 5604 } 5605 5606 /* Call ddi_intr_add_handler(). */ 5607 for (x = 0; x < actual; x++) { 5608 if (ddi_intr_add_handler(ahci_ctlp->ahcictl_intr_htable[x], 5609 ahci_intr, (caddr_t)ahci_ctlp, NULL) != DDI_SUCCESS) { 5610 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5611 "ddi_intr_add_handler() failed"); 5612 5613 for (y = 0; y < actual; y++) { 5614 (void) ddi_intr_free( 5615 ahci_ctlp->ahcictl_intr_htable[y]); 5616 } 5617 5618 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5619 ahci_ctlp->ahcictl_intr_size); 5620 return (DDI_FAILURE); 5621 } 5622 } 5623 5624 /* Call ddi_intr_enable() for legacy interrupts. */ 5625 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5626 (void) ddi_intr_enable(ahci_ctlp->ahcictl_intr_htable[x]); 5627 } 5628 5629 return (DDI_SUCCESS); 5630 } 5631 5632 /* 5633 * Handle MSI interrupts. 5634 */ 5635 static int 5636 ahci_add_msi_intrs(ahci_ctl_t *ahci_ctlp) 5637 { 5638 dev_info_t *dip = ahci_ctlp->ahcictl_dip; 5639 int count, avail, actual; 5640 int x, y, rc, inum = 0; 5641 5642 AHCIDBG0(AHCIDBG_ENTRY|AHCIDBG_INIT, ahci_ctlp, 5643 "ahci_add_msi_intrs enter"); 5644 5645 /* get number of interrupts. */ 5646 rc = ddi_intr_get_nintrs(dip, DDI_INTR_TYPE_MSI, &count); 5647 if ((rc != DDI_SUCCESS) || (count == 0)) { 5648 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5649 "ddi_intr_get_nintrs() failed, " 5650 "rc %d count %d\n", rc, count); 5651 return (DDI_FAILURE); 5652 } 5653 5654 /* get number of available interrupts. */ 5655 rc = ddi_intr_get_navail(dip, DDI_INTR_TYPE_MSI, &avail); 5656 if ((rc != DDI_SUCCESS) || (avail == 0)) { 5657 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5658 "ddi_intr_get_navail() failed, " 5659 "rc %d avail %d\n", rc, avail); 5660 return (DDI_FAILURE); 5661 } 5662 5663 #if AHCI_DEBUG 5664 if (avail < count) { 5665 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5666 "ddi_intr_get_nvail returned %d, navail() returned %d", 5667 count, avail); 5668 } 5669 #endif 5670 5671 /* Allocate an array of interrupt handles. */ 5672 ahci_ctlp->ahcictl_intr_size = count * sizeof (ddi_intr_handle_t); 5673 ahci_ctlp->ahcictl_intr_htable = 5674 kmem_alloc(ahci_ctlp->ahcictl_intr_size, KM_SLEEP); 5675 5676 /* call ddi_intr_alloc(). */ 5677 rc = ddi_intr_alloc(dip, ahci_ctlp->ahcictl_intr_htable, 5678 DDI_INTR_TYPE_MSI, inum, count, &actual, DDI_INTR_ALLOC_NORMAL); 5679 5680 if ((rc != DDI_SUCCESS) || (actual == 0)) { 5681 AHCIDBG1(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5682 "ddi_intr_alloc() failed, rc %d\n", rc); 5683 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5684 ahci_ctlp->ahcictl_intr_size); 5685 return (DDI_FAILURE); 5686 } 5687 5688 /* use interrupt count returned */ 5689 #if AHCI_DEBUG 5690 if (actual < count) { 5691 AHCIDBG2(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5692 "Requested: %d, Received: %d", count, actual); 5693 } 5694 #endif 5695 5696 ahci_ctlp->ahcictl_intr_cnt = actual; 5697 5698 /* 5699 * Get priority for first msi, assume remaining are all the same. 5700 */ 5701 if (ddi_intr_get_pri(ahci_ctlp->ahcictl_intr_htable[0], 5702 &ahci_ctlp->ahcictl_intr_pri) != DDI_SUCCESS) { 5703 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5704 "ddi_intr_get_pri() failed"); 5705 5706 /* Free already allocated intr. */ 5707 for (y = 0; y < actual; y++) { 5708 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[y]); 5709 } 5710 5711 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5712 ahci_ctlp->ahcictl_intr_size); 5713 return (DDI_FAILURE); 5714 } 5715 5716 /* Test for high level interrupt. */ 5717 if (ahci_ctlp->ahcictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 5718 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5719 "ahci_add_msi_intrs: Hi level intr not supported"); 5720 5721 /* Free already allocated intr. */ 5722 for (y = 0; y < actual; y++) { 5723 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[y]); 5724 } 5725 5726 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5727 sizeof (ddi_intr_handle_t)); 5728 5729 return (DDI_FAILURE); 5730 } 5731 5732 /* Call ddi_intr_add_handler(). */ 5733 for (x = 0; x < actual; x++) { 5734 if (ddi_intr_add_handler(ahci_ctlp->ahcictl_intr_htable[x], 5735 ahci_intr, (caddr_t)ahci_ctlp, NULL) != DDI_SUCCESS) { 5736 AHCIDBG0(AHCIDBG_INTR|AHCIDBG_INIT, ahci_ctlp, 5737 "ddi_intr_add_handler() failed"); 5738 5739 /* Free already allocated intr. */ 5740 for (y = 0; y < actual; y++) { 5741 (void) ddi_intr_free( 5742 ahci_ctlp->ahcictl_intr_htable[y]); 5743 } 5744 5745 kmem_free(ahci_ctlp->ahcictl_intr_htable, 5746 ahci_ctlp->ahcictl_intr_size); 5747 return (DDI_FAILURE); 5748 } 5749 } 5750 5751 5752 (void) ddi_intr_get_cap(ahci_ctlp->ahcictl_intr_htable[0], 5753 &ahci_ctlp->ahcictl_intr_cap); 5754 5755 if (ahci_ctlp->ahcictl_intr_cap & DDI_INTR_FLAG_BLOCK) { 5756 /* Call ddi_intr_block_enable() for MSI. */ 5757 (void) ddi_intr_block_enable(ahci_ctlp->ahcictl_intr_htable, 5758 ahci_ctlp->ahcictl_intr_cnt); 5759 } else { 5760 /* Call ddi_intr_enable() for MSI non block enable. */ 5761 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5762 (void) ddi_intr_enable( 5763 ahci_ctlp->ahcictl_intr_htable[x]); 5764 } 5765 } 5766 5767 return (DDI_SUCCESS); 5768 } 5769 5770 /* 5771 * Removes the registered interrupts irrespective of whether they 5772 * were legacy or MSI. 5773 * 5774 * WARNING!!! The controller interrupts must be disabled before calling 5775 * this routine. 5776 */ 5777 static void 5778 ahci_rem_intrs(ahci_ctl_t *ahci_ctlp) 5779 { 5780 int x; 5781 5782 AHCIDBG0(AHCIDBG_ENTRY, ahci_ctlp, "ahci_rem_intrs entered"); 5783 5784 /* Disable all interrupts. */ 5785 if ((ahci_ctlp->ahcictl_intr_type == DDI_INTR_TYPE_MSI) && 5786 (ahci_ctlp->ahcictl_intr_cap & DDI_INTR_FLAG_BLOCK)) { 5787 /* Call ddi_intr_block_disable(). */ 5788 (void) ddi_intr_block_disable(ahci_ctlp->ahcictl_intr_htable, 5789 ahci_ctlp->ahcictl_intr_cnt); 5790 } else { 5791 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5792 (void) ddi_intr_disable( 5793 ahci_ctlp->ahcictl_intr_htable[x]); 5794 } 5795 } 5796 5797 /* Call ddi_intr_remove_handler(). */ 5798 for (x = 0; x < ahci_ctlp->ahcictl_intr_cnt; x++) { 5799 (void) ddi_intr_remove_handler( 5800 ahci_ctlp->ahcictl_intr_htable[x]); 5801 (void) ddi_intr_free(ahci_ctlp->ahcictl_intr_htable[x]); 5802 } 5803 5804 kmem_free(ahci_ctlp->ahcictl_intr_htable, ahci_ctlp->ahcictl_intr_size); 5805 } 5806 5807 /* 5808 * This routine tries to put port into P:NotRunning state by clearing 5809 * PxCMD.ST. HBA will clear PxCI to 0h, PxSACT to 0h, PxCMD.CCS to 0h 5810 * and PxCMD.CR to '0'. 5811 * 5812 * WARNING!!! ahciport_mutex should be acquired before the function 5813 * is called. 5814 */ 5815 static int 5816 ahci_put_port_into_notrunning_state(ahci_ctl_t *ahci_ctlp, 5817 ahci_port_t *ahci_portp, uint8_t port) 5818 { 5819 uint32_t port_cmd_status; 5820 int loop_count; 5821 5822 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5823 "ahci_put_port_into_notrunning_state enter: port %d", port); 5824 5825 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5826 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5827 5828 port_cmd_status &= ~AHCI_CMD_STATUS_ST; 5829 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5830 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port), port_cmd_status); 5831 5832 /* Wait until PxCMD.CR is cleared */ 5833 loop_count = 0; 5834 do { 5835 port_cmd_status = 5836 ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5837 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 5838 5839 if (loop_count++ > AHCI_POLLRATE_PORT_IDLE) { 5840 AHCIDBG2(AHCIDBG_INIT, ahci_ctlp, 5841 "clearing port %d CMD.CR timeout, " 5842 "port_cmd_status = 0x%x", port, 5843 port_cmd_status); 5844 /* 5845 * We are effectively timing out after 0.5 sec. 5846 * This value is specified in AHCI spec. 5847 */ 5848 break; 5849 } 5850 5851 /* Wait for 10 millisec */ 5852 delay(AHCI_10MS_TICKS); 5853 } while (port_cmd_status & AHCI_CMD_STATUS_CR); 5854 5855 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_STARTED; 5856 5857 if (port_cmd_status & AHCI_CMD_STATUS_CR) { 5858 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 5859 "ahci_put_port_into_notrunning_state: failed to clear " 5860 "PxCMD.CR to '0' after loop count: %d, and " 5861 "port_cmd_status = 0x%x", loop_count, port_cmd_status); 5862 return (AHCI_FAILURE); 5863 } else { 5864 AHCIDBG2(AHCIDBG_INIT|AHCIDBG_POLL_LOOP, ahci_ctlp, 5865 "ahci_put_port_into_notrunning_state: succeeded to clear " 5866 "PxCMD.CR to '0' after loop count: %d, and " 5867 "port_cmd_status = 0x%x", loop_count, port_cmd_status); 5868 return (AHCI_SUCCESS); 5869 } 5870 } 5871 5872 /* 5873 * First clear PxCMD.ST, and then check PxTFD. If both PxTFD.STS.BSY 5874 * and PxTFD.STS.DRQ cleared to '0', it means the device is in a 5875 * stable state, then set PxCMD.ST to '1' to start the port directly. 5876 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then issue a 5877 * COMRESET to the device to put it in an idle state. 5878 * 5879 * The fifth argument returns whether the port reset is involved during 5880 * the process. 5881 * 5882 * The routine will be called under six scenarios: 5883 * 1. Initialize the port 5884 * 2. To abort the packet(s) 5885 * 3. To reset the port 5886 * 4. To activate the port 5887 * 5. Fatal error recovery 5888 * 6. To abort the timeout packet(s) 5889 * 5890 * WARNING!!! ahciport_mutex should be acquired before the function 5891 * is called. And ahciport_mutex will be released before the reset 5892 * event is reported to sata module by calling sata_hba_event_notify, 5893 * and then be acquired again later. 5894 * 5895 * NOTES!!! During this procedure, PxSERR register will be cleared, and 5896 * according to the spec, the clearance of three bits will also clear 5897 * three interrupt status bits. 5898 * 1. PxSERR.DIAG.F will clear PxIS.UFS 5899 * 2. PxSERR.DIAG.X will clear PxIS.PCS 5900 * 3. PxSERR.DIAG.N will clear PxIS.PRCS 5901 * 5902 * Among these three interrupt events, the driver needs to take care of 5903 * PxIS.PRCS, which is the hot plug event. When the driver found out 5904 * a device was unplugged, it will call the interrupt handler. 5905 */ 5906 static int 5907 ahci_restart_port_wait_till_ready(ahci_ctl_t *ahci_ctlp, 5908 ahci_port_t *ahci_portp, uint8_t port, int flag, int *reset_flag) 5909 { 5910 uint32_t port_sstatus; 5911 uint32_t task_file_status; 5912 sata_device_t sdevice; 5913 int rval; 5914 int dev_exists_begin = 0; 5915 int dev_exists_end = 0; 5916 5917 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 5918 "ahci_restart_port_wait_till_ready: port %d enter", port); 5919 5920 if ((flag != AHCI_PORT_INIT) && 5921 (ahci_portp->ahciport_device_type != SATA_DTYPE_NONE)) 5922 dev_exists_begin = 1; 5923 5924 /* First clear PxCMD.ST */ 5925 rval = ahci_put_port_into_notrunning_state(ahci_ctlp, ahci_portp, 5926 port); 5927 if (rval != AHCI_SUCCESS) 5928 /* 5929 * If PxCMD.CR does not clear within a reasonable time, it 5930 * may assume the interface is in a hung condition and may 5931 * continue with issuing the port reset. 5932 */ 5933 goto reset; 5934 5935 /* Then clear PxSERR */ 5936 ddi_put32(ahci_ctlp->ahcictl_ahci_acc_handle, 5937 (uint32_t *)AHCI_PORT_PxSERR(ahci_ctlp, port), 5938 AHCI_SERROR_CLEAR_ALL); 5939 5940 /* Then get PxTFD */ 5941 task_file_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 5942 (uint32_t *)AHCI_PORT_PxTFD(ahci_ctlp, port)); 5943 5944 /* 5945 * Check whether the device is in a stable status, if yes, 5946 * then start the port directly. However for ahci_tran_dport_reset, 5947 * we may have to perform a port reset. 5948 */ 5949 if (!(task_file_status & (AHCI_TFD_STS_BSY | AHCI_TFD_STS_DRQ)) && 5950 !(flag & AHCI_PORT_RESET)) 5951 goto out; 5952 5953 reset: 5954 /* 5955 * If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to '1', then issue 5956 * a COMRESET to the device 5957 */ 5958 rval = ahci_port_reset(ahci_ctlp, ahci_portp, port); 5959 5960 if (reset_flag != NULL) 5961 *reset_flag = 1; 5962 5963 /* Indicate to the framework that a reset has happened. */ 5964 if ((ahci_portp->ahciport_device_type != SATA_DTYPE_NONE) && 5965 !(flag & AHCI_RESET_NO_EVENTS_UP)) { 5966 /* Set the reset in progress flag */ 5967 ahci_portp->ahciport_reset_in_progress = 1; 5968 5969 bzero((void *)&sdevice, sizeof (sata_device_t)); 5970 sdevice.satadev_addr.cport = 5971 ahci_ctlp->ahcictl_port_to_cport[port]; 5972 sdevice.satadev_addr.pmport = 0; 5973 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 5974 5975 sdevice.satadev_state = SATA_DSTATE_RESET | 5976 SATA_DSTATE_PWR_ACTIVE; 5977 if (ahci_ctlp->ahcictl_sata_hba_tran) { 5978 mutex_exit(&ahci_portp->ahciport_mutex); 5979 sata_hba_event_notify( 5980 ahci_ctlp->ahcictl_sata_hba_tran->sata_tran_hba_dip, 5981 &sdevice, 5982 SATA_EVNT_DEVICE_RESET); 5983 mutex_enter(&ahci_portp->ahciport_mutex); 5984 } 5985 5986 AHCIDBG1(AHCIDBG_EVENT, ahci_ctlp, 5987 "port %d sending event up: SATA_EVNT_RESET", port); 5988 } else { 5989 ahci_portp->ahciport_reset_in_progress = 0; 5990 } 5991 5992 out: 5993 /* Start the port if not in initialization phase */ 5994 if (flag & AHCI_PORT_INIT) 5995 return (rval); 5996 5997 (void) ahci_start_port(ahci_ctlp, ahci_portp, port); 5998 5999 /* SStatus tells the presence of device. */ 6000 port_sstatus = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6001 (uint32_t *)AHCI_PORT_PxSSTS(ahci_ctlp, port)); 6002 6003 if (SSTATUS_GET_DET(port_sstatus) == SSTATUS_DET_DEVPRE_PHYCOM) { 6004 dev_exists_end = 1; 6005 ASSERT(ahci_portp->ahciport_device_type != SATA_DTYPE_NONE); 6006 } 6007 6008 /* Check whether a hot plug event happened */ 6009 if (dev_exists_begin == 1 && dev_exists_end == 0) { 6010 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6011 "ahci_restart_port_wait_till_ready: port %d " 6012 "device is removed", port); 6013 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_NODEV; 6014 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6015 "ahci_restart_port_wait_till_ready: port %d " 6016 "AHCI_PORT_FLAG_NODEV flag is set", port); 6017 mutex_exit(&ahci_portp->ahciport_mutex); 6018 (void) ahci_intr_phyrdy_change(ahci_ctlp, ahci_portp, port); 6019 mutex_enter(&ahci_portp->ahciport_mutex); 6020 } 6021 6022 return (rval); 6023 } 6024 6025 /* 6026 * This routine may be called under four scenarios: 6027 * a) do the recovery from fatal error 6028 * b) or we need to timeout some commands 6029 * c) or we need to abort some commands 6030 * d) or we need reset device/port/controller 6031 * 6032 * In all these scenarios, we need to send any pending unfinished 6033 * commands up to sata framework. 6034 * 6035 * WARNING!!! ahciport_mutex should be acquired before the function is called. 6036 */ 6037 static void 6038 ahci_mop_commands(ahci_ctl_t *ahci_ctlp, 6039 ahci_port_t *ahci_portp, 6040 uint32_t slot_status, 6041 uint32_t failed_tags, 6042 uint32_t timeout_tags, 6043 uint32_t aborted_tags, 6044 uint32_t reset_tags) 6045 { 6046 uint32_t finished_tags = 0; 6047 uint32_t unfinished_tags = 0; 6048 int tmp_slot; 6049 sata_pkt_t *satapkt; 6050 int ncq_cmd_in_progress = 0; 6051 int err_retri_cmd_in_progress = 0; 6052 6053 AHCIDBG2(AHCIDBG_ERRS|AHCIDBG_ENTRY, ahci_ctlp, 6054 "ahci_mop_commands entered: port: %d slot_status: 0x%x", 6055 ahci_portp->ahciport_port_num, slot_status); 6056 6057 AHCIDBG4(AHCIDBG_ERRS|AHCIDBG_ENTRY, ahci_ctlp, 6058 "ahci_mop_commands: failed_tags: 0x%x, " 6059 "timeout_tags: 0x%x aborted_tags: 0x%x, " 6060 "reset_tags: 0x%x", failed_tags, 6061 timeout_tags, aborted_tags, reset_tags); 6062 6063 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6064 finished_tags = ahci_portp->ahciport_pending_tags & 6065 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 6066 6067 unfinished_tags = slot_status & 6068 AHCI_SLOT_MASK(ahci_ctlp) & 6069 ~failed_tags & 6070 ~aborted_tags & 6071 ~reset_tags & 6072 ~timeout_tags; 6073 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6074 ncq_cmd_in_progress = 1; 6075 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 6076 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 6077 6078 unfinished_tags = slot_status & 6079 AHCI_NCQ_SLOT_MASK(ahci_portp) & 6080 ~failed_tags & 6081 ~aborted_tags & 6082 ~reset_tags & 6083 ~timeout_tags; 6084 } else if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6085 6086 /* 6087 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT is 6088 * set, it means REQUEST SENSE or READ LOG EXT command doesn't 6089 * complete successfully due to one of the following three 6090 * conditions: 6091 * 6092 * 1. Fatal error - failed_tags includes its slot 6093 * 2. Timed out - timeout_tags includes its slot 6094 * 3. Aborted when hot unplug - aborted_tags includes its 6095 * slot 6096 * 6097 * Please note that the command is always sent down in Slot 0 6098 */ 6099 err_retri_cmd_in_progress = 1; 6100 AHCIDBG1(AHCIDBG_ERRS|AHCIDBG_NCQ, ahci_ctlp, 6101 "ahci_mop_commands is called for port %d while " 6102 "REQUEST SENSE or READ LOG EXT for error retrieval " 6103 "is being executed", ahci_portp->ahciport_port_num); 6104 ASSERT(ahci_portp->ahciport_mop_in_progress > 1); 6105 ASSERT(slot_status == 0x1); 6106 } 6107 6108 /* Send up finished packets with SATA_PKT_COMPLETED */ 6109 while (finished_tags) { 6110 tmp_slot = ddi_ffs(finished_tags) - 1; 6111 if (tmp_slot == -1) { 6112 break; 6113 } 6114 6115 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6116 ASSERT(satapkt != NULL); 6117 6118 AHCIDBG1(AHCIDBG_INFO, ahci_ctlp, "ahci_mop_commands: " 6119 "sending up pkt 0x%p with SATA_PKT_COMPLETED", 6120 (void *)satapkt); 6121 6122 /* 6123 * Cannot fetch the return register content since the port 6124 * was restarted, so the corresponding tag will be set to 6125 * aborted tags. 6126 */ 6127 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) { 6128 CLEAR_BIT(finished_tags, tmp_slot); 6129 aborted_tags |= tmp_slot; 6130 continue; 6131 } 6132 6133 if (ncq_cmd_in_progress) 6134 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6135 tmp_slot); 6136 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6137 CLEAR_BIT(finished_tags, tmp_slot); 6138 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6139 6140 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_COMPLETED); 6141 } 6142 6143 /* Send up failed packets with SATA_PKT_DEV_ERROR. */ 6144 while (failed_tags) { 6145 if (err_retri_cmd_in_progress) { 6146 satapkt = ahci_portp->ahciport_err_retri_pkt; 6147 ASSERT(satapkt != NULL); 6148 ASSERT(failed_tags == 0x1); 6149 6150 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6151 "sending up pkt 0x%p with SATA_PKT_DEV_ERROR", 6152 (void *)satapkt); 6153 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_DEV_ERROR); 6154 break; 6155 } 6156 6157 tmp_slot = ddi_ffs(failed_tags) - 1; 6158 if (tmp_slot == -1) { 6159 break; 6160 } 6161 6162 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6163 ASSERT(satapkt != NULL); 6164 6165 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6166 "sending up pkt 0x%p with SATA_PKT_DEV_ERROR", 6167 (void *)satapkt); 6168 6169 if (ncq_cmd_in_progress) 6170 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6171 tmp_slot); 6172 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6173 CLEAR_BIT(failed_tags, tmp_slot); 6174 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6175 6176 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_DEV_ERROR); 6177 } 6178 6179 /* Send up timeout packets with SATA_PKT_TIMEOUT. */ 6180 while (timeout_tags) { 6181 if (err_retri_cmd_in_progress) { 6182 satapkt = ahci_portp->ahciport_err_retri_pkt; 6183 ASSERT(satapkt != NULL); 6184 ASSERT(timeout_tags == 0x1); 6185 6186 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6187 "sending up pkt 0x%p with SATA_PKT_TIMEOUT", 6188 (void *)satapkt); 6189 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_TIMEOUT); 6190 break; 6191 } 6192 6193 tmp_slot = ddi_ffs(timeout_tags) - 1; 6194 if (tmp_slot == -1) { 6195 break; 6196 } 6197 6198 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6199 ASSERT(satapkt != NULL); 6200 6201 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6202 "sending up pkt 0x%p with SATA_PKT_TIMEOUT", 6203 (void *)satapkt); 6204 6205 if (ncq_cmd_in_progress) 6206 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6207 tmp_slot); 6208 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6209 CLEAR_BIT(timeout_tags, tmp_slot); 6210 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6211 6212 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_TIMEOUT); 6213 } 6214 6215 /* Send up aborted packets with SATA_PKT_ABORTED */ 6216 while (aborted_tags) { 6217 if (err_retri_cmd_in_progress) { 6218 satapkt = ahci_portp->ahciport_err_retri_pkt; 6219 ASSERT(satapkt != NULL); 6220 ASSERT(aborted_tags == 0x1); 6221 6222 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6223 "sending up pkt 0x%p with SATA_PKT_ABORTED", 6224 (void *)satapkt); 6225 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_ABORTED); 6226 break; 6227 } 6228 6229 tmp_slot = ddi_ffs(aborted_tags) - 1; 6230 if (tmp_slot == -1) { 6231 break; 6232 } 6233 6234 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6235 ASSERT(satapkt != NULL); 6236 6237 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6238 "sending up pkt 0x%p with SATA_PKT_ABORTED", 6239 (void *)satapkt); 6240 6241 if (ncq_cmd_in_progress) 6242 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6243 tmp_slot); 6244 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6245 CLEAR_BIT(aborted_tags, tmp_slot); 6246 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6247 6248 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_ABORTED); 6249 } 6250 6251 /* Send up reset packets with SATA_PKT_RESET. */ 6252 while (reset_tags) { 6253 tmp_slot = ddi_ffs(reset_tags) - 1; 6254 if (tmp_slot == -1) { 6255 break; 6256 } 6257 6258 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6259 ASSERT(satapkt != NULL); 6260 6261 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6262 "sending up pkt 0x%p with SATA_PKT_RESET", 6263 (void *)satapkt); 6264 6265 if (ncq_cmd_in_progress) 6266 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6267 tmp_slot); 6268 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6269 CLEAR_BIT(reset_tags, tmp_slot); 6270 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6271 6272 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_RESET); 6273 } 6274 6275 /* Send up unfinished packets with SATA_PKT_RESET */ 6276 while (unfinished_tags) { 6277 tmp_slot = ddi_ffs(unfinished_tags) - 1; 6278 if (tmp_slot == -1) { 6279 break; 6280 } 6281 6282 satapkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6283 ASSERT(satapkt != NULL); 6284 6285 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, "ahci_mop_commands: " 6286 "sending up pkt 0x%p with SATA_PKT_RESET", 6287 (void *)satapkt); 6288 6289 if (ncq_cmd_in_progress) 6290 CLEAR_BIT(ahci_portp->ahciport_pending_ncq_tags, 6291 tmp_slot); 6292 CLEAR_BIT(ahci_portp->ahciport_pending_tags, tmp_slot); 6293 CLEAR_BIT(unfinished_tags, tmp_slot); 6294 ahci_portp->ahciport_slot_pkts[tmp_slot] = NULL; 6295 6296 SENDUP_PACKET(ahci_portp, satapkt, SATA_PKT_RESET); 6297 } 6298 6299 ahci_portp->ahciport_mop_in_progress--; 6300 ASSERT(ahci_portp->ahciport_mop_in_progress >= 0); 6301 6302 if (ahci_portp->ahciport_mop_in_progress == 0) 6303 ahci_portp->ahciport_flags &= ~AHCI_PORT_FLAG_MOPPING; 6304 } 6305 6306 /* 6307 * This routine is going to first request a READ LOG EXT sata pkt from sata 6308 * module, and then deliver it to the HBA to get the ncq failure context. 6309 * The return value is the exactly failed tags. 6310 */ 6311 static uint32_t 6312 ahci_get_rdlogext_data(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 6313 uint8_t port) 6314 { 6315 sata_device_t sdevice; 6316 sata_pkt_t *rdlog_spkt, *spkt; 6317 ddi_dma_handle_t buf_dma_handle; 6318 int loop_count; 6319 int rval; 6320 int failed_slot; 6321 uint32_t failed_tags = 0; 6322 struct sata_ncq_error_recovery_page *ncq_err_page; 6323 6324 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_NCQ, ahci_ctlp, 6325 "ahci_get_rdlogext_data enter: port %d", port); 6326 6327 /* Prepare the sdevice data */ 6328 bzero((void *)&sdevice, sizeof (sata_device_t)); 6329 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 6330 6331 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 6332 sdevice.satadev_addr.pmport = 0; 6333 6334 /* 6335 * Call the sata hba interface to get a rdlog spkt 6336 */ 6337 loop_count = 0; 6338 loop: 6339 rdlog_spkt = sata_get_error_retrieval_pkt(ahci_ctlp->ahcictl_dip, 6340 &sdevice, SATA_ERR_RETR_PKT_TYPE_NCQ); 6341 if (rdlog_spkt == NULL) { 6342 if (loop_count++ < AHCI_POLLRATE_GET_SPKT) { 6343 /* Sleep for a while */ 6344 delay(AHCI_10MS_TICKS); 6345 goto loop; 6346 } 6347 /* Timed out after 1s */ 6348 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6349 "failed to get rdlog spkt for port %d", port); 6350 return (failed_tags); 6351 } 6352 6353 ASSERT(rdlog_spkt->satapkt_op_mode & SATA_OPMODE_SYNCH); 6354 6355 /* 6356 * This flag is used to handle the specific error recovery when the 6357 * READ LOG EXT command gets a failure (fatal error or time-out). 6358 */ 6359 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_RDLOGEXT; 6360 6361 /* 6362 * This start is not supposed to fail because after port is restarted, 6363 * the whole command list is empty. 6364 */ 6365 ahci_portp->ahciport_err_retri_pkt = rdlog_spkt; 6366 (void) ahci_do_sync_start(ahci_ctlp, ahci_portp, port, rdlog_spkt); 6367 ahci_portp->ahciport_err_retri_pkt = NULL; 6368 6369 /* Remove the flag after READ LOG EXT command is completed */ 6370 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_RDLOGEXT; 6371 6372 if (rdlog_spkt->satapkt_reason == SATA_PKT_COMPLETED) { 6373 /* Update the request log data */ 6374 buf_dma_handle = *(ddi_dma_handle_t *) 6375 (rdlog_spkt->satapkt_cmd.satacmd_err_ret_buf_handle); 6376 rval = ddi_dma_sync(buf_dma_handle, 0, 0, 6377 DDI_DMA_SYNC_FORKERNEL); 6378 if (rval == DDI_SUCCESS) { 6379 ncq_err_page = 6380 (struct sata_ncq_error_recovery_page *)rdlog_spkt-> 6381 satapkt_cmd.satacmd_bp->b_un.b_addr; 6382 6383 /* Get the failed tag */ 6384 failed_slot = ncq_err_page->ncq_tag; 6385 AHCIDBG2(AHCIDBG_ERRS, ahci_ctlp, 6386 "ahci_get_rdlogext_data: port %d " 6387 "failed slot %d", port, failed_slot); 6388 if (failed_slot & NQ) { 6389 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 6390 "the failed slot is not a valid tag"); 6391 goto out; 6392 } 6393 6394 failed_slot &= NCQ_TAG_MASK; 6395 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 6396 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6397 "ahci_get_rdlogext_data: failed spkt 0x%p", 6398 (void *)spkt); 6399 if (spkt == NULL) { 6400 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, 6401 "the failed slot spkt is NULL") 6402 goto out; 6403 } 6404 6405 failed_tags = 0x1 << failed_slot; 6406 6407 /* Fill out the error context */ 6408 ahci_copy_ncq_err_page(&spkt->satapkt_cmd, 6409 ncq_err_page); 6410 ahci_update_sata_registers(ahci_ctlp, port, 6411 &spkt->satapkt_device); 6412 } 6413 } 6414 out: 6415 sata_free_error_retrieval_pkt(rdlog_spkt); 6416 6417 return (failed_tags); 6418 } 6419 6420 /* 6421 * This routine is going to first request a REQUEST SENSE sata pkt from sata 6422 * module, and then deliver it to the HBA to get the sense data and copy 6423 * the sense data back to the orignal failed sata pkt, and free the REQUEST 6424 * SENSE sata pkt later. 6425 */ 6426 static void 6427 ahci_get_rqsense_data(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 6428 uint8_t port, sata_pkt_t *spkt) 6429 { 6430 sata_device_t sdevice; 6431 sata_pkt_t *rs_spkt; 6432 sata_cmd_t *sata_cmd; 6433 ddi_dma_handle_t buf_dma_handle; 6434 int loop_count; 6435 #if AHCI_DEBUG 6436 struct scsi_extended_sense *rqsense; 6437 #endif 6438 6439 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 6440 "ahci_get_rqsense_data enter: port %d", port); 6441 6442 /* Prepare the sdevice data */ 6443 bzero((void *)&sdevice, sizeof (sata_device_t)); 6444 sdevice.satadev_addr.cport = ahci_ctlp->ahcictl_port_to_cport[port]; 6445 6446 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 6447 sdevice.satadev_addr.pmport = 0; 6448 6449 sata_cmd = &spkt->satapkt_cmd; 6450 6451 /* 6452 * Call the sata hba interface to get a rs spkt 6453 */ 6454 loop_count = 0; 6455 loop: 6456 rs_spkt = sata_get_error_retrieval_pkt(ahci_ctlp->ahcictl_dip, 6457 &sdevice, SATA_ERR_RETR_PKT_TYPE_ATAPI); 6458 if (rs_spkt == NULL) { 6459 if (loop_count++ < AHCI_POLLRATE_GET_SPKT) { 6460 /* Sleep for a while */ 6461 delay(AHCI_10MS_TICKS); 6462 goto loop; 6463 6464 } 6465 /* Timed out after 1s */ 6466 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6467 "failed to get rs spkt for port %d", port); 6468 return; 6469 } 6470 6471 ASSERT(rs_spkt->satapkt_op_mode & SATA_OPMODE_SYNCH); 6472 6473 /* 6474 * This flag is used to handle the specific error recovery when the 6475 * REQUEST SENSE command gets a faiure (fatal error or time-out). 6476 */ 6477 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_RQSENSE; 6478 6479 /* 6480 * This start is not supposed to fail because after port is restarted, 6481 * the whole command list is empty. 6482 */ 6483 ahci_portp->ahciport_err_retri_pkt = rs_spkt; 6484 (void) ahci_do_sync_start(ahci_ctlp, ahci_portp, port, rs_spkt); 6485 ahci_portp->ahciport_err_retri_pkt = NULL; 6486 6487 /* Remove the flag after REQUEST SENSE command is completed */ 6488 ahci_portp->ahciport_flags &= ~ AHCI_PORT_FLAG_RQSENSE; 6489 6490 if (rs_spkt->satapkt_reason == SATA_PKT_COMPLETED) { 6491 /* Update the request sense data */ 6492 buf_dma_handle = *(ddi_dma_handle_t *) 6493 (rs_spkt->satapkt_cmd.satacmd_err_ret_buf_handle); 6494 (void) ddi_dma_sync(buf_dma_handle, 0, 0, 6495 DDI_DMA_SYNC_FORKERNEL); 6496 /* Copy the request sense data */ 6497 bcopy(rs_spkt-> 6498 satapkt_cmd.satacmd_bp->b_un.b_addr, 6499 &sata_cmd->satacmd_rqsense, 6500 SATA_ATAPI_MIN_RQSENSE_LEN); 6501 #if AHCI_DEBUG 6502 rqsense = (struct scsi_extended_sense *) 6503 sata_cmd->satacmd_rqsense; 6504 6505 /* Dump the sense data */ 6506 AHCIDBG0(AHCIDBG_SENSEDATA, ahci_ctlp, "\n"); 6507 AHCIDBG2(AHCIDBG_SENSEDATA, ahci_ctlp, 6508 "Sense data for satapkt %p ATAPI cmd 0x%x", 6509 spkt, sata_cmd->satacmd_acdb[0]); 6510 AHCIDBG5(AHCIDBG_SENSEDATA, ahci_ctlp, 6511 " es_code 0x%x es_class 0x%x " 6512 "es_key 0x%x es_add_code 0x%x " 6513 "es_qual_code 0x%x", 6514 rqsense->es_code, rqsense->es_class, 6515 rqsense->es_key, rqsense->es_add_code, 6516 rqsense->es_qual_code); 6517 #endif 6518 } 6519 6520 sata_free_error_retrieval_pkt(rs_spkt); 6521 } 6522 6523 /* 6524 * Fatal errors will cause the HBA to enter the ERR: Fatal state. To recover, 6525 * the port must be restarted. When the HBA detects thus error, it may try 6526 * to abort a transfer. And if the transfer was aborted, the device is 6527 * expected to send a D2H Register FIS with PxTFD.STS.ERR set to '1' and both 6528 * PxTFD.STS.BSY and PxTFD.STS.DRQ cleared to '0'. Then system software knows 6529 * that the device is in a stable status and transfers may be restarted without 6530 * issuing a COMRESET to the device. If PxTFD.STS.BSY or PxTFD.STS.DRQ is set, 6531 * then the software will send the COMRESET to do the port reset. 6532 * 6533 * Software should perform the appropriate error recovery actions based on 6534 * whether non-queued commands were being issued or natived command queuing 6535 * commands were being issued. 6536 * 6537 * And software will complete the command that had the error with error mark 6538 * to higher level software. 6539 * 6540 * Fatal errors include the following: 6541 * PxIS.IFS - Interface Fatal Error Status 6542 * PxIS.HBDS - Host Bus Data Error Status 6543 * PxIS.HBFS - Host Bus Fatal Error Status 6544 * PxIS.TFES - Task File Error Status 6545 * 6546 * WARNING!!! ahciport_mutex should be acquired before the function is called. 6547 */ 6548 static void 6549 ahci_fatal_error_recovery_handler(ahci_ctl_t *ahci_ctlp, 6550 ahci_port_t *ahci_portp, uint8_t port, uint32_t intr_status) 6551 { 6552 uint32_t port_cmd_status; 6553 uint32_t slot_status = 0; 6554 uint32_t failed_tags = 0; 6555 int failed_slot; 6556 int reset_flag = 0; 6557 ahci_fis_d2h_register_t *ahci_rcvd_fisp; 6558 sata_cmd_t *sata_cmd = NULL; 6559 sata_pkt_t *spkt = NULL; 6560 6561 AHCIDBG1(AHCIDBG_ENTRY, ahci_ctlp, 6562 "ahci_fatal_error_recovery_handler enter: port %d", port); 6563 6564 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 6565 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6566 6567 /* Read PxCI to see which commands are still outstanding */ 6568 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6569 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 6570 6571 /* 6572 * Read PxCMD.CCS to determine the slot that the HBA 6573 * was processing when the error occurred. 6574 */ 6575 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6576 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 6577 failed_slot = (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 6578 AHCI_CMD_STATUS_CCS_SHIFT; 6579 6580 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6581 spkt = ahci_portp->ahciport_err_retri_pkt; 6582 ASSERT(spkt != NULL); 6583 } else { 6584 spkt = ahci_portp->ahciport_slot_pkts[failed_slot]; 6585 if (spkt == NULL) { 6586 /* May happen when interface errors occur? */ 6587 goto next; 6588 } 6589 } 6590 6591 sata_cmd = &spkt->satapkt_cmd; 6592 6593 /* Fill out the status and error registers for PxIS.TFES */ 6594 if (intr_status & AHCI_INTR_STATUS_TFES) { 6595 ahci_rcvd_fisp = &(ahci_portp->ahciport_rcvd_fis-> 6596 ahcirf_d2h_register_fis); 6597 6598 /* Copy the error context back to the sata_cmd */ 6599 ahci_copy_err_cnxt(sata_cmd, ahci_rcvd_fisp); 6600 } 6601 6602 /* The failed command must be one of the outstanding commands */ 6603 failed_tags = 0x1 << failed_slot; 6604 ASSERT(failed_tags & slot_status); 6605 6606 /* Update the sata registers, especially PxSERR register */ 6607 ahci_update_sata_registers(ahci_ctlp, port, 6608 &spkt->satapkt_device); 6609 6610 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6611 /* Read PxSACT to see which commands are still outstanding */ 6612 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6613 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 6614 } 6615 next: 6616 6617 #if AHCI_DEBUG 6618 /* 6619 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT flag is 6620 * set, it means a fatal error happened after REQUEST SENSE command 6621 * or READ LOG EXT command is delivered to the HBA during the error 6622 * recovery process. At this time, the only outstanding command is 6623 * supposed to be REQUEST SENSE command or READ LOG EXT command. 6624 */ 6625 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6626 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6627 "ahci_fatal_error_recovery_handler: port %d REQUEST SENSE " 6628 "command or READ LOG EXT command for error data retrieval " 6629 "failed", port); 6630 ASSERT(slot_status == 0x1); 6631 ASSERT(failed_slot == 0x1); 6632 ASSERT(spkt->satapkt_cmd.satacmd_acdb[0] == 6633 SCMD_REQUEST_SENSE || 6634 spkt->satapkt_cmd.satacmd_cmd_reg == 6635 SATAC_READ_LOG_EXT); 6636 } 6637 #endif 6638 6639 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 6640 ahci_portp->ahciport_mop_in_progress++; 6641 6642 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 6643 port, NULL, &reset_flag); 6644 6645 /* 6646 * Won't retrieve error information: 6647 * 1. Port reset was involved to recover 6648 * 2. Device is gone 6649 * 3. IDENTIFY DEVICE command sent to ATAPI device 6650 * 4. REQUEST SENSE or READ LOG EXT command during error recovery 6651 */ 6652 if (reset_flag || 6653 ahci_portp->ahciport_device_type == SATA_DTYPE_NONE || 6654 spkt && spkt->satapkt_cmd.satacmd_cmd_reg == SATAC_ID_DEVICE || 6655 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 6656 goto out; 6657 6658 /* 6659 * Deliver READ LOG EXT to gather information about the error when 6660 * a COMRESET has not been performed as part of the error recovery 6661 * during NCQ command processing. 6662 */ 6663 if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6664 failed_tags = ahci_get_rdlogext_data(ahci_ctlp, 6665 ahci_portp, port); 6666 goto out; 6667 } 6668 6669 /* 6670 * Deliver REQUEST SENSE for ATAPI command to gather information about 6671 * the error when a COMRESET has not been performed as part of the 6672 * error recovery. 6673 */ 6674 if (spkt && ahci_portp->ahciport_device_type == SATA_DTYPE_ATAPICD) 6675 ahci_get_rqsense_data(ahci_ctlp, ahci_portp, port, spkt); 6676 out: 6677 AHCIDBG5(AHCIDBG_ERRS, ahci_ctlp, 6678 "ahci_fatal_error_recovery_handler: port %d interface error " 6679 "occurred slot_status = 0x%x, pending_tags = 0x%x, " 6680 "pending_ncq_tags = 0x%x failed_tags = 0x%x", 6681 port, slot_status, ahci_portp->ahciport_pending_tags, 6682 ahci_portp->ahciport_pending_ncq_tags, failed_tags); 6683 6684 ahci_mop_commands(ahci_ctlp, 6685 ahci_portp, 6686 slot_status, 6687 failed_tags, /* failed tags */ 6688 0, /* timeout tags */ 6689 0, /* aborted tags */ 6690 0); /* reset tags */ 6691 } 6692 6693 /* 6694 * Handle events - fatal error recovery 6695 */ 6696 static void 6697 ahci_events_handler(void *args) 6698 { 6699 ahci_event_arg_t *ahci_event_arg; 6700 ahci_ctl_t *ahci_ctlp; 6701 ahci_port_t *ahci_portp; 6702 uint32_t event; 6703 uint8_t port; 6704 6705 ahci_event_arg = (ahci_event_arg_t *)args; 6706 6707 ahci_ctlp = ahci_event_arg->ahciea_ctlp; 6708 ahci_portp = ahci_event_arg->ahciea_portp; 6709 event = ahci_event_arg->ahciea_event; 6710 port = ahci_portp->ahciport_port_num; 6711 6712 AHCIDBG2(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 6713 "ahci_events_handler enter: port %d intr_status = 0x%x", 6714 port, event); 6715 6716 mutex_enter(&ahci_portp->ahciport_mutex); 6717 6718 /* 6719 * ahci_intr_phyrdy_change() may have rendered it to 6720 * SATA_DTYPE_NONE. 6721 */ 6722 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 6723 AHCIDBG1(AHCIDBG_ENTRY|AHCIDBG_INTR, ahci_ctlp, 6724 "ahci_events_handler: port %d no device attached, " 6725 "and just return without doing anything", port); 6726 goto out; 6727 } 6728 6729 if (event & (AHCI_INTR_STATUS_IFS | 6730 AHCI_INTR_STATUS_HBDS | 6731 AHCI_INTR_STATUS_HBFS | 6732 AHCI_INTR_STATUS_TFES)) 6733 ahci_fatal_error_recovery_handler(ahci_ctlp, ahci_portp, 6734 port, event); 6735 6736 out: 6737 mutex_exit(&ahci_portp->ahciport_mutex); 6738 } 6739 6740 /* 6741 * ahci_watchdog_handler() and ahci_do_sync_start will call us if they 6742 * detect there are some commands which are timed out. 6743 */ 6744 static void 6745 ahci_timeout_pkts(ahci_ctl_t *ahci_ctlp, ahci_port_t *ahci_portp, 6746 uint8_t port, uint32_t tmp_timeout_tags) 6747 { 6748 uint32_t slot_status = 0; 6749 uint32_t finished_tags = 0; 6750 uint32_t timeout_tags = 0; 6751 6752 AHCIDBG1(AHCIDBG_TIMEOUT|AHCIDBG_ENTRY, ahci_ctlp, 6753 "ahci_timeout_pkts enter: port %d", port); 6754 6755 mutex_enter(&ahci_portp->ahciport_mutex); 6756 6757 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) || 6758 ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6759 /* Read PxCI to see which commands are still outstanding */ 6760 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6761 (uint32_t *)AHCI_PORT_PxCI(ahci_ctlp, port)); 6762 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6763 /* Read PxSACT to see which commands are still outstanding */ 6764 slot_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6765 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 6766 } 6767 6768 #if AHCI_DEBUG 6769 /* 6770 * When AHCI_PORT_FLAG_RQSENSE or AHCI_PORT_FLAG_RDLOGEXT flag is 6771 * set, it means a fatal error happened after REQUEST SENSE command 6772 * or READ LOG EXT command is delivered to the HBA during the error 6773 * recovery process. At this time, the only outstanding command is 6774 * supposed to be REQUEST SENSE command or READ LOG EXT command. 6775 */ 6776 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6777 AHCIDBG4(AHCIDBG_ERRS|AHCIDBG_TIMEOUT, ahci_ctlp, 6778 "ahci_timeout_pkts called while REQUEST SENSE " 6779 "command or READ LOG EXT command for error recovery " 6780 "timed out timeout_tags = 0x%x, slot_status = 0x%x, " 6781 "pending_tags = 0x%x, pending_ncq_tags = 0x%x", 6782 tmp_timeout_tags, slot_status, 6783 ahci_portp->ahciport_pending_tags, 6784 ahci_portp->ahciport_pending_ncq_tags); 6785 ASSERT(slot_status == 0x1); 6786 } 6787 #endif 6788 6789 ahci_portp->ahciport_flags |= AHCI_PORT_FLAG_MOPPING; 6790 ahci_portp->ahciport_mop_in_progress++; 6791 6792 (void) ahci_restart_port_wait_till_ready(ahci_ctlp, ahci_portp, 6793 port, NULL, NULL); 6794 6795 /* 6796 * Re-identify timeout tags because some previously checked commands 6797 * could already complete. 6798 */ 6799 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6800 finished_tags = ahci_portp->ahciport_pending_tags & 6801 ~slot_status & AHCI_SLOT_MASK(ahci_ctlp); 6802 timeout_tags = tmp_timeout_tags & ~finished_tags; 6803 6804 AHCIDBG5(AHCIDBG_TIMEOUT, ahci_ctlp, 6805 "ahci_timeout_pkts: port %d, finished_tags = 0x%x, " 6806 "timeout_tags = 0x%x, port_cmd_issue = 0x%x, " 6807 "pending_tags = 0x%x ", 6808 port, finished_tags, timeout_tags, 6809 slot_status, ahci_portp->ahciport_pending_tags); 6810 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6811 finished_tags = ahci_portp->ahciport_pending_ncq_tags & 6812 ~slot_status & AHCI_NCQ_SLOT_MASK(ahci_portp); 6813 timeout_tags = tmp_timeout_tags & ~finished_tags; 6814 6815 AHCIDBG5(AHCIDBG_TIMEOUT|AHCIDBG_NCQ, ahci_ctlp, 6816 "ahci_timeout_pkts: port %d, finished_tags = 0x%x, " 6817 "timeout_tags = 0x%x, port_sactive = 0x%x, " 6818 "pending_ncq_tags = 0x%x ", 6819 port, finished_tags, timeout_tags, 6820 slot_status, ahci_portp->ahciport_pending_ncq_tags); 6821 } else if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6822 timeout_tags = tmp_timeout_tags; 6823 } 6824 6825 ahci_mop_commands(ahci_ctlp, 6826 ahci_portp, 6827 slot_status, 6828 0, /* failed tags */ 6829 timeout_tags, /* timeout tags */ 6830 0, /* aborted tags */ 6831 0); /* reset tags */ 6832 6833 mutex_exit(&ahci_portp->ahciport_mutex); 6834 } 6835 6836 /* 6837 * Watchdog handler kicks in every 5 seconds to timeout any commands pending 6838 * for long time. 6839 */ 6840 static void 6841 ahci_watchdog_handler(ahci_ctl_t *ahci_ctlp) 6842 { 6843 ahci_port_t *ahci_portp; 6844 sata_pkt_t *spkt; 6845 uint32_t pending_tags; 6846 uint32_t timeout_tags; 6847 uint32_t port_cmd_status; 6848 uint32_t port_sactive; 6849 uint8_t port; 6850 int tmp_slot; 6851 int current_slot; 6852 uint32_t current_tags; 6853 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 6854 /* max number of cycles this packet should survive */ 6855 int max_life_cycles; 6856 6857 /* how many cycles this packet survived so far */ 6858 int watched_cycles; 6859 6860 mutex_enter(&ahci_ctlp->ahcictl_mutex); 6861 6862 AHCIDBG0(AHCIDBG_TIMEOUT|AHCIDBG_ENTRY, ahci_ctlp, 6863 "ahci_watchdog_handler entered"); 6864 6865 for (port = 0; port < ahci_ctlp->ahcictl_num_ports; port++) { 6866 if (!AHCI_PORT_IMPLEMENTED(ahci_ctlp, port)) { 6867 continue; 6868 } 6869 6870 ahci_portp = ahci_ctlp->ahcictl_ports[port]; 6871 6872 mutex_enter(&ahci_portp->ahciport_mutex); 6873 if (ahci_portp->ahciport_device_type == SATA_DTYPE_NONE) { 6874 mutex_exit(&ahci_portp->ahciport_mutex); 6875 continue; 6876 } 6877 6878 /* Skip the check for those ports in error recovery */ 6879 if ((ahci_portp->ahciport_flags & AHCI_PORT_FLAG_MOPPING) && 6880 !(ERR_RETRI_CMD_IN_PROGRESS(ahci_portp))) { 6881 mutex_exit(&ahci_portp->ahciport_mutex); 6882 continue; 6883 } 6884 6885 pending_tags = 0; 6886 port_cmd_status = ddi_get32(ahci_ctlp->ahcictl_ahci_acc_handle, 6887 (uint32_t *)AHCI_PORT_PxCMD(ahci_ctlp, port)); 6888 6889 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) { 6890 current_slot = 0; 6891 pending_tags = 0x1; 6892 } else if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6893 current_slot = 6894 (port_cmd_status & AHCI_CMD_STATUS_CCS) >> 6895 AHCI_CMD_STATUS_CCS_SHIFT; 6896 pending_tags = ahci_portp->ahciport_pending_tags; 6897 } else if (NCQ_CMD_IN_PROGRESS(ahci_portp)) { 6898 port_sactive = ddi_get32( 6899 ahci_ctlp->ahcictl_ahci_acc_handle, 6900 (uint32_t *)AHCI_PORT_PxSACT(ahci_ctlp, port)); 6901 current_tags = port_sactive & 6902 ~port_cmd_status & 6903 AHCI_NCQ_SLOT_MASK(ahci_portp); 6904 pending_tags = ahci_portp->ahciport_pending_ncq_tags; 6905 } 6906 6907 timeout_tags = 0; 6908 while (pending_tags) { 6909 tmp_slot = ddi_ffs(pending_tags) - 1; 6910 if (tmp_slot == -1) { 6911 break; 6912 } 6913 6914 if (ERR_RETRI_CMD_IN_PROGRESS(ahci_portp)) 6915 spkt = ahci_portp->ahciport_err_retri_pkt; 6916 else 6917 spkt = ahci_portp->ahciport_slot_pkts[tmp_slot]; 6918 6919 if ((spkt != NULL) && spkt->satapkt_time && 6920 !(spkt->satapkt_op_mode & SATA_OPMODE_POLLING)) { 6921 /* 6922 * We are overloading satapkt_hba_driver_private 6923 * with watched_cycle count. 6924 * 6925 * If a packet has survived for more than it's 6926 * max life cycles, it is a candidate for time 6927 * out. 6928 */ 6929 watched_cycles = (int)(intptr_t) 6930 spkt->satapkt_hba_driver_private; 6931 watched_cycles++; 6932 max_life_cycles = (spkt->satapkt_time + 6933 ahci_watchdog_timeout - 1) / 6934 ahci_watchdog_timeout; 6935 6936 spkt->satapkt_hba_driver_private = 6937 (void *)(intptr_t)watched_cycles; 6938 6939 if (watched_cycles <= max_life_cycles) 6940 goto next; 6941 6942 AHCIDBG1(AHCIDBG_ERRS, ahci_ctlp, 6943 "the current slot is %d", current_slot); 6944 /* 6945 * We need to check whether the HBA has 6946 * begun to execute the command, if not, 6947 * then re-set the timer of the command. 6948 */ 6949 if (NON_NCQ_CMD_IN_PROGRESS(ahci_portp) && 6950 (tmp_slot != current_slot) || 6951 NCQ_CMD_IN_PROGRESS(ahci_portp) && 6952 ((0x1 << tmp_slot) & current_tags)) { 6953 spkt->satapkt_hba_driver_private = 6954 (void *)(intptr_t)0; 6955 } else { 6956 timeout_tags |= (0x1 << tmp_slot); 6957 cmn_err(CE_WARN, "!ahci%d: watchdog " 6958 "port %d satapkt 0x%p timed out\n", 6959 instance, port, (void *)spkt); 6960 } 6961 } 6962 next: 6963 CLEAR_BIT(pending_tags, tmp_slot); 6964 } 6965 6966 if (timeout_tags) { 6967 mutex_exit(&ahci_portp->ahciport_mutex); 6968 mutex_exit(&ahci_ctlp->ahcictl_mutex); 6969 ahci_timeout_pkts(ahci_ctlp, ahci_portp, 6970 port, timeout_tags); 6971 mutex_enter(&ahci_ctlp->ahcictl_mutex); 6972 mutex_enter(&ahci_portp->ahciport_mutex); 6973 } 6974 6975 mutex_exit(&ahci_portp->ahciport_mutex); 6976 } 6977 6978 /* Re-install the watchdog timeout handler */ 6979 if (ahci_ctlp->ahcictl_timeout_id != 0) { 6980 ahci_ctlp->ahcictl_timeout_id = 6981 timeout((void (*)(void *))ahci_watchdog_handler, 6982 (caddr_t)ahci_ctlp, ahci_watchdog_tick); 6983 } 6984 6985 mutex_exit(&ahci_ctlp->ahcictl_mutex); 6986 } 6987 6988 /* 6989 * Fill the error context into sata_cmd for non-queued command error. 6990 */ 6991 static void 6992 ahci_copy_err_cnxt(sata_cmd_t *scmd, ahci_fis_d2h_register_t *rfisp) 6993 { 6994 scmd->satacmd_status_reg = GET_RFIS_STATUS(rfisp); 6995 scmd->satacmd_error_reg = GET_RFIS_ERROR(rfisp); 6996 scmd->satacmd_sec_count_lsb = GET_RFIS_SECTOR_COUNT(rfisp); 6997 scmd->satacmd_lba_low_lsb = GET_RFIS_CYL_LOW(rfisp); 6998 scmd->satacmd_lba_mid_lsb = GET_RFIS_CYL_MID(rfisp); 6999 scmd->satacmd_lba_high_lsb = GET_RFIS_CYL_HI(rfisp); 7000 scmd->satacmd_device_reg = GET_RFIS_DEV_HEAD(rfisp); 7001 7002 if (scmd->satacmd_addr_type == ATA_ADDR_LBA48) { 7003 scmd->satacmd_sec_count_msb = GET_RFIS_SECTOR_COUNT_EXP(rfisp); 7004 scmd->satacmd_lba_low_msb = GET_RFIS_CYL_LOW_EXP(rfisp); 7005 scmd->satacmd_lba_mid_msb = GET_RFIS_CYL_MID_EXP(rfisp); 7006 scmd->satacmd_lba_high_msb = GET_RFIS_CYL_HI_EXP(rfisp); 7007 } 7008 } 7009 7010 /* 7011 * Fill the ncq error page into sata_cmd for queued command error. 7012 */ 7013 static void 7014 ahci_copy_ncq_err_page(sata_cmd_t *scmd, 7015 struct sata_ncq_error_recovery_page *ncq_err_page) 7016 { 7017 scmd->satacmd_sec_count_msb = ncq_err_page->ncq_sector_count_ext; 7018 scmd->satacmd_sec_count_lsb = ncq_err_page->ncq_sector_count; 7019 scmd->satacmd_lba_low_msb = ncq_err_page->ncq_sector_number_ext; 7020 scmd->satacmd_lba_low_lsb = ncq_err_page->ncq_sector_number; 7021 scmd->satacmd_lba_mid_msb = ncq_err_page->ncq_cyl_low_ext; 7022 scmd->satacmd_lba_mid_lsb = ncq_err_page->ncq_cyl_low; 7023 scmd->satacmd_lba_high_msb = ncq_err_page->ncq_cyl_high_ext; 7024 scmd->satacmd_lba_high_lsb = ncq_err_page->ncq_cyl_high; 7025 scmd->satacmd_device_reg = ncq_err_page->ncq_dev_head; 7026 scmd->satacmd_status_reg = ncq_err_page->ncq_status; 7027 scmd->satacmd_error_reg = ncq_err_page->ncq_error; 7028 } 7029 7030 /* 7031 * Put the respective register value to sata_cmd_t for satacmd_flags. 7032 */ 7033 static void 7034 ahci_copy_out_regs(sata_cmd_t *scmd, ahci_fis_d2h_register_t *rfisp) 7035 { 7036 if (scmd->satacmd_flags.sata_copy_out_sec_count_msb) 7037 scmd->satacmd_sec_count_msb = GET_RFIS_SECTOR_COUNT_EXP(rfisp); 7038 if (scmd->satacmd_flags.sata_copy_out_lba_low_msb) 7039 scmd->satacmd_lba_low_msb = GET_RFIS_CYL_LOW_EXP(rfisp); 7040 if (scmd->satacmd_flags.sata_copy_out_lba_mid_msb) 7041 scmd->satacmd_lba_mid_msb = GET_RFIS_CYL_MID_EXP(rfisp); 7042 if (scmd->satacmd_flags.sata_copy_out_lba_high_msb) 7043 scmd->satacmd_lba_high_msb = GET_RFIS_CYL_HI_EXP(rfisp); 7044 if (scmd->satacmd_flags.sata_copy_out_sec_count_lsb) 7045 scmd->satacmd_sec_count_lsb = GET_RFIS_SECTOR_COUNT(rfisp); 7046 if (scmd->satacmd_flags.sata_copy_out_lba_low_lsb) 7047 scmd->satacmd_lba_low_lsb = GET_RFIS_CYL_LOW(rfisp); 7048 if (scmd->satacmd_flags.sata_copy_out_lba_mid_lsb) 7049 scmd->satacmd_lba_mid_lsb = GET_RFIS_CYL_MID(rfisp); 7050 if (scmd->satacmd_flags.sata_copy_out_lba_high_lsb) 7051 scmd->satacmd_lba_high_lsb = GET_RFIS_CYL_HI(rfisp); 7052 if (scmd->satacmd_flags.sata_copy_out_device_reg) 7053 scmd->satacmd_device_reg = GET_RFIS_DEV_HEAD(rfisp); 7054 if (scmd->satacmd_flags.sata_copy_out_error_reg) 7055 scmd->satacmd_error_reg = GET_RFIS_ERROR(rfisp); 7056 } 7057 7058 static void 7059 ahci_log_fatal_error_message(ahci_ctl_t *ahci_ctlp, uint8_t port, 7060 uint32_t intr_status) 7061 { 7062 int instance = ddi_get_instance(ahci_ctlp->ahcictl_dip); 7063 7064 if (intr_status & AHCI_INTR_STATUS_IFS) 7065 cmn_err(CE_WARN, "ahci%d: ahci port %d has interface fatal " 7066 "error", instance, port); 7067 7068 if (intr_status & AHCI_INTR_STATUS_HBDS) 7069 cmn_err(CE_WARN, "ahci%d: ahci port %d has bus data error", 7070 instance, port); 7071 7072 if (intr_status & AHCI_INTR_STATUS_HBFS) 7073 cmn_err(CE_WARN, "ahci%d: ahci port %d has bus fatal error", 7074 instance, port); 7075 7076 if (intr_status & AHCI_INTR_STATUS_TFES) 7077 cmn_err(CE_WARN, "ahci%d: ahci port %d has task file error", 7078 instance, port); 7079 7080 cmn_err(CE_WARN, "ahci%d: ahci port %d is trying to do error " 7081 "recovery", instance, port); 7082 } 7083 7084 /* 7085 * Dump the serror message to the log. 7086 */ 7087 static void 7088 ahci_log_serror_message(ahci_ctl_t *ahci_ctlp, uint8_t port, 7089 uint32_t port_serror, int debug_only) 7090 { 7091 static char err_buf[512]; 7092 static char err_msg_header[16]; 7093 char *err_msg = err_buf; 7094 7095 *err_buf = '\0'; 7096 *err_msg_header = '\0'; 7097 7098 if (port_serror & SERROR_DATA_ERR_FIXED) { 7099 err_msg = strcat(err_msg, 7100 "\tRecovered Data Integrity Error (I)\n"); 7101 } 7102 7103 if (port_serror & SERROR_COMM_ERR_FIXED) { 7104 err_msg = strcat(err_msg, 7105 "\tRecovered Communication Error (M)\n"); 7106 } 7107 7108 if (port_serror & SERROR_DATA_ERR) { 7109 err_msg = strcat(err_msg, 7110 "\tTransient Data Integrity Error (T)\n"); 7111 } 7112 7113 if (port_serror & SERROR_PERSISTENT_ERR) { 7114 err_msg = strcat(err_msg, 7115 "\tPersistent Communication or Data Integrity Error (C)\n"); 7116 } 7117 7118 if (port_serror & SERROR_PROTOCOL_ERR) { 7119 err_msg = strcat(err_msg, "\tProtocol Error (P)\n"); 7120 } 7121 7122 if (port_serror & SERROR_INT_ERR) { 7123 err_msg = strcat(err_msg, "\tInternal Error (E)\n"); 7124 } 7125 7126 if (port_serror & SERROR_PHY_RDY_CHG) { 7127 err_msg = strcat(err_msg, "\tPhyRdy Change (N)\n"); 7128 } 7129 7130 if (port_serror & SERROR_PHY_INT_ERR) { 7131 err_msg = strcat(err_msg, "\tPhy Internal Error (I)\n"); 7132 } 7133 7134 if (port_serror & SERROR_COMM_WAKE) { 7135 err_msg = strcat(err_msg, "\tComm Wake (W)\n"); 7136 } 7137 7138 if (port_serror & SERROR_10B_TO_8B_ERR) { 7139 err_msg = strcat(err_msg, "\t10B to 8B Decode Error (B)\n"); 7140 } 7141 7142 if (port_serror & SERROR_DISPARITY_ERR) { 7143 err_msg = strcat(err_msg, "\tDisparity Error (D)\n"); 7144 } 7145 7146 if (port_serror & SERROR_CRC_ERR) { 7147 err_msg = strcat(err_msg, "\tCRC Error (C)\n"); 7148 } 7149 7150 if (port_serror & SERROR_HANDSHAKE_ERR) { 7151 err_msg = strcat(err_msg, "\tHandshake Error (H)\n"); 7152 } 7153 7154 if (port_serror & SERROR_LINK_SEQ_ERR) { 7155 err_msg = strcat(err_msg, "\tLink Sequence Error (S)\n"); 7156 } 7157 7158 if (port_serror & SERROR_TRANS_ERR) { 7159 err_msg = strcat(err_msg, 7160 "\tTransport state transition error (T)\n"); 7161 } 7162 7163 if (port_serror & SERROR_FIS_TYPE) { 7164 err_msg = strcat(err_msg, "\tUnknown FIS Type (F)\n"); 7165 } 7166 7167 if (port_serror & SERROR_EXCHANGED_ERR) { 7168 err_msg = strcat(err_msg, "\tExchanged (X)\n"); 7169 } 7170 7171 if (err_msg == NULL) 7172 return; 7173 7174 if (debug_only) { 7175 (void) sprintf(err_msg_header, "port %d", port); 7176 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, err_msg_header); 7177 AHCIDBG0(AHCIDBG_ERRS, ahci_ctlp, err_msg); 7178 } else if (ahci_ctlp) { 7179 cmn_err(CE_WARN, "ahci%d: %s %s", 7180 ddi_get_instance(ahci_ctlp->ahcictl_dip), 7181 err_msg_header, err_msg); 7182 } else { 7183 cmn_err(CE_WARN, "ahci: %s %s", err_msg_header, err_msg); 7184 } 7185 } 7186 7187 /* 7188 * This routine is to calculate the total number of ports implemented 7189 * by the HBA. 7190 */ 7191 static int 7192 ahci_get_num_implemented_ports(uint32_t ports_implemented) 7193 { 7194 uint8_t i; 7195 int num = 0; 7196 7197 for (i = 0; i < AHCI_MAX_PORTS; i++) { 7198 if (((uint32_t)0x1 << i) & ports_implemented) 7199 num++; 7200 } 7201 7202 return (num); 7203 } 7204 7205 #if AHCI_DEBUG 7206 static void 7207 ahci_log(ahci_ctl_t *ahci_ctlp, uint_t level, char *fmt, ...) 7208 { 7209 static char name[16]; 7210 va_list ap; 7211 7212 mutex_enter(&ahci_log_mutex); 7213 7214 va_start(ap, fmt); 7215 if (ahci_ctlp) { 7216 (void) sprintf(name, "ahci%d: ", 7217 ddi_get_instance(ahci_ctlp->ahcictl_dip)); 7218 } else { 7219 (void) sprintf(name, "ahci: "); 7220 } 7221 7222 (void) vsprintf(ahci_log_buf, fmt, ap); 7223 va_end(ap); 7224 7225 cmn_err(level, "%s%s", name, ahci_log_buf); 7226 7227 mutex_exit(&ahci_log_mutex); 7228 } 7229 #endif 7230