1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 28 29 30 /* 31 * SiliconImage 3124/3132 sata controller driver 32 */ 33 34 /* 35 * 36 * 37 * Few Design notes 38 * 39 * 40 * I. General notes 41 * 42 * Even though the driver is named as si3124, it is actually meant to 43 * work with both 3124 and 3132 controllers. 44 * 45 * The current file si3124.c is the main driver code. The si3124reg.h 46 * holds the register definitions from SiI 3124/3132 data sheets. The 47 * si3124var.h holds the driver specific definitions which are not 48 * directly derived from data sheets. 49 * 50 * 51 * II. Data structures 52 * 53 * si_ctl_state_t: This holds the driver private information for each 54 * controller instance. Each of the sata ports within a single 55 * controller are represented by si_port_state_t. The 56 * sictl_global_acc_handle and sictl_global_address map the 57 * controller-wide global register space and are derived from pci 58 * BAR 0. The sictl_port_acc_handle and sictl_port_addr map the 59 * per-port register space and are derived from pci BAR 1. 60 * 61 * si_port_state_t: This holds the per port information. The siport_mutex 62 * holds the per port mutex. The siport_pending_tags is the bit mask of 63 * commands posted to controller. The siport_slot_pkts[] holds the 64 * pending sata packets. The siport_port_type holds the device type 65 * connected directly to the port while the siport_portmult_state 66 * holds the similar information for the devices behind a port 67 * multiplier. 68 * 69 * si_prb_t: This contains the PRB being posted to the controller. 70 * The two SGE entries contained within si_prb_t itself are not 71 * really used to hold any scatter gather entries. The scatter gather 72 * list is maintained external to PRB and is linked from one 73 * of the contained SGEs inside the PRB. For atapi devices, the 74 * first contained SGE holds the PACKET and second contained 75 * SGE holds the link to an external SGT. For non-atapi devices, 76 * the first contained SGE works as link to external SGT while 77 * second SGE is blank. 78 * 79 * external SGT tables: The external SGT tables pointed to from 80 * within si_prb_t are actually abstracted as si_sgblock_t. Each 81 * si_sgblock_t contains SI_MAX_SGT_TABLES_PER_PRB number of 82 * SGT tables linked in a chain. Currently this max value of 83 * SGT tables per block is hard coded as 10 which translates 84 * to a maximum of 31 dma cookies per single dma transfer. 85 * 86 * 87 * III. Driver operation 88 * 89 * Command Issuing: We use the "indirect method of command issuance". The 90 * PRB contains the command [and atapi PACKET] and a link to the 91 * external SGT chain. We write the physical address of the PRB into 92 * command activation register. There are 31 command slots for 93 * each port. After posting a command, we remember the posted slot & 94 * the sata packet in siport_pending_tags & siport_slot_pkts[] 95 * respectively. 96 * 97 * Command completion: On a successful completion, intr_command_complete() 98 * receives the control. The slot_status register holds the outstanding 99 * commands. Any reading of slot_status register automatically clears 100 * the interrupt. By comparing the slot_status register contents with 101 * per port siport_pending_tags, we determine which of the previously 102 * posted commands have finished. 103 * 104 * Timeout handling: Every 5 seconds, the watchdog handler scans thru the 105 * pending packets. The satapkt->satapkt_hba_driver_private field is 106 * overloaded with the count of watchdog cycles a packet has survived. 107 * If a packet has not completed within satapkt->satapkt_time, it is 108 * failed with error code of SATA_PKT_TIMEOUT. There is one watchdog 109 * handler running for each instance of controller. 110 * 111 * Error handling: For 3124, whenever any single command has encountered 112 * an error, the whole port execution completely stalls; there is no 113 * way of canceling or aborting the particular failed command. If 114 * the port is connected to a port multiplier, we can however RESUME 115 * other non-error devices connected to the port multiplier. 116 * The only way to recover the failed commands is to either initialize 117 * the port or reset the port/device. Both port initialize and reset 118 * operations result in discarding any of pending commands on the port. 119 * All such discarded commands are sent up to framework with PKT_RESET 120 * satapkt_reason. The assumption is that framework [and sd] would 121 * retry these commands again. The failed command itself however is 122 * sent up with PKT_DEV_ERROR. 123 * 124 * Here is the implementation strategy based on SiliconImage email 125 * regarding how they handle the errors for their Windows driver: 126 * 127 * a) for DEVICEERROR: 128 * If the port is connected to port multiplier, then 129 * 1) Resume the port 130 * 2) Wait for all the non-failed commands to complete 131 * 3) Perform a Port Initialize 132 * 133 * If the port is not connected to port multiplier, issue 134 * a Port Initialize. 135 * 136 * b) for SDBERROR: [SDBERROR means failed command is an NCQ command] 137 * Handle exactly like DEVICEERROR handling. 138 * After the Port Initialize done, do a Read Log Extended. 139 * 140 * c) for SENDFISERROR: 141 * If the port is connected to port multiplier, then 142 * 1) Resume the port 143 * 2) Wait for all the non-failed commands to complete 144 * 3) Perform a Port Initialize 145 * 146 * If the port is not connected to port multiplier, issue 147 * a Device Reset. 148 * 149 * d) for DATAFISERROR: 150 * If the port was executing an NCQ command, issue a Device 151 * Reset. 152 * 153 * Otherwise, follow the same error recovery as DEVICEERROR. 154 * 155 * e) for any other error, simply issue a Device Reset. 156 * 157 * To synchronize the interactions between various control flows (e.g. 158 * error recovery, timeout handling, si_poll_timeout, incoming flow 159 * from framework etc.), the following precautions are taken care of: 160 * a) During mopping_in_progress, no more commands are 161 * accepted from the framework. 162 * 163 * b) While draining the port multiplier commands, we should 164 * handle the possibility of any of the other waited commands 165 * failing (possibly with a different error code) 166 * 167 * Atapi handling: For atapi devices, we use the first SGE within the PRB 168 * to fill the scsi cdb while the second SGE points to external SGT. 169 * 170 * Queuing: Queue management is achieved external to the driver inside sd. 171 * Based on sata_hba_tran->qdepth and IDENTIFY data, the framework 172 * enables or disables the queuing. The qdepth for si3124 is 31 173 * commands. 174 * 175 * Port Multiplier: Enumeration of port multiplier is handled during the 176 * controller initialization and also during the a hotplug operation. 177 * Current logic takes care of situation where a port multiplier 178 * is hotplugged into a port which had a cdisk connected previously 179 * and vice versa. 180 * 181 * Register poll timeouts: Currently most of poll timeouts on register 182 * reads is set to 0.5 seconds except for a value of 10 seconds 183 * while reading the device signature. [Such a big timeout values 184 * for device signature were found needed during cold reboots 185 * for devices behind port multiplier]. 186 * 187 * 188 * IV. Known Issues 189 * 190 * 1) Currently the atapi packet length is hard coded to 12 bytes 191 * This is wrong. The framework should determine it just like they 192 * determine ad_cdb_len in legacy atapi.c. It should even reject 193 * init_pkt() for greater CDB lengths. See atapi.c. Revisit this 194 * in 2nd phase of framework project. 195 * 196 * 2) Do real REQUEST SENSE command instead of faking for ATAPI case. 197 * 198 */ 199 200 201 #include <sys/note.h> 202 #include <sys/scsi/scsi.h> 203 #include <sys/pci.h> 204 #include <sys/sata/sata_hba.h> 205 #include <sys/sata/adapters/si3124/si3124reg.h> 206 #include <sys/sata/adapters/si3124/si3124var.h> 207 208 /* 209 * Function prototypes for driver entry points 210 */ 211 static int si_attach(dev_info_t *, ddi_attach_cmd_t); 212 static int si_detach(dev_info_t *, ddi_detach_cmd_t); 213 static int si_getinfo(dev_info_t *, ddi_info_cmd_t, void *, void **); 214 static int si_power(dev_info_t *, int, int); 215 216 /* 217 * Function prototypes for SATA Framework interfaces 218 */ 219 static int si_register_sata_hba_tran(si_ctl_state_t *); 220 static int si_unregister_sata_hba_tran(si_ctl_state_t *); 221 222 static int si_tran_probe_port(dev_info_t *, sata_device_t *); 223 static int si_tran_start(dev_info_t *, sata_pkt_t *spkt); 224 static int si_tran_abort(dev_info_t *, sata_pkt_t *, int); 225 static int si_tran_reset_dport(dev_info_t *, sata_device_t *); 226 static int si_tran_hotplug_port_activate(dev_info_t *, sata_device_t *); 227 static int si_tran_hotplug_port_deactivate(dev_info_t *, sata_device_t *); 228 229 /* 230 * Local function prototypes 231 */ 232 233 static int si_alloc_port_state(si_ctl_state_t *, int); 234 static void si_dealloc_port_state(si_ctl_state_t *, int); 235 static int si_alloc_sgbpool(si_ctl_state_t *, int); 236 static void si_dealloc_sgbpool(si_ctl_state_t *, int); 237 static int si_alloc_prbpool(si_ctl_state_t *, int); 238 static void si_dealloc_prbpool(si_ctl_state_t *, int); 239 240 static void si_find_dev_signature(si_ctl_state_t *, si_port_state_t *, 241 int, int); 242 static void si_poll_cmd(si_ctl_state_t *, si_port_state_t *, int, int, 243 sata_pkt_t *); 244 static int si_claim_free_slot(si_ctl_state_t *, si_port_state_t *, int); 245 static int si_deliver_satapkt(si_ctl_state_t *, si_port_state_t *, int, 246 sata_pkt_t *); 247 248 static int si_initialize_controller(si_ctl_state_t *); 249 static void si_deinititalize_controller(si_ctl_state_t *); 250 static void si_init_port(si_ctl_state_t *, int); 251 static int si_enumerate_port_multiplier(si_ctl_state_t *, 252 si_port_state_t *, int); 253 static int si_read_portmult_reg(si_ctl_state_t *, si_port_state_t *, 254 int, int, int, uint32_t *); 255 static int si_write_portmult_reg(si_ctl_state_t *, si_port_state_t *, 256 int, int, int, uint32_t); 257 static void si_set_sense_data(sata_pkt_t *, int); 258 259 static uint_t si_intr(caddr_t, caddr_t); 260 static int si_intr_command_complete(si_ctl_state_t *, 261 si_port_state_t *, int); 262 static int si_intr_command_error(si_ctl_state_t *, 263 si_port_state_t *, int); 264 static void si_error_recovery_DEVICEERROR(si_ctl_state_t *, 265 si_port_state_t *, int); 266 static void si_error_recovery_SDBERROR(si_ctl_state_t *, 267 si_port_state_t *, int); 268 static void si_error_recovery_DATAFISERROR(si_ctl_state_t *, 269 si_port_state_t *, int); 270 static void si_error_recovery_SENDFISERROR(si_ctl_state_t *, 271 si_port_state_t *, int); 272 static void si_error_recovery_default(si_ctl_state_t *, 273 si_port_state_t *, int); 274 static uint8_t si_read_log_ext(si_ctl_state_t *, 275 si_port_state_t *si_portp, int); 276 static void si_log_error_message(si_ctl_state_t *, int, uint32_t); 277 static int si_intr_port_ready(si_ctl_state_t *, si_port_state_t *, int); 278 static int si_intr_pwr_change(si_ctl_state_t *, si_port_state_t *, int); 279 static int si_intr_phy_ready_change(si_ctl_state_t *, si_port_state_t *, int); 280 static int si_intr_comwake_rcvd(si_ctl_state_t *, si_port_state_t *, int); 281 static int si_intr_unrecognised_fis(si_ctl_state_t *, si_port_state_t *, int); 282 static int si_intr_dev_xchanged(si_ctl_state_t *, si_port_state_t *, int); 283 static int si_intr_decode_err_threshold(si_ctl_state_t *, 284 si_port_state_t *, int); 285 static int si_intr_crc_err_threshold(si_ctl_state_t *, si_port_state_t *, int); 286 static int si_intr_handshake_err_threshold(si_ctl_state_t *, 287 si_port_state_t *, int); 288 static int si_intr_set_devbits_notify(si_ctl_state_t *, si_port_state_t *, int); 289 static void si_handle_attention_raised(si_ctl_state_t *, 290 si_port_state_t *, int); 291 292 static void si_enable_port_interrupts(si_ctl_state_t *, int); 293 static void si_enable_all_interrupts(si_ctl_state_t *); 294 static void si_disable_port_interrupts(si_ctl_state_t *, int); 295 static void si_disable_all_interrupts(si_ctl_state_t *); 296 static void fill_dev_sregisters(si_ctl_state_t *, int, sata_device_t *); 297 static int si_add_legacy_intrs(si_ctl_state_t *); 298 static int si_add_msi_intrs(si_ctl_state_t *); 299 static void si_rem_intrs(si_ctl_state_t *); 300 301 static int si_reset_dport_wait_till_ready(si_ctl_state_t *, 302 si_port_state_t *, int, int); 303 static int si_initialize_port_wait_till_ready(si_ctl_state_t *, int); 304 305 static void si_timeout_pkts(si_ctl_state_t *, si_port_state_t *, int, uint32_t); 306 static void si_watchdog_handler(si_ctl_state_t *); 307 308 static void si_log(si_ctl_state_t *, uint_t, char *, ...); 309 310 static void si_copy_out_regs(sata_cmd_t *, fis_reg_h2d_t *); 311 312 /* 313 * DMA attributes for the data buffer 314 */ 315 316 static ddi_dma_attr_t buffer_dma_attr = { 317 DMA_ATTR_V0, /* dma_attr_version */ 318 0, /* dma_attr_addr_lo: lowest bus address */ 319 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 320 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 321 1, /* dma_attr_align: single byte aligned */ 322 1, /* dma_attr_burstsizes */ 323 1, /* dma_attr_minxfer */ 324 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 325 0xffffffffull, /* dma_attr_seg */ 326 SI_MAX_SGL_LENGTH, /* dma_attr_sgllen */ 327 512, /* dma_attr_granular */ 328 0, /* dma_attr_flags */ 329 }; 330 331 /* 332 * DMA attributes for incore RPB and SGT pool 333 */ 334 static ddi_dma_attr_t prb_sgt_dma_attr = { 335 DMA_ATTR_V0, /* dma_attr_version */ 336 0, /* dma_attr_addr_lo: lowest bus address */ 337 0xffffffffffffffffull, /* dma_attr_addr_hi: highest bus address */ 338 0xffffffffull, /* dma_attr_count_max i.e. for one cookie */ 339 8, /* dma_attr_align: quad word aligned */ 340 1, /* dma_attr_burstsizes */ 341 1, /* dma_attr_minxfer */ 342 0xffffffffull, /* dma_attr_maxxfer i.e. includes all cookies */ 343 0xffffffffull, /* dma_attr_seg */ 344 1, /* dma_attr_sgllen */ 345 1, /* dma_attr_granular */ 346 0, /* dma_attr_flags */ 347 }; 348 349 /* Device access attributes */ 350 static ddi_device_acc_attr_t accattr = { 351 DDI_DEVICE_ATTR_V0, 352 DDI_STRUCTURE_LE_ACC, 353 DDI_STRICTORDER_ACC 354 }; 355 356 357 static struct dev_ops sictl_dev_ops = { 358 DEVO_REV, /* devo_rev */ 359 0, /* refcnt */ 360 si_getinfo, /* info */ 361 nulldev, /* identify */ 362 nulldev, /* probe */ 363 si_attach, /* attach */ 364 si_detach, /* detach */ 365 nodev, /* no reset */ 366 (struct cb_ops *)0, /* driver operations */ 367 NULL, /* bus operations */ 368 si_power, /* power */ 369 ddi_quiesce_not_supported, /* devo_quiesce */ 370 }; 371 372 static sata_tran_hotplug_ops_t si_tran_hotplug_ops = { 373 SATA_TRAN_HOTPLUG_OPS_REV_1, 374 si_tran_hotplug_port_activate, 375 si_tran_hotplug_port_deactivate 376 }; 377 378 379 static int si_watchdog_timeout = 5; /* 5 seconds */ 380 static int si_watchdog_tick; 381 382 extern struct mod_ops mod_driverops; 383 384 static struct modldrv modldrv = { 385 &mod_driverops, /* driverops */ 386 "si3124 driver", 387 &sictl_dev_ops, /* driver ops */ 388 }; 389 390 static struct modlinkage modlinkage = { 391 MODREV_1, 392 &modldrv, 393 NULL 394 }; 395 396 397 /* The following are needed for si_log() */ 398 static kmutex_t si_log_mutex; 399 static char si_log_buf[512]; 400 uint32_t si_debug_flags = 0x0; 401 static int is_msi_supported = 0; 402 403 /* Opaque state pointer to be initialized by ddi_soft_state_init() */ 404 static void *si_statep = NULL; 405 406 /* 407 * si3124 module initialization. 408 * 409 */ 410 int 411 _init(void) 412 { 413 int error; 414 415 error = ddi_soft_state_init(&si_statep, sizeof (si_ctl_state_t), 0); 416 if (error != 0) { 417 return (error); 418 } 419 420 mutex_init(&si_log_mutex, NULL, MUTEX_DRIVER, NULL); 421 422 if ((error = sata_hba_init(&modlinkage)) != 0) { 423 mutex_destroy(&si_log_mutex); 424 ddi_soft_state_fini(&si_statep); 425 return (error); 426 } 427 428 error = mod_install(&modlinkage); 429 if (error != 0) { 430 sata_hba_fini(&modlinkage); 431 mutex_destroy(&si_log_mutex); 432 ddi_soft_state_fini(&si_statep); 433 return (error); 434 } 435 436 si_watchdog_tick = drv_usectohz((clock_t)si_watchdog_timeout * 1000000); 437 438 return (error); 439 } 440 441 /* 442 * si3124 module uninitialize. 443 * 444 */ 445 int 446 _fini(void) 447 { 448 int error; 449 450 error = mod_remove(&modlinkage); 451 if (error != 0) { 452 return (error); 453 } 454 455 /* Remove the resources allocated in _init(). */ 456 sata_hba_fini(&modlinkage); 457 mutex_destroy(&si_log_mutex); 458 ddi_soft_state_fini(&si_statep); 459 460 return (error); 461 } 462 463 /* 464 * _info entry point 465 * 466 */ 467 int 468 _info(struct modinfo *modinfop) 469 { 470 return (mod_info(&modlinkage, modinfop)); 471 } 472 473 474 /* 475 * The attach entry point for dev_ops. 476 * 477 * We initialize the controller, initialize the soft state, register 478 * the interrupt handlers and then register ourselves with sata framework. 479 */ 480 static int 481 si_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 482 { 483 si_ctl_state_t *si_ctlp; 484 int instance; 485 int status; 486 int attach_state; 487 int intr_types; 488 sata_device_t sdevice; 489 490 SIDBG0(SIDBG_INIT|SIDBG_ENTRY, NULL, "si_attach enter"); 491 instance = ddi_get_instance(dip); 492 attach_state = ATTACH_PROGRESS_NONE; 493 494 switch (cmd) { 495 496 case DDI_ATTACH: 497 498 /* Allocate si_softc. */ 499 status = ddi_soft_state_zalloc(si_statep, instance); 500 if (status != DDI_SUCCESS) { 501 goto err_out; 502 } 503 504 si_ctlp = ddi_get_soft_state(si_statep, instance); 505 si_ctlp->sictl_devinfop = dip; 506 507 attach_state |= ATTACH_PROGRESS_STATEP_ALLOC; 508 509 /* Configure pci config space handle. */ 510 status = pci_config_setup(dip, &si_ctlp->sictl_pci_conf_handle); 511 if (status != DDI_SUCCESS) { 512 goto err_out; 513 } 514 515 si_ctlp->sictl_devid = 516 pci_config_get16(si_ctlp->sictl_pci_conf_handle, 517 PCI_CONF_DEVID); 518 if (si_ctlp->sictl_devid == SI3132_DEV_ID) { 519 si_ctlp->sictl_num_ports = SI3132_MAX_PORTS; 520 } else { 521 si_ctlp->sictl_num_ports = SI3124_MAX_PORTS; 522 } 523 524 attach_state |= ATTACH_PROGRESS_CONF_HANDLE; 525 526 /* Now map the bar0; the bar0 contains the global registers. */ 527 status = ddi_regs_map_setup(dip, 528 PCI_BAR0, 529 (caddr_t *)&si_ctlp->sictl_global_addr, 530 0, 531 0, 532 &accattr, 533 &si_ctlp->sictl_global_acc_handle); 534 if (status != DDI_SUCCESS) { 535 goto err_out; 536 } 537 538 attach_state |= ATTACH_PROGRESS_BAR0_MAP; 539 540 /* Now map bar1; the bar1 contains the port registers. */ 541 status = ddi_regs_map_setup(dip, 542 PCI_BAR1, 543 (caddr_t *)&si_ctlp->sictl_port_addr, 544 0, 545 0, 546 &accattr, 547 &si_ctlp->sictl_port_acc_handle); 548 if (status != DDI_SUCCESS) { 549 goto err_out; 550 } 551 552 attach_state |= ATTACH_PROGRESS_BAR1_MAP; 553 554 /* 555 * Disable all the interrupts before adding interrupt 556 * handler(s). The interrupts shall be re-enabled selectively 557 * out of si_init_port(). 558 */ 559 si_disable_all_interrupts(si_ctlp); 560 561 /* Get supported interrupt types. */ 562 if (ddi_intr_get_supported_types(dip, &intr_types) 563 != DDI_SUCCESS) { 564 SIDBG0(SIDBG_INIT, NULL, 565 "ddi_intr_get_supported_types failed"); 566 goto err_out; 567 } 568 569 SIDBG1(SIDBG_INIT, NULL, 570 "ddi_intr_get_supported_types() returned: 0x%x", 571 intr_types); 572 573 if (is_msi_supported && (intr_types & DDI_INTR_TYPE_MSI)) { 574 SIDBG0(SIDBG_INIT, NULL, "Using MSI interrupt type"); 575 576 /* 577 * Try MSI first, but fall back to legacy if MSI 578 * attach fails. 579 */ 580 if (si_add_msi_intrs(si_ctlp) == DDI_SUCCESS) { 581 si_ctlp->sictl_intr_type = DDI_INTR_TYPE_MSI; 582 attach_state |= ATTACH_PROGRESS_INTR_ADDED; 583 SIDBG0(SIDBG_INIT, NULL, 584 "MSI interrupt setup done"); 585 } else { 586 SIDBG0(SIDBG_INIT, NULL, 587 "MSI registration failed " 588 "will try Legacy interrupts"); 589 } 590 } 591 592 if (!(attach_state & ATTACH_PROGRESS_INTR_ADDED) && 593 (intr_types & DDI_INTR_TYPE_FIXED)) { 594 /* 595 * Either the MSI interrupt setup has failed or only 596 * fixed interrupts are available on the system. 597 */ 598 SIDBG0(SIDBG_INIT, NULL, "Using Legacy interrupt type"); 599 600 if (si_add_legacy_intrs(si_ctlp) == DDI_SUCCESS) { 601 si_ctlp->sictl_intr_type = DDI_INTR_TYPE_FIXED; 602 attach_state |= ATTACH_PROGRESS_INTR_ADDED; 603 SIDBG0(SIDBG_INIT, NULL, 604 "Legacy interrupt setup done"); 605 } else { 606 SIDBG0(SIDBG_INIT, NULL, 607 "legacy interrupt setup failed"); 608 goto err_out; 609 } 610 } 611 612 if (!(attach_state & ATTACH_PROGRESS_INTR_ADDED)) { 613 SIDBG0(SIDBG_INIT, NULL, 614 "si3124: No interrupts registered"); 615 goto err_out; 616 } 617 618 619 /* Initialize the mutex. */ 620 mutex_init(&si_ctlp->sictl_mutex, NULL, MUTEX_DRIVER, 621 (void *)(uintptr_t)si_ctlp->sictl_intr_pri); 622 623 attach_state |= ATTACH_PROGRESS_MUTEX_INIT; 624 625 /* 626 * Initialize the controller and driver core. 627 */ 628 si_ctlp->sictl_flags |= SI_ATTACH; 629 status = si_initialize_controller(si_ctlp); 630 si_ctlp->sictl_flags &= ~SI_ATTACH; 631 if (status) { 632 goto err_out; 633 } 634 635 attach_state |= ATTACH_PROGRESS_HW_INIT; 636 637 if (si_register_sata_hba_tran(si_ctlp)) { 638 SIDBG0(SIDBG_INIT, NULL, 639 "si3124: setting sata hba tran failed"); 640 goto err_out; 641 } 642 643 si_ctlp->sictl_timeout_id = timeout( 644 (void (*)(void *))si_watchdog_handler, 645 (caddr_t)si_ctlp, si_watchdog_tick); 646 647 si_ctlp->sictl_power_level = PM_LEVEL_D0; 648 649 return (DDI_SUCCESS); 650 651 case DDI_RESUME: 652 si_ctlp = ddi_get_soft_state(si_statep, instance); 653 654 status = si_initialize_controller(si_ctlp); 655 if (status) { 656 return (DDI_FAILURE); 657 } 658 659 si_ctlp->sictl_timeout_id = timeout( 660 (void (*)(void *))si_watchdog_handler, 661 (caddr_t)si_ctlp, si_watchdog_tick); 662 663 (void) pm_power_has_changed(dip, 0, PM_LEVEL_D0); 664 665 /* Notify SATA framework about RESUME. */ 666 if (sata_hba_attach(si_ctlp->sictl_devinfop, 667 si_ctlp->sictl_sata_hba_tran, 668 DDI_RESUME) != DDI_SUCCESS) { 669 return (DDI_FAILURE); 670 } 671 672 /* 673 * Notify the "framework" that it should reprobe ports to see 674 * if any device got changed while suspended. 675 */ 676 bzero((void *)&sdevice, sizeof (sata_device_t)); 677 sata_hba_event_notify(dip, &sdevice, 678 SATA_EVNT_PWR_LEVEL_CHANGED); 679 SIDBG0(SIDBG_INIT|SIDBG_EVENT, si_ctlp, 680 "sending event up: SATA_EVNT_PWR_LEVEL_CHANGED"); 681 682 (void) pm_idle_component(si_ctlp->sictl_devinfop, 0); 683 684 si_ctlp->sictl_power_level = PM_LEVEL_D0; 685 686 return (DDI_SUCCESS); 687 688 default: 689 return (DDI_FAILURE); 690 691 } 692 693 err_out: 694 if (attach_state & ATTACH_PROGRESS_HW_INIT) { 695 si_ctlp->sictl_flags |= SI_DETACH; 696 /* We want to set SI_DETACH to deallocate all memory */ 697 si_deinititalize_controller(si_ctlp); 698 si_ctlp->sictl_flags &= ~SI_DETACH; 699 } 700 701 if (attach_state & ATTACH_PROGRESS_MUTEX_INIT) { 702 mutex_destroy(&si_ctlp->sictl_mutex); 703 } 704 705 if (attach_state & ATTACH_PROGRESS_INTR_ADDED) { 706 si_rem_intrs(si_ctlp); 707 } 708 709 if (attach_state & ATTACH_PROGRESS_BAR1_MAP) { 710 ddi_regs_map_free(&si_ctlp->sictl_port_acc_handle); 711 } 712 713 if (attach_state & ATTACH_PROGRESS_BAR0_MAP) { 714 ddi_regs_map_free(&si_ctlp->sictl_global_acc_handle); 715 } 716 717 if (attach_state & ATTACH_PROGRESS_CONF_HANDLE) { 718 pci_config_teardown(&si_ctlp->sictl_pci_conf_handle); 719 } 720 721 if (attach_state & ATTACH_PROGRESS_STATEP_ALLOC) { 722 ddi_soft_state_free(si_statep, instance); 723 } 724 725 return (DDI_FAILURE); 726 } 727 728 729 /* 730 * The detach entry point for dev_ops. 731 * 732 * We undo the things we did in si_attach(). 733 */ 734 static int 735 si_detach(dev_info_t *dip, ddi_detach_cmd_t cmd) 736 { 737 si_ctl_state_t *si_ctlp; 738 int instance; 739 740 SIDBG0(SIDBG_INIT|SIDBG_ENTRY, NULL, "si_detach enter"); 741 instance = ddi_get_instance(dip); 742 si_ctlp = ddi_get_soft_state(si_statep, instance); 743 744 switch (cmd) { 745 746 case DDI_DETACH: 747 748 mutex_enter(&si_ctlp->sictl_mutex); 749 750 /* disable the interrupts for an uninterrupted detach */ 751 si_disable_all_interrupts(si_ctlp); 752 753 mutex_exit(&si_ctlp->sictl_mutex); 754 /* unregister from the sata framework. */ 755 if (si_unregister_sata_hba_tran(si_ctlp) != SI_SUCCESS) { 756 si_enable_all_interrupts(si_ctlp); 757 return (DDI_FAILURE); 758 } 759 mutex_enter(&si_ctlp->sictl_mutex); 760 761 /* now cancel the timeout handler. */ 762 si_ctlp->sictl_flags |= SI_NO_TIMEOUTS; 763 (void) untimeout(si_ctlp->sictl_timeout_id); 764 si_ctlp->sictl_flags &= ~SI_NO_TIMEOUTS; 765 766 /* deinitialize the controller. */ 767 si_ctlp->sictl_flags |= SI_DETACH; 768 si_deinititalize_controller(si_ctlp); 769 si_ctlp->sictl_flags &= ~SI_DETACH; 770 771 /* destroy any mutexes */ 772 mutex_exit(&si_ctlp->sictl_mutex); 773 mutex_destroy(&si_ctlp->sictl_mutex); 774 775 /* remove the interrupts */ 776 si_rem_intrs(si_ctlp); 777 778 /* remove the reg maps. */ 779 ddi_regs_map_free(&si_ctlp->sictl_port_acc_handle); 780 ddi_regs_map_free(&si_ctlp->sictl_global_acc_handle); 781 pci_config_teardown(&si_ctlp->sictl_pci_conf_handle); 782 783 /* free the soft state. */ 784 ddi_soft_state_free(si_statep, instance); 785 786 return (DDI_SUCCESS); 787 788 case DDI_SUSPEND: 789 /* Inform SATA framework */ 790 if (sata_hba_detach(dip, cmd) != DDI_SUCCESS) { 791 return (DDI_FAILURE); 792 } 793 794 mutex_enter(&si_ctlp->sictl_mutex); 795 796 /* 797 * Device needs to be at full power in case it is needed to 798 * handle dump(9e) to save CPR state after DDI_SUSPEND 799 * completes. This is OK since presumably power will be 800 * removed anyways. No outstanding transactions should be 801 * on the controller since the children are already quiesed. 802 * 803 * If any ioctls/cfgadm support is added that touches 804 * hardware, those entry points will need to check for 805 * suspend and then block or return errors until resume. 806 * 807 */ 808 if (pm_busy_component(si_ctlp->sictl_devinfop, 0) == 809 DDI_SUCCESS) { 810 mutex_exit(&si_ctlp->sictl_mutex); 811 (void) pm_raise_power(si_ctlp->sictl_devinfop, 0, 812 PM_LEVEL_D0); 813 mutex_enter(&si_ctlp->sictl_mutex); 814 } 815 816 si_deinititalize_controller(si_ctlp); 817 818 si_ctlp->sictl_flags |= SI_NO_TIMEOUTS; 819 (void) untimeout(si_ctlp->sictl_timeout_id); 820 si_ctlp->sictl_flags &= ~SI_NO_TIMEOUTS; 821 822 SIDBG1(SIDBG_POWER, NULL, "si3124%d: DDI_SUSPEND", instance); 823 824 mutex_exit(&si_ctlp->sictl_mutex); 825 826 return (DDI_SUCCESS); 827 828 default: 829 return (DDI_FAILURE); 830 831 } 832 833 } 834 835 static int 836 si_power(dev_info_t *dip, int component, int level) 837 { 838 #ifndef __lock_lint 839 _NOTE(ARGUNUSED(component)) 840 #endif /* __lock_lint */ 841 842 si_ctl_state_t *si_ctlp; 843 int instance = ddi_get_instance(dip); 844 int rval = DDI_SUCCESS; 845 int old_level; 846 sata_device_t sdevice; 847 848 si_ctlp = ddi_get_soft_state(si_statep, instance); 849 850 if (si_ctlp == NULL) { 851 return (DDI_FAILURE); 852 } 853 854 SIDBG0(SIDBG_ENTRY, NULL, "si_power enter"); 855 856 mutex_enter(&si_ctlp->sictl_mutex); 857 old_level = si_ctlp->sictl_power_level; 858 859 switch (level) { 860 case PM_LEVEL_D0: /* fully on */ 861 pci_config_put16(si_ctlp->sictl_pci_conf_handle, 862 PM_CSR(si_ctlp->sictl_devid), PCI_PMCSR_D0); 863 #ifndef __lock_lint 864 delay(drv_usectohz(10000)); 865 #endif /* __lock_lint */ 866 si_ctlp->sictl_power_level = PM_LEVEL_D0; 867 (void) pci_restore_config_regs(si_ctlp->sictl_devinfop); 868 869 SIDBG2(SIDBG_POWER, si_ctlp, 870 "si3124%d: turning power ON. old level %d", 871 instance, old_level); 872 /* 873 * If called from attach, just raise device power, 874 * restore config registers (if they were saved 875 * from a previous detach that lowered power), 876 * and exit. 877 */ 878 if (si_ctlp->sictl_flags & SI_ATTACH) 879 break; 880 881 mutex_exit(&si_ctlp->sictl_mutex); 882 (void) si_initialize_controller(si_ctlp); 883 mutex_enter(&si_ctlp->sictl_mutex); 884 885 si_ctlp->sictl_timeout_id = timeout( 886 (void (*)(void *))si_watchdog_handler, 887 (caddr_t)si_ctlp, si_watchdog_tick); 888 889 bzero((void *)&sdevice, sizeof (sata_device_t)); 890 sata_hba_event_notify( 891 si_ctlp->sictl_sata_hba_tran->sata_tran_hba_dip, 892 &sdevice, SATA_EVNT_PWR_LEVEL_CHANGED); 893 SIDBG0(SIDBG_EVENT|SIDBG_POWER, si_ctlp, 894 "sending event up: PWR_LEVEL_CHANGED"); 895 896 break; 897 898 case PM_LEVEL_D3: /* fully off */ 899 if (!(si_ctlp->sictl_flags & SI_DETACH)) { 900 si_ctlp->sictl_flags |= SI_NO_TIMEOUTS; 901 (void) untimeout(si_ctlp->sictl_timeout_id); 902 si_ctlp->sictl_flags &= ~SI_NO_TIMEOUTS; 903 904 si_deinititalize_controller(si_ctlp); 905 906 si_ctlp->sictl_power_level = PM_LEVEL_D3; 907 } 908 909 (void) pci_save_config_regs(si_ctlp->sictl_devinfop); 910 911 pci_config_put16(si_ctlp->sictl_pci_conf_handle, 912 PM_CSR(si_ctlp->sictl_devid), PCI_PMCSR_D3HOT); 913 914 SIDBG2(SIDBG_POWER, NULL, "si3124%d: turning power OFF. " 915 "old level %d", instance, old_level); 916 917 break; 918 919 default: 920 SIDBG2(SIDBG_POWER, NULL, "si3124%d: turning power OFF. " 921 "old level %d", instance, old_level); 922 rval = DDI_FAILURE; 923 break; 924 } 925 926 mutex_exit(&si_ctlp->sictl_mutex); 927 928 return (rval); 929 } 930 931 932 /* 933 * The info entry point for dev_ops. 934 * 935 */ 936 static int 937 si_getinfo(dev_info_t *dip, ddi_info_cmd_t infocmd, 938 void *arg, 939 void **result) 940 { 941 #ifndef __lock_lint 942 _NOTE(ARGUNUSED(dip)) 943 #endif /* __lock_lint */ 944 si_ctl_state_t *si_ctlp; 945 int instance; 946 dev_t dev; 947 948 dev = (dev_t)arg; 949 instance = getminor(dev); 950 951 switch (infocmd) { 952 case DDI_INFO_DEVT2DEVINFO: 953 si_ctlp = ddi_get_soft_state(si_statep, instance); 954 if (si_ctlp != NULL) { 955 *result = si_ctlp->sictl_devinfop; 956 return (DDI_SUCCESS); 957 } else { 958 *result = NULL; 959 return (DDI_FAILURE); 960 } 961 case DDI_INFO_DEVT2INSTANCE: 962 *(int *)result = instance; 963 break; 964 default: 965 break; 966 } 967 return (DDI_SUCCESS); 968 } 969 970 971 972 /* 973 * Registers the si3124 with sata framework. 974 */ 975 static int 976 si_register_sata_hba_tran(si_ctl_state_t *si_ctlp) 977 { 978 struct sata_hba_tran *sata_hba_tran; 979 980 SIDBG0(SIDBG_INIT|SIDBG_ENTRY, si_ctlp, 981 "si_register_sata_hba_tran entry"); 982 983 mutex_enter(&si_ctlp->sictl_mutex); 984 985 /* Allocate memory for the sata_hba_tran */ 986 sata_hba_tran = kmem_zalloc(sizeof (sata_hba_tran_t), KM_SLEEP); 987 988 sata_hba_tran->sata_tran_hba_rev = SATA_TRAN_HBA_REV; 989 sata_hba_tran->sata_tran_hba_dip = si_ctlp->sictl_devinfop; 990 sata_hba_tran->sata_tran_hba_dma_attr = &buffer_dma_attr; 991 992 sata_hba_tran->sata_tran_hba_num_cports = si_ctlp->sictl_num_ports; 993 sata_hba_tran->sata_tran_hba_features_support = 0; 994 sata_hba_tran->sata_tran_hba_qdepth = SI_NUM_SLOTS; 995 996 sata_hba_tran->sata_tran_probe_port = si_tran_probe_port; 997 sata_hba_tran->sata_tran_start = si_tran_start; 998 sata_hba_tran->sata_tran_abort = si_tran_abort; 999 sata_hba_tran->sata_tran_reset_dport = si_tran_reset_dport; 1000 sata_hba_tran->sata_tran_selftest = NULL; 1001 sata_hba_tran->sata_tran_hotplug_ops = &si_tran_hotplug_ops; 1002 sata_hba_tran->sata_tran_pwrmgt_ops = NULL; 1003 sata_hba_tran->sata_tran_ioctl = NULL; 1004 mutex_exit(&si_ctlp->sictl_mutex); 1005 1006 /* Attach it to SATA framework */ 1007 if (sata_hba_attach(si_ctlp->sictl_devinfop, sata_hba_tran, DDI_ATTACH) 1008 != DDI_SUCCESS) { 1009 kmem_free((void *)sata_hba_tran, sizeof (sata_hba_tran_t)); 1010 return (SI_FAILURE); 1011 } 1012 1013 mutex_enter(&si_ctlp->sictl_mutex); 1014 si_ctlp->sictl_sata_hba_tran = sata_hba_tran; 1015 mutex_exit(&si_ctlp->sictl_mutex); 1016 1017 return (SI_SUCCESS); 1018 } 1019 1020 1021 /* 1022 * Unregisters the si3124 with sata framework. 1023 */ 1024 static int 1025 si_unregister_sata_hba_tran(si_ctl_state_t *si_ctlp) 1026 { 1027 1028 /* Detach from the SATA framework. */ 1029 if (sata_hba_detach(si_ctlp->sictl_devinfop, DDI_DETACH) != 1030 DDI_SUCCESS) { 1031 return (SI_FAILURE); 1032 } 1033 1034 /* Deallocate sata_hba_tran. */ 1035 kmem_free((void *)si_ctlp->sictl_sata_hba_tran, 1036 sizeof (sata_hba_tran_t)); 1037 1038 si_ctlp->sictl_sata_hba_tran = NULL; 1039 1040 return (SI_SUCCESS); 1041 } 1042 1043 /* 1044 * Called by sata framework to probe a port. We return the 1045 * cached information from a previous hardware probe. 1046 * 1047 * The actual hardware probing itself was done either from within 1048 * si_initialize_controller() during the driver attach or 1049 * from a phy ready change interrupt handler. 1050 */ 1051 static int 1052 si_tran_probe_port(dev_info_t *dip, sata_device_t *sd) 1053 { 1054 1055 si_ctl_state_t *si_ctlp; 1056 uint8_t cport = sd->satadev_addr.cport; 1057 uint8_t pmport = sd->satadev_addr.pmport; 1058 uint8_t qual = sd->satadev_addr.qual; 1059 uint8_t port_type; 1060 si_port_state_t *si_portp; 1061 si_portmult_state_t *si_portmultp; 1062 1063 si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip)); 1064 1065 SIDBG3(SIDBG_ENTRY, si_ctlp, 1066 "si_tran_probe_port: cport: 0x%x, pmport: 0x%x, qual: 0x%x", 1067 cport, pmport, qual); 1068 1069 if (cport >= SI_MAX_PORTS) { 1070 sd->satadev_type = SATA_DTYPE_NONE; 1071 sd->satadev_state = SATA_STATE_UNKNOWN; /* invalid port */ 1072 return (SATA_FAILURE); 1073 } 1074 1075 mutex_enter(&si_ctlp->sictl_mutex); 1076 si_portp = si_ctlp->sictl_ports[cport]; 1077 mutex_exit(&si_ctlp->sictl_mutex); 1078 if (si_portp == NULL) { 1079 sd->satadev_type = SATA_DTYPE_NONE; 1080 sd->satadev_state = SATA_STATE_UNKNOWN; 1081 return (SATA_FAILURE); 1082 } 1083 1084 mutex_enter(&si_portp->siport_mutex); 1085 1086 if (qual == SATA_ADDR_PMPORT) { 1087 if (pmport >= si_portp->siport_portmult_state.sipm_num_ports) { 1088 sd->satadev_type = SATA_DTYPE_NONE; 1089 sd->satadev_state = SATA_STATE_UNKNOWN; 1090 mutex_exit(&si_portp->siport_mutex); 1091 return (SATA_FAILURE); 1092 } else { 1093 si_portmultp = &si_portp->siport_portmult_state; 1094 port_type = si_portmultp->sipm_port_type[pmport]; 1095 } 1096 } else { 1097 port_type = si_portp->siport_port_type; 1098 } 1099 1100 switch (port_type) { 1101 1102 case PORT_TYPE_DISK: 1103 sd->satadev_type = SATA_DTYPE_ATADISK; 1104 break; 1105 1106 case PORT_TYPE_ATAPI: 1107 sd->satadev_type = SATA_DTYPE_ATAPICD; 1108 break; 1109 1110 case PORT_TYPE_MULTIPLIER: 1111 sd->satadev_type = SATA_DTYPE_PMULT; 1112 sd->satadev_add_info = 1113 si_portp->siport_portmult_state.sipm_num_ports; 1114 break; 1115 1116 case PORT_TYPE_UNKNOWN: 1117 sd->satadev_type = SATA_DTYPE_UNKNOWN; 1118 break; 1119 1120 default: 1121 /* we don't support any other device types. */ 1122 sd->satadev_type = SATA_DTYPE_NONE; 1123 break; 1124 } 1125 sd->satadev_state = SATA_STATE_READY; 1126 1127 if (qual == SATA_ADDR_PMPORT) { 1128 (void) si_read_portmult_reg(si_ctlp, si_portp, cport, 1129 pmport, PSCR_REG0, &sd->satadev_scr.sstatus); 1130 (void) si_read_portmult_reg(si_ctlp, si_portp, cport, 1131 pmport, PSCR_REG1, &sd->satadev_scr.serror); 1132 (void) si_read_portmult_reg(si_ctlp, si_portp, cport, 1133 pmport, PSCR_REG2, &sd->satadev_scr.scontrol); 1134 (void) si_read_portmult_reg(si_ctlp, si_portp, cport, 1135 pmport, PSCR_REG3, &sd->satadev_scr.sactive); 1136 } else { 1137 fill_dev_sregisters(si_ctlp, cport, sd); 1138 if (!(si_portp->siport_active)) { 1139 /* 1140 * Since we are implementing the port deactivation 1141 * in software only, we need to fake a valid value 1142 * for sstatus when the device is in deactivated state. 1143 */ 1144 SSTATUS_SET_DET(sd->satadev_scr.sstatus, 1145 SSTATUS_DET_PHYOFFLINE); 1146 SSTATUS_SET_IPM(sd->satadev_scr.sstatus, 1147 SSTATUS_IPM_NODEV_NOPHY); 1148 sd->satadev_state = SATA_PSTATE_SHUTDOWN; 1149 } 1150 } 1151 1152 mutex_exit(&si_portp->siport_mutex); 1153 return (SATA_SUCCESS); 1154 } 1155 1156 /* 1157 * Called by sata framework to transport a sata packet down stream. 1158 * 1159 * The actual work of building the FIS & transporting it to the hardware 1160 * is done out of the subroutine si_deliver_satapkt(). 1161 */ 1162 static int 1163 si_tran_start(dev_info_t *dip, sata_pkt_t *spkt) 1164 { 1165 si_ctl_state_t *si_ctlp; 1166 uint8_t cport; 1167 si_port_state_t *si_portp; 1168 int slot; 1169 1170 cport = spkt->satapkt_device.satadev_addr.cport; 1171 si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip)); 1172 mutex_enter(&si_ctlp->sictl_mutex); 1173 si_portp = si_ctlp->sictl_ports[cport]; 1174 mutex_exit(&si_ctlp->sictl_mutex); 1175 1176 SIDBG1(SIDBG_ENTRY, si_ctlp, 1177 "si_tran_start entry: port: 0x%x", cport); 1178 1179 mutex_enter(&si_portp->siport_mutex); 1180 1181 if ((si_portp->siport_port_type == PORT_TYPE_NODEV) || 1182 !si_portp->siport_active) { 1183 /* 1184 * si_intr_phy_ready_change() may have rendered it to 1185 * PORT_TYPE_NODEV. cfgadm operation may have rendered 1186 * it inactive. 1187 */ 1188 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1189 fill_dev_sregisters(si_ctlp, cport, &spkt->satapkt_device); 1190 mutex_exit(&si_portp->siport_mutex); 1191 return (SATA_TRAN_PORT_ERROR); 1192 } 1193 1194 if (spkt->satapkt_cmd.satacmd_flags.sata_clear_dev_reset) { 1195 si_portp->siport_reset_in_progress = 0; 1196 SIDBG1(SIDBG_ENTRY, si_ctlp, 1197 "si_tran_start clearing the " 1198 "reset_in_progress for port: 0x%x", cport); 1199 } 1200 1201 if (si_portp->siport_reset_in_progress && 1202 ! spkt->satapkt_cmd.satacmd_flags.sata_ignore_dev_reset && 1203 ! ddi_in_panic()) { 1204 1205 spkt->satapkt_reason = SATA_PKT_BUSY; 1206 SIDBG1(SIDBG_ERRS, si_ctlp, 1207 "si_tran_start returning BUSY while " 1208 "reset in progress: port: 0x%x", cport); 1209 mutex_exit(&si_portp->siport_mutex); 1210 return (SATA_TRAN_BUSY); 1211 } 1212 1213 if (si_portp->mopping_in_progress) { 1214 spkt->satapkt_reason = SATA_PKT_BUSY; 1215 SIDBG1(SIDBG_ERRS, si_ctlp, 1216 "si_tran_start returning BUSY while " 1217 "mopping in progress: port: 0x%x", cport); 1218 mutex_exit(&si_portp->siport_mutex); 1219 return (SATA_TRAN_BUSY); 1220 } 1221 1222 if ((slot = si_deliver_satapkt(si_ctlp, si_portp, cport, spkt)) 1223 == SI_FAILURE) { 1224 spkt->satapkt_reason = SATA_PKT_QUEUE_FULL; 1225 SIDBG1(SIDBG_ERRS, si_ctlp, 1226 "si_tran_start returning QUEUE_FULL: port: 0x%x", 1227 cport); 1228 mutex_exit(&si_portp->siport_mutex); 1229 return (SATA_TRAN_QUEUE_FULL); 1230 } 1231 1232 if (spkt->satapkt_op_mode & (SATA_OPMODE_POLLING|SATA_OPMODE_SYNCH)) { 1233 /* we need to poll now */ 1234 mutex_exit(&si_portp->siport_mutex); 1235 si_poll_cmd(si_ctlp, si_portp, cport, slot, spkt); 1236 mutex_enter(&si_portp->siport_mutex); 1237 } 1238 1239 mutex_exit(&si_portp->siport_mutex); 1240 return (SATA_TRAN_ACCEPTED); 1241 } 1242 1243 #define SENDUP_PACKET(si_portp, satapkt, reason) \ 1244 if ((satapkt->satapkt_cmd.satacmd_cmd_reg == \ 1245 SATAC_WRITE_FPDMA_QUEUED) || \ 1246 (satapkt->satapkt_cmd.satacmd_cmd_reg == \ 1247 SATAC_READ_FPDMA_QUEUED)) { \ 1248 si_portp->siport_pending_ncq_count--; \ 1249 } \ 1250 if (satapkt) { \ 1251 satapkt->satapkt_reason = reason; \ 1252 /* \ 1253 * We set the satapkt_reason in both synch and \ 1254 * non-synch cases. \ 1255 */ \ 1256 } \ 1257 if (satapkt && \ 1258 !(satapkt->satapkt_op_mode & SATA_OPMODE_SYNCH) && \ 1259 satapkt->satapkt_comp) { \ 1260 mutex_exit(&si_portp->siport_mutex); \ 1261 (*satapkt->satapkt_comp)(satapkt); \ 1262 mutex_enter(&si_portp->siport_mutex); \ 1263 } 1264 1265 /* 1266 * Mopping is necessitated because of the si3124 hardware limitation. 1267 * The only way to recover from errors or to abort a command is to 1268 * reset the port/device but such a reset also results in throwing 1269 * away all the unfinished pending commands. 1270 * 1271 * A port or device is reset in four scenarios: 1272 * a) some commands failed with errors 1273 * b) or we need to timeout some commands 1274 * c) or we need to abort some commands 1275 * d) or we need reset the port at the request of sata framework 1276 * 1277 * In all these scenarios, we need to send any pending unfinished 1278 * commands up to sata framework. 1279 * 1280 * Only one mopping process at a time is allowed; this is achieved 1281 * by using siport_mop_mutex. 1282 */ 1283 static void 1284 si_mop_commands(si_ctl_state_t *si_ctlp, 1285 si_port_state_t *si_portp, 1286 uint8_t port, 1287 1288 uint32_t slot_status, 1289 uint32_t failed_tags, 1290 uint32_t timedout_tags, 1291 uint32_t aborting_tags, 1292 uint32_t reset_tags) 1293 { 1294 uint32_t finished_tags, unfinished_tags; 1295 int tmpslot; 1296 sata_pkt_t *satapkt; 1297 si_prb_t *prb; 1298 uint32_t *prb_word_ptr; 1299 int i; 1300 1301 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 1302 "si_mop_commands entered: slot_status: 0x%x", 1303 slot_status); 1304 1305 SIDBG4(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 1306 "si_mop_commands: failed_tags: 0x%x, timedout_tags: 0x%x" 1307 "aborting_tags: 0x%x, reset_tags: 0x%x", 1308 failed_tags, 1309 timedout_tags, 1310 aborting_tags, 1311 reset_tags); 1312 /* 1313 * We could be here for four reasons: abort, reset, 1314 * timeout or error handling. Only one such mopping 1315 * is allowed at a time. 1316 * 1317 * Note that we are already holding the main per port 1318 * mutex; all we need now is siport_mop_mutex. 1319 */ 1320 mutex_enter(&si_portp->siport_mop_mutex); 1321 mutex_enter(&si_portp->siport_mutex); 1322 1323 si_portp->mopping_in_progress = 1; 1324 1325 finished_tags = si_portp->siport_pending_tags & 1326 ~slot_status & SI_SLOT_MASK; 1327 1328 unfinished_tags = slot_status & SI_SLOT_MASK & 1329 ~failed_tags & 1330 ~aborting_tags & 1331 ~reset_tags & 1332 ~timedout_tags; 1333 1334 /* Send up the finished_tags with SATA_PKT_COMPLETED. */ 1335 while (finished_tags) { 1336 tmpslot = ddi_ffs(finished_tags) - 1; 1337 if (tmpslot == -1) { 1338 break; 1339 } 1340 1341 satapkt = si_portp->siport_slot_pkts[tmpslot]; 1342 ASSERT(satapkt != NULL); 1343 prb = &si_portp->siport_prbpool[tmpslot]; 1344 ASSERT(prb != NULL); 1345 satapkt->satapkt_cmd.satacmd_status_reg = 1346 GET_FIS_COMMAND(prb->prb_fis); 1347 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) 1348 si_copy_out_regs(&satapkt->satapkt_cmd, &prb->prb_fis); 1349 1350 SIDBG1(SIDBG_ERRS, si_ctlp, 1351 "si_mop_commands sending up completed satapkt: %x", 1352 satapkt); 1353 1354 CLEAR_BIT(si_portp->siport_pending_tags, tmpslot); 1355 CLEAR_BIT(finished_tags, tmpslot); 1356 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_COMPLETED); 1357 } 1358 1359 ASSERT(finished_tags == 0); 1360 1361 /* Send up failed_tags with SATA_PKT_DEV_ERROR. */ 1362 while (failed_tags) { 1363 tmpslot = ddi_ffs(failed_tags) - 1; 1364 if (tmpslot == -1) { 1365 break; 1366 } 1367 SIDBG1(SIDBG_ERRS, si_ctlp, "si3124: si_mop_commands: " 1368 "handling failed slot: 0x%x", tmpslot); 1369 1370 satapkt = si_portp->siport_slot_pkts[tmpslot]; 1371 ASSERT(satapkt != NULL); 1372 if (satapkt->satapkt_device.satadev_type == 1373 SATA_DTYPE_ATAPICD) { 1374 si_set_sense_data(satapkt, SATA_PKT_DEV_ERROR); 1375 } 1376 1377 /* 1378 * The LRAM contains the the modified FIS. 1379 * Read the modified FIS to obtain the Error & Status. 1380 */ 1381 prb = &(si_portp->siport_prbpool[tmpslot]); 1382 prb_word_ptr = (uint32_t *)prb; 1383 for (i = 0; i < (sizeof (si_prb_t)/4); i++) { 1384 prb_word_ptr[i] = ddi_get32( 1385 si_ctlp->sictl_port_acc_handle, 1386 (uint32_t *)(PORT_LRAM(si_ctlp, port, 1387 tmpslot)+i*4)); 1388 } 1389 1390 satapkt->satapkt_cmd.satacmd_status_reg = 1391 GET_FIS_COMMAND(prb->prb_fis); 1392 satapkt->satapkt_cmd.satacmd_error_reg = 1393 GET_FIS_FEATURES(prb->prb_fis); 1394 satapkt->satapkt_cmd.satacmd_sec_count_lsb = 1395 GET_FIS_SECTOR_COUNT(prb->prb_fis); 1396 satapkt->satapkt_cmd.satacmd_lba_low_lsb = 1397 GET_FIS_SECTOR(prb->prb_fis); 1398 satapkt->satapkt_cmd.satacmd_lba_mid_lsb = 1399 GET_FIS_CYL_LOW(prb->prb_fis); 1400 satapkt->satapkt_cmd.satacmd_lba_high_lsb = 1401 GET_FIS_CYL_HI(prb->prb_fis); 1402 satapkt->satapkt_cmd.satacmd_device_reg = 1403 GET_FIS_DEV_HEAD(prb->prb_fis); 1404 1405 if (satapkt->satapkt_cmd.satacmd_addr_type == ATA_ADDR_LBA48) { 1406 satapkt->satapkt_cmd.satacmd_sec_count_msb = 1407 GET_FIS_SECTOR_COUNT_EXP(prb->prb_fis); 1408 satapkt->satapkt_cmd.satacmd_lba_low_msb = 1409 GET_FIS_SECTOR_EXP(prb->prb_fis); 1410 satapkt->satapkt_cmd.satacmd_lba_mid_msb = 1411 GET_FIS_CYL_LOW_EXP(prb->prb_fis); 1412 satapkt->satapkt_cmd.satacmd_lba_high_msb = 1413 GET_FIS_CYL_HI_EXP(prb->prb_fis); 1414 } 1415 1416 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) 1417 si_copy_out_regs(&satapkt->satapkt_cmd, &prb->prb_fis); 1418 1419 /* 1420 * In the case of NCQ command failures, the error is 1421 * overwritten by the one obtained from issuing of a 1422 * READ LOG EXTENDED command. 1423 */ 1424 if (si_portp->siport_err_tags_SDBERROR & (1 << tmpslot)) { 1425 satapkt->satapkt_cmd.satacmd_error_reg = 1426 si_read_log_ext(si_ctlp, si_portp, port); 1427 } 1428 1429 CLEAR_BIT(failed_tags, tmpslot); 1430 CLEAR_BIT(si_portp->siport_pending_tags, tmpslot); 1431 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_DEV_ERROR); 1432 } 1433 1434 ASSERT(failed_tags == 0); 1435 1436 /* Send up timedout_tags with SATA_PKT_TIMEOUT. */ 1437 while (timedout_tags) { 1438 tmpslot = ddi_ffs(timedout_tags) - 1; 1439 if (tmpslot == -1) { 1440 break; 1441 } 1442 1443 satapkt = si_portp->siport_slot_pkts[tmpslot]; 1444 ASSERT(satapkt != NULL); 1445 SIDBG1(SIDBG_ERRS, si_ctlp, 1446 "si_mop_commands sending " 1447 "spkt up with PKT_TIMEOUT: %x", 1448 satapkt); 1449 1450 CLEAR_BIT(si_portp->siport_pending_tags, tmpslot); 1451 CLEAR_BIT(timedout_tags, tmpslot); 1452 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_TIMEOUT); 1453 } 1454 1455 ASSERT(timedout_tags == 0); 1456 1457 /* Send up aborting packets with SATA_PKT_ABORTED. */ 1458 while (aborting_tags) { 1459 tmpslot = ddi_ffs(unfinished_tags) - 1; 1460 if (tmpslot == -1) { 1461 break; 1462 } 1463 1464 satapkt = si_portp->siport_slot_pkts[tmpslot]; 1465 ASSERT(satapkt != NULL); 1466 SIDBG1(SIDBG_ERRS, si_ctlp, 1467 "si_mop_commands aborting spkt: %x", 1468 satapkt); 1469 if (satapkt->satapkt_device.satadev_type == 1470 SATA_DTYPE_ATAPICD) { 1471 si_set_sense_data(satapkt, SATA_PKT_ABORTED); 1472 } 1473 1474 CLEAR_BIT(si_portp->siport_pending_tags, tmpslot); 1475 CLEAR_BIT(aborting_tags, tmpslot); 1476 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_ABORTED); 1477 1478 } 1479 1480 ASSERT(aborting_tags == 0); 1481 1482 /* Reset tags are sent up to framework with SATA_PKT_RESET. */ 1483 while (reset_tags) { 1484 tmpslot = ddi_ffs(reset_tags) - 1; 1485 if (tmpslot == -1) { 1486 break; 1487 } 1488 satapkt = si_portp->siport_slot_pkts[tmpslot]; 1489 ASSERT(satapkt != NULL); 1490 SIDBG1(SIDBG_ERRS, si_ctlp, 1491 "si_mop_commands sending PKT_RESET for " 1492 "reset spkt: %x", 1493 satapkt); 1494 1495 CLEAR_BIT(reset_tags, tmpslot); 1496 CLEAR_BIT(si_portp->siport_pending_tags, tmpslot); 1497 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_RESET); 1498 } 1499 1500 ASSERT(reset_tags == 0); 1501 1502 /* Send up the unfinished_tags with SATA_PKT_BUSY. */ 1503 while (unfinished_tags) { 1504 tmpslot = ddi_ffs(unfinished_tags) - 1; 1505 if (tmpslot == -1) { 1506 break; 1507 } 1508 satapkt = si_portp->siport_slot_pkts[tmpslot]; 1509 ASSERT(satapkt != NULL); 1510 SIDBG1(SIDBG_ERRS, si_ctlp, 1511 "si_mop_commands sending PKT_BUSY for " 1512 "retry spkt: %x", 1513 satapkt); 1514 1515 CLEAR_BIT(unfinished_tags, tmpslot); 1516 CLEAR_BIT(si_portp->siport_pending_tags, tmpslot); 1517 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_BUSY); 1518 } 1519 1520 ASSERT(unfinished_tags == 0); 1521 1522 si_portp->mopping_in_progress = 0; 1523 1524 mutex_exit(&si_portp->siport_mutex); 1525 mutex_exit(&si_portp->siport_mop_mutex); 1526 1527 } 1528 1529 /* 1530 * Called by the sata framework to abort the previously sent packet(s). 1531 * 1532 * We reset the device and mop the commands on the port. 1533 */ 1534 static int 1535 si_tran_abort(dev_info_t *dip, sata_pkt_t *spkt, int flag) 1536 { 1537 uint32_t slot_status; 1538 uint8_t port; 1539 int tmpslot; 1540 uint32_t aborting_tags; 1541 uint32_t finished_tags; 1542 si_port_state_t *si_portp; 1543 si_ctl_state_t *si_ctlp; 1544 1545 port = spkt->satapkt_device.satadev_addr.cport; 1546 si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip)); 1547 mutex_enter(&si_ctlp->sictl_mutex); 1548 si_portp = si_ctlp->sictl_ports[port]; 1549 mutex_exit(&si_ctlp->sictl_mutex); 1550 1551 SIDBG1(SIDBG_ENTRY, si_ctlp, "si_tran_abort on port: %x", port); 1552 1553 mutex_enter(&si_portp->siport_mutex); 1554 1555 if ((si_portp->siport_port_type == PORT_TYPE_NODEV) || 1556 !si_portp->siport_active) { 1557 /* 1558 * si_intr_phy_ready_change() may have rendered it to 1559 * PORT_TYPE_NODEV. cfgadm operation may have rendered 1560 * it inactive. 1561 */ 1562 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 1563 fill_dev_sregisters(si_ctlp, port, &spkt->satapkt_device); 1564 mutex_exit(&si_portp->siport_mutex); 1565 return (SATA_FAILURE); 1566 } 1567 1568 if (flag == SATA_ABORT_ALL_PACKETS) { 1569 aborting_tags = si_portp->siport_pending_tags; 1570 } else { 1571 /* 1572 * Need to abort a single packet. 1573 * Search our siport_slot_pkts[] list for matching spkt. 1574 */ 1575 aborting_tags = 0xffffffff; /* 0xffffffff is impossible tag */ 1576 for (tmpslot = 0; tmpslot < SI_NUM_SLOTS; tmpslot++) { 1577 if (si_portp->siport_slot_pkts[tmpslot] == spkt) { 1578 aborting_tags = (0x1 << tmpslot); 1579 break; 1580 } 1581 } 1582 1583 if (aborting_tags == 0xffffffff) { 1584 /* requested packet is not on pending list. */ 1585 fill_dev_sregisters(si_ctlp, port, 1586 &spkt->satapkt_device); 1587 mutex_exit(&si_portp->siport_mutex); 1588 return (SATA_FAILURE); 1589 } 1590 } 1591 1592 1593 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 1594 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 1595 (void) si_reset_dport_wait_till_ready(si_ctlp, si_portp, 1596 port, SI_DEVICE_RESET); 1597 1598 /* 1599 * Compute which have finished and which need to be retried. 1600 * 1601 * The finished tags are siport_pending_tags minus the slot_status. 1602 * The aborting_tags have to be reduced by finished_tags since we 1603 * can't possibly abort a tag which had finished already. 1604 */ 1605 finished_tags = si_portp->siport_pending_tags & 1606 ~slot_status & SI_SLOT_MASK; 1607 aborting_tags &= ~finished_tags; 1608 1609 mutex_exit(&si_portp->siport_mutex); 1610 si_mop_commands(si_ctlp, 1611 si_portp, 1612 port, 1613 slot_status, 1614 0, /* failed_tags */ 1615 0, /* timedout_tags */ 1616 aborting_tags, 1617 0); /* reset_tags */ 1618 mutex_enter(&si_portp->siport_mutex); 1619 1620 fill_dev_sregisters(si_ctlp, port, &spkt->satapkt_device); 1621 mutex_exit(&si_portp->siport_mutex); 1622 return (SATA_SUCCESS); 1623 } 1624 1625 1626 /* 1627 * Used to reject all the pending packets on a port during a reset 1628 * operation. 1629 * 1630 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 1631 * before calling us. 1632 */ 1633 static void 1634 si_reject_all_reset_pkts( 1635 si_ctl_state_t *si_ctlp, 1636 si_port_state_t *si_portp, 1637 int port) 1638 { 1639 uint32_t slot_status; 1640 uint32_t reset_tags; 1641 1642 _NOTE(ASSUMING_PROTECTED(si_portp)) 1643 1644 SIDBG1(SIDBG_ENTRY, si_ctlp, 1645 "si_reject_all_reset_pkts on port: %x", 1646 port); 1647 1648 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 1649 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 1650 1651 /* Compute which tags need to be sent up. */ 1652 reset_tags = slot_status & SI_SLOT_MASK; 1653 1654 mutex_exit(&si_portp->siport_mutex); 1655 si_mop_commands(si_ctlp, 1656 si_portp, 1657 port, 1658 slot_status, 1659 0, /* failed_tags */ 1660 0, /* timedout_tags */ 1661 0, /* aborting_tags */ 1662 reset_tags); 1663 mutex_enter(&si_portp->siport_mutex); 1664 1665 } 1666 1667 1668 /* 1669 * Called by sata framework to reset a port(s) or device. 1670 * 1671 */ 1672 static int 1673 si_tran_reset_dport(dev_info_t *dip, sata_device_t *sd) 1674 { 1675 si_ctl_state_t *si_ctlp; 1676 uint8_t port = sd->satadev_addr.cport; 1677 int i; 1678 si_port_state_t *si_portp; 1679 int retval = SI_SUCCESS; 1680 1681 si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip)); 1682 SIDBG1(SIDBG_ENTRY, si_ctlp, 1683 "si_tran_reset_port entry: port: 0x%x", 1684 port); 1685 1686 switch (sd->satadev_addr.qual) { 1687 case SATA_ADDR_CPORT: 1688 mutex_enter(&si_ctlp->sictl_mutex); 1689 si_portp = si_ctlp->sictl_ports[port]; 1690 mutex_exit(&si_ctlp->sictl_mutex); 1691 1692 mutex_enter(&si_portp->siport_mutex); 1693 retval = si_reset_dport_wait_till_ready(si_ctlp, si_portp, port, 1694 SI_PORT_RESET); 1695 si_reject_all_reset_pkts(si_ctlp, si_portp, port); 1696 mutex_exit(&si_portp->siport_mutex); 1697 1698 break; 1699 1700 case SATA_ADDR_DCPORT: 1701 mutex_enter(&si_ctlp->sictl_mutex); 1702 si_portp = si_ctlp->sictl_ports[port]; 1703 mutex_exit(&si_ctlp->sictl_mutex); 1704 1705 mutex_enter(&si_portp->siport_mutex); 1706 1707 if ((si_portp->siport_port_type == PORT_TYPE_NODEV) || 1708 !si_portp->siport_active) { 1709 mutex_exit(&si_portp->siport_mutex); 1710 retval = SI_FAILURE; 1711 break; 1712 } 1713 1714 retval = si_reset_dport_wait_till_ready(si_ctlp, si_portp, port, 1715 SI_DEVICE_RESET); 1716 si_reject_all_reset_pkts(si_ctlp, si_portp, port); 1717 mutex_exit(&si_portp->siport_mutex); 1718 1719 break; 1720 1721 case SATA_ADDR_CNTRL: 1722 for (i = 0; i < si_ctlp->sictl_num_ports; i++) { 1723 mutex_enter(&si_ctlp->sictl_mutex); 1724 si_portp = si_ctlp->sictl_ports[port]; 1725 mutex_exit(&si_ctlp->sictl_mutex); 1726 1727 mutex_enter(&si_portp->siport_mutex); 1728 retval = si_reset_dport_wait_till_ready(si_ctlp, 1729 si_portp, i, SI_PORT_RESET); 1730 if (retval) { 1731 mutex_exit(&si_portp->siport_mutex); 1732 break; 1733 } 1734 si_reject_all_reset_pkts(si_ctlp, si_portp, port); 1735 mutex_exit(&si_portp->siport_mutex); 1736 } 1737 break; 1738 1739 case SATA_ADDR_PMPORT: 1740 case SATA_ADDR_DPMPORT: 1741 SIDBG0(SIDBG_VERBOSE, si_ctlp, 1742 "port mult reset not implemented yet"); 1743 /* FALLSTHROUGH */ 1744 1745 default: 1746 retval = SI_FAILURE; 1747 1748 } 1749 1750 return (retval); 1751 } 1752 1753 1754 /* 1755 * Called by sata framework to activate a port as part of hotplug. 1756 * 1757 * Note: Not port-mult aware. 1758 */ 1759 static int 1760 si_tran_hotplug_port_activate(dev_info_t *dip, sata_device_t *satadev) 1761 { 1762 si_ctl_state_t *si_ctlp; 1763 si_port_state_t *si_portp; 1764 uint8_t port; 1765 1766 si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip)); 1767 port = satadev->satadev_addr.cport; 1768 mutex_enter(&si_ctlp->sictl_mutex); 1769 si_portp = si_ctlp->sictl_ports[port]; 1770 mutex_exit(&si_ctlp->sictl_mutex); 1771 1772 SIDBG0(SIDBG_ENTRY, si_ctlp, "si_tran_hotplug_port_activate entry"); 1773 1774 mutex_enter(&si_portp->siport_mutex); 1775 si_enable_port_interrupts(si_ctlp, port); 1776 1777 /* 1778 * Reset the device so that a si_find_dev_signature() would trigger. 1779 * But this reset is an internal operation; the sata framework does 1780 * not need to know about it. 1781 */ 1782 (void) si_reset_dport_wait_till_ready(si_ctlp, si_portp, port, 1783 SI_DEVICE_RESET|SI_RESET_NO_EVENTS_UP); 1784 1785 satadev->satadev_state = SATA_STATE_READY; 1786 1787 si_portp->siport_active = PORT_ACTIVE; 1788 1789 fill_dev_sregisters(si_ctlp, port, satadev); 1790 1791 mutex_exit(&si_portp->siport_mutex); 1792 return (SATA_SUCCESS); 1793 } 1794 1795 /* 1796 * Called by sata framework to deactivate a port as part of hotplug. 1797 * 1798 * Note: Not port-mult aware. 1799 */ 1800 static int 1801 si_tran_hotplug_port_deactivate(dev_info_t *dip, sata_device_t *satadev) 1802 { 1803 si_ctl_state_t *si_ctlp; 1804 si_port_state_t *si_portp; 1805 uint8_t port; 1806 1807 si_ctlp = ddi_get_soft_state(si_statep, ddi_get_instance(dip)); 1808 port = satadev->satadev_addr.cport; 1809 mutex_enter(&si_ctlp->sictl_mutex); 1810 si_portp = si_ctlp->sictl_ports[port]; 1811 mutex_exit(&si_ctlp->sictl_mutex); 1812 1813 SIDBG0(SIDBG_ENTRY, NULL, "si_tran_hotplug_port_deactivate entry"); 1814 1815 mutex_enter(&si_portp->siport_mutex); 1816 if (si_portp->siport_pending_tags & SI_SLOT_MASK) { 1817 /* 1818 * There are pending commands on this port. 1819 * Fail the deactivate request. 1820 */ 1821 satadev->satadev_state = SATA_STATE_READY; 1822 mutex_exit(&si_portp->siport_mutex); 1823 return (SATA_FAILURE); 1824 } 1825 1826 /* mark the device as not accessible any more. */ 1827 si_portp->siport_active = PORT_INACTIVE; 1828 1829 /* disable the interrupts on the port. */ 1830 si_disable_port_interrupts(si_ctlp, port); 1831 1832 satadev->satadev_state = SATA_PSTATE_SHUTDOWN; 1833 1834 fill_dev_sregisters(si_ctlp, port, satadev); 1835 /* 1836 * Since we are implementing the port deactivation in software only, 1837 * we need to fake a valid value for sstatus. 1838 */ 1839 SSTATUS_SET_DET(satadev->satadev_scr.sstatus, SSTATUS_DET_PHYOFFLINE); 1840 SSTATUS_SET_IPM(satadev->satadev_scr.sstatus, SSTATUS_IPM_NODEV_NOPHY); 1841 1842 mutex_exit(&si_portp->siport_mutex); 1843 return (SATA_SUCCESS); 1844 } 1845 1846 1847 /* 1848 * Allocates the si_port_state_t. 1849 */ 1850 static int 1851 si_alloc_port_state(si_ctl_state_t *si_ctlp, int port) 1852 { 1853 si_port_state_t *si_portp; 1854 1855 si_ctlp->sictl_ports[port] = (si_port_state_t *)kmem_zalloc( 1856 sizeof (si_port_state_t), KM_SLEEP); 1857 1858 si_portp = si_ctlp->sictl_ports[port]; 1859 mutex_init(&si_portp->siport_mutex, NULL, MUTEX_DRIVER, 1860 (void *)(uintptr_t)si_ctlp->sictl_intr_pri); 1861 mutex_init(&si_portp->siport_mop_mutex, NULL, MUTEX_DRIVER, 1862 (void *)(uintptr_t)si_ctlp->sictl_intr_pri); 1863 mutex_enter(&si_portp->siport_mutex); 1864 1865 /* allocate prb & sgt pkts for this port. */ 1866 if (si_alloc_prbpool(si_ctlp, port)) { 1867 mutex_exit(&si_portp->siport_mutex); 1868 kmem_free(si_ctlp->sictl_ports[port], sizeof (si_port_state_t)); 1869 return (SI_FAILURE); 1870 } 1871 if (si_alloc_sgbpool(si_ctlp, port)) { 1872 si_dealloc_prbpool(si_ctlp, port); 1873 mutex_exit(&si_portp->siport_mutex); 1874 kmem_free(si_ctlp->sictl_ports[port], sizeof (si_port_state_t)); 1875 return (SI_FAILURE); 1876 } 1877 1878 si_portp->siport_active = PORT_ACTIVE; 1879 mutex_exit(&si_portp->siport_mutex); 1880 1881 return (SI_SUCCESS); 1882 1883 } 1884 1885 /* 1886 * Deallocates the si_port_state_t. 1887 */ 1888 static void 1889 si_dealloc_port_state(si_ctl_state_t *si_ctlp, int port) 1890 { 1891 si_port_state_t *si_portp; 1892 si_portp = si_ctlp->sictl_ports[port]; 1893 1894 mutex_enter(&si_portp->siport_mutex); 1895 si_dealloc_sgbpool(si_ctlp, port); 1896 si_dealloc_prbpool(si_ctlp, port); 1897 mutex_exit(&si_portp->siport_mutex); 1898 1899 mutex_destroy(&si_portp->siport_mutex); 1900 mutex_destroy(&si_portp->siport_mop_mutex); 1901 1902 kmem_free(si_ctlp->sictl_ports[port], sizeof (si_port_state_t)); 1903 1904 } 1905 1906 /* 1907 * Allocates the SGB (Scatter Gather Block) incore buffer. 1908 */ 1909 static int 1910 si_alloc_sgbpool(si_ctl_state_t *si_ctlp, int port) 1911 { 1912 si_port_state_t *si_portp; 1913 uint_t cookie_count; 1914 size_t incore_sgbpool_size = SI_NUM_SLOTS * sizeof (si_sgblock_t); 1915 size_t ret_len; 1916 ddi_dma_cookie_t sgbpool_dma_cookie; 1917 1918 si_portp = si_ctlp->sictl_ports[port]; 1919 1920 /* allocate sgbpool dma handle. */ 1921 if (ddi_dma_alloc_handle(si_ctlp->sictl_devinfop, 1922 &prb_sgt_dma_attr, 1923 DDI_DMA_SLEEP, 1924 NULL, 1925 &si_portp->siport_sgbpool_dma_handle) != 1926 DDI_SUCCESS) { 1927 1928 return (SI_FAILURE); 1929 } 1930 1931 /* allocate the memory for sgbpool. */ 1932 if (ddi_dma_mem_alloc(si_portp->siport_sgbpool_dma_handle, 1933 incore_sgbpool_size, 1934 &accattr, 1935 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 1936 DDI_DMA_SLEEP, 1937 NULL, 1938 (caddr_t *)&si_portp->siport_sgbpool, 1939 &ret_len, 1940 &si_portp->siport_sgbpool_acc_handle) != NULL) { 1941 1942 /* error.. free the dma handle. */ 1943 ddi_dma_free_handle(&si_portp->siport_sgbpool_dma_handle); 1944 return (SI_FAILURE); 1945 } 1946 1947 /* now bind it */ 1948 if (ddi_dma_addr_bind_handle(si_portp->siport_sgbpool_dma_handle, 1949 NULL, 1950 (caddr_t)si_portp->siport_sgbpool, 1951 incore_sgbpool_size, 1952 DDI_DMA_CONSISTENT, 1953 DDI_DMA_SLEEP, 1954 NULL, 1955 &sgbpool_dma_cookie, 1956 &cookie_count) != DDI_DMA_MAPPED) { 1957 /* error.. free the dma handle & free the memory. */ 1958 ddi_dma_mem_free(&si_portp->siport_sgbpool_acc_handle); 1959 ddi_dma_free_handle(&si_portp->siport_sgbpool_dma_handle); 1960 return (SI_FAILURE); 1961 } 1962 1963 si_portp->siport_sgbpool_physaddr = sgbpool_dma_cookie.dmac_laddress; 1964 return (SI_SUCCESS); 1965 } 1966 1967 /* 1968 * Deallocates the SGB (Scatter Gather Block) incore buffer. 1969 */ 1970 static void 1971 si_dealloc_sgbpool(si_ctl_state_t *si_ctlp, int port) 1972 { 1973 si_port_state_t *si_portp = si_ctlp->sictl_ports[port]; 1974 1975 /* Unbind the dma handle first. */ 1976 (void) ddi_dma_unbind_handle(si_portp->siport_sgbpool_dma_handle); 1977 1978 /* Then free the underlying memory. */ 1979 ddi_dma_mem_free(&si_portp->siport_sgbpool_acc_handle); 1980 1981 /* Now free the handle itself. */ 1982 ddi_dma_free_handle(&si_portp->siport_sgbpool_dma_handle); 1983 1984 } 1985 1986 /* 1987 * Allocates the PRB (Port Request Block) incore packets. 1988 */ 1989 static int 1990 si_alloc_prbpool(si_ctl_state_t *si_ctlp, int port) 1991 { 1992 si_port_state_t *si_portp; 1993 uint_t cookie_count; 1994 size_t incore_pkt_size = SI_NUM_SLOTS * sizeof (si_prb_t); 1995 size_t ret_len; 1996 ddi_dma_cookie_t prbpool_dma_cookie; 1997 1998 si_portp = si_ctlp->sictl_ports[port]; 1999 2000 /* allocate prb pkts. */ 2001 if (ddi_dma_alloc_handle(si_ctlp->sictl_devinfop, 2002 &prb_sgt_dma_attr, 2003 DDI_DMA_SLEEP, 2004 NULL, 2005 &si_portp->siport_prbpool_dma_handle) != 2006 DDI_SUCCESS) { 2007 2008 return (SI_FAILURE); 2009 } 2010 2011 if (ddi_dma_mem_alloc(si_portp->siport_prbpool_dma_handle, 2012 incore_pkt_size, 2013 &accattr, 2014 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 2015 DDI_DMA_SLEEP, 2016 NULL, 2017 (caddr_t *)&si_portp->siport_prbpool, 2018 &ret_len, 2019 &si_portp->siport_prbpool_acc_handle) != NULL) { 2020 2021 /* error.. free the dma handle. */ 2022 ddi_dma_free_handle(&si_portp->siport_prbpool_dma_handle); 2023 return (SI_FAILURE); 2024 } 2025 2026 if (ddi_dma_addr_bind_handle(si_portp->siport_prbpool_dma_handle, 2027 NULL, 2028 (caddr_t)si_portp->siport_prbpool, 2029 incore_pkt_size, 2030 DDI_DMA_CONSISTENT, 2031 DDI_DMA_SLEEP, 2032 NULL, 2033 &prbpool_dma_cookie, 2034 &cookie_count) != DDI_DMA_MAPPED) { 2035 /* error.. free the dma handle & free the memory. */ 2036 ddi_dma_mem_free(&si_portp->siport_prbpool_acc_handle); 2037 ddi_dma_free_handle(&si_portp->siport_prbpool_dma_handle); 2038 return (SI_FAILURE); 2039 } 2040 2041 si_portp->siport_prbpool_physaddr = 2042 prbpool_dma_cookie.dmac_laddress; 2043 return (SI_SUCCESS); 2044 } 2045 2046 /* 2047 * Deallocates the PRB (Port Request Block) incore packets. 2048 */ 2049 static void 2050 si_dealloc_prbpool(si_ctl_state_t *si_ctlp, int port) 2051 { 2052 si_port_state_t *si_portp = si_ctlp->sictl_ports[port]; 2053 2054 /* Unbind the prb dma handle first. */ 2055 (void) ddi_dma_unbind_handle(si_portp->siport_prbpool_dma_handle); 2056 2057 /* Then free the underlying memory. */ 2058 ddi_dma_mem_free(&si_portp->siport_prbpool_acc_handle); 2059 2060 /* Now free the handle itself. */ 2061 ddi_dma_free_handle(&si_portp->siport_prbpool_dma_handle); 2062 2063 } 2064 2065 2066 2067 /* 2068 * Soft-reset the port to find the signature of the device connected to 2069 * the port. 2070 */ 2071 static void 2072 si_find_dev_signature( 2073 si_ctl_state_t *si_ctlp, 2074 si_port_state_t *si_portp, 2075 int port, 2076 int pmp) 2077 { 2078 si_prb_t *prb; 2079 uint32_t slot_status, signature; 2080 int slot, loop_count; 2081 2082 SIDBG2(SIDBG_ENTRY|SIDBG_INIT, si_ctlp, 2083 "si_find_dev_signature enter: port: %x, pmp: %x", 2084 port, pmp); 2085 2086 /* Build a Soft Reset PRB in host memory. */ 2087 mutex_enter(&si_portp->siport_mutex); 2088 2089 slot = si_claim_free_slot(si_ctlp, si_portp, port); 2090 if (slot == -1) { 2091 /* Empty slot could not be found. */ 2092 if (pmp != PORTMULT_CONTROL_PORT) { 2093 /* We are behind port multiplier. */ 2094 si_portp->siport_portmult_state.sipm_port_type[pmp] = 2095 PORT_TYPE_NODEV; 2096 } else { 2097 si_portp->siport_port_type = PORT_TYPE_NODEV; 2098 } 2099 2100 mutex_exit(&si_portp->siport_mutex); 2101 return; 2102 } 2103 prb = &si_portp->siport_prbpool[slot]; 2104 bzero((void *)prb, sizeof (si_prb_t)); 2105 2106 SET_FIS_PMP(prb->prb_fis, pmp); 2107 SET_PRB_CONTROL_SOFT_RESET(prb); 2108 2109 #if SI_DEBUG 2110 if (si_debug_flags & SIDBG_DUMP_PRB) { 2111 char *ptr; 2112 int j; 2113 2114 ptr = (char *)prb; 2115 cmn_err(CE_WARN, "si_find_dev_signature, prb: "); 2116 for (j = 0; j < (sizeof (si_prb_t)); j++) { 2117 if (j%4 == 0) { 2118 cmn_err(CE_WARN, "----"); 2119 } 2120 cmn_err(CE_WARN, "%x ", ptr[j]); 2121 } 2122 2123 } 2124 #endif /* SI_DEBUG */ 2125 2126 /* deliver soft reset prb to empty slot. */ 2127 POST_PRB_ADDR(si_ctlp, si_portp, port, slot); 2128 2129 loop_count = 0; 2130 /* Loop till the soft reset is finished. */ 2131 do { 2132 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 2133 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 2134 2135 if (loop_count++ > SI_POLLRATE_SOFT_RESET) { 2136 /* We are effectively timing out after 10 sec. */ 2137 break; 2138 } 2139 2140 /* Wait for 10 millisec */ 2141 #ifndef __lock_lint 2142 delay(SI_10MS_TICKS); 2143 #endif /* __lock_lint */ 2144 2145 } while (slot_status & SI_SLOT_MASK & (0x1 << slot)); 2146 2147 SIDBG2(SIDBG_POLL_LOOP, si_ctlp, 2148 "si_find_dev_signature: loop count: %d, slot_status: 0x%x", 2149 loop_count, slot_status); 2150 2151 CLEAR_BIT(si_portp->siport_pending_tags, slot); 2152 2153 /* Read device signature from command slot. */ 2154 signature = ddi_get32(si_ctlp->sictl_port_acc_handle, 2155 (uint32_t *)(PORT_SIGNATURE_MSB(si_ctlp, port, slot))); 2156 signature <<= 8; 2157 signature |= (0xff & ddi_get32(si_ctlp->sictl_port_acc_handle, 2158 (uint32_t *)(PORT_SIGNATURE_LSB(si_ctlp, 2159 port, slot)))); 2160 2161 SIDBG1(SIDBG_INIT, si_ctlp, "Device signature: 0x%x", signature); 2162 2163 if (signature == SI_SIGNATURE_PORT_MULTIPLIER) { 2164 2165 SIDBG2(SIDBG_INIT, si_ctlp, 2166 "Found multiplier at cport: 0x%d, pmport: 0x%x", 2167 port, pmp); 2168 2169 if (pmp != PORTMULT_CONTROL_PORT) { 2170 /* 2171 * It is wrong to chain a port multiplier behind 2172 * another port multiplier. 2173 */ 2174 si_portp->siport_portmult_state.sipm_port_type[pmp] = 2175 PORT_TYPE_NODEV; 2176 } else { 2177 si_portp->siport_port_type = PORT_TYPE_MULTIPLIER; 2178 mutex_exit(&si_portp->siport_mutex); 2179 (void) si_enumerate_port_multiplier(si_ctlp, 2180 si_portp, port); 2181 mutex_enter(&si_portp->siport_mutex); 2182 } 2183 si_init_port(si_ctlp, port); 2184 2185 } else if (signature == SI_SIGNATURE_ATAPI) { 2186 if (pmp != PORTMULT_CONTROL_PORT) { 2187 /* We are behind port multiplier. */ 2188 si_portp->siport_portmult_state.sipm_port_type[pmp] = 2189 PORT_TYPE_ATAPI; 2190 } else { 2191 si_portp->siport_port_type = PORT_TYPE_ATAPI; 2192 si_init_port(si_ctlp, port); 2193 } 2194 SIDBG2(SIDBG_INIT, si_ctlp, 2195 "Found atapi at : cport: %x, pmport: %x", 2196 port, pmp); 2197 2198 } else if (signature == SI_SIGNATURE_DISK) { 2199 2200 if (pmp != PORTMULT_CONTROL_PORT) { 2201 /* We are behind port multiplier. */ 2202 si_portp->siport_portmult_state.sipm_port_type[pmp] = 2203 PORT_TYPE_DISK; 2204 } else { 2205 si_portp->siport_port_type = PORT_TYPE_DISK; 2206 si_init_port(si_ctlp, port); 2207 } 2208 SIDBG2(SIDBG_INIT, si_ctlp, 2209 "found disk at : cport: %x, pmport: %x", 2210 port, pmp); 2211 2212 } else { 2213 if (pmp != PORTMULT_CONTROL_PORT) { 2214 /* We are behind port multiplier. */ 2215 si_portp->siport_portmult_state.sipm_port_type[pmp] = 2216 PORT_TYPE_UNKNOWN; 2217 } else { 2218 si_portp->siport_port_type = PORT_TYPE_UNKNOWN; 2219 } 2220 SIDBG3(SIDBG_INIT, si_ctlp, 2221 "Found unknown signature 0x%x at: port: %x, pmp: %x", 2222 signature, port, pmp); 2223 } 2224 2225 mutex_exit(&si_portp->siport_mutex); 2226 } 2227 2228 2229 /* 2230 * Polls for the completion of the command. This is safe with both 2231 * interrupts enabled or disabled. 2232 */ 2233 static void 2234 si_poll_cmd( 2235 si_ctl_state_t *si_ctlp, 2236 si_port_state_t *si_portp, 2237 int port, 2238 int slot, 2239 sata_pkt_t *satapkt) 2240 { 2241 uint32_t slot_status; 2242 int pkt_timeout_ticks; 2243 uint32_t port_intr_status; 2244 int in_panic = ddi_in_panic(); 2245 2246 SIDBG1(SIDBG_ENTRY, si_ctlp, "si_poll_cmd entered: port: 0x%x", port); 2247 2248 pkt_timeout_ticks = drv_usectohz((clock_t)satapkt->satapkt_time * 2249 1000000); 2250 2251 mutex_enter(&si_portp->siport_mutex); 2252 2253 /* we start out with SATA_PKT_COMPLETED as the satapkt_reason */ 2254 satapkt->satapkt_reason = SATA_PKT_COMPLETED; 2255 2256 do { 2257 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 2258 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 2259 2260 if (slot_status & SI_SLOT_MASK & (0x1 << slot)) { 2261 if (in_panic) { 2262 /* 2263 * If we are in panic, we can't rely on 2264 * timers; so, busy wait instead of delay(). 2265 */ 2266 mutex_exit(&si_portp->siport_mutex); 2267 drv_usecwait(SI_1MS_USECS); 2268 mutex_enter(&si_portp->siport_mutex); 2269 } else { 2270 mutex_exit(&si_portp->siport_mutex); 2271 #ifndef __lock_lint 2272 delay(SI_1MS_TICKS); 2273 #endif /* __lock_lint */ 2274 mutex_enter(&si_portp->siport_mutex); 2275 } 2276 } else { 2277 break; 2278 } 2279 2280 pkt_timeout_ticks -= SI_1MS_TICKS; 2281 2282 } while (pkt_timeout_ticks > 0); 2283 2284 if (satapkt->satapkt_reason != SATA_PKT_COMPLETED) { 2285 /* The si_mop_command() got to our packet before us */ 2286 goto poll_done; 2287 } 2288 2289 /* 2290 * Interrupts and timers may not be working properly in a crash dump 2291 * situation; we may need to handle all the three conditions here: 2292 * successful completion, packet failure and packet timeout. 2293 */ 2294 if (IS_ATTENTION_RAISED(slot_status)) { /* error seen on port */ 2295 2296 port_intr_status = ddi_get32(si_ctlp->sictl_global_acc_handle, 2297 (uint32_t *)PORT_INTERRUPT_STATUS(si_ctlp, port)); 2298 2299 SIDBG2(SIDBG_VERBOSE, si_ctlp, 2300 "si_poll_cmd: port_intr_status: 0x%x, port: %x", 2301 port_intr_status, port); 2302 2303 if (port_intr_status & INTR_COMMAND_ERROR) { 2304 mutex_exit(&si_portp->siport_mutex); 2305 (void) si_intr_command_error(si_ctlp, si_portp, port); 2306 mutex_enter(&si_portp->siport_mutex); 2307 2308 goto poll_done; 2309 2310 /* 2311 * Why do we need to call si_intr_command_error() ? 2312 * 2313 * Answer: Even if the current packet is not the 2314 * offending command, we need to restart the stalled 2315 * port; (may be, the interrupts are not working well 2316 * in panic condition). The call to routine 2317 * si_intr_command_error() will achieve that. 2318 * 2319 * What if the interrupts are working fine and the 2320 * si_intr_command_error() gets called once more from 2321 * interrupt context ? 2322 * 2323 * Answer: The second instance of routine 2324 * si_intr_command_error() will not mop anything 2325 * since the first error handler has already blown 2326 * away the hardware pending queues through reset. 2327 * 2328 * Will the si_intr_command_error() hurt current 2329 * packet ? 2330 * 2331 * Answer: No. 2332 */ 2333 } else { 2334 /* Ignore any non-error interrupts at this stage */ 2335 ddi_put32(si_ctlp->sictl_port_acc_handle, 2336 (uint32_t *)(PORT_INTERRUPT_STATUS(si_ctlp, 2337 port)), 2338 port_intr_status & INTR_MASK); 2339 } 2340 2341 2342 } else if (slot_status & SI_SLOT_MASK & (0x1 << slot)) { 2343 satapkt->satapkt_reason = SATA_PKT_TIMEOUT; 2344 } /* else: the command completed successfully */ 2345 2346 if ((satapkt->satapkt_cmd.satacmd_cmd_reg == 2347 SATAC_WRITE_FPDMA_QUEUED) || 2348 (satapkt->satapkt_cmd.satacmd_cmd_reg == 2349 SATAC_READ_FPDMA_QUEUED)) { 2350 si_portp->siport_pending_ncq_count--; 2351 } 2352 2353 CLEAR_BIT(si_portp->siport_pending_tags, slot); 2354 2355 poll_done: 2356 mutex_exit(&si_portp->siport_mutex); 2357 2358 /* 2359 * tidbit: What is the interaction of abort with polling ? 2360 * What happens if the current polled pkt is aborted in parallel ? 2361 * 2362 * Answer: Assuming that the si_mop_commands() completes ahead 2363 * of polling, all it does is to set the satapkt_reason to 2364 * SPKT_PKT_ABORTED. That would be fine with us. 2365 * 2366 * The same logic applies to reset interacting with polling. 2367 */ 2368 } 2369 2370 2371 /* 2372 * Searches for and claims a free slot. 2373 * 2374 * Returns: SI_FAILURE if no slots found 2375 * claimed slot number if successful 2376 * 2377 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 2378 * before calling us. 2379 */ 2380 /*ARGSUSED*/ 2381 static int 2382 si_claim_free_slot(si_ctl_state_t *si_ctlp, si_port_state_t *si_portp, int port) 2383 { 2384 uint32_t free_slots; 2385 int slot; 2386 2387 _NOTE(ASSUMING_PROTECTED(si_portp)) 2388 2389 SIDBG1(SIDBG_ENTRY, si_ctlp, 2390 "si_claim_free_slot entry: siport_pending_tags: %x", 2391 si_portp->siport_pending_tags); 2392 2393 free_slots = (~si_portp->siport_pending_tags) & SI_SLOT_MASK; 2394 slot = ddi_ffs(free_slots) - 1; 2395 if (slot == -1) { 2396 SIDBG0(SIDBG_VERBOSE, si_ctlp, 2397 "si_claim_free_slot: no empty slots"); 2398 return (SI_FAILURE); 2399 } 2400 2401 si_portp->siport_pending_tags |= (0x1 << slot); 2402 SIDBG1(SIDBG_VERBOSE, si_ctlp, "si_claim_free_slot: found slot: 0x%x", 2403 slot); 2404 return (slot); 2405 } 2406 2407 /* 2408 * Builds the PRB for the sata packet and delivers it to controller. 2409 * 2410 * Returns: 2411 * slot number if we can obtain a slot successfully 2412 * otherwise, return SI_FAILURE 2413 * 2414 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 2415 * before calling us. 2416 */ 2417 static int 2418 si_deliver_satapkt( 2419 si_ctl_state_t *si_ctlp, 2420 si_port_state_t *si_portp, 2421 int port, 2422 sata_pkt_t *spkt) 2423 { 2424 int slot; 2425 si_prb_t *prb; 2426 sata_cmd_t *cmd; 2427 si_sge_t *sgep; /* scatter gather entry pointer */ 2428 si_sgt_t *sgtp; /* scatter gather table pointer */ 2429 si_sgblock_t *sgbp; /* scatter gather block pointer */ 2430 int i, j, cookie_index; 2431 int ncookies; 2432 int is_atapi = 0; 2433 ddi_dma_cookie_t cookie; 2434 2435 _NOTE(ASSUMING_PROTECTED(si_portp)) 2436 2437 slot = si_claim_free_slot(si_ctlp, si_portp, port); 2438 if (slot == -1) { 2439 return (SI_FAILURE); 2440 } 2441 2442 if (spkt->satapkt_device.satadev_type == SATA_DTYPE_ATAPICD) { 2443 is_atapi = 1; 2444 } 2445 2446 if ((si_portp->siport_port_type == PORT_TYPE_NODEV) || 2447 !si_portp->siport_active) { 2448 /* 2449 * si_intr_phy_ready_change() may have rendered it to 2450 * PORT_TYPE_NODEV. cfgadm operation may have rendered 2451 * it inactive. 2452 */ 2453 spkt->satapkt_reason = SATA_PKT_PORT_ERROR; 2454 fill_dev_sregisters(si_ctlp, port, &spkt->satapkt_device); 2455 2456 return (SI_FAILURE); 2457 } 2458 2459 2460 prb = &(si_portp->siport_prbpool[slot]); 2461 bzero((void *)prb, sizeof (si_prb_t)); 2462 2463 cmd = &spkt->satapkt_cmd; 2464 2465 SIDBG4(SIDBG_ENTRY, si_ctlp, 2466 "si_deliver_satpkt entry: cmd_reg: 0x%x, slot: 0x%x, \ 2467 port: %x, satapkt: %x", 2468 cmd->satacmd_cmd_reg, slot, port, (uint32_t)(intptr_t)spkt); 2469 2470 /* Now fill the prb. */ 2471 if (is_atapi) { 2472 if (spkt->satapkt_cmd.satacmd_flags.sata_data_direction == 2473 SATA_DIR_READ) { 2474 SET_PRB_CONTROL_PKT_READ(prb); 2475 } else if (spkt->satapkt_cmd.satacmd_flags.sata_data_direction 2476 == SATA_DIR_WRITE) { 2477 SET_PRB_CONTROL_PKT_WRITE(prb); 2478 } 2479 } 2480 2481 SET_FIS_TYPE(prb->prb_fis, REGISTER_FIS_H2D); 2482 if ((spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_PMPORT) || 2483 (spkt->satapkt_device.satadev_addr.qual == SATA_ADDR_DPMPORT)) { 2484 SET_FIS_PMP(prb->prb_fis, 2485 spkt->satapkt_device.satadev_addr.pmport); 2486 } 2487 SET_FIS_CDMDEVCTL(prb->prb_fis, 1); 2488 SET_FIS_COMMAND(prb->prb_fis, cmd->satacmd_cmd_reg); 2489 SET_FIS_FEATURES(prb->prb_fis, cmd->satacmd_features_reg); 2490 SET_FIS_SECTOR_COUNT(prb->prb_fis, cmd->satacmd_sec_count_lsb); 2491 2492 switch (cmd->satacmd_addr_type) { 2493 2494 case ATA_ADDR_LBA: 2495 /* fallthru */ 2496 2497 case ATA_ADDR_LBA28: 2498 /* LBA[7:0] */ 2499 SET_FIS_SECTOR(prb->prb_fis, cmd->satacmd_lba_low_lsb); 2500 2501 /* LBA[15:8] */ 2502 SET_FIS_CYL_LOW(prb->prb_fis, cmd->satacmd_lba_mid_lsb); 2503 2504 /* LBA[23:16] */ 2505 SET_FIS_CYL_HI(prb->prb_fis, cmd->satacmd_lba_high_lsb); 2506 2507 /* LBA [27:24] (also called dev_head) */ 2508 SET_FIS_DEV_HEAD(prb->prb_fis, cmd->satacmd_device_reg); 2509 2510 break; 2511 2512 case ATA_ADDR_LBA48: 2513 /* LBA[7:0] */ 2514 SET_FIS_SECTOR(prb->prb_fis, cmd->satacmd_lba_low_lsb); 2515 2516 /* LBA[15:8] */ 2517 SET_FIS_CYL_LOW(prb->prb_fis, cmd->satacmd_lba_mid_lsb); 2518 2519 /* LBA[23:16] */ 2520 SET_FIS_CYL_HI(prb->prb_fis, cmd->satacmd_lba_high_lsb); 2521 2522 /* LBA [31:24] */ 2523 SET_FIS_SECTOR_EXP(prb->prb_fis, cmd->satacmd_lba_low_msb); 2524 2525 /* LBA [39:32] */ 2526 SET_FIS_CYL_LOW_EXP(prb->prb_fis, cmd->satacmd_lba_mid_msb); 2527 2528 /* LBA [47:40] */ 2529 SET_FIS_CYL_HI_EXP(prb->prb_fis, cmd->satacmd_lba_high_msb); 2530 2531 /* Set dev_head */ 2532 SET_FIS_DEV_HEAD(prb->prb_fis, cmd->satacmd_device_reg); 2533 2534 /* Set the extended sector count and features */ 2535 SET_FIS_SECTOR_COUNT_EXP(prb->prb_fis, 2536 cmd->satacmd_sec_count_msb); 2537 SET_FIS_FEATURES_EXP(prb->prb_fis, 2538 cmd->satacmd_features_reg_ext); 2539 2540 break; 2541 2542 } 2543 2544 if (cmd->satacmd_flags.sata_queued) { 2545 /* 2546 * For queued commands, the TAG for the sector count lsb is 2547 * generated from current slot number. 2548 */ 2549 SET_FIS_SECTOR_COUNT(prb->prb_fis, slot << 3); 2550 } 2551 2552 if ((cmd->satacmd_cmd_reg == SATAC_WRITE_FPDMA_QUEUED) || 2553 (cmd->satacmd_cmd_reg == SATAC_READ_FPDMA_QUEUED)) { 2554 si_portp->siport_pending_ncq_count++; 2555 } 2556 2557 /* *** now fill the scatter gather list ******* */ 2558 2559 if (is_atapi) { /* It is an ATAPI drive */ 2560 /* atapi command goes into sge0 */ 2561 bcopy(cmd->satacmd_acdb, &prb->prb_sge0, sizeof (si_sge_t)); 2562 2563 /* Now fill sge1 with pointer to external SGT. */ 2564 if (spkt->satapkt_cmd.satacmd_num_dma_cookies) { 2565 prb->prb_sge1.sge_addr = 2566 si_portp->siport_sgbpool_physaddr + 2567 slot*sizeof (si_sgblock_t); 2568 SET_SGE_LNK(prb->prb_sge1); 2569 } else { 2570 SET_SGE_TRM(prb->prb_sge1); 2571 } 2572 } else { 2573 /* Fill the sge0 */ 2574 if (spkt->satapkt_cmd.satacmd_num_dma_cookies) { 2575 prb->prb_sge0.sge_addr = 2576 si_portp->siport_sgbpool_physaddr + 2577 slot*sizeof (si_sgblock_t); 2578 SET_SGE_LNK(prb->prb_sge0); 2579 2580 } else { 2581 SET_SGE_TRM(prb->prb_sge0); 2582 } 2583 2584 /* sge1 is left empty in non-ATAPI case */ 2585 } 2586 2587 bzero(&si_portp->siport_sgbpool[slot], sizeof (si_sgblock_t)); 2588 2589 ncookies = spkt->satapkt_cmd.satacmd_num_dma_cookies; 2590 ASSERT(ncookies <= SI_MAX_SGL_LENGTH); 2591 2592 SIDBG1(SIDBG_COOKIES, si_ctlp, "total ncookies: %d", ncookies); 2593 if (ncookies == 0) { 2594 sgbp = &si_portp->siport_sgbpool[slot]; 2595 sgtp = &sgbp->sgb_sgt[0]; 2596 sgep = &sgtp->sgt_sge[0]; 2597 2598 /* No cookies. Terminate the chain. */ 2599 SIDBG0(SIDBG_COOKIES, si_ctlp, "empty cookies: terminating."); 2600 2601 sgep->sge_addr_low = 0; 2602 sgep->sge_addr_high = 0; 2603 sgep->sge_data_count = 0; 2604 SET_SGE_TRM((*sgep)); 2605 2606 goto sgl_fill_done; 2607 } 2608 2609 for (i = 0, cookie_index = 0, sgbp = &si_portp->siport_sgbpool[slot]; 2610 i < SI_MAX_SGT_TABLES_PER_PRB; i++) { 2611 2612 sgtp = &sgbp->sgb_sgt[i]; 2613 2614 /* Now fill the first 3 entries of SGT in the loop below. */ 2615 for (j = 0, sgep = &sgtp->sgt_sge[0]; 2616 ((j < 3) && (cookie_index < ncookies-1)); 2617 j++, cookie_index++, sgep++) { 2618 ASSERT(cookie_index < ncookies); 2619 SIDBG2(SIDBG_COOKIES, si_ctlp, 2620 "inner loop: cookie_index: %d, ncookies: %d", 2621 cookie_index, 2622 ncookies); 2623 cookie = spkt->satapkt_cmd. 2624 satacmd_dma_cookie_list[cookie_index]; 2625 2626 sgep->sge_addr_low = cookie._dmu._dmac_la[0]; 2627 sgep->sge_addr_high = cookie._dmu._dmac_la[1]; 2628 sgep->sge_data_count = cookie.dmac_size; 2629 } 2630 2631 /* 2632 * If this happens to be the last cookie, we terminate it here. 2633 * Otherwise, we link to next SGT. 2634 */ 2635 2636 if (cookie_index == ncookies-1) { 2637 /* This is the last cookie. Terminate the chain. */ 2638 SIDBG2(SIDBG_COOKIES, si_ctlp, 2639 "filling the last: cookie_index: %d, " 2640 "ncookies: %d", 2641 cookie_index, 2642 ncookies); 2643 cookie = spkt->satapkt_cmd. 2644 satacmd_dma_cookie_list[cookie_index]; 2645 2646 sgep->sge_addr_low = cookie._dmu._dmac_la[0]; 2647 sgep->sge_addr_high = cookie._dmu._dmac_la[1]; 2648 sgep->sge_data_count = cookie.dmac_size; 2649 SET_SGE_TRM((*sgep)); 2650 2651 break; /* we break the loop */ 2652 2653 } else { 2654 /* This is not the last one. So link it. */ 2655 SIDBG2(SIDBG_COOKIES, si_ctlp, 2656 "linking SGT: cookie_index: %d, ncookies: %d", 2657 cookie_index, 2658 ncookies); 2659 sgep->sge_addr = si_portp->siport_sgbpool_physaddr + 2660 slot * sizeof (si_sgblock_t) + 2661 (i+1) * sizeof (si_sgt_t); 2662 2663 SET_SGE_LNK((*sgep)); 2664 } 2665 2666 } 2667 2668 /* *** finished filling the scatter gather list ******* */ 2669 2670 sgl_fill_done: 2671 /* Now remember the sata packet in siport_slot_pkts[]. */ 2672 si_portp->siport_slot_pkts[slot] = spkt; 2673 2674 /* 2675 * We are overloading satapkt_hba_driver_private with 2676 * watched_cycle count. 2677 */ 2678 spkt->satapkt_hba_driver_private = (void *)(intptr_t)0; 2679 2680 if (is_atapi) { 2681 /* program the packet_lenth if it is atapi device. */ 2682 2683 2684 #ifdef ATAPI_2nd_PHASE 2685 /* 2686 * Framework needs to calculate the acdb_len based on 2687 * identify packet data. This needs to be accomplished 2688 * in second phase of the project. 2689 */ 2690 ASSERT((cmd->satacmd_acdb_len == 12) || 2691 (cmd->satacmd_acdb_len == 16)); 2692 SIDBG1(SIDBG_VERBOSE, si_ctlp, "deliver: acdb_len: %d", 2693 cmd->satacmd_acdb_len); 2694 2695 if (cmd->satacmd_acdb_len == 16) { 2696 ddi_put32(si_ctlp->sictl_port_acc_handle, 2697 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 2698 PORT_CONTROL_SET_BITS_PACKET_LEN); 2699 } else { 2700 ddi_put32(si_ctlp->sictl_port_acc_handle, 2701 (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port), 2702 PORT_CONTROL_CLEAR_BITS_PACKET_LEN); 2703 } 2704 2705 #else /* ATAPI_2nd_PHASE */ 2706 /* hard coding for now to 12 bytes */ 2707 ddi_put32(si_ctlp->sictl_port_acc_handle, 2708 (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port), 2709 PORT_CONTROL_CLEAR_BITS_PACKET_LEN); 2710 #endif /* ATAPI_2nd_PHASE */ 2711 } 2712 2713 2714 #if SI_DEBUG 2715 if (si_debug_flags & SIDBG_DUMP_PRB) { 2716 if (!(is_atapi && (prb->prb_sge0.sge_addr_low == 0))) { 2717 /* 2718 * Do not dump the atapi Test-Unit-Ready commands. 2719 * The sd_media_watch spews too many of these. 2720 */ 2721 int *ptr; 2722 si_sge_t *tmpsgep; 2723 int j; 2724 2725 ptr = (int *)prb; 2726 cmn_err(CE_WARN, "si_deliver_satpkt prb: "); 2727 for (j = 0; j < (sizeof (si_prb_t)/4); j++) { 2728 cmn_err(CE_WARN, "%x ", ptr[j]); 2729 } 2730 2731 cmn_err(CE_WARN, 2732 "si_deliver_satpkt sgt: low, high, count link"); 2733 for (j = 0, 2734 tmpsgep = (si_sge_t *) 2735 &si_portp->siport_sgbpool[slot]; 2736 j < (sizeof (si_sgblock_t)/ sizeof (si_sge_t)); 2737 j++, tmpsgep++) { 2738 ptr = (int *)tmpsgep; 2739 cmn_err(CE_WARN, "%x %x %x %x", 2740 ptr[0], 2741 ptr[1], 2742 ptr[2], 2743 ptr[3]); 2744 if (IS_SGE_TRM_SET((*tmpsgep))) { 2745 break; 2746 } 2747 2748 } 2749 } 2750 2751 } 2752 #endif /* SI_DEBUG */ 2753 2754 /* Deliver PRB */ 2755 POST_PRB_ADDR(si_ctlp, si_portp, port, slot); 2756 2757 return (slot); 2758 } 2759 2760 /* 2761 * Initialize the controller and set up driver data structures. 2762 * 2763 * This routine can be called from three separate cases: DDI_ATTACH, PM_LEVEL_D0 2764 * and DDI_RESUME. The DDI_ATTACH case is different from other two cases; the 2765 * memory allocation & device signature probing are attempted only during 2766 * DDI_ATTACH case. In the case of PM_LEVEL_D0 & DDI_RESUME, we are starting 2767 * from a previously initialized state; so there is no need to allocate memory 2768 * or to attempt probing the device signatures. 2769 */ 2770 static int 2771 si_initialize_controller(si_ctl_state_t *si_ctlp) 2772 { 2773 uint32_t port_status; 2774 uint32_t SStatus; 2775 uint32_t SControl; 2776 int port; 2777 int loop_count = 0; 2778 si_port_state_t *si_portp; 2779 2780 SIDBG0(SIDBG_INIT|SIDBG_ENTRY, si_ctlp, 2781 "si3124: si_initialize_controller entered"); 2782 2783 mutex_enter(&si_ctlp->sictl_mutex); 2784 2785 /* Remove the Global Reset. */ 2786 ddi_put32(si_ctlp->sictl_global_acc_handle, 2787 (uint32_t *)GLOBAL_CONTROL_REG(si_ctlp), 2788 GLOBAL_CONTROL_REG_BITS_CLEAR); 2789 2790 for (port = 0; port < si_ctlp->sictl_num_ports; port++) { 2791 2792 if (si_ctlp->sictl_flags & SI_ATTACH) { 2793 /* 2794 * We allocate the port state only during attach 2795 * sequence. We don't want to do it during 2796 * suspend/resume sequence. 2797 */ 2798 if (si_alloc_port_state(si_ctlp, port)) { 2799 mutex_exit(&si_ctlp->sictl_mutex); 2800 return (SI_FAILURE); 2801 } 2802 } 2803 2804 si_portp = si_ctlp->sictl_ports[port]; 2805 mutex_enter(&si_portp->siport_mutex); 2806 2807 /* Clear Port Reset. */ 2808 ddi_put32(si_ctlp->sictl_port_acc_handle, 2809 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 2810 PORT_CONTROL_SET_BITS_PORT_RESET); 2811 ddi_put32(si_ctlp->sictl_port_acc_handle, 2812 (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port), 2813 PORT_CONTROL_CLEAR_BITS_PORT_RESET); 2814 2815 /* 2816 * Arm the interrupts for: Cmd completion, Cmd error, 2817 * Port Ready, PM Change, PhyRdyChange, Commwake, 2818 * UnrecFIS, Devxchanged, SDBNotify. 2819 */ 2820 ddi_put32(si_ctlp->sictl_port_acc_handle, 2821 (uint32_t *)PORT_INTERRUPT_ENABLE_SET(si_ctlp, port), 2822 (INTR_COMMAND_COMPLETE | 2823 INTR_COMMAND_ERROR | 2824 INTR_PORT_READY | 2825 INTR_POWER_CHANGE | 2826 INTR_PHYRDY_CHANGE | 2827 INTR_COMWAKE_RECEIVED | 2828 INTR_UNRECOG_FIS | 2829 INTR_DEV_XCHANGED | 2830 INTR_SETDEVBITS_NOTIFY)); 2831 2832 /* Now enable the interrupts. */ 2833 si_enable_port_interrupts(si_ctlp, port); 2834 2835 /* 2836 * The following PHY initialization is redundant in 2837 * in x86 since the BIOS anyway does this as part of 2838 * device enumeration during the power up. But this 2839 * is a required step in sparc since there is no BIOS. 2840 * 2841 * The way to initialize the PHY is to write a 1 and then 2842 * a 0 to DET field of SControl register. 2843 */ 2844 2845 /* 2846 * Fetch the current SControl before writing the 2847 * DET part with 1 2848 */ 2849 SControl = ddi_get32(si_ctlp->sictl_port_acc_handle, 2850 (uint32_t *)PORT_SCONTROL(si_ctlp, port)); 2851 SCONTROL_SET_DET(SControl, SCONTROL_DET_COMRESET); 2852 ddi_put32(si_ctlp->sictl_port_acc_handle, 2853 (uint32_t *)(PORT_SCONTROL(si_ctlp, port)), 2854 SControl); 2855 #ifndef __lock_lint 2856 delay(SI_10MS_TICKS); /* give time for COMRESET to percolate */ 2857 #endif /* __lock_lint */ 2858 2859 /* 2860 * Now fetch the SControl again and rewrite the 2861 * DET part with 0 2862 */ 2863 SControl = ddi_get32(si_ctlp->sictl_port_acc_handle, 2864 (uint32_t *)PORT_SCONTROL(si_ctlp, port)); 2865 SCONTROL_SET_DET(SControl, SCONTROL_DET_NOACTION); 2866 ddi_put32(si_ctlp->sictl_port_acc_handle, 2867 (uint32_t *)(PORT_SCONTROL(si_ctlp, port)), 2868 SControl); 2869 2870 /* 2871 * PHY may be initialized by now. Check the DET field of 2872 * SStatus to determine if there is a device present. 2873 * 2874 * The DET field is valid only if IPM field indicates that 2875 * the interface is in active state. 2876 */ 2877 2878 loop_count = 0; 2879 do { 2880 SStatus = ddi_get32(si_ctlp->sictl_port_acc_handle, 2881 (uint32_t *)PORT_SSTATUS(si_ctlp, port)); 2882 2883 if (SSTATUS_GET_IPM(SStatus) != 2884 SSTATUS_IPM_INTERFACE_ACTIVE) { 2885 /* 2886 * If the interface is not active, the DET field 2887 * is considered not accurate. So we want to 2888 * continue looping. 2889 */ 2890 SSTATUS_SET_DET(SStatus, 2891 SSTATUS_DET_NODEV_NOPHY); 2892 } 2893 2894 if (loop_count++ > SI_POLLRATE_SSTATUS) { 2895 /* 2896 * We are effectively timing out after 0.1 sec. 2897 */ 2898 break; 2899 } 2900 2901 /* Wait for 10 millisec */ 2902 #ifndef __lock_lint 2903 delay(SI_10MS_TICKS); 2904 #endif /* __lock_lint */ 2905 2906 } while (SSTATUS_GET_DET(SStatus) != 2907 SSTATUS_DET_DEVPRESENT_PHYONLINE); 2908 2909 SIDBG2(SIDBG_POLL_LOOP|SIDBG_INIT, si_ctlp, 2910 "si_initialize_controller: 1st loop count: %d, " 2911 "SStatus: 0x%x", 2912 loop_count, 2913 SStatus); 2914 2915 if ((SSTATUS_GET_IPM(SStatus) != 2916 SSTATUS_IPM_INTERFACE_ACTIVE) || 2917 (SSTATUS_GET_DET(SStatus) != 2918 SSTATUS_DET_DEVPRESENT_PHYONLINE)) { 2919 /* 2920 * Either the port is not active or there 2921 * is no device present. 2922 */ 2923 si_ctlp->sictl_ports[port]->siport_port_type = 2924 PORT_TYPE_NODEV; 2925 mutex_exit(&si_portp->siport_mutex); 2926 continue; 2927 } 2928 2929 /* Wait until Port Ready */ 2930 loop_count = 0; 2931 do { 2932 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 2933 (uint32_t *)PORT_STATUS(si_ctlp, port)); 2934 2935 if (loop_count++ > SI_POLLRATE_PORTREADY) { 2936 /* 2937 * We are effectively timing out after 0.5 sec. 2938 */ 2939 break; 2940 } 2941 2942 /* Wait for 10 millisec */ 2943 #ifndef __lock_lint 2944 delay(SI_10MS_TICKS); 2945 #endif /* __lock_lint */ 2946 2947 } while (!(port_status & PORT_STATUS_BITS_PORT_READY)); 2948 2949 SIDBG1(SIDBG_POLL_LOOP|SIDBG_INIT, si_ctlp, 2950 "si_initialize_controller: 2nd loop count: %d", 2951 loop_count); 2952 2953 if (si_ctlp->sictl_flags & SI_ATTACH) { 2954 /* 2955 * We want to probe for dev signature only during attach 2956 * case. Don't do it during suspend/resume sequence. 2957 */ 2958 if (port_status & PORT_STATUS_BITS_PORT_READY) { 2959 mutex_exit(&si_portp->siport_mutex); 2960 si_find_dev_signature(si_ctlp, si_portp, port, 2961 PORTMULT_CONTROL_PORT); 2962 mutex_enter(&si_portp->siport_mutex); 2963 } else { 2964 si_ctlp->sictl_ports[port]->siport_port_type = 2965 PORT_TYPE_NODEV; 2966 } 2967 } 2968 2969 mutex_exit(&si_portp->siport_mutex); 2970 } 2971 2972 mutex_exit(&si_ctlp->sictl_mutex); 2973 return (SI_SUCCESS); 2974 } 2975 2976 /* 2977 * Reverse of si_initialize_controller(). 2978 * 2979 * WARNING, WARNING: The caller is expected to obtain the sictl_mutex 2980 * before calling us. 2981 */ 2982 static void 2983 si_deinititalize_controller(si_ctl_state_t *si_ctlp) 2984 { 2985 int port; 2986 2987 _NOTE(ASSUMING_PROTECTED(si_ctlp)) 2988 2989 SIDBG0(SIDBG_INIT|SIDBG_ENTRY, si_ctlp, 2990 "si3124: si_deinititalize_controller entered"); 2991 2992 /* disable all the interrupts. */ 2993 si_disable_all_interrupts(si_ctlp); 2994 2995 if (si_ctlp->sictl_flags & SI_DETACH) { 2996 /* 2997 * We want to dealloc all the memory in detach case. 2998 */ 2999 for (port = 0; port < si_ctlp->sictl_num_ports; port++) { 3000 si_dealloc_port_state(si_ctlp, port); 3001 } 3002 } 3003 3004 } 3005 3006 /* 3007 * Prepare the port ready for usage. 3008 * 3009 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3010 * before calling us. 3011 */ 3012 static void 3013 si_init_port(si_ctl_state_t *si_ctlp, int port) 3014 { 3015 3016 SIDBG1(SIDBG_ENTRY|SIDBG_INIT, si_ctlp, 3017 "si_init_port entered: port: 0x%x", 3018 port); 3019 3020 /* Initialize the port. */ 3021 ddi_put32(si_ctlp->sictl_port_acc_handle, 3022 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 3023 PORT_CONTROL_SET_BITS_PORT_INITIALIZE); 3024 3025 /* 3026 * Clear the InterruptNCOR (Interupt No Clear on Read). 3027 * This step ensures that a mere reading of slot_status will clear 3028 * the interrupt; no explicit clearing of interrupt condition 3029 * will be needed for successful completion of commands. 3030 */ 3031 ddi_put32(si_ctlp->sictl_port_acc_handle, 3032 (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port), 3033 PORT_CONTROL_CLEAR_BITS_INTR_NCoR); 3034 3035 /* clear any pending interrupts at this point */ 3036 ddi_put32(si_ctlp->sictl_port_acc_handle, 3037 (uint32_t *)(PORT_INTERRUPT_STATUS(si_ctlp, port)), 3038 INTR_MASK); 3039 3040 } 3041 3042 3043 /* 3044 * Enumerate the devices connected to the port multiplier. 3045 * Once a device is detected, we call si_find_dev_signature() 3046 * to find the type of device connected. Even though we are 3047 * called from within si_find_dev_signature(), there is no 3048 * recursion possible. 3049 */ 3050 static int 3051 si_enumerate_port_multiplier( 3052 si_ctl_state_t *si_ctlp, 3053 si_port_state_t *si_portp, 3054 int port) 3055 { 3056 uint32_t num_dev_ports = 0; 3057 int pmport; 3058 uint32_t SControl = 0; 3059 uint32_t SStatus = 0; 3060 uint32_t SError = 0; 3061 int loop_count = 0; 3062 3063 SIDBG1(SIDBG_ENTRY|SIDBG_INIT, si_ctlp, 3064 "si_enumerate_port_multiplier entered: port: %d", 3065 port); 3066 3067 mutex_enter(&si_portp->siport_mutex); 3068 3069 /* Enable Port Multiplier context switching. */ 3070 ddi_put32(si_ctlp->sictl_port_acc_handle, 3071 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 3072 PORT_CONTROL_SET_BITS_PM_ENABLE); 3073 3074 /* 3075 * Read the num dev ports connected. 3076 * GSCR[2] contains the number of device ports. 3077 */ 3078 if (si_read_portmult_reg(si_ctlp, si_portp, port, PORTMULT_CONTROL_PORT, 3079 PSCR_REG2, &num_dev_ports)) { 3080 mutex_exit(&si_portp->siport_mutex); 3081 return (SI_FAILURE); 3082 } 3083 si_portp->siport_portmult_state.sipm_num_ports = num_dev_ports; 3084 3085 SIDBG1(SIDBG_INIT, si_ctlp, 3086 "si_enumerate_port_multiplier: ports found: %d", 3087 num_dev_ports); 3088 3089 for (pmport = 0; pmport < num_dev_ports-1; pmport++) { 3090 /* 3091 * Enable PHY by writing a 1, then a 0 to SControl 3092 * (i.e. PSCR[2]) DET field. 3093 */ 3094 if (si_read_portmult_reg(si_ctlp, si_portp, port, pmport, 3095 PSCR_REG2, &SControl)) { 3096 continue; 3097 } 3098 3099 /* First write a 1 to DET field of SControl. */ 3100 SCONTROL_SET_DET(SControl, SCONTROL_DET_COMRESET); 3101 if (si_write_portmult_reg(si_ctlp, si_portp, port, pmport, 3102 PSCR_REG2, SControl)) { 3103 continue; 3104 } 3105 #ifndef __lock_lint 3106 delay(SI_10MS_TICKS); /* give time for COMRESET to percolate */ 3107 #endif /* __lock_lint */ 3108 3109 /* Then write a 0 to the DET field of SControl. */ 3110 SCONTROL_SET_DET(SControl, SCONTROL_DET_NOACTION); 3111 if (si_write_portmult_reg(si_ctlp, si_portp, port, pmport, 3112 PSCR_REG2, SControl)) { 3113 continue; 3114 } 3115 3116 /* Wait for PHYRDY by polling SStatus (i.e. PSCR[0]). */ 3117 loop_count = 0; 3118 do { 3119 if (si_read_portmult_reg(si_ctlp, si_portp, port, 3120 pmport, PSCR_REG0, &SStatus)) { 3121 break; 3122 } 3123 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 3124 "looping for PHYRDY: SStatus: %x", 3125 SStatus); 3126 3127 if (SSTATUS_GET_IPM(SStatus) != 3128 SSTATUS_IPM_INTERFACE_ACTIVE) { 3129 /* 3130 * If the interface is not active, the DET field 3131 * is considered not accurate. So we want to 3132 * continue looping. 3133 */ 3134 SSTATUS_SET_DET(SStatus, 3135 SSTATUS_DET_NODEV_NOPHY); 3136 } 3137 3138 if (loop_count++ > SI_POLLRATE_SSTATUS) { 3139 /* 3140 * We are effectively timing out after 0.1 sec. 3141 */ 3142 break; 3143 } 3144 3145 /* Wait for 10 millisec */ 3146 #ifndef __lock_lint 3147 delay(SI_10MS_TICKS); 3148 #endif /* __lock_lint */ 3149 3150 } while (SSTATUS_GET_DET(SStatus) != 3151 SSTATUS_DET_DEVPRESENT_PHYONLINE); 3152 3153 SIDBG2(SIDBG_POLL_LOOP, si_ctlp, 3154 "si_enumerate_port_multiplier: " 3155 "loop count: %d, SStatus: 0x%x", 3156 loop_count, 3157 SStatus); 3158 3159 if ((SSTATUS_GET_IPM(SStatus) == 3160 SSTATUS_IPM_INTERFACE_ACTIVE) && 3161 (SSTATUS_GET_DET(SStatus) == 3162 SSTATUS_DET_DEVPRESENT_PHYONLINE)) { 3163 /* The interface is active and the device is present */ 3164 SIDBG1(SIDBG_INIT, si_ctlp, 3165 "Status: %x, device exists", 3166 SStatus); 3167 /* 3168 * Clear error bits in SError register (i.e. PSCR[1] 3169 * by writing back error bits. 3170 */ 3171 if (si_read_portmult_reg(si_ctlp, si_portp, port, 3172 pmport, PSCR_REG1, &SError)) { 3173 continue; 3174 } 3175 SIDBG1(SIDBG_INIT, si_ctlp, 3176 "SError bits are: %x", SError); 3177 if (si_write_portmult_reg(si_ctlp, si_portp, port, 3178 pmport, PSCR_REG1, SError)) { 3179 continue; 3180 } 3181 3182 /* There exists a device. */ 3183 mutex_exit(&si_portp->siport_mutex); 3184 si_find_dev_signature(si_ctlp, si_portp, port, pmport); 3185 mutex_enter(&si_portp->siport_mutex); 3186 } 3187 } 3188 3189 mutex_exit(&si_portp->siport_mutex); 3190 3191 return (SI_SUCCESS); 3192 } 3193 3194 3195 /* 3196 * Read a port multiplier register. 3197 * 3198 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3199 * before calling us. 3200 */ 3201 static int 3202 si_read_portmult_reg( 3203 si_ctl_state_t *si_ctlp, 3204 si_port_state_t *si_portp, 3205 int port, 3206 int pmport, 3207 int regnum, 3208 uint32_t *regval) 3209 { 3210 int slot; 3211 si_prb_t *prb; 3212 uint32_t *prb_word_ptr; 3213 int i; 3214 uint32_t slot_status; 3215 int loop_count = 0; 3216 3217 _NOTE(ASSUMING_PROTECTED(si_portp)) 3218 3219 SIDBG3(SIDBG_ENTRY, si_ctlp, "si_read_portmult_reg: port: %x," 3220 "pmport: %x, regnum: %x", 3221 port, pmport, regnum); 3222 3223 slot = si_claim_free_slot(si_ctlp, si_portp, port); 3224 if (slot == -1) { 3225 return (SI_FAILURE); 3226 } 3227 3228 prb = &(si_portp->siport_prbpool[slot]); 3229 bzero((void *)prb, sizeof (si_prb_t)); 3230 3231 /* Now fill the prb. */ 3232 SET_FIS_TYPE(prb->prb_fis, REGISTER_FIS_H2D); 3233 SET_FIS_PMP(prb->prb_fis, PORTMULT_CONTROL_PORT); 3234 SET_FIS_CDMDEVCTL(prb->prb_fis, 1); 3235 SET_FIS_COMMAND(prb->prb_fis, SATAC_READ_PM_REG); 3236 3237 SET_FIS_DEV_HEAD(prb->prb_fis, pmport); 3238 SET_FIS_FEATURES(prb->prb_fis, regnum); 3239 3240 /* no real data transfer is involved. */ 3241 SET_SGE_TRM(prb->prb_sge0); 3242 3243 #if SI_DEBUG 3244 if (si_debug_flags & SIDBG_DUMP_PRB) { 3245 int *ptr; 3246 int j; 3247 3248 ptr = (int *)prb; 3249 cmn_err(CE_WARN, "read_port_mult_reg, prb: "); 3250 for (j = 0; j < (sizeof (si_prb_t)/4); j++) { 3251 cmn_err(CE_WARN, "%x ", ptr[j]); 3252 } 3253 3254 } 3255 #endif /* SI_DEBUG */ 3256 3257 /* Deliver PRB */ 3258 POST_PRB_ADDR(si_ctlp, si_portp, port, slot); 3259 3260 /* Loop till the command is finished. */ 3261 do { 3262 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3263 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 3264 3265 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 3266 "looping read_pm slot_status: 0x%x", 3267 slot_status); 3268 3269 if (loop_count++ > SI_POLLRATE_SLOTSTATUS) { 3270 /* We are effectively timing out after 0.5 sec. */ 3271 break; 3272 } 3273 3274 /* Wait for 10 millisec */ 3275 #ifndef __lock_lint 3276 delay(SI_10MS_TICKS); 3277 #endif /* __lock_lint */ 3278 3279 } while (slot_status & SI_SLOT_MASK & (0x1 << slot)); 3280 3281 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 3282 "read_portmult_reg: loop count: %d", 3283 loop_count); 3284 3285 CLEAR_BIT(si_portp->siport_pending_tags, slot); 3286 3287 /* Now inspect the port LRAM for the modified FIS. */ 3288 prb_word_ptr = (uint32_t *)prb; 3289 for (i = 0; i < (sizeof (si_prb_t)/4); i++) { 3290 prb_word_ptr[i] = ddi_get32(si_ctlp->sictl_port_acc_handle, 3291 (uint32_t *)(PORT_LRAM(si_ctlp, port, slot)+i*4)); 3292 } 3293 3294 if (((GET_FIS_COMMAND(prb->prb_fis) & 0x1) != 0) || 3295 (GET_FIS_FEATURES(prb->prb_fis) != 0)) { 3296 /* command failed. */ 3297 return (SI_FAILURE); 3298 } 3299 3300 /* command succeeded. */ 3301 *regval = (GET_FIS_SECTOR_COUNT(prb->prb_fis) & 0xff) | 3302 ((GET_FIS_SECTOR(prb->prb_fis) << 8) & 0xff00) | 3303 ((GET_FIS_CYL_LOW(prb->prb_fis) << 16) & 0xff0000) | 3304 ((GET_FIS_CYL_HI(prb->prb_fis) << 24) & 0xff000000); 3305 3306 return (SI_SUCCESS); 3307 } 3308 3309 /* 3310 * Write a port multiplier register. 3311 * 3312 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3313 * before calling us. 3314 */ 3315 static int 3316 si_write_portmult_reg( 3317 si_ctl_state_t *si_ctlp, 3318 si_port_state_t *si_portp, 3319 int port, 3320 int pmport, 3321 int regnum, 3322 uint32_t regval) 3323 { 3324 int slot; 3325 si_prb_t *prb; 3326 uint32_t *prb_word_ptr; 3327 uint32_t slot_status; 3328 int i; 3329 int loop_count = 0; 3330 3331 _NOTE(ASSUMING_PROTECTED(si_portp)) 3332 3333 SIDBG4(SIDBG_ENTRY, si_ctlp, 3334 "si_write_portmult_reg: port: %x, pmport: %x," 3335 "regnum: %x, regval: %x", 3336 port, pmport, regnum, regval); 3337 3338 slot = si_claim_free_slot(si_ctlp, si_portp, port); 3339 if (slot == -1) { 3340 return (SI_FAILURE); 3341 } 3342 3343 prb = &(si_portp->siport_prbpool[slot]); 3344 bzero((void *)prb, sizeof (si_prb_t)); 3345 3346 /* Now fill the prb. */ 3347 SET_FIS_TYPE(prb->prb_fis, REGISTER_FIS_H2D); 3348 SET_FIS_PMP(prb->prb_fis, PORTMULT_CONTROL_PORT); 3349 SET_FIS_CDMDEVCTL(prb->prb_fis, 1); 3350 3351 SET_FIS_COMMAND(prb->prb_fis, SATAC_WRITE_PM_REG); 3352 SET_FIS_DEV_HEAD(prb->prb_fis, pmport); 3353 SET_FIS_FEATURES(prb->prb_fis, regnum); 3354 3355 SET_FIS_SECTOR_COUNT(prb->prb_fis, regval & 0xff); 3356 SET_FIS_SECTOR(prb->prb_fis, (regval >> 8) & 0xff); 3357 SET_FIS_CYL_LOW(prb->prb_fis, (regval >> 16) & 0xff); 3358 SET_FIS_CYL_HI(prb->prb_fis, (regval >> 24) & 0xff); 3359 3360 /* no real data transfer is involved. */ 3361 SET_SGE_TRM(prb->prb_sge0); 3362 3363 #if SI_DEBUG 3364 if (si_debug_flags & SIDBG_DUMP_PRB) { 3365 int *ptr; 3366 int j; 3367 3368 ptr = (int *)prb; 3369 cmn_err(CE_WARN, "read_port_mult_reg, prb: "); 3370 for (j = 0; j < (sizeof (si_prb_t)/4); j++) { 3371 cmn_err(CE_WARN, "%x ", ptr[j]); 3372 } 3373 3374 } 3375 #endif /* SI_DEBUG */ 3376 3377 /* Deliver PRB */ 3378 POST_PRB_ADDR(si_ctlp, si_portp, port, slot); 3379 3380 /* Loop till the command is finished. */ 3381 do { 3382 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3383 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 3384 3385 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 3386 "looping write_pmp slot_status: 0x%x", 3387 slot_status); 3388 3389 if (loop_count++ > SI_POLLRATE_SLOTSTATUS) { 3390 /* We are effectively timing out after 0.5 sec. */ 3391 break; 3392 } 3393 3394 /* Wait for 10 millisec */ 3395 #ifndef __lock_lint 3396 delay(SI_10MS_TICKS); 3397 #endif /* __lock_lint */ 3398 3399 } while (slot_status & SI_SLOT_MASK & (0x1 << slot)); 3400 3401 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 3402 "write_portmult_reg: loop count: %d", 3403 loop_count); 3404 3405 CLEAR_BIT(si_portp->siport_pending_tags, slot); 3406 3407 /* Now inspect the port LRAM for the modified FIS. */ 3408 prb_word_ptr = (uint32_t *)prb; 3409 for (i = 0; i < (sizeof (si_prb_t)/4); i++) { 3410 prb_word_ptr[i] = ddi_get32(si_ctlp->sictl_port_acc_handle, 3411 (uint32_t *)(PORT_LRAM(si_ctlp, port, slot)+i*4)); 3412 } 3413 3414 if (((GET_FIS_COMMAND(prb->prb_fis) & 0x1) != 0) || 3415 (GET_FIS_FEATURES(prb->prb_fis) != 0)) { 3416 /* command failed */ 3417 return (SI_FAILURE); 3418 } 3419 3420 /* command succeeded */ 3421 return (SI_SUCCESS); 3422 } 3423 3424 3425 /* 3426 * Set the auto sense data for ATAPI devices. 3427 * 3428 * Note: Currently the sense data is simulated; this code will be enhanced 3429 * in second phase to fetch the real sense data from the atapi device. 3430 */ 3431 static void 3432 si_set_sense_data(sata_pkt_t *satapkt, int reason) 3433 { 3434 struct scsi_extended_sense *sense; 3435 3436 sense = (struct scsi_extended_sense *) 3437 satapkt->satapkt_cmd.satacmd_rqsense; 3438 bzero(sense, sizeof (struct scsi_extended_sense)); 3439 sense->es_valid = 1; /* Valid sense */ 3440 sense->es_class = 7; /* Response code 0x70 - current err */ 3441 sense->es_key = 0; 3442 sense->es_info_1 = 0; 3443 sense->es_info_2 = 0; 3444 sense->es_info_3 = 0; 3445 sense->es_info_4 = 0; 3446 sense->es_add_len = 6; /* Additional length */ 3447 sense->es_cmd_info[0] = 0; 3448 sense->es_cmd_info[1] = 0; 3449 sense->es_cmd_info[2] = 0; 3450 sense->es_cmd_info[3] = 0; 3451 sense->es_add_code = 0; 3452 sense->es_qual_code = 0; 3453 3454 if ((reason == SATA_PKT_DEV_ERROR) || (reason == SATA_PKT_TIMEOUT)) { 3455 sense->es_key = KEY_HARDWARE_ERROR; 3456 } 3457 } 3458 3459 3460 /* 3461 * Interrupt service handler. We loop through each of the ports to find 3462 * if the interrupt belongs to any of them. 3463 * 3464 * Bulk of the interrupt handling is actually done out of subroutines 3465 * like si_intr_command_complete() etc. 3466 */ 3467 /*ARGSUSED*/ 3468 static uint_t 3469 si_intr(caddr_t arg1, caddr_t arg2) 3470 { 3471 3472 si_ctl_state_t *si_ctlp = (si_ctl_state_t *)arg1; 3473 si_port_state_t *si_portp; 3474 uint32_t global_intr_status; 3475 uint32_t mask, port_intr_status; 3476 int port; 3477 3478 global_intr_status = ddi_get32(si_ctlp->sictl_global_acc_handle, 3479 (uint32_t *)GLOBAL_INTERRUPT_STATUS(si_ctlp)); 3480 3481 SIDBG1(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, 3482 "si_intr: global_int_status: 0x%x", 3483 global_intr_status); 3484 3485 if (!(global_intr_status & SI31xx_INTR_PORT_MASK)) { 3486 /* Sorry, the interrupt is not ours. */ 3487 return (DDI_INTR_UNCLAIMED); 3488 } 3489 3490 /* Loop for all the ports. */ 3491 for (port = 0; port < si_ctlp->sictl_num_ports; port++) { 3492 3493 mask = 0x1 << port; 3494 if (!(global_intr_status & mask)) { 3495 continue; 3496 } 3497 3498 mutex_enter(&si_ctlp->sictl_mutex); 3499 si_portp = si_ctlp->sictl_ports[port]; 3500 mutex_exit(&si_ctlp->sictl_mutex); 3501 3502 port_intr_status = ddi_get32(si_ctlp->sictl_global_acc_handle, 3503 (uint32_t *)PORT_INTERRUPT_STATUS(si_ctlp, port)); 3504 3505 SIDBG2(SIDBG_VERBOSE, si_ctlp, 3506 "s_intr: port_intr_status: 0x%x, port: %x", 3507 port_intr_status, 3508 port); 3509 3510 if (port_intr_status & INTR_COMMAND_COMPLETE) { 3511 (void) si_intr_command_complete(si_ctlp, si_portp, 3512 port); 3513 } else { 3514 /* Clear the interrupts */ 3515 ddi_put32(si_ctlp->sictl_port_acc_handle, 3516 (uint32_t *)(PORT_INTERRUPT_STATUS(si_ctlp, port)), 3517 port_intr_status & INTR_MASK); 3518 } 3519 3520 /* 3521 * Note that we did not clear the interrupt for command 3522 * completion interrupt. Reading of slot_status takes care 3523 * of clearing the interrupt for command completion case. 3524 */ 3525 3526 if (port_intr_status & INTR_COMMAND_ERROR) { 3527 (void) si_intr_command_error(si_ctlp, si_portp, port); 3528 } 3529 3530 if (port_intr_status & INTR_PORT_READY) { 3531 (void) si_intr_port_ready(si_ctlp, si_portp, port); 3532 } 3533 3534 if (port_intr_status & INTR_POWER_CHANGE) { 3535 (void) si_intr_pwr_change(si_ctlp, si_portp, port); 3536 } 3537 3538 if (port_intr_status & INTR_PHYRDY_CHANGE) { 3539 (void) si_intr_phy_ready_change(si_ctlp, si_portp, 3540 port); 3541 } 3542 3543 if (port_intr_status & INTR_COMWAKE_RECEIVED) { 3544 (void) si_intr_comwake_rcvd(si_ctlp, si_portp, 3545 port); 3546 } 3547 3548 if (port_intr_status & INTR_UNRECOG_FIS) { 3549 (void) si_intr_unrecognised_fis(si_ctlp, si_portp, 3550 port); 3551 } 3552 3553 if (port_intr_status & INTR_DEV_XCHANGED) { 3554 (void) si_intr_dev_xchanged(si_ctlp, si_portp, port); 3555 } 3556 3557 if (port_intr_status & INTR_8B10B_DECODE_ERROR) { 3558 (void) si_intr_decode_err_threshold(si_ctlp, si_portp, 3559 port); 3560 } 3561 3562 if (port_intr_status & INTR_CRC_ERROR) { 3563 (void) si_intr_crc_err_threshold(si_ctlp, si_portp, 3564 port); 3565 } 3566 3567 if (port_intr_status & INTR_HANDSHAKE_ERROR) { 3568 (void) si_intr_handshake_err_threshold(si_ctlp, 3569 si_portp, port); 3570 } 3571 3572 if (port_intr_status & INTR_SETDEVBITS_NOTIFY) { 3573 (void) si_intr_set_devbits_notify(si_ctlp, si_portp, 3574 port); 3575 } 3576 } 3577 3578 return (DDI_INTR_CLAIMED); 3579 } 3580 3581 /* 3582 * Interrupt which indicates that one or more commands have successfully 3583 * completed. 3584 * 3585 * Since we disabled W1C (write-one-to-clear) previously, mere reading 3586 * of slot_status register clears the interrupt. There is no need to 3587 * explicitly clear the interrupt. 3588 */ 3589 static int 3590 si_intr_command_complete( 3591 si_ctl_state_t *si_ctlp, 3592 si_port_state_t *si_portp, 3593 int port) 3594 { 3595 3596 uint32_t slot_status; 3597 uint32_t finished_tags; 3598 int finished_slot; 3599 sata_pkt_t *satapkt; 3600 3601 SIDBG0(SIDBG_ENTRY|SIDBG_INTR, si_ctlp, 3602 "si_intr_command_complete enter"); 3603 3604 mutex_enter(&si_portp->siport_mutex); 3605 3606 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3607 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 3608 3609 if (!si_portp->siport_pending_tags) { 3610 /* 3611 * Spurious interrupt. Nothing to be done. 3612 * The interrupt was cleared when slot_status was read. 3613 */ 3614 mutex_exit(&si_portp->siport_mutex); 3615 return (SI_SUCCESS); 3616 } 3617 3618 SIDBG2(SIDBG_VERBOSE, si_ctlp, "si3124: si_intr_command_complete: " 3619 "pending_tags: %x, slot_status: %x", 3620 si_portp->siport_pending_tags, 3621 slot_status); 3622 3623 finished_tags = si_portp->siport_pending_tags & 3624 ~slot_status & SI_SLOT_MASK; 3625 while (finished_tags) { 3626 si_prb_t *prb; 3627 3628 finished_slot = ddi_ffs(finished_tags) - 1; 3629 if (finished_slot == -1) { 3630 break; 3631 } 3632 prb = &si_portp->siport_prbpool[finished_slot]; 3633 3634 satapkt = si_portp->siport_slot_pkts[finished_slot]; 3635 satapkt->satapkt_cmd.satacmd_status_reg = 3636 GET_FIS_COMMAND(prb->prb_fis); 3637 3638 if (satapkt->satapkt_cmd.satacmd_flags.sata_special_regs) 3639 si_copy_out_regs(&satapkt->satapkt_cmd, &prb->prb_fis); 3640 3641 CLEAR_BIT(si_portp->siport_pending_tags, finished_slot); 3642 CLEAR_BIT(finished_tags, finished_slot); 3643 SENDUP_PACKET(si_portp, satapkt, SATA_PKT_COMPLETED); 3644 } 3645 3646 SIDBG2(SIDBG_PKTCOMP, si_ctlp, 3647 "command_complete done: pend_tags: 0x%x, slot_status: 0x%x", 3648 si_portp->siport_pending_tags, 3649 slot_status); 3650 3651 /* 3652 * tidbit: no need to clear the interrupt since reading of 3653 * slot_status automatically clears the interrupt in the case 3654 * of a successful command completion. 3655 */ 3656 3657 mutex_exit(&si_portp->siport_mutex); 3658 3659 return (SI_SUCCESS); 3660 } 3661 3662 /* 3663 * Interrupt which indicates that a command did not complete successfully. 3664 * 3665 * The port halts whenever a command error interrupt is received. 3666 * The only way to restart it is to reset or reinitialize the port 3667 * but such an operation throws away all the pending commands on 3668 * the port. 3669 * 3670 * We reset the device and mop the commands on the port. 3671 */ 3672 static int 3673 si_intr_command_error( 3674 si_ctl_state_t *si_ctlp, 3675 si_port_state_t *si_portp, 3676 int port) 3677 { 3678 uint32_t command_error, slot_status; 3679 uint32_t failed_tags; 3680 3681 command_error = ddi_get32(si_ctlp->sictl_port_acc_handle, 3682 (uint32_t *)(PORT_COMMAND_ERROR(si_ctlp, port))); 3683 3684 SIDBG1(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, 3685 "si_intr_command_error: command_error: 0x%x", 3686 command_error); 3687 3688 mutex_enter(&si_portp->siport_mutex); 3689 3690 /* 3691 * Remember the slot_status since any of the recovery handler 3692 * can blow it away with reset operation. 3693 */ 3694 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3695 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 3696 3697 si_log_error_message(si_ctlp, port, command_error); 3698 3699 switch (command_error) { 3700 3701 case CMD_ERR_DEVICEERRROR: 3702 si_error_recovery_DEVICEERROR(si_ctlp, si_portp, port); 3703 break; 3704 3705 case CMD_ERR_SDBERROR: 3706 si_error_recovery_SDBERROR(si_ctlp, si_portp, port); 3707 break; 3708 3709 case CMD_ERR_DATAFISERROR: 3710 si_error_recovery_DATAFISERROR(si_ctlp, si_portp, port); 3711 break; 3712 3713 case CMD_ERR_SENDFISERROR: 3714 si_error_recovery_SENDFISERROR(si_ctlp, si_portp, port); 3715 break; 3716 3717 default: 3718 si_error_recovery_default(si_ctlp, si_portp, port); 3719 break; 3720 3721 } 3722 3723 /* 3724 * Compute the failed_tags by adding up the error tags. 3725 * 3726 * The siport_err_tags_SDBERROR and siport_err_tags_nonSDBERROR 3727 * were filled in by the si_error_recovery_* routines. 3728 */ 3729 failed_tags = si_portp->siport_pending_tags & 3730 (si_portp->siport_err_tags_SDBERROR | 3731 si_portp->siport_err_tags_nonSDBERROR); 3732 3733 SIDBG3(SIDBG_ERRS|SIDBG_INTR, si_ctlp, "si_intr_command_error: " 3734 "err_tags_SDBERROR: 0x%x, " 3735 "err_tags_nonSDBERRROR: 0x%x, " 3736 "failed_tags: 0x%x", 3737 si_portp->siport_err_tags_SDBERROR, 3738 si_portp->siport_err_tags_nonSDBERROR, 3739 failed_tags); 3740 3741 SIDBG2(SIDBG_ERRS|SIDBG_INTR, si_ctlp, "si3124: si_intr_command_error: " 3742 "slot_status:0x%x, pending_tags: 0x%x", 3743 slot_status, 3744 si_portp->siport_pending_tags); 3745 3746 mutex_exit(&si_portp->siport_mutex); 3747 si_mop_commands(si_ctlp, 3748 si_portp, 3749 port, 3750 slot_status, 3751 failed_tags, 3752 0, /* timedout_tags */ 3753 0, /* aborting_tags */ 3754 0); /* reset_tags */ 3755 mutex_enter(&si_portp->siport_mutex); 3756 3757 ASSERT(si_portp->siport_pending_tags == 0); 3758 3759 si_portp->siport_err_tags_SDBERROR = 0; 3760 si_portp->siport_err_tags_nonSDBERROR = 0; 3761 3762 mutex_exit(&si_portp->siport_mutex); 3763 3764 return (SI_SUCCESS); 3765 } 3766 3767 /* 3768 * There is a subtle difference between errors on a normal port and 3769 * a port-mult port. When an error happens on a normal port, the port 3770 * is halted effectively until the port is reset or initialized. 3771 * However, in port-mult port errors, port does not get halted since 3772 * other non-error devices behind the port multiplier can still 3773 * continue to operate. So we wait till all the commands are drained 3774 * instead of resetting it right away. 3775 * 3776 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3777 * before calling us. 3778 */ 3779 static void 3780 si_recover_portmult_errors( 3781 si_ctl_state_t *si_ctlp, 3782 si_port_state_t *si_portp, 3783 int port) 3784 { 3785 uint32_t command_error, slot_status, port_status; 3786 int failed_slot; 3787 int loop_count = 0; 3788 3789 _NOTE(ASSUMING_PROTECTED(si_portp)) 3790 3791 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 3792 "si_recover_portmult_errors: port: 0x%x", 3793 port); 3794 3795 /* Resume the port */ 3796 ddi_put32(si_ctlp->sictl_port_acc_handle, 3797 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 3798 PORT_CONTROL_SET_BITS_RESUME); 3799 3800 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3801 (uint32_t *)PORT_STATUS(si_ctlp, port)); 3802 3803 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 3804 command_error = ddi_get32(si_ctlp->sictl_port_acc_handle, 3805 (uint32_t *)(PORT_COMMAND_ERROR(si_ctlp, port))); 3806 3807 if (command_error == CMD_ERR_SDBERROR) { 3808 si_portp->siport_err_tags_SDBERROR |= (0x1 << failed_slot); 3809 } else { 3810 si_portp->siport_err_tags_nonSDBERROR |= (0x1 << failed_slot); 3811 } 3812 3813 /* Now we drain the pending commands. */ 3814 do { 3815 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3816 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 3817 3818 /* 3819 * Since we have not yet returned DDI_INTR_CLAIMED, 3820 * our interrupt handler is guaranteed not to be called again. 3821 * So we need to check IS_ATTENTION_RAISED() for further 3822 * decisions. 3823 * 3824 * This is a too big a delay for an interrupt context. 3825 * But this is supposed to be a rare condition. 3826 */ 3827 3828 if (IS_ATTENTION_RAISED(slot_status)) { 3829 /* Resume again */ 3830 ddi_put32(si_ctlp->sictl_port_acc_handle, 3831 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 3832 PORT_CONTROL_SET_BITS_RESUME); 3833 3834 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3835 (uint32_t *)PORT_STATUS(si_ctlp, port)); 3836 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 3837 command_error = ddi_get32( 3838 si_ctlp->sictl_port_acc_handle, 3839 (uint32_t *)(PORT_COMMAND_ERROR(si_ctlp, 3840 port))); 3841 if (command_error == CMD_ERR_SDBERROR) { 3842 si_portp->siport_err_tags_SDBERROR |= 3843 (0x1 << failed_slot); 3844 } else { 3845 si_portp->siport_err_tags_nonSDBERROR |= 3846 (0x1 << failed_slot); 3847 } 3848 } 3849 3850 if (loop_count++ > SI_POLLRATE_RECOVERPORTMULT) { 3851 /* We are effectively timing out after 10 sec. */ 3852 break; 3853 } 3854 3855 /* Wait for 10 millisec */ 3856 #ifndef __lock_lint 3857 delay(SI_10MS_TICKS); 3858 #endif /* __lock_lint */ 3859 3860 } while (slot_status & SI_SLOT_MASK); 3861 3862 /* 3863 * The above loop can be improved for 3132 since we could obtain the 3864 * Port Multiplier Context of the device in error. Then we could 3865 * do a better job in filtering out commands for the device in error. 3866 * The loop could finish much earlier with such a logic. 3867 */ 3868 3869 /* Clear the RESUME bit. */ 3870 ddi_put32(si_ctlp->sictl_port_acc_handle, 3871 (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port), 3872 PORT_CONTROL_CLEAR_BITS_RESUME); 3873 3874 } 3875 3876 /* 3877 * If we are connected to port multiplier, drain the non-failed devices. 3878 * Otherwise, we initialize the port (which effectively fails all the 3879 * pending commands in the hope that sd would retry them later). 3880 * 3881 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3882 * before calling us. 3883 */ 3884 static void 3885 si_error_recovery_DEVICEERROR( 3886 si_ctl_state_t *si_ctlp, 3887 si_port_state_t *si_portp, 3888 int port) 3889 { 3890 uint32_t port_status; 3891 int failed_slot; 3892 3893 _NOTE(ASSUMING_PROTECTED(si_portp)) 3894 3895 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 3896 "si_error_recovery_DEVICEERROR: port: 0x%x", 3897 port); 3898 3899 if (si_portp->siport_port_type == PORT_TYPE_MULTIPLIER) { 3900 si_recover_portmult_errors(si_ctlp, si_portp, port); 3901 } else { 3902 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3903 (uint32_t *)PORT_STATUS(si_ctlp, port)); 3904 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 3905 si_portp->siport_err_tags_nonSDBERROR |= (0x1 << failed_slot); 3906 } 3907 3908 /* In either case (port-mult or not), we reinitialize the port. */ 3909 (void) si_initialize_port_wait_till_ready(si_ctlp, port); 3910 } 3911 3912 /* 3913 * Handle exactly like DEVICEERROR. Remember the tags with SDBERROR 3914 * to perform read_log_ext on them later. SDBERROR means that the 3915 * error was for an NCQ command. 3916 * 3917 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3918 * before calling us. 3919 */ 3920 static void 3921 si_error_recovery_SDBERROR( 3922 si_ctl_state_t *si_ctlp, 3923 si_port_state_t *si_portp, 3924 int port) 3925 { 3926 uint32_t port_status; 3927 int failed_slot; 3928 3929 _NOTE(ASSUMING_PROTECTED(si_portp)) 3930 3931 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 3932 "si3124: si_error_recovery_SDBERROR: port: 0x%x", 3933 port); 3934 3935 if (si_portp->siport_port_type == PORT_TYPE_MULTIPLIER) { 3936 si_recover_portmult_errors(si_ctlp, si_portp, port); 3937 } else { 3938 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3939 (uint32_t *)PORT_STATUS(si_ctlp, port)); 3940 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 3941 si_portp->siport_err_tags_SDBERROR |= (0x1 << failed_slot); 3942 } 3943 3944 /* In either case (port-mult or not), we reinitialize the port. */ 3945 (void) si_initialize_port_wait_till_ready(si_ctlp, port); 3946 } 3947 3948 /* 3949 * Handle exactly like DEVICEERROR except resetting the port if there was 3950 * an NCQ command on the port. 3951 * 3952 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3953 * before calling us. 3954 */ 3955 static void 3956 si_error_recovery_DATAFISERROR( 3957 si_ctl_state_t *si_ctlp, 3958 si_port_state_t *si_portp, 3959 int port) 3960 { 3961 uint32_t port_status; 3962 int failed_slot; 3963 3964 _NOTE(ASSUMING_PROTECTED(si_portp)) 3965 3966 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 3967 "si3124: si_error_recovery_DATAFISERROR: port: 0x%x", 3968 port); 3969 3970 /* reset device if we were waiting for any ncq commands. */ 3971 if (si_portp->siport_pending_ncq_count) { 3972 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 3973 (uint32_t *)PORT_STATUS(si_ctlp, port)); 3974 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 3975 si_portp->siport_err_tags_nonSDBERROR |= (0x1 << failed_slot); 3976 (void) si_reset_dport_wait_till_ready(si_ctlp, si_portp, port, 3977 SI_DEVICE_RESET); 3978 return; 3979 } 3980 3981 /* 3982 * If we don't have any ncq commands pending, the rest of 3983 * the process is similar to the one for DEVICEERROR. 3984 */ 3985 si_error_recovery_DEVICEERROR(si_ctlp, si_portp, port); 3986 } 3987 3988 /* 3989 * We handle just like DEVICERROR except that we reset the device instead 3990 * of initializing the port. 3991 * 3992 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 3993 * before calling us. 3994 */ 3995 static void 3996 si_error_recovery_SENDFISERROR( 3997 si_ctl_state_t *si_ctlp, 3998 si_port_state_t *si_portp, 3999 int port) 4000 { 4001 uint32_t port_status; 4002 int failed_slot; 4003 4004 _NOTE(ASSUMING_PROTECTED(si_portp)) 4005 4006 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 4007 "si3124: si_error_recovery_SENDFISERROR: port: 0x%x", 4008 port); 4009 4010 if (si_portp->siport_port_type == PORT_TYPE_MULTIPLIER) { 4011 si_recover_portmult_errors(si_ctlp, si_portp, port); 4012 } else { 4013 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 4014 (uint32_t *)PORT_STATUS(si_ctlp, port)); 4015 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 4016 si_portp->siport_err_tags_nonSDBERROR |= (0x1 << failed_slot); 4017 (void) si_reset_dport_wait_till_ready(si_ctlp, si_portp, port, 4018 SI_DEVICE_RESET); 4019 } 4020 } 4021 4022 /* 4023 * The default behavior for all other errors is to reset the device. 4024 * 4025 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 4026 * before calling us. 4027 */ 4028 static void 4029 si_error_recovery_default( 4030 si_ctl_state_t *si_ctlp, 4031 si_port_state_t *si_portp, 4032 int port) 4033 { 4034 uint32_t port_status; 4035 int failed_slot; 4036 4037 _NOTE(ASSUMING_PROTECTED(si_portp)) 4038 4039 SIDBG1(SIDBG_ERRS|SIDBG_ENTRY, si_ctlp, 4040 "si3124: si_error_recovery_default: port: 0x%x", 4041 port); 4042 4043 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 4044 (uint32_t *)PORT_STATUS(si_ctlp, port)); 4045 failed_slot = (port_status >> 16) & SI_NUM_SLOTS; 4046 si_portp->siport_err_tags_nonSDBERROR |= (0x1 << failed_slot); 4047 4048 (void) si_reset_dport_wait_till_ready(si_ctlp, si_portp, port, 4049 SI_DEVICE_RESET); 4050 } 4051 4052 /* 4053 * Read Log Ext with PAGE 10 to retrieve the error for an NCQ command. 4054 * 4055 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 4056 * before calling us. 4057 */ 4058 static uint8_t 4059 si_read_log_ext(si_ctl_state_t *si_ctlp, si_port_state_t *si_portp, int port) 4060 { 4061 int slot; 4062 si_prb_t *prb; 4063 int i; 4064 uint32_t slot_status; 4065 int loop_count = 0; 4066 uint32_t *prb_word_ptr; 4067 uint8_t error; 4068 4069 _NOTE(ASSUMING_PROTECTED(si_portp)) 4070 4071 SIDBG1(SIDBG_ENTRY|SIDBG_ERRS, si_ctlp, 4072 "si_read_log_ext: port: %x", port); 4073 4074 slot = si_claim_free_slot(si_ctlp, si_portp, port); 4075 if (slot == -1) { 4076 return (0); 4077 } 4078 4079 prb = &(si_portp->siport_prbpool[slot]); 4080 bzero((void *)prb, sizeof (si_prb_t)); 4081 4082 /* Now fill the prb */ 4083 SET_FIS_TYPE(prb->prb_fis, REGISTER_FIS_H2D); 4084 SET_FIS_PMP(prb->prb_fis, PORTMULT_CONTROL_PORT); 4085 SET_FIS_CDMDEVCTL(prb->prb_fis, 1); 4086 SET_FIS_COMMAND(prb->prb_fis, SATAC_READ_LOG_EXT); 4087 SET_FIS_SECTOR(prb->prb_fis, SATA_LOG_PAGE_10); 4088 4089 /* no real data transfer is involved */ 4090 SET_SGE_TRM(prb->prb_sge0); 4091 4092 #if SI_DEBUG 4093 if (si_debug_flags & SIDBG_DUMP_PRB) { 4094 int *ptr; 4095 int j; 4096 4097 ptr = (int *)prb; 4098 cmn_err(CE_WARN, "read_port_mult_reg, prb: "); 4099 for (j = 0; j < (sizeof (si_prb_t)/4); j++) { 4100 cmn_err(CE_WARN, "%x ", ptr[j]); 4101 } 4102 4103 } 4104 #endif /* SI_DEBUG */ 4105 4106 /* Deliver PRB */ 4107 POST_PRB_ADDR(si_ctlp, si_portp, port, slot); 4108 4109 /* Loop till the command is finished. */ 4110 do { 4111 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 4112 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 4113 4114 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 4115 "looping read_log_ext slot_status: 0x%x", 4116 slot_status); 4117 4118 if (loop_count++ > SI_POLLRATE_SLOTSTATUS) { 4119 /* We are effectively timing out after 0.5 sec. */ 4120 break; 4121 } 4122 4123 /* Wait for 10 millisec */ 4124 #ifndef __lock_lint 4125 delay(SI_10MS_TICKS); 4126 #endif /* __lock_lint */ 4127 4128 } while (slot_status & SI_SLOT_MASK & (0x1 << slot)); 4129 4130 if (slot_status & SI_SLOT_MASK & (0x1 << slot)) { 4131 /* 4132 * If we fail with the READ LOG EXT command, we need to 4133 * initialize the port to clear the slot_status register. 4134 * We don't need to worry about any other valid commands 4135 * being thrown away because we are already in recovery 4136 * mode and READ LOG EXT is the only pending command. 4137 */ 4138 (void) si_initialize_port_wait_till_ready(si_ctlp, port); 4139 } 4140 4141 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 4142 "read_portmult_reg: loop count: %d", 4143 loop_count); 4144 4145 /* 4146 * The LRAM contains the the modified FIS. 4147 * Read the modified FIS to obtain the Error. 4148 */ 4149 prb_word_ptr = (uint32_t *)prb; 4150 for (i = 0; i < (sizeof (si_prb_t)/4); i++) { 4151 prb_word_ptr[i] = ddi_get32(si_ctlp->sictl_port_acc_handle, 4152 (uint32_t *)(PORT_LRAM(si_ctlp, port, slot)+i*4)); 4153 } 4154 error = GET_FIS_FEATURES(prb->prb_fis); 4155 4156 CLEAR_BIT(si_portp->siport_pending_tags, slot); 4157 4158 return (error); 4159 4160 } 4161 4162 /* 4163 * Dump the error message to the log. 4164 */ 4165 static void 4166 si_log_error_message(si_ctl_state_t *si_ctlp, int port, uint32_t command_error) 4167 { 4168 char *errstr; 4169 4170 switch (command_error) { 4171 4172 case CMD_ERR_DEVICEERRROR: 4173 errstr = "Standard Error: Error bit set in register - device" 4174 " to host FIS"; 4175 break; 4176 4177 case CMD_ERR_SDBERROR: 4178 errstr = "NCQ Error: Error bit set in register - device" 4179 " to host FIS"; 4180 break; 4181 4182 case CMD_ERR_DATAFISERROR: 4183 errstr = "Error in data FIS not detected by device"; 4184 break; 4185 4186 case CMD_ERR_SENDFISERROR: 4187 errstr = "Initial command FIS transmission failed"; 4188 break; 4189 4190 case CMD_ERR_INCONSISTENTSTATE: 4191 errstr = "Inconsistency in protocol"; 4192 break; 4193 4194 case CMD_ERR_DIRECTIONERROR: 4195 errstr = "DMA direction flag does not match the command"; 4196 break; 4197 4198 case CMD_ERR_UNDERRUNERROR: 4199 errstr = "Run out of scatter gather entries while writing data"; 4200 break; 4201 4202 case CMD_ERR_OVERRUNERROR: 4203 errstr = "Run out of scatter gather entries while reading data"; 4204 break; 4205 4206 case CMD_ERR_PACKETPROTOCOLERROR: 4207 errstr = "Packet protocol error"; 4208 break; 4209 4210 case CMD_ERR_PLDSGTERRORBOUNDARY: 4211 errstr = "Scatter/gather table not on quadword boundary"; 4212 break; 4213 4214 case CMD_ERR_PLDSGTERRORTARETABORT: 4215 errstr = "PCI(X) Target abort while fetching scatter/gather" 4216 " table"; 4217 break; 4218 4219 case CMD_ERR_PLDSGTERRORMASTERABORT: 4220 errstr = "PCI(X) Master abort while fetching scatter/gather" 4221 " table"; 4222 break; 4223 4224 case CMD_ERR_PLDSGTERRORPCIERR: 4225 errstr = "PCI(X) parity error while fetching scatter/gather" 4226 " table"; 4227 break; 4228 4229 case CMD_ERR_PLDCMDERRORBOUNDARY: 4230 errstr = "PRB not on quadword boundary"; 4231 break; 4232 4233 case CMD_ERR_PLDCMDERRORTARGETABORT: 4234 errstr = "PCI(X) Target abort while fetching PRB"; 4235 break; 4236 4237 case CMD_ERR_PLDCMDERRORMASTERABORT: 4238 errstr = "PCI(X) Master abort while fetching PRB"; 4239 break; 4240 4241 case CMD_ERR_PLDCMDERORPCIERR: 4242 errstr = "PCI(X) parity error while fetching PRB"; 4243 break; 4244 4245 case CMD_ERR_PSDERRORTARGETABORT: 4246 errstr = "PCI(X) Target abort during data transfer"; 4247 break; 4248 4249 case CMD_ERR_PSDERRORMASTERABORT: 4250 errstr = "PCI(X) Master abort during data transfer"; 4251 break; 4252 4253 case CMD_ERR_PSDERRORPCIERR: 4254 errstr = "PCI(X) parity error during data transfer"; 4255 break; 4256 4257 case CMD_ERR_SENDSERVICEERROR: 4258 errstr = "FIS received while sending service FIS in" 4259 " legacy queuing operation"; 4260 break; 4261 4262 default: 4263 errstr = "Unknown Error"; 4264 break; 4265 4266 } 4267 4268 SIDBG2(SIDBG_ERRS, si_ctlp, 4269 "command error: port: 0x%x, error: %s", 4270 port, 4271 errstr); 4272 4273 } 4274 4275 4276 /* 4277 * Interrupt which indicates that the Port Ready state has changed 4278 * from zero to one. 4279 * 4280 * We are not interested in this interrupt; we just log a debug message. 4281 */ 4282 /*ARGSUSED*/ 4283 static int 4284 si_intr_port_ready( 4285 si_ctl_state_t *si_ctlp, 4286 si_port_state_t *si_portp, 4287 int port) 4288 { 4289 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_ready"); 4290 return (SI_SUCCESS); 4291 } 4292 4293 /* 4294 * Interrupt which indicates that the port power management state 4295 * has been modified. 4296 * 4297 * We are not interested in this interrupt; we just log a debug message. 4298 */ 4299 /*ARGSUSED*/ 4300 static int 4301 si_intr_pwr_change( 4302 si_ctl_state_t *si_ctlp, 4303 si_port_state_t *si_portp, 4304 int port) 4305 { 4306 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_pwr_change"); 4307 return (SI_SUCCESS); 4308 } 4309 4310 /* 4311 * Interrupt which indicates that the PHY sate has changed either from 4312 * Not-Ready to Ready or from Ready to Not-Ready. 4313 */ 4314 static int 4315 si_intr_phy_ready_change( 4316 si_ctl_state_t *si_ctlp, 4317 si_port_state_t *si_portp, 4318 int port) 4319 { 4320 sata_device_t sdevice; 4321 uint32_t SStatus = 0; /* No dev present & PHY not established. */ 4322 int dev_exists_now = 0; 4323 int dev_existed_previously = 0; 4324 4325 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_phy_rdy_change"); 4326 4327 mutex_enter(&si_ctlp->sictl_mutex); 4328 if ((si_ctlp->sictl_sata_hba_tran == NULL) || (si_portp == NULL)) { 4329 /* the whole controller setup is not yet done. */ 4330 mutex_exit(&si_ctlp->sictl_mutex); 4331 return (SI_SUCCESS); 4332 } 4333 4334 mutex_exit(&si_ctlp->sictl_mutex); 4335 4336 mutex_enter(&si_portp->siport_mutex); 4337 4338 /* SStatus tells the presence of device. */ 4339 SStatus = ddi_get32(si_ctlp->sictl_port_acc_handle, 4340 (uint32_t *)PORT_SSTATUS(si_ctlp, port)); 4341 dev_exists_now = 4342 (SSTATUS_GET_DET(SStatus) == SSTATUS_DET_DEVPRESENT_PHYONLINE); 4343 4344 if (si_portp->siport_port_type != PORT_TYPE_NODEV) { 4345 dev_existed_previously = 1; 4346 } 4347 4348 bzero((void *)&sdevice, sizeof (sata_device_t)); 4349 sdevice.satadev_addr.cport = port; 4350 sdevice.satadev_addr.pmport = PORTMULT_CONTROL_PORT; 4351 4352 /* we don't have a way of determining the exact port-mult port. */ 4353 if (si_portp->siport_port_type == PORT_TYPE_MULTIPLIER) { 4354 sdevice.satadev_addr.qual = SATA_ADDR_PMPORT; 4355 } else { 4356 sdevice.satadev_addr.qual = SATA_ADDR_CPORT; 4357 } 4358 4359 sdevice.satadev_state = SATA_STATE_READY; /* port state */ 4360 4361 if (dev_exists_now) { 4362 if (dev_existed_previously) { 4363 4364 /* Things are fine now. The loss was temporary. */ 4365 SIDBG0(SIDBG_INTR, NULL, 4366 "phyrdy: doing BOTH EVENTS TOGETHER"); 4367 if (si_portp->siport_active) { 4368 SIDBG0(SIDBG_EVENT, si_ctlp, 4369 "sending event: LINK_LOST & " 4370 "LINK_ESTABLISHED"); 4371 4372 sata_hba_event_notify( 4373 si_ctlp->sictl_sata_hba_tran->\ 4374 sata_tran_hba_dip, 4375 &sdevice, 4376 SATA_EVNT_LINK_LOST| 4377 SATA_EVNT_LINK_ESTABLISHED); 4378 } 4379 4380 } else { 4381 4382 /* A new device has been detected. */ 4383 mutex_exit(&si_portp->siport_mutex); 4384 si_find_dev_signature(si_ctlp, si_portp, port, 4385 PORTMULT_CONTROL_PORT); 4386 mutex_enter(&si_portp->siport_mutex); 4387 SIDBG0(SIDBG_INTR, NULL, "phyrdy: doing ATTACH event"); 4388 if (si_portp->siport_active) { 4389 SIDBG0(SIDBG_EVENT, si_ctlp, 4390 "sending event up: LINK_ESTABLISHED"); 4391 4392 sata_hba_event_notify( 4393 si_ctlp->sictl_sata_hba_tran->\ 4394 sata_tran_hba_dip, 4395 &sdevice, 4396 SATA_EVNT_LINK_ESTABLISHED); 4397 } 4398 4399 } 4400 } else { /* No device exists now */ 4401 4402 if (dev_existed_previously) { 4403 4404 /* An existing device is lost. */ 4405 if (si_portp->siport_active) { 4406 SIDBG0(SIDBG_EVENT, si_ctlp, 4407 "sending event up: LINK_LOST"); 4408 4409 sata_hba_event_notify( 4410 si_ctlp->sictl_sata_hba_tran-> 4411 sata_tran_hba_dip, 4412 &sdevice, 4413 SATA_EVNT_LINK_LOST); 4414 } 4415 si_portp->siport_port_type = PORT_TYPE_NODEV; 4416 4417 } else { 4418 4419 /* spurious interrupt */ 4420 SIDBG0(SIDBG_INTR, NULL, 4421 "spurious phy ready interrupt"); 4422 } 4423 } 4424 4425 mutex_exit(&si_portp->siport_mutex); 4426 return (SI_SUCCESS); 4427 } 4428 4429 4430 /* 4431 * Interrupt which indicates that a COMWAKE OOB signal has been decoded 4432 * on the receiver. 4433 * 4434 * We are not interested in this interrupt; we just log a debug message. 4435 */ 4436 /*ARGSUSED*/ 4437 static int 4438 si_intr_comwake_rcvd( 4439 si_ctl_state_t *si_ctlp, 4440 si_port_state_t *si_portp, 4441 int port) 4442 { 4443 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_commwake_rcvd"); 4444 return (SI_SUCCESS); 4445 } 4446 4447 /* 4448 * Interrupt which indicates that the F-bit has been set in SError 4449 * Diag field. 4450 * 4451 * We are not interested in this interrupt; we just log a debug message. 4452 */ 4453 /*ARGSUSED*/ 4454 static int 4455 si_intr_unrecognised_fis( 4456 si_ctl_state_t *si_ctlp, 4457 si_port_state_t *si_portp, 4458 int port) 4459 { 4460 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_unrecognised_fis"); 4461 return (SI_SUCCESS); 4462 } 4463 4464 /* 4465 * Interrupt which indicates that the X-bit has been set in SError 4466 * Diag field. 4467 * 4468 * We are not interested in this interrupt; we just log a debug message. 4469 */ 4470 /*ARGSUSED*/ 4471 static int 4472 si_intr_dev_xchanged( 4473 si_ctl_state_t *si_ctlp, 4474 si_port_state_t *si_portp, 4475 int port) 4476 { 4477 4478 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_dev_xchanged"); 4479 return (SI_SUCCESS); 4480 } 4481 4482 /* 4483 * Interrupt which indicates that the 8b/10 Decode Error counter has 4484 * exceeded the programmed non-zero threshold value. 4485 * 4486 * We are not interested in this interrupt; we just log a debug message. 4487 */ 4488 /*ARGSUSED*/ 4489 static int 4490 si_intr_decode_err_threshold( 4491 si_ctl_state_t *si_ctlp, 4492 si_port_state_t *si_portp, 4493 int port) 4494 { 4495 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_err_threshold"); 4496 return (SI_SUCCESS); 4497 } 4498 4499 /* 4500 * Interrupt which indicates that the CRC Error counter has exceeded the 4501 * programmed non-zero threshold value. 4502 * 4503 * We are not interested in this interrupt; we just log a debug message. 4504 */ 4505 /*ARGSUSED*/ 4506 static int 4507 si_intr_crc_err_threshold( 4508 si_ctl_state_t *si_ctlp, 4509 si_port_state_t *si_portp, 4510 int port) 4511 { 4512 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_crc_threshold"); 4513 return (SI_SUCCESS); 4514 } 4515 4516 /* 4517 * Interrupt which indicates that the Handshake Error counter has 4518 * exceeded the programmed non-zero threshold value. 4519 * 4520 * We are not interested in this interrupt; we just log a debug message. 4521 */ 4522 /*ARGSUSED*/ 4523 static int 4524 si_intr_handshake_err_threshold( 4525 si_ctl_state_t *si_ctlp, 4526 si_port_state_t *si_portp, 4527 int port) 4528 { 4529 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, 4530 "si_intr_handshake_err_threshold"); 4531 return (SI_SUCCESS); 4532 } 4533 4534 /* 4535 * Interrupt which indicates that a "Set Device Bits" FIS has been 4536 * received with N-bit set in the control field. 4537 * 4538 * We are not interested in this interrupt; we just log a debug message. 4539 */ 4540 /*ARGSUSED*/ 4541 static int 4542 si_intr_set_devbits_notify( 4543 si_ctl_state_t *si_ctlp, 4544 si_port_state_t *si_portp, 4545 int port) 4546 { 4547 SIDBG0(SIDBG_INTR|SIDBG_ENTRY, si_ctlp, "si_intr_set_devbits_notify"); 4548 return (SI_SUCCESS); 4549 } 4550 4551 4552 /* 4553 * Enable the interrupts for a particular port. 4554 * 4555 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 4556 * before calling us. 4557 */ 4558 static void 4559 si_enable_port_interrupts(si_ctl_state_t *si_ctlp, int port) 4560 { 4561 uint32_t mask; 4562 4563 /* get the current settings first. */ 4564 mask = ddi_get32(si_ctlp->sictl_global_acc_handle, 4565 (uint32_t *)GLOBAL_CONTROL_REG(si_ctlp)); 4566 4567 SIDBG1(SIDBG_INIT|SIDBG_ENTRY, si_ctlp, 4568 "si_enable_port_interrupts: current mask: 0x%x", 4569 mask); 4570 4571 /* enable the bit for current port. */ 4572 SET_BIT(mask, port); 4573 4574 /* now use this mask to enable the interrupt. */ 4575 ddi_put32(si_ctlp->sictl_global_acc_handle, 4576 (uint32_t *)GLOBAL_CONTROL_REG(si_ctlp), 4577 mask); 4578 } 4579 4580 /* 4581 * Enable interrupts for all the ports. 4582 */ 4583 static void 4584 si_enable_all_interrupts(si_ctl_state_t *si_ctlp) 4585 { 4586 int port; 4587 4588 for (port = 0; port < si_ctlp->sictl_num_ports; port++) { 4589 si_enable_port_interrupts(si_ctlp, port); 4590 } 4591 } 4592 4593 /* 4594 * Disable interrupts for a particular port. 4595 * 4596 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 4597 * before calling us. 4598 */ 4599 static void 4600 si_disable_port_interrupts(si_ctl_state_t *si_ctlp, int port) 4601 { 4602 uint32_t mask; 4603 4604 /* get the current settings first. */ 4605 mask = ddi_get32(si_ctlp->sictl_global_acc_handle, 4606 (uint32_t *)GLOBAL_CONTROL_REG(si_ctlp)); 4607 4608 /* clear the bit for current port. */ 4609 CLEAR_BIT(mask, port); 4610 4611 /* now use this mask to disable the interrupt. */ 4612 ddi_put32(si_ctlp->sictl_global_acc_handle, 4613 (uint32_t *)GLOBAL_CONTROL_REG(si_ctlp), 4614 mask); 4615 4616 } 4617 4618 /* 4619 * Disable interrupts for all the ports. 4620 */ 4621 static void 4622 si_disable_all_interrupts(si_ctl_state_t *si_ctlp) 4623 { 4624 int port; 4625 4626 for (port = 0; port < si_ctlp->sictl_num_ports; port++) { 4627 si_disable_port_interrupts(si_ctlp, port); 4628 } 4629 } 4630 4631 /* 4632 * Fetches the latest sstatus, scontrol, serror, sactive registers 4633 * and stuffs them into sata_device_t structure. 4634 */ 4635 static void 4636 fill_dev_sregisters(si_ctl_state_t *si_ctlp, int port, sata_device_t *satadev) 4637 { 4638 satadev->satadev_scr.sstatus = ddi_get32(si_ctlp->sictl_port_acc_handle, 4639 (uint32_t *)(PORT_SSTATUS(si_ctlp, port))); 4640 satadev->satadev_scr.serror = ddi_get32(si_ctlp->sictl_port_acc_handle, 4641 (uint32_t *)(PORT_SERROR(si_ctlp, port))); 4642 satadev->satadev_scr.sactive = ddi_get32(si_ctlp->sictl_port_acc_handle, 4643 (uint32_t *)(PORT_SACTIVE(si_ctlp, port))); 4644 satadev->satadev_scr.scontrol = 4645 ddi_get32(si_ctlp->sictl_port_acc_handle, 4646 (uint32_t *)(PORT_SCONTROL(si_ctlp, port))); 4647 4648 } 4649 4650 /* 4651 * si_add_legacy_intrs() handles INTx and legacy interrupts. 4652 */ 4653 static int 4654 si_add_legacy_intrs(si_ctl_state_t *si_ctlp) 4655 { 4656 dev_info_t *devinfo = si_ctlp->sictl_devinfop; 4657 int actual, count = 0; 4658 int x, y, rc, inum = 0; 4659 4660 SIDBG0(SIDBG_ENTRY, si_ctlp, "si_add_legacy_intrs"); 4661 4662 /* get number of interrupts. */ 4663 rc = ddi_intr_get_nintrs(devinfo, DDI_INTR_TYPE_FIXED, &count); 4664 if ((rc != DDI_SUCCESS) || (count == 0)) { 4665 SIDBG2(SIDBG_INTR|SIDBG_INIT, si_ctlp, 4666 "ddi_intr_get_nintrs() failed, " 4667 "rc %d count %d\n", rc, count); 4668 return (DDI_FAILURE); 4669 } 4670 4671 /* Allocate an array of interrupt handles. */ 4672 si_ctlp->sictl_intr_size = count * sizeof (ddi_intr_handle_t); 4673 si_ctlp->sictl_htable = kmem_zalloc(si_ctlp->sictl_intr_size, KM_SLEEP); 4674 4675 /* call ddi_intr_alloc(). */ 4676 rc = ddi_intr_alloc(devinfo, si_ctlp->sictl_htable, DDI_INTR_TYPE_FIXED, 4677 inum, count, &actual, DDI_INTR_ALLOC_STRICT); 4678 4679 if ((rc != DDI_SUCCESS) || (actual == 0)) { 4680 SIDBG1(SIDBG_INTR|SIDBG_INIT, si_ctlp, 4681 "ddi_intr_alloc() failed, rc %d\n", rc); 4682 kmem_free(si_ctlp->sictl_htable, si_ctlp->sictl_intr_size); 4683 return (DDI_FAILURE); 4684 } 4685 4686 if (actual < count) { 4687 SIDBG2(SIDBG_INTR|SIDBG_INIT, si_ctlp, 4688 "Requested: %d, Received: %d", count, actual); 4689 4690 for (x = 0; x < actual; x++) { 4691 (void) ddi_intr_free(si_ctlp->sictl_htable[x]); 4692 } 4693 4694 kmem_free(si_ctlp->sictl_htable, si_ctlp->sictl_intr_size); 4695 return (DDI_FAILURE); 4696 } 4697 4698 si_ctlp->sictl_intr_cnt = actual; 4699 4700 /* Get intr priority. */ 4701 if (ddi_intr_get_pri(si_ctlp->sictl_htable[0], 4702 &si_ctlp->sictl_intr_pri) != DDI_SUCCESS) { 4703 SIDBG0(SIDBG_INTR|SIDBG_INIT, si_ctlp, 4704 "ddi_intr_get_pri() failed"); 4705 4706 for (x = 0; x < actual; x++) { 4707 (void) ddi_intr_free(si_ctlp->sictl_htable[x]); 4708 } 4709 4710 kmem_free(si_ctlp->sictl_htable, si_ctlp->sictl_intr_size); 4711 return (DDI_FAILURE); 4712 } 4713 4714 /* Test for high level mutex. */ 4715 if (si_ctlp->sictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 4716 SIDBG0(SIDBG_INTR|SIDBG_INIT, si_ctlp, 4717 "si_add_legacy_intrs: Hi level intr not supported"); 4718 4719 for (x = 0; x < actual; x++) { 4720 (void) ddi_intr_free(si_ctlp->sictl_htable[x]); 4721 } 4722 4723 kmem_free(si_ctlp->sictl_htable, sizeof (ddi_intr_handle_t)); 4724 4725 return (DDI_FAILURE); 4726 } 4727 4728 /* Call ddi_intr_add_handler(). */ 4729 for (x = 0; x < actual; x++) { 4730 if (ddi_intr_add_handler(si_ctlp->sictl_htable[x], si_intr, 4731 (caddr_t)si_ctlp, NULL) != DDI_SUCCESS) { 4732 SIDBG0(SIDBG_INTR|SIDBG_INIT, si_ctlp, 4733 "ddi_intr_add_handler() failed"); 4734 4735 for (y = 0; y < actual; y++) { 4736 (void) ddi_intr_free(si_ctlp->sictl_htable[y]); 4737 } 4738 4739 kmem_free(si_ctlp->sictl_htable, 4740 si_ctlp->sictl_intr_size); 4741 return (DDI_FAILURE); 4742 } 4743 } 4744 4745 /* Call ddi_intr_enable() for legacy interrupts. */ 4746 for (x = 0; x < si_ctlp->sictl_intr_cnt; x++) { 4747 (void) ddi_intr_enable(si_ctlp->sictl_htable[x]); 4748 } 4749 4750 return (DDI_SUCCESS); 4751 } 4752 4753 /* 4754 * si_add_msictl_intrs() handles MSI interrupts. 4755 */ 4756 static int 4757 si_add_msi_intrs(si_ctl_state_t *si_ctlp) 4758 { 4759 dev_info_t *devinfo = si_ctlp->sictl_devinfop; 4760 int count, avail, actual; 4761 int x, y, rc, inum = 0; 4762 4763 SIDBG0(SIDBG_ENTRY|SIDBG_INIT, si_ctlp, "si_add_msi_intrs"); 4764 4765 /* get number of interrupts. */ 4766 rc = ddi_intr_get_nintrs(devinfo, DDI_INTR_TYPE_MSI, &count); 4767 if ((rc != DDI_SUCCESS) || (count == 0)) { 4768 SIDBG2(SIDBG_INIT, si_ctlp, 4769 "ddi_intr_get_nintrs() failed, " 4770 "rc %d count %d\n", rc, count); 4771 return (DDI_FAILURE); 4772 } 4773 4774 /* get number of available interrupts. */ 4775 rc = ddi_intr_get_navail(devinfo, DDI_INTR_TYPE_MSI, &avail); 4776 if ((rc != DDI_SUCCESS) || (avail == 0)) { 4777 SIDBG2(SIDBG_INIT, si_ctlp, 4778 "ddi_intr_get_navail() failed, " 4779 "rc %d avail %d\n", rc, avail); 4780 return (DDI_FAILURE); 4781 } 4782 4783 if (avail < count) { 4784 SIDBG2(SIDBG_INIT, si_ctlp, 4785 "ddi_intr_get_nvail returned %d, navail() returned %d", 4786 count, avail); 4787 } 4788 4789 /* Allocate an array of interrupt handles. */ 4790 si_ctlp->sictl_intr_size = count * sizeof (ddi_intr_handle_t); 4791 si_ctlp->sictl_htable = kmem_alloc(si_ctlp->sictl_intr_size, KM_SLEEP); 4792 4793 /* call ddi_intr_alloc(). */ 4794 rc = ddi_intr_alloc(devinfo, si_ctlp->sictl_htable, DDI_INTR_TYPE_MSI, 4795 inum, count, &actual, DDI_INTR_ALLOC_NORMAL); 4796 4797 if ((rc != DDI_SUCCESS) || (actual == 0)) { 4798 SIDBG1(SIDBG_INIT, si_ctlp, 4799 "ddi_intr_alloc() failed, rc %d\n", rc); 4800 kmem_free(si_ctlp->sictl_htable, si_ctlp->sictl_intr_size); 4801 return (DDI_FAILURE); 4802 } 4803 4804 /* use interrupt count returned */ 4805 if (actual < count) { 4806 SIDBG2(SIDBG_INIT, si_ctlp, 4807 "Requested: %d, Received: %d", count, actual); 4808 } 4809 4810 si_ctlp->sictl_intr_cnt = actual; 4811 4812 /* 4813 * Get priority for first msi, assume remaining are all the same. 4814 */ 4815 if (ddi_intr_get_pri(si_ctlp->sictl_htable[0], 4816 &si_ctlp->sictl_intr_pri) != DDI_SUCCESS) { 4817 SIDBG0(SIDBG_INIT, si_ctlp, "ddi_intr_get_pri() failed"); 4818 4819 /* Free already allocated intr. */ 4820 for (y = 0; y < actual; y++) { 4821 (void) ddi_intr_free(si_ctlp->sictl_htable[y]); 4822 } 4823 4824 kmem_free(si_ctlp->sictl_htable, si_ctlp->sictl_intr_size); 4825 return (DDI_FAILURE); 4826 } 4827 4828 /* Test for high level mutex. */ 4829 if (si_ctlp->sictl_intr_pri >= ddi_intr_get_hilevel_pri()) { 4830 SIDBG0(SIDBG_INIT, si_ctlp, 4831 "si_add_msi_intrs: Hi level intr not supported"); 4832 4833 /* Free already allocated intr. */ 4834 for (y = 0; y < actual; y++) { 4835 (void) ddi_intr_free(si_ctlp->sictl_htable[y]); 4836 } 4837 4838 kmem_free(si_ctlp->sictl_htable, sizeof (ddi_intr_handle_t)); 4839 4840 return (DDI_FAILURE); 4841 } 4842 4843 /* Call ddi_intr_add_handler(). */ 4844 for (x = 0; x < actual; x++) { 4845 if (ddi_intr_add_handler(si_ctlp->sictl_htable[x], si_intr, 4846 (caddr_t)si_ctlp, NULL) != DDI_SUCCESS) { 4847 SIDBG0(SIDBG_INIT, si_ctlp, 4848 "ddi_intr_add_handler() failed"); 4849 4850 /* Free already allocated intr. */ 4851 for (y = 0; y < actual; y++) { 4852 (void) ddi_intr_free(si_ctlp->sictl_htable[y]); 4853 } 4854 4855 kmem_free(si_ctlp->sictl_htable, 4856 si_ctlp->sictl_intr_size); 4857 return (DDI_FAILURE); 4858 } 4859 } 4860 4861 (void) ddi_intr_get_cap(si_ctlp->sictl_htable[0], 4862 &si_ctlp->sictl_intr_cap); 4863 4864 if (si_ctlp->sictl_intr_cap & DDI_INTR_FLAG_BLOCK) { 4865 /* Call ddi_intr_block_enable() for MSI. */ 4866 (void) ddi_intr_block_enable(si_ctlp->sictl_htable, 4867 si_ctlp->sictl_intr_cnt); 4868 } else { 4869 /* Call ddi_intr_enable() for MSI non block enable. */ 4870 for (x = 0; x < si_ctlp->sictl_intr_cnt; x++) { 4871 (void) ddi_intr_enable(si_ctlp->sictl_htable[x]); 4872 } 4873 } 4874 4875 return (DDI_SUCCESS); 4876 } 4877 4878 /* 4879 * Removes the registered interrupts irrespective of whether they 4880 * were legacy or MSI. 4881 */ 4882 static void 4883 si_rem_intrs(si_ctl_state_t *si_ctlp) 4884 { 4885 int x; 4886 4887 SIDBG0(SIDBG_ENTRY, si_ctlp, "si_rem_intrs entered"); 4888 4889 /* Disable all interrupts. */ 4890 if ((si_ctlp->sictl_intr_type == DDI_INTR_TYPE_MSI) && 4891 (si_ctlp->sictl_intr_cap & DDI_INTR_FLAG_BLOCK)) { 4892 /* Call ddi_intr_block_disable(). */ 4893 (void) ddi_intr_block_disable(si_ctlp->sictl_htable, 4894 si_ctlp->sictl_intr_cnt); 4895 } else { 4896 for (x = 0; x < si_ctlp->sictl_intr_cnt; x++) { 4897 (void) ddi_intr_disable(si_ctlp->sictl_htable[x]); 4898 } 4899 } 4900 4901 /* Call ddi_intr_remove_handler(). */ 4902 for (x = 0; x < si_ctlp->sictl_intr_cnt; x++) { 4903 (void) ddi_intr_remove_handler(si_ctlp->sictl_htable[x]); 4904 (void) ddi_intr_free(si_ctlp->sictl_htable[x]); 4905 } 4906 4907 kmem_free(si_ctlp->sictl_htable, si_ctlp->sictl_intr_size); 4908 } 4909 4910 /* 4911 * Resets either the port or the device connected to the port based on 4912 * the flag variable. 4913 * 4914 * The reset effectively throws away all the pending commands. So, the caller 4915 * has to make provision to handle the pending commands. 4916 * 4917 * After the reset, we wait till the port is ready again. 4918 * 4919 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 4920 * before calling us. 4921 * 4922 * Note: Not port-mult aware. 4923 */ 4924 static int 4925 si_reset_dport_wait_till_ready( 4926 si_ctl_state_t *si_ctlp, 4927 si_port_state_t *si_portp, 4928 int port, 4929 int flag) 4930 { 4931 uint32_t port_status; 4932 int loop_count = 0; 4933 sata_device_t sdevice; 4934 uint32_t SStatus; 4935 uint32_t SControl; 4936 4937 _NOTE(ASSUMING_PROTECTED(si_portp)) 4938 4939 if (flag == SI_PORT_RESET) { 4940 ddi_put32(si_ctlp->sictl_port_acc_handle, 4941 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 4942 PORT_CONTROL_SET_BITS_PORT_RESET); 4943 4944 /* Port reset is not self clearing. So clear it now. */ 4945 ddi_put32(si_ctlp->sictl_port_acc_handle, 4946 (uint32_t *)PORT_CONTROL_CLEAR(si_ctlp, port), 4947 PORT_CONTROL_CLEAR_BITS_PORT_RESET); 4948 } else { 4949 /* Reset the device. */ 4950 ddi_put32(si_ctlp->sictl_port_acc_handle, 4951 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 4952 PORT_CONTROL_SET_BITS_DEV_RESET); 4953 4954 /* 4955 * tidbit: this bit is self clearing; so there is no need 4956 * for manual clear as we did for port reset. 4957 */ 4958 } 4959 4960 /* Set the reset in progress flag */ 4961 if (!(flag & SI_RESET_NO_EVENTS_UP)) { 4962 si_portp->siport_reset_in_progress = 1; 4963 } 4964 4965 /* 4966 * For some reason, we are losing the interrupt enablement after 4967 * any reset condition. So restore them back now. 4968 */ 4969 SIDBG1(SIDBG_INIT, si_ctlp, 4970 "current interrupt enable set: 0x%x", 4971 ddi_get32(si_ctlp->sictl_port_acc_handle, 4972 (uint32_t *)PORT_INTERRUPT_ENABLE_SET(si_ctlp, port))); 4973 4974 ddi_put32(si_ctlp->sictl_port_acc_handle, 4975 (uint32_t *)PORT_INTERRUPT_ENABLE_SET(si_ctlp, port), 4976 (INTR_COMMAND_COMPLETE | 4977 INTR_COMMAND_ERROR | 4978 INTR_PORT_READY | 4979 INTR_POWER_CHANGE | 4980 INTR_PHYRDY_CHANGE | 4981 INTR_COMWAKE_RECEIVED | 4982 INTR_UNRECOG_FIS | 4983 INTR_DEV_XCHANGED | 4984 INTR_SETDEVBITS_NOTIFY)); 4985 4986 si_enable_port_interrupts(si_ctlp, port); 4987 4988 /* 4989 * Every reset needs a PHY initialization. 4990 * 4991 * The way to initialize the PHY is to write a 1 and then 4992 * a 0 to DET field of SControl register. 4993 */ 4994 4995 /* Fetch the current SControl before writing the DET part with 1. */ 4996 SControl = ddi_get32(si_ctlp->sictl_port_acc_handle, 4997 (uint32_t *)PORT_SCONTROL(si_ctlp, port)); 4998 SCONTROL_SET_DET(SControl, SCONTROL_DET_COMRESET); 4999 ddi_put32(si_ctlp->sictl_port_acc_handle, 5000 (uint32_t *)(PORT_SCONTROL(si_ctlp, port)), 5001 SControl); 5002 #ifndef __lock_lint 5003 delay(SI_10MS_TICKS); /* give time for COMRESET to percolate */ 5004 #endif /* __lock_lint */ 5005 5006 /* Now fetch the SControl again and rewrite the DET part with 0 */ 5007 SControl = ddi_get32(si_ctlp->sictl_port_acc_handle, 5008 (uint32_t *)PORT_SCONTROL(si_ctlp, port)); 5009 SCONTROL_SET_DET(SControl, SCONTROL_DET_NOACTION); 5010 ddi_put32(si_ctlp->sictl_port_acc_handle, 5011 (uint32_t *)(PORT_SCONTROL(si_ctlp, port)), 5012 SControl); 5013 5014 /* 5015 * PHY may be initialized by now. Check the DET field of SStatus 5016 * to determine if there is a device present. 5017 * 5018 * The DET field is valid only if IPM field indicates that 5019 * the interface is in active state. 5020 */ 5021 5022 loop_count = 0; 5023 do { 5024 SStatus = ddi_get32(si_ctlp->sictl_port_acc_handle, 5025 (uint32_t *)PORT_SSTATUS(si_ctlp, port)); 5026 5027 if (SSTATUS_GET_IPM(SStatus) != 5028 SSTATUS_IPM_INTERFACE_ACTIVE) { 5029 /* 5030 * If the interface is not active, the DET field 5031 * is considered not accurate. So we want to 5032 * continue looping. 5033 */ 5034 SSTATUS_SET_DET(SStatus, SSTATUS_DET_NODEV_NOPHY); 5035 } 5036 5037 if (loop_count++ > SI_POLLRATE_SSTATUS) { 5038 /* We are effectively timing out after 0.1 sec. */ 5039 break; 5040 } 5041 5042 /* Wait for 10 millisec */ 5043 #ifndef __lock_lint 5044 delay(SI_10MS_TICKS); 5045 #endif /* __lock_lint */ 5046 5047 } while (SSTATUS_GET_DET(SStatus) != SSTATUS_DET_DEVPRESENT_PHYONLINE); 5048 5049 SIDBG2(SIDBG_POLL_LOOP, si_ctlp, 5050 "si_reset_dport_wait_till_ready: loop count: %d, \ 5051 SStatus: 0x%x", 5052 loop_count, 5053 SStatus); 5054 5055 /* Now check for port readiness. */ 5056 loop_count = 0; 5057 do { 5058 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 5059 (uint32_t *)PORT_STATUS(si_ctlp, port)); 5060 5061 if (loop_count++ > SI_POLLRATE_PORTREADY) { 5062 /* We are effectively timing out after 0.5 sec. */ 5063 break; 5064 } 5065 5066 /* Wait for 10 millisec */ 5067 #ifndef __lock_lint 5068 delay(SI_10MS_TICKS); 5069 #endif /* __lock_lint */ 5070 5071 } while (!(port_status & PORT_STATUS_BITS_PORT_READY)); 5072 5073 SIDBG3(SIDBG_POLL_LOOP, si_ctlp, 5074 "si_reset_dport_wait_till_ready: loop count: %d, \ 5075 port_status: 0x%x, SStatus: 0x%x", 5076 loop_count, 5077 port_status, 5078 SStatus); 5079 5080 /* Indicate to the framework that a reset has happened. */ 5081 if (!(flag & SI_RESET_NO_EVENTS_UP)) { 5082 5083 bzero((void *)&sdevice, sizeof (sata_device_t)); 5084 sdevice.satadev_addr.cport = port; 5085 sdevice.satadev_addr.pmport = PORTMULT_CONTROL_PORT; 5086 5087 if (si_portp->siport_port_type == PORT_TYPE_MULTIPLIER) { 5088 sdevice.satadev_addr.qual = SATA_ADDR_DPMPORT; 5089 } else { 5090 sdevice.satadev_addr.qual = SATA_ADDR_DCPORT; 5091 } 5092 sdevice.satadev_state = SATA_DSTATE_RESET | 5093 SATA_DSTATE_PWR_ACTIVE; 5094 if (si_ctlp->sictl_sata_hba_tran) { 5095 sata_hba_event_notify( 5096 si_ctlp->sictl_sata_hba_tran->sata_tran_hba_dip, 5097 &sdevice, 5098 SATA_EVNT_DEVICE_RESET); 5099 } 5100 5101 SIDBG0(SIDBG_EVENT, si_ctlp, 5102 "sending event up: SATA_EVNT_RESET"); 5103 } 5104 5105 if ((SSTATUS_GET_IPM(SStatus) == SSTATUS_IPM_INTERFACE_ACTIVE) && 5106 (SSTATUS_GET_DET(SStatus) == 5107 SSTATUS_DET_DEVPRESENT_PHYONLINE)) { 5108 /* The interface is active and the device is present */ 5109 if (!(port_status & PORT_STATUS_BITS_PORT_READY)) { 5110 /* But the port is is not ready for some reason */ 5111 SIDBG0(SIDBG_POLL_LOOP, si_ctlp, 5112 "si_reset_dport_wait_till_ready failed"); 5113 return (SI_FAILURE); 5114 } 5115 } 5116 5117 SIDBG0(SIDBG_POLL_LOOP, si_ctlp, 5118 "si_reset_dport_wait_till_ready returning success"); 5119 5120 return (SI_SUCCESS); 5121 } 5122 5123 /* 5124 * Initializes the port. 5125 * 5126 * Initialization effectively throws away all the pending commands on 5127 * the port. So, the caller has to make provision to handle the pending 5128 * commands. 5129 * 5130 * After the port initialization, we wait till the port is ready again. 5131 * 5132 * WARNING, WARNING: The caller is expected to obtain the siport_mutex 5133 * before calling us. 5134 */ 5135 static int 5136 si_initialize_port_wait_till_ready(si_ctl_state_t *si_ctlp, int port) 5137 { 5138 uint32_t port_status; 5139 int loop_count = 0; 5140 uint32_t SStatus; 5141 5142 /* Initialize the port. */ 5143 ddi_put32(si_ctlp->sictl_port_acc_handle, 5144 (uint32_t *)PORT_CONTROL_SET(si_ctlp, port), 5145 PORT_CONTROL_SET_BITS_PORT_INITIALIZE); 5146 5147 /* Wait until Port Ready */ 5148 loop_count = 0; 5149 do { 5150 port_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 5151 (uint32_t *)PORT_STATUS(si_ctlp, port)); 5152 5153 if (loop_count++ > SI_POLLRATE_PORTREADY) { 5154 SIDBG1(SIDBG_INTR, si_ctlp, 5155 "si_initialize_port_wait is timing out: " 5156 "port_status: %x", 5157 port_status); 5158 /* We are effectively timing out after 0.5 sec. */ 5159 break; 5160 } 5161 5162 /* Wait for 10 millisec */ 5163 #ifndef __lock_lint 5164 delay(SI_10MS_TICKS); 5165 #endif /* __lock_lint */ 5166 5167 } while (!(port_status & PORT_STATUS_BITS_PORT_READY)); 5168 5169 SIDBG1(SIDBG_POLL_LOOP, si_ctlp, 5170 "si_initialize_port_wait_till_ready: loop count: %d", 5171 loop_count); 5172 5173 SStatus = ddi_get32(si_ctlp->sictl_port_acc_handle, 5174 (uint32_t *)PORT_SSTATUS(si_ctlp, port)); 5175 5176 if ((SSTATUS_GET_IPM(SStatus) == SSTATUS_IPM_INTERFACE_ACTIVE) && 5177 (SSTATUS_GET_DET(SStatus) == 5178 SSTATUS_DET_DEVPRESENT_PHYONLINE)) { 5179 /* The interface is active and the device is present */ 5180 if (!(port_status & PORT_STATUS_BITS_PORT_READY)) { 5181 /* But the port is is not ready for some reason */ 5182 return (SI_FAILURE); 5183 } 5184 } 5185 5186 return (SI_SUCCESS); 5187 } 5188 5189 5190 /* 5191 * si_watchdog_handler() calls us if it detects that there are some 5192 * commands which timed out. We recalculate the timed out commands once 5193 * again since some of them may have finished recently. 5194 */ 5195 static void 5196 si_timeout_pkts( 5197 si_ctl_state_t *si_ctlp, 5198 si_port_state_t *si_portp, 5199 int port, 5200 uint32_t timedout_tags) 5201 { 5202 uint32_t slot_status; 5203 uint32_t finished_tags; 5204 5205 SIDBG0(SIDBG_TIMEOUT|SIDBG_ENTRY, si_ctlp, "si_timeout_pkts entry"); 5206 5207 mutex_enter(&si_portp->siport_mutex); 5208 slot_status = ddi_get32(si_ctlp->sictl_port_acc_handle, 5209 (uint32_t *)(PORT_SLOT_STATUS(si_ctlp, port))); 5210 5211 /* 5212 * Initialize the controller. The only way to timeout the commands 5213 * is to reset or initialize the controller. We mop commands after 5214 * the initialization. 5215 */ 5216 (void) si_initialize_port_wait_till_ready(si_ctlp, port); 5217 5218 /* 5219 * Recompute the timedout tags since some of them may have finished 5220 * meanwhile. 5221 */ 5222 finished_tags = si_portp->siport_pending_tags & 5223 ~slot_status & SI_SLOT_MASK; 5224 timedout_tags &= ~finished_tags; 5225 5226 SIDBG2(SIDBG_TIMEOUT, si_ctlp, 5227 "si_timeout_pkts: finished: %x, timeout: %x", 5228 finished_tags, 5229 timedout_tags); 5230 5231 mutex_exit(&si_portp->siport_mutex); 5232 si_mop_commands(si_ctlp, 5233 si_portp, 5234 port, 5235 slot_status, 5236 0, /* failed_tags */ 5237 timedout_tags, 5238 0, /* aborting_tags */ 5239 0); /* reset_tags */ 5240 5241 } 5242 5243 5244 5245 /* 5246 * Watchdog handler kicks in every 5 seconds to timeout any commands pending 5247 * for long time. 5248 */ 5249 static void 5250 si_watchdog_handler(si_ctl_state_t *si_ctlp) 5251 { 5252 uint32_t pending_tags = 0; 5253 uint32_t timedout_tags = 0; 5254 si_port_state_t *si_portp; 5255 int port; 5256 int tmpslot; 5257 sata_pkt_t *satapkt; 5258 5259 /* max number of cycles this packet should survive */ 5260 int max_life_cycles; 5261 5262 /* how many cycles this packet survived so far */ 5263 int watched_cycles; 5264 5265 mutex_enter(&si_ctlp->sictl_mutex); 5266 SIDBG0(SIDBG_TIMEOUT|SIDBG_ENTRY, si_ctlp, 5267 "si_watchdog_handler entered"); 5268 5269 for (port = 0; port < si_ctlp->sictl_num_ports; port++) { 5270 5271 si_portp = si_ctlp->sictl_ports[port]; 5272 if (si_portp == NULL) { 5273 continue; 5274 } 5275 5276 mutex_enter(&si_portp->siport_mutex); 5277 5278 if (si_portp->siport_port_type == PORT_TYPE_NODEV) { 5279 mutex_exit(&si_portp->siport_mutex); 5280 continue; 5281 } 5282 5283 pending_tags = si_portp->siport_pending_tags; 5284 timedout_tags = 0; 5285 while (pending_tags) { 5286 tmpslot = ddi_ffs(pending_tags) - 1; 5287 if (tmpslot == -1) { 5288 break; 5289 } 5290 satapkt = si_portp->siport_slot_pkts[tmpslot]; 5291 5292 if ((satapkt != NULL) && satapkt->satapkt_time) { 5293 5294 /* 5295 * We are overloading satapkt_hba_driver_private 5296 * with watched_cycle count. 5297 * 5298 * If a packet has survived for more than it's 5299 * max life cycles, it is a candidate for time 5300 * out. 5301 */ 5302 watched_cycles = (int)(intptr_t) 5303 satapkt->satapkt_hba_driver_private; 5304 watched_cycles++; 5305 max_life_cycles = (satapkt->satapkt_time + 5306 si_watchdog_timeout - 1) / 5307 si_watchdog_timeout; 5308 if (watched_cycles > max_life_cycles) { 5309 timedout_tags |= (0x1 << tmpslot); 5310 SIDBG1(SIDBG_TIMEOUT|SIDBG_VERBOSE, 5311 si_ctlp, 5312 "watchdog: timedout_tags: 0x%x", 5313 timedout_tags); 5314 } 5315 satapkt->satapkt_hba_driver_private = 5316 (void *)(intptr_t)watched_cycles; 5317 } 5318 5319 CLEAR_BIT(pending_tags, tmpslot); 5320 } 5321 5322 if (timedout_tags) { 5323 mutex_exit(&si_portp->siport_mutex); 5324 mutex_exit(&si_ctlp->sictl_mutex); 5325 si_timeout_pkts(si_ctlp, si_portp, port, timedout_tags); 5326 mutex_enter(&si_ctlp->sictl_mutex); 5327 mutex_enter(&si_portp->siport_mutex); 5328 } 5329 5330 mutex_exit(&si_portp->siport_mutex); 5331 } 5332 5333 /* Reinstall the watchdog timeout handler. */ 5334 if (!(si_ctlp->sictl_flags & SI_NO_TIMEOUTS)) { 5335 si_ctlp->sictl_timeout_id = 5336 timeout((void (*)(void *))si_watchdog_handler, 5337 (caddr_t)si_ctlp, si_watchdog_tick); 5338 } 5339 mutex_exit(&si_ctlp->sictl_mutex); 5340 } 5341 5342 5343 /* 5344 * Logs the message. 5345 */ 5346 static void 5347 si_log(si_ctl_state_t *si_ctlp, uint_t level, char *fmt, ...) 5348 { 5349 va_list ap; 5350 5351 mutex_enter(&si_log_mutex); 5352 5353 va_start(ap, fmt); 5354 if (si_ctlp) { 5355 (void) sprintf(si_log_buf, "%s-[%d]:", 5356 ddi_get_name(si_ctlp->sictl_devinfop), 5357 ddi_get_instance(si_ctlp->sictl_devinfop)); 5358 } else { 5359 (void) sprintf(si_log_buf, "si3124:"); 5360 } 5361 (void) vsprintf(si_log_buf, fmt, ap); 5362 va_end(ap); 5363 5364 cmn_err(level, "%s", si_log_buf); 5365 5366 mutex_exit(&si_log_mutex); 5367 5368 } 5369 5370 static void 5371 si_copy_out_regs(sata_cmd_t *scmd, fis_reg_h2d_t *fisp) 5372 { 5373 fis_reg_h2d_t fis = *fisp; 5374 5375 if (scmd->satacmd_flags.sata_copy_out_sec_count_msb) 5376 scmd->satacmd_sec_count_msb = GET_FIS_SECTOR_COUNT_EXP(fis); 5377 if (scmd->satacmd_flags.sata_copy_out_lba_low_msb) 5378 scmd->satacmd_lba_low_msb = GET_FIS_SECTOR_EXP(fis); 5379 if (scmd->satacmd_flags.sata_copy_out_lba_mid_msb) 5380 scmd->satacmd_lba_mid_msb = GET_FIS_CYL_LOW_EXP(fis); 5381 if (scmd->satacmd_flags.sata_copy_out_lba_high_msb) 5382 scmd->satacmd_lba_high_msb = GET_FIS_CYL_HI_EXP(fis); 5383 if (scmd->satacmd_flags.sata_copy_out_sec_count_lsb) 5384 scmd->satacmd_sec_count_lsb = GET_FIS_SECTOR_COUNT(fis); 5385 if (scmd->satacmd_flags.sata_copy_out_lba_low_lsb) 5386 scmd->satacmd_lba_low_lsb = GET_FIS_SECTOR(fis); 5387 if (scmd->satacmd_flags.sata_copy_out_lba_mid_lsb) 5388 scmd->satacmd_lba_mid_lsb = GET_FIS_CYL_LOW(fis); 5389 if (scmd->satacmd_flags.sata_copy_out_lba_high_lsb) 5390 scmd->satacmd_lba_high_lsb = GET_FIS_CYL_HI(fis); 5391 if (scmd->satacmd_flags.sata_copy_out_device_reg) 5392 scmd->satacmd_device_reg = GET_FIS_DEV_HEAD(fis); 5393 if (scmd->satacmd_flags.sata_copy_out_error_reg) 5394 scmd->satacmd_error_reg = GET_FIS_FEATURES(fis); 5395 } 5396