1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved. 24 * Copyright 2016 Nexenta Systems, Inc. All rights reserved. 25 * Copyright 2016 Joyent, Inc. 26 * Copyright 2014 OmniTI Computer Consulting, Inc. All rights reserved. 27 * Copyright (c) 2014, Tegile Systems Inc. All rights reserved. 28 */ 29 30 /* 31 * Copyright (c) 2000 to 2010, LSI Corporation. 32 * All rights reserved. 33 * 34 * Redistribution and use in source and binary forms of all code within 35 * this file that is exclusively owned by LSI, with or without 36 * modification, is permitted provided that, in addition to the CDDL 1.0 37 * License requirements, the following conditions are met: 38 * 39 * Neither the name of the author nor the names of its contributors may be 40 * used to endorse or promote products derived from this software without 41 * specific prior written permission. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 44 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 45 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 46 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 47 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 49 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 50 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 51 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 52 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 53 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 54 * DAMAGE. 55 */ 56 57 /* 58 * mptsas - This is a driver based on LSI Logic's MPT2.0/2.5 interface. 59 * 60 */ 61 62 #if defined(lint) || defined(DEBUG) 63 #define MPTSAS_DEBUG 64 #endif 65 66 /* 67 * standard header files. 68 */ 69 #include <sys/note.h> 70 #include <sys/scsi/scsi.h> 71 #include <sys/pci.h> 72 #include <sys/file.h> 73 #include <sys/policy.h> 74 #include <sys/model.h> 75 #include <sys/sysevent.h> 76 #include <sys/sysevent/eventdefs.h> 77 #include <sys/sysevent/dr.h> 78 #include <sys/sata/sata_defs.h> 79 #include <sys/sata/sata_hba.h> 80 #include <sys/scsi/generic/sas.h> 81 #include <sys/scsi/impl/scsi_sas.h> 82 83 #pragma pack(1) 84 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_type.h> 85 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2.h> 86 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h> 87 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_init.h> 88 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_ioc.h> 89 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_sas.h> 90 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h> 91 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_raid.h> 92 #pragma pack() 93 94 /* 95 * private header files. 96 * 97 */ 98 #include <sys/scsi/impl/scsi_reset_notify.h> 99 #include <sys/scsi/adapters/mpt_sas/mptsas_var.h> 100 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h> 101 #include <sys/scsi/adapters/mpt_sas/mptsas_smhba.h> 102 #include <sys/scsi/adapters/mpt_sas/mptsas_hash.h> 103 #include <sys/raidioctl.h> 104 105 #include <sys/fs/dv_node.h> /* devfs_clean */ 106 107 /* 108 * FMA header files 109 */ 110 #include <sys/ddifm.h> 111 #include <sys/fm/protocol.h> 112 #include <sys/fm/util.h> 113 #include <sys/fm/io/ddi.h> 114 115 /* 116 * autoconfiguration data and routines. 117 */ 118 static int mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 119 static int mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd); 120 static int mptsas_power(dev_info_t *dip, int component, int level); 121 122 /* 123 * cb_ops function 124 */ 125 static int mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode, 126 cred_t *credp, int *rval); 127 #ifdef __sparc 128 static int mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd); 129 #else /* __sparc */ 130 static int mptsas_quiesce(dev_info_t *devi); 131 #endif /* __sparc */ 132 133 /* 134 * Resource initilaization for hardware 135 */ 136 static void mptsas_setup_cmd_reg(mptsas_t *mpt); 137 static void mptsas_disable_bus_master(mptsas_t *mpt); 138 static void mptsas_hba_fini(mptsas_t *mpt); 139 static void mptsas_cfg_fini(mptsas_t *mptsas_blkp); 140 static int mptsas_hba_setup(mptsas_t *mpt); 141 static void mptsas_hba_teardown(mptsas_t *mpt); 142 static int mptsas_config_space_init(mptsas_t *mpt); 143 static void mptsas_config_space_fini(mptsas_t *mpt); 144 static void mptsas_iport_register(mptsas_t *mpt); 145 static int mptsas_smp_setup(mptsas_t *mpt); 146 static void mptsas_smp_teardown(mptsas_t *mpt); 147 static int mptsas_enc_setup(mptsas_t *mpt); 148 static void mptsas_enc_teardown(mptsas_t *mpt); 149 static int mptsas_cache_create(mptsas_t *mpt); 150 static void mptsas_cache_destroy(mptsas_t *mpt); 151 static int mptsas_alloc_request_frames(mptsas_t *mpt); 152 static int mptsas_alloc_sense_bufs(mptsas_t *mpt); 153 static int mptsas_alloc_reply_frames(mptsas_t *mpt); 154 static int mptsas_alloc_free_queue(mptsas_t *mpt); 155 static int mptsas_alloc_post_queue(mptsas_t *mpt); 156 static void mptsas_alloc_reply_args(mptsas_t *mpt); 157 static int mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd); 158 static void mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd); 159 static int mptsas_init_chip(mptsas_t *mpt, int first_time); 160 static void mptsas_update_hashtab(mptsas_t *mpt); 161 162 /* 163 * SCSA function prototypes 164 */ 165 static int mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt); 166 static int mptsas_scsi_reset(struct scsi_address *ap, int level); 167 static int mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt); 168 static int mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly); 169 static int mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value, 170 int tgtonly); 171 static void mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt); 172 static struct scsi_pkt *mptsas_scsi_init_pkt(struct scsi_address *ap, 173 struct scsi_pkt *pkt, struct buf *bp, int cmdlen, int statuslen, 174 int tgtlen, int flags, int (*callback)(), caddr_t arg); 175 static void mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt); 176 static void mptsas_scsi_destroy_pkt(struct scsi_address *ap, 177 struct scsi_pkt *pkt); 178 static int mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip, 179 scsi_hba_tran_t *hba_tran, struct scsi_device *sd); 180 static void mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip, 181 scsi_hba_tran_t *hba_tran, struct scsi_device *sd); 182 static int mptsas_scsi_reset_notify(struct scsi_address *ap, int flag, 183 void (*callback)(caddr_t), caddr_t arg); 184 static int mptsas_get_name(struct scsi_device *sd, char *name, int len); 185 static int mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len); 186 static int mptsas_scsi_quiesce(dev_info_t *dip); 187 static int mptsas_scsi_unquiesce(dev_info_t *dip); 188 static int mptsas_bus_config(dev_info_t *pdip, uint_t flags, 189 ddi_bus_config_op_t op, void *arg, dev_info_t **childp); 190 191 /* 192 * SMP functions 193 */ 194 static int mptsas_smp_start(struct smp_pkt *smp_pkt); 195 196 /* 197 * internal function prototypes. 198 */ 199 static void mptsas_list_add(mptsas_t *mpt); 200 static void mptsas_list_del(mptsas_t *mpt); 201 202 static int mptsas_quiesce_bus(mptsas_t *mpt); 203 static int mptsas_unquiesce_bus(mptsas_t *mpt); 204 205 static int mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size); 206 static void mptsas_free_handshake_msg(mptsas_t *mpt); 207 208 static void mptsas_ncmds_checkdrain(void *arg); 209 210 static int mptsas_prepare_pkt(mptsas_cmd_t *cmd); 211 static int mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *sp); 212 static int mptsas_accept_txwq_and_pkt(mptsas_t *mpt, mptsas_cmd_t *sp); 213 static void mptsas_accept_tx_waitq(mptsas_t *mpt); 214 215 static int mptsas_do_detach(dev_info_t *dev); 216 static int mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl); 217 static int mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun, 218 struct scsi_pkt *pkt); 219 static int mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp); 220 221 static void mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd); 222 static void mptsas_handle_event(void *args); 223 static int mptsas_handle_event_sync(void *args); 224 static void mptsas_handle_dr(void *args); 225 static void mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node, 226 dev_info_t *pdip); 227 228 static void mptsas_restart_cmd(void *); 229 230 static void mptsas_flush_hba(mptsas_t *mpt); 231 static void mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun, 232 uint8_t tasktype); 233 static void mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd, 234 uchar_t reason, uint_t stat); 235 236 static uint_t mptsas_intr(caddr_t arg1, caddr_t arg2); 237 static void mptsas_process_intr(mptsas_t *mpt, 238 pMpi2ReplyDescriptorsUnion_t reply_desc_union); 239 static void mptsas_handle_scsi_io_success(mptsas_t *mpt, 240 pMpi2ReplyDescriptorsUnion_t reply_desc); 241 static void mptsas_handle_address_reply(mptsas_t *mpt, 242 pMpi2ReplyDescriptorsUnion_t reply_desc); 243 static int mptsas_wait_intr(mptsas_t *mpt, int polltime); 244 static void mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd, 245 uint32_t *control, pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl); 246 247 static void mptsas_watch(void *arg); 248 static void mptsas_watchsubr(mptsas_t *mpt); 249 static void mptsas_cmd_timeout(mptsas_t *mpt, mptsas_target_t *ptgt); 250 251 static void mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd); 252 static int mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply, 253 uint8_t *data, uint32_t request_size, uint32_t reply_size, 254 uint32_t data_size, uint32_t direction, uint8_t *dataout, 255 uint32_t dataout_size, short timeout, int mode); 256 static int mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl); 257 258 static uint8_t mptsas_get_fw_diag_buffer_number(mptsas_t *mpt, 259 uint32_t unique_id); 260 static void mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd); 261 static int mptsas_post_fw_diag_buffer(mptsas_t *mpt, 262 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code); 263 static int mptsas_release_fw_diag_buffer(mptsas_t *mpt, 264 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code, 265 uint32_t diag_type); 266 static int mptsas_diag_register(mptsas_t *mpt, 267 mptsas_fw_diag_register_t *diag_register, uint32_t *return_code); 268 static int mptsas_diag_unregister(mptsas_t *mpt, 269 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code); 270 static int mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query, 271 uint32_t *return_code); 272 static int mptsas_diag_read_buffer(mptsas_t *mpt, 273 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf, 274 uint32_t *return_code, int ioctl_mode); 275 static int mptsas_diag_release(mptsas_t *mpt, 276 mptsas_fw_diag_release_t *diag_release, uint32_t *return_code); 277 static int mptsas_do_diag_action(mptsas_t *mpt, uint32_t action, 278 uint8_t *diag_action, uint32_t length, uint32_t *return_code, 279 int ioctl_mode); 280 static int mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *data, 281 int mode); 282 283 static int mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd, 284 int cmdlen, int tgtlen, int statuslen, int kf); 285 static void mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd); 286 287 static int mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags); 288 static void mptsas_kmem_cache_destructor(void *buf, void *cdrarg); 289 290 static int mptsas_cache_frames_constructor(void *buf, void *cdrarg, 291 int kmflags); 292 static void mptsas_cache_frames_destructor(void *buf, void *cdrarg); 293 294 static void mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply, 295 mptsas_cmd_t *cmd); 296 static void mptsas_check_task_mgt(mptsas_t *mpt, 297 pMpi2SCSIManagementReply_t reply, mptsas_cmd_t *cmd); 298 static int mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap, 299 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp, 300 int *resid); 301 302 static int mptsas_alloc_active_slots(mptsas_t *mpt, int flag); 303 static void mptsas_free_active_slots(mptsas_t *mpt); 304 static int mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd); 305 306 static void mptsas_restart_hba(mptsas_t *mpt); 307 static void mptsas_restart_waitq(mptsas_t *mpt); 308 309 static void mptsas_deliver_doneq_thread(mptsas_t *mpt); 310 static void mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd); 311 static void mptsas_doneq_mv(mptsas_t *mpt, uint64_t t); 312 313 static mptsas_cmd_t *mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t); 314 static void mptsas_doneq_empty(mptsas_t *mpt); 315 static void mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg); 316 317 static mptsas_cmd_t *mptsas_waitq_rm(mptsas_t *mpt); 318 static void mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd); 319 static mptsas_cmd_t *mptsas_tx_waitq_rm(mptsas_t *mpt); 320 static void mptsas_tx_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd); 321 322 323 static void mptsas_start_watch_reset_delay(); 324 static void mptsas_setup_bus_reset_delay(mptsas_t *mpt); 325 static void mptsas_watch_reset_delay(void *arg); 326 static int mptsas_watch_reset_delay_subr(mptsas_t *mpt); 327 328 /* 329 * helper functions 330 */ 331 static void mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd); 332 333 static dev_info_t *mptsas_find_child(dev_info_t *pdip, char *name); 334 static dev_info_t *mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy); 335 static dev_info_t *mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr, 336 int lun); 337 static mdi_pathinfo_t *mptsas_find_path_addr(dev_info_t *pdip, uint64_t sasaddr, 338 int lun); 339 static mdi_pathinfo_t *mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy); 340 static dev_info_t *mptsas_find_smp_child(dev_info_t *pdip, char *str_wwn); 341 342 static int mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy, 343 int *lun); 344 static int mptsas_parse_smp_name(char *name, uint64_t *wwn); 345 346 static mptsas_target_t *mptsas_phy_to_tgt(mptsas_t *mpt, 347 mptsas_phymask_t phymask, uint8_t phy); 348 static mptsas_target_t *mptsas_wwid_to_ptgt(mptsas_t *mpt, 349 mptsas_phymask_t phymask, uint64_t wwid); 350 static mptsas_smp_t *mptsas_wwid_to_psmp(mptsas_t *mpt, 351 mptsas_phymask_t phymask, uint64_t wwid); 352 353 static int mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun, 354 uchar_t page, unsigned char *buf, int len, int *rlen, uchar_t evpd); 355 356 static int mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address, 357 uint16_t *handle, mptsas_target_t **pptgt); 358 static void mptsas_update_phymask(mptsas_t *mpt); 359 360 static int mptsas_send_sep(mptsas_t *mpt, mptsas_target_t *ptgt, 361 uint32_t *status, uint8_t cmd); 362 static dev_info_t *mptsas_get_dip_from_dev(dev_t dev, 363 mptsas_phymask_t *phymask); 364 static mptsas_target_t *mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr, 365 mptsas_phymask_t phymask); 366 static int mptsas_flush_led_status(mptsas_t *mpt, mptsas_target_t *ptgt); 367 368 369 /* 370 * Enumeration / DR functions 371 */ 372 static void mptsas_config_all(dev_info_t *pdip); 373 static int mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun, 374 dev_info_t **lundip); 375 static int mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun, 376 dev_info_t **lundip); 377 378 static int mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt); 379 static int mptsas_offline_target(dev_info_t *pdip, char *name); 380 381 static int mptsas_config_raid(dev_info_t *pdip, uint16_t target, 382 dev_info_t **dip); 383 384 static int mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt); 385 static int mptsas_probe_lun(dev_info_t *pdip, int lun, 386 dev_info_t **dip, mptsas_target_t *ptgt); 387 388 static int mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq, 389 dev_info_t **dip, mptsas_target_t *ptgt, int lun); 390 391 static int mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *sd, 392 char *guid, dev_info_t **dip, mptsas_target_t *ptgt, int lun); 393 static int mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *sd, 394 char *guid, dev_info_t **dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt, 395 int lun); 396 397 static void mptsas_offline_missed_luns(dev_info_t *pdip, 398 uint16_t *repluns, int lun_cnt, mptsas_target_t *ptgt); 399 static int mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip, 400 mdi_pathinfo_t *rpip, uint_t flags); 401 402 static int mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn, 403 dev_info_t **smp_dip); 404 static int mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, 405 uint_t flags); 406 407 static int mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data, 408 int mode, int *rval); 409 static int mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data, 410 int mode, int *rval); 411 static int mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data, 412 int mode, int *rval); 413 static void mptsas_record_event(void *args); 414 static int mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data, 415 int mode); 416 417 mptsas_target_t *mptsas_tgt_alloc(refhash_t *, uint16_t, uint64_t, 418 uint32_t, mptsas_phymask_t, uint8_t); 419 static mptsas_smp_t *mptsas_smp_alloc(mptsas_t *, mptsas_smp_t *); 420 static int mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, 421 dev_info_t **smp_dip); 422 423 /* 424 * Power management functions 425 */ 426 static int mptsas_get_pci_cap(mptsas_t *mpt); 427 static int mptsas_init_pm(mptsas_t *mpt); 428 429 /* 430 * MPT MSI tunable: 431 * 432 * By default MSI is enabled on all supported platforms. 433 */ 434 boolean_t mptsas_enable_msi = B_TRUE; 435 boolean_t mptsas_physical_bind_failed_page_83 = B_FALSE; 436 437 /* 438 * Global switch for use of MPI2.5 FAST PATH. 439 * We don't really know what FAST PATH actually does, so if it is suspected 440 * to cause problems it can be turned off by setting this variable to B_FALSE. 441 */ 442 boolean_t mptsas_use_fastpath = B_TRUE; 443 444 static int mptsas_register_intrs(mptsas_t *); 445 static void mptsas_unregister_intrs(mptsas_t *); 446 static int mptsas_add_intrs(mptsas_t *, int); 447 static void mptsas_rem_intrs(mptsas_t *); 448 449 /* 450 * FMA Prototypes 451 */ 452 static void mptsas_fm_init(mptsas_t *mpt); 453 static void mptsas_fm_fini(mptsas_t *mpt); 454 static int mptsas_fm_error_cb(dev_info_t *, ddi_fm_error_t *, const void *); 455 456 extern pri_t minclsyspri, maxclsyspri; 457 458 /* 459 * This device is created by the SCSI pseudo nexus driver (SCSI vHCI). It is 460 * under this device that the paths to a physical device are created when 461 * MPxIO is used. 462 */ 463 extern dev_info_t *scsi_vhci_dip; 464 465 /* 466 * Tunable timeout value for Inquiry VPD page 0x83 467 * By default the value is 30 seconds. 468 */ 469 int mptsas_inq83_retry_timeout = 30; 470 471 /* 472 * This is used to allocate memory for message frame storage, not for 473 * data I/O DMA. All message frames must be stored in the first 4G of 474 * physical memory. 475 */ 476 ddi_dma_attr_t mptsas_dma_attrs = { 477 DMA_ATTR_V0, /* attribute layout version */ 478 0x0ull, /* address low - should be 0 (longlong) */ 479 0xffffffffull, /* address high - 32-bit max range */ 480 0x00ffffffull, /* count max - max DMA object size */ 481 4, /* allocation alignment requirements */ 482 0x78, /* burstsizes - binary encoded values */ 483 1, /* minxfer - gran. of DMA engine */ 484 0x00ffffffull, /* maxxfer - gran. of DMA engine */ 485 0xffffffffull, /* max segment size (DMA boundary) */ 486 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */ 487 512, /* granularity - device transfer size */ 488 0 /* flags, set to 0 */ 489 }; 490 491 /* 492 * This is used for data I/O DMA memory allocation. (full 64-bit DMA 493 * physical addresses are supported.) 494 */ 495 ddi_dma_attr_t mptsas_dma_attrs64 = { 496 DMA_ATTR_V0, /* attribute layout version */ 497 0x0ull, /* address low - should be 0 (longlong) */ 498 0xffffffffffffffffull, /* address high - 64-bit max */ 499 0x00ffffffull, /* count max - max DMA object size */ 500 4, /* allocation alignment requirements */ 501 0x78, /* burstsizes - binary encoded values */ 502 1, /* minxfer - gran. of DMA engine */ 503 0x00ffffffull, /* maxxfer - gran. of DMA engine */ 504 0xffffffffull, /* max segment size (DMA boundary) */ 505 MPTSAS_MAX_DMA_SEGS, /* scatter/gather list length */ 506 512, /* granularity - device transfer size */ 507 0 /* flags, set to 0 */ 508 }; 509 510 ddi_device_acc_attr_t mptsas_dev_attr = { 511 DDI_DEVICE_ATTR_V1, 512 DDI_STRUCTURE_LE_ACC, 513 DDI_STRICTORDER_ACC, 514 DDI_DEFAULT_ACC 515 }; 516 517 static struct cb_ops mptsas_cb_ops = { 518 scsi_hba_open, /* open */ 519 scsi_hba_close, /* close */ 520 nodev, /* strategy */ 521 nodev, /* print */ 522 nodev, /* dump */ 523 nodev, /* read */ 524 nodev, /* write */ 525 mptsas_ioctl, /* ioctl */ 526 nodev, /* devmap */ 527 nodev, /* mmap */ 528 nodev, /* segmap */ 529 nochpoll, /* chpoll */ 530 ddi_prop_op, /* cb_prop_op */ 531 NULL, /* streamtab */ 532 D_MP, /* cb_flag */ 533 CB_REV, /* rev */ 534 nodev, /* aread */ 535 nodev /* awrite */ 536 }; 537 538 static struct dev_ops mptsas_ops = { 539 DEVO_REV, /* devo_rev, */ 540 0, /* refcnt */ 541 ddi_no_info, /* info */ 542 nulldev, /* identify */ 543 nulldev, /* probe */ 544 mptsas_attach, /* attach */ 545 mptsas_detach, /* detach */ 546 #ifdef __sparc 547 mptsas_reset, 548 #else 549 nodev, /* reset */ 550 #endif /* __sparc */ 551 &mptsas_cb_ops, /* driver operations */ 552 NULL, /* bus operations */ 553 mptsas_power, /* power management */ 554 #ifdef __sparc 555 ddi_quiesce_not_needed 556 #else 557 mptsas_quiesce /* quiesce */ 558 #endif /* __sparc */ 559 }; 560 561 562 #define MPTSAS_MOD_STRING "MPTSAS HBA Driver 00.00.00.24" 563 564 static struct modldrv modldrv = { 565 &mod_driverops, /* Type of module. This one is a driver */ 566 MPTSAS_MOD_STRING, /* Name of the module. */ 567 &mptsas_ops, /* driver ops */ 568 }; 569 570 static struct modlinkage modlinkage = { 571 MODREV_1, &modldrv, NULL 572 }; 573 #define TARGET_PROP "target" 574 #define LUN_PROP "lun" 575 #define LUN64_PROP "lun64" 576 #define SAS_PROP "sas-mpt" 577 #define MDI_GUID "wwn" 578 #define NDI_GUID "guid" 579 #define MPTSAS_DEV_GONE "mptsas_dev_gone" 580 581 /* 582 * Local static data 583 */ 584 #if defined(MPTSAS_DEBUG) 585 /* 586 * Flags to indicate which debug messages are to be printed and which go to the 587 * debug log ring buffer. Default is to not print anything, and to log 588 * everything except the watchsubr() output which normally happens every second. 589 */ 590 uint32_t mptsas_debugprt_flags = 0x0; 591 uint32_t mptsas_debuglog_flags = ~(1U << 30); 592 #endif /* defined(MPTSAS_DEBUG) */ 593 uint32_t mptsas_debug_resets = 0; 594 595 static kmutex_t mptsas_global_mutex; 596 static void *mptsas_state; /* soft state ptr */ 597 static krwlock_t mptsas_global_rwlock; 598 599 static kmutex_t mptsas_log_mutex; 600 static char mptsas_log_buf[256]; 601 _NOTE(MUTEX_PROTECTS_DATA(mptsas_log_mutex, mptsas_log_buf)) 602 603 static mptsas_t *mptsas_head, *mptsas_tail; 604 static clock_t mptsas_scsi_watchdog_tick; 605 static clock_t mptsas_tick; 606 static timeout_id_t mptsas_reset_watch; 607 static timeout_id_t mptsas_timeout_id; 608 static int mptsas_timeouts_enabled = 0; 609 610 /* 611 * Default length for extended auto request sense buffers. 612 * All sense buffers need to be under the same alloc because there 613 * is only one common top 32bits (of 64bits) address register. 614 * Most requests only require 32 bytes, but some request >256. 615 * We use rmalloc()/rmfree() on this additional memory to manage the 616 * "extended" requests. 617 */ 618 int mptsas_extreq_sense_bufsize = 256*64; 619 620 /* 621 * We believe that all software resrictions of having to run with DMA 622 * attributes to limit allocation to the first 4G are removed. 623 * However, this flag remains to enable quick switchback should suspicious 624 * problems emerge. 625 * Note that scsi_alloc_consistent_buf() does still adhere to allocating 626 * 32 bit addressable memory, but we can cope if that is changed now. 627 */ 628 int mptsas_use_64bit_msgaddr = 1; 629 630 /* 631 * warlock directives 632 */ 633 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", scsi_pkt \ 634 mptsas_cmd NcrTableIndirect buf scsi_cdb scsi_status)) 635 _NOTE(SCHEME_PROTECTS_DATA("unique per pkt", smp_pkt)) 636 _NOTE(SCHEME_PROTECTS_DATA("stable data", scsi_device scsi_address)) 637 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", mptsas_tgt_private)) 638 _NOTE(SCHEME_PROTECTS_DATA("No Mutex Needed", scsi_hba_tran::tran_tgt_private)) 639 640 /* 641 * SM - HBA statics 642 */ 643 char *mptsas_driver_rev = MPTSAS_MOD_STRING; 644 645 #ifdef MPTSAS_DEBUG 646 void debug_enter(char *); 647 #endif 648 649 /* 650 * Notes: 651 * - scsi_hba_init(9F) initializes SCSI HBA modules 652 * - must call scsi_hba_fini(9F) if modload() fails 653 */ 654 int 655 _init(void) 656 { 657 int status; 658 /* CONSTCOND */ 659 ASSERT(NO_COMPETING_THREADS); 660 661 NDBG0(("_init")); 662 663 status = ddi_soft_state_init(&mptsas_state, MPTSAS_SIZE, 664 MPTSAS_INITIAL_SOFT_SPACE); 665 if (status != 0) { 666 return (status); 667 } 668 669 if ((status = scsi_hba_init(&modlinkage)) != 0) { 670 ddi_soft_state_fini(&mptsas_state); 671 return (status); 672 } 673 674 mutex_init(&mptsas_global_mutex, NULL, MUTEX_DRIVER, NULL); 675 rw_init(&mptsas_global_rwlock, NULL, RW_DRIVER, NULL); 676 mutex_init(&mptsas_log_mutex, NULL, MUTEX_DRIVER, NULL); 677 678 if ((status = mod_install(&modlinkage)) != 0) { 679 mutex_destroy(&mptsas_log_mutex); 680 rw_destroy(&mptsas_global_rwlock); 681 mutex_destroy(&mptsas_global_mutex); 682 ddi_soft_state_fini(&mptsas_state); 683 scsi_hba_fini(&modlinkage); 684 } 685 686 return (status); 687 } 688 689 /* 690 * Notes: 691 * - scsi_hba_fini(9F) uninitializes SCSI HBA modules 692 */ 693 int 694 _fini(void) 695 { 696 int status; 697 /* CONSTCOND */ 698 ASSERT(NO_COMPETING_THREADS); 699 700 NDBG0(("_fini")); 701 702 if ((status = mod_remove(&modlinkage)) == 0) { 703 ddi_soft_state_fini(&mptsas_state); 704 scsi_hba_fini(&modlinkage); 705 mutex_destroy(&mptsas_global_mutex); 706 rw_destroy(&mptsas_global_rwlock); 707 mutex_destroy(&mptsas_log_mutex); 708 } 709 return (status); 710 } 711 712 /* 713 * The loadable-module _info(9E) entry point 714 */ 715 int 716 _info(struct modinfo *modinfop) 717 { 718 /* CONSTCOND */ 719 ASSERT(NO_COMPETING_THREADS); 720 NDBG0(("mptsas _info")); 721 722 return (mod_info(&modlinkage, modinfop)); 723 } 724 725 static int 726 mptsas_target_eval_devhdl(const void *op, void *arg) 727 { 728 uint16_t dh = *(uint16_t *)arg; 729 const mptsas_target_t *tp = op; 730 731 return ((int)tp->m_devhdl - (int)dh); 732 } 733 734 static int 735 mptsas_target_eval_slot(const void *op, void *arg) 736 { 737 mptsas_led_control_t *lcp = arg; 738 const mptsas_target_t *tp = op; 739 740 if (tp->m_enclosure != lcp->Enclosure) 741 return ((int)tp->m_enclosure - (int)lcp->Enclosure); 742 743 return ((int)tp->m_slot_num - (int)lcp->Slot); 744 } 745 746 static int 747 mptsas_target_eval_nowwn(const void *op, void *arg) 748 { 749 uint8_t phy = *(uint8_t *)arg; 750 const mptsas_target_t *tp = op; 751 752 if (tp->m_addr.mta_wwn != 0) 753 return (-1); 754 755 return ((int)tp->m_phynum - (int)phy); 756 } 757 758 static int 759 mptsas_smp_eval_devhdl(const void *op, void *arg) 760 { 761 uint16_t dh = *(uint16_t *)arg; 762 const mptsas_smp_t *sp = op; 763 764 return ((int)sp->m_devhdl - (int)dh); 765 } 766 767 static uint64_t 768 mptsas_target_addr_hash(const void *tp) 769 { 770 const mptsas_target_addr_t *tap = tp; 771 772 return ((tap->mta_wwn & 0xffffffffffffULL) | 773 ((uint64_t)tap->mta_phymask << 48)); 774 } 775 776 static int 777 mptsas_target_addr_cmp(const void *a, const void *b) 778 { 779 const mptsas_target_addr_t *aap = a; 780 const mptsas_target_addr_t *bap = b; 781 782 if (aap->mta_wwn < bap->mta_wwn) 783 return (-1); 784 if (aap->mta_wwn > bap->mta_wwn) 785 return (1); 786 return ((int)bap->mta_phymask - (int)aap->mta_phymask); 787 } 788 789 static uint64_t 790 mptsas_tmp_target_hash(const void *tp) 791 { 792 return ((uint64_t)(uintptr_t)tp); 793 } 794 795 static int 796 mptsas_tmp_target_cmp(const void *a, const void *b) 797 { 798 if (a > b) 799 return (1); 800 if (b < a) 801 return (-1); 802 803 return (0); 804 } 805 806 static void 807 mptsas_target_free(void *op) 808 { 809 kmem_free(op, sizeof (mptsas_target_t)); 810 } 811 812 static void 813 mptsas_smp_free(void *op) 814 { 815 kmem_free(op, sizeof (mptsas_smp_t)); 816 } 817 818 static void 819 mptsas_destroy_hashes(mptsas_t *mpt) 820 { 821 mptsas_target_t *tp; 822 mptsas_smp_t *sp; 823 824 for (tp = refhash_first(mpt->m_targets); tp != NULL; 825 tp = refhash_next(mpt->m_targets, tp)) { 826 refhash_remove(mpt->m_targets, tp); 827 } 828 for (sp = refhash_first(mpt->m_smp_targets); sp != NULL; 829 sp = refhash_next(mpt->m_smp_targets, sp)) { 830 refhash_remove(mpt->m_smp_targets, sp); 831 } 832 refhash_destroy(mpt->m_tmp_targets); 833 refhash_destroy(mpt->m_targets); 834 refhash_destroy(mpt->m_smp_targets); 835 mpt->m_targets = NULL; 836 mpt->m_smp_targets = NULL; 837 } 838 839 static int 840 mptsas_iport_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 841 { 842 dev_info_t *pdip; 843 mptsas_t *mpt; 844 scsi_hba_tran_t *hba_tran; 845 char *iport = NULL; 846 char phymask[MPTSAS_MAX_PHYS]; 847 mptsas_phymask_t phy_mask = 0; 848 int dynamic_port = 0; 849 uint32_t page_address; 850 char initiator_wwnstr[MPTSAS_WWN_STRLEN]; 851 int rval = DDI_FAILURE; 852 int i = 0; 853 uint8_t numphys = 0; 854 uint8_t phy_id; 855 uint8_t phy_port = 0; 856 uint16_t attached_devhdl = 0; 857 uint32_t dev_info; 858 uint64_t attached_sas_wwn; 859 uint16_t dev_hdl; 860 uint16_t pdev_hdl; 861 uint16_t bay_num, enclosure, io_flags; 862 char attached_wwnstr[MPTSAS_WWN_STRLEN]; 863 864 /* CONSTCOND */ 865 ASSERT(NO_COMPETING_THREADS); 866 867 switch (cmd) { 868 case DDI_ATTACH: 869 break; 870 871 case DDI_RESUME: 872 /* 873 * If this a scsi-iport node, nothing to do here. 874 */ 875 return (DDI_SUCCESS); 876 877 default: 878 return (DDI_FAILURE); 879 } 880 881 pdip = ddi_get_parent(dip); 882 883 if ((hba_tran = ndi_flavorv_get(pdip, SCSA_FLAVOR_SCSI_DEVICE)) == 884 NULL) { 885 cmn_err(CE_WARN, "Failed attach iport because fail to " 886 "get tran vector for the HBA node"); 887 return (DDI_FAILURE); 888 } 889 890 mpt = TRAN2MPT(hba_tran); 891 ASSERT(mpt != NULL); 892 if (mpt == NULL) 893 return (DDI_FAILURE); 894 895 if ((hba_tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) == 896 NULL) { 897 mptsas_log(mpt, CE_WARN, "Failed attach iport because fail to " 898 "get tran vector for the iport node"); 899 return (DDI_FAILURE); 900 } 901 902 /* 903 * Overwrite parent's tran_hba_private to iport's tran vector 904 */ 905 hba_tran->tran_hba_private = mpt; 906 907 ddi_report_dev(dip); 908 909 /* 910 * Get SAS address for initiator port according dev_handle 911 */ 912 iport = ddi_get_name_addr(dip); 913 if (iport && strncmp(iport, "v0", 2) == 0) { 914 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 915 MPTSAS_VIRTUAL_PORT, 1) != 916 DDI_PROP_SUCCESS) { 917 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, 918 MPTSAS_VIRTUAL_PORT); 919 mptsas_log(mpt, CE_WARN, "mptsas virtual port " 920 "prop update failed"); 921 return (DDI_FAILURE); 922 } 923 return (DDI_SUCCESS); 924 } 925 926 mutex_enter(&mpt->m_mutex); 927 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 928 bzero(phymask, sizeof (phymask)); 929 (void) sprintf(phymask, 930 "%x", mpt->m_phy_info[i].phy_mask); 931 if (strcmp(phymask, iport) == 0) { 932 break; 933 } 934 } 935 936 if (i == MPTSAS_MAX_PHYS) { 937 mptsas_log(mpt, CE_WARN, "Failed attach port %s because port" 938 "seems not exist", iport); 939 mutex_exit(&mpt->m_mutex); 940 return (DDI_FAILURE); 941 } 942 943 phy_mask = mpt->m_phy_info[i].phy_mask; 944 945 if (mpt->m_phy_info[i].port_flags & AUTO_PORT_CONFIGURATION) 946 dynamic_port = 1; 947 else 948 dynamic_port = 0; 949 950 /* 951 * Update PHY info for smhba 952 */ 953 if (mptsas_smhba_phy_init(mpt)) { 954 mutex_exit(&mpt->m_mutex); 955 mptsas_log(mpt, CE_WARN, "mptsas phy update " 956 "failed"); 957 return (DDI_FAILURE); 958 } 959 960 mutex_exit(&mpt->m_mutex); 961 962 numphys = 0; 963 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 964 if ((phy_mask >> i) & 0x01) { 965 numphys++; 966 } 967 } 968 969 bzero(initiator_wwnstr, sizeof (initiator_wwnstr)); 970 (void) sprintf(initiator_wwnstr, "w%016"PRIx64, 971 mpt->un.m_base_wwid); 972 973 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip, 974 SCSI_ADDR_PROP_INITIATOR_PORT, initiator_wwnstr) != 975 DDI_PROP_SUCCESS) { 976 (void) ddi_prop_remove(DDI_DEV_T_NONE, 977 dip, SCSI_ADDR_PROP_INITIATOR_PORT); 978 mptsas_log(mpt, CE_WARN, "mptsas Initiator port " 979 "prop update failed"); 980 return (DDI_FAILURE); 981 } 982 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 983 MPTSAS_NUM_PHYS, numphys) != 984 DDI_PROP_SUCCESS) { 985 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, MPTSAS_NUM_PHYS); 986 return (DDI_FAILURE); 987 } 988 989 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 990 "phymask", phy_mask) != 991 DDI_PROP_SUCCESS) { 992 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "phymask"); 993 mptsas_log(mpt, CE_WARN, "mptsas phy mask " 994 "prop update failed"); 995 return (DDI_FAILURE); 996 } 997 998 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 999 "dynamic-port", dynamic_port) != 1000 DDI_PROP_SUCCESS) { 1001 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "dynamic-port"); 1002 mptsas_log(mpt, CE_WARN, "mptsas dynamic port " 1003 "prop update failed"); 1004 return (DDI_FAILURE); 1005 } 1006 if (ddi_prop_update_int(DDI_DEV_T_NONE, dip, 1007 MPTSAS_VIRTUAL_PORT, 0) != 1008 DDI_PROP_SUCCESS) { 1009 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, 1010 MPTSAS_VIRTUAL_PORT); 1011 mptsas_log(mpt, CE_WARN, "mptsas virtual port " 1012 "prop update failed"); 1013 return (DDI_FAILURE); 1014 } 1015 mptsas_smhba_set_all_phy_props(mpt, dip, numphys, phy_mask, 1016 &attached_devhdl); 1017 1018 mutex_enter(&mpt->m_mutex); 1019 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 1020 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)attached_devhdl; 1021 rval = mptsas_get_sas_device_page0(mpt, page_address, &dev_hdl, 1022 &attached_sas_wwn, &dev_info, &phy_port, &phy_id, 1023 &pdev_hdl, &bay_num, &enclosure, &io_flags); 1024 if (rval != DDI_SUCCESS) { 1025 mptsas_log(mpt, CE_WARN, 1026 "Failed to get device page0 for handle:%d", 1027 attached_devhdl); 1028 mutex_exit(&mpt->m_mutex); 1029 return (DDI_FAILURE); 1030 } 1031 1032 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 1033 bzero(phymask, sizeof (phymask)); 1034 (void) sprintf(phymask, "%x", mpt->m_phy_info[i].phy_mask); 1035 if (strcmp(phymask, iport) == 0) { 1036 (void) sprintf(&mpt->m_phy_info[i].smhba_info.path[0], 1037 "%x", 1038 mpt->m_phy_info[i].phy_mask); 1039 } 1040 } 1041 mutex_exit(&mpt->m_mutex); 1042 1043 bzero(attached_wwnstr, sizeof (attached_wwnstr)); 1044 (void) sprintf(attached_wwnstr, "w%016"PRIx64, 1045 attached_sas_wwn); 1046 if (ddi_prop_update_string(DDI_DEV_T_NONE, dip, 1047 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) != 1048 DDI_PROP_SUCCESS) { 1049 (void) ddi_prop_remove(DDI_DEV_T_NONE, 1050 dip, SCSI_ADDR_PROP_ATTACHED_PORT); 1051 return (DDI_FAILURE); 1052 } 1053 1054 /* Create kstats for each phy on this iport */ 1055 1056 mptsas_create_phy_stats(mpt, iport, dip); 1057 1058 /* 1059 * register sas hba iport with mdi (MPxIO/vhci) 1060 */ 1061 if (mdi_phci_register(MDI_HCI_CLASS_SCSI, 1062 dip, 0) == MDI_SUCCESS) { 1063 mpt->m_mpxio_enable = TRUE; 1064 } 1065 return (DDI_SUCCESS); 1066 } 1067 1068 /* 1069 * Notes: 1070 * Set up all device state and allocate data structures, 1071 * mutexes, condition variables, etc. for device operation. 1072 * Add interrupts needed. 1073 * Return DDI_SUCCESS if device is ready, else return DDI_FAILURE. 1074 */ 1075 static int 1076 mptsas_attach(dev_info_t *dip, ddi_attach_cmd_t cmd) 1077 { 1078 mptsas_t *mpt = NULL; 1079 int instance, i, j; 1080 int doneq_thread_num; 1081 char intr_added = 0; 1082 char map_setup = 0; 1083 char config_setup = 0; 1084 char hba_attach_setup = 0; 1085 char smp_attach_setup = 0; 1086 char enc_attach_setup = 0; 1087 char mutex_init_done = 0; 1088 char event_taskq_create = 0; 1089 char dr_taskq_create = 0; 1090 char doneq_thread_create = 0; 1091 char added_watchdog = 0; 1092 scsi_hba_tran_t *hba_tran; 1093 uint_t mem_bar = MEM_SPACE; 1094 int rval = DDI_FAILURE; 1095 1096 /* CONSTCOND */ 1097 ASSERT(NO_COMPETING_THREADS); 1098 1099 if (scsi_hba_iport_unit_address(dip)) { 1100 return (mptsas_iport_attach(dip, cmd)); 1101 } 1102 1103 switch (cmd) { 1104 case DDI_ATTACH: 1105 break; 1106 1107 case DDI_RESUME: 1108 if ((hba_tran = ddi_get_driver_private(dip)) == NULL) 1109 return (DDI_FAILURE); 1110 1111 mpt = TRAN2MPT(hba_tran); 1112 1113 if (!mpt) { 1114 return (DDI_FAILURE); 1115 } 1116 1117 /* 1118 * Reset hardware and softc to "no outstanding commands" 1119 * Note that a check condition can result on first command 1120 * to a target. 1121 */ 1122 mutex_enter(&mpt->m_mutex); 1123 1124 /* 1125 * raise power. 1126 */ 1127 if (mpt->m_options & MPTSAS_OPT_PM) { 1128 mutex_exit(&mpt->m_mutex); 1129 (void) pm_busy_component(dip, 0); 1130 rval = pm_power_has_changed(dip, 0, PM_LEVEL_D0); 1131 if (rval == DDI_SUCCESS) { 1132 mutex_enter(&mpt->m_mutex); 1133 } else { 1134 /* 1135 * The pm_raise_power() call above failed, 1136 * and that can only occur if we were unable 1137 * to reset the hardware. This is probably 1138 * due to unhealty hardware, and because 1139 * important filesystems(such as the root 1140 * filesystem) could be on the attached disks, 1141 * it would not be a good idea to continue, 1142 * as we won't be entirely certain we are 1143 * writing correct data. So we panic() here 1144 * to not only prevent possible data corruption, 1145 * but to give developers or end users a hope 1146 * of identifying and correcting any problems. 1147 */ 1148 fm_panic("mptsas could not reset hardware " 1149 "during resume"); 1150 } 1151 } 1152 1153 mpt->m_suspended = 0; 1154 1155 /* 1156 * Reinitialize ioc 1157 */ 1158 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET; 1159 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) { 1160 mutex_exit(&mpt->m_mutex); 1161 if (mpt->m_options & MPTSAS_OPT_PM) { 1162 (void) pm_idle_component(dip, 0); 1163 } 1164 fm_panic("mptsas init chip fail during resume"); 1165 } 1166 /* 1167 * mptsas_update_driver_data needs interrupts so enable them 1168 * first. 1169 */ 1170 MPTSAS_ENABLE_INTR(mpt); 1171 mptsas_update_driver_data(mpt); 1172 1173 /* start requests, if possible */ 1174 mptsas_restart_hba(mpt); 1175 1176 mutex_exit(&mpt->m_mutex); 1177 1178 /* 1179 * Restart watch thread 1180 */ 1181 mutex_enter(&mptsas_global_mutex); 1182 if (mptsas_timeout_id == 0) { 1183 mptsas_timeout_id = timeout(mptsas_watch, NULL, 1184 mptsas_tick); 1185 mptsas_timeouts_enabled = 1; 1186 } 1187 mutex_exit(&mptsas_global_mutex); 1188 1189 /* report idle status to pm framework */ 1190 if (mpt->m_options & MPTSAS_OPT_PM) { 1191 (void) pm_idle_component(dip, 0); 1192 } 1193 1194 return (DDI_SUCCESS); 1195 1196 default: 1197 return (DDI_FAILURE); 1198 1199 } 1200 1201 instance = ddi_get_instance(dip); 1202 1203 /* 1204 * Allocate softc information. 1205 */ 1206 if (ddi_soft_state_zalloc(mptsas_state, instance) != DDI_SUCCESS) { 1207 mptsas_log(NULL, CE_WARN, 1208 "mptsas%d: cannot allocate soft state", instance); 1209 goto fail; 1210 } 1211 1212 mpt = ddi_get_soft_state(mptsas_state, instance); 1213 1214 if (mpt == NULL) { 1215 mptsas_log(NULL, CE_WARN, 1216 "mptsas%d: cannot get soft state", instance); 1217 goto fail; 1218 } 1219 1220 /* Indicate that we are 'sizeof (scsi_*(9S))' clean. */ 1221 scsi_size_clean(dip); 1222 1223 mpt->m_dip = dip; 1224 mpt->m_instance = instance; 1225 1226 /* Make a per-instance copy of the structures */ 1227 mpt->m_io_dma_attr = mptsas_dma_attrs64; 1228 if (mptsas_use_64bit_msgaddr) { 1229 mpt->m_msg_dma_attr = mptsas_dma_attrs64; 1230 } else { 1231 mpt->m_msg_dma_attr = mptsas_dma_attrs; 1232 } 1233 mpt->m_reg_acc_attr = mptsas_dev_attr; 1234 mpt->m_dev_acc_attr = mptsas_dev_attr; 1235 1236 /* 1237 * Size of individual request sense buffer 1238 */ 1239 mpt->m_req_sense_size = EXTCMDS_STATUS_SIZE; 1240 1241 /* 1242 * Initialize FMA 1243 */ 1244 mpt->m_fm_capabilities = ddi_getprop(DDI_DEV_T_ANY, mpt->m_dip, 1245 DDI_PROP_CANSLEEP | DDI_PROP_DONTPASS, "fm-capable", 1246 DDI_FM_EREPORT_CAPABLE | DDI_FM_ACCCHK_CAPABLE | 1247 DDI_FM_DMACHK_CAPABLE | DDI_FM_ERRCB_CAPABLE); 1248 1249 mptsas_fm_init(mpt); 1250 1251 if (mptsas_alloc_handshake_msg(mpt, 1252 sizeof (Mpi2SCSITaskManagementRequest_t)) == DDI_FAILURE) { 1253 mptsas_log(mpt, CE_WARN, "cannot initialize handshake msg."); 1254 goto fail; 1255 } 1256 1257 /* 1258 * Setup configuration space 1259 */ 1260 if (mptsas_config_space_init(mpt) == FALSE) { 1261 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init failed"); 1262 goto fail; 1263 } 1264 config_setup++; 1265 1266 if (ddi_regs_map_setup(dip, mem_bar, (caddr_t *)&mpt->m_reg, 1267 0, 0, &mpt->m_reg_acc_attr, &mpt->m_datap) != DDI_SUCCESS) { 1268 mptsas_log(mpt, CE_WARN, "map setup failed"); 1269 goto fail; 1270 } 1271 map_setup++; 1272 1273 /* 1274 * A taskq is created for dealing with the event handler 1275 */ 1276 if ((mpt->m_event_taskq = ddi_taskq_create(dip, "mptsas_event_taskq", 1277 1, TASKQ_DEFAULTPRI, 0)) == NULL) { 1278 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create failed"); 1279 goto fail; 1280 } 1281 event_taskq_create++; 1282 1283 /* 1284 * A taskq is created for dealing with dr events 1285 */ 1286 if ((mpt->m_dr_taskq = ddi_taskq_create(dip, 1287 "mptsas_dr_taskq", 1288 1, TASKQ_DEFAULTPRI, 0)) == NULL) { 1289 mptsas_log(mpt, CE_NOTE, "ddi_taskq_create for discovery " 1290 "failed"); 1291 goto fail; 1292 } 1293 dr_taskq_create++; 1294 1295 mpt->m_doneq_thread_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1296 0, "mptsas_doneq_thread_threshold_prop", 10); 1297 mpt->m_doneq_length_threshold = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1298 0, "mptsas_doneq_length_threshold_prop", 8); 1299 mpt->m_doneq_thread_n = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 1300 0, "mptsas_doneq_thread_n_prop", 8); 1301 1302 if (mpt->m_doneq_thread_n) { 1303 cv_init(&mpt->m_doneq_thread_cv, NULL, CV_DRIVER, NULL); 1304 mutex_init(&mpt->m_doneq_mutex, NULL, MUTEX_DRIVER, NULL); 1305 1306 mutex_enter(&mpt->m_doneq_mutex); 1307 mpt->m_doneq_thread_id = 1308 kmem_zalloc(sizeof (mptsas_doneq_thread_list_t) 1309 * mpt->m_doneq_thread_n, KM_SLEEP); 1310 1311 for (j = 0; j < mpt->m_doneq_thread_n; j++) { 1312 cv_init(&mpt->m_doneq_thread_id[j].cv, NULL, 1313 CV_DRIVER, NULL); 1314 mutex_init(&mpt->m_doneq_thread_id[j].mutex, NULL, 1315 MUTEX_DRIVER, NULL); 1316 mutex_enter(&mpt->m_doneq_thread_id[j].mutex); 1317 mpt->m_doneq_thread_id[j].flag |= 1318 MPTSAS_DONEQ_THREAD_ACTIVE; 1319 mpt->m_doneq_thread_id[j].arg.mpt = mpt; 1320 mpt->m_doneq_thread_id[j].arg.t = j; 1321 mpt->m_doneq_thread_id[j].threadp = 1322 thread_create(NULL, 0, mptsas_doneq_thread, 1323 &mpt->m_doneq_thread_id[j].arg, 1324 0, &p0, TS_RUN, minclsyspri); 1325 mpt->m_doneq_thread_id[j].donetail = 1326 &mpt->m_doneq_thread_id[j].doneq; 1327 mutex_exit(&mpt->m_doneq_thread_id[j].mutex); 1328 } 1329 mutex_exit(&mpt->m_doneq_mutex); 1330 doneq_thread_create++; 1331 } 1332 1333 /* 1334 * Disable hardware interrupt since we're not ready to 1335 * handle it yet. 1336 */ 1337 MPTSAS_DISABLE_INTR(mpt); 1338 if (mptsas_register_intrs(mpt) == FALSE) 1339 goto fail; 1340 intr_added++; 1341 1342 /* Initialize mutex used in interrupt handler */ 1343 mutex_init(&mpt->m_mutex, NULL, MUTEX_DRIVER, 1344 DDI_INTR_PRI(mpt->m_intr_pri)); 1345 mutex_init(&mpt->m_passthru_mutex, NULL, MUTEX_DRIVER, NULL); 1346 mutex_init(&mpt->m_tx_waitq_mutex, NULL, MUTEX_DRIVER, 1347 DDI_INTR_PRI(mpt->m_intr_pri)); 1348 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 1349 mutex_init(&mpt->m_phy_info[i].smhba_info.phy_mutex, 1350 NULL, MUTEX_DRIVER, 1351 DDI_INTR_PRI(mpt->m_intr_pri)); 1352 } 1353 1354 cv_init(&mpt->m_cv, NULL, CV_DRIVER, NULL); 1355 cv_init(&mpt->m_passthru_cv, NULL, CV_DRIVER, NULL); 1356 cv_init(&mpt->m_fw_cv, NULL, CV_DRIVER, NULL); 1357 cv_init(&mpt->m_config_cv, NULL, CV_DRIVER, NULL); 1358 cv_init(&mpt->m_fw_diag_cv, NULL, CV_DRIVER, NULL); 1359 cv_init(&mpt->m_extreq_sense_refcount_cv, NULL, CV_DRIVER, NULL); 1360 mutex_init_done++; 1361 1362 mutex_enter(&mpt->m_mutex); 1363 /* 1364 * Initialize power management component 1365 */ 1366 if (mpt->m_options & MPTSAS_OPT_PM) { 1367 if (mptsas_init_pm(mpt)) { 1368 mutex_exit(&mpt->m_mutex); 1369 mptsas_log(mpt, CE_WARN, "mptsas pm initialization " 1370 "failed"); 1371 goto fail; 1372 } 1373 } 1374 1375 /* 1376 * Initialize chip using Message Unit Reset, if allowed 1377 */ 1378 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET; 1379 if (mptsas_init_chip(mpt, TRUE) == DDI_FAILURE) { 1380 mutex_exit(&mpt->m_mutex); 1381 mptsas_log(mpt, CE_WARN, "mptsas chip initialization failed"); 1382 goto fail; 1383 } 1384 1385 mpt->m_targets = refhash_create(MPTSAS_TARGET_BUCKET_COUNT, 1386 mptsas_target_addr_hash, mptsas_target_addr_cmp, 1387 mptsas_target_free, sizeof (mptsas_target_t), 1388 offsetof(mptsas_target_t, m_link), 1389 offsetof(mptsas_target_t, m_addr), KM_SLEEP); 1390 1391 /* 1392 * The refhash for temporary targets uses the address of the target 1393 * struct itself as tag, so the tag offset is 0. See the implementation 1394 * of mptsas_tmp_target_hash() and mptsas_tmp_target_cmp(). 1395 */ 1396 mpt->m_tmp_targets = refhash_create(MPTSAS_TMP_TARGET_BUCKET_COUNT, 1397 mptsas_tmp_target_hash, mptsas_tmp_target_cmp, 1398 mptsas_target_free, sizeof (mptsas_target_t), 1399 offsetof(mptsas_target_t, m_link), 0, KM_SLEEP); 1400 1401 /* 1402 * Fill in the phy_info structure and get the base WWID 1403 */ 1404 if (mptsas_get_manufacture_page5(mpt) == DDI_FAILURE) { 1405 mptsas_log(mpt, CE_WARN, 1406 "mptsas_get_manufacture_page5 failed!"); 1407 goto fail; 1408 } 1409 1410 if (mptsas_get_sas_io_unit_page_hndshk(mpt)) { 1411 mptsas_log(mpt, CE_WARN, 1412 "mptsas_get_sas_io_unit_page_hndshk failed!"); 1413 goto fail; 1414 } 1415 1416 if (mptsas_get_manufacture_page0(mpt) == DDI_FAILURE) { 1417 mptsas_log(mpt, CE_WARN, 1418 "mptsas_get_manufacture_page0 failed!"); 1419 goto fail; 1420 } 1421 1422 mutex_exit(&mpt->m_mutex); 1423 1424 /* 1425 * Register the iport for multiple port HBA 1426 */ 1427 mptsas_iport_register(mpt); 1428 1429 /* 1430 * initialize SCSI HBA transport structure 1431 */ 1432 if (mptsas_hba_setup(mpt) == FALSE) 1433 goto fail; 1434 hba_attach_setup++; 1435 1436 if (mptsas_smp_setup(mpt) == FALSE) 1437 goto fail; 1438 smp_attach_setup++; 1439 1440 if (mptsas_enc_setup(mpt) == FALSE) 1441 goto fail; 1442 enc_attach_setup++; 1443 1444 if (mptsas_cache_create(mpt) == FALSE) 1445 goto fail; 1446 1447 mpt->m_scsi_reset_delay = ddi_prop_get_int(DDI_DEV_T_ANY, 1448 dip, 0, "scsi-reset-delay", SCSI_DEFAULT_RESET_DELAY); 1449 if (mpt->m_scsi_reset_delay == 0) { 1450 mptsas_log(mpt, CE_NOTE, 1451 "scsi_reset_delay of 0 is not recommended," 1452 " resetting to SCSI_DEFAULT_RESET_DELAY\n"); 1453 mpt->m_scsi_reset_delay = SCSI_DEFAULT_RESET_DELAY; 1454 } 1455 1456 /* 1457 * Initialize the wait and done FIFO queue 1458 */ 1459 mpt->m_donetail = &mpt->m_doneq; 1460 mpt->m_waitqtail = &mpt->m_waitq; 1461 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; 1462 mpt->m_tx_draining = 0; 1463 1464 /* 1465 * ioc cmd queue initialize 1466 */ 1467 mpt->m_ioc_event_cmdtail = &mpt->m_ioc_event_cmdq; 1468 mpt->m_dev_handle = 0xFFFF; 1469 1470 MPTSAS_ENABLE_INTR(mpt); 1471 1472 /* 1473 * enable event notification 1474 */ 1475 mutex_enter(&mpt->m_mutex); 1476 if (mptsas_ioc_enable_event_notification(mpt)) { 1477 mutex_exit(&mpt->m_mutex); 1478 goto fail; 1479 } 1480 mutex_exit(&mpt->m_mutex); 1481 1482 /* 1483 * used for mptsas_watch 1484 */ 1485 mptsas_list_add(mpt); 1486 1487 mutex_enter(&mptsas_global_mutex); 1488 if (mptsas_timeouts_enabled == 0) { 1489 mptsas_scsi_watchdog_tick = ddi_prop_get_int(DDI_DEV_T_ANY, 1490 dip, 0, "scsi-watchdog-tick", DEFAULT_WD_TICK); 1491 1492 mptsas_tick = mptsas_scsi_watchdog_tick * 1493 drv_usectohz((clock_t)1000000); 1494 1495 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick); 1496 mptsas_timeouts_enabled = 1; 1497 } 1498 mutex_exit(&mptsas_global_mutex); 1499 added_watchdog++; 1500 1501 /* 1502 * Initialize PHY info for smhba. 1503 * This requires watchdog to be enabled otherwise if interrupts 1504 * don't work the system will hang. 1505 */ 1506 if (mptsas_smhba_setup(mpt)) { 1507 mptsas_log(mpt, CE_WARN, "mptsas phy initialization " 1508 "failed"); 1509 goto fail; 1510 } 1511 1512 /* Check all dma handles allocated in attach */ 1513 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) 1514 != DDI_SUCCESS) || 1515 (mptsas_check_dma_handle(mpt->m_dma_req_sense_hdl) 1516 != DDI_SUCCESS) || 1517 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) 1518 != DDI_SUCCESS) || 1519 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) 1520 != DDI_SUCCESS) || 1521 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) 1522 != DDI_SUCCESS) || 1523 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) 1524 != DDI_SUCCESS)) { 1525 goto fail; 1526 } 1527 1528 /* Check all acc handles allocated in attach */ 1529 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) || 1530 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) 1531 != DDI_SUCCESS) || 1532 (mptsas_check_acc_handle(mpt->m_acc_req_sense_hdl) 1533 != DDI_SUCCESS) || 1534 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) 1535 != DDI_SUCCESS) || 1536 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) 1537 != DDI_SUCCESS) || 1538 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) 1539 != DDI_SUCCESS) || 1540 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) 1541 != DDI_SUCCESS) || 1542 (mptsas_check_acc_handle(mpt->m_config_handle) 1543 != DDI_SUCCESS)) { 1544 goto fail; 1545 } 1546 1547 /* 1548 * After this point, we are not going to fail the attach. 1549 */ 1550 1551 /* Print message of HBA present */ 1552 ddi_report_dev(dip); 1553 1554 /* report idle status to pm framework */ 1555 if (mpt->m_options & MPTSAS_OPT_PM) { 1556 (void) pm_idle_component(dip, 0); 1557 } 1558 1559 return (DDI_SUCCESS); 1560 1561 fail: 1562 mptsas_log(mpt, CE_WARN, "attach failed"); 1563 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE); 1564 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST); 1565 if (mpt) { 1566 /* deallocate in reverse order */ 1567 if (added_watchdog) { 1568 mptsas_list_del(mpt); 1569 mutex_enter(&mptsas_global_mutex); 1570 1571 if (mptsas_timeout_id && (mptsas_head == NULL)) { 1572 timeout_id_t tid = mptsas_timeout_id; 1573 mptsas_timeouts_enabled = 0; 1574 mptsas_timeout_id = 0; 1575 mutex_exit(&mptsas_global_mutex); 1576 (void) untimeout(tid); 1577 mutex_enter(&mptsas_global_mutex); 1578 } 1579 mutex_exit(&mptsas_global_mutex); 1580 } 1581 1582 mptsas_cache_destroy(mpt); 1583 1584 if (smp_attach_setup) { 1585 mptsas_smp_teardown(mpt); 1586 } 1587 if (enc_attach_setup) { 1588 mptsas_enc_teardown(mpt); 1589 } 1590 if (hba_attach_setup) { 1591 mptsas_hba_teardown(mpt); 1592 } 1593 1594 if (mpt->m_tmp_targets) 1595 refhash_destroy(mpt->m_tmp_targets); 1596 if (mpt->m_targets) 1597 refhash_destroy(mpt->m_targets); 1598 if (mpt->m_smp_targets) 1599 refhash_destroy(mpt->m_smp_targets); 1600 1601 if (mpt->m_active) { 1602 mptsas_free_active_slots(mpt); 1603 } 1604 if (intr_added) { 1605 mptsas_unregister_intrs(mpt); 1606 } 1607 1608 if (doneq_thread_create) { 1609 mutex_enter(&mpt->m_doneq_mutex); 1610 doneq_thread_num = mpt->m_doneq_thread_n; 1611 for (j = 0; j < mpt->m_doneq_thread_n; j++) { 1612 mutex_enter(&mpt->m_doneq_thread_id[j].mutex); 1613 mpt->m_doneq_thread_id[j].flag &= 1614 (~MPTSAS_DONEQ_THREAD_ACTIVE); 1615 cv_signal(&mpt->m_doneq_thread_id[j].cv); 1616 mutex_exit(&mpt->m_doneq_thread_id[j].mutex); 1617 } 1618 while (mpt->m_doneq_thread_n) { 1619 cv_wait(&mpt->m_doneq_thread_cv, 1620 &mpt->m_doneq_mutex); 1621 } 1622 for (j = 0; j < doneq_thread_num; j++) { 1623 cv_destroy(&mpt->m_doneq_thread_id[j].cv); 1624 mutex_destroy(&mpt->m_doneq_thread_id[j].mutex); 1625 } 1626 kmem_free(mpt->m_doneq_thread_id, 1627 sizeof (mptsas_doneq_thread_list_t) 1628 * doneq_thread_num); 1629 mutex_exit(&mpt->m_doneq_mutex); 1630 cv_destroy(&mpt->m_doneq_thread_cv); 1631 mutex_destroy(&mpt->m_doneq_mutex); 1632 } 1633 if (event_taskq_create) { 1634 ddi_taskq_destroy(mpt->m_event_taskq); 1635 } 1636 if (dr_taskq_create) { 1637 ddi_taskq_destroy(mpt->m_dr_taskq); 1638 } 1639 if (mutex_init_done) { 1640 mutex_destroy(&mpt->m_tx_waitq_mutex); 1641 mutex_destroy(&mpt->m_passthru_mutex); 1642 mutex_destroy(&mpt->m_mutex); 1643 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 1644 mutex_destroy( 1645 &mpt->m_phy_info[i].smhba_info.phy_mutex); 1646 } 1647 cv_destroy(&mpt->m_cv); 1648 cv_destroy(&mpt->m_passthru_cv); 1649 cv_destroy(&mpt->m_fw_cv); 1650 cv_destroy(&mpt->m_config_cv); 1651 cv_destroy(&mpt->m_fw_diag_cv); 1652 cv_destroy(&mpt->m_extreq_sense_refcount_cv); 1653 } 1654 1655 if (map_setup) { 1656 mptsas_cfg_fini(mpt); 1657 } 1658 if (config_setup) { 1659 mptsas_config_space_fini(mpt); 1660 } 1661 mptsas_free_handshake_msg(mpt); 1662 mptsas_hba_fini(mpt); 1663 1664 mptsas_fm_fini(mpt); 1665 ddi_soft_state_free(mptsas_state, instance); 1666 ddi_prop_remove_all(dip); 1667 } 1668 return (DDI_FAILURE); 1669 } 1670 1671 static int 1672 mptsas_suspend(dev_info_t *devi) 1673 { 1674 mptsas_t *mpt, *g; 1675 scsi_hba_tran_t *tran; 1676 1677 if (scsi_hba_iport_unit_address(devi)) { 1678 return (DDI_SUCCESS); 1679 } 1680 1681 if ((tran = ddi_get_driver_private(devi)) == NULL) 1682 return (DDI_SUCCESS); 1683 1684 mpt = TRAN2MPT(tran); 1685 if (!mpt) { 1686 return (DDI_SUCCESS); 1687 } 1688 1689 mutex_enter(&mpt->m_mutex); 1690 1691 if (mpt->m_suspended++) { 1692 mutex_exit(&mpt->m_mutex); 1693 return (DDI_SUCCESS); 1694 } 1695 1696 /* 1697 * Cancel timeout threads for this mpt 1698 */ 1699 if (mpt->m_quiesce_timeid) { 1700 timeout_id_t tid = mpt->m_quiesce_timeid; 1701 mpt->m_quiesce_timeid = 0; 1702 mutex_exit(&mpt->m_mutex); 1703 (void) untimeout(tid); 1704 mutex_enter(&mpt->m_mutex); 1705 } 1706 1707 if (mpt->m_restart_cmd_timeid) { 1708 timeout_id_t tid = mpt->m_restart_cmd_timeid; 1709 mpt->m_restart_cmd_timeid = 0; 1710 mutex_exit(&mpt->m_mutex); 1711 (void) untimeout(tid); 1712 mutex_enter(&mpt->m_mutex); 1713 } 1714 1715 mutex_exit(&mpt->m_mutex); 1716 1717 (void) pm_idle_component(mpt->m_dip, 0); 1718 1719 /* 1720 * Cancel watch threads if all mpts suspended 1721 */ 1722 rw_enter(&mptsas_global_rwlock, RW_WRITER); 1723 for (g = mptsas_head; g != NULL; g = g->m_next) { 1724 if (!g->m_suspended) 1725 break; 1726 } 1727 rw_exit(&mptsas_global_rwlock); 1728 1729 mutex_enter(&mptsas_global_mutex); 1730 if (g == NULL) { 1731 timeout_id_t tid; 1732 1733 mptsas_timeouts_enabled = 0; 1734 if (mptsas_timeout_id) { 1735 tid = mptsas_timeout_id; 1736 mptsas_timeout_id = 0; 1737 mutex_exit(&mptsas_global_mutex); 1738 (void) untimeout(tid); 1739 mutex_enter(&mptsas_global_mutex); 1740 } 1741 if (mptsas_reset_watch) { 1742 tid = mptsas_reset_watch; 1743 mptsas_reset_watch = 0; 1744 mutex_exit(&mptsas_global_mutex); 1745 (void) untimeout(tid); 1746 mutex_enter(&mptsas_global_mutex); 1747 } 1748 } 1749 mutex_exit(&mptsas_global_mutex); 1750 1751 mutex_enter(&mpt->m_mutex); 1752 1753 /* 1754 * If this mpt is not in full power(PM_LEVEL_D0), just return. 1755 */ 1756 if ((mpt->m_options & MPTSAS_OPT_PM) && 1757 (mpt->m_power_level != PM_LEVEL_D0)) { 1758 mutex_exit(&mpt->m_mutex); 1759 return (DDI_SUCCESS); 1760 } 1761 1762 /* Disable HBA interrupts in hardware */ 1763 MPTSAS_DISABLE_INTR(mpt); 1764 /* 1765 * Send RAID action system shutdown to sync IR 1766 */ 1767 mptsas_raid_action_system_shutdown(mpt); 1768 1769 mutex_exit(&mpt->m_mutex); 1770 1771 /* drain the taskq */ 1772 ddi_taskq_wait(mpt->m_event_taskq); 1773 ddi_taskq_wait(mpt->m_dr_taskq); 1774 1775 return (DDI_SUCCESS); 1776 } 1777 1778 #ifdef __sparc 1779 /*ARGSUSED*/ 1780 static int 1781 mptsas_reset(dev_info_t *devi, ddi_reset_cmd_t cmd) 1782 { 1783 mptsas_t *mpt; 1784 scsi_hba_tran_t *tran; 1785 1786 /* 1787 * If this call is for iport, just return. 1788 */ 1789 if (scsi_hba_iport_unit_address(devi)) 1790 return (DDI_SUCCESS); 1791 1792 if ((tran = ddi_get_driver_private(devi)) == NULL) 1793 return (DDI_SUCCESS); 1794 1795 if ((mpt = TRAN2MPT(tran)) == NULL) 1796 return (DDI_SUCCESS); 1797 1798 /* 1799 * Send RAID action system shutdown to sync IR. Disable HBA 1800 * interrupts in hardware first. 1801 */ 1802 MPTSAS_DISABLE_INTR(mpt); 1803 mptsas_raid_action_system_shutdown(mpt); 1804 1805 return (DDI_SUCCESS); 1806 } 1807 #else /* __sparc */ 1808 /* 1809 * quiesce(9E) entry point. 1810 * 1811 * This function is called when the system is single-threaded at high 1812 * PIL with preemption disabled. Therefore, this function must not be 1813 * blocked. 1814 * 1815 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 1816 * DDI_FAILURE indicates an error condition and should almost never happen. 1817 */ 1818 static int 1819 mptsas_quiesce(dev_info_t *devi) 1820 { 1821 mptsas_t *mpt; 1822 scsi_hba_tran_t *tran; 1823 1824 /* 1825 * If this call is for iport, just return. 1826 */ 1827 if (scsi_hba_iport_unit_address(devi)) 1828 return (DDI_SUCCESS); 1829 1830 if ((tran = ddi_get_driver_private(devi)) == NULL) 1831 return (DDI_SUCCESS); 1832 1833 if ((mpt = TRAN2MPT(tran)) == NULL) 1834 return (DDI_SUCCESS); 1835 1836 /* Disable HBA interrupts in hardware */ 1837 MPTSAS_DISABLE_INTR(mpt); 1838 /* Send RAID action system shutdonw to sync IR */ 1839 mptsas_raid_action_system_shutdown(mpt); 1840 1841 return (DDI_SUCCESS); 1842 } 1843 #endif /* __sparc */ 1844 1845 /* 1846 * detach(9E). Remove all device allocations and system resources; 1847 * disable device interrupts. 1848 * Return DDI_SUCCESS if done; DDI_FAILURE if there's a problem. 1849 */ 1850 static int 1851 mptsas_detach(dev_info_t *devi, ddi_detach_cmd_t cmd) 1852 { 1853 /* CONSTCOND */ 1854 ASSERT(NO_COMPETING_THREADS); 1855 NDBG0(("mptsas_detach: dip=0x%p cmd=0x%p", (void *)devi, (void *)cmd)); 1856 1857 switch (cmd) { 1858 case DDI_DETACH: 1859 return (mptsas_do_detach(devi)); 1860 1861 case DDI_SUSPEND: 1862 return (mptsas_suspend(devi)); 1863 1864 default: 1865 return (DDI_FAILURE); 1866 } 1867 /* NOTREACHED */ 1868 } 1869 1870 static int 1871 mptsas_do_detach(dev_info_t *dip) 1872 { 1873 mptsas_t *mpt; 1874 scsi_hba_tran_t *tran; 1875 int circ = 0; 1876 int circ1 = 0; 1877 mdi_pathinfo_t *pip = NULL; 1878 int i; 1879 int doneq_thread_num = 0; 1880 1881 NDBG0(("mptsas_do_detach: dip=0x%p", (void *)dip)); 1882 1883 if ((tran = ndi_flavorv_get(dip, SCSA_FLAVOR_SCSI_DEVICE)) == NULL) 1884 return (DDI_FAILURE); 1885 1886 mpt = TRAN2MPT(tran); 1887 if (!mpt) { 1888 return (DDI_FAILURE); 1889 } 1890 /* 1891 * Still have pathinfo child, should not detach mpt driver 1892 */ 1893 if (scsi_hba_iport_unit_address(dip)) { 1894 if (mpt->m_mpxio_enable) { 1895 /* 1896 * MPxIO enabled for the iport 1897 */ 1898 ndi_devi_enter(scsi_vhci_dip, &circ1); 1899 ndi_devi_enter(dip, &circ); 1900 while (pip = mdi_get_next_client_path(dip, NULL)) { 1901 if (mdi_pi_free(pip, 0) == MDI_SUCCESS) { 1902 continue; 1903 } 1904 ndi_devi_exit(dip, circ); 1905 ndi_devi_exit(scsi_vhci_dip, circ1); 1906 NDBG12(("detach failed because of " 1907 "outstanding path info")); 1908 return (DDI_FAILURE); 1909 } 1910 ndi_devi_exit(dip, circ); 1911 ndi_devi_exit(scsi_vhci_dip, circ1); 1912 (void) mdi_phci_unregister(dip, 0); 1913 } 1914 1915 ddi_prop_remove_all(dip); 1916 1917 return (DDI_SUCCESS); 1918 } 1919 1920 /* Make sure power level is D0 before accessing registers */ 1921 if (mpt->m_options & MPTSAS_OPT_PM) { 1922 (void) pm_busy_component(dip, 0); 1923 if (mpt->m_power_level != PM_LEVEL_D0) { 1924 if (pm_raise_power(dip, 0, PM_LEVEL_D0) != 1925 DDI_SUCCESS) { 1926 mptsas_log(mpt, CE_WARN, 1927 "mptsas%d: Raise power request failed.", 1928 mpt->m_instance); 1929 (void) pm_idle_component(dip, 0); 1930 return (DDI_FAILURE); 1931 } 1932 } 1933 } 1934 1935 /* 1936 * Send RAID action system shutdown to sync IR. After action, send a 1937 * Message Unit Reset. Since after that DMA resource will be freed, 1938 * set ioc to READY state will avoid HBA initiated DMA operation. 1939 */ 1940 mutex_enter(&mpt->m_mutex); 1941 MPTSAS_DISABLE_INTR(mpt); 1942 mptsas_raid_action_system_shutdown(mpt); 1943 mpt->m_softstate |= MPTSAS_SS_MSG_UNIT_RESET; 1944 (void) mptsas_ioc_reset(mpt, FALSE); 1945 mutex_exit(&mpt->m_mutex); 1946 mptsas_rem_intrs(mpt); 1947 ddi_taskq_destroy(mpt->m_event_taskq); 1948 ddi_taskq_destroy(mpt->m_dr_taskq); 1949 1950 if (mpt->m_doneq_thread_n) { 1951 mutex_enter(&mpt->m_doneq_mutex); 1952 doneq_thread_num = mpt->m_doneq_thread_n; 1953 for (i = 0; i < mpt->m_doneq_thread_n; i++) { 1954 mutex_enter(&mpt->m_doneq_thread_id[i].mutex); 1955 mpt->m_doneq_thread_id[i].flag &= 1956 (~MPTSAS_DONEQ_THREAD_ACTIVE); 1957 cv_signal(&mpt->m_doneq_thread_id[i].cv); 1958 mutex_exit(&mpt->m_doneq_thread_id[i].mutex); 1959 } 1960 while (mpt->m_doneq_thread_n) { 1961 cv_wait(&mpt->m_doneq_thread_cv, 1962 &mpt->m_doneq_mutex); 1963 } 1964 for (i = 0; i < doneq_thread_num; i++) { 1965 cv_destroy(&mpt->m_doneq_thread_id[i].cv); 1966 mutex_destroy(&mpt->m_doneq_thread_id[i].mutex); 1967 } 1968 kmem_free(mpt->m_doneq_thread_id, 1969 sizeof (mptsas_doneq_thread_list_t) 1970 * doneq_thread_num); 1971 mutex_exit(&mpt->m_doneq_mutex); 1972 cv_destroy(&mpt->m_doneq_thread_cv); 1973 mutex_destroy(&mpt->m_doneq_mutex); 1974 } 1975 1976 scsi_hba_reset_notify_tear_down(mpt->m_reset_notify_listf); 1977 1978 mptsas_list_del(mpt); 1979 1980 /* 1981 * Cancel timeout threads for this mpt 1982 */ 1983 mutex_enter(&mpt->m_mutex); 1984 if (mpt->m_quiesce_timeid) { 1985 timeout_id_t tid = mpt->m_quiesce_timeid; 1986 mpt->m_quiesce_timeid = 0; 1987 mutex_exit(&mpt->m_mutex); 1988 (void) untimeout(tid); 1989 mutex_enter(&mpt->m_mutex); 1990 } 1991 1992 if (mpt->m_restart_cmd_timeid) { 1993 timeout_id_t tid = mpt->m_restart_cmd_timeid; 1994 mpt->m_restart_cmd_timeid = 0; 1995 mutex_exit(&mpt->m_mutex); 1996 (void) untimeout(tid); 1997 mutex_enter(&mpt->m_mutex); 1998 } 1999 2000 mutex_exit(&mpt->m_mutex); 2001 2002 /* 2003 * last mpt? ... if active, CANCEL watch threads. 2004 */ 2005 mutex_enter(&mptsas_global_mutex); 2006 if (mptsas_head == NULL) { 2007 timeout_id_t tid; 2008 /* 2009 * Clear mptsas_timeouts_enable so that the watch thread 2010 * gets restarted on DDI_ATTACH 2011 */ 2012 mptsas_timeouts_enabled = 0; 2013 if (mptsas_timeout_id) { 2014 tid = mptsas_timeout_id; 2015 mptsas_timeout_id = 0; 2016 mutex_exit(&mptsas_global_mutex); 2017 (void) untimeout(tid); 2018 mutex_enter(&mptsas_global_mutex); 2019 } 2020 if (mptsas_reset_watch) { 2021 tid = mptsas_reset_watch; 2022 mptsas_reset_watch = 0; 2023 mutex_exit(&mptsas_global_mutex); 2024 (void) untimeout(tid); 2025 mutex_enter(&mptsas_global_mutex); 2026 } 2027 } 2028 mutex_exit(&mptsas_global_mutex); 2029 2030 /* 2031 * Delete Phy stats 2032 */ 2033 mptsas_destroy_phy_stats(mpt); 2034 2035 mptsas_destroy_hashes(mpt); 2036 2037 /* 2038 * Delete nt_active. 2039 */ 2040 mutex_enter(&mpt->m_mutex); 2041 mptsas_free_active_slots(mpt); 2042 mutex_exit(&mpt->m_mutex); 2043 2044 /* deallocate everything that was allocated in mptsas_attach */ 2045 mptsas_cache_destroy(mpt); 2046 2047 mptsas_hba_fini(mpt); 2048 mptsas_cfg_fini(mpt); 2049 2050 /* Lower the power informing PM Framework */ 2051 if (mpt->m_options & MPTSAS_OPT_PM) { 2052 if (pm_lower_power(dip, 0, PM_LEVEL_D3) != DDI_SUCCESS) 2053 mptsas_log(mpt, CE_WARN, 2054 "!mptsas%d: Lower power request failed " 2055 "during detach, ignoring.", 2056 mpt->m_instance); 2057 } 2058 2059 mutex_destroy(&mpt->m_tx_waitq_mutex); 2060 mutex_destroy(&mpt->m_passthru_mutex); 2061 mutex_destroy(&mpt->m_mutex); 2062 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 2063 mutex_destroy(&mpt->m_phy_info[i].smhba_info.phy_mutex); 2064 } 2065 cv_destroy(&mpt->m_cv); 2066 cv_destroy(&mpt->m_passthru_cv); 2067 cv_destroy(&mpt->m_fw_cv); 2068 cv_destroy(&mpt->m_config_cv); 2069 cv_destroy(&mpt->m_fw_diag_cv); 2070 cv_destroy(&mpt->m_extreq_sense_refcount_cv); 2071 2072 mptsas_smp_teardown(mpt); 2073 mptsas_enc_teardown(mpt); 2074 mptsas_hba_teardown(mpt); 2075 2076 mptsas_config_space_fini(mpt); 2077 2078 mptsas_free_handshake_msg(mpt); 2079 2080 mptsas_fm_fini(mpt); 2081 ddi_soft_state_free(mptsas_state, ddi_get_instance(dip)); 2082 ddi_prop_remove_all(dip); 2083 2084 return (DDI_SUCCESS); 2085 } 2086 2087 static void 2088 mptsas_list_add(mptsas_t *mpt) 2089 { 2090 rw_enter(&mptsas_global_rwlock, RW_WRITER); 2091 2092 if (mptsas_head == NULL) { 2093 mptsas_head = mpt; 2094 } else { 2095 mptsas_tail->m_next = mpt; 2096 } 2097 mptsas_tail = mpt; 2098 rw_exit(&mptsas_global_rwlock); 2099 } 2100 2101 static void 2102 mptsas_list_del(mptsas_t *mpt) 2103 { 2104 mptsas_t *m; 2105 /* 2106 * Remove device instance from the global linked list 2107 */ 2108 rw_enter(&mptsas_global_rwlock, RW_WRITER); 2109 if (mptsas_head == mpt) { 2110 m = mptsas_head = mpt->m_next; 2111 } else { 2112 for (m = mptsas_head; m != NULL; m = m->m_next) { 2113 if (m->m_next == mpt) { 2114 m->m_next = mpt->m_next; 2115 break; 2116 } 2117 } 2118 if (m == NULL) { 2119 mptsas_log(mpt, CE_PANIC, "Not in softc list!"); 2120 } 2121 } 2122 2123 if (mptsas_tail == mpt) { 2124 mptsas_tail = m; 2125 } 2126 rw_exit(&mptsas_global_rwlock); 2127 } 2128 2129 static int 2130 mptsas_alloc_handshake_msg(mptsas_t *mpt, size_t alloc_size) 2131 { 2132 ddi_dma_attr_t task_dma_attrs; 2133 2134 mpt->m_hshk_dma_size = 0; 2135 task_dma_attrs = mpt->m_msg_dma_attr; 2136 task_dma_attrs.dma_attr_sgllen = 1; 2137 task_dma_attrs.dma_attr_granular = (uint32_t)(alloc_size); 2138 2139 /* allocate Task Management ddi_dma resources */ 2140 if (mptsas_dma_addr_create(mpt, task_dma_attrs, 2141 &mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl, &mpt->m_hshk_memp, 2142 alloc_size, NULL) == FALSE) { 2143 return (DDI_FAILURE); 2144 } 2145 mpt->m_hshk_dma_size = alloc_size; 2146 2147 return (DDI_SUCCESS); 2148 } 2149 2150 static void 2151 mptsas_free_handshake_msg(mptsas_t *mpt) 2152 { 2153 if (mpt->m_hshk_dma_size == 0) 2154 return; 2155 mptsas_dma_addr_destroy(&mpt->m_hshk_dma_hdl, &mpt->m_hshk_acc_hdl); 2156 mpt->m_hshk_dma_size = 0; 2157 } 2158 2159 static int 2160 mptsas_hba_setup(mptsas_t *mpt) 2161 { 2162 scsi_hba_tran_t *hba_tran; 2163 int tran_flags; 2164 2165 /* Allocate a transport structure */ 2166 hba_tran = mpt->m_tran = scsi_hba_tran_alloc(mpt->m_dip, 2167 SCSI_HBA_CANSLEEP); 2168 ASSERT(mpt->m_tran != NULL); 2169 2170 hba_tran->tran_hba_private = mpt; 2171 hba_tran->tran_tgt_private = NULL; 2172 2173 hba_tran->tran_tgt_init = mptsas_scsi_tgt_init; 2174 hba_tran->tran_tgt_free = mptsas_scsi_tgt_free; 2175 2176 hba_tran->tran_start = mptsas_scsi_start; 2177 hba_tran->tran_reset = mptsas_scsi_reset; 2178 hba_tran->tran_abort = mptsas_scsi_abort; 2179 hba_tran->tran_getcap = mptsas_scsi_getcap; 2180 hba_tran->tran_setcap = mptsas_scsi_setcap; 2181 hba_tran->tran_init_pkt = mptsas_scsi_init_pkt; 2182 hba_tran->tran_destroy_pkt = mptsas_scsi_destroy_pkt; 2183 2184 hba_tran->tran_dmafree = mptsas_scsi_dmafree; 2185 hba_tran->tran_sync_pkt = mptsas_scsi_sync_pkt; 2186 hba_tran->tran_reset_notify = mptsas_scsi_reset_notify; 2187 2188 hba_tran->tran_get_bus_addr = mptsas_get_bus_addr; 2189 hba_tran->tran_get_name = mptsas_get_name; 2190 2191 hba_tran->tran_quiesce = mptsas_scsi_quiesce; 2192 hba_tran->tran_unquiesce = mptsas_scsi_unquiesce; 2193 hba_tran->tran_bus_reset = NULL; 2194 2195 hba_tran->tran_add_eventcall = NULL; 2196 hba_tran->tran_get_eventcookie = NULL; 2197 hba_tran->tran_post_event = NULL; 2198 hba_tran->tran_remove_eventcall = NULL; 2199 2200 hba_tran->tran_bus_config = mptsas_bus_config; 2201 2202 hba_tran->tran_interconnect_type = INTERCONNECT_SAS; 2203 2204 /* 2205 * All children of the HBA are iports. We need tran was cloned. 2206 * So we pass the flags to SCSA. SCSI_HBA_TRAN_CLONE will be 2207 * inherited to iport's tran vector. 2208 */ 2209 tran_flags = (SCSI_HBA_HBA | SCSI_HBA_TRAN_CLONE); 2210 2211 if (scsi_hba_attach_setup(mpt->m_dip, &mpt->m_msg_dma_attr, 2212 hba_tran, tran_flags) != DDI_SUCCESS) { 2213 mptsas_log(mpt, CE_WARN, "hba attach setup failed"); 2214 scsi_hba_tran_free(hba_tran); 2215 mpt->m_tran = NULL; 2216 return (FALSE); 2217 } 2218 return (TRUE); 2219 } 2220 2221 static void 2222 mptsas_hba_teardown(mptsas_t *mpt) 2223 { 2224 (void) scsi_hba_detach(mpt->m_dip); 2225 if (mpt->m_tran != NULL) { 2226 scsi_hba_tran_free(mpt->m_tran); 2227 mpt->m_tran = NULL; 2228 } 2229 } 2230 2231 static void 2232 mptsas_iport_register(mptsas_t *mpt) 2233 { 2234 int i, j; 2235 mptsas_phymask_t mask = 0x0; 2236 /* 2237 * initial value of mask is 0 2238 */ 2239 mutex_enter(&mpt->m_mutex); 2240 for (i = 0; i < mpt->m_num_phys; i++) { 2241 mptsas_phymask_t phy_mask = 0x0; 2242 char phy_mask_name[MPTSAS_MAX_PHYS]; 2243 uint8_t current_port; 2244 2245 if (mpt->m_phy_info[i].attached_devhdl == 0) 2246 continue; 2247 2248 bzero(phy_mask_name, sizeof (phy_mask_name)); 2249 2250 current_port = mpt->m_phy_info[i].port_num; 2251 2252 if ((mask & (1 << i)) != 0) 2253 continue; 2254 2255 for (j = 0; j < mpt->m_num_phys; j++) { 2256 if (mpt->m_phy_info[j].attached_devhdl && 2257 (mpt->m_phy_info[j].port_num == current_port)) { 2258 phy_mask |= (1 << j); 2259 } 2260 } 2261 mask = mask | phy_mask; 2262 2263 for (j = 0; j < mpt->m_num_phys; j++) { 2264 if ((phy_mask >> j) & 0x01) { 2265 mpt->m_phy_info[j].phy_mask = phy_mask; 2266 } 2267 } 2268 2269 (void) sprintf(phy_mask_name, "%x", phy_mask); 2270 2271 mutex_exit(&mpt->m_mutex); 2272 /* 2273 * register a iport 2274 */ 2275 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name); 2276 mutex_enter(&mpt->m_mutex); 2277 } 2278 mutex_exit(&mpt->m_mutex); 2279 /* 2280 * register a virtual port for RAID volume always 2281 */ 2282 (void) scsi_hba_iport_register(mpt->m_dip, "v0"); 2283 2284 } 2285 2286 static int 2287 mptsas_smp_setup(mptsas_t *mpt) 2288 { 2289 mpt->m_smptran = smp_hba_tran_alloc(mpt->m_dip); 2290 ASSERT(mpt->m_smptran != NULL); 2291 mpt->m_smptran->smp_tran_hba_private = mpt; 2292 mpt->m_smptran->smp_tran_start = mptsas_smp_start; 2293 if (smp_hba_attach_setup(mpt->m_dip, mpt->m_smptran) != DDI_SUCCESS) { 2294 mptsas_log(mpt, CE_WARN, "smp attach setup failed"); 2295 smp_hba_tran_free(mpt->m_smptran); 2296 mpt->m_smptran = NULL; 2297 return (FALSE); 2298 } 2299 /* 2300 * Initialize smp hash table 2301 */ 2302 mpt->m_smp_targets = refhash_create(MPTSAS_SMP_BUCKET_COUNT, 2303 mptsas_target_addr_hash, mptsas_target_addr_cmp, 2304 mptsas_smp_free, sizeof (mptsas_smp_t), 2305 offsetof(mptsas_smp_t, m_link), offsetof(mptsas_smp_t, m_addr), 2306 KM_SLEEP); 2307 mpt->m_smp_devhdl = 0xFFFF; 2308 2309 return (TRUE); 2310 } 2311 2312 static void 2313 mptsas_smp_teardown(mptsas_t *mpt) 2314 { 2315 (void) smp_hba_detach(mpt->m_dip); 2316 if (mpt->m_smptran != NULL) { 2317 smp_hba_tran_free(mpt->m_smptran); 2318 mpt->m_smptran = NULL; 2319 } 2320 mpt->m_smp_devhdl = 0; 2321 } 2322 2323 static int 2324 mptsas_enc_setup(mptsas_t *mpt) 2325 { 2326 list_create(&mpt->m_enclosures, sizeof (mptsas_enclosure_t), 2327 offsetof(mptsas_enclosure_t, me_link)); 2328 return (TRUE); 2329 } 2330 2331 static void 2332 mptsas_enc_teardown(mptsas_t *mpt) 2333 { 2334 mptsas_enclosure_t *mep; 2335 2336 while ((mep = list_remove_head(&mpt->m_enclosures)) != NULL) { 2337 kmem_free(mep, sizeof (mptsas_enclosure_t)); 2338 } 2339 list_destroy(&mpt->m_enclosures); 2340 } 2341 2342 static mptsas_enclosure_t * 2343 mptsas_enc_lookup(mptsas_t *mpt, uint16_t hdl) 2344 { 2345 mptsas_enclosure_t *mep; 2346 2347 ASSERT(MUTEX_HELD(&mpt->m_mutex)); 2348 2349 for (mep = list_head(&mpt->m_enclosures); mep != NULL; 2350 mep = list_next(&mpt->m_enclosures, mep)) { 2351 if (hdl == mep->me_enchdl) { 2352 return (mep); 2353 } 2354 } 2355 2356 return (NULL); 2357 } 2358 2359 static int 2360 mptsas_cache_create(mptsas_t *mpt) 2361 { 2362 int instance = mpt->m_instance; 2363 char buf[64]; 2364 2365 /* 2366 * create kmem cache for packets 2367 */ 2368 (void) sprintf(buf, "mptsas%d_cache", instance); 2369 mpt->m_kmem_cache = kmem_cache_create(buf, 2370 sizeof (struct mptsas_cmd) + scsi_pkt_size(), 8, 2371 mptsas_kmem_cache_constructor, mptsas_kmem_cache_destructor, 2372 NULL, (void *)mpt, NULL, 0); 2373 2374 if (mpt->m_kmem_cache == NULL) { 2375 mptsas_log(mpt, CE_WARN, "creating kmem cache failed"); 2376 return (FALSE); 2377 } 2378 2379 /* 2380 * create kmem cache for extra SGL frames if SGL cannot 2381 * be accomodated into main request frame. 2382 */ 2383 (void) sprintf(buf, "mptsas%d_cache_frames", instance); 2384 mpt->m_cache_frames = kmem_cache_create(buf, 2385 sizeof (mptsas_cache_frames_t), 8, 2386 mptsas_cache_frames_constructor, mptsas_cache_frames_destructor, 2387 NULL, (void *)mpt, NULL, 0); 2388 2389 if (mpt->m_cache_frames == NULL) { 2390 mptsas_log(mpt, CE_WARN, "creating cache for frames failed"); 2391 return (FALSE); 2392 } 2393 2394 return (TRUE); 2395 } 2396 2397 static void 2398 mptsas_cache_destroy(mptsas_t *mpt) 2399 { 2400 /* deallocate in reverse order */ 2401 if (mpt->m_cache_frames) { 2402 kmem_cache_destroy(mpt->m_cache_frames); 2403 mpt->m_cache_frames = NULL; 2404 } 2405 if (mpt->m_kmem_cache) { 2406 kmem_cache_destroy(mpt->m_kmem_cache); 2407 mpt->m_kmem_cache = NULL; 2408 } 2409 } 2410 2411 static int 2412 mptsas_power(dev_info_t *dip, int component, int level) 2413 { 2414 #ifndef __lock_lint 2415 _NOTE(ARGUNUSED(component)) 2416 #endif 2417 mptsas_t *mpt; 2418 int rval = DDI_SUCCESS; 2419 int polls = 0; 2420 uint32_t ioc_status; 2421 2422 if (scsi_hba_iport_unit_address(dip) != 0) 2423 return (DDI_SUCCESS); 2424 2425 mpt = ddi_get_soft_state(mptsas_state, ddi_get_instance(dip)); 2426 if (mpt == NULL) { 2427 return (DDI_FAILURE); 2428 } 2429 2430 mutex_enter(&mpt->m_mutex); 2431 2432 /* 2433 * If the device is busy, don't lower its power level 2434 */ 2435 if (mpt->m_busy && (mpt->m_power_level > level)) { 2436 mutex_exit(&mpt->m_mutex); 2437 return (DDI_FAILURE); 2438 } 2439 switch (level) { 2440 case PM_LEVEL_D0: 2441 NDBG11(("mptsas%d: turning power ON.", mpt->m_instance)); 2442 MPTSAS_POWER_ON(mpt); 2443 /* 2444 * Wait up to 30 seconds for IOC to come out of reset. 2445 */ 2446 while (((ioc_status = ddi_get32(mpt->m_datap, 2447 &mpt->m_reg->Doorbell)) & 2448 MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_RESET) { 2449 if (polls++ > 3000) { 2450 break; 2451 } 2452 delay(drv_usectohz(10000)); 2453 } 2454 /* 2455 * If IOC is not in operational state, try to hard reset it. 2456 */ 2457 if ((ioc_status & MPI2_IOC_STATE_MASK) != 2458 MPI2_IOC_STATE_OPERATIONAL) { 2459 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET; 2460 if (mptsas_restart_ioc(mpt) == DDI_FAILURE) { 2461 mptsas_log(mpt, CE_WARN, 2462 "mptsas_power: hard reset failed"); 2463 mutex_exit(&mpt->m_mutex); 2464 return (DDI_FAILURE); 2465 } 2466 } 2467 mpt->m_power_level = PM_LEVEL_D0; 2468 break; 2469 case PM_LEVEL_D3: 2470 NDBG11(("mptsas%d: turning power OFF.", mpt->m_instance)); 2471 MPTSAS_POWER_OFF(mpt); 2472 break; 2473 default: 2474 mptsas_log(mpt, CE_WARN, "mptsas%d: unknown power level <%x>.", 2475 mpt->m_instance, level); 2476 rval = DDI_FAILURE; 2477 break; 2478 } 2479 mutex_exit(&mpt->m_mutex); 2480 return (rval); 2481 } 2482 2483 /* 2484 * Initialize configuration space and figure out which 2485 * chip and revison of the chip the mpt driver is using. 2486 */ 2487 static int 2488 mptsas_config_space_init(mptsas_t *mpt) 2489 { 2490 NDBG0(("mptsas_config_space_init")); 2491 2492 if (mpt->m_config_handle != NULL) 2493 return (TRUE); 2494 2495 if (pci_config_setup(mpt->m_dip, 2496 &mpt->m_config_handle) != DDI_SUCCESS) { 2497 mptsas_log(mpt, CE_WARN, "cannot map configuration space."); 2498 return (FALSE); 2499 } 2500 2501 /* 2502 * This is a workaround for a XMITS ASIC bug which does not 2503 * drive the CBE upper bits. 2504 */ 2505 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT) & 2506 PCI_STAT_PERROR) { 2507 pci_config_put16(mpt->m_config_handle, PCI_CONF_STAT, 2508 PCI_STAT_PERROR); 2509 } 2510 2511 mptsas_setup_cmd_reg(mpt); 2512 2513 /* 2514 * Get the chip device id: 2515 */ 2516 mpt->m_devid = pci_config_get16(mpt->m_config_handle, PCI_CONF_DEVID); 2517 2518 /* 2519 * Save the revision. 2520 */ 2521 mpt->m_revid = pci_config_get8(mpt->m_config_handle, PCI_CONF_REVID); 2522 2523 /* 2524 * Save the SubSystem Vendor and Device IDs 2525 */ 2526 mpt->m_svid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBVENID); 2527 mpt->m_ssid = pci_config_get16(mpt->m_config_handle, PCI_CONF_SUBSYSID); 2528 2529 /* 2530 * Set the latency timer to 0x40 as specified by the upa -> pci 2531 * bridge chip design team. This may be done by the sparc pci 2532 * bus nexus driver, but the driver should make sure the latency 2533 * timer is correct for performance reasons. 2534 */ 2535 pci_config_put8(mpt->m_config_handle, PCI_CONF_LATENCY_TIMER, 2536 MPTSAS_LATENCY_TIMER); 2537 2538 (void) mptsas_get_pci_cap(mpt); 2539 return (TRUE); 2540 } 2541 2542 static void 2543 mptsas_config_space_fini(mptsas_t *mpt) 2544 { 2545 if (mpt->m_config_handle != NULL) { 2546 mptsas_disable_bus_master(mpt); 2547 pci_config_teardown(&mpt->m_config_handle); 2548 mpt->m_config_handle = NULL; 2549 } 2550 } 2551 2552 static void 2553 mptsas_setup_cmd_reg(mptsas_t *mpt) 2554 { 2555 ushort_t cmdreg; 2556 2557 /* 2558 * Set the command register to the needed values. 2559 */ 2560 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM); 2561 cmdreg |= (PCI_COMM_ME | PCI_COMM_SERR_ENABLE | 2562 PCI_COMM_PARITY_DETECT | PCI_COMM_MAE); 2563 cmdreg &= ~PCI_COMM_IO; 2564 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg); 2565 } 2566 2567 static void 2568 mptsas_disable_bus_master(mptsas_t *mpt) 2569 { 2570 ushort_t cmdreg; 2571 2572 /* 2573 * Clear the master enable bit in the PCI command register. 2574 * This prevents any bus mastering activity like DMA. 2575 */ 2576 cmdreg = pci_config_get16(mpt->m_config_handle, PCI_CONF_COMM); 2577 cmdreg &= ~PCI_COMM_ME; 2578 pci_config_put16(mpt->m_config_handle, PCI_CONF_COMM, cmdreg); 2579 } 2580 2581 int 2582 mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep) 2583 { 2584 ddi_dma_attr_t attrs; 2585 2586 attrs = mpt->m_io_dma_attr; 2587 attrs.dma_attr_sgllen = 1; 2588 2589 ASSERT(dma_statep != NULL); 2590 2591 if (mptsas_dma_addr_create(mpt, attrs, &dma_statep->handle, 2592 &dma_statep->accessp, &dma_statep->memp, dma_statep->size, 2593 &dma_statep->cookie) == FALSE) { 2594 return (DDI_FAILURE); 2595 } 2596 2597 return (DDI_SUCCESS); 2598 } 2599 2600 void 2601 mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep) 2602 { 2603 ASSERT(dma_statep != NULL); 2604 mptsas_dma_addr_destroy(&dma_statep->handle, &dma_statep->accessp); 2605 dma_statep->size = 0; 2606 } 2607 2608 int 2609 mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)()) 2610 { 2611 ddi_dma_attr_t attrs; 2612 ddi_dma_handle_t dma_handle; 2613 caddr_t memp; 2614 ddi_acc_handle_t accessp; 2615 int rval; 2616 2617 ASSERT(mutex_owned(&mpt->m_mutex)); 2618 2619 attrs = mpt->m_msg_dma_attr; 2620 attrs.dma_attr_sgllen = 1; 2621 attrs.dma_attr_granular = size; 2622 2623 if (mptsas_dma_addr_create(mpt, attrs, &dma_handle, 2624 &accessp, &memp, size, NULL) == FALSE) { 2625 return (DDI_FAILURE); 2626 } 2627 2628 rval = (*callback) (mpt, memp, var, accessp); 2629 2630 if ((mptsas_check_dma_handle(dma_handle) != DDI_SUCCESS) || 2631 (mptsas_check_acc_handle(accessp) != DDI_SUCCESS)) { 2632 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 2633 rval = DDI_FAILURE; 2634 } 2635 2636 mptsas_dma_addr_destroy(&dma_handle, &accessp); 2637 return (rval); 2638 2639 } 2640 2641 static int 2642 mptsas_alloc_request_frames(mptsas_t *mpt) 2643 { 2644 ddi_dma_attr_t frame_dma_attrs; 2645 caddr_t memp; 2646 ddi_dma_cookie_t cookie; 2647 size_t mem_size; 2648 2649 /* 2650 * re-alloc when it has already alloced 2651 */ 2652 if (mpt->m_dma_req_frame_hdl) 2653 mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl, 2654 &mpt->m_acc_req_frame_hdl); 2655 2656 /* 2657 * The size of the request frame pool is: 2658 * Number of Request Frames * Request Frame Size 2659 */ 2660 mem_size = mpt->m_max_requests * mpt->m_req_frame_size; 2661 2662 /* 2663 * set the DMA attributes. System Request Message Frames must be 2664 * aligned on a 16-byte boundry. 2665 */ 2666 frame_dma_attrs = mpt->m_msg_dma_attr; 2667 frame_dma_attrs.dma_attr_align = 16; 2668 frame_dma_attrs.dma_attr_sgllen = 1; 2669 2670 /* 2671 * allocate the request frame pool. 2672 */ 2673 if (mptsas_dma_addr_create(mpt, frame_dma_attrs, 2674 &mpt->m_dma_req_frame_hdl, &mpt->m_acc_req_frame_hdl, &memp, 2675 mem_size, &cookie) == FALSE) { 2676 return (DDI_FAILURE); 2677 } 2678 2679 /* 2680 * Store the request frame memory address. This chip uses this 2681 * address to dma to and from the driver's frame. The second 2682 * address is the address mpt uses to fill in the frame. 2683 */ 2684 mpt->m_req_frame_dma_addr = cookie.dmac_laddress; 2685 mpt->m_req_frame = memp; 2686 2687 /* 2688 * Clear the request frame pool. 2689 */ 2690 bzero(mpt->m_req_frame, mem_size); 2691 2692 return (DDI_SUCCESS); 2693 } 2694 2695 static int 2696 mptsas_alloc_sense_bufs(mptsas_t *mpt) 2697 { 2698 ddi_dma_attr_t sense_dma_attrs; 2699 caddr_t memp; 2700 ddi_dma_cookie_t cookie; 2701 size_t mem_size; 2702 int num_extrqsense_bufs; 2703 2704 ASSERT(mpt->m_extreq_sense_refcount == 0); 2705 2706 /* 2707 * re-alloc when it has already alloced 2708 */ 2709 if (mpt->m_dma_req_sense_hdl) { 2710 rmfreemap(mpt->m_erqsense_map); 2711 mptsas_dma_addr_destroy(&mpt->m_dma_req_sense_hdl, 2712 &mpt->m_acc_req_sense_hdl); 2713 } 2714 2715 /* 2716 * The size of the request sense pool is: 2717 * (Number of Request Frames - 2 ) * Request Sense Size + 2718 * extra memory for extended sense requests. 2719 */ 2720 mem_size = ((mpt->m_max_requests - 2) * mpt->m_req_sense_size) + 2721 mptsas_extreq_sense_bufsize; 2722 2723 /* 2724 * set the DMA attributes. ARQ buffers 2725 * aligned on a 16-byte boundry. 2726 */ 2727 sense_dma_attrs = mpt->m_msg_dma_attr; 2728 sense_dma_attrs.dma_attr_align = 16; 2729 sense_dma_attrs.dma_attr_sgllen = 1; 2730 2731 /* 2732 * allocate the request sense buffer pool. 2733 */ 2734 if (mptsas_dma_addr_create(mpt, sense_dma_attrs, 2735 &mpt->m_dma_req_sense_hdl, &mpt->m_acc_req_sense_hdl, &memp, 2736 mem_size, &cookie) == FALSE) { 2737 return (DDI_FAILURE); 2738 } 2739 2740 /* 2741 * Store the request sense base memory address. This chip uses this 2742 * address to dma the request sense data. The second 2743 * address is the address mpt uses to access the data. 2744 * The third is the base for the extended rqsense buffers. 2745 */ 2746 mpt->m_req_sense_dma_addr = cookie.dmac_laddress; 2747 mpt->m_req_sense = memp; 2748 memp += (mpt->m_max_requests - 2) * mpt->m_req_sense_size; 2749 mpt->m_extreq_sense = memp; 2750 2751 /* 2752 * The extra memory is divided up into multiples of the base 2753 * buffer size in order to allocate via rmalloc(). 2754 * Note that the rmallocmap cannot start at zero! 2755 */ 2756 num_extrqsense_bufs = mptsas_extreq_sense_bufsize / 2757 mpt->m_req_sense_size; 2758 mpt->m_erqsense_map = rmallocmap_wait(num_extrqsense_bufs); 2759 rmfree(mpt->m_erqsense_map, num_extrqsense_bufs, 1); 2760 2761 /* 2762 * Clear the pool. 2763 */ 2764 bzero(mpt->m_req_sense, mem_size); 2765 2766 return (DDI_SUCCESS); 2767 } 2768 2769 static int 2770 mptsas_alloc_reply_frames(mptsas_t *mpt) 2771 { 2772 ddi_dma_attr_t frame_dma_attrs; 2773 caddr_t memp; 2774 ddi_dma_cookie_t cookie; 2775 size_t mem_size; 2776 2777 /* 2778 * re-alloc when it has already alloced 2779 */ 2780 if (mpt->m_dma_reply_frame_hdl) { 2781 mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl, 2782 &mpt->m_acc_reply_frame_hdl); 2783 } 2784 2785 /* 2786 * The size of the reply frame pool is: 2787 * Number of Reply Frames * Reply Frame Size 2788 */ 2789 mem_size = mpt->m_max_replies * mpt->m_reply_frame_size; 2790 2791 /* 2792 * set the DMA attributes. System Reply Message Frames must be 2793 * aligned on a 4-byte boundry. This is the default. 2794 */ 2795 frame_dma_attrs = mpt->m_msg_dma_attr; 2796 frame_dma_attrs.dma_attr_sgllen = 1; 2797 2798 /* 2799 * allocate the reply frame pool 2800 */ 2801 if (mptsas_dma_addr_create(mpt, frame_dma_attrs, 2802 &mpt->m_dma_reply_frame_hdl, &mpt->m_acc_reply_frame_hdl, &memp, 2803 mem_size, &cookie) == FALSE) { 2804 return (DDI_FAILURE); 2805 } 2806 2807 /* 2808 * Store the reply frame memory address. This chip uses this 2809 * address to dma to and from the driver's frame. The second 2810 * address is the address mpt uses to process the frame. 2811 */ 2812 mpt->m_reply_frame_dma_addr = cookie.dmac_laddress; 2813 mpt->m_reply_frame = memp; 2814 2815 /* 2816 * Clear the reply frame pool. 2817 */ 2818 bzero(mpt->m_reply_frame, mem_size); 2819 2820 return (DDI_SUCCESS); 2821 } 2822 2823 static int 2824 mptsas_alloc_free_queue(mptsas_t *mpt) 2825 { 2826 ddi_dma_attr_t frame_dma_attrs; 2827 caddr_t memp; 2828 ddi_dma_cookie_t cookie; 2829 size_t mem_size; 2830 2831 /* 2832 * re-alloc when it has already alloced 2833 */ 2834 if (mpt->m_dma_free_queue_hdl) { 2835 mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl, 2836 &mpt->m_acc_free_queue_hdl); 2837 } 2838 2839 /* 2840 * The reply free queue size is: 2841 * Reply Free Queue Depth * 4 2842 * The "4" is the size of one 32 bit address (low part of 64-bit 2843 * address) 2844 */ 2845 mem_size = mpt->m_free_queue_depth * 4; 2846 2847 /* 2848 * set the DMA attributes The Reply Free Queue must be aligned on a 2849 * 16-byte boundry. 2850 */ 2851 frame_dma_attrs = mpt->m_msg_dma_attr; 2852 frame_dma_attrs.dma_attr_align = 16; 2853 frame_dma_attrs.dma_attr_sgllen = 1; 2854 2855 /* 2856 * allocate the reply free queue 2857 */ 2858 if (mptsas_dma_addr_create(mpt, frame_dma_attrs, 2859 &mpt->m_dma_free_queue_hdl, &mpt->m_acc_free_queue_hdl, &memp, 2860 mem_size, &cookie) == FALSE) { 2861 return (DDI_FAILURE); 2862 } 2863 2864 /* 2865 * Store the reply free queue memory address. This chip uses this 2866 * address to read from the reply free queue. The second address 2867 * is the address mpt uses to manage the queue. 2868 */ 2869 mpt->m_free_queue_dma_addr = cookie.dmac_laddress; 2870 mpt->m_free_queue = memp; 2871 2872 /* 2873 * Clear the reply free queue memory. 2874 */ 2875 bzero(mpt->m_free_queue, mem_size); 2876 2877 return (DDI_SUCCESS); 2878 } 2879 2880 static int 2881 mptsas_alloc_post_queue(mptsas_t *mpt) 2882 { 2883 ddi_dma_attr_t frame_dma_attrs; 2884 caddr_t memp; 2885 ddi_dma_cookie_t cookie; 2886 size_t mem_size; 2887 2888 /* 2889 * re-alloc when it has already alloced 2890 */ 2891 if (mpt->m_dma_post_queue_hdl) { 2892 mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl, 2893 &mpt->m_acc_post_queue_hdl); 2894 } 2895 2896 /* 2897 * The reply descriptor post queue size is: 2898 * Reply Descriptor Post Queue Depth * 8 2899 * The "8" is the size of each descriptor (8 bytes or 64 bits). 2900 */ 2901 mem_size = mpt->m_post_queue_depth * 8; 2902 2903 /* 2904 * set the DMA attributes. The Reply Descriptor Post Queue must be 2905 * aligned on a 16-byte boundry. 2906 */ 2907 frame_dma_attrs = mpt->m_msg_dma_attr; 2908 frame_dma_attrs.dma_attr_align = 16; 2909 frame_dma_attrs.dma_attr_sgllen = 1; 2910 2911 /* 2912 * allocate the reply post queue 2913 */ 2914 if (mptsas_dma_addr_create(mpt, frame_dma_attrs, 2915 &mpt->m_dma_post_queue_hdl, &mpt->m_acc_post_queue_hdl, &memp, 2916 mem_size, &cookie) == FALSE) { 2917 return (DDI_FAILURE); 2918 } 2919 2920 /* 2921 * Store the reply descriptor post queue memory address. This chip 2922 * uses this address to write to the reply descriptor post queue. The 2923 * second address is the address mpt uses to manage the queue. 2924 */ 2925 mpt->m_post_queue_dma_addr = cookie.dmac_laddress; 2926 mpt->m_post_queue = memp; 2927 2928 /* 2929 * Clear the reply post queue memory. 2930 */ 2931 bzero(mpt->m_post_queue, mem_size); 2932 2933 return (DDI_SUCCESS); 2934 } 2935 2936 static void 2937 mptsas_alloc_reply_args(mptsas_t *mpt) 2938 { 2939 if (mpt->m_replyh_args == NULL) { 2940 mpt->m_replyh_args = kmem_zalloc(sizeof (m_replyh_arg_t) * 2941 mpt->m_max_replies, KM_SLEEP); 2942 } 2943 } 2944 2945 static int 2946 mptsas_alloc_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd) 2947 { 2948 mptsas_cache_frames_t *frames = NULL; 2949 if (cmd->cmd_extra_frames == NULL) { 2950 frames = kmem_cache_alloc(mpt->m_cache_frames, KM_NOSLEEP); 2951 if (frames == NULL) { 2952 return (DDI_FAILURE); 2953 } 2954 cmd->cmd_extra_frames = frames; 2955 } 2956 return (DDI_SUCCESS); 2957 } 2958 2959 static void 2960 mptsas_free_extra_sgl_frame(mptsas_t *mpt, mptsas_cmd_t *cmd) 2961 { 2962 if (cmd->cmd_extra_frames) { 2963 kmem_cache_free(mpt->m_cache_frames, 2964 (void *)cmd->cmd_extra_frames); 2965 cmd->cmd_extra_frames = NULL; 2966 } 2967 } 2968 2969 static void 2970 mptsas_cfg_fini(mptsas_t *mpt) 2971 { 2972 NDBG0(("mptsas_cfg_fini")); 2973 ddi_regs_map_free(&mpt->m_datap); 2974 } 2975 2976 static void 2977 mptsas_hba_fini(mptsas_t *mpt) 2978 { 2979 NDBG0(("mptsas_hba_fini")); 2980 2981 /* 2982 * Free up any allocated memory 2983 */ 2984 if (mpt->m_dma_req_frame_hdl) { 2985 mptsas_dma_addr_destroy(&mpt->m_dma_req_frame_hdl, 2986 &mpt->m_acc_req_frame_hdl); 2987 } 2988 2989 if (mpt->m_dma_req_sense_hdl) { 2990 rmfreemap(mpt->m_erqsense_map); 2991 mptsas_dma_addr_destroy(&mpt->m_dma_req_sense_hdl, 2992 &mpt->m_acc_req_sense_hdl); 2993 } 2994 2995 if (mpt->m_dma_reply_frame_hdl) { 2996 mptsas_dma_addr_destroy(&mpt->m_dma_reply_frame_hdl, 2997 &mpt->m_acc_reply_frame_hdl); 2998 } 2999 3000 if (mpt->m_dma_free_queue_hdl) { 3001 mptsas_dma_addr_destroy(&mpt->m_dma_free_queue_hdl, 3002 &mpt->m_acc_free_queue_hdl); 3003 } 3004 3005 if (mpt->m_dma_post_queue_hdl) { 3006 mptsas_dma_addr_destroy(&mpt->m_dma_post_queue_hdl, 3007 &mpt->m_acc_post_queue_hdl); 3008 } 3009 3010 if (mpt->m_replyh_args != NULL) { 3011 kmem_free(mpt->m_replyh_args, sizeof (m_replyh_arg_t) 3012 * mpt->m_max_replies); 3013 } 3014 } 3015 3016 static int 3017 mptsas_name_child(dev_info_t *lun_dip, char *name, int len) 3018 { 3019 int lun = 0; 3020 char *sas_wwn = NULL; 3021 int phynum = -1; 3022 int reallen = 0; 3023 3024 /* Get the target num */ 3025 lun = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip, DDI_PROP_DONTPASS, 3026 LUN_PROP, 0); 3027 3028 if ((phynum = ddi_prop_get_int(DDI_DEV_T_ANY, lun_dip, 3029 DDI_PROP_DONTPASS, "sata-phy", -1)) != -1) { 3030 /* 3031 * Stick in the address of form "pPHY,LUN" 3032 */ 3033 reallen = snprintf(name, len, "p%x,%x", phynum, lun); 3034 } else if (ddi_prop_lookup_string(DDI_DEV_T_ANY, lun_dip, 3035 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &sas_wwn) 3036 == DDI_PROP_SUCCESS) { 3037 /* 3038 * Stick in the address of the form "wWWN,LUN" 3039 */ 3040 reallen = snprintf(name, len, "%s,%x", sas_wwn, lun); 3041 ddi_prop_free(sas_wwn); 3042 } else { 3043 return (DDI_FAILURE); 3044 } 3045 3046 ASSERT(reallen < len); 3047 if (reallen >= len) { 3048 mptsas_log(0, CE_WARN, "!mptsas_get_name: name parameter " 3049 "length too small, it needs to be %d bytes", reallen + 1); 3050 } 3051 return (DDI_SUCCESS); 3052 } 3053 3054 /* 3055 * tran_tgt_init(9E) - target device instance initialization 3056 */ 3057 static int 3058 mptsas_scsi_tgt_init(dev_info_t *hba_dip, dev_info_t *tgt_dip, 3059 scsi_hba_tran_t *hba_tran, struct scsi_device *sd) 3060 { 3061 #ifndef __lock_lint 3062 _NOTE(ARGUNUSED(hba_tran)) 3063 #endif 3064 3065 /* 3066 * At this point, the scsi_device structure already exists 3067 * and has been initialized. 3068 * 3069 * Use this function to allocate target-private data structures, 3070 * if needed by this HBA. Add revised flow-control and queue 3071 * properties for child here, if desired and if you can tell they 3072 * support tagged queueing by now. 3073 */ 3074 mptsas_t *mpt; 3075 int lun = sd->sd_address.a_lun; 3076 mdi_pathinfo_t *pip = NULL; 3077 mptsas_tgt_private_t *tgt_private = NULL; 3078 mptsas_target_t *ptgt = NULL; 3079 char *psas_wwn = NULL; 3080 mptsas_phymask_t phymask = 0; 3081 uint64_t sas_wwn = 0; 3082 mptsas_target_addr_t addr; 3083 mpt = SDEV2MPT(sd); 3084 3085 ASSERT(scsi_hba_iport_unit_address(hba_dip) != 0); 3086 3087 NDBG0(("mptsas_scsi_tgt_init: hbadip=0x%p tgtdip=0x%p lun=%d", 3088 (void *)hba_dip, (void *)tgt_dip, lun)); 3089 3090 if (ndi_dev_is_persistent_node(tgt_dip) == 0) { 3091 (void) ndi_merge_node(tgt_dip, mptsas_name_child); 3092 ddi_set_name_addr(tgt_dip, NULL); 3093 return (DDI_FAILURE); 3094 } 3095 /* 3096 * phymask is 0 means the virtual port for RAID 3097 */ 3098 phymask = (mptsas_phymask_t)ddi_prop_get_int(DDI_DEV_T_ANY, hba_dip, 0, 3099 "phymask", 0); 3100 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) { 3101 if ((pip = (void *)(sd->sd_private)) == NULL) { 3102 /* 3103 * Very bad news if this occurs. Somehow scsi_vhci has 3104 * lost the pathinfo node for this target. 3105 */ 3106 return (DDI_NOT_WELL_FORMED); 3107 } 3108 3109 if (mdi_prop_lookup_int(pip, LUN_PROP, &lun) != 3110 DDI_PROP_SUCCESS) { 3111 mptsas_log(mpt, CE_WARN, "Get lun property failed\n"); 3112 return (DDI_FAILURE); 3113 } 3114 3115 if (mdi_prop_lookup_string(pip, SCSI_ADDR_PROP_TARGET_PORT, 3116 &psas_wwn) == MDI_SUCCESS) { 3117 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) { 3118 sas_wwn = 0; 3119 } 3120 (void) mdi_prop_free(psas_wwn); 3121 } 3122 } else { 3123 lun = ddi_prop_get_int(DDI_DEV_T_ANY, tgt_dip, 3124 DDI_PROP_DONTPASS, LUN_PROP, 0); 3125 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, tgt_dip, 3126 DDI_PROP_DONTPASS, SCSI_ADDR_PROP_TARGET_PORT, &psas_wwn) == 3127 DDI_PROP_SUCCESS) { 3128 if (scsi_wwnstr_to_wwn(psas_wwn, &sas_wwn)) { 3129 sas_wwn = 0; 3130 } 3131 ddi_prop_free(psas_wwn); 3132 } else { 3133 sas_wwn = 0; 3134 } 3135 } 3136 3137 ASSERT((sas_wwn != 0) || (phymask != 0)); 3138 addr.mta_wwn = sas_wwn; 3139 addr.mta_phymask = phymask; 3140 mutex_enter(&mpt->m_mutex); 3141 ptgt = refhash_lookup(mpt->m_targets, &addr); 3142 mutex_exit(&mpt->m_mutex); 3143 if (ptgt == NULL) { 3144 mptsas_log(mpt, CE_WARN, "!tgt_init: target doesn't exist or " 3145 "gone already! phymask:%x, saswwn %"PRIx64, phymask, 3146 sas_wwn); 3147 return (DDI_FAILURE); 3148 } 3149 if (hba_tran->tran_tgt_private == NULL) { 3150 tgt_private = kmem_zalloc(sizeof (mptsas_tgt_private_t), 3151 KM_SLEEP); 3152 tgt_private->t_lun = lun; 3153 tgt_private->t_private = ptgt; 3154 hba_tran->tran_tgt_private = tgt_private; 3155 } 3156 3157 if (mdi_component_is_client(tgt_dip, NULL) == MDI_SUCCESS) { 3158 return (DDI_SUCCESS); 3159 } 3160 mutex_enter(&mpt->m_mutex); 3161 3162 if (ptgt->m_deviceinfo & 3163 (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 3164 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 3165 uchar_t *inq89 = NULL; 3166 int inq89_len = 0x238; 3167 int reallen = 0; 3168 int rval = 0; 3169 struct sata_id *sid = NULL; 3170 char model[SATA_ID_MODEL_LEN + 1]; 3171 char fw[SATA_ID_FW_LEN + 1]; 3172 char *vid, *pid; 3173 3174 mutex_exit(&mpt->m_mutex); 3175 /* 3176 * According SCSI/ATA Translation -2 (SAT-2) revision 01a 3177 * chapter 12.4.2 VPD page 89h includes 512 bytes ATA IDENTIFY 3178 * DEVICE data or ATA IDENTIFY PACKET DEVICE data. 3179 */ 3180 inq89 = kmem_zalloc(inq89_len, KM_SLEEP); 3181 rval = mptsas_inquiry(mpt, ptgt, 0, 0x89, 3182 inq89, inq89_len, &reallen, 1); 3183 3184 if (rval != 0) { 3185 if (inq89 != NULL) { 3186 kmem_free(inq89, inq89_len); 3187 } 3188 3189 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page " 3190 "0x89 for SATA target:%x failed!", ptgt->m_devhdl); 3191 return (DDI_SUCCESS); 3192 } 3193 sid = (void *)(&inq89[60]); 3194 3195 swab(sid->ai_model, model, SATA_ID_MODEL_LEN); 3196 swab(sid->ai_fw, fw, SATA_ID_FW_LEN); 3197 3198 model[SATA_ID_MODEL_LEN] = 0; 3199 fw[SATA_ID_FW_LEN] = 0; 3200 3201 sata_split_model(model, &vid, &pid); 3202 3203 /* 3204 * override SCSA "inquiry-*" properties 3205 */ 3206 if (vid) 3207 (void) scsi_device_prop_update_inqstring(sd, 3208 INQUIRY_VENDOR_ID, vid, strlen(vid)); 3209 if (pid) 3210 (void) scsi_device_prop_update_inqstring(sd, 3211 INQUIRY_PRODUCT_ID, pid, strlen(pid)); 3212 (void) scsi_device_prop_update_inqstring(sd, 3213 INQUIRY_REVISION_ID, fw, strlen(fw)); 3214 3215 if (inq89 != NULL) { 3216 kmem_free(inq89, inq89_len); 3217 } 3218 } else { 3219 mutex_exit(&mpt->m_mutex); 3220 } 3221 3222 return (DDI_SUCCESS); 3223 } 3224 /* 3225 * tran_tgt_free(9E) - target device instance deallocation 3226 */ 3227 static void 3228 mptsas_scsi_tgt_free(dev_info_t *hba_dip, dev_info_t *tgt_dip, 3229 scsi_hba_tran_t *hba_tran, struct scsi_device *sd) 3230 { 3231 #ifndef __lock_lint 3232 _NOTE(ARGUNUSED(hba_dip, tgt_dip, hba_tran, sd)) 3233 #endif 3234 3235 mptsas_tgt_private_t *tgt_private = hba_tran->tran_tgt_private; 3236 3237 if (tgt_private != NULL) { 3238 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t)); 3239 hba_tran->tran_tgt_private = NULL; 3240 } 3241 } 3242 3243 /* 3244 * scsi_pkt handling 3245 * 3246 * Visible to the external world via the transport structure. 3247 */ 3248 3249 /* 3250 * Notes: 3251 * - transport the command to the addressed SCSI target/lun device 3252 * - normal operation is to schedule the command to be transported, 3253 * and return TRAN_ACCEPT if this is successful. 3254 * - if NO_INTR, tran_start must poll device for command completion 3255 */ 3256 static int 3257 mptsas_scsi_start(struct scsi_address *ap, struct scsi_pkt *pkt) 3258 { 3259 #ifndef __lock_lint 3260 _NOTE(ARGUNUSED(ap)) 3261 #endif 3262 mptsas_t *mpt = PKT2MPT(pkt); 3263 mptsas_cmd_t *cmd = PKT2CMD(pkt); 3264 int rval; 3265 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 3266 3267 NDBG1(("mptsas_scsi_start: pkt=0x%p", (void *)pkt)); 3268 ASSERT(ptgt); 3269 if (ptgt == NULL) 3270 return (TRAN_FATAL_ERROR); 3271 3272 /* 3273 * prepare the pkt before taking mutex. 3274 */ 3275 rval = mptsas_prepare_pkt(cmd); 3276 if (rval != TRAN_ACCEPT) { 3277 return (rval); 3278 } 3279 3280 /* 3281 * Send the command to target/lun, however your HBA requires it. 3282 * If busy, return TRAN_BUSY; if there's some other formatting error 3283 * in the packet, return TRAN_BADPKT; otherwise, fall through to the 3284 * return of TRAN_ACCEPT. 3285 * 3286 * Remember that access to shared resources, including the mptsas_t 3287 * data structure and the HBA hardware registers, must be protected 3288 * with mutexes, here and everywhere. 3289 * 3290 * Also remember that at interrupt time, you'll get an argument 3291 * to the interrupt handler which is a pointer to your mptsas_t 3292 * structure; you'll have to remember which commands are outstanding 3293 * and which scsi_pkt is the currently-running command so the 3294 * interrupt handler can refer to the pkt to set completion 3295 * status, call the target driver back through pkt_comp, etc. 3296 * 3297 * If the instance lock is held by other thread, don't spin to wait 3298 * for it. Instead, queue the cmd and next time when the instance lock 3299 * is not held, accept all the queued cmd. A extra tx_waitq is 3300 * introduced to protect the queue. 3301 * 3302 * The polled cmd will not be queud and accepted as usual. 3303 * 3304 * Under the tx_waitq mutex, record whether a thread is draining 3305 * the tx_waitq. An IO requesting thread that finds the instance 3306 * mutex contended appends to the tx_waitq and while holding the 3307 * tx_wait mutex, if the draining flag is not set, sets it and then 3308 * proceeds to spin for the instance mutex. This scheme ensures that 3309 * the last cmd in a burst be processed. 3310 * 3311 * we enable this feature only when the helper threads are enabled, 3312 * at which we think the loads are heavy. 3313 * 3314 * per instance mutex m_tx_waitq_mutex is introduced to protect the 3315 * m_tx_waitqtail, m_tx_waitq, m_tx_draining. 3316 */ 3317 3318 if (mpt->m_doneq_thread_n) { 3319 if (mutex_tryenter(&mpt->m_mutex) != 0) { 3320 rval = mptsas_accept_txwq_and_pkt(mpt, cmd); 3321 mutex_exit(&mpt->m_mutex); 3322 } else if (cmd->cmd_pkt_flags & FLAG_NOINTR) { 3323 mutex_enter(&mpt->m_mutex); 3324 rval = mptsas_accept_txwq_and_pkt(mpt, cmd); 3325 mutex_exit(&mpt->m_mutex); 3326 } else { 3327 mutex_enter(&mpt->m_tx_waitq_mutex); 3328 /* 3329 * ptgt->m_dr_flag is protected by m_mutex or 3330 * m_tx_waitq_mutex. In this case, m_tx_waitq_mutex 3331 * is acquired. 3332 */ 3333 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) { 3334 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) { 3335 /* 3336 * The command should be allowed to 3337 * retry by returning TRAN_BUSY to 3338 * to stall the I/O's which come from 3339 * scsi_vhci since the device/path is 3340 * in unstable state now. 3341 */ 3342 mutex_exit(&mpt->m_tx_waitq_mutex); 3343 return (TRAN_BUSY); 3344 } else { 3345 /* 3346 * The device is offline, just fail the 3347 * command by returning 3348 * TRAN_FATAL_ERROR. 3349 */ 3350 mutex_exit(&mpt->m_tx_waitq_mutex); 3351 return (TRAN_FATAL_ERROR); 3352 } 3353 } 3354 if (mpt->m_tx_draining) { 3355 cmd->cmd_flags |= CFLAG_TXQ; 3356 *mpt->m_tx_waitqtail = cmd; 3357 mpt->m_tx_waitqtail = &cmd->cmd_linkp; 3358 mutex_exit(&mpt->m_tx_waitq_mutex); 3359 } else { /* drain the queue */ 3360 mpt->m_tx_draining = 1; 3361 mutex_exit(&mpt->m_tx_waitq_mutex); 3362 mutex_enter(&mpt->m_mutex); 3363 rval = mptsas_accept_txwq_and_pkt(mpt, cmd); 3364 mutex_exit(&mpt->m_mutex); 3365 } 3366 } 3367 } else { 3368 mutex_enter(&mpt->m_mutex); 3369 /* 3370 * ptgt->m_dr_flag is protected by m_mutex or m_tx_waitq_mutex 3371 * in this case, m_mutex is acquired. 3372 */ 3373 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) { 3374 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) { 3375 /* 3376 * commands should be allowed to retry by 3377 * returning TRAN_BUSY to stall the I/O's 3378 * which come from scsi_vhci since the device/ 3379 * path is in unstable state now. 3380 */ 3381 mutex_exit(&mpt->m_mutex); 3382 return (TRAN_BUSY); 3383 } else { 3384 /* 3385 * The device is offline, just fail the 3386 * command by returning TRAN_FATAL_ERROR. 3387 */ 3388 mutex_exit(&mpt->m_mutex); 3389 return (TRAN_FATAL_ERROR); 3390 } 3391 } 3392 rval = mptsas_accept_pkt(mpt, cmd); 3393 mutex_exit(&mpt->m_mutex); 3394 } 3395 3396 return (rval); 3397 } 3398 3399 /* 3400 * Accept all the queued cmds(if any) before accept the current one. 3401 */ 3402 static int 3403 mptsas_accept_txwq_and_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd) 3404 { 3405 int rval; 3406 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 3407 3408 ASSERT(mutex_owned(&mpt->m_mutex)); 3409 /* 3410 * The call to mptsas_accept_tx_waitq() must always be performed 3411 * because that is where mpt->m_tx_draining is cleared. 3412 */ 3413 mutex_enter(&mpt->m_tx_waitq_mutex); 3414 mptsas_accept_tx_waitq(mpt); 3415 mutex_exit(&mpt->m_tx_waitq_mutex); 3416 /* 3417 * ptgt->m_dr_flag is protected by m_mutex or m_tx_waitq_mutex 3418 * in this case, m_mutex is acquired. 3419 */ 3420 if (ptgt->m_dr_flag == MPTSAS_DR_INTRANSITION) { 3421 if (cmd->cmd_pkt_flags & FLAG_NOQUEUE) { 3422 /* 3423 * The command should be allowed to retry by returning 3424 * TRAN_BUSY to stall the I/O's which come from 3425 * scsi_vhci since the device/path is in unstable state 3426 * now. 3427 */ 3428 return (TRAN_BUSY); 3429 } else { 3430 /* 3431 * The device is offline, just fail the command by 3432 * return TRAN_FATAL_ERROR. 3433 */ 3434 return (TRAN_FATAL_ERROR); 3435 } 3436 } 3437 rval = mptsas_accept_pkt(mpt, cmd); 3438 3439 return (rval); 3440 } 3441 3442 static int 3443 mptsas_accept_pkt(mptsas_t *mpt, mptsas_cmd_t *cmd) 3444 { 3445 int rval = TRAN_ACCEPT; 3446 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 3447 3448 NDBG1(("mptsas_accept_pkt: cmd=0x%p", (void *)cmd)); 3449 3450 ASSERT(mutex_owned(&mpt->m_mutex)); 3451 3452 if ((cmd->cmd_flags & CFLAG_PREPARED) == 0) { 3453 rval = mptsas_prepare_pkt(cmd); 3454 if (rval != TRAN_ACCEPT) { 3455 cmd->cmd_flags &= ~CFLAG_TRANFLAG; 3456 return (rval); 3457 } 3458 } 3459 3460 /* 3461 * reset the throttle if we were draining 3462 */ 3463 if ((ptgt->m_t_ncmds == 0) && 3464 (ptgt->m_t_throttle == DRAIN_THROTTLE)) { 3465 NDBG23(("reset throttle")); 3466 ASSERT(ptgt->m_reset_delay == 0); 3467 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 3468 } 3469 3470 /* 3471 * If HBA is being reset, the DevHandles are being re-initialized, 3472 * which means that they could be invalid even if the target is still 3473 * attached. Check if being reset and if DevHandle is being 3474 * re-initialized. If this is the case, return BUSY so the I/O can be 3475 * retried later. 3476 */ 3477 if ((ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) && mpt->m_in_reset) { 3478 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET); 3479 if (cmd->cmd_flags & CFLAG_TXQ) { 3480 mptsas_doneq_add(mpt, cmd); 3481 mptsas_doneq_empty(mpt); 3482 return (rval); 3483 } else { 3484 return (TRAN_BUSY); 3485 } 3486 } 3487 3488 /* 3489 * If device handle has already been invalidated, just 3490 * fail the command. In theory, command from scsi_vhci 3491 * client is impossible send down command with invalid 3492 * devhdl since devhdl is set after path offline, target 3493 * driver is not suppose to select a offlined path. 3494 */ 3495 if (ptgt->m_devhdl == MPTSAS_INVALID_DEVHDL) { 3496 NDBG3(("rejecting command, it might because invalid devhdl " 3497 "request.")); 3498 mptsas_set_pkt_reason(mpt, cmd, CMD_DEV_GONE, STAT_TERMINATED); 3499 if (cmd->cmd_flags & CFLAG_TXQ) { 3500 mptsas_doneq_add(mpt, cmd); 3501 mptsas_doneq_empty(mpt); 3502 return (rval); 3503 } else { 3504 return (TRAN_FATAL_ERROR); 3505 } 3506 } 3507 /* 3508 * The first case is the normal case. mpt gets a command from the 3509 * target driver and starts it. 3510 * Since SMID 0 is reserved and the TM slot is reserved, the actual max 3511 * commands is m_max_requests - 2. 3512 */ 3513 if ((mpt->m_ncmds <= (mpt->m_max_requests - 2)) && 3514 (ptgt->m_t_throttle > HOLD_THROTTLE) && 3515 (ptgt->m_t_ncmds < ptgt->m_t_throttle) && 3516 (ptgt->m_reset_delay == 0) && 3517 (ptgt->m_t_nwait == 0) && 3518 ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0)) { 3519 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 3520 (void) mptsas_start_cmd(mpt, cmd); 3521 } else { 3522 mptsas_waitq_add(mpt, cmd); 3523 } 3524 } else { 3525 /* 3526 * Add this pkt to the work queue 3527 */ 3528 mptsas_waitq_add(mpt, cmd); 3529 3530 if (cmd->cmd_pkt_flags & FLAG_NOINTR) { 3531 (void) mptsas_poll(mpt, cmd, MPTSAS_POLL_TIME); 3532 3533 /* 3534 * Only flush the doneq if this is not a TM 3535 * cmd. For TM cmds the flushing of the 3536 * doneq will be done in those routines. 3537 */ 3538 if ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) { 3539 mptsas_doneq_empty(mpt); 3540 } 3541 } 3542 } 3543 return (rval); 3544 } 3545 3546 int 3547 mptsas_save_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd) 3548 { 3549 mptsas_slots_t *slots = mpt->m_active; 3550 uint_t slot, start_rotor; 3551 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 3552 3553 ASSERT(MUTEX_HELD(&mpt->m_mutex)); 3554 3555 /* 3556 * Account for reserved TM request slot and reserved SMID of 0. 3557 */ 3558 ASSERT(slots->m_n_normal == (mpt->m_max_requests - 2)); 3559 3560 /* 3561 * Find the next available slot, beginning at m_rotor. If no slot is 3562 * available, we'll return FALSE to indicate that. This mechanism 3563 * considers only the normal slots, not the reserved slot 0 nor the 3564 * task management slot m_n_normal + 1. The rotor is left to point to 3565 * the normal slot after the one we select, unless we select the last 3566 * normal slot in which case it returns to slot 1. 3567 */ 3568 start_rotor = slots->m_rotor; 3569 do { 3570 slot = slots->m_rotor++; 3571 if (slots->m_rotor > slots->m_n_normal) 3572 slots->m_rotor = 1; 3573 3574 if (slots->m_rotor == start_rotor) 3575 break; 3576 } while (slots->m_slot[slot] != NULL); 3577 3578 if (slots->m_slot[slot] != NULL) 3579 return (FALSE); 3580 3581 ASSERT(slot != 0 && slot <= slots->m_n_normal); 3582 3583 cmd->cmd_slot = slot; 3584 slots->m_slot[slot] = cmd; 3585 mpt->m_ncmds++; 3586 3587 /* 3588 * only increment per target ncmds if this is not a 3589 * command that has no target associated with it (i.e. a 3590 * event acknoledgment) 3591 */ 3592 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) { 3593 /* 3594 * Expiration time is set in mptsas_start_cmd 3595 */ 3596 ptgt->m_t_ncmds++; 3597 cmd->cmd_active_expiration = 0; 3598 } else { 3599 /* 3600 * Initialize expiration time for passthrough commands, 3601 */ 3602 cmd->cmd_active_expiration = gethrtime() + 3603 (hrtime_t)cmd->cmd_pkt->pkt_time * NANOSEC; 3604 } 3605 return (TRUE); 3606 } 3607 3608 /* 3609 * prepare the pkt: 3610 * the pkt may have been resubmitted or just reused so 3611 * initialize some fields and do some checks. 3612 */ 3613 static int 3614 mptsas_prepare_pkt(mptsas_cmd_t *cmd) 3615 { 3616 struct scsi_pkt *pkt = CMD2PKT(cmd); 3617 3618 NDBG1(("mptsas_prepare_pkt: cmd=0x%p", (void *)cmd)); 3619 3620 /* 3621 * Reinitialize some fields that need it; the packet may 3622 * have been resubmitted 3623 */ 3624 pkt->pkt_reason = CMD_CMPLT; 3625 pkt->pkt_state = 0; 3626 pkt->pkt_statistics = 0; 3627 pkt->pkt_resid = 0; 3628 cmd->cmd_age = 0; 3629 cmd->cmd_pkt_flags = pkt->pkt_flags; 3630 3631 /* 3632 * zero status byte. 3633 */ 3634 *(pkt->pkt_scbp) = 0; 3635 3636 if (cmd->cmd_flags & CFLAG_DMAVALID) { 3637 pkt->pkt_resid = cmd->cmd_dmacount; 3638 3639 /* 3640 * consistent packets need to be sync'ed first 3641 * (only for data going out) 3642 */ 3643 if ((cmd->cmd_flags & CFLAG_CMDIOPB) && 3644 (cmd->cmd_flags & CFLAG_DMASEND)) { 3645 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0, 3646 DDI_DMA_SYNC_FORDEV); 3647 } 3648 } 3649 3650 cmd->cmd_flags = 3651 (cmd->cmd_flags & ~(CFLAG_TRANFLAG)) | 3652 CFLAG_PREPARED | CFLAG_IN_TRANSPORT; 3653 3654 return (TRAN_ACCEPT); 3655 } 3656 3657 /* 3658 * tran_init_pkt(9E) - allocate scsi_pkt(9S) for command 3659 * 3660 * One of three possibilities: 3661 * - allocate scsi_pkt 3662 * - allocate scsi_pkt and DMA resources 3663 * - allocate DMA resources to an already-allocated pkt 3664 */ 3665 static struct scsi_pkt * 3666 mptsas_scsi_init_pkt(struct scsi_address *ap, struct scsi_pkt *pkt, 3667 struct buf *bp, int cmdlen, int statuslen, int tgtlen, int flags, 3668 int (*callback)(), caddr_t arg) 3669 { 3670 mptsas_cmd_t *cmd, *new_cmd; 3671 mptsas_t *mpt = ADDR2MPT(ap); 3672 uint_t oldcookiec; 3673 mptsas_target_t *ptgt = NULL; 3674 int rval; 3675 mptsas_tgt_private_t *tgt_private; 3676 int kf; 3677 3678 kf = (callback == SLEEP_FUNC)? KM_SLEEP: KM_NOSLEEP; 3679 3680 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran-> 3681 tran_tgt_private; 3682 ASSERT(tgt_private != NULL); 3683 if (tgt_private == NULL) { 3684 return (NULL); 3685 } 3686 ptgt = tgt_private->t_private; 3687 ASSERT(ptgt != NULL); 3688 if (ptgt == NULL) 3689 return (NULL); 3690 ap->a_target = ptgt->m_devhdl; 3691 ap->a_lun = tgt_private->t_lun; 3692 3693 ASSERT(callback == NULL_FUNC || callback == SLEEP_FUNC); 3694 #ifdef MPTSAS_TEST_EXTRN_ALLOC 3695 statuslen *= 100; tgtlen *= 4; 3696 #endif 3697 NDBG3(("mptsas_scsi_init_pkt:\n" 3698 "\ttgt=%d in=0x%p bp=0x%p clen=%d slen=%d tlen=%d flags=%x", 3699 ap->a_target, (void *)pkt, (void *)bp, 3700 cmdlen, statuslen, tgtlen, flags)); 3701 3702 /* 3703 * Allocate the new packet. 3704 */ 3705 if (pkt == NULL) { 3706 ddi_dma_handle_t save_dma_handle; 3707 3708 cmd = kmem_cache_alloc(mpt->m_kmem_cache, kf); 3709 if (cmd == NULL) 3710 return (NULL); 3711 3712 save_dma_handle = cmd->cmd_dmahandle; 3713 bzero(cmd, sizeof (*cmd) + scsi_pkt_size()); 3714 cmd->cmd_dmahandle = save_dma_handle; 3715 3716 pkt = (void *)((uchar_t *)cmd + 3717 sizeof (struct mptsas_cmd)); 3718 pkt->pkt_ha_private = (opaque_t)cmd; 3719 pkt->pkt_address = *ap; 3720 pkt->pkt_private = (opaque_t)cmd->cmd_pkt_private; 3721 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb; 3722 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb; 3723 cmd->cmd_pkt = (struct scsi_pkt *)pkt; 3724 cmd->cmd_cdblen = (uchar_t)cmdlen; 3725 cmd->cmd_scblen = statuslen; 3726 cmd->cmd_rqslen = SENSE_LENGTH; 3727 cmd->cmd_tgt_addr = ptgt; 3728 3729 if ((cmdlen > sizeof (cmd->cmd_cdb)) || 3730 (tgtlen > PKT_PRIV_LEN) || 3731 (statuslen > EXTCMDS_STATUS_SIZE)) { 3732 int failure; 3733 3734 /* 3735 * We are going to allocate external packet space which 3736 * might include the sense data buffer for DMA so we 3737 * need to increase the reference counter here. In a 3738 * case the HBA is in reset we just simply free the 3739 * allocated packet and bail out. 3740 */ 3741 mutex_enter(&mpt->m_mutex); 3742 if (mpt->m_in_reset) { 3743 mutex_exit(&mpt->m_mutex); 3744 3745 cmd->cmd_flags = CFLAG_FREE; 3746 kmem_cache_free(mpt->m_kmem_cache, cmd); 3747 return (NULL); 3748 } 3749 mpt->m_extreq_sense_refcount++; 3750 ASSERT(mpt->m_extreq_sense_refcount > 0); 3751 mutex_exit(&mpt->m_mutex); 3752 3753 /* 3754 * if extern alloc fails, all will be 3755 * deallocated, including cmd 3756 */ 3757 failure = mptsas_pkt_alloc_extern(mpt, cmd, 3758 cmdlen, tgtlen, statuslen, kf); 3759 3760 if (failure != 0 || cmd->cmd_extrqslen == 0) { 3761 /* 3762 * If the external packet space allocation 3763 * failed, or we didn't allocate the sense 3764 * data buffer for DMA we need to decrease the 3765 * reference counter. 3766 */ 3767 mutex_enter(&mpt->m_mutex); 3768 ASSERT(mpt->m_extreq_sense_refcount > 0); 3769 mpt->m_extreq_sense_refcount--; 3770 if (mpt->m_extreq_sense_refcount == 0) 3771 cv_broadcast( 3772 &mpt->m_extreq_sense_refcount_cv); 3773 mutex_exit(&mpt->m_mutex); 3774 3775 if (failure != 0) { 3776 /* 3777 * if extern allocation fails, it will 3778 * deallocate the new pkt as well 3779 */ 3780 return (NULL); 3781 } 3782 } 3783 } 3784 new_cmd = cmd; 3785 3786 } else { 3787 cmd = PKT2CMD(pkt); 3788 new_cmd = NULL; 3789 } 3790 3791 3792 /* grab cmd->cmd_cookiec here as oldcookiec */ 3793 3794 oldcookiec = cmd->cmd_cookiec; 3795 3796 /* 3797 * If the dma was broken up into PARTIAL transfers cmd_nwin will be 3798 * greater than 0 and we'll need to grab the next dma window 3799 */ 3800 /* 3801 * SLM-not doing extra command frame right now; may add later 3802 */ 3803 3804 if (cmd->cmd_nwin > 0) { 3805 3806 /* 3807 * Make sure we havn't gone past the the total number 3808 * of windows 3809 */ 3810 if (++cmd->cmd_winindex >= cmd->cmd_nwin) { 3811 return (NULL); 3812 } 3813 if (ddi_dma_getwin(cmd->cmd_dmahandle, cmd->cmd_winindex, 3814 &cmd->cmd_dma_offset, &cmd->cmd_dma_len, 3815 &cmd->cmd_cookie, &cmd->cmd_cookiec) == DDI_FAILURE) { 3816 return (NULL); 3817 } 3818 goto get_dma_cookies; 3819 } 3820 3821 3822 if (flags & PKT_XARQ) { 3823 cmd->cmd_flags |= CFLAG_XARQ; 3824 } 3825 3826 /* 3827 * DMA resource allocation. This version assumes your 3828 * HBA has some sort of bus-mastering or onboard DMA capability, with a 3829 * scatter-gather list of length MPTSAS_MAX_DMA_SEGS, as given in the 3830 * ddi_dma_attr_t structure and passed to scsi_impl_dmaget. 3831 */ 3832 if (bp && (bp->b_bcount != 0) && 3833 (cmd->cmd_flags & CFLAG_DMAVALID) == 0) { 3834 3835 int cnt, dma_flags; 3836 mptti_t *dmap; /* ptr to the S/G list */ 3837 3838 /* 3839 * Set up DMA memory and position to the next DMA segment. 3840 */ 3841 ASSERT(cmd->cmd_dmahandle != NULL); 3842 3843 if (bp->b_flags & B_READ) { 3844 dma_flags = DDI_DMA_READ; 3845 cmd->cmd_flags &= ~CFLAG_DMASEND; 3846 } else { 3847 dma_flags = DDI_DMA_WRITE; 3848 cmd->cmd_flags |= CFLAG_DMASEND; 3849 } 3850 if (flags & PKT_CONSISTENT) { 3851 cmd->cmd_flags |= CFLAG_CMDIOPB; 3852 dma_flags |= DDI_DMA_CONSISTENT; 3853 } 3854 3855 if (flags & PKT_DMA_PARTIAL) { 3856 dma_flags |= DDI_DMA_PARTIAL; 3857 } 3858 3859 /* 3860 * workaround for byte hole issue on psycho and 3861 * schizo pre 2.1 3862 */ 3863 if ((bp->b_flags & B_READ) && ((bp->b_flags & 3864 (B_PAGEIO|B_REMAPPED)) != B_PAGEIO) && 3865 ((uintptr_t)bp->b_un.b_addr & 0x7)) { 3866 dma_flags |= DDI_DMA_CONSISTENT; 3867 } 3868 3869 rval = ddi_dma_buf_bind_handle(cmd->cmd_dmahandle, bp, 3870 dma_flags, callback, arg, 3871 &cmd->cmd_cookie, &cmd->cmd_cookiec); 3872 if (rval == DDI_DMA_PARTIAL_MAP) { 3873 (void) ddi_dma_numwin(cmd->cmd_dmahandle, 3874 &cmd->cmd_nwin); 3875 cmd->cmd_winindex = 0; 3876 (void) ddi_dma_getwin(cmd->cmd_dmahandle, 3877 cmd->cmd_winindex, &cmd->cmd_dma_offset, 3878 &cmd->cmd_dma_len, &cmd->cmd_cookie, 3879 &cmd->cmd_cookiec); 3880 } else if (rval && (rval != DDI_DMA_MAPPED)) { 3881 switch (rval) { 3882 case DDI_DMA_NORESOURCES: 3883 bioerror(bp, 0); 3884 break; 3885 case DDI_DMA_BADATTR: 3886 case DDI_DMA_NOMAPPING: 3887 bioerror(bp, EFAULT); 3888 break; 3889 case DDI_DMA_TOOBIG: 3890 default: 3891 bioerror(bp, EINVAL); 3892 break; 3893 } 3894 cmd->cmd_flags &= ~CFLAG_DMAVALID; 3895 if (new_cmd) { 3896 mptsas_scsi_destroy_pkt(ap, pkt); 3897 } 3898 return ((struct scsi_pkt *)NULL); 3899 } 3900 3901 get_dma_cookies: 3902 cmd->cmd_flags |= CFLAG_DMAVALID; 3903 ASSERT(cmd->cmd_cookiec > 0); 3904 3905 if (cmd->cmd_cookiec > MPTSAS_MAX_CMD_SEGS) { 3906 mptsas_log(mpt, CE_NOTE, "large cookiec received %d\n", 3907 cmd->cmd_cookiec); 3908 bioerror(bp, EINVAL); 3909 if (new_cmd) { 3910 mptsas_scsi_destroy_pkt(ap, pkt); 3911 } 3912 return ((struct scsi_pkt *)NULL); 3913 } 3914 3915 /* 3916 * Allocate extra SGL buffer if needed. 3917 */ 3918 if ((cmd->cmd_cookiec > MPTSAS_MAX_FRAME_SGES64(mpt)) && 3919 (cmd->cmd_extra_frames == NULL)) { 3920 if (mptsas_alloc_extra_sgl_frame(mpt, cmd) == 3921 DDI_FAILURE) { 3922 mptsas_log(mpt, CE_WARN, "MPT SGL mem alloc " 3923 "failed"); 3924 bioerror(bp, ENOMEM); 3925 if (new_cmd) { 3926 mptsas_scsi_destroy_pkt(ap, pkt); 3927 } 3928 return ((struct scsi_pkt *)NULL); 3929 } 3930 } 3931 3932 /* 3933 * Always use scatter-gather transfer 3934 * Use the loop below to store physical addresses of 3935 * DMA segments, from the DMA cookies, into your HBA's 3936 * scatter-gather list. 3937 * We need to ensure we have enough kmem alloc'd 3938 * for the sg entries since we are no longer using an 3939 * array inside mptsas_cmd_t. 3940 * 3941 * We check cmd->cmd_cookiec against oldcookiec so 3942 * the scatter-gather list is correctly allocated 3943 */ 3944 3945 if (oldcookiec != cmd->cmd_cookiec) { 3946 if (cmd->cmd_sg != (mptti_t *)NULL) { 3947 kmem_free(cmd->cmd_sg, sizeof (mptti_t) * 3948 oldcookiec); 3949 cmd->cmd_sg = NULL; 3950 } 3951 } 3952 3953 if (cmd->cmd_sg == (mptti_t *)NULL) { 3954 cmd->cmd_sg = kmem_alloc((size_t)(sizeof (mptti_t)* 3955 cmd->cmd_cookiec), kf); 3956 3957 if (cmd->cmd_sg == (mptti_t *)NULL) { 3958 mptsas_log(mpt, CE_WARN, 3959 "unable to kmem_alloc enough memory " 3960 "for scatter/gather list"); 3961 /* 3962 * if we have an ENOMEM condition we need to behave 3963 * the same way as the rest of this routine 3964 */ 3965 3966 bioerror(bp, ENOMEM); 3967 if (new_cmd) { 3968 mptsas_scsi_destroy_pkt(ap, pkt); 3969 } 3970 return ((struct scsi_pkt *)NULL); 3971 } 3972 } 3973 3974 dmap = cmd->cmd_sg; 3975 3976 ASSERT(cmd->cmd_cookie.dmac_size != 0); 3977 3978 /* 3979 * store the first segment into the S/G list 3980 */ 3981 dmap->count = cmd->cmd_cookie.dmac_size; 3982 dmap->addr.address64.Low = (uint32_t) 3983 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull); 3984 dmap->addr.address64.High = (uint32_t) 3985 (cmd->cmd_cookie.dmac_laddress >> 32); 3986 3987 /* 3988 * dmacount counts the size of the dma for this window 3989 * (if partial dma is being used). totaldmacount 3990 * keeps track of the total amount of dma we have 3991 * transferred for all the windows (needed to calculate 3992 * the resid value below). 3993 */ 3994 cmd->cmd_dmacount = cmd->cmd_cookie.dmac_size; 3995 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size; 3996 3997 /* 3998 * We already stored the first DMA scatter gather segment, 3999 * start at 1 if we need to store more. 4000 */ 4001 for (cnt = 1; cnt < cmd->cmd_cookiec; cnt++) { 4002 /* 4003 * Get next DMA cookie 4004 */ 4005 ddi_dma_nextcookie(cmd->cmd_dmahandle, 4006 &cmd->cmd_cookie); 4007 dmap++; 4008 4009 cmd->cmd_dmacount += cmd->cmd_cookie.dmac_size; 4010 cmd->cmd_totaldmacount += cmd->cmd_cookie.dmac_size; 4011 4012 /* 4013 * store the segment parms into the S/G list 4014 */ 4015 dmap->count = cmd->cmd_cookie.dmac_size; 4016 dmap->addr.address64.Low = (uint32_t) 4017 (cmd->cmd_cookie.dmac_laddress & 0xffffffffull); 4018 dmap->addr.address64.High = (uint32_t) 4019 (cmd->cmd_cookie.dmac_laddress >> 32); 4020 } 4021 4022 /* 4023 * If this was partially allocated we set the resid 4024 * the amount of data NOT transferred in this window 4025 * If there is only one window, the resid will be 0 4026 */ 4027 pkt->pkt_resid = (bp->b_bcount - cmd->cmd_totaldmacount); 4028 NDBG3(("mptsas_scsi_init_pkt: cmd_dmacount=%d.", 4029 cmd->cmd_dmacount)); 4030 } 4031 return (pkt); 4032 } 4033 4034 /* 4035 * tran_destroy_pkt(9E) - scsi_pkt(9s) deallocation 4036 * 4037 * Notes: 4038 * - also frees DMA resources if allocated 4039 * - implicit DMA synchonization 4040 */ 4041 static void 4042 mptsas_scsi_destroy_pkt(struct scsi_address *ap, struct scsi_pkt *pkt) 4043 { 4044 mptsas_cmd_t *cmd = PKT2CMD(pkt); 4045 mptsas_t *mpt = ADDR2MPT(ap); 4046 4047 NDBG3(("mptsas_scsi_destroy_pkt: target=%d pkt=0x%p", 4048 ap->a_target, (void *)pkt)); 4049 4050 if (cmd->cmd_flags & CFLAG_DMAVALID) { 4051 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle); 4052 cmd->cmd_flags &= ~CFLAG_DMAVALID; 4053 } 4054 4055 if (cmd->cmd_sg) { 4056 kmem_free(cmd->cmd_sg, sizeof (mptti_t) * cmd->cmd_cookiec); 4057 cmd->cmd_sg = NULL; 4058 } 4059 4060 mptsas_free_extra_sgl_frame(mpt, cmd); 4061 4062 if ((cmd->cmd_flags & 4063 (CFLAG_FREE | CFLAG_CDBEXTERN | CFLAG_PRIVEXTERN | 4064 CFLAG_SCBEXTERN)) == 0) { 4065 cmd->cmd_flags = CFLAG_FREE; 4066 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd); 4067 } else { 4068 boolean_t extrqslen = cmd->cmd_extrqslen != 0; 4069 4070 mptsas_pkt_destroy_extern(mpt, cmd); 4071 4072 /* 4073 * If the packet had the sense data buffer for DMA allocated we 4074 * need to decrease the reference counter. 4075 */ 4076 if (extrqslen) { 4077 mutex_enter(&mpt->m_mutex); 4078 ASSERT(mpt->m_extreq_sense_refcount > 0); 4079 mpt->m_extreq_sense_refcount--; 4080 if (mpt->m_extreq_sense_refcount == 0) 4081 cv_broadcast(&mpt->m_extreq_sense_refcount_cv); 4082 mutex_exit(&mpt->m_mutex); 4083 } 4084 } 4085 } 4086 4087 /* 4088 * kmem cache constructor and destructor: 4089 * When constructing, we bzero the cmd and allocate the dma handle 4090 * When destructing, just free the dma handle 4091 */ 4092 static int 4093 mptsas_kmem_cache_constructor(void *buf, void *cdrarg, int kmflags) 4094 { 4095 mptsas_cmd_t *cmd = buf; 4096 mptsas_t *mpt = cdrarg; 4097 int (*callback)(caddr_t); 4098 4099 callback = (kmflags == KM_SLEEP)? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT; 4100 4101 NDBG4(("mptsas_kmem_cache_constructor")); 4102 4103 /* 4104 * allocate a dma handle 4105 */ 4106 if ((ddi_dma_alloc_handle(mpt->m_dip, &mpt->m_io_dma_attr, callback, 4107 NULL, &cmd->cmd_dmahandle)) != DDI_SUCCESS) { 4108 cmd->cmd_dmahandle = NULL; 4109 return (-1); 4110 } 4111 return (0); 4112 } 4113 4114 static void 4115 mptsas_kmem_cache_destructor(void *buf, void *cdrarg) 4116 { 4117 #ifndef __lock_lint 4118 _NOTE(ARGUNUSED(cdrarg)) 4119 #endif 4120 mptsas_cmd_t *cmd = buf; 4121 4122 NDBG4(("mptsas_kmem_cache_destructor")); 4123 4124 if (cmd->cmd_dmahandle) { 4125 ddi_dma_free_handle(&cmd->cmd_dmahandle); 4126 cmd->cmd_dmahandle = NULL; 4127 } 4128 } 4129 4130 static int 4131 mptsas_cache_frames_constructor(void *buf, void *cdrarg, int kmflags) 4132 { 4133 mptsas_cache_frames_t *p = buf; 4134 mptsas_t *mpt = cdrarg; 4135 ddi_dma_attr_t frame_dma_attr; 4136 size_t mem_size, alloc_len; 4137 ddi_dma_cookie_t cookie; 4138 uint_t ncookie; 4139 int (*callback)(caddr_t) = (kmflags == KM_SLEEP) 4140 ? DDI_DMA_SLEEP: DDI_DMA_DONTWAIT; 4141 4142 frame_dma_attr = mpt->m_msg_dma_attr; 4143 frame_dma_attr.dma_attr_align = 0x10; 4144 frame_dma_attr.dma_attr_sgllen = 1; 4145 4146 if (ddi_dma_alloc_handle(mpt->m_dip, &frame_dma_attr, callback, NULL, 4147 &p->m_dma_hdl) != DDI_SUCCESS) { 4148 mptsas_log(mpt, CE_WARN, "Unable to allocate dma handle for" 4149 " extra SGL."); 4150 return (DDI_FAILURE); 4151 } 4152 4153 mem_size = (mpt->m_max_request_frames - 1) * mpt->m_req_frame_size; 4154 4155 if (ddi_dma_mem_alloc(p->m_dma_hdl, mem_size, &mpt->m_dev_acc_attr, 4156 DDI_DMA_CONSISTENT, callback, NULL, (caddr_t *)&p->m_frames_addr, 4157 &alloc_len, &p->m_acc_hdl) != DDI_SUCCESS) { 4158 ddi_dma_free_handle(&p->m_dma_hdl); 4159 p->m_dma_hdl = NULL; 4160 mptsas_log(mpt, CE_WARN, "Unable to allocate dma memory for" 4161 " extra SGL."); 4162 return (DDI_FAILURE); 4163 } 4164 4165 if (ddi_dma_addr_bind_handle(p->m_dma_hdl, NULL, p->m_frames_addr, 4166 alloc_len, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, callback, NULL, 4167 &cookie, &ncookie) != DDI_DMA_MAPPED) { 4168 (void) ddi_dma_mem_free(&p->m_acc_hdl); 4169 ddi_dma_free_handle(&p->m_dma_hdl); 4170 p->m_dma_hdl = NULL; 4171 mptsas_log(mpt, CE_WARN, "Unable to bind DMA resources for" 4172 " extra SGL"); 4173 return (DDI_FAILURE); 4174 } 4175 4176 /* 4177 * Store the SGL memory address. This chip uses this 4178 * address to dma to and from the driver. The second 4179 * address is the address mpt uses to fill in the SGL. 4180 */ 4181 p->m_phys_addr = cookie.dmac_laddress; 4182 4183 return (DDI_SUCCESS); 4184 } 4185 4186 static void 4187 mptsas_cache_frames_destructor(void *buf, void *cdrarg) 4188 { 4189 #ifndef __lock_lint 4190 _NOTE(ARGUNUSED(cdrarg)) 4191 #endif 4192 mptsas_cache_frames_t *p = buf; 4193 if (p->m_dma_hdl != NULL) { 4194 (void) ddi_dma_unbind_handle(p->m_dma_hdl); 4195 (void) ddi_dma_mem_free(&p->m_acc_hdl); 4196 ddi_dma_free_handle(&p->m_dma_hdl); 4197 p->m_phys_addr = NULL; 4198 p->m_frames_addr = NULL; 4199 p->m_dma_hdl = NULL; 4200 p->m_acc_hdl = NULL; 4201 } 4202 4203 } 4204 4205 /* 4206 * Figure out if we need to use a different method for the request 4207 * sense buffer and allocate from the map if necessary. 4208 */ 4209 static boolean_t 4210 mptsas_cmdarqsize(mptsas_t *mpt, mptsas_cmd_t *cmd, size_t senselength, int kf) 4211 { 4212 if (senselength > mpt->m_req_sense_size) { 4213 unsigned long i; 4214 4215 /* Sense length is limited to an 8 bit value in MPI Spec. */ 4216 if (senselength > 255) 4217 senselength = 255; 4218 cmd->cmd_extrqschunks = (senselength + 4219 (mpt->m_req_sense_size - 1))/mpt->m_req_sense_size; 4220 i = (kf == KM_SLEEP ? rmalloc_wait : rmalloc) 4221 (mpt->m_erqsense_map, cmd->cmd_extrqschunks); 4222 4223 if (i == 0) 4224 return (B_FALSE); 4225 4226 cmd->cmd_extrqslen = (uint16_t)senselength; 4227 cmd->cmd_extrqsidx = i - 1; 4228 cmd->cmd_arq_buf = mpt->m_extreq_sense + 4229 (cmd->cmd_extrqsidx * mpt->m_req_sense_size); 4230 } else { 4231 cmd->cmd_rqslen = (uchar_t)senselength; 4232 } 4233 4234 return (B_TRUE); 4235 } 4236 4237 /* 4238 * allocate and deallocate external pkt space (ie. not part of mptsas_cmd) 4239 * for non-standard length cdb, pkt_private, status areas 4240 * if allocation fails, then deallocate all external space and the pkt 4241 */ 4242 /* ARGSUSED */ 4243 static int 4244 mptsas_pkt_alloc_extern(mptsas_t *mpt, mptsas_cmd_t *cmd, 4245 int cmdlen, int tgtlen, int statuslen, int kf) 4246 { 4247 caddr_t cdbp, scbp, tgt; 4248 4249 NDBG3(("mptsas_pkt_alloc_extern: " 4250 "cmd=0x%p cmdlen=%d tgtlen=%d statuslen=%d kf=%x", 4251 (void *)cmd, cmdlen, tgtlen, statuslen, kf)); 4252 4253 tgt = cdbp = scbp = NULL; 4254 cmd->cmd_scblen = statuslen; 4255 cmd->cmd_privlen = (uchar_t)tgtlen; 4256 4257 if (cmdlen > sizeof (cmd->cmd_cdb)) { 4258 if ((cdbp = kmem_zalloc((size_t)cmdlen, kf)) == NULL) { 4259 goto fail; 4260 } 4261 cmd->cmd_pkt->pkt_cdbp = (opaque_t)cdbp; 4262 cmd->cmd_flags |= CFLAG_CDBEXTERN; 4263 } 4264 if (tgtlen > PKT_PRIV_LEN) { 4265 if ((tgt = kmem_zalloc((size_t)tgtlen, kf)) == NULL) { 4266 goto fail; 4267 } 4268 cmd->cmd_flags |= CFLAG_PRIVEXTERN; 4269 cmd->cmd_pkt->pkt_private = tgt; 4270 } 4271 if (statuslen > EXTCMDS_STATUS_SIZE) { 4272 if ((scbp = kmem_zalloc((size_t)statuslen, kf)) == NULL) { 4273 goto fail; 4274 } 4275 cmd->cmd_flags |= CFLAG_SCBEXTERN; 4276 cmd->cmd_pkt->pkt_scbp = (opaque_t)scbp; 4277 4278 /* allocate sense data buf for DMA */ 4279 if (mptsas_cmdarqsize(mpt, cmd, statuslen - 4280 MPTSAS_GET_ITEM_OFF(struct scsi_arq_status, sts_sensedata), 4281 kf) == B_FALSE) 4282 goto fail; 4283 } 4284 return (0); 4285 fail: 4286 mptsas_pkt_destroy_extern(mpt, cmd); 4287 return (1); 4288 } 4289 4290 /* 4291 * deallocate external pkt space and deallocate the pkt 4292 */ 4293 static void 4294 mptsas_pkt_destroy_extern(mptsas_t *mpt, mptsas_cmd_t *cmd) 4295 { 4296 NDBG3(("mptsas_pkt_destroy_extern: cmd=0x%p", (void *)cmd)); 4297 4298 if (cmd->cmd_flags & CFLAG_FREE) { 4299 mptsas_log(mpt, CE_PANIC, 4300 "mptsas_pkt_destroy_extern: freeing free packet"); 4301 _NOTE(NOT_REACHED) 4302 /* NOTREACHED */ 4303 } 4304 if (cmd->cmd_extrqslen != 0) { 4305 rmfree(mpt->m_erqsense_map, cmd->cmd_extrqschunks, 4306 cmd->cmd_extrqsidx + 1); 4307 } 4308 if (cmd->cmd_flags & CFLAG_CDBEXTERN) { 4309 kmem_free(cmd->cmd_pkt->pkt_cdbp, (size_t)cmd->cmd_cdblen); 4310 } 4311 if (cmd->cmd_flags & CFLAG_SCBEXTERN) { 4312 kmem_free(cmd->cmd_pkt->pkt_scbp, (size_t)cmd->cmd_scblen); 4313 } 4314 if (cmd->cmd_flags & CFLAG_PRIVEXTERN) { 4315 kmem_free(cmd->cmd_pkt->pkt_private, (size_t)cmd->cmd_privlen); 4316 } 4317 cmd->cmd_flags = CFLAG_FREE; 4318 kmem_cache_free(mpt->m_kmem_cache, (void *)cmd); 4319 } 4320 4321 /* 4322 * tran_sync_pkt(9E) - explicit DMA synchronization 4323 */ 4324 /*ARGSUSED*/ 4325 static void 4326 mptsas_scsi_sync_pkt(struct scsi_address *ap, struct scsi_pkt *pkt) 4327 { 4328 mptsas_cmd_t *cmd = PKT2CMD(pkt); 4329 4330 NDBG3(("mptsas_scsi_sync_pkt: target=%d, pkt=0x%p", 4331 ap->a_target, (void *)pkt)); 4332 4333 if (cmd->cmd_dmahandle) { 4334 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0, 4335 (cmd->cmd_flags & CFLAG_DMASEND) ? 4336 DDI_DMA_SYNC_FORDEV : DDI_DMA_SYNC_FORCPU); 4337 } 4338 } 4339 4340 /* 4341 * tran_dmafree(9E) - deallocate DMA resources allocated for command 4342 */ 4343 /*ARGSUSED*/ 4344 static void 4345 mptsas_scsi_dmafree(struct scsi_address *ap, struct scsi_pkt *pkt) 4346 { 4347 mptsas_cmd_t *cmd = PKT2CMD(pkt); 4348 mptsas_t *mpt = ADDR2MPT(ap); 4349 4350 NDBG3(("mptsas_scsi_dmafree: target=%d pkt=0x%p", 4351 ap->a_target, (void *)pkt)); 4352 4353 if (cmd->cmd_flags & CFLAG_DMAVALID) { 4354 (void) ddi_dma_unbind_handle(cmd->cmd_dmahandle); 4355 cmd->cmd_flags &= ~CFLAG_DMAVALID; 4356 } 4357 4358 mptsas_free_extra_sgl_frame(mpt, cmd); 4359 } 4360 4361 static void 4362 mptsas_pkt_comp(struct scsi_pkt *pkt, mptsas_cmd_t *cmd) 4363 { 4364 if ((cmd->cmd_flags & CFLAG_CMDIOPB) && 4365 (!(cmd->cmd_flags & CFLAG_DMASEND))) { 4366 (void) ddi_dma_sync(cmd->cmd_dmahandle, 0, 0, 4367 DDI_DMA_SYNC_FORCPU); 4368 } 4369 (*pkt->pkt_comp)(pkt); 4370 } 4371 4372 static void 4373 mptsas_sge_mainframe(mptsas_cmd_t *cmd, pMpi2SCSIIORequest_t frame, 4374 ddi_acc_handle_t acc_hdl, uint_t cookiec, uint32_t end_flags) 4375 { 4376 pMpi2SGESimple64_t sge; 4377 mptti_t *dmap; 4378 uint32_t flags; 4379 4380 dmap = cmd->cmd_sg; 4381 4382 sge = (pMpi2SGESimple64_t)(&frame->SGL); 4383 while (cookiec--) { 4384 ddi_put32(acc_hdl, 4385 &sge->Address.Low, dmap->addr.address64.Low); 4386 ddi_put32(acc_hdl, 4387 &sge->Address.High, dmap->addr.address64.High); 4388 ddi_put32(acc_hdl, &sge->FlagsLength, 4389 dmap->count); 4390 flags = ddi_get32(acc_hdl, &sge->FlagsLength); 4391 flags |= ((uint32_t) 4392 (MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 4393 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4394 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 4395 MPI2_SGE_FLAGS_SHIFT); 4396 4397 /* 4398 * If this is the last cookie, we set the flags 4399 * to indicate so 4400 */ 4401 if (cookiec == 0) { 4402 flags |= end_flags; 4403 } 4404 if (cmd->cmd_flags & CFLAG_DMASEND) { 4405 flags |= (MPI2_SGE_FLAGS_HOST_TO_IOC << 4406 MPI2_SGE_FLAGS_SHIFT); 4407 } else { 4408 flags |= (MPI2_SGE_FLAGS_IOC_TO_HOST << 4409 MPI2_SGE_FLAGS_SHIFT); 4410 } 4411 ddi_put32(acc_hdl, &sge->FlagsLength, flags); 4412 dmap++; 4413 sge++; 4414 } 4415 } 4416 4417 static void 4418 mptsas_sge_chain(mptsas_t *mpt, mptsas_cmd_t *cmd, 4419 pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl) 4420 { 4421 pMpi2SGESimple64_t sge; 4422 pMpi2SGEChain64_t sgechain; 4423 uint64_t nframe_phys_addr; 4424 uint_t cookiec; 4425 mptti_t *dmap; 4426 uint32_t flags; 4427 4428 /* 4429 * Save the number of entries in the DMA 4430 * Scatter/Gather list 4431 */ 4432 cookiec = cmd->cmd_cookiec; 4433 4434 /* 4435 * Hereby we start to deal with multiple frames. 4436 * The process is as follows: 4437 * 1. Determine how many frames are needed for SGL element 4438 * storage; Note that all frames are stored in contiguous 4439 * memory space and in 64-bit DMA mode each element is 4440 * 3 double-words (12 bytes) long. 4441 * 2. Fill up the main frame. We need to do this separately 4442 * since it contains the SCSI IO request header and needs 4443 * dedicated processing. Note that the last 4 double-words 4444 * of the SCSI IO header is for SGL element storage 4445 * (MPI2_SGE_IO_UNION). 4446 * 3. Fill the chain element in the main frame, so the DMA 4447 * engine can use the following frames. 4448 * 4. Enter a loop to fill the remaining frames. Note that the 4449 * last frame contains no chain element. The remaining 4450 * frames go into the mpt SGL buffer allocated on the fly, 4451 * not immediately following the main message frame, as in 4452 * Gen1. 4453 * Some restrictions: 4454 * 1. For 64-bit DMA, the simple element and chain element 4455 * are both of 3 double-words (12 bytes) in size, even 4456 * though all frames are stored in the first 4G of mem 4457 * range and the higher 32-bits of the address are always 0. 4458 * 2. On some controllers (like the 1064/1068), a frame can 4459 * hold SGL elements with the last 1 or 2 double-words 4460 * (4 or 8 bytes) un-used. On these controllers, we should 4461 * recognize that there's not enough room for another SGL 4462 * element and move the sge pointer to the next frame. 4463 */ 4464 int i, j, k, l, frames, sgemax; 4465 int temp; 4466 uint8_t chainflags; 4467 uint16_t chainlength; 4468 mptsas_cache_frames_t *p; 4469 4470 /* 4471 * Sgemax is the number of SGE's that will fit 4472 * each extra frame and frames is total 4473 * number of frames we'll need. 1 sge entry per 4474 * frame is reseverd for the chain element thus the -1 below. 4475 */ 4476 sgemax = ((mpt->m_req_frame_size / sizeof (MPI2_SGE_SIMPLE64)) 4477 - 1); 4478 temp = (cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) / sgemax; 4479 4480 /* 4481 * A little check to see if we need to round up the number 4482 * of frames we need 4483 */ 4484 if ((cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) - (temp * 4485 sgemax) > 1) { 4486 frames = (temp + 1); 4487 } else { 4488 frames = temp; 4489 } 4490 dmap = cmd->cmd_sg; 4491 sge = (pMpi2SGESimple64_t)(&frame->SGL); 4492 4493 /* 4494 * First fill in the main frame 4495 */ 4496 j = MPTSAS_MAX_FRAME_SGES64(mpt) - 1; 4497 mptsas_sge_mainframe(cmd, frame, acc_hdl, j, 4498 ((uint32_t)(MPI2_SGE_FLAGS_LAST_ELEMENT) << 4499 MPI2_SGE_FLAGS_SHIFT)); 4500 dmap += j; 4501 sge += j; 4502 j++; 4503 4504 /* 4505 * Fill in the chain element in the main frame. 4506 * About calculation on ChainOffset: 4507 * 1. Struct msg_scsi_io_request has 4 double-words (16 bytes) 4508 * in the end reserved for SGL element storage 4509 * (MPI2_SGE_IO_UNION); we should count it in our 4510 * calculation. See its definition in the header file. 4511 * 2. Constant j is the counter of the current SGL element 4512 * that will be processed, and (j - 1) is the number of 4513 * SGL elements that have been processed (stored in the 4514 * main frame). 4515 * 3. ChainOffset value should be in units of double-words (4 4516 * bytes) so the last value should be divided by 4. 4517 */ 4518 ddi_put8(acc_hdl, &frame->ChainOffset, 4519 (sizeof (MPI2_SCSI_IO_REQUEST) - 4520 sizeof (MPI2_SGE_IO_UNION) + 4521 (j - 1) * sizeof (MPI2_SGE_SIMPLE64)) >> 2); 4522 sgechain = (pMpi2SGEChain64_t)sge; 4523 chainflags = (MPI2_SGE_FLAGS_CHAIN_ELEMENT | 4524 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4525 MPI2_SGE_FLAGS_64_BIT_ADDRESSING); 4526 ddi_put8(acc_hdl, &sgechain->Flags, chainflags); 4527 4528 /* 4529 * The size of the next frame is the accurate size of space 4530 * (in bytes) used to store the SGL elements. j is the counter 4531 * of SGL elements. (j - 1) is the number of SGL elements that 4532 * have been processed (stored in frames). 4533 */ 4534 if (frames >= 2) { 4535 ASSERT(mpt->m_req_frame_size >= sizeof (MPI2_SGE_SIMPLE64)); 4536 chainlength = mpt->m_req_frame_size / 4537 sizeof (MPI2_SGE_SIMPLE64) * 4538 sizeof (MPI2_SGE_SIMPLE64); 4539 } else { 4540 chainlength = ((cookiec - (j - 1)) * 4541 sizeof (MPI2_SGE_SIMPLE64)); 4542 } 4543 4544 p = cmd->cmd_extra_frames; 4545 4546 ddi_put16(acc_hdl, &sgechain->Length, chainlength); 4547 ddi_put32(acc_hdl, &sgechain->Address.Low, p->m_phys_addr); 4548 ddi_put32(acc_hdl, &sgechain->Address.High, p->m_phys_addr >> 32); 4549 4550 /* 4551 * If there are more than 2 frames left we have to 4552 * fill in the next chain offset to the location of 4553 * the chain element in the next frame. 4554 * sgemax is the number of simple elements in an extra 4555 * frame. Note that the value NextChainOffset should be 4556 * in double-words (4 bytes). 4557 */ 4558 if (frames >= 2) { 4559 ddi_put8(acc_hdl, &sgechain->NextChainOffset, 4560 (sgemax * sizeof (MPI2_SGE_SIMPLE64)) >> 2); 4561 } else { 4562 ddi_put8(acc_hdl, &sgechain->NextChainOffset, 0); 4563 } 4564 4565 /* 4566 * Jump to next frame; 4567 * Starting here, chain buffers go into the per command SGL. 4568 * This buffer is allocated when chain buffers are needed. 4569 */ 4570 sge = (pMpi2SGESimple64_t)p->m_frames_addr; 4571 i = cookiec; 4572 4573 /* 4574 * Start filling in frames with SGE's. If we 4575 * reach the end of frame and still have SGE's 4576 * to fill we need to add a chain element and 4577 * use another frame. j will be our counter 4578 * for what cookie we are at and i will be 4579 * the total cookiec. k is the current frame 4580 */ 4581 for (k = 1; k <= frames; k++) { 4582 for (l = 1; (l <= (sgemax + 1)) && (j <= i); j++, l++) { 4583 4584 /* 4585 * If we have reached the end of frame 4586 * and we have more SGE's to fill in 4587 * we have to fill the final entry 4588 * with a chain element and then 4589 * continue to the next frame 4590 */ 4591 if ((l == (sgemax + 1)) && (k != frames)) { 4592 sgechain = (pMpi2SGEChain64_t)sge; 4593 j--; 4594 chainflags = ( 4595 MPI2_SGE_FLAGS_CHAIN_ELEMENT | 4596 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4597 MPI2_SGE_FLAGS_64_BIT_ADDRESSING); 4598 ddi_put8(p->m_acc_hdl, 4599 &sgechain->Flags, chainflags); 4600 /* 4601 * k is the frame counter and (k + 1) 4602 * is the number of the next frame. 4603 * Note that frames are in contiguous 4604 * memory space. 4605 */ 4606 nframe_phys_addr = p->m_phys_addr + 4607 (mpt->m_req_frame_size * k); 4608 ddi_put32(p->m_acc_hdl, 4609 &sgechain->Address.Low, 4610 nframe_phys_addr); 4611 ddi_put32(p->m_acc_hdl, 4612 &sgechain->Address.High, 4613 nframe_phys_addr >> 32); 4614 4615 /* 4616 * If there are more than 2 frames left 4617 * we have to next chain offset to 4618 * the location of the chain element 4619 * in the next frame and fill in the 4620 * length of the next chain 4621 */ 4622 if ((frames - k) >= 2) { 4623 ddi_put8(p->m_acc_hdl, 4624 &sgechain->NextChainOffset, 4625 (sgemax * 4626 sizeof (MPI2_SGE_SIMPLE64)) 4627 >> 2); 4628 ddi_put16(p->m_acc_hdl, 4629 &sgechain->Length, 4630 mpt->m_req_frame_size / 4631 sizeof (MPI2_SGE_SIMPLE64) * 4632 sizeof (MPI2_SGE_SIMPLE64)); 4633 } else { 4634 /* 4635 * This is the last frame. Set 4636 * the NextChainOffset to 0 and 4637 * Length is the total size of 4638 * all remaining simple elements 4639 */ 4640 ddi_put8(p->m_acc_hdl, 4641 &sgechain->NextChainOffset, 4642 0); 4643 ddi_put16(p->m_acc_hdl, 4644 &sgechain->Length, 4645 (cookiec - j) * 4646 sizeof (MPI2_SGE_SIMPLE64)); 4647 } 4648 4649 /* Jump to the next frame */ 4650 sge = (pMpi2SGESimple64_t) 4651 ((char *)p->m_frames_addr + 4652 (int)mpt->m_req_frame_size * k); 4653 4654 continue; 4655 } 4656 4657 ddi_put32(p->m_acc_hdl, 4658 &sge->Address.Low, 4659 dmap->addr.address64.Low); 4660 ddi_put32(p->m_acc_hdl, 4661 &sge->Address.High, 4662 dmap->addr.address64.High); 4663 ddi_put32(p->m_acc_hdl, 4664 &sge->FlagsLength, dmap->count); 4665 flags = ddi_get32(p->m_acc_hdl, 4666 &sge->FlagsLength); 4667 flags |= ((uint32_t)( 4668 MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 4669 MPI2_SGE_FLAGS_SYSTEM_ADDRESS | 4670 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 4671 MPI2_SGE_FLAGS_SHIFT); 4672 4673 /* 4674 * If we are at the end of the frame and 4675 * there is another frame to fill in 4676 * we set the last simple element as last 4677 * element 4678 */ 4679 if ((l == sgemax) && (k != frames)) { 4680 flags |= ((uint32_t) 4681 (MPI2_SGE_FLAGS_LAST_ELEMENT) << 4682 MPI2_SGE_FLAGS_SHIFT); 4683 } 4684 4685 /* 4686 * If this is the final cookie we 4687 * indicate it by setting the flags 4688 */ 4689 if (j == i) { 4690 flags |= ((uint32_t) 4691 (MPI2_SGE_FLAGS_LAST_ELEMENT | 4692 MPI2_SGE_FLAGS_END_OF_BUFFER | 4693 MPI2_SGE_FLAGS_END_OF_LIST) << 4694 MPI2_SGE_FLAGS_SHIFT); 4695 } 4696 if (cmd->cmd_flags & CFLAG_DMASEND) { 4697 flags |= 4698 (MPI2_SGE_FLAGS_HOST_TO_IOC << 4699 MPI2_SGE_FLAGS_SHIFT); 4700 } else { 4701 flags |= 4702 (MPI2_SGE_FLAGS_IOC_TO_HOST << 4703 MPI2_SGE_FLAGS_SHIFT); 4704 } 4705 ddi_put32(p->m_acc_hdl, 4706 &sge->FlagsLength, flags); 4707 dmap++; 4708 sge++; 4709 } 4710 } 4711 4712 /* 4713 * Sync DMA with the chain buffers that were just created 4714 */ 4715 (void) ddi_dma_sync(p->m_dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV); 4716 } 4717 4718 static void 4719 mptsas_ieee_sge_mainframe(mptsas_cmd_t *cmd, pMpi2SCSIIORequest_t frame, 4720 ddi_acc_handle_t acc_hdl, uint_t cookiec, uint8_t end_flag) 4721 { 4722 pMpi2IeeeSgeSimple64_t ieeesge; 4723 mptti_t *dmap; 4724 uint8_t flags; 4725 4726 dmap = cmd->cmd_sg; 4727 4728 NDBG1(("mptsas_ieee_sge_mainframe: cookiec=%d, %s", cookiec, 4729 cmd->cmd_flags & CFLAG_DMASEND?"Out":"In")); 4730 4731 ieeesge = (pMpi2IeeeSgeSimple64_t)(&frame->SGL); 4732 while (cookiec--) { 4733 ddi_put32(acc_hdl, 4734 &ieeesge->Address.Low, dmap->addr.address64.Low); 4735 ddi_put32(acc_hdl, 4736 &ieeesge->Address.High, dmap->addr.address64.High); 4737 ddi_put32(acc_hdl, &ieeesge->Length, 4738 dmap->count); 4739 NDBG1(("mptsas_ieee_sge_mainframe: len=%d", dmap->count)); 4740 flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 4741 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR); 4742 4743 /* 4744 * If this is the last cookie, we set the flags 4745 * to indicate so 4746 */ 4747 if (cookiec == 0) { 4748 flags |= end_flag; 4749 } 4750 4751 ddi_put8(acc_hdl, &ieeesge->Flags, flags); 4752 dmap++; 4753 ieeesge++; 4754 } 4755 } 4756 4757 static void 4758 mptsas_ieee_sge_chain(mptsas_t *mpt, mptsas_cmd_t *cmd, 4759 pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl) 4760 { 4761 pMpi2IeeeSgeSimple64_t ieeesge; 4762 pMpi25IeeeSgeChain64_t ieeesgechain; 4763 uint64_t nframe_phys_addr; 4764 uint_t cookiec; 4765 mptti_t *dmap; 4766 uint8_t flags; 4767 4768 /* 4769 * Save the number of entries in the DMA 4770 * Scatter/Gather list 4771 */ 4772 cookiec = cmd->cmd_cookiec; 4773 4774 NDBG1(("mptsas_ieee_sge_chain: cookiec=%d", cookiec)); 4775 4776 /* 4777 * Hereby we start to deal with multiple frames. 4778 * The process is as follows: 4779 * 1. Determine how many frames are needed for SGL element 4780 * storage; Note that all frames are stored in contiguous 4781 * memory space and in 64-bit DMA mode each element is 4782 * 4 double-words (16 bytes) long. 4783 * 2. Fill up the main frame. We need to do this separately 4784 * since it contains the SCSI IO request header and needs 4785 * dedicated processing. Note that the last 4 double-words 4786 * of the SCSI IO header is for SGL element storage 4787 * (MPI2_SGE_IO_UNION). 4788 * 3. Fill the chain element in the main frame, so the DMA 4789 * engine can use the following frames. 4790 * 4. Enter a loop to fill the remaining frames. Note that the 4791 * last frame contains no chain element. The remaining 4792 * frames go into the mpt SGL buffer allocated on the fly, 4793 * not immediately following the main message frame, as in 4794 * Gen1. 4795 * Restrictions: 4796 * For 64-bit DMA, the simple element and chain element 4797 * are both of 4 double-words (16 bytes) in size, even 4798 * though all frames are stored in the first 4G of mem 4799 * range and the higher 32-bits of the address are always 0. 4800 */ 4801 int i, j, k, l, frames, sgemax; 4802 int temp; 4803 uint8_t chainflags; 4804 uint32_t chainlength; 4805 mptsas_cache_frames_t *p; 4806 4807 /* 4808 * Sgemax is the number of SGE's that will fit 4809 * each extra frame and frames is total 4810 * number of frames we'll need. 1 sge entry per 4811 * frame is reseverd for the chain element thus the -1 below. 4812 */ 4813 sgemax = ((mpt->m_req_frame_size / sizeof (MPI2_IEEE_SGE_SIMPLE64)) 4814 - 1); 4815 temp = (cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) / sgemax; 4816 4817 /* 4818 * A little check to see if we need to round up the number 4819 * of frames we need 4820 */ 4821 if ((cookiec - (MPTSAS_MAX_FRAME_SGES64(mpt) - 1)) - (temp * 4822 sgemax) > 1) { 4823 frames = (temp + 1); 4824 } else { 4825 frames = temp; 4826 } 4827 NDBG1(("mptsas_ieee_sge_chain: temp=%d, frames=%d", temp, frames)); 4828 dmap = cmd->cmd_sg; 4829 ieeesge = (pMpi2IeeeSgeSimple64_t)(&frame->SGL); 4830 4831 /* 4832 * First fill in the main frame 4833 */ 4834 j = MPTSAS_MAX_FRAME_SGES64(mpt) - 1; 4835 mptsas_ieee_sge_mainframe(cmd, frame, acc_hdl, j, 0); 4836 dmap += j; 4837 ieeesge += j; 4838 j++; 4839 4840 /* 4841 * Fill in the chain element in the main frame. 4842 * About calculation on ChainOffset: 4843 * 1. Struct msg_scsi_io_request has 4 double-words (16 bytes) 4844 * in the end reserved for SGL element storage 4845 * (MPI2_SGE_IO_UNION); we should count it in our 4846 * calculation. See its definition in the header file. 4847 * 2. Constant j is the counter of the current SGL element 4848 * that will be processed, and (j - 1) is the number of 4849 * SGL elements that have been processed (stored in the 4850 * main frame). 4851 * 3. ChainOffset value should be in units of quad-words (16 4852 * bytes) so the last value should be divided by 16. 4853 */ 4854 ddi_put8(acc_hdl, &frame->ChainOffset, 4855 (sizeof (MPI2_SCSI_IO_REQUEST) - 4856 sizeof (MPI2_SGE_IO_UNION) + 4857 (j - 1) * sizeof (MPI2_IEEE_SGE_SIMPLE64)) >> 4); 4858 ieeesgechain = (pMpi25IeeeSgeChain64_t)ieeesge; 4859 chainflags = (MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT | 4860 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR); 4861 ddi_put8(acc_hdl, &ieeesgechain->Flags, chainflags); 4862 4863 /* 4864 * The size of the next frame is the accurate size of space 4865 * (in bytes) used to store the SGL elements. j is the counter 4866 * of SGL elements. (j - 1) is the number of SGL elements that 4867 * have been processed (stored in frames). 4868 */ 4869 if (frames >= 2) { 4870 ASSERT(mpt->m_req_frame_size >= 4871 sizeof (MPI2_IEEE_SGE_SIMPLE64)); 4872 chainlength = mpt->m_req_frame_size / 4873 sizeof (MPI2_IEEE_SGE_SIMPLE64) * 4874 sizeof (MPI2_IEEE_SGE_SIMPLE64); 4875 } else { 4876 chainlength = ((cookiec - (j - 1)) * 4877 sizeof (MPI2_IEEE_SGE_SIMPLE64)); 4878 } 4879 4880 p = cmd->cmd_extra_frames; 4881 4882 ddi_put32(acc_hdl, &ieeesgechain->Length, chainlength); 4883 ddi_put32(acc_hdl, &ieeesgechain->Address.Low, p->m_phys_addr); 4884 ddi_put32(acc_hdl, &ieeesgechain->Address.High, p->m_phys_addr >> 32); 4885 4886 /* 4887 * If there are more than 2 frames left we have to 4888 * fill in the next chain offset to the location of 4889 * the chain element in the next frame. 4890 * sgemax is the number of simple elements in an extra 4891 * frame. Note that the value NextChainOffset should be 4892 * in double-words (4 bytes). 4893 */ 4894 if (frames >= 2) { 4895 ddi_put8(acc_hdl, &ieeesgechain->NextChainOffset, 4896 (sgemax * sizeof (MPI2_IEEE_SGE_SIMPLE64)) >> 4); 4897 } else { 4898 ddi_put8(acc_hdl, &ieeesgechain->NextChainOffset, 0); 4899 } 4900 4901 /* 4902 * Jump to next frame; 4903 * Starting here, chain buffers go into the per command SGL. 4904 * This buffer is allocated when chain buffers are needed. 4905 */ 4906 ieeesge = (pMpi2IeeeSgeSimple64_t)p->m_frames_addr; 4907 i = cookiec; 4908 4909 /* 4910 * Start filling in frames with SGE's. If we 4911 * reach the end of frame and still have SGE's 4912 * to fill we need to add a chain element and 4913 * use another frame. j will be our counter 4914 * for what cookie we are at and i will be 4915 * the total cookiec. k is the current frame 4916 */ 4917 for (k = 1; k <= frames; k++) { 4918 for (l = 1; (l <= (sgemax + 1)) && (j <= i); j++, l++) { 4919 4920 /* 4921 * If we have reached the end of frame 4922 * and we have more SGE's to fill in 4923 * we have to fill the final entry 4924 * with a chain element and then 4925 * continue to the next frame 4926 */ 4927 if ((l == (sgemax + 1)) && (k != frames)) { 4928 ieeesgechain = (pMpi25IeeeSgeChain64_t)ieeesge; 4929 j--; 4930 chainflags = 4931 MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT | 4932 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR; 4933 ddi_put8(p->m_acc_hdl, 4934 &ieeesgechain->Flags, chainflags); 4935 /* 4936 * k is the frame counter and (k + 1) 4937 * is the number of the next frame. 4938 * Note that frames are in contiguous 4939 * memory space. 4940 */ 4941 nframe_phys_addr = p->m_phys_addr + 4942 (mpt->m_req_frame_size * k); 4943 ddi_put32(p->m_acc_hdl, 4944 &ieeesgechain->Address.Low, 4945 nframe_phys_addr); 4946 ddi_put32(p->m_acc_hdl, 4947 &ieeesgechain->Address.High, 4948 nframe_phys_addr >> 32); 4949 4950 /* 4951 * If there are more than 2 frames left 4952 * we have to next chain offset to 4953 * the location of the chain element 4954 * in the next frame and fill in the 4955 * length of the next chain 4956 */ 4957 if ((frames - k) >= 2) { 4958 ddi_put8(p->m_acc_hdl, 4959 &ieeesgechain->NextChainOffset, 4960 (sgemax * 4961 sizeof (MPI2_IEEE_SGE_SIMPLE64)) 4962 >> 4); 4963 ASSERT(mpt->m_req_frame_size >= 4964 sizeof (MPI2_IEEE_SGE_SIMPLE64)); 4965 ddi_put32(p->m_acc_hdl, 4966 &ieeesgechain->Length, 4967 mpt->m_req_frame_size / 4968 sizeof (MPI2_IEEE_SGE_SIMPLE64) * 4969 sizeof (MPI2_IEEE_SGE_SIMPLE64)); 4970 } else { 4971 /* 4972 * This is the last frame. Set 4973 * the NextChainOffset to 0 and 4974 * Length is the total size of 4975 * all remaining simple elements 4976 */ 4977 ddi_put8(p->m_acc_hdl, 4978 &ieeesgechain->NextChainOffset, 4979 0); 4980 ddi_put32(p->m_acc_hdl, 4981 &ieeesgechain->Length, 4982 (cookiec - j) * 4983 sizeof (MPI2_IEEE_SGE_SIMPLE64)); 4984 } 4985 4986 /* Jump to the next frame */ 4987 ieeesge = (pMpi2IeeeSgeSimple64_t) 4988 ((char *)p->m_frames_addr + 4989 (int)mpt->m_req_frame_size * k); 4990 4991 continue; 4992 } 4993 4994 ddi_put32(p->m_acc_hdl, 4995 &ieeesge->Address.Low, 4996 dmap->addr.address64.Low); 4997 ddi_put32(p->m_acc_hdl, 4998 &ieeesge->Address.High, 4999 dmap->addr.address64.High); 5000 ddi_put32(p->m_acc_hdl, 5001 &ieeesge->Length, dmap->count); 5002 flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 5003 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR); 5004 5005 /* 5006 * If we are at the end of the frame and 5007 * there is another frame to fill in 5008 * do we need to do anything? 5009 * if ((l == sgemax) && (k != frames)) { 5010 * } 5011 */ 5012 5013 /* 5014 * If this is the final cookie set end of list. 5015 */ 5016 if (j == i) { 5017 flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST; 5018 } 5019 5020 ddi_put8(p->m_acc_hdl, &ieeesge->Flags, flags); 5021 dmap++; 5022 ieeesge++; 5023 } 5024 } 5025 5026 /* 5027 * Sync DMA with the chain buffers that were just created 5028 */ 5029 (void) ddi_dma_sync(p->m_dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV); 5030 } 5031 5032 static void 5033 mptsas_sge_setup(mptsas_t *mpt, mptsas_cmd_t *cmd, uint32_t *control, 5034 pMpi2SCSIIORequest_t frame, ddi_acc_handle_t acc_hdl) 5035 { 5036 ASSERT(cmd->cmd_flags & CFLAG_DMAVALID); 5037 5038 NDBG1(("mptsas_sge_setup: cookiec=%d", cmd->cmd_cookiec)); 5039 5040 /* 5041 * Set read/write bit in control. 5042 */ 5043 if (cmd->cmd_flags & CFLAG_DMASEND) { 5044 *control |= MPI2_SCSIIO_CONTROL_WRITE; 5045 } else { 5046 *control |= MPI2_SCSIIO_CONTROL_READ; 5047 } 5048 5049 ddi_put32(acc_hdl, &frame->DataLength, cmd->cmd_dmacount); 5050 5051 /* 5052 * We have 4 cases here. First where we can fit all the 5053 * SG elements into the main frame, and the case 5054 * where we can't. The SG element is also different when using 5055 * MPI2.5 interface. 5056 * If we have more cookies than we can attach to a frame 5057 * we will need to use a chain element to point 5058 * a location of memory where the rest of the S/G 5059 * elements reside. 5060 */ 5061 if (cmd->cmd_cookiec <= MPTSAS_MAX_FRAME_SGES64(mpt)) { 5062 if (mpt->m_MPI25) { 5063 mptsas_ieee_sge_mainframe(cmd, frame, acc_hdl, 5064 cmd->cmd_cookiec, 5065 MPI25_IEEE_SGE_FLAGS_END_OF_LIST); 5066 } else { 5067 mptsas_sge_mainframe(cmd, frame, acc_hdl, 5068 cmd->cmd_cookiec, 5069 ((uint32_t)(MPI2_SGE_FLAGS_LAST_ELEMENT 5070 | MPI2_SGE_FLAGS_END_OF_BUFFER 5071 | MPI2_SGE_FLAGS_END_OF_LIST) << 5072 MPI2_SGE_FLAGS_SHIFT)); 5073 } 5074 } else { 5075 if (mpt->m_MPI25) { 5076 mptsas_ieee_sge_chain(mpt, cmd, frame, acc_hdl); 5077 } else { 5078 mptsas_sge_chain(mpt, cmd, frame, acc_hdl); 5079 } 5080 } 5081 } 5082 5083 /* 5084 * Interrupt handling 5085 * Utility routine. Poll for status of a command sent to HBA 5086 * without interrupts (a FLAG_NOINTR command). 5087 */ 5088 int 5089 mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime) 5090 { 5091 int rval = TRUE; 5092 5093 NDBG5(("mptsas_poll: cmd=0x%p", (void *)poll_cmd)); 5094 5095 if ((poll_cmd->cmd_flags & CFLAG_TM_CMD) == 0) { 5096 mptsas_restart_hba(mpt); 5097 } 5098 5099 /* 5100 * Wait, using drv_usecwait(), long enough for the command to 5101 * reasonably return from the target if the target isn't 5102 * "dead". A polled command may well be sent from scsi_poll, and 5103 * there are retries built in to scsi_poll if the transport 5104 * accepted the packet (TRAN_ACCEPT). scsi_poll waits 1 second 5105 * and retries the transport up to scsi_poll_busycnt times 5106 * (currently 60) if 5107 * 1. pkt_reason is CMD_INCOMPLETE and pkt_state is 0, or 5108 * 2. pkt_reason is CMD_CMPLT and *pkt_scbp has STATUS_BUSY 5109 * 5110 * limit the waiting to avoid a hang in the event that the 5111 * cmd never gets started but we are still receiving interrupts 5112 */ 5113 while (!(poll_cmd->cmd_flags & CFLAG_FINISHED)) { 5114 if (mptsas_wait_intr(mpt, polltime) == FALSE) { 5115 NDBG5(("mptsas_poll: command incomplete")); 5116 rval = FALSE; 5117 break; 5118 } 5119 } 5120 5121 if (rval == FALSE) { 5122 5123 /* 5124 * this isn't supposed to happen, the hba must be wedged 5125 * Mark this cmd as a timeout. 5126 */ 5127 mptsas_set_pkt_reason(mpt, poll_cmd, CMD_TIMEOUT, 5128 (STAT_TIMEOUT|STAT_ABORTED)); 5129 5130 if (poll_cmd->cmd_queued == FALSE) { 5131 5132 NDBG5(("mptsas_poll: not on waitq")); 5133 5134 poll_cmd->cmd_pkt->pkt_state |= 5135 (STATE_GOT_BUS|STATE_GOT_TARGET|STATE_SENT_CMD); 5136 } else { 5137 5138 /* find and remove it from the waitq */ 5139 NDBG5(("mptsas_poll: delete from waitq")); 5140 mptsas_waitq_delete(mpt, poll_cmd); 5141 } 5142 5143 } 5144 mptsas_fma_check(mpt, poll_cmd); 5145 NDBG5(("mptsas_poll: done")); 5146 return (rval); 5147 } 5148 5149 /* 5150 * Used for polling cmds and TM function 5151 */ 5152 static int 5153 mptsas_wait_intr(mptsas_t *mpt, int polltime) 5154 { 5155 int cnt; 5156 pMpi2ReplyDescriptorsUnion_t reply_desc_union; 5157 uint32_t int_mask; 5158 5159 NDBG5(("mptsas_wait_intr")); 5160 5161 mpt->m_polled_intr = 1; 5162 5163 /* 5164 * Get the current interrupt mask and disable interrupts. When 5165 * re-enabling ints, set mask to saved value. 5166 */ 5167 int_mask = ddi_get32(mpt->m_datap, &mpt->m_reg->HostInterruptMask); 5168 MPTSAS_DISABLE_INTR(mpt); 5169 5170 /* 5171 * Keep polling for at least (polltime * 1000) seconds 5172 */ 5173 for (cnt = 0; cnt < polltime; cnt++) { 5174 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0, 5175 DDI_DMA_SYNC_FORCPU); 5176 5177 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t) 5178 MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index); 5179 5180 if (ddi_get32(mpt->m_acc_post_queue_hdl, 5181 &reply_desc_union->Words.Low) == 0xFFFFFFFF || 5182 ddi_get32(mpt->m_acc_post_queue_hdl, 5183 &reply_desc_union->Words.High) == 0xFFFFFFFF) { 5184 drv_usecwait(1000); 5185 continue; 5186 } 5187 5188 /* 5189 * The reply is valid, process it according to its 5190 * type. 5191 */ 5192 mptsas_process_intr(mpt, reply_desc_union); 5193 5194 if (++mpt->m_post_index == mpt->m_post_queue_depth) { 5195 mpt->m_post_index = 0; 5196 } 5197 5198 /* 5199 * Update the global reply index 5200 */ 5201 ddi_put32(mpt->m_datap, 5202 &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index); 5203 mpt->m_polled_intr = 0; 5204 5205 /* 5206 * Re-enable interrupts and quit. 5207 */ 5208 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, 5209 int_mask); 5210 return (TRUE); 5211 5212 } 5213 5214 /* 5215 * Clear polling flag, re-enable interrupts and quit. 5216 */ 5217 mpt->m_polled_intr = 0; 5218 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, int_mask); 5219 return (FALSE); 5220 } 5221 5222 static void 5223 mptsas_handle_scsi_io_success(mptsas_t *mpt, 5224 pMpi2ReplyDescriptorsUnion_t reply_desc) 5225 { 5226 pMpi2SCSIIOSuccessReplyDescriptor_t scsi_io_success; 5227 uint16_t SMID; 5228 mptsas_slots_t *slots = mpt->m_active; 5229 mptsas_cmd_t *cmd = NULL; 5230 struct scsi_pkt *pkt; 5231 5232 ASSERT(mutex_owned(&mpt->m_mutex)); 5233 5234 scsi_io_success = (pMpi2SCSIIOSuccessReplyDescriptor_t)reply_desc; 5235 SMID = ddi_get16(mpt->m_acc_post_queue_hdl, &scsi_io_success->SMID); 5236 5237 /* 5238 * This is a success reply so just complete the IO. First, do a sanity 5239 * check on the SMID. The final slot is used for TM requests, which 5240 * would not come into this reply handler. 5241 */ 5242 if ((SMID == 0) || (SMID > slots->m_n_normal)) { 5243 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of %d\n", 5244 SMID); 5245 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 5246 return; 5247 } 5248 5249 cmd = slots->m_slot[SMID]; 5250 5251 /* 5252 * print warning and return if the slot is empty 5253 */ 5254 if (cmd == NULL) { 5255 mptsas_log(mpt, CE_WARN, "?NULL command for successful SCSI IO " 5256 "in slot %d", SMID); 5257 return; 5258 } 5259 5260 pkt = CMD2PKT(cmd); 5261 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | STATE_SENT_CMD | 5262 STATE_GOT_STATUS); 5263 if (cmd->cmd_flags & CFLAG_DMAVALID) { 5264 pkt->pkt_state |= STATE_XFERRED_DATA; 5265 } 5266 pkt->pkt_resid = 0; 5267 5268 if (cmd->cmd_flags & CFLAG_PASSTHRU) { 5269 cmd->cmd_flags |= CFLAG_FINISHED; 5270 cv_broadcast(&mpt->m_passthru_cv); 5271 return; 5272 } else { 5273 mptsas_remove_cmd(mpt, cmd); 5274 } 5275 5276 if (cmd->cmd_flags & CFLAG_RETRY) { 5277 /* 5278 * The target returned QFULL or busy, do not add tihs 5279 * pkt to the doneq since the hba will retry 5280 * this cmd. 5281 * 5282 * The pkt has already been resubmitted in 5283 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error(). 5284 * Remove this cmd_flag here. 5285 */ 5286 cmd->cmd_flags &= ~CFLAG_RETRY; 5287 } else { 5288 mptsas_doneq_add(mpt, cmd); 5289 } 5290 } 5291 5292 static void 5293 mptsas_handle_address_reply(mptsas_t *mpt, 5294 pMpi2ReplyDescriptorsUnion_t reply_desc) 5295 { 5296 pMpi2AddressReplyDescriptor_t address_reply; 5297 pMPI2DefaultReply_t reply; 5298 mptsas_fw_diagnostic_buffer_t *pBuffer; 5299 uint32_t reply_addr, reply_frame_dma_baseaddr; 5300 uint16_t SMID, iocstatus; 5301 mptsas_slots_t *slots = mpt->m_active; 5302 mptsas_cmd_t *cmd = NULL; 5303 uint8_t function, buffer_type; 5304 m_replyh_arg_t *args; 5305 int reply_frame_no; 5306 5307 ASSERT(mutex_owned(&mpt->m_mutex)); 5308 5309 address_reply = (pMpi2AddressReplyDescriptor_t)reply_desc; 5310 reply_addr = ddi_get32(mpt->m_acc_post_queue_hdl, 5311 &address_reply->ReplyFrameAddress); 5312 SMID = ddi_get16(mpt->m_acc_post_queue_hdl, &address_reply->SMID); 5313 5314 /* 5315 * If reply frame is not in the proper range we should ignore this 5316 * message and exit the interrupt handler. 5317 */ 5318 reply_frame_dma_baseaddr = mpt->m_reply_frame_dma_addr & 0xffffffffu; 5319 if ((reply_addr < reply_frame_dma_baseaddr) || 5320 (reply_addr >= (reply_frame_dma_baseaddr + 5321 (mpt->m_reply_frame_size * mpt->m_max_replies))) || 5322 ((reply_addr - reply_frame_dma_baseaddr) % 5323 mpt->m_reply_frame_size != 0)) { 5324 mptsas_log(mpt, CE_WARN, "?Received invalid reply frame " 5325 "address 0x%x\n", reply_addr); 5326 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 5327 return; 5328 } 5329 5330 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0, 5331 DDI_DMA_SYNC_FORCPU); 5332 reply = (pMPI2DefaultReply_t)(mpt->m_reply_frame + (reply_addr - 5333 reply_frame_dma_baseaddr)); 5334 function = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->Function); 5335 5336 NDBG31(("mptsas_handle_address_reply: function 0x%x, reply_addr=0x%x", 5337 function, reply_addr)); 5338 5339 /* 5340 * don't get slot information and command for events since these values 5341 * don't exist 5342 */ 5343 if ((function != MPI2_FUNCTION_EVENT_NOTIFICATION) && 5344 (function != MPI2_FUNCTION_DIAG_BUFFER_POST)) { 5345 /* 5346 * This could be a TM reply, which use the last allocated SMID, 5347 * so allow for that. 5348 */ 5349 if ((SMID == 0) || (SMID > (slots->m_n_normal + 1))) { 5350 mptsas_log(mpt, CE_WARN, "?Received invalid SMID of " 5351 "%d\n", SMID); 5352 ddi_fm_service_impact(mpt->m_dip, 5353 DDI_SERVICE_UNAFFECTED); 5354 return; 5355 } 5356 5357 cmd = slots->m_slot[SMID]; 5358 5359 /* 5360 * print warning and return if the slot is empty 5361 */ 5362 if (cmd == NULL) { 5363 mptsas_log(mpt, CE_WARN, "?NULL command for address " 5364 "reply in slot %d", SMID); 5365 return; 5366 } 5367 if ((cmd->cmd_flags & 5368 (CFLAG_PASSTHRU | CFLAG_CONFIG | CFLAG_FW_DIAG))) { 5369 cmd->cmd_rfm = reply_addr; 5370 cmd->cmd_flags |= CFLAG_FINISHED; 5371 cv_broadcast(&mpt->m_passthru_cv); 5372 cv_broadcast(&mpt->m_config_cv); 5373 cv_broadcast(&mpt->m_fw_diag_cv); 5374 return; 5375 } else if (!(cmd->cmd_flags & CFLAG_FW_CMD)) { 5376 mptsas_remove_cmd(mpt, cmd); 5377 } 5378 NDBG31(("\t\tmptsas_process_intr: slot=%d", SMID)); 5379 } 5380 /* 5381 * Depending on the function, we need to handle 5382 * the reply frame (and cmd) differently. 5383 */ 5384 switch (function) { 5385 case MPI2_FUNCTION_SCSI_IO_REQUEST: 5386 mptsas_check_scsi_io_error(mpt, (pMpi2SCSIIOReply_t)reply, cmd); 5387 break; 5388 case MPI2_FUNCTION_SCSI_TASK_MGMT: 5389 cmd->cmd_rfm = reply_addr; 5390 mptsas_check_task_mgt(mpt, (pMpi2SCSIManagementReply_t)reply, 5391 cmd); 5392 break; 5393 case MPI2_FUNCTION_FW_DOWNLOAD: 5394 cmd->cmd_flags |= CFLAG_FINISHED; 5395 cv_signal(&mpt->m_fw_cv); 5396 break; 5397 case MPI2_FUNCTION_EVENT_NOTIFICATION: 5398 reply_frame_no = (reply_addr - reply_frame_dma_baseaddr) / 5399 mpt->m_reply_frame_size; 5400 args = &mpt->m_replyh_args[reply_frame_no]; 5401 args->mpt = (void *)mpt; 5402 args->rfm = reply_addr; 5403 5404 /* 5405 * Record the event if its type is enabled in 5406 * this mpt instance by ioctl. 5407 */ 5408 mptsas_record_event(args); 5409 5410 /* 5411 * Handle time critical events 5412 * NOT_RESPONDING/ADDED only now 5413 */ 5414 if (mptsas_handle_event_sync(args) == DDI_SUCCESS) { 5415 /* 5416 * Would not return main process, 5417 * just let taskq resolve ack action 5418 * and ack would be sent in taskq thread 5419 */ 5420 NDBG20(("send mptsas_handle_event_sync success")); 5421 } 5422 5423 if (mpt->m_in_reset) { 5424 NDBG20(("dropping event received during reset")); 5425 return; 5426 } 5427 5428 if ((ddi_taskq_dispatch(mpt->m_event_taskq, mptsas_handle_event, 5429 (void *)args, DDI_NOSLEEP)) != DDI_SUCCESS) { 5430 mptsas_log(mpt, CE_WARN, "No memory available" 5431 "for dispatch taskq"); 5432 /* 5433 * Return the reply frame to the free queue. 5434 */ 5435 ddi_put32(mpt->m_acc_free_queue_hdl, 5436 &((uint32_t *)(void *) 5437 mpt->m_free_queue)[mpt->m_free_index], reply_addr); 5438 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 5439 DDI_DMA_SYNC_FORDEV); 5440 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 5441 mpt->m_free_index = 0; 5442 } 5443 5444 ddi_put32(mpt->m_datap, 5445 &mpt->m_reg->ReplyFreeHostIndex, mpt->m_free_index); 5446 } 5447 return; 5448 case MPI2_FUNCTION_DIAG_BUFFER_POST: 5449 /* 5450 * If SMID is 0, this implies that the reply is due to a 5451 * release function with a status that the buffer has been 5452 * released. Set the buffer flags accordingly. 5453 */ 5454 if (SMID == 0) { 5455 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 5456 &reply->IOCStatus); 5457 buffer_type = ddi_get8(mpt->m_acc_reply_frame_hdl, 5458 &(((pMpi2DiagBufferPostReply_t)reply)->BufferType)); 5459 if (iocstatus == MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED) { 5460 pBuffer = 5461 &mpt->m_fw_diag_buffer_list[buffer_type]; 5462 pBuffer->valid_data = TRUE; 5463 pBuffer->owned_by_firmware = FALSE; 5464 pBuffer->immediate = FALSE; 5465 } 5466 } else { 5467 /* 5468 * Normal handling of diag post reply with SMID. 5469 */ 5470 cmd = slots->m_slot[SMID]; 5471 5472 /* 5473 * print warning and return if the slot is empty 5474 */ 5475 if (cmd == NULL) { 5476 mptsas_log(mpt, CE_WARN, "?NULL command for " 5477 "address reply in slot %d", SMID); 5478 return; 5479 } 5480 cmd->cmd_rfm = reply_addr; 5481 cmd->cmd_flags |= CFLAG_FINISHED; 5482 cv_broadcast(&mpt->m_fw_diag_cv); 5483 } 5484 return; 5485 default: 5486 mptsas_log(mpt, CE_WARN, "Unknown function 0x%x ", function); 5487 break; 5488 } 5489 5490 /* 5491 * Return the reply frame to the free queue. 5492 */ 5493 ddi_put32(mpt->m_acc_free_queue_hdl, 5494 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], 5495 reply_addr); 5496 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 5497 DDI_DMA_SYNC_FORDEV); 5498 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 5499 mpt->m_free_index = 0; 5500 } 5501 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 5502 mpt->m_free_index); 5503 5504 if (cmd->cmd_flags & CFLAG_FW_CMD) 5505 return; 5506 5507 if (cmd->cmd_flags & CFLAG_RETRY) { 5508 /* 5509 * The target returned QFULL or busy, do not add this 5510 * pkt to the doneq since the hba will retry 5511 * this cmd. 5512 * 5513 * The pkt has already been resubmitted in 5514 * mptsas_handle_qfull() or in mptsas_check_scsi_io_error(). 5515 * Remove this cmd_flag here. 5516 */ 5517 cmd->cmd_flags &= ~CFLAG_RETRY; 5518 } else { 5519 mptsas_doneq_add(mpt, cmd); 5520 } 5521 } 5522 5523 #ifdef MPTSAS_DEBUG 5524 static uint8_t mptsas_last_sense[256]; 5525 #endif 5526 5527 static void 5528 mptsas_check_scsi_io_error(mptsas_t *mpt, pMpi2SCSIIOReply_t reply, 5529 mptsas_cmd_t *cmd) 5530 { 5531 uint8_t scsi_status, scsi_state; 5532 uint16_t ioc_status, cmd_rqs_len; 5533 uint32_t xferred, sensecount, responsedata, loginfo = 0; 5534 struct scsi_pkt *pkt; 5535 struct scsi_arq_status *arqstat; 5536 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 5537 uint8_t *sensedata = NULL; 5538 uint64_t sas_wwn; 5539 uint8_t phy; 5540 char wwn_str[MPTSAS_WWN_STRLEN]; 5541 5542 scsi_status = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIStatus); 5543 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus); 5544 scsi_state = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->SCSIState); 5545 xferred = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->TransferCount); 5546 sensecount = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->SenseCount); 5547 responsedata = ddi_get32(mpt->m_acc_reply_frame_hdl, 5548 &reply->ResponseInfo); 5549 5550 if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { 5551 sas_wwn = ptgt->m_addr.mta_wwn; 5552 phy = ptgt->m_phynum; 5553 if (sas_wwn == 0) { 5554 (void) sprintf(wwn_str, "p%x", phy); 5555 } else { 5556 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn); 5557 } 5558 loginfo = ddi_get32(mpt->m_acc_reply_frame_hdl, 5559 &reply->IOCLogInfo); 5560 mptsas_log(mpt, CE_NOTE, 5561 "?Log info 0x%x received for target %d %s.\n" 5562 "\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x", 5563 loginfo, Tgt(cmd), wwn_str, scsi_status, ioc_status, 5564 scsi_state); 5565 } 5566 5567 NDBG31(("\t\tscsi_status=0x%x, ioc_status=0x%x, scsi_state=0x%x", 5568 scsi_status, ioc_status, scsi_state)); 5569 5570 pkt = CMD2PKT(cmd); 5571 *(pkt->pkt_scbp) = scsi_status; 5572 5573 if (loginfo == 0x31170000) { 5574 /* 5575 * if loginfo PL_LOGINFO_CODE_IO_DEVICE_MISSING_DELAY_RETRY 5576 * 0x31170000 comes, that means the device missing delay 5577 * is in progressing, the command need retry later. 5578 */ 5579 *(pkt->pkt_scbp) = STATUS_BUSY; 5580 return; 5581 } 5582 5583 if ((scsi_state & MPI2_SCSI_STATE_NO_SCSI_STATUS) && 5584 ((ioc_status & MPI2_IOCSTATUS_MASK) == 5585 MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE)) { 5586 pkt->pkt_reason = CMD_INCOMPLETE; 5587 pkt->pkt_state |= STATE_GOT_BUS; 5588 if (ptgt->m_reset_delay == 0) { 5589 mptsas_set_throttle(mpt, ptgt, 5590 DRAIN_THROTTLE); 5591 } 5592 return; 5593 } 5594 5595 if (scsi_state & MPI2_SCSI_STATE_RESPONSE_INFO_VALID) { 5596 responsedata &= 0x000000FF; 5597 if (responsedata & MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF) { 5598 mptsas_log(mpt, CE_NOTE, "Do not support the TLR\n"); 5599 pkt->pkt_reason = CMD_TLR_OFF; 5600 return; 5601 } 5602 } 5603 5604 5605 switch (scsi_status) { 5606 case MPI2_SCSI_STATUS_CHECK_CONDITION: 5607 pkt->pkt_resid = (cmd->cmd_dmacount - xferred); 5608 arqstat = (void*)(pkt->pkt_scbp); 5609 arqstat->sts_rqpkt_status = *((struct scsi_status *) 5610 (pkt->pkt_scbp)); 5611 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET | 5612 STATE_SENT_CMD | STATE_GOT_STATUS | STATE_ARQ_DONE); 5613 if (cmd->cmd_flags & CFLAG_XARQ) { 5614 pkt->pkt_state |= STATE_XARQ_DONE; 5615 } 5616 if (pkt->pkt_resid != cmd->cmd_dmacount) { 5617 pkt->pkt_state |= STATE_XFERRED_DATA; 5618 } 5619 arqstat->sts_rqpkt_reason = pkt->pkt_reason; 5620 arqstat->sts_rqpkt_state = pkt->pkt_state; 5621 arqstat->sts_rqpkt_state |= STATE_XFERRED_DATA; 5622 arqstat->sts_rqpkt_statistics = pkt->pkt_statistics; 5623 sensedata = (uint8_t *)&arqstat->sts_sensedata; 5624 cmd_rqs_len = cmd->cmd_extrqslen ? 5625 cmd->cmd_extrqslen : cmd->cmd_rqslen; 5626 (void) ddi_dma_sync(mpt->m_dma_req_sense_hdl, 0, 0, 5627 DDI_DMA_SYNC_FORKERNEL); 5628 #ifdef MPTSAS_DEBUG 5629 bcopy(cmd->cmd_arq_buf, mptsas_last_sense, 5630 ((cmd_rqs_len >= sizeof (mptsas_last_sense)) ? 5631 sizeof (mptsas_last_sense):cmd_rqs_len)); 5632 #endif 5633 bcopy((uchar_t *)cmd->cmd_arq_buf, sensedata, 5634 ((cmd_rqs_len >= sensecount) ? sensecount : 5635 cmd_rqs_len)); 5636 arqstat->sts_rqpkt_resid = (cmd_rqs_len - sensecount); 5637 cmd->cmd_flags |= CFLAG_CMDARQ; 5638 /* 5639 * Set proper status for pkt if autosense was valid 5640 */ 5641 if (scsi_state & MPI2_SCSI_STATE_AUTOSENSE_VALID) { 5642 struct scsi_status zero_status = { 0 }; 5643 arqstat->sts_rqpkt_status = zero_status; 5644 } 5645 5646 /* 5647 * ASC=0x47 is parity error 5648 * ASC=0x48 is initiator detected error received 5649 */ 5650 if ((scsi_sense_key(sensedata) == KEY_ABORTED_COMMAND) && 5651 ((scsi_sense_asc(sensedata) == 0x47) || 5652 (scsi_sense_asc(sensedata) == 0x48))) { 5653 mptsas_log(mpt, CE_NOTE, "Aborted_command!"); 5654 } 5655 5656 /* 5657 * ASC/ASCQ=0x3F/0x0E means report_luns data changed 5658 * ASC/ASCQ=0x25/0x00 means invalid lun 5659 */ 5660 if (((scsi_sense_key(sensedata) == KEY_UNIT_ATTENTION) && 5661 (scsi_sense_asc(sensedata) == 0x3F) && 5662 (scsi_sense_ascq(sensedata) == 0x0E)) || 5663 ((scsi_sense_key(sensedata) == KEY_ILLEGAL_REQUEST) && 5664 (scsi_sense_asc(sensedata) == 0x25) && 5665 (scsi_sense_ascq(sensedata) == 0x00))) { 5666 mptsas_topo_change_list_t *topo_node = NULL; 5667 5668 topo_node = kmem_zalloc( 5669 sizeof (mptsas_topo_change_list_t), 5670 KM_NOSLEEP); 5671 if (topo_node == NULL) { 5672 mptsas_log(mpt, CE_NOTE, "No memory" 5673 "resource for handle SAS dynamic" 5674 "reconfigure.\n"); 5675 break; 5676 } 5677 topo_node->mpt = mpt; 5678 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_TARGET; 5679 topo_node->un.phymask = ptgt->m_addr.mta_phymask; 5680 topo_node->devhdl = ptgt->m_devhdl; 5681 topo_node->object = (void *)ptgt; 5682 topo_node->flags = MPTSAS_TOPO_FLAG_LUN_ASSOCIATED; 5683 5684 if ((ddi_taskq_dispatch(mpt->m_dr_taskq, 5685 mptsas_handle_dr, 5686 (void *)topo_node, 5687 DDI_NOSLEEP)) != DDI_SUCCESS) { 5688 kmem_free(topo_node, 5689 sizeof (mptsas_topo_change_list_t)); 5690 mptsas_log(mpt, CE_NOTE, "mptsas start taskq" 5691 "for handle SAS dynamic reconfigure" 5692 "failed. \n"); 5693 } 5694 } 5695 break; 5696 case MPI2_SCSI_STATUS_GOOD: 5697 switch (ioc_status & MPI2_IOCSTATUS_MASK) { 5698 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE: 5699 pkt->pkt_reason = CMD_DEV_GONE; 5700 pkt->pkt_state |= STATE_GOT_BUS; 5701 if (ptgt->m_reset_delay == 0) { 5702 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 5703 } 5704 NDBG31(("lost disk for target%d, command:%x", 5705 Tgt(cmd), pkt->pkt_cdbp[0])); 5706 break; 5707 case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN: 5708 NDBG31(("data overrun: xferred=%d", xferred)); 5709 NDBG31(("dmacount=%d", cmd->cmd_dmacount)); 5710 pkt->pkt_reason = CMD_DATA_OVR; 5711 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET 5712 | STATE_SENT_CMD | STATE_GOT_STATUS 5713 | STATE_XFERRED_DATA); 5714 pkt->pkt_resid = 0; 5715 break; 5716 case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: 5717 case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN: 5718 NDBG31(("data underrun: xferred=%d", xferred)); 5719 NDBG31(("dmacount=%d", cmd->cmd_dmacount)); 5720 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET 5721 | STATE_SENT_CMD | STATE_GOT_STATUS); 5722 pkt->pkt_resid = (cmd->cmd_dmacount - xferred); 5723 if (pkt->pkt_resid != cmd->cmd_dmacount) { 5724 pkt->pkt_state |= STATE_XFERRED_DATA; 5725 } 5726 break; 5727 case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED: 5728 if (cmd->cmd_active_expiration <= gethrtime()) { 5729 /* 5730 * When timeout requested, propagate 5731 * proper reason and statistics to 5732 * target drivers. 5733 */ 5734 mptsas_set_pkt_reason(mpt, cmd, CMD_TIMEOUT, 5735 STAT_BUS_RESET | STAT_TIMEOUT); 5736 } else { 5737 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, 5738 STAT_BUS_RESET); 5739 } 5740 break; 5741 case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED: 5742 case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED: 5743 mptsas_set_pkt_reason(mpt, 5744 cmd, CMD_RESET, STAT_DEV_RESET); 5745 break; 5746 case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR: 5747 case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR: 5748 pkt->pkt_state |= (STATE_GOT_BUS | STATE_GOT_TARGET); 5749 mptsas_set_pkt_reason(mpt, 5750 cmd, CMD_TERMINATED, STAT_TERMINATED); 5751 break; 5752 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES: 5753 case MPI2_IOCSTATUS_BUSY: 5754 /* 5755 * set throttles to drain 5756 */ 5757 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 5758 ptgt = refhash_next(mpt->m_targets, ptgt)) { 5759 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 5760 } 5761 5762 /* 5763 * retry command 5764 */ 5765 cmd->cmd_flags |= CFLAG_RETRY; 5766 cmd->cmd_pkt_flags |= FLAG_HEAD; 5767 5768 (void) mptsas_accept_pkt(mpt, cmd); 5769 break; 5770 default: 5771 mptsas_log(mpt, CE_WARN, 5772 "unknown ioc_status = %x\n", ioc_status); 5773 mptsas_log(mpt, CE_CONT, "scsi_state = %x, transfer " 5774 "count = %x, scsi_status = %x", scsi_state, 5775 xferred, scsi_status); 5776 break; 5777 } 5778 break; 5779 case MPI2_SCSI_STATUS_TASK_SET_FULL: 5780 mptsas_handle_qfull(mpt, cmd); 5781 break; 5782 case MPI2_SCSI_STATUS_BUSY: 5783 NDBG31(("scsi_status busy received")); 5784 break; 5785 case MPI2_SCSI_STATUS_RESERVATION_CONFLICT: 5786 NDBG31(("scsi_status reservation conflict received")); 5787 break; 5788 default: 5789 mptsas_log(mpt, CE_WARN, "scsi_status=%x, ioc_status=%x\n", 5790 scsi_status, ioc_status); 5791 mptsas_log(mpt, CE_WARN, 5792 "mptsas_process_intr: invalid scsi status\n"); 5793 break; 5794 } 5795 } 5796 5797 static void 5798 mptsas_check_task_mgt(mptsas_t *mpt, pMpi2SCSIManagementReply_t reply, 5799 mptsas_cmd_t *cmd) 5800 { 5801 uint8_t task_type; 5802 uint16_t ioc_status; 5803 uint32_t log_info; 5804 uint16_t dev_handle; 5805 struct scsi_pkt *pkt = CMD2PKT(cmd); 5806 5807 task_type = ddi_get8(mpt->m_acc_reply_frame_hdl, &reply->TaskType); 5808 ioc_status = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->IOCStatus); 5809 log_info = ddi_get32(mpt->m_acc_reply_frame_hdl, &reply->IOCLogInfo); 5810 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, &reply->DevHandle); 5811 5812 if (ioc_status != MPI2_IOCSTATUS_SUCCESS) { 5813 mptsas_log(mpt, CE_WARN, "mptsas_check_task_mgt: Task 0x%x " 5814 "failed. IOCStatus=0x%x IOCLogInfo=0x%x target=%d\n", 5815 task_type, ioc_status, log_info, dev_handle); 5816 pkt->pkt_reason = CMD_INCOMPLETE; 5817 return; 5818 } 5819 5820 switch (task_type) { 5821 case MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK: 5822 case MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET: 5823 case MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK: 5824 case MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA: 5825 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET: 5826 case MPI2_SCSITASKMGMT_TASKTYPE_QRY_UNIT_ATTENTION: 5827 break; 5828 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET: 5829 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET: 5830 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET: 5831 /* 5832 * Check for invalid DevHandle of 0 in case application 5833 * sends bad command. DevHandle of 0 could cause problems. 5834 */ 5835 if (dev_handle == 0) { 5836 mptsas_log(mpt, CE_WARN, "!Can't flush target with" 5837 " DevHandle of 0."); 5838 } else { 5839 mptsas_flush_target(mpt, dev_handle, Lun(cmd), 5840 task_type); 5841 } 5842 break; 5843 default: 5844 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.", 5845 task_type); 5846 mptsas_log(mpt, CE_WARN, "ioc status = %x", ioc_status); 5847 break; 5848 } 5849 } 5850 5851 static void 5852 mptsas_doneq_thread(mptsas_doneq_thread_arg_t *arg) 5853 { 5854 mptsas_t *mpt = arg->mpt; 5855 uint64_t t = arg->t; 5856 mptsas_cmd_t *cmd; 5857 struct scsi_pkt *pkt; 5858 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t]; 5859 5860 mutex_enter(&item->mutex); 5861 while (item->flag & MPTSAS_DONEQ_THREAD_ACTIVE) { 5862 if (!item->doneq) { 5863 cv_wait(&item->cv, &item->mutex); 5864 } 5865 pkt = NULL; 5866 if ((cmd = mptsas_doneq_thread_rm(mpt, t)) != NULL) { 5867 cmd->cmd_flags |= CFLAG_COMPLETED; 5868 pkt = CMD2PKT(cmd); 5869 } 5870 mutex_exit(&item->mutex); 5871 if (pkt) { 5872 mptsas_pkt_comp(pkt, cmd); 5873 } 5874 mutex_enter(&item->mutex); 5875 } 5876 mutex_exit(&item->mutex); 5877 mutex_enter(&mpt->m_doneq_mutex); 5878 mpt->m_doneq_thread_n--; 5879 cv_broadcast(&mpt->m_doneq_thread_cv); 5880 mutex_exit(&mpt->m_doneq_mutex); 5881 } 5882 5883 5884 /* 5885 * mpt interrupt handler. 5886 */ 5887 static uint_t 5888 mptsas_intr(caddr_t arg1, caddr_t arg2) 5889 { 5890 mptsas_t *mpt = (void *)arg1; 5891 pMpi2ReplyDescriptorsUnion_t reply_desc_union; 5892 uchar_t did_reply = FALSE; 5893 5894 NDBG1(("mptsas_intr: arg1 0x%p arg2 0x%p", (void *)arg1, (void *)arg2)); 5895 5896 mutex_enter(&mpt->m_mutex); 5897 5898 /* 5899 * If interrupts are shared by two channels then check whether this 5900 * interrupt is genuinely for this channel by making sure first the 5901 * chip is in high power state. 5902 */ 5903 if ((mpt->m_options & MPTSAS_OPT_PM) && 5904 (mpt->m_power_level != PM_LEVEL_D0)) { 5905 mutex_exit(&mpt->m_mutex); 5906 return (DDI_INTR_UNCLAIMED); 5907 } 5908 5909 /* 5910 * If polling, interrupt was triggered by some shared interrupt because 5911 * IOC interrupts are disabled during polling, so polling routine will 5912 * handle any replies. Considering this, if polling is happening, 5913 * return with interrupt unclaimed. 5914 */ 5915 if (mpt->m_polled_intr) { 5916 mutex_exit(&mpt->m_mutex); 5917 mptsas_log(mpt, CE_WARN, "mpt_sas: Unclaimed interrupt"); 5918 return (DDI_INTR_UNCLAIMED); 5919 } 5920 5921 /* 5922 * Read the istat register. 5923 */ 5924 if ((INTPENDING(mpt)) != 0) { 5925 /* 5926 * read fifo until empty. 5927 */ 5928 #ifndef __lock_lint 5929 _NOTE(CONSTCOND) 5930 #endif 5931 while (TRUE) { 5932 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0, 5933 DDI_DMA_SYNC_FORCPU); 5934 reply_desc_union = (pMpi2ReplyDescriptorsUnion_t) 5935 MPTSAS_GET_NEXT_REPLY(mpt, mpt->m_post_index); 5936 5937 if (ddi_get32(mpt->m_acc_post_queue_hdl, 5938 &reply_desc_union->Words.Low) == 0xFFFFFFFF || 5939 ddi_get32(mpt->m_acc_post_queue_hdl, 5940 &reply_desc_union->Words.High) == 0xFFFFFFFF) { 5941 break; 5942 } 5943 5944 /* 5945 * The reply is valid, process it according to its 5946 * type. Also, set a flag for updating the reply index 5947 * after they've all been processed. 5948 */ 5949 did_reply = TRUE; 5950 5951 mptsas_process_intr(mpt, reply_desc_union); 5952 5953 /* 5954 * Increment post index and roll over if needed. 5955 */ 5956 if (++mpt->m_post_index == mpt->m_post_queue_depth) { 5957 mpt->m_post_index = 0; 5958 } 5959 } 5960 5961 /* 5962 * Update the global reply index if at least one reply was 5963 * processed. 5964 */ 5965 if (did_reply) { 5966 ddi_put32(mpt->m_datap, 5967 &mpt->m_reg->ReplyPostHostIndex, mpt->m_post_index); 5968 } 5969 } else { 5970 mutex_exit(&mpt->m_mutex); 5971 return (DDI_INTR_UNCLAIMED); 5972 } 5973 NDBG1(("mptsas_intr complete")); 5974 5975 /* 5976 * If no helper threads are created, process the doneq in ISR. If 5977 * helpers are created, use the doneq length as a metric to measure the 5978 * load on the interrupt CPU. If it is long enough, which indicates the 5979 * load is heavy, then we deliver the IO completions to the helpers. 5980 * This measurement has some limitations, although it is simple and 5981 * straightforward and works well for most of the cases at present. 5982 */ 5983 if (!mpt->m_doneq_thread_n || 5984 (mpt->m_doneq_len <= mpt->m_doneq_length_threshold)) { 5985 mptsas_doneq_empty(mpt); 5986 } else { 5987 mptsas_deliver_doneq_thread(mpt); 5988 } 5989 5990 /* 5991 * If there are queued cmd, start them now. 5992 */ 5993 if (mpt->m_waitq != NULL) { 5994 mptsas_restart_waitq(mpt); 5995 } 5996 5997 mutex_exit(&mpt->m_mutex); 5998 return (DDI_INTR_CLAIMED); 5999 } 6000 6001 static void 6002 mptsas_process_intr(mptsas_t *mpt, 6003 pMpi2ReplyDescriptorsUnion_t reply_desc_union) 6004 { 6005 uint8_t reply_type; 6006 6007 ASSERT(mutex_owned(&mpt->m_mutex)); 6008 6009 /* 6010 * The reply is valid, process it according to its 6011 * type. Also, set a flag for updated the reply index 6012 * after they've all been processed. 6013 */ 6014 reply_type = ddi_get8(mpt->m_acc_post_queue_hdl, 6015 &reply_desc_union->Default.ReplyFlags); 6016 reply_type &= MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; 6017 if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS || 6018 reply_type == MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS) { 6019 mptsas_handle_scsi_io_success(mpt, reply_desc_union); 6020 } else if (reply_type == MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) { 6021 mptsas_handle_address_reply(mpt, reply_desc_union); 6022 } else { 6023 mptsas_log(mpt, CE_WARN, "?Bad reply type %x", reply_type); 6024 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 6025 } 6026 6027 /* 6028 * Clear the reply descriptor for re-use and increment 6029 * index. 6030 */ 6031 ddi_put64(mpt->m_acc_post_queue_hdl, 6032 &((uint64_t *)(void *)mpt->m_post_queue)[mpt->m_post_index], 6033 0xFFFFFFFFFFFFFFFF); 6034 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0, 6035 DDI_DMA_SYNC_FORDEV); 6036 } 6037 6038 /* 6039 * handle qfull condition 6040 */ 6041 static void 6042 mptsas_handle_qfull(mptsas_t *mpt, mptsas_cmd_t *cmd) 6043 { 6044 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 6045 6046 if ((++cmd->cmd_qfull_retries > ptgt->m_qfull_retries) || 6047 (ptgt->m_qfull_retries == 0)) { 6048 /* 6049 * We have exhausted the retries on QFULL, or, 6050 * the target driver has indicated that it 6051 * wants to handle QFULL itself by setting 6052 * qfull-retries capability to 0. In either case 6053 * we want the target driver's QFULL handling 6054 * to kick in. We do this by having pkt_reason 6055 * as CMD_CMPLT and pkt_scbp as STATUS_QFULL. 6056 */ 6057 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 6058 } else { 6059 if (ptgt->m_reset_delay == 0) { 6060 ptgt->m_t_throttle = 6061 max((ptgt->m_t_ncmds - 2), 0); 6062 } 6063 6064 cmd->cmd_pkt_flags |= FLAG_HEAD; 6065 cmd->cmd_flags &= ~(CFLAG_TRANFLAG); 6066 cmd->cmd_flags |= CFLAG_RETRY; 6067 6068 (void) mptsas_accept_pkt(mpt, cmd); 6069 6070 /* 6071 * when target gives queue full status with no commands 6072 * outstanding (m_t_ncmds == 0), throttle is set to 0 6073 * (HOLD_THROTTLE), and the queue full handling start 6074 * (see psarc/1994/313); if there are commands outstanding, 6075 * throttle is set to (m_t_ncmds - 2) 6076 */ 6077 if (ptgt->m_t_throttle == HOLD_THROTTLE) { 6078 /* 6079 * By setting throttle to QFULL_THROTTLE, we 6080 * avoid submitting new commands and in 6081 * mptsas_restart_cmd find out slots which need 6082 * their throttles to be cleared. 6083 */ 6084 mptsas_set_throttle(mpt, ptgt, QFULL_THROTTLE); 6085 if (mpt->m_restart_cmd_timeid == 0) { 6086 mpt->m_restart_cmd_timeid = 6087 timeout(mptsas_restart_cmd, mpt, 6088 ptgt->m_qfull_retry_interval); 6089 } 6090 } 6091 } 6092 } 6093 6094 mptsas_phymask_t 6095 mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport) 6096 { 6097 mptsas_phymask_t phy_mask = 0; 6098 uint8_t i = 0; 6099 6100 NDBG20(("mptsas%d physport_to_phymask enter", mpt->m_instance)); 6101 6102 ASSERT(mutex_owned(&mpt->m_mutex)); 6103 6104 /* 6105 * If physport is 0xFF, this is a RAID volume. Use phymask of 0. 6106 */ 6107 if (physport == 0xFF) { 6108 return (0); 6109 } 6110 6111 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 6112 if (mpt->m_phy_info[i].attached_devhdl && 6113 (mpt->m_phy_info[i].phy_mask != 0) && 6114 (mpt->m_phy_info[i].port_num == physport)) { 6115 phy_mask = mpt->m_phy_info[i].phy_mask; 6116 break; 6117 } 6118 } 6119 NDBG20(("mptsas%d physport_to_phymask:physport :%x phymask :%x, ", 6120 mpt->m_instance, physport, phy_mask)); 6121 return (phy_mask); 6122 } 6123 6124 /* 6125 * mpt free device handle after device gone, by use of passthrough 6126 */ 6127 static int 6128 mptsas_free_devhdl(mptsas_t *mpt, uint16_t devhdl) 6129 { 6130 Mpi2SasIoUnitControlRequest_t req; 6131 Mpi2SasIoUnitControlReply_t rep; 6132 int ret; 6133 6134 ASSERT(mutex_owned(&mpt->m_mutex)); 6135 6136 /* 6137 * Need to compose a SAS IO Unit Control request message 6138 * and call mptsas_do_passthru() function 6139 */ 6140 bzero(&req, sizeof (req)); 6141 bzero(&rep, sizeof (rep)); 6142 6143 req.Function = MPI2_FUNCTION_SAS_IO_UNIT_CONTROL; 6144 req.Operation = MPI2_SAS_OP_REMOVE_DEVICE; 6145 req.DevHandle = LE_16(devhdl); 6146 6147 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL, 6148 sizeof (req), sizeof (rep), NULL, 0, NULL, 0, 60, FKIOCTL); 6149 if (ret != 0) { 6150 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit " 6151 "Control error %d", ret); 6152 return (DDI_FAILURE); 6153 } 6154 6155 /* do passthrough success, check the ioc status */ 6156 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) { 6157 cmn_err(CE_WARN, "mptsas_free_devhdl: passthru SAS IO Unit " 6158 "Control IOCStatus %d", LE_16(rep.IOCStatus)); 6159 return (DDI_FAILURE); 6160 } 6161 6162 return (DDI_SUCCESS); 6163 } 6164 6165 static void 6166 mptsas_update_phymask(mptsas_t *mpt) 6167 { 6168 mptsas_phymask_t mask = 0, phy_mask; 6169 char *phy_mask_name; 6170 uint8_t current_port; 6171 int i, j; 6172 6173 NDBG20(("mptsas%d update phymask ", mpt->m_instance)); 6174 6175 ASSERT(mutex_owned(&mpt->m_mutex)); 6176 6177 (void) mptsas_get_sas_io_unit_page(mpt); 6178 6179 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP); 6180 6181 for (i = 0; i < mpt->m_num_phys; i++) { 6182 phy_mask = 0x00; 6183 6184 if (mpt->m_phy_info[i].attached_devhdl == 0) 6185 continue; 6186 6187 bzero(phy_mask_name, sizeof (phy_mask_name)); 6188 6189 current_port = mpt->m_phy_info[i].port_num; 6190 6191 if ((mask & (1 << i)) != 0) 6192 continue; 6193 6194 for (j = 0; j < mpt->m_num_phys; j++) { 6195 if (mpt->m_phy_info[j].attached_devhdl && 6196 (mpt->m_phy_info[j].port_num == current_port)) { 6197 phy_mask |= (1 << j); 6198 } 6199 } 6200 mask = mask | phy_mask; 6201 6202 for (j = 0; j < mpt->m_num_phys; j++) { 6203 if ((phy_mask >> j) & 0x01) { 6204 mpt->m_phy_info[j].phy_mask = phy_mask; 6205 } 6206 } 6207 6208 (void) sprintf(phy_mask_name, "%x", phy_mask); 6209 6210 mutex_exit(&mpt->m_mutex); 6211 /* 6212 * register a iport, if the port has already been existed 6213 * SCSA will do nothing and just return. 6214 */ 6215 (void) scsi_hba_iport_register(mpt->m_dip, phy_mask_name); 6216 mutex_enter(&mpt->m_mutex); 6217 } 6218 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS); 6219 NDBG20(("mptsas%d update phymask return", mpt->m_instance)); 6220 } 6221 6222 /* 6223 * mptsas_handle_dr is a task handler for DR, the DR action includes: 6224 * 1. Directly attched Device Added/Removed. 6225 * 2. Expander Device Added/Removed. 6226 * 3. Indirectly Attached Device Added/Expander. 6227 * 4. LUNs of a existing device status change. 6228 * 5. RAID volume created/deleted. 6229 * 6. Member of RAID volume is released because of RAID deletion. 6230 * 7. Physical disks are removed because of RAID creation. 6231 */ 6232 static void 6233 mptsas_handle_dr(void *args) 6234 { 6235 mptsas_topo_change_list_t *topo_node = NULL; 6236 mptsas_topo_change_list_t *save_node = NULL; 6237 mptsas_t *mpt; 6238 dev_info_t *parent = NULL; 6239 mptsas_phymask_t phymask = 0; 6240 char *phy_mask_name; 6241 uint8_t flags = 0, physport = 0xff; 6242 uint8_t port_update = 0; 6243 uint_t event; 6244 6245 topo_node = (mptsas_topo_change_list_t *)args; 6246 6247 mpt = topo_node->mpt; 6248 event = topo_node->event; 6249 flags = topo_node->flags; 6250 6251 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP); 6252 6253 NDBG20(("mptsas%d handle_dr enter", mpt->m_instance)); 6254 6255 switch (event) { 6256 case MPTSAS_DR_EVENT_RECONFIG_TARGET: 6257 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) || 6258 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE) || 6259 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) { 6260 /* 6261 * Direct attached or expander attached device added 6262 * into system or a Phys Disk that is being unhidden. 6263 */ 6264 port_update = 1; 6265 } 6266 break; 6267 case MPTSAS_DR_EVENT_RECONFIG_SMP: 6268 /* 6269 * New expander added into system, it must be the head 6270 * of topo_change_list_t 6271 */ 6272 port_update = 1; 6273 break; 6274 default: 6275 port_update = 0; 6276 break; 6277 } 6278 /* 6279 * All cases port_update == 1 may cause initiator port form change 6280 */ 6281 mutex_enter(&mpt->m_mutex); 6282 if (mpt->m_port_chng && port_update) { 6283 /* 6284 * mpt->m_port_chng flag indicates some PHYs of initiator 6285 * port have changed to online. So when expander added or 6286 * directly attached device online event come, we force to 6287 * update port information by issueing SAS IO Unit Page and 6288 * update PHYMASKs. 6289 */ 6290 (void) mptsas_update_phymask(mpt); 6291 mpt->m_port_chng = 0; 6292 6293 } 6294 mutex_exit(&mpt->m_mutex); 6295 while (topo_node) { 6296 phymask = 0; 6297 if (parent == NULL) { 6298 physport = topo_node->un.physport; 6299 event = topo_node->event; 6300 flags = topo_node->flags; 6301 if (event & (MPTSAS_DR_EVENT_OFFLINE_TARGET | 6302 MPTSAS_DR_EVENT_OFFLINE_SMP)) { 6303 /* 6304 * For all offline events, phymask is known 6305 */ 6306 phymask = topo_node->un.phymask; 6307 goto find_parent; 6308 } 6309 if (event & MPTSAS_TOPO_FLAG_REMOVE_HANDLE) { 6310 goto handle_topo_change; 6311 } 6312 if (flags & MPTSAS_TOPO_FLAG_LUN_ASSOCIATED) { 6313 phymask = topo_node->un.phymask; 6314 goto find_parent; 6315 } 6316 6317 if ((flags == 6318 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) && 6319 (event == MPTSAS_DR_EVENT_RECONFIG_TARGET)) { 6320 /* 6321 * There is no any field in IR_CONFIG_CHANGE 6322 * event indicate physport/phynum, let's get 6323 * parent after SAS Device Page0 request. 6324 */ 6325 goto handle_topo_change; 6326 } 6327 6328 mutex_enter(&mpt->m_mutex); 6329 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) { 6330 /* 6331 * If the direct attached device added or a 6332 * phys disk is being unhidden, argument 6333 * physport actually is PHY#, so we have to get 6334 * phymask according PHY#. 6335 */ 6336 physport = mpt->m_phy_info[physport].port_num; 6337 } 6338 6339 /* 6340 * Translate physport to phymask so that we can search 6341 * parent dip. 6342 */ 6343 phymask = mptsas_physport_to_phymask(mpt, 6344 physport); 6345 mutex_exit(&mpt->m_mutex); 6346 6347 find_parent: 6348 bzero(phy_mask_name, MPTSAS_MAX_PHYS); 6349 /* 6350 * For RAID topology change node, write the iport name 6351 * as v0. 6352 */ 6353 if (flags & MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) { 6354 (void) sprintf(phy_mask_name, "v0"); 6355 } else { 6356 /* 6357 * phymask can bo 0 if the drive has been 6358 * pulled by the time an add event is 6359 * processed. If phymask is 0, just skip this 6360 * event and continue. 6361 */ 6362 if (phymask == 0) { 6363 mutex_enter(&mpt->m_mutex); 6364 save_node = topo_node; 6365 topo_node = topo_node->next; 6366 ASSERT(save_node); 6367 kmem_free(save_node, 6368 sizeof (mptsas_topo_change_list_t)); 6369 mutex_exit(&mpt->m_mutex); 6370 6371 parent = NULL; 6372 continue; 6373 } 6374 (void) sprintf(phy_mask_name, "%x", phymask); 6375 } 6376 parent = scsi_hba_iport_find(mpt->m_dip, 6377 phy_mask_name); 6378 if (parent == NULL) { 6379 mptsas_log(mpt, CE_WARN, "Failed to find an " 6380 "iport, should not happen!"); 6381 goto out; 6382 } 6383 6384 } 6385 ASSERT(parent); 6386 handle_topo_change: 6387 6388 mutex_enter(&mpt->m_mutex); 6389 /* 6390 * If HBA is being reset, don't perform operations depending 6391 * on the IOC. We must free the topo list, however. 6392 */ 6393 if (!mpt->m_in_reset) 6394 mptsas_handle_topo_change(topo_node, parent); 6395 else 6396 NDBG20(("skipping topo change received during reset")); 6397 save_node = topo_node; 6398 topo_node = topo_node->next; 6399 ASSERT(save_node); 6400 kmem_free(save_node, sizeof (mptsas_topo_change_list_t)); 6401 mutex_exit(&mpt->m_mutex); 6402 6403 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) || 6404 (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) || 6405 (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED)) { 6406 /* 6407 * If direct attached device associated, make sure 6408 * reset the parent before start the next one. But 6409 * all devices associated with expander shares the 6410 * parent. Also, reset parent if this is for RAID. 6411 */ 6412 parent = NULL; 6413 } 6414 } 6415 out: 6416 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS); 6417 } 6418 6419 static void 6420 mptsas_handle_topo_change(mptsas_topo_change_list_t *topo_node, 6421 dev_info_t *parent) 6422 { 6423 mptsas_target_t *ptgt = NULL; 6424 mptsas_smp_t *psmp = NULL; 6425 mptsas_t *mpt = (void *)topo_node->mpt; 6426 uint16_t devhdl; 6427 uint16_t attached_devhdl; 6428 uint64_t sas_wwn = 0; 6429 int rval = 0; 6430 uint32_t page_address; 6431 uint8_t phy, flags; 6432 char *addr = NULL; 6433 dev_info_t *lundip; 6434 int circ = 0, circ1 = 0; 6435 char attached_wwnstr[MPTSAS_WWN_STRLEN]; 6436 6437 NDBG20(("mptsas%d handle_topo_change enter, devhdl 0x%x," 6438 "event 0x%x, flags 0x%x", mpt->m_instance, topo_node->devhdl, 6439 topo_node->event, topo_node->flags)); 6440 6441 ASSERT(mutex_owned(&mpt->m_mutex)); 6442 6443 switch (topo_node->event) { 6444 case MPTSAS_DR_EVENT_RECONFIG_TARGET: 6445 { 6446 char *phy_mask_name; 6447 mptsas_phymask_t phymask = 0; 6448 6449 if (topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) { 6450 /* 6451 * Get latest RAID info. 6452 */ 6453 (void) mptsas_get_raid_info(mpt); 6454 ptgt = refhash_linear_search(mpt->m_targets, 6455 mptsas_target_eval_devhdl, &topo_node->devhdl); 6456 if (ptgt == NULL) 6457 break; 6458 } else { 6459 ptgt = (void *)topo_node->object; 6460 } 6461 6462 if (ptgt == NULL) { 6463 /* 6464 * If a Phys Disk was deleted, RAID info needs to be 6465 * updated to reflect the new topology. 6466 */ 6467 (void) mptsas_get_raid_info(mpt); 6468 6469 /* 6470 * Get sas device page 0 by DevHandle to make sure if 6471 * SSP/SATA end device exist. 6472 */ 6473 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 6474 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 6475 topo_node->devhdl; 6476 6477 rval = mptsas_get_target_device_info(mpt, page_address, 6478 &devhdl, &ptgt); 6479 if (rval == DEV_INFO_WRONG_DEVICE_TYPE) { 6480 mptsas_log(mpt, CE_NOTE, 6481 "mptsas_handle_topo_change: target %d is " 6482 "not a SAS/SATA device. \n", 6483 topo_node->devhdl); 6484 } else if (rval == DEV_INFO_FAIL_ALLOC) { 6485 mptsas_log(mpt, CE_NOTE, 6486 "mptsas_handle_topo_change: could not " 6487 "allocate memory. \n"); 6488 } else if (rval == DEV_INFO_FAIL_GUID) { 6489 mptsas_log(mpt, CE_NOTE, 6490 "mptsas_handle_topo_change: could not " 6491 "get SATA GUID for target %d. \n", 6492 topo_node->devhdl); 6493 } 6494 /* 6495 * If rval is DEV_INFO_PHYS_DISK or indicates failure 6496 * then there is nothing else to do, just leave. 6497 */ 6498 if (rval != DEV_INFO_SUCCESS) { 6499 return; 6500 } 6501 } 6502 6503 ASSERT(ptgt->m_devhdl == topo_node->devhdl); 6504 6505 mutex_exit(&mpt->m_mutex); 6506 flags = topo_node->flags; 6507 6508 if (flags == MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED) { 6509 phymask = ptgt->m_addr.mta_phymask; 6510 phy_mask_name = kmem_zalloc(MPTSAS_MAX_PHYS, KM_SLEEP); 6511 (void) sprintf(phy_mask_name, "%x", phymask); 6512 parent = scsi_hba_iport_find(mpt->m_dip, 6513 phy_mask_name); 6514 kmem_free(phy_mask_name, MPTSAS_MAX_PHYS); 6515 if (parent == NULL) { 6516 mptsas_log(mpt, CE_WARN, "Failed to find a " 6517 "iport for PD, should not happen!"); 6518 mutex_enter(&mpt->m_mutex); 6519 break; 6520 } 6521 } 6522 6523 if (flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) { 6524 ndi_devi_enter(parent, &circ1); 6525 (void) mptsas_config_raid(parent, topo_node->devhdl, 6526 &lundip); 6527 ndi_devi_exit(parent, circ1); 6528 } else { 6529 /* 6530 * hold nexus for bus configure 6531 */ 6532 ndi_devi_enter(scsi_vhci_dip, &circ); 6533 ndi_devi_enter(parent, &circ1); 6534 rval = mptsas_config_target(parent, ptgt); 6535 /* 6536 * release nexus for bus configure 6537 */ 6538 ndi_devi_exit(parent, circ1); 6539 ndi_devi_exit(scsi_vhci_dip, circ); 6540 6541 /* 6542 * Add parent's props for SMHBA support 6543 */ 6544 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) { 6545 bzero(attached_wwnstr, 6546 sizeof (attached_wwnstr)); 6547 (void) sprintf(attached_wwnstr, "w%016"PRIx64, 6548 ptgt->m_addr.mta_wwn); 6549 if (ddi_prop_update_string(DDI_DEV_T_NONE, 6550 parent, 6551 SCSI_ADDR_PROP_ATTACHED_PORT, 6552 attached_wwnstr) 6553 != DDI_PROP_SUCCESS) { 6554 (void) ddi_prop_remove(DDI_DEV_T_NONE, 6555 parent, 6556 SCSI_ADDR_PROP_ATTACHED_PORT); 6557 mptsas_log(mpt, CE_WARN, "Failed to" 6558 "attached-port props"); 6559 return; 6560 } 6561 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6562 MPTSAS_NUM_PHYS, 1) != 6563 DDI_PROP_SUCCESS) { 6564 (void) ddi_prop_remove(DDI_DEV_T_NONE, 6565 parent, MPTSAS_NUM_PHYS); 6566 mptsas_log(mpt, CE_WARN, "Failed to" 6567 " create num-phys props"); 6568 return; 6569 } 6570 6571 /* 6572 * Update PHY info for smhba 6573 */ 6574 mutex_enter(&mpt->m_mutex); 6575 if (mptsas_smhba_phy_init(mpt)) { 6576 mutex_exit(&mpt->m_mutex); 6577 mptsas_log(mpt, CE_WARN, "mptsas phy" 6578 " update failed"); 6579 return; 6580 } 6581 mutex_exit(&mpt->m_mutex); 6582 6583 /* 6584 * topo_node->un.physport is really the PHY# 6585 * for direct attached devices 6586 */ 6587 mptsas_smhba_set_one_phy_props(mpt, parent, 6588 topo_node->un.physport, &attached_devhdl); 6589 6590 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6591 MPTSAS_VIRTUAL_PORT, 0) != 6592 DDI_PROP_SUCCESS) { 6593 (void) ddi_prop_remove(DDI_DEV_T_NONE, 6594 parent, MPTSAS_VIRTUAL_PORT); 6595 mptsas_log(mpt, CE_WARN, 6596 "mptsas virtual-port" 6597 "port prop update failed"); 6598 return; 6599 } 6600 } 6601 } 6602 mutex_enter(&mpt->m_mutex); 6603 6604 NDBG20(("mptsas%d handle_topo_change to online devhdl:%x, " 6605 "phymask:%x.", mpt->m_instance, ptgt->m_devhdl, 6606 ptgt->m_addr.mta_phymask)); 6607 break; 6608 } 6609 case MPTSAS_DR_EVENT_OFFLINE_TARGET: 6610 { 6611 devhdl = topo_node->devhdl; 6612 ptgt = refhash_linear_search(mpt->m_targets, 6613 mptsas_target_eval_devhdl, &devhdl); 6614 if (ptgt == NULL) 6615 break; 6616 6617 sas_wwn = ptgt->m_addr.mta_wwn; 6618 phy = ptgt->m_phynum; 6619 6620 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 6621 6622 if (sas_wwn) { 6623 (void) sprintf(addr, "w%016"PRIx64, sas_wwn); 6624 } else { 6625 (void) sprintf(addr, "p%x", phy); 6626 } 6627 ASSERT(ptgt->m_devhdl == devhdl); 6628 6629 if ((topo_node->flags == MPTSAS_TOPO_FLAG_RAID_ASSOCIATED) || 6630 (topo_node->flags == 6631 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED)) { 6632 /* 6633 * Get latest RAID info if RAID volume status changes 6634 * or Phys Disk status changes 6635 */ 6636 (void) mptsas_get_raid_info(mpt); 6637 } 6638 /* 6639 * Abort all outstanding command on the device 6640 */ 6641 rval = mptsas_do_scsi_reset(mpt, devhdl); 6642 if (rval) { 6643 NDBG20(("mptsas%d handle_topo_change to reset target " 6644 "before offline devhdl:%x, phymask:%x, rval:%x", 6645 mpt->m_instance, ptgt->m_devhdl, 6646 ptgt->m_addr.mta_phymask, rval)); 6647 } 6648 6649 mutex_exit(&mpt->m_mutex); 6650 6651 ndi_devi_enter(scsi_vhci_dip, &circ); 6652 ndi_devi_enter(parent, &circ1); 6653 rval = mptsas_offline_target(parent, addr); 6654 ndi_devi_exit(parent, circ1); 6655 ndi_devi_exit(scsi_vhci_dip, circ); 6656 NDBG20(("mptsas%d handle_topo_change to offline devhdl:%x, " 6657 "phymask:%x, rval:%x", mpt->m_instance, 6658 ptgt->m_devhdl, ptgt->m_addr.mta_phymask, rval)); 6659 6660 kmem_free(addr, SCSI_MAXNAMELEN); 6661 6662 /* 6663 * Clear parent's props for SMHBA support 6664 */ 6665 flags = topo_node->flags; 6666 if (flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) { 6667 bzero(attached_wwnstr, sizeof (attached_wwnstr)); 6668 if (ddi_prop_update_string(DDI_DEV_T_NONE, parent, 6669 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) != 6670 DDI_PROP_SUCCESS) { 6671 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6672 SCSI_ADDR_PROP_ATTACHED_PORT); 6673 mptsas_log(mpt, CE_WARN, "mptsas attached port " 6674 "prop update failed"); 6675 break; 6676 } 6677 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6678 MPTSAS_NUM_PHYS, 0) != 6679 DDI_PROP_SUCCESS) { 6680 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6681 MPTSAS_NUM_PHYS); 6682 mptsas_log(mpt, CE_WARN, "mptsas num phys " 6683 "prop update failed"); 6684 break; 6685 } 6686 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6687 MPTSAS_VIRTUAL_PORT, 1) != 6688 DDI_PROP_SUCCESS) { 6689 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6690 MPTSAS_VIRTUAL_PORT); 6691 mptsas_log(mpt, CE_WARN, "mptsas virtual port " 6692 "prop update failed"); 6693 break; 6694 } 6695 } 6696 6697 mutex_enter(&mpt->m_mutex); 6698 ptgt->m_led_status = 0; 6699 (void) mptsas_flush_led_status(mpt, ptgt); 6700 if (rval == DDI_SUCCESS) { 6701 refhash_remove(mpt->m_targets, ptgt); 6702 ptgt = NULL; 6703 } else { 6704 /* 6705 * clean DR_INTRANSITION flag to allow I/O down to 6706 * PHCI driver since failover finished. 6707 * Invalidate the devhdl 6708 */ 6709 ptgt->m_devhdl = MPTSAS_INVALID_DEVHDL; 6710 ptgt->m_tgt_unconfigured = 0; 6711 mutex_enter(&mpt->m_tx_waitq_mutex); 6712 ptgt->m_dr_flag = MPTSAS_DR_INACTIVE; 6713 mutex_exit(&mpt->m_tx_waitq_mutex); 6714 } 6715 6716 /* 6717 * Send SAS IO Unit Control to free the dev handle 6718 */ 6719 if ((flags == MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE) || 6720 (flags == MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE)) { 6721 rval = mptsas_free_devhdl(mpt, devhdl); 6722 6723 NDBG20(("mptsas%d handle_topo_change to remove " 6724 "devhdl:%x, rval:%x", mpt->m_instance, devhdl, 6725 rval)); 6726 } 6727 6728 break; 6729 } 6730 case MPTSAS_TOPO_FLAG_REMOVE_HANDLE: 6731 { 6732 devhdl = topo_node->devhdl; 6733 /* 6734 * If this is the remove handle event, do a reset first. 6735 */ 6736 if (topo_node->event == MPTSAS_TOPO_FLAG_REMOVE_HANDLE) { 6737 rval = mptsas_do_scsi_reset(mpt, devhdl); 6738 if (rval) { 6739 NDBG20(("mpt%d reset target before remove " 6740 "devhdl:%x, rval:%x", mpt->m_instance, 6741 devhdl, rval)); 6742 } 6743 } 6744 6745 /* 6746 * Send SAS IO Unit Control to free the dev handle 6747 */ 6748 rval = mptsas_free_devhdl(mpt, devhdl); 6749 NDBG20(("mptsas%d handle_topo_change to remove " 6750 "devhdl:%x, rval:%x", mpt->m_instance, devhdl, 6751 rval)); 6752 break; 6753 } 6754 case MPTSAS_DR_EVENT_RECONFIG_SMP: 6755 { 6756 mptsas_smp_t smp; 6757 dev_info_t *smpdip; 6758 6759 devhdl = topo_node->devhdl; 6760 6761 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL & 6762 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)devhdl; 6763 rval = mptsas_get_sas_expander_page0(mpt, page_address, &smp); 6764 if (rval != DDI_SUCCESS) { 6765 mptsas_log(mpt, CE_WARN, "failed to online smp, " 6766 "handle %x", devhdl); 6767 return; 6768 } 6769 6770 psmp = mptsas_smp_alloc(mpt, &smp); 6771 if (psmp == NULL) { 6772 return; 6773 } 6774 6775 mutex_exit(&mpt->m_mutex); 6776 ndi_devi_enter(parent, &circ1); 6777 (void) mptsas_online_smp(parent, psmp, &smpdip); 6778 ndi_devi_exit(parent, circ1); 6779 6780 mutex_enter(&mpt->m_mutex); 6781 break; 6782 } 6783 case MPTSAS_DR_EVENT_OFFLINE_SMP: 6784 { 6785 devhdl = topo_node->devhdl; 6786 uint32_t dev_info; 6787 6788 psmp = refhash_linear_search(mpt->m_smp_targets, 6789 mptsas_smp_eval_devhdl, &devhdl); 6790 if (psmp == NULL) 6791 break; 6792 /* 6793 * The mptsas_smp_t data is released only if the dip is offlined 6794 * successfully. 6795 */ 6796 mutex_exit(&mpt->m_mutex); 6797 6798 ndi_devi_enter(parent, &circ1); 6799 rval = mptsas_offline_smp(parent, psmp, NDI_DEVI_REMOVE); 6800 ndi_devi_exit(parent, circ1); 6801 6802 dev_info = psmp->m_deviceinfo; 6803 if ((dev_info & DEVINFO_DIRECT_ATTACHED) == 6804 DEVINFO_DIRECT_ATTACHED) { 6805 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6806 MPTSAS_VIRTUAL_PORT, 1) != 6807 DDI_PROP_SUCCESS) { 6808 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6809 MPTSAS_VIRTUAL_PORT); 6810 mptsas_log(mpt, CE_WARN, "mptsas virtual port " 6811 "prop update failed"); 6812 return; 6813 } 6814 /* 6815 * Check whether the smp connected to the iport, 6816 */ 6817 if (ddi_prop_update_int(DDI_DEV_T_NONE, parent, 6818 MPTSAS_NUM_PHYS, 0) != 6819 DDI_PROP_SUCCESS) { 6820 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6821 MPTSAS_NUM_PHYS); 6822 mptsas_log(mpt, CE_WARN, "mptsas num phys" 6823 "prop update failed"); 6824 return; 6825 } 6826 /* 6827 * Clear parent's attached-port props 6828 */ 6829 bzero(attached_wwnstr, sizeof (attached_wwnstr)); 6830 if (ddi_prop_update_string(DDI_DEV_T_NONE, parent, 6831 SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwnstr) != 6832 DDI_PROP_SUCCESS) { 6833 (void) ddi_prop_remove(DDI_DEV_T_NONE, parent, 6834 SCSI_ADDR_PROP_ATTACHED_PORT); 6835 mptsas_log(mpt, CE_WARN, "mptsas attached port " 6836 "prop update failed"); 6837 return; 6838 } 6839 } 6840 6841 mutex_enter(&mpt->m_mutex); 6842 NDBG20(("mptsas%d handle_topo_change to remove devhdl:%x, " 6843 "rval:%x", mpt->m_instance, psmp->m_devhdl, rval)); 6844 if (rval == DDI_SUCCESS) { 6845 refhash_remove(mpt->m_smp_targets, psmp); 6846 } else { 6847 psmp->m_devhdl = MPTSAS_INVALID_DEVHDL; 6848 } 6849 6850 bzero(attached_wwnstr, sizeof (attached_wwnstr)); 6851 6852 break; 6853 } 6854 default: 6855 return; 6856 } 6857 } 6858 6859 /* 6860 * Record the event if its type is enabled in mpt instance by ioctl. 6861 */ 6862 static void 6863 mptsas_record_event(void *args) 6864 { 6865 m_replyh_arg_t *replyh_arg; 6866 pMpi2EventNotificationReply_t eventreply; 6867 uint32_t event, rfm; 6868 mptsas_t *mpt; 6869 int i, j; 6870 uint16_t event_data_len; 6871 boolean_t sendAEN = FALSE; 6872 6873 replyh_arg = (m_replyh_arg_t *)args; 6874 rfm = replyh_arg->rfm; 6875 mpt = replyh_arg->mpt; 6876 6877 eventreply = (pMpi2EventNotificationReply_t) 6878 (mpt->m_reply_frame + (rfm - 6879 (mpt->m_reply_frame_dma_addr & 0xffffffffu))); 6880 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event); 6881 6882 6883 /* 6884 * Generate a system event to let anyone who cares know that a 6885 * LOG_ENTRY_ADDED event has occurred. This is sent no matter what the 6886 * event mask is set to. 6887 */ 6888 if (event == MPI2_EVENT_LOG_ENTRY_ADDED) { 6889 sendAEN = TRUE; 6890 } 6891 6892 /* 6893 * Record the event only if it is not masked. Determine which dword 6894 * and bit of event mask to test. 6895 */ 6896 i = (uint8_t)(event / 32); 6897 j = (uint8_t)(event % 32); 6898 if ((i < 4) && ((1 << j) & mpt->m_event_mask[i])) { 6899 i = mpt->m_event_index; 6900 mpt->m_events[i].Type = event; 6901 mpt->m_events[i].Number = ++mpt->m_event_number; 6902 bzero(mpt->m_events[i].Data, MPTSAS_MAX_EVENT_DATA_LENGTH * 4); 6903 event_data_len = ddi_get16(mpt->m_acc_reply_frame_hdl, 6904 &eventreply->EventDataLength); 6905 6906 if (event_data_len > 0) { 6907 /* 6908 * Limit data to size in m_event entry 6909 */ 6910 if (event_data_len > MPTSAS_MAX_EVENT_DATA_LENGTH) { 6911 event_data_len = MPTSAS_MAX_EVENT_DATA_LENGTH; 6912 } 6913 for (j = 0; j < event_data_len; j++) { 6914 mpt->m_events[i].Data[j] = 6915 ddi_get32(mpt->m_acc_reply_frame_hdl, 6916 &(eventreply->EventData[j])); 6917 } 6918 6919 /* 6920 * check for index wrap-around 6921 */ 6922 if (++i == MPTSAS_EVENT_QUEUE_SIZE) { 6923 i = 0; 6924 } 6925 mpt->m_event_index = (uint8_t)i; 6926 6927 /* 6928 * Set flag to send the event. 6929 */ 6930 sendAEN = TRUE; 6931 } 6932 } 6933 6934 /* 6935 * Generate a system event if flag is set to let anyone who cares know 6936 * that an event has occurred. 6937 */ 6938 if (sendAEN) { 6939 (void) ddi_log_sysevent(mpt->m_dip, DDI_VENDOR_LSI, "MPT_SAS", 6940 "SAS", NULL, NULL, DDI_NOSLEEP); 6941 } 6942 } 6943 6944 #define SMP_RESET_IN_PROGRESS MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS 6945 /* 6946 * handle sync events from ioc in interrupt 6947 * return value: 6948 * DDI_SUCCESS: The event is handled by this func 6949 * DDI_FAILURE: Event is not handled 6950 */ 6951 static int 6952 mptsas_handle_event_sync(void *args) 6953 { 6954 m_replyh_arg_t *replyh_arg; 6955 pMpi2EventNotificationReply_t eventreply; 6956 uint32_t event, rfm; 6957 mptsas_t *mpt; 6958 uint_t iocstatus; 6959 6960 replyh_arg = (m_replyh_arg_t *)args; 6961 rfm = replyh_arg->rfm; 6962 mpt = replyh_arg->mpt; 6963 6964 ASSERT(mutex_owned(&mpt->m_mutex)); 6965 6966 eventreply = (pMpi2EventNotificationReply_t) 6967 (mpt->m_reply_frame + (rfm - 6968 (mpt->m_reply_frame_dma_addr & 0xffffffffu))); 6969 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event); 6970 6971 if (iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 6972 &eventreply->IOCStatus)) { 6973 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { 6974 mptsas_log(mpt, CE_WARN, 6975 "!mptsas_handle_event_sync: event 0x%x, " 6976 "IOCStatus=0x%x, " 6977 "IOCLogInfo=0x%x", event, iocstatus, 6978 ddi_get32(mpt->m_acc_reply_frame_hdl, 6979 &eventreply->IOCLogInfo)); 6980 } else { 6981 mptsas_log(mpt, CE_WARN, 6982 "mptsas_handle_event_sync: event 0x%x, " 6983 "IOCStatus=0x%x, " 6984 "(IOCLogInfo=0x%x)", event, iocstatus, 6985 ddi_get32(mpt->m_acc_reply_frame_hdl, 6986 &eventreply->IOCLogInfo)); 6987 } 6988 } 6989 6990 /* 6991 * figure out what kind of event we got and handle accordingly 6992 */ 6993 switch (event) { 6994 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST: 6995 { 6996 pMpi2EventDataSasTopologyChangeList_t sas_topo_change_list; 6997 uint8_t num_entries, expstatus, phy; 6998 uint8_t phystatus, physport, state, i; 6999 uint8_t start_phy_num, link_rate; 7000 uint16_t dev_handle, reason_code; 7001 uint16_t enc_handle, expd_handle; 7002 char string[80], curr[80], prev[80]; 7003 mptsas_topo_change_list_t *topo_head = NULL; 7004 mptsas_topo_change_list_t *topo_tail = NULL; 7005 mptsas_topo_change_list_t *topo_node = NULL; 7006 mptsas_target_t *ptgt; 7007 mptsas_smp_t *psmp; 7008 uint8_t flags = 0, exp_flag; 7009 smhba_info_t *pSmhba = NULL; 7010 7011 NDBG20(("mptsas_handle_event_sync: SAS topology change")); 7012 7013 sas_topo_change_list = (pMpi2EventDataSasTopologyChangeList_t) 7014 eventreply->EventData; 7015 7016 enc_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7017 &sas_topo_change_list->EnclosureHandle); 7018 expd_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7019 &sas_topo_change_list->ExpanderDevHandle); 7020 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl, 7021 &sas_topo_change_list->NumEntries); 7022 start_phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl, 7023 &sas_topo_change_list->StartPhyNum); 7024 expstatus = ddi_get8(mpt->m_acc_reply_frame_hdl, 7025 &sas_topo_change_list->ExpStatus); 7026 physport = ddi_get8(mpt->m_acc_reply_frame_hdl, 7027 &sas_topo_change_list->PhysicalPort); 7028 7029 string[0] = 0; 7030 if (expd_handle) { 7031 flags = MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED; 7032 switch (expstatus) { 7033 case MPI2_EVENT_SAS_TOPO_ES_ADDED: 7034 (void) sprintf(string, " added"); 7035 /* 7036 * New expander device added 7037 */ 7038 mpt->m_port_chng = 1; 7039 topo_node = kmem_zalloc( 7040 sizeof (mptsas_topo_change_list_t), 7041 KM_SLEEP); 7042 topo_node->mpt = mpt; 7043 topo_node->event = MPTSAS_DR_EVENT_RECONFIG_SMP; 7044 topo_node->un.physport = physport; 7045 topo_node->devhdl = expd_handle; 7046 topo_node->flags = flags; 7047 topo_node->object = NULL; 7048 if (topo_head == NULL) { 7049 topo_head = topo_tail = topo_node; 7050 } else { 7051 topo_tail->next = topo_node; 7052 topo_tail = topo_node; 7053 } 7054 break; 7055 case MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING: 7056 (void) sprintf(string, " not responding, " 7057 "removed"); 7058 psmp = refhash_linear_search(mpt->m_smp_targets, 7059 mptsas_smp_eval_devhdl, &expd_handle); 7060 if (psmp == NULL) 7061 break; 7062 7063 topo_node = kmem_zalloc( 7064 sizeof (mptsas_topo_change_list_t), 7065 KM_SLEEP); 7066 topo_node->mpt = mpt; 7067 topo_node->un.phymask = 7068 psmp->m_addr.mta_phymask; 7069 topo_node->event = MPTSAS_DR_EVENT_OFFLINE_SMP; 7070 topo_node->devhdl = expd_handle; 7071 topo_node->flags = flags; 7072 topo_node->object = NULL; 7073 if (topo_head == NULL) { 7074 topo_head = topo_tail = topo_node; 7075 } else { 7076 topo_tail->next = topo_node; 7077 topo_tail = topo_node; 7078 } 7079 break; 7080 case MPI2_EVENT_SAS_TOPO_ES_RESPONDING: 7081 break; 7082 case MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING: 7083 (void) sprintf(string, " not responding, " 7084 "delaying removal"); 7085 break; 7086 default: 7087 break; 7088 } 7089 } else { 7090 flags = MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE; 7091 } 7092 7093 NDBG20(("SAS TOPOLOGY CHANGE for enclosure %x expander %x%s\n", 7094 enc_handle, expd_handle, string)); 7095 for (i = 0; i < num_entries; i++) { 7096 phy = i + start_phy_num; 7097 phystatus = ddi_get8(mpt->m_acc_reply_frame_hdl, 7098 &sas_topo_change_list->PHY[i].PhyStatus); 7099 dev_handle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7100 &sas_topo_change_list->PHY[i].AttachedDevHandle); 7101 reason_code = phystatus & MPI2_EVENT_SAS_TOPO_RC_MASK; 7102 /* 7103 * Filter out processing of Phy Vacant Status unless 7104 * the reason code is "Not Responding". Process all 7105 * other combinations of Phy Status and Reason Codes. 7106 */ 7107 if ((phystatus & 7108 MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT) && 7109 (reason_code != 7110 MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING)) { 7111 continue; 7112 } 7113 curr[0] = 0; 7114 prev[0] = 0; 7115 string[0] = 0; 7116 switch (reason_code) { 7117 case MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED: 7118 { 7119 NDBG20(("mptsas%d phy %d physical_port %d " 7120 "dev_handle %d added", mpt->m_instance, phy, 7121 physport, dev_handle)); 7122 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl, 7123 &sas_topo_change_list->PHY[i].LinkRate); 7124 state = (link_rate & 7125 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >> 7126 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT; 7127 switch (state) { 7128 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED: 7129 (void) sprintf(curr, "is disabled"); 7130 break; 7131 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED: 7132 (void) sprintf(curr, "is offline, " 7133 "failed speed negotiation"); 7134 break; 7135 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE: 7136 (void) sprintf(curr, "SATA OOB " 7137 "complete"); 7138 break; 7139 case SMP_RESET_IN_PROGRESS: 7140 (void) sprintf(curr, "SMP reset in " 7141 "progress"); 7142 break; 7143 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5: 7144 (void) sprintf(curr, "is online at " 7145 "1.5 Gbps"); 7146 break; 7147 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0: 7148 (void) sprintf(curr, "is online at 3.0 " 7149 "Gbps"); 7150 break; 7151 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0: 7152 (void) sprintf(curr, "is online at 6.0 " 7153 "Gbps"); 7154 break; 7155 case MPI25_EVENT_SAS_TOPO_LR_RATE_12_0: 7156 (void) sprintf(curr, 7157 "is online at 12.0 Gbps"); 7158 break; 7159 default: 7160 (void) sprintf(curr, "state is " 7161 "unknown"); 7162 break; 7163 } 7164 /* 7165 * New target device added into the system. 7166 * Set association flag according to if an 7167 * expander is used or not. 7168 */ 7169 exp_flag = 7170 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE; 7171 if (flags == 7172 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) { 7173 flags = exp_flag; 7174 } 7175 topo_node = kmem_zalloc( 7176 sizeof (mptsas_topo_change_list_t), 7177 KM_SLEEP); 7178 topo_node->mpt = mpt; 7179 topo_node->event = 7180 MPTSAS_DR_EVENT_RECONFIG_TARGET; 7181 if (expd_handle == 0) { 7182 /* 7183 * Per MPI 2, if expander dev handle 7184 * is 0, it's a directly attached 7185 * device. So driver use PHY to decide 7186 * which iport is associated 7187 */ 7188 physport = phy; 7189 mpt->m_port_chng = 1; 7190 } 7191 topo_node->un.physport = physport; 7192 topo_node->devhdl = dev_handle; 7193 topo_node->flags = flags; 7194 topo_node->object = NULL; 7195 if (topo_head == NULL) { 7196 topo_head = topo_tail = topo_node; 7197 } else { 7198 topo_tail->next = topo_node; 7199 topo_tail = topo_node; 7200 } 7201 break; 7202 } 7203 case MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING: 7204 { 7205 NDBG20(("mptsas%d phy %d physical_port %d " 7206 "dev_handle %d removed", mpt->m_instance, 7207 phy, physport, dev_handle)); 7208 /* 7209 * Set association flag according to if an 7210 * expander is used or not. 7211 */ 7212 exp_flag = 7213 MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE; 7214 if (flags == 7215 MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED) { 7216 flags = exp_flag; 7217 } 7218 /* 7219 * Target device is removed from the system 7220 * Before the device is really offline from 7221 * from system. 7222 */ 7223 ptgt = refhash_linear_search(mpt->m_targets, 7224 mptsas_target_eval_devhdl, &dev_handle); 7225 /* 7226 * If ptgt is NULL here, it means that the 7227 * DevHandle is not in the hash table. This is 7228 * reasonable sometimes. For example, if a 7229 * disk was pulled, then added, then pulled 7230 * again, the disk will not have been put into 7231 * the hash table because the add event will 7232 * have an invalid phymask. BUT, this does not 7233 * mean that the DevHandle is invalid. The 7234 * controller will still have a valid DevHandle 7235 * that must be removed. To do this, use the 7236 * MPTSAS_TOPO_FLAG_REMOVE_HANDLE event. 7237 */ 7238 if (ptgt == NULL) { 7239 topo_node = kmem_zalloc( 7240 sizeof (mptsas_topo_change_list_t), 7241 KM_SLEEP); 7242 topo_node->mpt = mpt; 7243 topo_node->un.phymask = 0; 7244 topo_node->event = 7245 MPTSAS_TOPO_FLAG_REMOVE_HANDLE; 7246 topo_node->devhdl = dev_handle; 7247 topo_node->flags = flags; 7248 topo_node->object = NULL; 7249 if (topo_head == NULL) { 7250 topo_head = topo_tail = 7251 topo_node; 7252 } else { 7253 topo_tail->next = topo_node; 7254 topo_tail = topo_node; 7255 } 7256 break; 7257 } 7258 7259 /* 7260 * Update DR flag immediately avoid I/O failure 7261 * before failover finish. Pay attention to the 7262 * mutex protect, we need grab m_tx_waitq_mutex 7263 * during set m_dr_flag because we won't add 7264 * the following command into waitq, instead, 7265 * we need return TRAN_BUSY in the tran_start 7266 * context. 7267 */ 7268 mutex_enter(&mpt->m_tx_waitq_mutex); 7269 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION; 7270 mutex_exit(&mpt->m_tx_waitq_mutex); 7271 7272 topo_node = kmem_zalloc( 7273 sizeof (mptsas_topo_change_list_t), 7274 KM_SLEEP); 7275 topo_node->mpt = mpt; 7276 topo_node->un.phymask = 7277 ptgt->m_addr.mta_phymask; 7278 topo_node->event = 7279 MPTSAS_DR_EVENT_OFFLINE_TARGET; 7280 topo_node->devhdl = dev_handle; 7281 topo_node->flags = flags; 7282 topo_node->object = NULL; 7283 if (topo_head == NULL) { 7284 topo_head = topo_tail = topo_node; 7285 } else { 7286 topo_tail->next = topo_node; 7287 topo_tail = topo_node; 7288 } 7289 break; 7290 } 7291 case MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED: 7292 link_rate = ddi_get8(mpt->m_acc_reply_frame_hdl, 7293 &sas_topo_change_list->PHY[i].LinkRate); 7294 state = (link_rate & 7295 MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK) >> 7296 MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT; 7297 pSmhba = &mpt->m_phy_info[i].smhba_info; 7298 pSmhba->negotiated_link_rate = state; 7299 switch (state) { 7300 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED: 7301 (void) sprintf(curr, "is disabled"); 7302 mptsas_smhba_log_sysevent(mpt, 7303 ESC_SAS_PHY_EVENT, 7304 SAS_PHY_REMOVE, 7305 &mpt->m_phy_info[i].smhba_info); 7306 mpt->m_phy_info[i].smhba_info. 7307 negotiated_link_rate 7308 = 0x1; 7309 break; 7310 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED: 7311 (void) sprintf(curr, "is offline, " 7312 "failed speed negotiation"); 7313 mptsas_smhba_log_sysevent(mpt, 7314 ESC_SAS_PHY_EVENT, 7315 SAS_PHY_OFFLINE, 7316 &mpt->m_phy_info[i].smhba_info); 7317 break; 7318 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE: 7319 (void) sprintf(curr, "SATA OOB " 7320 "complete"); 7321 break; 7322 case SMP_RESET_IN_PROGRESS: 7323 (void) sprintf(curr, "SMP reset in " 7324 "progress"); 7325 break; 7326 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5: 7327 (void) sprintf(curr, "is online at " 7328 "1.5 Gbps"); 7329 if ((expd_handle == 0) && 7330 (enc_handle == 1)) { 7331 mpt->m_port_chng = 1; 7332 } 7333 mptsas_smhba_log_sysevent(mpt, 7334 ESC_SAS_PHY_EVENT, 7335 SAS_PHY_ONLINE, 7336 &mpt->m_phy_info[i].smhba_info); 7337 break; 7338 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0: 7339 (void) sprintf(curr, "is online at 3.0 " 7340 "Gbps"); 7341 if ((expd_handle == 0) && 7342 (enc_handle == 1)) { 7343 mpt->m_port_chng = 1; 7344 } 7345 mptsas_smhba_log_sysevent(mpt, 7346 ESC_SAS_PHY_EVENT, 7347 SAS_PHY_ONLINE, 7348 &mpt->m_phy_info[i].smhba_info); 7349 break; 7350 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0: 7351 (void) sprintf(curr, "is online at " 7352 "6.0 Gbps"); 7353 if ((expd_handle == 0) && 7354 (enc_handle == 1)) { 7355 mpt->m_port_chng = 1; 7356 } 7357 mptsas_smhba_log_sysevent(mpt, 7358 ESC_SAS_PHY_EVENT, 7359 SAS_PHY_ONLINE, 7360 &mpt->m_phy_info[i].smhba_info); 7361 break; 7362 case MPI25_EVENT_SAS_TOPO_LR_RATE_12_0: 7363 (void) sprintf(curr, "is online at " 7364 "12.0 Gbps"); 7365 if ((expd_handle == 0) && 7366 (enc_handle == 1)) { 7367 mpt->m_port_chng = 1; 7368 } 7369 mptsas_smhba_log_sysevent(mpt, 7370 ESC_SAS_PHY_EVENT, 7371 SAS_PHY_ONLINE, 7372 &mpt->m_phy_info[i].smhba_info); 7373 break; 7374 default: 7375 (void) sprintf(curr, "state is " 7376 "unknown"); 7377 break; 7378 } 7379 7380 state = (link_rate & 7381 MPI2_EVENT_SAS_TOPO_LR_PREV_MASK) >> 7382 MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT; 7383 switch (state) { 7384 case MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED: 7385 (void) sprintf(prev, ", was disabled"); 7386 break; 7387 case MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED: 7388 (void) sprintf(prev, ", was offline, " 7389 "failed speed negotiation"); 7390 break; 7391 case MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE: 7392 (void) sprintf(prev, ", was SATA OOB " 7393 "complete"); 7394 break; 7395 case SMP_RESET_IN_PROGRESS: 7396 (void) sprintf(prev, ", was SMP reset " 7397 "in progress"); 7398 break; 7399 case MPI2_EVENT_SAS_TOPO_LR_RATE_1_5: 7400 (void) sprintf(prev, ", was online at " 7401 "1.5 Gbps"); 7402 break; 7403 case MPI2_EVENT_SAS_TOPO_LR_RATE_3_0: 7404 (void) sprintf(prev, ", was online at " 7405 "3.0 Gbps"); 7406 break; 7407 case MPI2_EVENT_SAS_TOPO_LR_RATE_6_0: 7408 (void) sprintf(prev, ", was online at " 7409 "6.0 Gbps"); 7410 break; 7411 case MPI25_EVENT_SAS_TOPO_LR_RATE_12_0: 7412 (void) sprintf(prev, ", was online at " 7413 "12.0 Gbps"); 7414 break; 7415 default: 7416 break; 7417 } 7418 (void) sprintf(&string[strlen(string)], "link " 7419 "changed, "); 7420 break; 7421 case MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE: 7422 continue; 7423 case MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING: 7424 (void) sprintf(&string[strlen(string)], 7425 "target not responding, delaying " 7426 "removal"); 7427 break; 7428 } 7429 NDBG20(("mptsas%d phy %d DevHandle %x, %s%s%s\n", 7430 mpt->m_instance, phy, dev_handle, string, curr, 7431 prev)); 7432 } 7433 if (topo_head != NULL) { 7434 /* 7435 * Launch DR taskq to handle topology change 7436 */ 7437 if ((ddi_taskq_dispatch(mpt->m_dr_taskq, 7438 mptsas_handle_dr, (void *)topo_head, 7439 DDI_NOSLEEP)) != DDI_SUCCESS) { 7440 while (topo_head != NULL) { 7441 topo_node = topo_head; 7442 topo_head = topo_head->next; 7443 kmem_free(topo_node, 7444 sizeof (mptsas_topo_change_list_t)); 7445 } 7446 mptsas_log(mpt, CE_NOTE, "mptsas start taskq " 7447 "for handle SAS DR event failed. \n"); 7448 } 7449 } 7450 break; 7451 } 7452 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST: 7453 { 7454 Mpi2EventDataIrConfigChangeList_t *irChangeList; 7455 mptsas_topo_change_list_t *topo_head = NULL; 7456 mptsas_topo_change_list_t *topo_tail = NULL; 7457 mptsas_topo_change_list_t *topo_node = NULL; 7458 mptsas_target_t *ptgt; 7459 uint8_t num_entries, i, reason; 7460 uint16_t volhandle, diskhandle; 7461 7462 irChangeList = (pMpi2EventDataIrConfigChangeList_t) 7463 eventreply->EventData; 7464 num_entries = ddi_get8(mpt->m_acc_reply_frame_hdl, 7465 &irChangeList->NumElements); 7466 7467 NDBG20(("mptsas%d IR_CONFIGURATION_CHANGE_LIST event received", 7468 mpt->m_instance)); 7469 7470 for (i = 0; i < num_entries; i++) { 7471 reason = ddi_get8(mpt->m_acc_reply_frame_hdl, 7472 &irChangeList->ConfigElement[i].ReasonCode); 7473 volhandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7474 &irChangeList->ConfigElement[i].VolDevHandle); 7475 diskhandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7476 &irChangeList->ConfigElement[i].PhysDiskDevHandle); 7477 7478 switch (reason) { 7479 case MPI2_EVENT_IR_CHANGE_RC_ADDED: 7480 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED: 7481 { 7482 NDBG20(("mptsas %d volume added\n", 7483 mpt->m_instance)); 7484 7485 topo_node = kmem_zalloc( 7486 sizeof (mptsas_topo_change_list_t), 7487 KM_SLEEP); 7488 7489 topo_node->mpt = mpt; 7490 topo_node->event = 7491 MPTSAS_DR_EVENT_RECONFIG_TARGET; 7492 topo_node->un.physport = 0xff; 7493 topo_node->devhdl = volhandle; 7494 topo_node->flags = 7495 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED; 7496 topo_node->object = NULL; 7497 if (topo_head == NULL) { 7498 topo_head = topo_tail = topo_node; 7499 } else { 7500 topo_tail->next = topo_node; 7501 topo_tail = topo_node; 7502 } 7503 break; 7504 } 7505 case MPI2_EVENT_IR_CHANGE_RC_REMOVED: 7506 case MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED: 7507 { 7508 NDBG20(("mptsas %d volume deleted\n", 7509 mpt->m_instance)); 7510 ptgt = refhash_linear_search(mpt->m_targets, 7511 mptsas_target_eval_devhdl, &volhandle); 7512 if (ptgt == NULL) 7513 break; 7514 7515 /* 7516 * Clear any flags related to volume 7517 */ 7518 (void) mptsas_delete_volume(mpt, volhandle); 7519 7520 /* 7521 * Update DR flag immediately avoid I/O failure 7522 */ 7523 mutex_enter(&mpt->m_tx_waitq_mutex); 7524 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION; 7525 mutex_exit(&mpt->m_tx_waitq_mutex); 7526 7527 topo_node = kmem_zalloc( 7528 sizeof (mptsas_topo_change_list_t), 7529 KM_SLEEP); 7530 topo_node->mpt = mpt; 7531 topo_node->un.phymask = 7532 ptgt->m_addr.mta_phymask; 7533 topo_node->event = 7534 MPTSAS_DR_EVENT_OFFLINE_TARGET; 7535 topo_node->devhdl = volhandle; 7536 topo_node->flags = 7537 MPTSAS_TOPO_FLAG_RAID_ASSOCIATED; 7538 topo_node->object = (void *)ptgt; 7539 if (topo_head == NULL) { 7540 topo_head = topo_tail = topo_node; 7541 } else { 7542 topo_tail->next = topo_node; 7543 topo_tail = topo_node; 7544 } 7545 break; 7546 } 7547 case MPI2_EVENT_IR_CHANGE_RC_PD_CREATED: 7548 case MPI2_EVENT_IR_CHANGE_RC_HIDE: 7549 { 7550 ptgt = refhash_linear_search(mpt->m_targets, 7551 mptsas_target_eval_devhdl, &diskhandle); 7552 if (ptgt == NULL) 7553 break; 7554 7555 /* 7556 * Update DR flag immediately avoid I/O failure 7557 */ 7558 mutex_enter(&mpt->m_tx_waitq_mutex); 7559 ptgt->m_dr_flag = MPTSAS_DR_INTRANSITION; 7560 mutex_exit(&mpt->m_tx_waitq_mutex); 7561 7562 topo_node = kmem_zalloc( 7563 sizeof (mptsas_topo_change_list_t), 7564 KM_SLEEP); 7565 topo_node->mpt = mpt; 7566 topo_node->un.phymask = 7567 ptgt->m_addr.mta_phymask; 7568 topo_node->event = 7569 MPTSAS_DR_EVENT_OFFLINE_TARGET; 7570 topo_node->devhdl = diskhandle; 7571 topo_node->flags = 7572 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED; 7573 topo_node->object = (void *)ptgt; 7574 if (topo_head == NULL) { 7575 topo_head = topo_tail = topo_node; 7576 } else { 7577 topo_tail->next = topo_node; 7578 topo_tail = topo_node; 7579 } 7580 break; 7581 } 7582 case MPI2_EVENT_IR_CHANGE_RC_UNHIDE: 7583 case MPI2_EVENT_IR_CHANGE_RC_PD_DELETED: 7584 { 7585 /* 7586 * The physical drive is released by a IR 7587 * volume. But we cannot get the the physport 7588 * or phynum from the event data, so we only 7589 * can get the physport/phynum after SAS 7590 * Device Page0 request for the devhdl. 7591 */ 7592 topo_node = kmem_zalloc( 7593 sizeof (mptsas_topo_change_list_t), 7594 KM_SLEEP); 7595 topo_node->mpt = mpt; 7596 topo_node->un.phymask = 0; 7597 topo_node->event = 7598 MPTSAS_DR_EVENT_RECONFIG_TARGET; 7599 topo_node->devhdl = diskhandle; 7600 topo_node->flags = 7601 MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED; 7602 topo_node->object = NULL; 7603 mpt->m_port_chng = 1; 7604 if (topo_head == NULL) { 7605 topo_head = topo_tail = topo_node; 7606 } else { 7607 topo_tail->next = topo_node; 7608 topo_tail = topo_node; 7609 } 7610 break; 7611 } 7612 default: 7613 break; 7614 } 7615 } 7616 7617 if (topo_head != NULL) { 7618 /* 7619 * Launch DR taskq to handle topology change 7620 */ 7621 if ((ddi_taskq_dispatch(mpt->m_dr_taskq, 7622 mptsas_handle_dr, (void *)topo_head, 7623 DDI_NOSLEEP)) != DDI_SUCCESS) { 7624 while (topo_head != NULL) { 7625 topo_node = topo_head; 7626 topo_head = topo_head->next; 7627 kmem_free(topo_node, 7628 sizeof (mptsas_topo_change_list_t)); 7629 } 7630 mptsas_log(mpt, CE_NOTE, "mptsas start taskq " 7631 "for handle SAS DR event failed. \n"); 7632 } 7633 } 7634 break; 7635 } 7636 default: 7637 return (DDI_FAILURE); 7638 } 7639 7640 return (DDI_SUCCESS); 7641 } 7642 7643 /* 7644 * handle events from ioc 7645 */ 7646 static void 7647 mptsas_handle_event(void *args) 7648 { 7649 m_replyh_arg_t *replyh_arg; 7650 pMpi2EventNotificationReply_t eventreply; 7651 uint32_t event, iocloginfo, rfm; 7652 uint32_t status; 7653 uint8_t port; 7654 mptsas_t *mpt; 7655 uint_t iocstatus; 7656 7657 replyh_arg = (m_replyh_arg_t *)args; 7658 rfm = replyh_arg->rfm; 7659 mpt = replyh_arg->mpt; 7660 7661 mutex_enter(&mpt->m_mutex); 7662 /* 7663 * If HBA is being reset, drop incoming event. 7664 */ 7665 if (mpt->m_in_reset) { 7666 NDBG20(("dropping event received prior to reset")); 7667 mutex_exit(&mpt->m_mutex); 7668 return; 7669 } 7670 7671 eventreply = (pMpi2EventNotificationReply_t) 7672 (mpt->m_reply_frame + (rfm - 7673 (mpt->m_reply_frame_dma_addr & 0xffffffffu))); 7674 event = ddi_get16(mpt->m_acc_reply_frame_hdl, &eventreply->Event); 7675 7676 if (iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 7677 &eventreply->IOCStatus)) { 7678 if (iocstatus == MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) { 7679 mptsas_log(mpt, CE_WARN, 7680 "!mptsas_handle_event: IOCStatus=0x%x, " 7681 "IOCLogInfo=0x%x", iocstatus, 7682 ddi_get32(mpt->m_acc_reply_frame_hdl, 7683 &eventreply->IOCLogInfo)); 7684 } else { 7685 mptsas_log(mpt, CE_WARN, 7686 "mptsas_handle_event: IOCStatus=0x%x, " 7687 "IOCLogInfo=0x%x", iocstatus, 7688 ddi_get32(mpt->m_acc_reply_frame_hdl, 7689 &eventreply->IOCLogInfo)); 7690 } 7691 } 7692 7693 /* 7694 * figure out what kind of event we got and handle accordingly 7695 */ 7696 switch (event) { 7697 case MPI2_EVENT_LOG_ENTRY_ADDED: 7698 break; 7699 case MPI2_EVENT_LOG_DATA: 7700 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl, 7701 &eventreply->IOCLogInfo); 7702 NDBG20(("mptsas %d log info %x received.\n", mpt->m_instance, 7703 iocloginfo)); 7704 break; 7705 case MPI2_EVENT_STATE_CHANGE: 7706 NDBG20(("mptsas%d state change.", mpt->m_instance)); 7707 break; 7708 case MPI2_EVENT_HARD_RESET_RECEIVED: 7709 NDBG20(("mptsas%d event change.", mpt->m_instance)); 7710 break; 7711 case MPI2_EVENT_SAS_DISCOVERY: 7712 { 7713 MPI2_EVENT_DATA_SAS_DISCOVERY *sasdiscovery; 7714 char string[80]; 7715 uint8_t rc; 7716 7717 sasdiscovery = 7718 (pMpi2EventDataSasDiscovery_t)eventreply->EventData; 7719 7720 rc = ddi_get8(mpt->m_acc_reply_frame_hdl, 7721 &sasdiscovery->ReasonCode); 7722 port = ddi_get8(mpt->m_acc_reply_frame_hdl, 7723 &sasdiscovery->PhysicalPort); 7724 status = ddi_get32(mpt->m_acc_reply_frame_hdl, 7725 &sasdiscovery->DiscoveryStatus); 7726 7727 string[0] = 0; 7728 switch (rc) { 7729 case MPI2_EVENT_SAS_DISC_RC_STARTED: 7730 (void) sprintf(string, "STARTING"); 7731 break; 7732 case MPI2_EVENT_SAS_DISC_RC_COMPLETED: 7733 (void) sprintf(string, "COMPLETED"); 7734 break; 7735 default: 7736 (void) sprintf(string, "UNKNOWN"); 7737 break; 7738 } 7739 7740 NDBG20(("SAS DISCOVERY is %s for port %d, status %x", string, 7741 port, status)); 7742 7743 break; 7744 } 7745 case MPI2_EVENT_EVENT_CHANGE: 7746 NDBG20(("mptsas%d event change.", mpt->m_instance)); 7747 break; 7748 case MPI2_EVENT_TASK_SET_FULL: 7749 { 7750 pMpi2EventDataTaskSetFull_t taskfull; 7751 7752 taskfull = (pMpi2EventDataTaskSetFull_t)eventreply->EventData; 7753 7754 NDBG20(("TASK_SET_FULL received for mptsas%d, depth %d\n", 7755 mpt->m_instance, ddi_get16(mpt->m_acc_reply_frame_hdl, 7756 &taskfull->CurrentDepth))); 7757 break; 7758 } 7759 case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST: 7760 { 7761 /* 7762 * SAS TOPOLOGY CHANGE LIST Event has already been handled 7763 * in mptsas_handle_event_sync() of interrupt context 7764 */ 7765 break; 7766 } 7767 case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE: 7768 { 7769 pMpi2EventDataSasEnclDevStatusChange_t encstatus; 7770 uint8_t rc; 7771 uint16_t enchdl; 7772 char string[80]; 7773 mptsas_enclosure_t *mep; 7774 7775 encstatus = (pMpi2EventDataSasEnclDevStatusChange_t) 7776 eventreply->EventData; 7777 7778 rc = ddi_get8(mpt->m_acc_reply_frame_hdl, 7779 &encstatus->ReasonCode); 7780 enchdl = ddi_get16(mpt->m_acc_reply_frame_hdl, 7781 &encstatus->EnclosureHandle); 7782 7783 switch (rc) { 7784 case MPI2_EVENT_SAS_ENCL_RC_ADDED: 7785 (void) sprintf(string, "added"); 7786 break; 7787 case MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING: 7788 mep = mptsas_enc_lookup(mpt, enchdl); 7789 if (mep != NULL) { 7790 list_remove(&mpt->m_enclosures, mep); 7791 kmem_free(mep, sizeof (*mep)); 7792 } 7793 (void) sprintf(string, ", not responding"); 7794 break; 7795 default: 7796 break; 7797 } 7798 NDBG20(("mptsas%d ENCLOSURE STATUS CHANGE for enclosure " 7799 "%x%s\n", mpt->m_instance, 7800 ddi_get16(mpt->m_acc_reply_frame_hdl, 7801 &encstatus->EnclosureHandle), string)); 7802 7803 /* 7804 * No matter what has happened, update all of our device state 7805 * for enclosures, by retriggering an evaluation. 7806 */ 7807 mpt->m_done_traverse_enc = 0; 7808 mptsas_update_hashtab(mpt); 7809 break; 7810 } 7811 7812 /* 7813 * MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE is handled by 7814 * mptsas_handle_event_sync,in here just send ack message. 7815 */ 7816 case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE: 7817 { 7818 pMpi2EventDataSasDeviceStatusChange_t statuschange; 7819 uint8_t rc; 7820 uint16_t devhdl; 7821 uint64_t wwn = 0; 7822 uint32_t wwn_lo, wwn_hi; 7823 7824 statuschange = (pMpi2EventDataSasDeviceStatusChange_t) 7825 eventreply->EventData; 7826 rc = ddi_get8(mpt->m_acc_reply_frame_hdl, 7827 &statuschange->ReasonCode); 7828 wwn_lo = ddi_get32(mpt->m_acc_reply_frame_hdl, 7829 (uint32_t *)(void *)&statuschange->SASAddress); 7830 wwn_hi = ddi_get32(mpt->m_acc_reply_frame_hdl, 7831 (uint32_t *)(void *)&statuschange->SASAddress + 1); 7832 wwn = ((uint64_t)wwn_hi << 32) | wwn_lo; 7833 devhdl = ddi_get16(mpt->m_acc_reply_frame_hdl, 7834 &statuschange->DevHandle); 7835 7836 NDBG13(("MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE wwn is %"PRIx64, 7837 wwn)); 7838 7839 switch (rc) { 7840 case MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA: 7841 NDBG20(("SMART data received, ASC/ASCQ = %02x/%02x", 7842 ddi_get8(mpt->m_acc_reply_frame_hdl, 7843 &statuschange->ASC), 7844 ddi_get8(mpt->m_acc_reply_frame_hdl, 7845 &statuschange->ASCQ))); 7846 break; 7847 7848 case MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED: 7849 NDBG20(("Device not supported")); 7850 break; 7851 7852 case MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET: 7853 NDBG20(("IOC internally generated the Target Reset " 7854 "for devhdl:%x", devhdl)); 7855 break; 7856 7857 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET: 7858 NDBG20(("IOC's internally generated Target Reset " 7859 "completed for devhdl:%x", devhdl)); 7860 break; 7861 7862 case MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL: 7863 NDBG20(("IOC internally generated Abort Task")); 7864 break; 7865 7866 case MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL: 7867 NDBG20(("IOC's internally generated Abort Task " 7868 "completed")); 7869 break; 7870 7871 case MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL: 7872 NDBG20(("IOC internally generated Abort Task Set")); 7873 break; 7874 7875 case MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL: 7876 NDBG20(("IOC internally generated Clear Task Set")); 7877 break; 7878 7879 case MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL: 7880 NDBG20(("IOC internally generated Query Task")); 7881 break; 7882 7883 case MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION: 7884 NDBG20(("Device sent an Asynchronous Notification")); 7885 break; 7886 7887 default: 7888 break; 7889 } 7890 break; 7891 } 7892 case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST: 7893 { 7894 /* 7895 * IR TOPOLOGY CHANGE LIST Event has already been handled 7896 * in mpt_handle_event_sync() of interrupt context 7897 */ 7898 break; 7899 } 7900 case MPI2_EVENT_IR_OPERATION_STATUS: 7901 { 7902 Mpi2EventDataIrOperationStatus_t *irOpStatus; 7903 char reason_str[80]; 7904 uint8_t rc, percent; 7905 uint16_t handle; 7906 7907 irOpStatus = (pMpi2EventDataIrOperationStatus_t) 7908 eventreply->EventData; 7909 rc = ddi_get8(mpt->m_acc_reply_frame_hdl, 7910 &irOpStatus->RAIDOperation); 7911 percent = ddi_get8(mpt->m_acc_reply_frame_hdl, 7912 &irOpStatus->PercentComplete); 7913 handle = ddi_get16(mpt->m_acc_reply_frame_hdl, 7914 &irOpStatus->VolDevHandle); 7915 7916 switch (rc) { 7917 case MPI2_EVENT_IR_RAIDOP_RESYNC: 7918 (void) sprintf(reason_str, "resync"); 7919 break; 7920 case MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION: 7921 (void) sprintf(reason_str, "online capacity " 7922 "expansion"); 7923 break; 7924 case MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK: 7925 (void) sprintf(reason_str, "consistency check"); 7926 break; 7927 default: 7928 (void) sprintf(reason_str, "unknown reason %x", 7929 rc); 7930 } 7931 7932 NDBG20(("mptsas%d raid operational status: (%s)" 7933 "\thandle(0x%04x), percent complete(%d)\n", 7934 mpt->m_instance, reason_str, handle, percent)); 7935 break; 7936 } 7937 case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE: 7938 { 7939 pMpi2EventDataSasBroadcastPrimitive_t sas_broadcast; 7940 uint8_t phy_num; 7941 uint8_t primitive; 7942 7943 sas_broadcast = (pMpi2EventDataSasBroadcastPrimitive_t) 7944 eventreply->EventData; 7945 7946 phy_num = ddi_get8(mpt->m_acc_reply_frame_hdl, 7947 &sas_broadcast->PhyNum); 7948 primitive = ddi_get8(mpt->m_acc_reply_frame_hdl, 7949 &sas_broadcast->Primitive); 7950 7951 switch (primitive) { 7952 case MPI2_EVENT_PRIMITIVE_CHANGE: 7953 mptsas_smhba_log_sysevent(mpt, 7954 ESC_SAS_HBA_PORT_BROADCAST, 7955 SAS_PORT_BROADCAST_CHANGE, 7956 &mpt->m_phy_info[phy_num].smhba_info); 7957 break; 7958 case MPI2_EVENT_PRIMITIVE_SES: 7959 mptsas_smhba_log_sysevent(mpt, 7960 ESC_SAS_HBA_PORT_BROADCAST, 7961 SAS_PORT_BROADCAST_SES, 7962 &mpt->m_phy_info[phy_num].smhba_info); 7963 break; 7964 case MPI2_EVENT_PRIMITIVE_EXPANDER: 7965 mptsas_smhba_log_sysevent(mpt, 7966 ESC_SAS_HBA_PORT_BROADCAST, 7967 SAS_PORT_BROADCAST_D01_4, 7968 &mpt->m_phy_info[phy_num].smhba_info); 7969 break; 7970 case MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT: 7971 mptsas_smhba_log_sysevent(mpt, 7972 ESC_SAS_HBA_PORT_BROADCAST, 7973 SAS_PORT_BROADCAST_D04_7, 7974 &mpt->m_phy_info[phy_num].smhba_info); 7975 break; 7976 case MPI2_EVENT_PRIMITIVE_RESERVED3: 7977 mptsas_smhba_log_sysevent(mpt, 7978 ESC_SAS_HBA_PORT_BROADCAST, 7979 SAS_PORT_BROADCAST_D16_7, 7980 &mpt->m_phy_info[phy_num].smhba_info); 7981 break; 7982 case MPI2_EVENT_PRIMITIVE_RESERVED4: 7983 mptsas_smhba_log_sysevent(mpt, 7984 ESC_SAS_HBA_PORT_BROADCAST, 7985 SAS_PORT_BROADCAST_D29_7, 7986 &mpt->m_phy_info[phy_num].smhba_info); 7987 break; 7988 case MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED: 7989 mptsas_smhba_log_sysevent(mpt, 7990 ESC_SAS_HBA_PORT_BROADCAST, 7991 SAS_PORT_BROADCAST_D24_0, 7992 &mpt->m_phy_info[phy_num].smhba_info); 7993 break; 7994 case MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED: 7995 mptsas_smhba_log_sysevent(mpt, 7996 ESC_SAS_HBA_PORT_BROADCAST, 7997 SAS_PORT_BROADCAST_D27_4, 7998 &mpt->m_phy_info[phy_num].smhba_info); 7999 break; 8000 default: 8001 NDBG16(("mptsas%d: unknown BROADCAST PRIMITIVE" 8002 " %x received", 8003 mpt->m_instance, primitive)); 8004 break; 8005 } 8006 NDBG16(("mptsas%d sas broadcast primitive: " 8007 "\tprimitive(0x%04x), phy(%d) complete\n", 8008 mpt->m_instance, primitive, phy_num)); 8009 break; 8010 } 8011 case MPI2_EVENT_IR_VOLUME: 8012 { 8013 Mpi2EventDataIrVolume_t *irVolume; 8014 uint16_t devhandle; 8015 uint32_t state; 8016 int config, vol; 8017 uint8_t found = FALSE; 8018 8019 irVolume = (pMpi2EventDataIrVolume_t)eventreply->EventData; 8020 state = ddi_get32(mpt->m_acc_reply_frame_hdl, 8021 &irVolume->NewValue); 8022 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 8023 &irVolume->VolDevHandle); 8024 8025 NDBG20(("EVENT_IR_VOLUME event is received")); 8026 8027 /* 8028 * Get latest RAID info and then find the DevHandle for this 8029 * event in the configuration. If the DevHandle is not found 8030 * just exit the event. 8031 */ 8032 (void) mptsas_get_raid_info(mpt); 8033 for (config = 0; (config < mpt->m_num_raid_configs) && 8034 (!found); config++) { 8035 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) { 8036 if (mpt->m_raidconfig[config].m_raidvol[vol]. 8037 m_raidhandle == devhandle) { 8038 found = TRUE; 8039 break; 8040 } 8041 } 8042 } 8043 if (!found) { 8044 break; 8045 } 8046 8047 switch (irVolume->ReasonCode) { 8048 case MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED: 8049 { 8050 uint32_t i; 8051 mpt->m_raidconfig[config].m_raidvol[vol].m_settings = 8052 state; 8053 8054 i = state & MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING; 8055 mptsas_log(mpt, CE_NOTE, " Volume %d settings changed" 8056 ", auto-config of hot-swap drives is %s" 8057 ", write caching is %s" 8058 ", hot-spare pool mask is %02x\n", 8059 vol, state & 8060 MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE 8061 ? "disabled" : "enabled", 8062 i == MPI2_RAIDVOL0_SETTING_UNCHANGED 8063 ? "controlled by member disks" : 8064 i == MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING 8065 ? "disabled" : 8066 i == MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING 8067 ? "enabled" : 8068 "incorrectly set", 8069 (state >> 16) & 0xff); 8070 break; 8071 } 8072 case MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED: 8073 { 8074 mpt->m_raidconfig[config].m_raidvol[vol].m_state = 8075 (uint8_t)state; 8076 8077 mptsas_log(mpt, CE_NOTE, 8078 "Volume %d is now %s\n", vol, 8079 state == MPI2_RAID_VOL_STATE_OPTIMAL 8080 ? "optimal" : 8081 state == MPI2_RAID_VOL_STATE_DEGRADED 8082 ? "degraded" : 8083 state == MPI2_RAID_VOL_STATE_ONLINE 8084 ? "online" : 8085 state == MPI2_RAID_VOL_STATE_INITIALIZING 8086 ? "initializing" : 8087 state == MPI2_RAID_VOL_STATE_FAILED 8088 ? "failed" : 8089 state == MPI2_RAID_VOL_STATE_MISSING 8090 ? "missing" : 8091 "state unknown"); 8092 break; 8093 } 8094 case MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED: 8095 { 8096 mpt->m_raidconfig[config].m_raidvol[vol]. 8097 m_statusflags = state; 8098 8099 mptsas_log(mpt, CE_NOTE, 8100 " Volume %d is now %s%s%s%s%s%s%s%s%s\n", 8101 vol, 8102 state & MPI2_RAIDVOL0_STATUS_FLAG_ENABLED 8103 ? ", enabled" : ", disabled", 8104 state & MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED 8105 ? ", quiesced" : "", 8106 state & MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE 8107 ? ", inactive" : ", active", 8108 state & 8109 MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL 8110 ? ", bad block table is full" : "", 8111 state & 8112 MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS 8113 ? ", resync in progress" : "", 8114 state & MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT 8115 ? ", background initialization in progress" : "", 8116 state & 8117 MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION 8118 ? ", capacity expansion in progress" : "", 8119 state & 8120 MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK 8121 ? ", consistency check in progress" : "", 8122 state & MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB 8123 ? ", data scrub in progress" : ""); 8124 break; 8125 } 8126 default: 8127 break; 8128 } 8129 break; 8130 } 8131 case MPI2_EVENT_IR_PHYSICAL_DISK: 8132 { 8133 Mpi2EventDataIrPhysicalDisk_t *irPhysDisk; 8134 uint16_t devhandle, enchandle, slot; 8135 uint32_t status, state; 8136 uint8_t physdisknum, reason; 8137 8138 irPhysDisk = (Mpi2EventDataIrPhysicalDisk_t *) 8139 eventreply->EventData; 8140 physdisknum = ddi_get8(mpt->m_acc_reply_frame_hdl, 8141 &irPhysDisk->PhysDiskNum); 8142 devhandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 8143 &irPhysDisk->PhysDiskDevHandle); 8144 enchandle = ddi_get16(mpt->m_acc_reply_frame_hdl, 8145 &irPhysDisk->EnclosureHandle); 8146 slot = ddi_get16(mpt->m_acc_reply_frame_hdl, 8147 &irPhysDisk->Slot); 8148 state = ddi_get32(mpt->m_acc_reply_frame_hdl, 8149 &irPhysDisk->NewValue); 8150 reason = ddi_get8(mpt->m_acc_reply_frame_hdl, 8151 &irPhysDisk->ReasonCode); 8152 8153 NDBG20(("EVENT_IR_PHYSICAL_DISK event is received")); 8154 8155 switch (reason) { 8156 case MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED: 8157 mptsas_log(mpt, CE_NOTE, 8158 " PhysDiskNum %d with DevHandle 0x%x in slot %d " 8159 "for enclosure with handle 0x%x is now in hot " 8160 "spare pool %d", 8161 physdisknum, devhandle, slot, enchandle, 8162 (state >> 16) & 0xff); 8163 break; 8164 8165 case MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED: 8166 status = state; 8167 mptsas_log(mpt, CE_NOTE, 8168 " PhysDiskNum %d with DevHandle 0x%x in slot %d " 8169 "for enclosure with handle 0x%x is now " 8170 "%s%s%s%s%s\n", physdisknum, devhandle, slot, 8171 enchandle, 8172 status & MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME 8173 ? ", inactive" : ", active", 8174 status & MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC 8175 ? ", out of sync" : "", 8176 status & MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED 8177 ? ", quiesced" : "", 8178 status & 8179 MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED 8180 ? ", write cache enabled" : "", 8181 status & MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET 8182 ? ", capacity expansion target" : ""); 8183 break; 8184 8185 case MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED: 8186 mptsas_log(mpt, CE_NOTE, 8187 " PhysDiskNum %d with DevHandle 0x%x in slot %d " 8188 "for enclosure with handle 0x%x is now %s\n", 8189 physdisknum, devhandle, slot, enchandle, 8190 state == MPI2_RAID_PD_STATE_OPTIMAL 8191 ? "optimal" : 8192 state == MPI2_RAID_PD_STATE_REBUILDING 8193 ? "rebuilding" : 8194 state == MPI2_RAID_PD_STATE_DEGRADED 8195 ? "degraded" : 8196 state == MPI2_RAID_PD_STATE_HOT_SPARE 8197 ? "a hot spare" : 8198 state == MPI2_RAID_PD_STATE_ONLINE 8199 ? "online" : 8200 state == MPI2_RAID_PD_STATE_OFFLINE 8201 ? "offline" : 8202 state == MPI2_RAID_PD_STATE_NOT_COMPATIBLE 8203 ? "not compatible" : 8204 state == MPI2_RAID_PD_STATE_NOT_CONFIGURED 8205 ? "not configured" : 8206 "state unknown"); 8207 break; 8208 } 8209 break; 8210 } 8211 default: 8212 NDBG20(("mptsas%d: unknown event %x received", 8213 mpt->m_instance, event)); 8214 break; 8215 } 8216 8217 /* 8218 * Return the reply frame to the free queue. 8219 */ 8220 ddi_put32(mpt->m_acc_free_queue_hdl, 8221 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], rfm); 8222 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 8223 DDI_DMA_SYNC_FORDEV); 8224 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 8225 mpt->m_free_index = 0; 8226 } 8227 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 8228 mpt->m_free_index); 8229 mutex_exit(&mpt->m_mutex); 8230 } 8231 8232 /* 8233 * invoked from timeout() to restart qfull cmds with throttle == 0 8234 */ 8235 static void 8236 mptsas_restart_cmd(void *arg) 8237 { 8238 mptsas_t *mpt = arg; 8239 mptsas_target_t *ptgt = NULL; 8240 8241 mutex_enter(&mpt->m_mutex); 8242 8243 mpt->m_restart_cmd_timeid = 0; 8244 8245 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 8246 ptgt = refhash_next(mpt->m_targets, ptgt)) { 8247 if (ptgt->m_reset_delay == 0) { 8248 if (ptgt->m_t_throttle == QFULL_THROTTLE) { 8249 mptsas_set_throttle(mpt, ptgt, 8250 MAX_THROTTLE); 8251 } 8252 } 8253 } 8254 mptsas_restart_hba(mpt); 8255 mutex_exit(&mpt->m_mutex); 8256 } 8257 8258 void 8259 mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd) 8260 { 8261 int slot; 8262 mptsas_slots_t *slots = mpt->m_active; 8263 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 8264 8265 ASSERT(cmd != NULL); 8266 ASSERT(cmd->cmd_queued == FALSE); 8267 8268 /* 8269 * Task Management cmds are removed in their own routines. Also, 8270 * we don't want to modify timeout based on TM cmds. 8271 */ 8272 if (cmd->cmd_flags & CFLAG_TM_CMD) { 8273 return; 8274 } 8275 8276 slot = cmd->cmd_slot; 8277 8278 /* 8279 * remove the cmd. 8280 */ 8281 if (cmd == slots->m_slot[slot]) { 8282 NDBG31(("mptsas_remove_cmd: removing cmd=0x%p, flags " 8283 "0x%x", (void *)cmd, cmd->cmd_flags)); 8284 slots->m_slot[slot] = NULL; 8285 mpt->m_ncmds--; 8286 8287 /* 8288 * only decrement per target ncmds if command 8289 * has a target associated with it. 8290 */ 8291 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) { 8292 ptgt->m_t_ncmds--; 8293 /* 8294 * reset throttle if we just ran an untagged command 8295 * to a tagged target 8296 */ 8297 if ((ptgt->m_t_ncmds == 0) && 8298 ((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0)) { 8299 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 8300 } 8301 8302 /* 8303 * Remove this command from the active queue. 8304 */ 8305 if (cmd->cmd_active_expiration != 0) { 8306 TAILQ_REMOVE(&ptgt->m_active_cmdq, cmd, 8307 cmd_active_link); 8308 cmd->cmd_active_expiration = 0; 8309 } 8310 } 8311 } 8312 8313 /* 8314 * This is all we need to do for ioc commands. 8315 */ 8316 if (cmd->cmd_flags & CFLAG_CMDIOC) { 8317 mptsas_return_to_pool(mpt, cmd); 8318 return; 8319 } 8320 8321 ASSERT(cmd != slots->m_slot[cmd->cmd_slot]); 8322 } 8323 8324 /* 8325 * accept all cmds on the tx_waitq if any and then 8326 * start a fresh request from the top of the device queue. 8327 * 8328 * since there are always cmds queued on the tx_waitq, and rare cmds on 8329 * the instance waitq, so this function should not be invoked in the ISR, 8330 * the mptsas_restart_waitq() is invoked in the ISR instead. otherwise, the 8331 * burden belongs to the IO dispatch CPUs is moved the interrupt CPU. 8332 */ 8333 static void 8334 mptsas_restart_hba(mptsas_t *mpt) 8335 { 8336 ASSERT(mutex_owned(&mpt->m_mutex)); 8337 8338 mutex_enter(&mpt->m_tx_waitq_mutex); 8339 if (mpt->m_tx_waitq) { 8340 mptsas_accept_tx_waitq(mpt); 8341 } 8342 mutex_exit(&mpt->m_tx_waitq_mutex); 8343 mptsas_restart_waitq(mpt); 8344 } 8345 8346 /* 8347 * start a fresh request from the top of the device queue 8348 */ 8349 static void 8350 mptsas_restart_waitq(mptsas_t *mpt) 8351 { 8352 mptsas_cmd_t *cmd, *next_cmd; 8353 mptsas_target_t *ptgt = NULL; 8354 8355 NDBG1(("mptsas_restart_waitq: mpt=0x%p", (void *)mpt)); 8356 8357 ASSERT(mutex_owned(&mpt->m_mutex)); 8358 8359 /* 8360 * If there is a reset delay, don't start any cmds. Otherwise, start 8361 * as many cmds as possible. 8362 * Since SMID 0 is reserved and the TM slot is reserved, the actual max 8363 * commands is m_max_requests - 2. 8364 */ 8365 cmd = mpt->m_waitq; 8366 8367 while (cmd != NULL) { 8368 next_cmd = cmd->cmd_linkp; 8369 if (cmd->cmd_flags & CFLAG_PASSTHRU) { 8370 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 8371 /* 8372 * passthru command get slot need 8373 * set CFLAG_PREPARED. 8374 */ 8375 cmd->cmd_flags |= CFLAG_PREPARED; 8376 mptsas_waitq_delete(mpt, cmd); 8377 mptsas_start_passthru(mpt, cmd); 8378 } 8379 cmd = next_cmd; 8380 continue; 8381 } 8382 if (cmd->cmd_flags & CFLAG_CONFIG) { 8383 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 8384 /* 8385 * Send the config page request and delete it 8386 * from the waitq. 8387 */ 8388 cmd->cmd_flags |= CFLAG_PREPARED; 8389 mptsas_waitq_delete(mpt, cmd); 8390 mptsas_start_config_page_access(mpt, cmd); 8391 } 8392 cmd = next_cmd; 8393 continue; 8394 } 8395 if (cmd->cmd_flags & CFLAG_FW_DIAG) { 8396 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 8397 /* 8398 * Send the FW Diag request and delete if from 8399 * the waitq. 8400 */ 8401 cmd->cmd_flags |= CFLAG_PREPARED; 8402 mptsas_waitq_delete(mpt, cmd); 8403 mptsas_start_diag(mpt, cmd); 8404 } 8405 cmd = next_cmd; 8406 continue; 8407 } 8408 8409 ptgt = cmd->cmd_tgt_addr; 8410 if (ptgt && (ptgt->m_t_throttle == DRAIN_THROTTLE) && 8411 (ptgt->m_t_ncmds == 0)) { 8412 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 8413 } 8414 if ((mpt->m_ncmds <= (mpt->m_max_requests - 2)) && 8415 (ptgt && (ptgt->m_reset_delay == 0)) && 8416 (ptgt && (ptgt->m_t_ncmds < 8417 ptgt->m_t_throttle))) { 8418 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 8419 mptsas_waitq_delete(mpt, cmd); 8420 (void) mptsas_start_cmd(mpt, cmd); 8421 } 8422 } 8423 cmd = next_cmd; 8424 } 8425 } 8426 /* 8427 * Cmds are queued if tran_start() doesn't get the m_mutexlock(no wait). 8428 * Accept all those queued cmds before new cmd is accept so that the 8429 * cmds are sent in order. 8430 */ 8431 static void 8432 mptsas_accept_tx_waitq(mptsas_t *mpt) 8433 { 8434 mptsas_cmd_t *cmd; 8435 8436 ASSERT(mutex_owned(&mpt->m_mutex)); 8437 ASSERT(mutex_owned(&mpt->m_tx_waitq_mutex)); 8438 8439 /* 8440 * A Bus Reset could occur at any time and flush the tx_waitq, 8441 * so we cannot count on the tx_waitq to contain even one cmd. 8442 * And when the m_tx_waitq_mutex is released and run 8443 * mptsas_accept_pkt(), the tx_waitq may be flushed. 8444 */ 8445 cmd = mpt->m_tx_waitq; 8446 for (;;) { 8447 if ((cmd = mpt->m_tx_waitq) == NULL) { 8448 mpt->m_tx_draining = 0; 8449 break; 8450 } 8451 if ((mpt->m_tx_waitq = cmd->cmd_linkp) == NULL) { 8452 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; 8453 } 8454 cmd->cmd_linkp = NULL; 8455 mutex_exit(&mpt->m_tx_waitq_mutex); 8456 if (mptsas_accept_pkt(mpt, cmd) != TRAN_ACCEPT) 8457 cmn_err(CE_WARN, "mpt: mptsas_accept_tx_waitq: failed " 8458 "to accept cmd on queue\n"); 8459 mutex_enter(&mpt->m_tx_waitq_mutex); 8460 } 8461 } 8462 8463 8464 /* 8465 * mpt tag type lookup 8466 */ 8467 static char mptsas_tag_lookup[] = 8468 {0, MSG_HEAD_QTAG, MSG_ORDERED_QTAG, 0, MSG_SIMPLE_QTAG}; 8469 8470 static int 8471 mptsas_start_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd) 8472 { 8473 struct scsi_pkt *pkt = CMD2PKT(cmd); 8474 uint32_t control = 0; 8475 caddr_t mem, arsbuf; 8476 pMpi2SCSIIORequest_t io_request; 8477 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl; 8478 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl; 8479 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 8480 uint16_t SMID, io_flags = 0; 8481 uint8_t ars_size; 8482 uint64_t request_desc; 8483 uint32_t ars_dmaaddrlow; 8484 mptsas_cmd_t *c; 8485 8486 NDBG1(("mptsas_start_cmd: cmd=0x%p, flags 0x%x", (void *)cmd, 8487 cmd->cmd_flags)); 8488 8489 /* 8490 * Set SMID and increment index. Rollover to 1 instead of 0 if index 8491 * is at the max. 0 is an invalid SMID, so we call the first index 1. 8492 */ 8493 SMID = cmd->cmd_slot; 8494 8495 /* 8496 * It is possible for back to back device reset to 8497 * happen before the reset delay has expired. That's 8498 * ok, just let the device reset go out on the bus. 8499 */ 8500 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) { 8501 ASSERT(ptgt->m_reset_delay == 0); 8502 } 8503 8504 /* 8505 * if a non-tagged cmd is submitted to an active tagged target 8506 * then drain before submitting this cmd; SCSI-2 allows RQSENSE 8507 * to be untagged 8508 */ 8509 if (((cmd->cmd_pkt_flags & FLAG_TAGMASK) == 0) && 8510 (ptgt->m_t_ncmds > 1) && 8511 ((cmd->cmd_flags & CFLAG_TM_CMD) == 0) && 8512 (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE)) { 8513 if ((cmd->cmd_pkt_flags & FLAG_NOINTR) == 0) { 8514 NDBG23(("target=%d, untagged cmd, start draining\n", 8515 ptgt->m_devhdl)); 8516 8517 if (ptgt->m_reset_delay == 0) { 8518 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 8519 } 8520 8521 mptsas_remove_cmd(mpt, cmd); 8522 cmd->cmd_pkt_flags |= FLAG_HEAD; 8523 mptsas_waitq_add(mpt, cmd); 8524 } 8525 return (DDI_FAILURE); 8526 } 8527 8528 /* 8529 * Set correct tag bits. 8530 */ 8531 if (cmd->cmd_pkt_flags & FLAG_TAGMASK) { 8532 switch (mptsas_tag_lookup[((cmd->cmd_pkt_flags & 8533 FLAG_TAGMASK) >> 12)]) { 8534 case MSG_SIMPLE_QTAG: 8535 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ; 8536 break; 8537 case MSG_HEAD_QTAG: 8538 control |= MPI2_SCSIIO_CONTROL_HEADOFQ; 8539 break; 8540 case MSG_ORDERED_QTAG: 8541 control |= MPI2_SCSIIO_CONTROL_ORDEREDQ; 8542 break; 8543 default: 8544 mptsas_log(mpt, CE_WARN, "mpt: Invalid tag type\n"); 8545 break; 8546 } 8547 } else { 8548 if (*(cmd->cmd_pkt->pkt_cdbp) != SCMD_REQUEST_SENSE) { 8549 ptgt->m_t_throttle = 1; 8550 } 8551 control |= MPI2_SCSIIO_CONTROL_SIMPLEQ; 8552 } 8553 8554 if (cmd->cmd_pkt_flags & FLAG_TLR) { 8555 control |= MPI2_SCSIIO_CONTROL_TLR_ON; 8556 } 8557 8558 mem = mpt->m_req_frame + (mpt->m_req_frame_size * SMID); 8559 io_request = (pMpi2SCSIIORequest_t)mem; 8560 if (cmd->cmd_extrqslen != 0) { 8561 /* 8562 * Mapping of the buffer was done in mptsas_pkt_alloc_extern(). 8563 * Calculate the DMA address with the same offset. 8564 */ 8565 arsbuf = cmd->cmd_arq_buf; 8566 ars_size = cmd->cmd_extrqslen; 8567 ars_dmaaddrlow = (mpt->m_req_sense_dma_addr + 8568 ((uintptr_t)arsbuf - (uintptr_t)mpt->m_req_sense)) & 8569 0xffffffffu; 8570 } else { 8571 arsbuf = mpt->m_req_sense + (mpt->m_req_sense_size * (SMID-1)); 8572 cmd->cmd_arq_buf = arsbuf; 8573 ars_size = mpt->m_req_sense_size; 8574 ars_dmaaddrlow = (mpt->m_req_sense_dma_addr + 8575 (mpt->m_req_sense_size * (SMID-1))) & 8576 0xffffffffu; 8577 } 8578 bzero(io_request, sizeof (Mpi2SCSIIORequest_t)); 8579 bzero(arsbuf, ars_size); 8580 8581 ddi_put8(acc_hdl, &io_request->SGLOffset0, offsetof 8582 (MPI2_SCSI_IO_REQUEST, SGL) / 4); 8583 mptsas_init_std_hdr(acc_hdl, io_request, ptgt->m_devhdl, Lun(cmd), 0, 8584 MPI2_FUNCTION_SCSI_IO_REQUEST); 8585 8586 (void) ddi_rep_put8(acc_hdl, (uint8_t *)pkt->pkt_cdbp, 8587 io_request->CDB.CDB32, cmd->cmd_cdblen, DDI_DEV_AUTOINCR); 8588 8589 io_flags = cmd->cmd_cdblen; 8590 if (mptsas_use_fastpath && 8591 ptgt->m_io_flags & MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH) { 8592 io_flags |= MPI25_SCSIIO_IOFLAGS_FAST_PATH; 8593 request_desc = MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO; 8594 } else { 8595 request_desc = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; 8596 } 8597 ddi_put16(acc_hdl, &io_request->IoFlags, io_flags); 8598 /* 8599 * setup the Scatter/Gather DMA list for this request 8600 */ 8601 if (cmd->cmd_cookiec > 0) { 8602 mptsas_sge_setup(mpt, cmd, &control, io_request, acc_hdl); 8603 } else { 8604 ddi_put32(acc_hdl, &io_request->SGL.MpiSimple.FlagsLength, 8605 ((uint32_t)MPI2_SGE_FLAGS_LAST_ELEMENT | 8606 MPI2_SGE_FLAGS_END_OF_BUFFER | 8607 MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 8608 MPI2_SGE_FLAGS_END_OF_LIST) << MPI2_SGE_FLAGS_SHIFT); 8609 } 8610 8611 /* 8612 * save ARQ information 8613 */ 8614 ddi_put8(acc_hdl, &io_request->SenseBufferLength, ars_size); 8615 ddi_put32(acc_hdl, &io_request->SenseBufferLowAddress, ars_dmaaddrlow); 8616 8617 ddi_put32(acc_hdl, &io_request->Control, control); 8618 8619 NDBG31(("starting message=%d(0x%p), with cmd=0x%p", 8620 SMID, (void *)io_request, (void *)cmd)); 8621 8622 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV); 8623 (void) ddi_dma_sync(mpt->m_dma_req_sense_hdl, 0, 0, 8624 DDI_DMA_SYNC_FORDEV); 8625 8626 /* 8627 * Build request descriptor and write it to the request desc post reg. 8628 */ 8629 request_desc |= (SMID << 16); 8630 request_desc |= (uint64_t)ptgt->m_devhdl << 48; 8631 MPTSAS_START_CMD(mpt, request_desc); 8632 8633 /* 8634 * Start timeout. 8635 */ 8636 cmd->cmd_active_expiration = 8637 gethrtime() + (hrtime_t)pkt->pkt_time * NANOSEC; 8638 #ifdef MPTSAS_TEST 8639 /* 8640 * Force timeouts to happen immediately. 8641 */ 8642 if (mptsas_test_timeouts) 8643 cmd->cmd_active_expiration = gethrtime(); 8644 #endif 8645 c = TAILQ_FIRST(&ptgt->m_active_cmdq); 8646 if (c == NULL || 8647 c->cmd_active_expiration < cmd->cmd_active_expiration) { 8648 /* 8649 * Common case is that this is the last pending expiration 8650 * (or queue is empty). Insert at head of the queue. 8651 */ 8652 TAILQ_INSERT_HEAD(&ptgt->m_active_cmdq, cmd, cmd_active_link); 8653 } else { 8654 /* 8655 * Queue is not empty and first element expires later than 8656 * this command. Search for element expiring sooner. 8657 */ 8658 while ((c = TAILQ_NEXT(c, cmd_active_link)) != NULL) { 8659 if (c->cmd_active_expiration < 8660 cmd->cmd_active_expiration) { 8661 TAILQ_INSERT_BEFORE(c, cmd, cmd_active_link); 8662 break; 8663 } 8664 } 8665 if (c == NULL) { 8666 /* 8667 * No element found expiring sooner, append to 8668 * non-empty queue. 8669 */ 8670 TAILQ_INSERT_TAIL(&ptgt->m_active_cmdq, cmd, 8671 cmd_active_link); 8672 } 8673 } 8674 8675 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) || 8676 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) { 8677 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 8678 return (DDI_FAILURE); 8679 } 8680 return (DDI_SUCCESS); 8681 } 8682 8683 /* 8684 * Select a helper thread to handle current doneq 8685 */ 8686 static void 8687 mptsas_deliver_doneq_thread(mptsas_t *mpt) 8688 { 8689 uint64_t t, i; 8690 uint32_t min = 0xffffffff; 8691 mptsas_doneq_thread_list_t *item; 8692 8693 for (i = 0; i < mpt->m_doneq_thread_n; i++) { 8694 item = &mpt->m_doneq_thread_id[i]; 8695 /* 8696 * If the completed command on help thread[i] less than 8697 * doneq_thread_threshold, then pick the thread[i]. Otherwise 8698 * pick a thread which has least completed command. 8699 */ 8700 8701 mutex_enter(&item->mutex); 8702 if (item->len < mpt->m_doneq_thread_threshold) { 8703 t = i; 8704 mutex_exit(&item->mutex); 8705 break; 8706 } 8707 if (item->len < min) { 8708 min = item->len; 8709 t = i; 8710 } 8711 mutex_exit(&item->mutex); 8712 } 8713 mutex_enter(&mpt->m_doneq_thread_id[t].mutex); 8714 mptsas_doneq_mv(mpt, t); 8715 cv_signal(&mpt->m_doneq_thread_id[t].cv); 8716 mutex_exit(&mpt->m_doneq_thread_id[t].mutex); 8717 } 8718 8719 /* 8720 * move the current global doneq to the doneq of thead[t] 8721 */ 8722 static void 8723 mptsas_doneq_mv(mptsas_t *mpt, uint64_t t) 8724 { 8725 mptsas_cmd_t *cmd; 8726 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t]; 8727 8728 ASSERT(mutex_owned(&item->mutex)); 8729 while ((cmd = mpt->m_doneq) != NULL) { 8730 if ((mpt->m_doneq = cmd->cmd_linkp) == NULL) { 8731 mpt->m_donetail = &mpt->m_doneq; 8732 } 8733 cmd->cmd_linkp = NULL; 8734 *item->donetail = cmd; 8735 item->donetail = &cmd->cmd_linkp; 8736 mpt->m_doneq_len--; 8737 item->len++; 8738 } 8739 } 8740 8741 void 8742 mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd) 8743 { 8744 struct scsi_pkt *pkt = CMD2PKT(cmd); 8745 8746 /* Check all acc and dma handles */ 8747 if ((mptsas_check_acc_handle(mpt->m_datap) != 8748 DDI_SUCCESS) || 8749 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) != 8750 DDI_SUCCESS) || 8751 (mptsas_check_acc_handle(mpt->m_acc_req_sense_hdl) != 8752 DDI_SUCCESS) || 8753 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) != 8754 DDI_SUCCESS) || 8755 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) != 8756 DDI_SUCCESS) || 8757 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) != 8758 DDI_SUCCESS) || 8759 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) != 8760 DDI_SUCCESS) || 8761 (mptsas_check_acc_handle(mpt->m_config_handle) != 8762 DDI_SUCCESS)) { 8763 ddi_fm_service_impact(mpt->m_dip, 8764 DDI_SERVICE_UNAFFECTED); 8765 ddi_fm_acc_err_clear(mpt->m_config_handle, 8766 DDI_FME_VER0); 8767 pkt->pkt_reason = CMD_TRAN_ERR; 8768 pkt->pkt_statistics = 0; 8769 } 8770 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) != 8771 DDI_SUCCESS) || 8772 (mptsas_check_dma_handle(mpt->m_dma_req_sense_hdl) != 8773 DDI_SUCCESS) || 8774 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) != 8775 DDI_SUCCESS) || 8776 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) != 8777 DDI_SUCCESS) || 8778 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) != 8779 DDI_SUCCESS) || 8780 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) != 8781 DDI_SUCCESS)) { 8782 ddi_fm_service_impact(mpt->m_dip, 8783 DDI_SERVICE_UNAFFECTED); 8784 pkt->pkt_reason = CMD_TRAN_ERR; 8785 pkt->pkt_statistics = 0; 8786 } 8787 if (cmd->cmd_dmahandle && 8788 (mptsas_check_dma_handle(cmd->cmd_dmahandle) != DDI_SUCCESS)) { 8789 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 8790 pkt->pkt_reason = CMD_TRAN_ERR; 8791 pkt->pkt_statistics = 0; 8792 } 8793 if ((cmd->cmd_extra_frames && 8794 ((mptsas_check_dma_handle(cmd->cmd_extra_frames->m_dma_hdl) != 8795 DDI_SUCCESS) || 8796 (mptsas_check_acc_handle(cmd->cmd_extra_frames->m_acc_hdl) != 8797 DDI_SUCCESS)))) { 8798 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 8799 pkt->pkt_reason = CMD_TRAN_ERR; 8800 pkt->pkt_statistics = 0; 8801 } 8802 } 8803 8804 /* 8805 * These routines manipulate the queue of commands that 8806 * are waiting for their completion routines to be called. 8807 * The queue is usually in FIFO order but on an MP system 8808 * it's possible for the completion routines to get out 8809 * of order. If that's a problem you need to add a global 8810 * mutex around the code that calls the completion routine 8811 * in the interrupt handler. 8812 */ 8813 static void 8814 mptsas_doneq_add(mptsas_t *mpt, mptsas_cmd_t *cmd) 8815 { 8816 struct scsi_pkt *pkt = CMD2PKT(cmd); 8817 8818 NDBG31(("mptsas_doneq_add: cmd=0x%p", (void *)cmd)); 8819 8820 ASSERT((cmd->cmd_flags & CFLAG_COMPLETED) == 0); 8821 cmd->cmd_linkp = NULL; 8822 cmd->cmd_flags |= CFLAG_FINISHED; 8823 cmd->cmd_flags &= ~CFLAG_IN_TRANSPORT; 8824 8825 mptsas_fma_check(mpt, cmd); 8826 8827 /* 8828 * only add scsi pkts that have completion routines to 8829 * the doneq. no intr cmds do not have callbacks. 8830 */ 8831 if (pkt && (pkt->pkt_comp)) { 8832 *mpt->m_donetail = cmd; 8833 mpt->m_donetail = &cmd->cmd_linkp; 8834 mpt->m_doneq_len++; 8835 } 8836 } 8837 8838 static mptsas_cmd_t * 8839 mptsas_doneq_thread_rm(mptsas_t *mpt, uint64_t t) 8840 { 8841 mptsas_cmd_t *cmd; 8842 mptsas_doneq_thread_list_t *item = &mpt->m_doneq_thread_id[t]; 8843 8844 /* pop one off the done queue */ 8845 if ((cmd = item->doneq) != NULL) { 8846 /* if the queue is now empty fix the tail pointer */ 8847 NDBG31(("mptsas_doneq_thread_rm: cmd=0x%p", (void *)cmd)); 8848 if ((item->doneq = cmd->cmd_linkp) == NULL) { 8849 item->donetail = &item->doneq; 8850 } 8851 cmd->cmd_linkp = NULL; 8852 item->len--; 8853 } 8854 return (cmd); 8855 } 8856 8857 static void 8858 mptsas_doneq_empty(mptsas_t *mpt) 8859 { 8860 if (mpt->m_doneq && !mpt->m_in_callback) { 8861 mptsas_cmd_t *cmd, *next; 8862 struct scsi_pkt *pkt; 8863 8864 mpt->m_in_callback = 1; 8865 cmd = mpt->m_doneq; 8866 mpt->m_doneq = NULL; 8867 mpt->m_donetail = &mpt->m_doneq; 8868 mpt->m_doneq_len = 0; 8869 8870 mutex_exit(&mpt->m_mutex); 8871 /* 8872 * run the completion routines of all the 8873 * completed commands 8874 */ 8875 while (cmd != NULL) { 8876 next = cmd->cmd_linkp; 8877 cmd->cmd_linkp = NULL; 8878 /* run this command's completion routine */ 8879 cmd->cmd_flags |= CFLAG_COMPLETED; 8880 pkt = CMD2PKT(cmd); 8881 mptsas_pkt_comp(pkt, cmd); 8882 cmd = next; 8883 } 8884 mutex_enter(&mpt->m_mutex); 8885 mpt->m_in_callback = 0; 8886 } 8887 } 8888 8889 /* 8890 * These routines manipulate the target's queue of pending requests 8891 */ 8892 void 8893 mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd) 8894 { 8895 NDBG7(("mptsas_waitq_add: cmd=0x%p", (void *)cmd)); 8896 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 8897 cmd->cmd_queued = TRUE; 8898 if (ptgt) 8899 ptgt->m_t_nwait++; 8900 if (cmd->cmd_pkt_flags & FLAG_HEAD) { 8901 if ((cmd->cmd_linkp = mpt->m_waitq) == NULL) { 8902 mpt->m_waitqtail = &cmd->cmd_linkp; 8903 } 8904 mpt->m_waitq = cmd; 8905 } else { 8906 cmd->cmd_linkp = NULL; 8907 *(mpt->m_waitqtail) = cmd; 8908 mpt->m_waitqtail = &cmd->cmd_linkp; 8909 } 8910 } 8911 8912 static mptsas_cmd_t * 8913 mptsas_waitq_rm(mptsas_t *mpt) 8914 { 8915 mptsas_cmd_t *cmd; 8916 mptsas_target_t *ptgt; 8917 NDBG7(("mptsas_waitq_rm")); 8918 8919 MPTSAS_WAITQ_RM(mpt, cmd); 8920 8921 NDBG7(("mptsas_waitq_rm: cmd=0x%p", (void *)cmd)); 8922 if (cmd) { 8923 ptgt = cmd->cmd_tgt_addr; 8924 if (ptgt) { 8925 ptgt->m_t_nwait--; 8926 ASSERT(ptgt->m_t_nwait >= 0); 8927 } 8928 } 8929 return (cmd); 8930 } 8931 8932 /* 8933 * remove specified cmd from the middle of the wait queue. 8934 */ 8935 static void 8936 mptsas_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd) 8937 { 8938 mptsas_cmd_t *prevp = mpt->m_waitq; 8939 mptsas_target_t *ptgt = cmd->cmd_tgt_addr; 8940 8941 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p", 8942 (void *)mpt, (void *)cmd)); 8943 if (ptgt) { 8944 ptgt->m_t_nwait--; 8945 ASSERT(ptgt->m_t_nwait >= 0); 8946 } 8947 8948 if (prevp == cmd) { 8949 if ((mpt->m_waitq = cmd->cmd_linkp) == NULL) 8950 mpt->m_waitqtail = &mpt->m_waitq; 8951 8952 cmd->cmd_linkp = NULL; 8953 cmd->cmd_queued = FALSE; 8954 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p", 8955 (void *)mpt, (void *)cmd)); 8956 return; 8957 } 8958 8959 while (prevp != NULL) { 8960 if (prevp->cmd_linkp == cmd) { 8961 if ((prevp->cmd_linkp = cmd->cmd_linkp) == NULL) 8962 mpt->m_waitqtail = &prevp->cmd_linkp; 8963 8964 cmd->cmd_linkp = NULL; 8965 cmd->cmd_queued = FALSE; 8966 NDBG7(("mptsas_waitq_delete: mpt=0x%p cmd=0x%p", 8967 (void *)mpt, (void *)cmd)); 8968 return; 8969 } 8970 prevp = prevp->cmd_linkp; 8971 } 8972 cmn_err(CE_PANIC, "mpt: mptsas_waitq_delete: queue botch"); 8973 } 8974 8975 static mptsas_cmd_t * 8976 mptsas_tx_waitq_rm(mptsas_t *mpt) 8977 { 8978 mptsas_cmd_t *cmd; 8979 NDBG7(("mptsas_tx_waitq_rm")); 8980 8981 MPTSAS_TX_WAITQ_RM(mpt, cmd); 8982 8983 NDBG7(("mptsas_tx_waitq_rm: cmd=0x%p", (void *)cmd)); 8984 8985 return (cmd); 8986 } 8987 8988 /* 8989 * remove specified cmd from the middle of the tx_waitq. 8990 */ 8991 static void 8992 mptsas_tx_waitq_delete(mptsas_t *mpt, mptsas_cmd_t *cmd) 8993 { 8994 mptsas_cmd_t *prevp = mpt->m_tx_waitq; 8995 8996 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p", 8997 (void *)mpt, (void *)cmd)); 8998 8999 if (prevp == cmd) { 9000 if ((mpt->m_tx_waitq = cmd->cmd_linkp) == NULL) 9001 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; 9002 9003 cmd->cmd_linkp = NULL; 9004 cmd->cmd_queued = FALSE; 9005 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p", 9006 (void *)mpt, (void *)cmd)); 9007 return; 9008 } 9009 9010 while (prevp != NULL) { 9011 if (prevp->cmd_linkp == cmd) { 9012 if ((prevp->cmd_linkp = cmd->cmd_linkp) == NULL) 9013 mpt->m_tx_waitqtail = &prevp->cmd_linkp; 9014 9015 cmd->cmd_linkp = NULL; 9016 cmd->cmd_queued = FALSE; 9017 NDBG7(("mptsas_tx_waitq_delete: mpt=0x%p cmd=0x%p", 9018 (void *)mpt, (void *)cmd)); 9019 return; 9020 } 9021 prevp = prevp->cmd_linkp; 9022 } 9023 cmn_err(CE_PANIC, "mpt: mptsas_tx_waitq_delete: queue botch"); 9024 } 9025 9026 /* 9027 * device and bus reset handling 9028 * 9029 * Notes: 9030 * - RESET_ALL: reset the controller 9031 * - RESET_TARGET: reset the target specified in scsi_address 9032 */ 9033 static int 9034 mptsas_scsi_reset(struct scsi_address *ap, int level) 9035 { 9036 mptsas_t *mpt = ADDR2MPT(ap); 9037 int rval; 9038 mptsas_tgt_private_t *tgt_private; 9039 mptsas_target_t *ptgt = NULL; 9040 9041 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran->tran_tgt_private; 9042 ptgt = tgt_private->t_private; 9043 if (ptgt == NULL) { 9044 return (FALSE); 9045 } 9046 NDBG22(("mptsas_scsi_reset: target=%d level=%d", ptgt->m_devhdl, 9047 level)); 9048 9049 mutex_enter(&mpt->m_mutex); 9050 /* 9051 * if we are not in panic set up a reset delay for this target 9052 */ 9053 if (!ddi_in_panic()) { 9054 mptsas_setup_bus_reset_delay(mpt); 9055 } else { 9056 drv_usecwait(mpt->m_scsi_reset_delay * 1000); 9057 } 9058 rval = mptsas_do_scsi_reset(mpt, ptgt->m_devhdl); 9059 mutex_exit(&mpt->m_mutex); 9060 9061 /* 9062 * The transport layer expect to only see TRUE and 9063 * FALSE. Therefore, we will adjust the return value 9064 * if mptsas_do_scsi_reset returns FAILED. 9065 */ 9066 if (rval == FAILED) 9067 rval = FALSE; 9068 return (rval); 9069 } 9070 9071 static int 9072 mptsas_do_scsi_reset(mptsas_t *mpt, uint16_t devhdl) 9073 { 9074 int rval = FALSE; 9075 uint8_t config, disk; 9076 9077 ASSERT(mutex_owned(&mpt->m_mutex)); 9078 9079 if (mptsas_debug_resets) { 9080 mptsas_log(mpt, CE_WARN, "mptsas_do_scsi_reset: target=%d", 9081 devhdl); 9082 } 9083 9084 /* 9085 * Issue a Target Reset message to the target specified but not to a 9086 * disk making up a raid volume. Just look through the RAID config 9087 * Phys Disk list of DevHandles. If the target's DevHandle is in this 9088 * list, then don't reset this target. 9089 */ 9090 for (config = 0; config < mpt->m_num_raid_configs; config++) { 9091 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) { 9092 if (devhdl == mpt->m_raidconfig[config]. 9093 m_physdisk_devhdl[disk]) { 9094 return (TRUE); 9095 } 9096 } 9097 } 9098 9099 rval = mptsas_ioc_task_management(mpt, 9100 MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET, devhdl, 0, NULL, 0, 0); 9101 9102 mptsas_doneq_empty(mpt); 9103 return (rval); 9104 } 9105 9106 static int 9107 mptsas_scsi_reset_notify(struct scsi_address *ap, int flag, 9108 void (*callback)(caddr_t), caddr_t arg) 9109 { 9110 mptsas_t *mpt = ADDR2MPT(ap); 9111 9112 NDBG22(("mptsas_scsi_reset_notify: tgt=%d", ap->a_target)); 9113 9114 return (scsi_hba_reset_notify_setup(ap, flag, callback, arg, 9115 &mpt->m_mutex, &mpt->m_reset_notify_listf)); 9116 } 9117 9118 static int 9119 mptsas_get_name(struct scsi_device *sd, char *name, int len) 9120 { 9121 dev_info_t *lun_dip = NULL; 9122 9123 ASSERT(sd != NULL); 9124 ASSERT(name != NULL); 9125 lun_dip = sd->sd_dev; 9126 ASSERT(lun_dip != NULL); 9127 9128 if (mptsas_name_child(lun_dip, name, len) == DDI_SUCCESS) { 9129 return (1); 9130 } else { 9131 return (0); 9132 } 9133 } 9134 9135 static int 9136 mptsas_get_bus_addr(struct scsi_device *sd, char *name, int len) 9137 { 9138 return (mptsas_get_name(sd, name, len)); 9139 } 9140 9141 void 9142 mptsas_set_throttle(mptsas_t *mpt, mptsas_target_t *ptgt, int what) 9143 { 9144 9145 NDBG25(("mptsas_set_throttle: throttle=%x", what)); 9146 9147 /* 9148 * if the bus is draining/quiesced, no changes to the throttles 9149 * are allowed. Not allowing change of throttles during draining 9150 * limits error recovery but will reduce draining time 9151 * 9152 * all throttles should have been set to HOLD_THROTTLE 9153 */ 9154 if (mpt->m_softstate & (MPTSAS_SS_QUIESCED | MPTSAS_SS_DRAINING)) { 9155 return; 9156 } 9157 9158 if (what == HOLD_THROTTLE) { 9159 ptgt->m_t_throttle = HOLD_THROTTLE; 9160 } else if (ptgt->m_reset_delay == 0) { 9161 ptgt->m_t_throttle = what; 9162 } 9163 } 9164 9165 /* 9166 * Clean up from a device reset. 9167 * For the case of target reset, this function clears the waitq of all 9168 * commands for a particular target. For the case of abort task set, this 9169 * function clears the waitq of all commonds for a particular target/lun. 9170 */ 9171 static void 9172 mptsas_flush_target(mptsas_t *mpt, ushort_t target, int lun, uint8_t tasktype) 9173 { 9174 mptsas_slots_t *slots = mpt->m_active; 9175 mptsas_cmd_t *cmd, *next_cmd; 9176 int slot; 9177 uchar_t reason; 9178 uint_t stat; 9179 hrtime_t timestamp; 9180 9181 NDBG25(("mptsas_flush_target: target=%d lun=%d", target, lun)); 9182 9183 timestamp = gethrtime(); 9184 9185 /* 9186 * Make sure the I/O Controller has flushed all cmds 9187 * that are associated with this target for a target reset 9188 * and target/lun for abort task set. 9189 * Account for TM requests, which use the last SMID. 9190 */ 9191 for (slot = 0; slot <= mpt->m_active->m_n_normal; slot++) { 9192 if ((cmd = slots->m_slot[slot]) == NULL) 9193 continue; 9194 reason = CMD_RESET; 9195 stat = STAT_DEV_RESET; 9196 switch (tasktype) { 9197 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET: 9198 if (Tgt(cmd) == target) { 9199 if (cmd->cmd_active_expiration <= timestamp) { 9200 /* 9201 * When timeout requested, propagate 9202 * proper reason and statistics to 9203 * target drivers. 9204 */ 9205 reason = CMD_TIMEOUT; 9206 stat |= STAT_TIMEOUT; 9207 } 9208 NDBG25(("mptsas_flush_target discovered non-" 9209 "NULL cmd in slot %d, tasktype 0x%x", slot, 9210 tasktype)); 9211 mptsas_dump_cmd(mpt, cmd); 9212 mptsas_remove_cmd(mpt, cmd); 9213 mptsas_set_pkt_reason(mpt, cmd, reason, stat); 9214 mptsas_doneq_add(mpt, cmd); 9215 } 9216 break; 9217 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET: 9218 reason = CMD_ABORTED; 9219 stat = STAT_ABORTED; 9220 /*FALLTHROUGH*/ 9221 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET: 9222 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) { 9223 9224 NDBG25(("mptsas_flush_target discovered non-" 9225 "NULL cmd in slot %d, tasktype 0x%x", slot, 9226 tasktype)); 9227 mptsas_dump_cmd(mpt, cmd); 9228 mptsas_remove_cmd(mpt, cmd); 9229 mptsas_set_pkt_reason(mpt, cmd, reason, 9230 stat); 9231 mptsas_doneq_add(mpt, cmd); 9232 } 9233 break; 9234 default: 9235 break; 9236 } 9237 } 9238 9239 /* 9240 * Flush the waitq and tx_waitq of this target's cmds 9241 */ 9242 cmd = mpt->m_waitq; 9243 9244 reason = CMD_RESET; 9245 stat = STAT_DEV_RESET; 9246 9247 switch (tasktype) { 9248 case MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET: 9249 while (cmd != NULL) { 9250 next_cmd = cmd->cmd_linkp; 9251 if (Tgt(cmd) == target) { 9252 mptsas_waitq_delete(mpt, cmd); 9253 mptsas_set_pkt_reason(mpt, cmd, 9254 reason, stat); 9255 mptsas_doneq_add(mpt, cmd); 9256 } 9257 cmd = next_cmd; 9258 } 9259 mutex_enter(&mpt->m_tx_waitq_mutex); 9260 cmd = mpt->m_tx_waitq; 9261 while (cmd != NULL) { 9262 next_cmd = cmd->cmd_linkp; 9263 if (Tgt(cmd) == target) { 9264 mptsas_tx_waitq_delete(mpt, cmd); 9265 mutex_exit(&mpt->m_tx_waitq_mutex); 9266 mptsas_set_pkt_reason(mpt, cmd, 9267 reason, stat); 9268 mptsas_doneq_add(mpt, cmd); 9269 mutex_enter(&mpt->m_tx_waitq_mutex); 9270 } 9271 cmd = next_cmd; 9272 } 9273 mutex_exit(&mpt->m_tx_waitq_mutex); 9274 break; 9275 case MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET: 9276 reason = CMD_ABORTED; 9277 stat = STAT_ABORTED; 9278 /*FALLTHROUGH*/ 9279 case MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET: 9280 while (cmd != NULL) { 9281 next_cmd = cmd->cmd_linkp; 9282 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) { 9283 mptsas_waitq_delete(mpt, cmd); 9284 mptsas_set_pkt_reason(mpt, cmd, 9285 reason, stat); 9286 mptsas_doneq_add(mpt, cmd); 9287 } 9288 cmd = next_cmd; 9289 } 9290 mutex_enter(&mpt->m_tx_waitq_mutex); 9291 cmd = mpt->m_tx_waitq; 9292 while (cmd != NULL) { 9293 next_cmd = cmd->cmd_linkp; 9294 if ((Tgt(cmd) == target) && (Lun(cmd) == lun)) { 9295 mptsas_tx_waitq_delete(mpt, cmd); 9296 mutex_exit(&mpt->m_tx_waitq_mutex); 9297 mptsas_set_pkt_reason(mpt, cmd, 9298 reason, stat); 9299 mptsas_doneq_add(mpt, cmd); 9300 mutex_enter(&mpt->m_tx_waitq_mutex); 9301 } 9302 cmd = next_cmd; 9303 } 9304 mutex_exit(&mpt->m_tx_waitq_mutex); 9305 break; 9306 default: 9307 mptsas_log(mpt, CE_WARN, "Unknown task management type %d.", 9308 tasktype); 9309 break; 9310 } 9311 } 9312 9313 /* 9314 * Clean up hba state, abort all outstanding command and commands in waitq 9315 * reset timeout of all targets. 9316 */ 9317 static void 9318 mptsas_flush_hba(mptsas_t *mpt) 9319 { 9320 mptsas_slots_t *slots = mpt->m_active; 9321 mptsas_cmd_t *cmd; 9322 int slot; 9323 9324 NDBG25(("mptsas_flush_hba")); 9325 9326 /* 9327 * The I/O Controller should have already sent back 9328 * all commands via the scsi I/O reply frame. Make 9329 * sure all commands have been flushed. 9330 * Account for TM request, which use the last SMID. 9331 */ 9332 for (slot = 0; slot <= mpt->m_active->m_n_normal; slot++) { 9333 if ((cmd = slots->m_slot[slot]) == NULL) 9334 continue; 9335 9336 if (cmd->cmd_flags & CFLAG_CMDIOC) { 9337 /* 9338 * Need to make sure to tell everyone that might be 9339 * waiting on this command that it's going to fail. If 9340 * we get here, this command will never timeout because 9341 * the active command table is going to be re-allocated, 9342 * so there will be nothing to check against a time out. 9343 * Instead, mark the command as failed due to reset. 9344 */ 9345 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, 9346 STAT_BUS_RESET); 9347 if ((cmd->cmd_flags & 9348 (CFLAG_PASSTHRU | CFLAG_CONFIG | CFLAG_FW_DIAG))) { 9349 cmd->cmd_flags |= CFLAG_FINISHED; 9350 cv_broadcast(&mpt->m_passthru_cv); 9351 cv_broadcast(&mpt->m_config_cv); 9352 cv_broadcast(&mpt->m_fw_diag_cv); 9353 } 9354 continue; 9355 } 9356 9357 NDBG25(("mptsas_flush_hba discovered non-NULL cmd in slot %d", 9358 slot)); 9359 mptsas_dump_cmd(mpt, cmd); 9360 9361 mptsas_remove_cmd(mpt, cmd); 9362 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET); 9363 mptsas_doneq_add(mpt, cmd); 9364 } 9365 9366 /* 9367 * Flush the waitq. 9368 */ 9369 while ((cmd = mptsas_waitq_rm(mpt)) != NULL) { 9370 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET); 9371 if ((cmd->cmd_flags & CFLAG_PASSTHRU) || 9372 (cmd->cmd_flags & CFLAG_CONFIG) || 9373 (cmd->cmd_flags & CFLAG_FW_DIAG)) { 9374 cmd->cmd_flags |= CFLAG_FINISHED; 9375 cv_broadcast(&mpt->m_passthru_cv); 9376 cv_broadcast(&mpt->m_config_cv); 9377 cv_broadcast(&mpt->m_fw_diag_cv); 9378 } else { 9379 mptsas_doneq_add(mpt, cmd); 9380 } 9381 } 9382 9383 /* 9384 * Flush the tx_waitq 9385 */ 9386 mutex_enter(&mpt->m_tx_waitq_mutex); 9387 while ((cmd = mptsas_tx_waitq_rm(mpt)) != NULL) { 9388 mutex_exit(&mpt->m_tx_waitq_mutex); 9389 mptsas_set_pkt_reason(mpt, cmd, CMD_RESET, STAT_BUS_RESET); 9390 mptsas_doneq_add(mpt, cmd); 9391 mutex_enter(&mpt->m_tx_waitq_mutex); 9392 } 9393 mutex_exit(&mpt->m_tx_waitq_mutex); 9394 9395 /* 9396 * Drain the taskqs prior to reallocating resources. The thread 9397 * passing through here could be launched from either (dr) 9398 * or (event) taskqs so only wait on the 'other' queue since 9399 * waiting on 'this' queue is a deadlock condition. 9400 */ 9401 mutex_exit(&mpt->m_mutex); 9402 if (!taskq_member((taskq_t *)mpt->m_event_taskq, curthread)) 9403 ddi_taskq_wait(mpt->m_event_taskq); 9404 if (!taskq_member((taskq_t *)mpt->m_dr_taskq, curthread)) 9405 ddi_taskq_wait(mpt->m_dr_taskq); 9406 9407 mutex_enter(&mpt->m_mutex); 9408 } 9409 9410 /* 9411 * set pkt_reason and OR in pkt_statistics flag 9412 */ 9413 static void 9414 mptsas_set_pkt_reason(mptsas_t *mpt, mptsas_cmd_t *cmd, uchar_t reason, 9415 uint_t stat) 9416 { 9417 #ifndef __lock_lint 9418 _NOTE(ARGUNUSED(mpt)) 9419 #endif 9420 9421 NDBG25(("mptsas_set_pkt_reason: cmd=0x%p reason=%x stat=%x", 9422 (void *)cmd, reason, stat)); 9423 9424 if (cmd) { 9425 if (cmd->cmd_pkt->pkt_reason == CMD_CMPLT) { 9426 cmd->cmd_pkt->pkt_reason = reason; 9427 } 9428 cmd->cmd_pkt->pkt_statistics |= stat; 9429 } 9430 } 9431 9432 static void 9433 mptsas_start_watch_reset_delay() 9434 { 9435 NDBG22(("mptsas_start_watch_reset_delay")); 9436 9437 mutex_enter(&mptsas_global_mutex); 9438 if (mptsas_reset_watch == NULL && mptsas_timeouts_enabled) { 9439 mptsas_reset_watch = timeout(mptsas_watch_reset_delay, NULL, 9440 drv_usectohz((clock_t) 9441 MPTSAS_WATCH_RESET_DELAY_TICK * 1000)); 9442 ASSERT(mptsas_reset_watch != NULL); 9443 } 9444 mutex_exit(&mptsas_global_mutex); 9445 } 9446 9447 static void 9448 mptsas_setup_bus_reset_delay(mptsas_t *mpt) 9449 { 9450 mptsas_target_t *ptgt = NULL; 9451 9452 ASSERT(MUTEX_HELD(&mpt->m_mutex)); 9453 9454 NDBG22(("mptsas_setup_bus_reset_delay")); 9455 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 9456 ptgt = refhash_next(mpt->m_targets, ptgt)) { 9457 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE); 9458 ptgt->m_reset_delay = mpt->m_scsi_reset_delay; 9459 } 9460 9461 mptsas_start_watch_reset_delay(); 9462 } 9463 9464 /* 9465 * mptsas_watch_reset_delay(_subr) is invoked by timeout() and checks every 9466 * mpt instance for active reset delays 9467 */ 9468 static void 9469 mptsas_watch_reset_delay(void *arg) 9470 { 9471 #ifndef __lock_lint 9472 _NOTE(ARGUNUSED(arg)) 9473 #endif 9474 9475 mptsas_t *mpt; 9476 int not_done = 0; 9477 9478 NDBG22(("mptsas_watch_reset_delay")); 9479 9480 mutex_enter(&mptsas_global_mutex); 9481 mptsas_reset_watch = 0; 9482 mutex_exit(&mptsas_global_mutex); 9483 rw_enter(&mptsas_global_rwlock, RW_READER); 9484 for (mpt = mptsas_head; mpt != NULL; mpt = mpt->m_next) { 9485 if (mpt->m_tran == 0) { 9486 continue; 9487 } 9488 mutex_enter(&mpt->m_mutex); 9489 not_done += mptsas_watch_reset_delay_subr(mpt); 9490 mutex_exit(&mpt->m_mutex); 9491 } 9492 rw_exit(&mptsas_global_rwlock); 9493 9494 if (not_done) { 9495 mptsas_start_watch_reset_delay(); 9496 } 9497 } 9498 9499 static int 9500 mptsas_watch_reset_delay_subr(mptsas_t *mpt) 9501 { 9502 int done = 0; 9503 int restart = 0; 9504 mptsas_target_t *ptgt = NULL; 9505 9506 NDBG22(("mptsas_watch_reset_delay_subr: mpt=0x%p", (void *)mpt)); 9507 9508 ASSERT(mutex_owned(&mpt->m_mutex)); 9509 9510 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 9511 ptgt = refhash_next(mpt->m_targets, ptgt)) { 9512 if (ptgt->m_reset_delay != 0) { 9513 ptgt->m_reset_delay -= 9514 MPTSAS_WATCH_RESET_DELAY_TICK; 9515 if (ptgt->m_reset_delay <= 0) { 9516 ptgt->m_reset_delay = 0; 9517 mptsas_set_throttle(mpt, ptgt, 9518 MAX_THROTTLE); 9519 restart++; 9520 } else { 9521 done = -1; 9522 } 9523 } 9524 } 9525 9526 if (restart > 0) { 9527 mptsas_restart_hba(mpt); 9528 } 9529 return (done); 9530 } 9531 9532 #ifdef MPTSAS_TEST 9533 static void 9534 mptsas_test_reset(mptsas_t *mpt, int target) 9535 { 9536 mptsas_target_t *ptgt = NULL; 9537 9538 if (mptsas_rtest == target) { 9539 if (mptsas_do_scsi_reset(mpt, target) == TRUE) { 9540 mptsas_rtest = -1; 9541 } 9542 if (mptsas_rtest == -1) { 9543 NDBG22(("mptsas_test_reset success")); 9544 } 9545 } 9546 } 9547 #endif 9548 9549 /* 9550 * abort handling: 9551 * 9552 * Notes: 9553 * - if pkt is not NULL, abort just that command 9554 * - if pkt is NULL, abort all outstanding commands for target 9555 */ 9556 static int 9557 mptsas_scsi_abort(struct scsi_address *ap, struct scsi_pkt *pkt) 9558 { 9559 mptsas_t *mpt = ADDR2MPT(ap); 9560 int rval; 9561 mptsas_tgt_private_t *tgt_private; 9562 int target, lun; 9563 9564 tgt_private = (mptsas_tgt_private_t *)ap->a_hba_tran-> 9565 tran_tgt_private; 9566 ASSERT(tgt_private != NULL); 9567 target = tgt_private->t_private->m_devhdl; 9568 lun = tgt_private->t_lun; 9569 9570 NDBG23(("mptsas_scsi_abort: target=%d.%d", target, lun)); 9571 9572 mutex_enter(&mpt->m_mutex); 9573 rval = mptsas_do_scsi_abort(mpt, target, lun, pkt); 9574 mutex_exit(&mpt->m_mutex); 9575 return (rval); 9576 } 9577 9578 static int 9579 mptsas_do_scsi_abort(mptsas_t *mpt, int target, int lun, struct scsi_pkt *pkt) 9580 { 9581 mptsas_cmd_t *sp = NULL; 9582 mptsas_slots_t *slots = mpt->m_active; 9583 int rval = FALSE; 9584 9585 ASSERT(mutex_owned(&mpt->m_mutex)); 9586 9587 /* 9588 * Abort the command pkt on the target/lun in ap. If pkt is 9589 * NULL, abort all outstanding commands on that target/lun. 9590 * If you can abort them, return 1, else return 0. 9591 * Each packet that's aborted should be sent back to the target 9592 * driver through the callback routine, with pkt_reason set to 9593 * CMD_ABORTED. 9594 * 9595 * abort cmd pkt on HBA hardware; clean out of outstanding 9596 * command lists, etc. 9597 */ 9598 if (pkt != NULL) { 9599 /* abort the specified packet */ 9600 sp = PKT2CMD(pkt); 9601 9602 if (sp->cmd_queued) { 9603 NDBG23(("mptsas_do_scsi_abort: queued sp=0x%p aborted", 9604 (void *)sp)); 9605 mptsas_waitq_delete(mpt, sp); 9606 mptsas_set_pkt_reason(mpt, sp, CMD_ABORTED, 9607 STAT_ABORTED); 9608 mptsas_doneq_add(mpt, sp); 9609 rval = TRUE; 9610 goto done; 9611 } 9612 9613 /* 9614 * Have mpt firmware abort this command 9615 */ 9616 9617 if (slots->m_slot[sp->cmd_slot] != NULL) { 9618 rval = mptsas_ioc_task_management(mpt, 9619 MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK, target, 9620 lun, NULL, 0, 0); 9621 9622 /* 9623 * The transport layer expects only TRUE and FALSE. 9624 * Therefore, if mptsas_ioc_task_management returns 9625 * FAILED we will return FALSE. 9626 */ 9627 if (rval == FAILED) 9628 rval = FALSE; 9629 goto done; 9630 } 9631 } 9632 9633 /* 9634 * If pkt is NULL then abort task set 9635 */ 9636 rval = mptsas_ioc_task_management(mpt, 9637 MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET, target, lun, NULL, 0, 0); 9638 9639 /* 9640 * The transport layer expects only TRUE and FALSE. 9641 * Therefore, if mptsas_ioc_task_management returns 9642 * FAILED we will return FALSE. 9643 */ 9644 if (rval == FAILED) 9645 rval = FALSE; 9646 9647 #ifdef MPTSAS_TEST 9648 if (rval && mptsas_test_stop) { 9649 debug_enter("mptsas_do_scsi_abort"); 9650 } 9651 #endif 9652 9653 done: 9654 mptsas_doneq_empty(mpt); 9655 return (rval); 9656 } 9657 9658 /* 9659 * capability handling: 9660 * (*tran_getcap). Get the capability named, and return its value. 9661 */ 9662 static int 9663 mptsas_scsi_getcap(struct scsi_address *ap, char *cap, int tgtonly) 9664 { 9665 mptsas_t *mpt = ADDR2MPT(ap); 9666 int ckey; 9667 int rval = FALSE; 9668 9669 NDBG24(("mptsas_scsi_getcap: target=%d, cap=%s tgtonly=%x", 9670 ap->a_target, cap, tgtonly)); 9671 9672 mutex_enter(&mpt->m_mutex); 9673 9674 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) { 9675 mutex_exit(&mpt->m_mutex); 9676 return (UNDEFINED); 9677 } 9678 9679 switch (ckey) { 9680 case SCSI_CAP_DMA_MAX: 9681 rval = (int)mpt->m_msg_dma_attr.dma_attr_maxxfer; 9682 break; 9683 case SCSI_CAP_ARQ: 9684 rval = TRUE; 9685 break; 9686 case SCSI_CAP_MSG_OUT: 9687 case SCSI_CAP_PARITY: 9688 case SCSI_CAP_UNTAGGED_QING: 9689 rval = TRUE; 9690 break; 9691 case SCSI_CAP_TAGGED_QING: 9692 rval = TRUE; 9693 break; 9694 case SCSI_CAP_RESET_NOTIFICATION: 9695 rval = TRUE; 9696 break; 9697 case SCSI_CAP_LINKED_CMDS: 9698 rval = FALSE; 9699 break; 9700 case SCSI_CAP_QFULL_RETRIES: 9701 rval = ((mptsas_tgt_private_t *)(ap->a_hba_tran-> 9702 tran_tgt_private))->t_private->m_qfull_retries; 9703 break; 9704 case SCSI_CAP_QFULL_RETRY_INTERVAL: 9705 rval = drv_hztousec(((mptsas_tgt_private_t *) 9706 (ap->a_hba_tran->tran_tgt_private))-> 9707 t_private->m_qfull_retry_interval) / 1000; 9708 break; 9709 case SCSI_CAP_CDB_LEN: 9710 rval = CDB_GROUP4; 9711 break; 9712 case SCSI_CAP_INTERCONNECT_TYPE: 9713 rval = INTERCONNECT_SAS; 9714 break; 9715 case SCSI_CAP_TRAN_LAYER_RETRIES: 9716 if (mpt->m_ioc_capabilities & 9717 MPI2_IOCFACTS_CAPABILITY_TLR) 9718 rval = TRUE; 9719 else 9720 rval = FALSE; 9721 break; 9722 default: 9723 rval = UNDEFINED; 9724 break; 9725 } 9726 9727 NDBG24(("mptsas_scsi_getcap: %s, rval=%x", cap, rval)); 9728 9729 mutex_exit(&mpt->m_mutex); 9730 return (rval); 9731 } 9732 9733 /* 9734 * (*tran_setcap). Set the capability named to the value given. 9735 */ 9736 static int 9737 mptsas_scsi_setcap(struct scsi_address *ap, char *cap, int value, int tgtonly) 9738 { 9739 mptsas_t *mpt = ADDR2MPT(ap); 9740 int ckey; 9741 int rval = FALSE; 9742 9743 NDBG24(("mptsas_scsi_setcap: target=%d, cap=%s value=%x tgtonly=%x", 9744 ap->a_target, cap, value, tgtonly)); 9745 9746 if (!tgtonly) { 9747 return (rval); 9748 } 9749 9750 mutex_enter(&mpt->m_mutex); 9751 9752 if ((mptsas_scsi_capchk(cap, tgtonly, &ckey)) != TRUE) { 9753 mutex_exit(&mpt->m_mutex); 9754 return (UNDEFINED); 9755 } 9756 9757 switch (ckey) { 9758 case SCSI_CAP_DMA_MAX: 9759 case SCSI_CAP_MSG_OUT: 9760 case SCSI_CAP_PARITY: 9761 case SCSI_CAP_INITIATOR_ID: 9762 case SCSI_CAP_LINKED_CMDS: 9763 case SCSI_CAP_UNTAGGED_QING: 9764 case SCSI_CAP_RESET_NOTIFICATION: 9765 /* 9766 * None of these are settable via 9767 * the capability interface. 9768 */ 9769 break; 9770 case SCSI_CAP_ARQ: 9771 /* 9772 * We cannot turn off arq so return false if asked to 9773 */ 9774 if (value) { 9775 rval = TRUE; 9776 } else { 9777 rval = FALSE; 9778 } 9779 break; 9780 case SCSI_CAP_TAGGED_QING: 9781 mptsas_set_throttle(mpt, ((mptsas_tgt_private_t *) 9782 (ap->a_hba_tran->tran_tgt_private))->t_private, 9783 MAX_THROTTLE); 9784 rval = TRUE; 9785 break; 9786 case SCSI_CAP_QFULL_RETRIES: 9787 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))-> 9788 t_private->m_qfull_retries = (uchar_t)value; 9789 rval = TRUE; 9790 break; 9791 case SCSI_CAP_QFULL_RETRY_INTERVAL: 9792 ((mptsas_tgt_private_t *)(ap->a_hba_tran->tran_tgt_private))-> 9793 t_private->m_qfull_retry_interval = 9794 drv_usectohz(value * 1000); 9795 rval = TRUE; 9796 break; 9797 default: 9798 rval = UNDEFINED; 9799 break; 9800 } 9801 mutex_exit(&mpt->m_mutex); 9802 return (rval); 9803 } 9804 9805 /* 9806 * Utility routine for mptsas_ifsetcap/ifgetcap 9807 */ 9808 /*ARGSUSED*/ 9809 static int 9810 mptsas_scsi_capchk(char *cap, int tgtonly, int *cidxp) 9811 { 9812 NDBG24(("mptsas_scsi_capchk: cap=%s", cap)); 9813 9814 if (!cap) 9815 return (FALSE); 9816 9817 *cidxp = scsi_hba_lookup_capstr(cap); 9818 return (TRUE); 9819 } 9820 9821 static int 9822 mptsas_alloc_active_slots(mptsas_t *mpt, int flag) 9823 { 9824 mptsas_slots_t *old_active = mpt->m_active; 9825 mptsas_slots_t *new_active; 9826 size_t size; 9827 9828 /* 9829 * if there are active commands, then we cannot 9830 * change size of active slots array. 9831 */ 9832 ASSERT(mpt->m_ncmds == 0); 9833 9834 size = MPTSAS_SLOTS_SIZE(mpt); 9835 new_active = kmem_zalloc(size, flag); 9836 if (new_active == NULL) { 9837 NDBG1(("new active alloc failed")); 9838 return (-1); 9839 } 9840 /* 9841 * Since SMID 0 is reserved and the TM slot is reserved, the 9842 * number of slots that can be used at any one time is 9843 * m_max_requests - 2. 9844 */ 9845 new_active->m_n_normal = (mpt->m_max_requests - 2); 9846 new_active->m_size = size; 9847 new_active->m_rotor = 1; 9848 if (old_active) 9849 mptsas_free_active_slots(mpt); 9850 mpt->m_active = new_active; 9851 9852 return (0); 9853 } 9854 9855 static void 9856 mptsas_free_active_slots(mptsas_t *mpt) 9857 { 9858 mptsas_slots_t *active = mpt->m_active; 9859 size_t size; 9860 9861 if (active == NULL) 9862 return; 9863 size = active->m_size; 9864 kmem_free(active, size); 9865 mpt->m_active = NULL; 9866 } 9867 9868 /* 9869 * Error logging, printing, and debug print routines. 9870 */ 9871 static char *mptsas_label = "mpt_sas"; 9872 9873 /*PRINTFLIKE3*/ 9874 void 9875 mptsas_log(mptsas_t *mpt, int level, char *fmt, ...) 9876 { 9877 dev_info_t *dev; 9878 va_list ap; 9879 9880 if (mpt) { 9881 dev = mpt->m_dip; 9882 } else { 9883 dev = 0; 9884 } 9885 9886 mutex_enter(&mptsas_log_mutex); 9887 9888 va_start(ap, fmt); 9889 (void) vsprintf(mptsas_log_buf, fmt, ap); 9890 va_end(ap); 9891 9892 if (level == CE_CONT) { 9893 scsi_log(dev, mptsas_label, level, "%s\n", mptsas_log_buf); 9894 } else { 9895 scsi_log(dev, mptsas_label, level, "%s", mptsas_log_buf); 9896 } 9897 9898 mutex_exit(&mptsas_log_mutex); 9899 } 9900 9901 #ifdef MPTSAS_DEBUG 9902 /* 9903 * Use a circular buffer to log messages to private memory. 9904 * Increment idx atomically to minimize risk to miss lines. 9905 * It's fast and does not hold up the proceedings too much. 9906 */ 9907 static const size_t mptsas_dbglog_linecnt = MPTSAS_DBGLOG_LINECNT; 9908 static const size_t mptsas_dbglog_linelen = MPTSAS_DBGLOG_LINELEN; 9909 static char mptsas_dbglog_bufs[MPTSAS_DBGLOG_LINECNT][MPTSAS_DBGLOG_LINELEN]; 9910 static uint32_t mptsas_dbglog_idx = 0; 9911 9912 /*PRINTFLIKE1*/ 9913 void 9914 mptsas_debug_log(char *fmt, ...) 9915 { 9916 va_list ap; 9917 uint32_t idx; 9918 9919 idx = atomic_inc_32_nv(&mptsas_dbglog_idx) & 9920 (mptsas_dbglog_linecnt - 1); 9921 9922 va_start(ap, fmt); 9923 (void) vsnprintf(mptsas_dbglog_bufs[idx], 9924 mptsas_dbglog_linelen, fmt, ap); 9925 va_end(ap); 9926 } 9927 9928 /*PRINTFLIKE1*/ 9929 void 9930 mptsas_printf(char *fmt, ...) 9931 { 9932 dev_info_t *dev = 0; 9933 va_list ap; 9934 9935 mutex_enter(&mptsas_log_mutex); 9936 9937 va_start(ap, fmt); 9938 (void) vsprintf(mptsas_log_buf, fmt, ap); 9939 va_end(ap); 9940 9941 #ifdef PROM_PRINTF 9942 prom_printf("%s:\t%s\n", mptsas_label, mptsas_log_buf); 9943 #else 9944 scsi_log(dev, mptsas_label, CE_CONT, "!%s\n", mptsas_log_buf); 9945 #endif 9946 mutex_exit(&mptsas_log_mutex); 9947 } 9948 #endif 9949 9950 /* 9951 * timeout handling 9952 */ 9953 static void 9954 mptsas_watch(void *arg) 9955 { 9956 #ifndef __lock_lint 9957 _NOTE(ARGUNUSED(arg)) 9958 #endif 9959 9960 mptsas_t *mpt; 9961 uint32_t doorbell; 9962 9963 NDBG30(("mptsas_watch")); 9964 9965 rw_enter(&mptsas_global_rwlock, RW_READER); 9966 for (mpt = mptsas_head; mpt != (mptsas_t *)NULL; mpt = mpt->m_next) { 9967 9968 mutex_enter(&mpt->m_mutex); 9969 9970 /* Skip device if not powered on */ 9971 if (mpt->m_options & MPTSAS_OPT_PM) { 9972 if (mpt->m_power_level == PM_LEVEL_D0) { 9973 (void) pm_busy_component(mpt->m_dip, 0); 9974 mpt->m_busy = 1; 9975 } else { 9976 mutex_exit(&mpt->m_mutex); 9977 continue; 9978 } 9979 } 9980 9981 /* 9982 * Check if controller is in a FAULT state. If so, reset it. 9983 */ 9984 doorbell = ddi_get32(mpt->m_datap, &mpt->m_reg->Doorbell); 9985 if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { 9986 doorbell &= MPI2_DOORBELL_DATA_MASK; 9987 mptsas_log(mpt, CE_WARN, "MPT Firmware Fault, " 9988 "code: %04x", doorbell); 9989 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET; 9990 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) { 9991 mptsas_log(mpt, CE_WARN, "Reset failed" 9992 "after fault was detected"); 9993 } 9994 } 9995 9996 /* 9997 * For now, always call mptsas_watchsubr. 9998 */ 9999 mptsas_watchsubr(mpt); 10000 10001 if (mpt->m_options & MPTSAS_OPT_PM) { 10002 mpt->m_busy = 0; 10003 (void) pm_idle_component(mpt->m_dip, 0); 10004 } 10005 10006 mutex_exit(&mpt->m_mutex); 10007 } 10008 rw_exit(&mptsas_global_rwlock); 10009 10010 mutex_enter(&mptsas_global_mutex); 10011 if (mptsas_timeouts_enabled) 10012 mptsas_timeout_id = timeout(mptsas_watch, NULL, mptsas_tick); 10013 mutex_exit(&mptsas_global_mutex); 10014 } 10015 10016 static void 10017 mptsas_watchsubr_tgt(mptsas_t *mpt, mptsas_target_t *ptgt, hrtime_t timestamp) 10018 { 10019 mptsas_cmd_t *cmd; 10020 10021 /* 10022 * If we were draining due to a qfull condition, 10023 * go back to full throttle. 10024 */ 10025 if ((ptgt->m_t_throttle < MAX_THROTTLE) && 10026 (ptgt->m_t_throttle > HOLD_THROTTLE) && 10027 (ptgt->m_t_ncmds < ptgt->m_t_throttle)) { 10028 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 10029 mptsas_restart_hba(mpt); 10030 } 10031 10032 cmd = TAILQ_LAST(&ptgt->m_active_cmdq, mptsas_active_cmdq); 10033 if (cmd == NULL) 10034 return; 10035 10036 if (cmd->cmd_active_expiration <= timestamp) { 10037 /* 10038 * Earliest command timeout expired. Drain throttle. 10039 */ 10040 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 10041 10042 /* 10043 * Check for remaining commands. 10044 */ 10045 cmd = TAILQ_FIRST(&ptgt->m_active_cmdq); 10046 if (cmd->cmd_active_expiration > timestamp) { 10047 /* 10048 * Wait for remaining commands to complete or 10049 * time out. 10050 */ 10051 NDBG23(("command timed out, pending drain")); 10052 return; 10053 } 10054 10055 /* 10056 * All command timeouts expired. 10057 */ 10058 mptsas_log(mpt, CE_NOTE, "Timeout of %d seconds " 10059 "expired with %d commands on target %d lun %d.", 10060 cmd->cmd_pkt->pkt_time, ptgt->m_t_ncmds, 10061 ptgt->m_devhdl, Lun(cmd)); 10062 10063 mptsas_cmd_timeout(mpt, ptgt); 10064 } else if (cmd->cmd_active_expiration <= 10065 timestamp + (hrtime_t)mptsas_scsi_watchdog_tick * NANOSEC) { 10066 NDBG23(("pending timeout")); 10067 mptsas_set_throttle(mpt, ptgt, DRAIN_THROTTLE); 10068 } 10069 } 10070 10071 static void 10072 mptsas_watchsubr(mptsas_t *mpt) 10073 { 10074 int i; 10075 mptsas_cmd_t *cmd; 10076 mptsas_target_t *ptgt = NULL; 10077 hrtime_t timestamp = gethrtime(); 10078 10079 ASSERT(MUTEX_HELD(&mpt->m_mutex)); 10080 10081 NDBG30(("mptsas_watchsubr: mpt=0x%p", (void *)mpt)); 10082 10083 #ifdef MPTSAS_TEST 10084 if (mptsas_enable_untagged) { 10085 mptsas_test_untagged++; 10086 } 10087 #endif 10088 10089 /* 10090 * Check for commands stuck in active slot 10091 * Account for TM requests, which use the last SMID. 10092 */ 10093 for (i = 0; i <= mpt->m_active->m_n_normal; i++) { 10094 if ((cmd = mpt->m_active->m_slot[i]) != NULL) { 10095 if (cmd->cmd_active_expiration <= timestamp) { 10096 if ((cmd->cmd_flags & CFLAG_CMDIOC) == 0) { 10097 /* 10098 * There seems to be a command stuck 10099 * in the active slot. Drain throttle. 10100 */ 10101 mptsas_set_throttle(mpt, 10102 cmd->cmd_tgt_addr, 10103 DRAIN_THROTTLE); 10104 } else if (cmd->cmd_flags & 10105 (CFLAG_PASSTHRU | CFLAG_CONFIG | 10106 CFLAG_FW_DIAG)) { 10107 /* 10108 * passthrough command timeout 10109 */ 10110 cmd->cmd_flags |= (CFLAG_FINISHED | 10111 CFLAG_TIMEOUT); 10112 cv_broadcast(&mpt->m_passthru_cv); 10113 cv_broadcast(&mpt->m_config_cv); 10114 cv_broadcast(&mpt->m_fw_diag_cv); 10115 } 10116 } 10117 } 10118 } 10119 10120 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 10121 ptgt = refhash_next(mpt->m_targets, ptgt)) { 10122 mptsas_watchsubr_tgt(mpt, ptgt, timestamp); 10123 } 10124 10125 for (ptgt = refhash_first(mpt->m_tmp_targets); ptgt != NULL; 10126 ptgt = refhash_next(mpt->m_tmp_targets, ptgt)) { 10127 mptsas_watchsubr_tgt(mpt, ptgt, timestamp); 10128 } 10129 } 10130 10131 /* 10132 * timeout recovery 10133 */ 10134 static void 10135 mptsas_cmd_timeout(mptsas_t *mpt, mptsas_target_t *ptgt) 10136 { 10137 uint16_t devhdl; 10138 uint64_t sas_wwn; 10139 uint8_t phy; 10140 char wwn_str[MPTSAS_WWN_STRLEN]; 10141 10142 devhdl = ptgt->m_devhdl; 10143 sas_wwn = ptgt->m_addr.mta_wwn; 10144 phy = ptgt->m_phynum; 10145 if (sas_wwn == 0) { 10146 (void) sprintf(wwn_str, "p%x", phy); 10147 } else { 10148 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn); 10149 } 10150 10151 NDBG29(("mptsas_cmd_timeout: target=%d", devhdl)); 10152 mptsas_log(mpt, CE_WARN, "Disconnected command timeout for " 10153 "target %d %s, enclosure %u", devhdl, wwn_str, 10154 ptgt->m_enclosure); 10155 10156 /* 10157 * Abort all outstanding commands on the device. 10158 */ 10159 NDBG29(("mptsas_cmd_timeout: device reset")); 10160 if (mptsas_do_scsi_reset(mpt, devhdl) != TRUE) { 10161 mptsas_log(mpt, CE_WARN, "Target %d reset for command timeout " 10162 "recovery failed!", devhdl); 10163 } 10164 } 10165 10166 /* 10167 * Device / Hotplug control 10168 */ 10169 static int 10170 mptsas_scsi_quiesce(dev_info_t *dip) 10171 { 10172 mptsas_t *mpt; 10173 scsi_hba_tran_t *tran; 10174 10175 tran = ddi_get_driver_private(dip); 10176 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL) 10177 return (-1); 10178 10179 return (mptsas_quiesce_bus(mpt)); 10180 } 10181 10182 static int 10183 mptsas_scsi_unquiesce(dev_info_t *dip) 10184 { 10185 mptsas_t *mpt; 10186 scsi_hba_tran_t *tran; 10187 10188 tran = ddi_get_driver_private(dip); 10189 if (tran == NULL || (mpt = TRAN2MPT(tran)) == NULL) 10190 return (-1); 10191 10192 return (mptsas_unquiesce_bus(mpt)); 10193 } 10194 10195 static int 10196 mptsas_quiesce_bus(mptsas_t *mpt) 10197 { 10198 mptsas_target_t *ptgt = NULL; 10199 10200 NDBG28(("mptsas_quiesce_bus")); 10201 mutex_enter(&mpt->m_mutex); 10202 10203 /* Set all the throttles to zero */ 10204 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 10205 ptgt = refhash_next(mpt->m_targets, ptgt)) { 10206 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE); 10207 } 10208 10209 /* If there are any outstanding commands in the queue */ 10210 if (mpt->m_ncmds) { 10211 mpt->m_softstate |= MPTSAS_SS_DRAINING; 10212 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain, 10213 mpt, (MPTSAS_QUIESCE_TIMEOUT * drv_usectohz(1000000))); 10214 if (cv_wait_sig(&mpt->m_cv, &mpt->m_mutex) == 0) { 10215 /* 10216 * Quiesce has been interrupted 10217 */ 10218 mpt->m_softstate &= ~MPTSAS_SS_DRAINING; 10219 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 10220 ptgt = refhash_next(mpt->m_targets, ptgt)) { 10221 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 10222 } 10223 mptsas_restart_hba(mpt); 10224 if (mpt->m_quiesce_timeid != 0) { 10225 timeout_id_t tid = mpt->m_quiesce_timeid; 10226 mpt->m_quiesce_timeid = 0; 10227 mutex_exit(&mpt->m_mutex); 10228 (void) untimeout(tid); 10229 return (-1); 10230 } 10231 mutex_exit(&mpt->m_mutex); 10232 return (-1); 10233 } else { 10234 /* Bus has been quiesced */ 10235 ASSERT(mpt->m_quiesce_timeid == 0); 10236 mpt->m_softstate &= ~MPTSAS_SS_DRAINING; 10237 mpt->m_softstate |= MPTSAS_SS_QUIESCED; 10238 mutex_exit(&mpt->m_mutex); 10239 return (0); 10240 } 10241 } 10242 /* Bus was not busy - QUIESCED */ 10243 mutex_exit(&mpt->m_mutex); 10244 10245 return (0); 10246 } 10247 10248 static int 10249 mptsas_unquiesce_bus(mptsas_t *mpt) 10250 { 10251 mptsas_target_t *ptgt = NULL; 10252 10253 NDBG28(("mptsas_unquiesce_bus")); 10254 mutex_enter(&mpt->m_mutex); 10255 mpt->m_softstate &= ~MPTSAS_SS_QUIESCED; 10256 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 10257 ptgt = refhash_next(mpt->m_targets, ptgt)) { 10258 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 10259 } 10260 mptsas_restart_hba(mpt); 10261 mutex_exit(&mpt->m_mutex); 10262 return (0); 10263 } 10264 10265 static void 10266 mptsas_ncmds_checkdrain(void *arg) 10267 { 10268 mptsas_t *mpt = arg; 10269 mptsas_target_t *ptgt = NULL; 10270 10271 mutex_enter(&mpt->m_mutex); 10272 if (mpt->m_softstate & MPTSAS_SS_DRAINING) { 10273 mpt->m_quiesce_timeid = 0; 10274 if (mpt->m_ncmds == 0) { 10275 /* Command queue has been drained */ 10276 cv_signal(&mpt->m_cv); 10277 } else { 10278 /* 10279 * The throttle may have been reset because 10280 * of a SCSI bus reset 10281 */ 10282 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 10283 ptgt = refhash_next(mpt->m_targets, ptgt)) { 10284 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE); 10285 } 10286 10287 mpt->m_quiesce_timeid = timeout(mptsas_ncmds_checkdrain, 10288 mpt, (MPTSAS_QUIESCE_TIMEOUT * 10289 drv_usectohz(1000000))); 10290 } 10291 } 10292 mutex_exit(&mpt->m_mutex); 10293 } 10294 10295 /*ARGSUSED*/ 10296 static void 10297 mptsas_dump_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd) 10298 { 10299 int i; 10300 uint8_t *cp = (uchar_t *)cmd->cmd_pkt->pkt_cdbp; 10301 char buf[128]; 10302 10303 buf[0] = '\0'; 10304 NDBG25(("?Cmd (0x%p) dump for Target %d Lun %d:\n", (void *)cmd, 10305 Tgt(cmd), Lun(cmd))); 10306 (void) sprintf(&buf[0], "\tcdb=["); 10307 for (i = 0; i < (int)cmd->cmd_cdblen; i++) { 10308 (void) sprintf(&buf[strlen(buf)], " 0x%x", *cp++); 10309 } 10310 (void) sprintf(&buf[strlen(buf)], " ]"); 10311 NDBG25(("?%s\n", buf)); 10312 NDBG25(("?pkt_flags=0x%x pkt_statistics=0x%x pkt_state=0x%x\n", 10313 cmd->cmd_pkt->pkt_flags, cmd->cmd_pkt->pkt_statistics, 10314 cmd->cmd_pkt->pkt_state)); 10315 NDBG25(("?pkt_scbp=0x%x cmd_flags=0x%x\n", cmd->cmd_pkt->pkt_scbp ? 10316 *(cmd->cmd_pkt->pkt_scbp) : 0, cmd->cmd_flags)); 10317 } 10318 10319 static void 10320 mptsas_passthru_sge(ddi_acc_handle_t acc_hdl, mptsas_pt_request_t *pt, 10321 pMpi2SGESimple64_t sgep) 10322 { 10323 uint32_t sge_flags; 10324 uint32_t data_size, dataout_size; 10325 ddi_dma_cookie_t data_cookie; 10326 ddi_dma_cookie_t dataout_cookie; 10327 10328 data_size = pt->data_size; 10329 dataout_size = pt->dataout_size; 10330 data_cookie = pt->data_cookie; 10331 dataout_cookie = pt->dataout_cookie; 10332 10333 if (dataout_size) { 10334 sge_flags = dataout_size | 10335 ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 10336 MPI2_SGE_FLAGS_END_OF_BUFFER | 10337 MPI2_SGE_FLAGS_HOST_TO_IOC | 10338 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 10339 MPI2_SGE_FLAGS_SHIFT); 10340 ddi_put32(acc_hdl, &sgep->FlagsLength, sge_flags); 10341 ddi_put32(acc_hdl, &sgep->Address.Low, 10342 (uint32_t)(dataout_cookie.dmac_laddress & 10343 0xffffffffull)); 10344 ddi_put32(acc_hdl, &sgep->Address.High, 10345 (uint32_t)(dataout_cookie.dmac_laddress 10346 >> 32)); 10347 sgep++; 10348 } 10349 sge_flags = data_size; 10350 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 10351 MPI2_SGE_FLAGS_LAST_ELEMENT | 10352 MPI2_SGE_FLAGS_END_OF_BUFFER | 10353 MPI2_SGE_FLAGS_END_OF_LIST | 10354 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 10355 MPI2_SGE_FLAGS_SHIFT); 10356 if (pt->direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) { 10357 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_HOST_TO_IOC) << 10358 MPI2_SGE_FLAGS_SHIFT); 10359 } else { 10360 sge_flags |= ((uint32_t)(MPI2_SGE_FLAGS_IOC_TO_HOST) << 10361 MPI2_SGE_FLAGS_SHIFT); 10362 } 10363 ddi_put32(acc_hdl, &sgep->FlagsLength, 10364 sge_flags); 10365 ddi_put32(acc_hdl, &sgep->Address.Low, 10366 (uint32_t)(data_cookie.dmac_laddress & 10367 0xffffffffull)); 10368 ddi_put32(acc_hdl, &sgep->Address.High, 10369 (uint32_t)(data_cookie.dmac_laddress >> 32)); 10370 } 10371 10372 static void 10373 mptsas_passthru_ieee_sge(ddi_acc_handle_t acc_hdl, mptsas_pt_request_t *pt, 10374 pMpi2IeeeSgeSimple64_t ieeesgep) 10375 { 10376 uint8_t sge_flags; 10377 uint32_t data_size, dataout_size; 10378 ddi_dma_cookie_t data_cookie; 10379 ddi_dma_cookie_t dataout_cookie; 10380 10381 data_size = pt->data_size; 10382 dataout_size = pt->dataout_size; 10383 data_cookie = pt->data_cookie; 10384 dataout_cookie = pt->dataout_cookie; 10385 10386 sge_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 10387 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR); 10388 if (dataout_size) { 10389 ddi_put32(acc_hdl, &ieeesgep->Length, dataout_size); 10390 ddi_put32(acc_hdl, &ieeesgep->Address.Low, 10391 (uint32_t)(dataout_cookie.dmac_laddress & 10392 0xffffffffull)); 10393 ddi_put32(acc_hdl, &ieeesgep->Address.High, 10394 (uint32_t)(dataout_cookie.dmac_laddress >> 32)); 10395 ddi_put8(acc_hdl, &ieeesgep->Flags, sge_flags); 10396 ieeesgep++; 10397 } 10398 sge_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST; 10399 ddi_put32(acc_hdl, &ieeesgep->Length, data_size); 10400 ddi_put32(acc_hdl, &ieeesgep->Address.Low, 10401 (uint32_t)(data_cookie.dmac_laddress & 0xffffffffull)); 10402 ddi_put32(acc_hdl, &ieeesgep->Address.High, 10403 (uint32_t)(data_cookie.dmac_laddress >> 32)); 10404 ddi_put8(acc_hdl, &ieeesgep->Flags, sge_flags); 10405 } 10406 10407 static void 10408 mptsas_start_passthru(mptsas_t *mpt, mptsas_cmd_t *cmd) 10409 { 10410 caddr_t memp; 10411 pMPI2RequestHeader_t request_hdrp; 10412 struct scsi_pkt *pkt = cmd->cmd_pkt; 10413 mptsas_pt_request_t *pt = pkt->pkt_ha_private; 10414 uint32_t request_size; 10415 uint32_t i; 10416 uint64_t request_desc = 0; 10417 uint8_t desc_type; 10418 uint16_t SMID; 10419 uint8_t *request, function; 10420 ddi_dma_handle_t dma_hdl = mpt->m_dma_req_frame_hdl; 10421 ddi_acc_handle_t acc_hdl = mpt->m_acc_req_frame_hdl; 10422 10423 desc_type = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 10424 10425 request = pt->request; 10426 request_size = pt->request_size; 10427 10428 SMID = cmd->cmd_slot; 10429 10430 /* 10431 * Store the passthrough message in memory location 10432 * corresponding to our slot number 10433 */ 10434 memp = mpt->m_req_frame + (mpt->m_req_frame_size * SMID); 10435 request_hdrp = (pMPI2RequestHeader_t)memp; 10436 bzero(memp, mpt->m_req_frame_size); 10437 10438 for (i = 0; i < request_size; i++) { 10439 bcopy(request + i, memp + i, 1); 10440 } 10441 10442 NDBG15(("mptsas_start_passthru: Func 0x%x, MsgFlags 0x%x, " 10443 "size=%d, in %d, out %d, SMID %d", request_hdrp->Function, 10444 request_hdrp->MsgFlags, request_size, 10445 pt->data_size, pt->dataout_size, SMID)); 10446 10447 /* 10448 * Add an SGE, even if the length is zero. 10449 */ 10450 if (mpt->m_MPI25 && pt->simple == 0) { 10451 mptsas_passthru_ieee_sge(acc_hdl, pt, 10452 (pMpi2IeeeSgeSimple64_t) 10453 ((uint8_t *)request_hdrp + pt->sgl_offset)); 10454 } else { 10455 mptsas_passthru_sge(acc_hdl, pt, 10456 (pMpi2SGESimple64_t) 10457 ((uint8_t *)request_hdrp + pt->sgl_offset)); 10458 } 10459 10460 function = request_hdrp->Function; 10461 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) || 10462 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) { 10463 pMpi2SCSIIORequest_t scsi_io_req; 10464 caddr_t arsbuf; 10465 uint8_t ars_size; 10466 uint32_t ars_dmaaddrlow; 10467 10468 NDBG15(("mptsas_start_passthru: Is SCSI IO Req")); 10469 scsi_io_req = (pMpi2SCSIIORequest_t)request_hdrp; 10470 10471 if (cmd->cmd_extrqslen != 0) { 10472 /* 10473 * Mapping of the buffer was done in 10474 * mptsas_do_passthru(). 10475 * Calculate the DMA address with the same offset. 10476 */ 10477 arsbuf = cmd->cmd_arq_buf; 10478 ars_size = cmd->cmd_extrqslen; 10479 ars_dmaaddrlow = (mpt->m_req_sense_dma_addr + 10480 ((uintptr_t)arsbuf - (uintptr_t)mpt->m_req_sense)) & 10481 0xffffffffu; 10482 } else { 10483 arsbuf = mpt->m_req_sense + 10484 (mpt->m_req_sense_size * (SMID-1)); 10485 cmd->cmd_arq_buf = arsbuf; 10486 ars_size = mpt->m_req_sense_size; 10487 ars_dmaaddrlow = (mpt->m_req_sense_dma_addr + 10488 (mpt->m_req_sense_size * (SMID-1))) & 10489 0xffffffffu; 10490 } 10491 bzero(arsbuf, ars_size); 10492 10493 ddi_put8(acc_hdl, &scsi_io_req->SenseBufferLength, ars_size); 10494 ddi_put32(acc_hdl, &scsi_io_req->SenseBufferLowAddress, 10495 ars_dmaaddrlow); 10496 10497 /* 10498 * Put SGE for data and data_out buffer at the end of 10499 * scsi_io_request message header.(64 bytes in total) 10500 * Set SGLOffset0 value 10501 */ 10502 ddi_put8(acc_hdl, &scsi_io_req->SGLOffset0, 10503 offsetof(MPI2_SCSI_IO_REQUEST, SGL) / 4); 10504 10505 /* 10506 * Setup descriptor info. RAID passthrough must use the 10507 * default request descriptor which is already set, so if this 10508 * is a SCSI IO request, change the descriptor to SCSI IO. 10509 */ 10510 if (function == MPI2_FUNCTION_SCSI_IO_REQUEST) { 10511 desc_type = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO; 10512 request_desc = ((uint64_t)ddi_get16(acc_hdl, 10513 &scsi_io_req->DevHandle) << 48); 10514 } 10515 (void) ddi_dma_sync(mpt->m_dma_req_sense_hdl, 0, 0, 10516 DDI_DMA_SYNC_FORDEV); 10517 } 10518 10519 /* 10520 * We must wait till the message has been completed before 10521 * beginning the next message so we wait for this one to 10522 * finish. 10523 */ 10524 (void) ddi_dma_sync(dma_hdl, 0, 0, DDI_DMA_SYNC_FORDEV); 10525 request_desc |= (SMID << 16) + desc_type; 10526 cmd->cmd_rfm = NULL; 10527 MPTSAS_START_CMD(mpt, request_desc); 10528 if ((mptsas_check_dma_handle(dma_hdl) != DDI_SUCCESS) || 10529 (mptsas_check_acc_handle(acc_hdl) != DDI_SUCCESS)) { 10530 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 10531 } 10532 } 10533 10534 typedef void (mptsas_pre_f)(mptsas_t *, mptsas_pt_request_t *); 10535 static mptsas_pre_f mpi_pre_ioc_facts; 10536 static mptsas_pre_f mpi_pre_port_facts; 10537 static mptsas_pre_f mpi_pre_fw_download; 10538 static mptsas_pre_f mpi_pre_fw_25_download; 10539 static mptsas_pre_f mpi_pre_fw_upload; 10540 static mptsas_pre_f mpi_pre_fw_25_upload; 10541 static mptsas_pre_f mpi_pre_sata_passthrough; 10542 static mptsas_pre_f mpi_pre_smp_passthrough; 10543 static mptsas_pre_f mpi_pre_config; 10544 static mptsas_pre_f mpi_pre_sas_io_unit_control; 10545 static mptsas_pre_f mpi_pre_scsi_io_req; 10546 10547 /* 10548 * Prepare the pt for a SAS2 FW_DOWNLOAD request. 10549 */ 10550 static void 10551 mpi_pre_fw_download(mptsas_t *mpt, mptsas_pt_request_t *pt) 10552 { 10553 pMpi2FWDownloadTCSGE_t tcsge; 10554 pMpi2FWDownloadRequest req; 10555 10556 /* 10557 * If SAS3, call separate function. 10558 */ 10559 if (mpt->m_MPI25) { 10560 mpi_pre_fw_25_download(mpt, pt); 10561 return; 10562 } 10563 10564 /* 10565 * User requests should come in with the Transaction 10566 * context element where the SGL will go. Putting the 10567 * SGL after that seems to work, but don't really know 10568 * why. Other drivers tend to create an extra SGL and 10569 * refer to the TCE through that. 10570 */ 10571 req = (pMpi2FWDownloadRequest)pt->request; 10572 tcsge = (pMpi2FWDownloadTCSGE_t)&req->SGL; 10573 if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 || 10574 tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) { 10575 mptsas_log(mpt, CE_WARN, "FW Download tce invalid!"); 10576 } 10577 10578 pt->sgl_offset = offsetof(MPI2_FW_DOWNLOAD_REQUEST, SGL) + 10579 sizeof (*tcsge); 10580 if (pt->request_size != pt->sgl_offset) 10581 NDBG15(("mpi_pre_fw_download(): Incorrect req size, " 10582 "0x%x, should be 0x%x, dataoutsz 0x%x", 10583 (int)pt->request_size, (int)pt->sgl_offset, 10584 (int)pt->dataout_size)); 10585 if (pt->data_size < sizeof (MPI2_FW_DOWNLOAD_REPLY)) 10586 NDBG15(("mpi_pre_fw_download(): Incorrect rep size, " 10587 "0x%x, should be 0x%x", pt->data_size, 10588 (int)sizeof (MPI2_FW_DOWNLOAD_REPLY))); 10589 } 10590 10591 /* 10592 * Prepare the pt for a SAS3 FW_DOWNLOAD request. 10593 */ 10594 static void 10595 mpi_pre_fw_25_download(mptsas_t *mpt, mptsas_pt_request_t *pt) 10596 { 10597 pMpi2FWDownloadTCSGE_t tcsge; 10598 pMpi2FWDownloadRequest req2; 10599 pMpi25FWDownloadRequest req25; 10600 10601 /* 10602 * User requests should come in with the Transaction 10603 * context element where the SGL will go. The new firmware 10604 * Doesn't use TCE and has space in the main request for 10605 * this information. So move to the right place. 10606 */ 10607 req2 = (pMpi2FWDownloadRequest)pt->request; 10608 req25 = (pMpi25FWDownloadRequest)pt->request; 10609 tcsge = (pMpi2FWDownloadTCSGE_t)&req2->SGL; 10610 if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 || 10611 tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) { 10612 mptsas_log(mpt, CE_WARN, "FW Download tce invalid!"); 10613 } 10614 req25->ImageOffset = tcsge->ImageOffset; 10615 req25->ImageSize = tcsge->ImageSize; 10616 10617 pt->sgl_offset = offsetof(MPI25_FW_DOWNLOAD_REQUEST, SGL); 10618 if (pt->request_size != pt->sgl_offset) 10619 NDBG15(("mpi_pre_fw_25_download(): Incorrect req size, " 10620 "0x%x, should be 0x%x, dataoutsz 0x%x", 10621 pt->request_size, pt->sgl_offset, 10622 pt->dataout_size)); 10623 if (pt->data_size < sizeof (MPI2_FW_DOWNLOAD_REPLY)) 10624 NDBG15(("mpi_pre_fw_25_download(): Incorrect rep size, " 10625 "0x%x, should be 0x%x", pt->data_size, 10626 (int)sizeof (MPI2_FW_UPLOAD_REPLY))); 10627 } 10628 10629 /* 10630 * Prepare the pt for a SAS2 FW_UPLOAD request. 10631 */ 10632 static void 10633 mpi_pre_fw_upload(mptsas_t *mpt, mptsas_pt_request_t *pt) 10634 { 10635 pMpi2FWUploadTCSGE_t tcsge; 10636 pMpi2FWUploadRequest_t req; 10637 10638 /* 10639 * If SAS3, call separate function. 10640 */ 10641 if (mpt->m_MPI25) { 10642 mpi_pre_fw_25_upload(mpt, pt); 10643 return; 10644 } 10645 10646 /* 10647 * User requests should come in with the Transaction 10648 * context element where the SGL will go. Putting the 10649 * SGL after that seems to work, but don't really know 10650 * why. Other drivers tend to create an extra SGL and 10651 * refer to the TCE through that. 10652 */ 10653 req = (pMpi2FWUploadRequest_t)pt->request; 10654 tcsge = (pMpi2FWUploadTCSGE_t)&req->SGL; 10655 if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 || 10656 tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) { 10657 mptsas_log(mpt, CE_WARN, "FW Upload tce invalid!"); 10658 } 10659 10660 pt->sgl_offset = offsetof(MPI2_FW_UPLOAD_REQUEST, SGL) + 10661 sizeof (*tcsge); 10662 if (pt->request_size != pt->sgl_offset) 10663 NDBG15(("mpi_pre_fw_upload(): Incorrect req size, " 10664 "0x%x, should be 0x%x, dataoutsz 0x%x", 10665 pt->request_size, pt->sgl_offset, 10666 pt->dataout_size)); 10667 if (pt->data_size < sizeof (MPI2_FW_UPLOAD_REPLY)) 10668 NDBG15(("mpi_pre_fw_upload(): Incorrect rep size, " 10669 "0x%x, should be 0x%x", pt->data_size, 10670 (int)sizeof (MPI2_FW_UPLOAD_REPLY))); 10671 } 10672 10673 /* 10674 * Prepare the pt a SAS3 FW_UPLOAD request. 10675 */ 10676 static void 10677 mpi_pre_fw_25_upload(mptsas_t *mpt, mptsas_pt_request_t *pt) 10678 { 10679 pMpi2FWUploadTCSGE_t tcsge; 10680 pMpi2FWUploadRequest_t req2; 10681 pMpi25FWUploadRequest_t req25; 10682 10683 /* 10684 * User requests should come in with the Transaction 10685 * context element where the SGL will go. The new firmware 10686 * Doesn't use TCE and has space in the main request for 10687 * this information. So move to the right place. 10688 */ 10689 req2 = (pMpi2FWUploadRequest_t)pt->request; 10690 req25 = (pMpi25FWUploadRequest_t)pt->request; 10691 tcsge = (pMpi2FWUploadTCSGE_t)&req2->SGL; 10692 if (tcsge->ContextSize != 0 || tcsge->DetailsLength != 12 || 10693 tcsge->Flags != MPI2_SGE_FLAGS_TRANSACTION_ELEMENT) { 10694 mptsas_log(mpt, CE_WARN, "FW Upload tce invalid!"); 10695 } 10696 req25->ImageOffset = tcsge->ImageOffset; 10697 req25->ImageSize = tcsge->ImageSize; 10698 10699 pt->sgl_offset = offsetof(MPI25_FW_UPLOAD_REQUEST, SGL); 10700 if (pt->request_size != pt->sgl_offset) 10701 NDBG15(("mpi_pre_fw_25_upload(): Incorrect req size, " 10702 "0x%x, should be 0x%x, dataoutsz 0x%x", 10703 pt->request_size, pt->sgl_offset, 10704 pt->dataout_size)); 10705 if (pt->data_size < sizeof (MPI2_FW_UPLOAD_REPLY)) 10706 NDBG15(("mpi_pre_fw_25_upload(): Incorrect rep size, " 10707 "0x%x, should be 0x%x", pt->data_size, 10708 (int)sizeof (MPI2_FW_UPLOAD_REPLY))); 10709 } 10710 10711 /* 10712 * Prepare the pt for an IOC_FACTS request. 10713 */ 10714 static void 10715 mpi_pre_ioc_facts(mptsas_t *mpt, mptsas_pt_request_t *pt) 10716 { 10717 #ifndef __lock_lint 10718 _NOTE(ARGUNUSED(mpt)) 10719 #endif 10720 if (pt->request_size != sizeof (MPI2_IOC_FACTS_REQUEST)) 10721 NDBG15(("mpi_pre_ioc_facts(): Incorrect req size, " 10722 "0x%x, should be 0x%x, dataoutsz 0x%x", 10723 pt->request_size, 10724 (int)sizeof (MPI2_IOC_FACTS_REQUEST), 10725 pt->dataout_size)); 10726 if (pt->data_size != sizeof (MPI2_IOC_FACTS_REPLY)) 10727 NDBG15(("mpi_pre_ioc_facts(): Incorrect rep size, " 10728 "0x%x, should be 0x%x", pt->data_size, 10729 (int)sizeof (MPI2_IOC_FACTS_REPLY))); 10730 pt->sgl_offset = (uint16_t)pt->request_size; 10731 } 10732 10733 /* 10734 * Prepare the pt for a PORT_FACTS request. 10735 */ 10736 static void 10737 mpi_pre_port_facts(mptsas_t *mpt, mptsas_pt_request_t *pt) 10738 { 10739 #ifndef __lock_lint 10740 _NOTE(ARGUNUSED(mpt)) 10741 #endif 10742 if (pt->request_size != sizeof (MPI2_PORT_FACTS_REQUEST)) 10743 NDBG15(("mpi_pre_port_facts(): Incorrect req size, " 10744 "0x%x, should be 0x%x, dataoutsz 0x%x", 10745 pt->request_size, 10746 (int)sizeof (MPI2_PORT_FACTS_REQUEST), 10747 pt->dataout_size)); 10748 if (pt->data_size != sizeof (MPI2_PORT_FACTS_REPLY)) 10749 NDBG15(("mpi_pre_port_facts(): Incorrect rep size, " 10750 "0x%x, should be 0x%x", pt->data_size, 10751 (int)sizeof (MPI2_PORT_FACTS_REPLY))); 10752 pt->sgl_offset = (uint16_t)pt->request_size; 10753 } 10754 10755 /* 10756 * Prepare pt for a SATA_PASSTHROUGH request. 10757 */ 10758 static void 10759 mpi_pre_sata_passthrough(mptsas_t *mpt, mptsas_pt_request_t *pt) 10760 { 10761 #ifndef __lock_lint 10762 _NOTE(ARGUNUSED(mpt)) 10763 #endif 10764 pt->sgl_offset = offsetof(MPI2_SATA_PASSTHROUGH_REQUEST, SGL); 10765 if (pt->request_size != pt->sgl_offset) 10766 NDBG15(("mpi_pre_sata_passthrough(): Incorrect req size, " 10767 "0x%x, should be 0x%x, dataoutsz 0x%x", 10768 pt->request_size, pt->sgl_offset, 10769 pt->dataout_size)); 10770 if (pt->data_size != sizeof (MPI2_SATA_PASSTHROUGH_REPLY)) 10771 NDBG15(("mpi_pre_sata_passthrough(): Incorrect rep size, " 10772 "0x%x, should be 0x%x", pt->data_size, 10773 (int)sizeof (MPI2_SATA_PASSTHROUGH_REPLY))); 10774 } 10775 10776 static void 10777 mpi_pre_smp_passthrough(mptsas_t *mpt, mptsas_pt_request_t *pt) 10778 { 10779 #ifndef __lock_lint 10780 _NOTE(ARGUNUSED(mpt)) 10781 #endif 10782 pt->sgl_offset = offsetof(MPI2_SMP_PASSTHROUGH_REQUEST, SGL); 10783 if (pt->request_size != pt->sgl_offset) 10784 NDBG15(("mpi_pre_smp_passthrough(): Incorrect req size, " 10785 "0x%x, should be 0x%x, dataoutsz 0x%x", 10786 pt->request_size, pt->sgl_offset, 10787 pt->dataout_size)); 10788 if (pt->data_size != sizeof (MPI2_SMP_PASSTHROUGH_REPLY)) 10789 NDBG15(("mpi_pre_smp_passthrough(): Incorrect rep size, " 10790 "0x%x, should be 0x%x", pt->data_size, 10791 (int)sizeof (MPI2_SMP_PASSTHROUGH_REPLY))); 10792 } 10793 10794 /* 10795 * Prepare pt for a CONFIG request. 10796 */ 10797 static void 10798 mpi_pre_config(mptsas_t *mpt, mptsas_pt_request_t *pt) 10799 { 10800 #ifndef __lock_lint 10801 _NOTE(ARGUNUSED(mpt)) 10802 #endif 10803 pt->sgl_offset = offsetof(MPI2_CONFIG_REQUEST, PageBufferSGE); 10804 if (pt->request_size != pt->sgl_offset) 10805 NDBG15(("mpi_pre_config(): Incorrect req size, 0x%x, " 10806 "should be 0x%x, dataoutsz 0x%x", pt->request_size, 10807 pt->sgl_offset, pt->dataout_size)); 10808 if (pt->data_size != sizeof (MPI2_CONFIG_REPLY)) 10809 NDBG15(("mpi_pre_config(): Incorrect rep size, 0x%x, " 10810 "should be 0x%x", pt->data_size, 10811 (int)sizeof (MPI2_CONFIG_REPLY))); 10812 pt->simple = 1; 10813 } 10814 10815 /* 10816 * Prepare pt for a SCSI_IO_REQ request. 10817 */ 10818 static void 10819 mpi_pre_scsi_io_req(mptsas_t *mpt, mptsas_pt_request_t *pt) 10820 { 10821 #ifndef __lock_lint 10822 _NOTE(ARGUNUSED(mpt)) 10823 #endif 10824 pt->sgl_offset = offsetof(MPI2_SCSI_IO_REQUEST, SGL); 10825 if (pt->request_size != pt->sgl_offset) 10826 NDBG15(("mpi_pre_config(): Incorrect req size, 0x%x, " 10827 "should be 0x%x, dataoutsz 0x%x", pt->request_size, 10828 pt->sgl_offset, 10829 pt->dataout_size)); 10830 if (pt->data_size != sizeof (MPI2_SCSI_IO_REPLY)) 10831 NDBG15(("mpi_pre_config(): Incorrect rep size, 0x%x, " 10832 "should be 0x%x", pt->data_size, 10833 (int)sizeof (MPI2_SCSI_IO_REPLY))); 10834 } 10835 10836 /* 10837 * Prepare the mptsas_cmd for a SAS_IO_UNIT_CONTROL request. 10838 */ 10839 static void 10840 mpi_pre_sas_io_unit_control(mptsas_t *mpt, mptsas_pt_request_t *pt) 10841 { 10842 #ifndef __lock_lint 10843 _NOTE(ARGUNUSED(mpt)) 10844 #endif 10845 pt->sgl_offset = (uint16_t)pt->request_size; 10846 } 10847 10848 /* 10849 * A set of functions to prepare an mptsas_cmd for the various 10850 * supported requests. 10851 */ 10852 static struct mptsas_func { 10853 U8 Function; 10854 char *Name; 10855 mptsas_pre_f *f_pre; 10856 } mptsas_func_list[] = { 10857 { MPI2_FUNCTION_IOC_FACTS, "IOC_FACTS", mpi_pre_ioc_facts }, 10858 { MPI2_FUNCTION_PORT_FACTS, "PORT_FACTS", mpi_pre_port_facts }, 10859 { MPI2_FUNCTION_FW_DOWNLOAD, "FW_DOWNLOAD", mpi_pre_fw_download }, 10860 { MPI2_FUNCTION_FW_UPLOAD, "FW_UPLOAD", mpi_pre_fw_upload }, 10861 { MPI2_FUNCTION_SATA_PASSTHROUGH, "SATA_PASSTHROUGH", 10862 mpi_pre_sata_passthrough }, 10863 { MPI2_FUNCTION_SMP_PASSTHROUGH, "SMP_PASSTHROUGH", 10864 mpi_pre_smp_passthrough}, 10865 { MPI2_FUNCTION_SCSI_IO_REQUEST, "SCSI_IO_REQUEST", 10866 mpi_pre_scsi_io_req}, 10867 { MPI2_FUNCTION_CONFIG, "CONFIG", mpi_pre_config}, 10868 { MPI2_FUNCTION_SAS_IO_UNIT_CONTROL, "SAS_IO_UNIT_CONTROL", 10869 mpi_pre_sas_io_unit_control }, 10870 { 0xFF, NULL, NULL } /* list end */ 10871 }; 10872 10873 static void 10874 mptsas_prep_sgl_offset(mptsas_t *mpt, mptsas_pt_request_t *pt) 10875 { 10876 pMPI2RequestHeader_t hdr; 10877 struct mptsas_func *f; 10878 10879 hdr = (pMPI2RequestHeader_t)pt->request; 10880 10881 for (f = mptsas_func_list; f->f_pre != NULL; f++) { 10882 if (hdr->Function == f->Function) { 10883 f->f_pre(mpt, pt); 10884 NDBG15(("mptsas_prep_sgl_offset: Function %s," 10885 " sgl_offset 0x%x", f->Name, 10886 pt->sgl_offset)); 10887 return; 10888 } 10889 } 10890 NDBG15(("mptsas_prep_sgl_offset: Unknown Function 0x%02x," 10891 " returning req_size 0x%x for sgl_offset", 10892 hdr->Function, pt->request_size)); 10893 pt->sgl_offset = (uint16_t)pt->request_size; 10894 } 10895 10896 10897 static int 10898 mptsas_do_passthru(mptsas_t *mpt, uint8_t *request, uint8_t *reply, 10899 uint8_t *data, uint32_t request_size, uint32_t reply_size, 10900 uint32_t data_size, uint32_t direction, uint8_t *dataout, 10901 uint32_t dataout_size, short timeout, int mode) 10902 { 10903 mptsas_pt_request_t pt; 10904 mptsas_dma_alloc_state_t data_dma_state; 10905 mptsas_dma_alloc_state_t dataout_dma_state; 10906 caddr_t memp; 10907 mptsas_cmd_t *cmd = NULL; 10908 struct scsi_pkt *pkt; 10909 uint32_t reply_len = 0, sense_len = 0; 10910 pMPI2RequestHeader_t request_hdrp; 10911 pMPI2RequestHeader_t request_msg; 10912 pMPI2DefaultReply_t reply_msg; 10913 Mpi2SCSIIOReply_t rep_msg; 10914 int rvalue; 10915 int i, status = 0, pt_flags = 0, rv = 0; 10916 uint8_t function; 10917 10918 ASSERT(mutex_owned(&mpt->m_mutex)); 10919 10920 reply_msg = (pMPI2DefaultReply_t)(&rep_msg); 10921 bzero(reply_msg, sizeof (MPI2_DEFAULT_REPLY)); 10922 request_msg = kmem_zalloc(request_size, KM_SLEEP); 10923 10924 mutex_exit(&mpt->m_mutex); 10925 /* 10926 * copy in the request buffer since it could be used by 10927 * another thread when the pt request into waitq 10928 */ 10929 if (ddi_copyin(request, request_msg, request_size, mode)) { 10930 mutex_enter(&mpt->m_mutex); 10931 status = EFAULT; 10932 mptsas_log(mpt, CE_WARN, "failed to copy request data"); 10933 goto out; 10934 } 10935 NDBG27(("mptsas_do_passthru: mode 0x%x, size 0x%x, Func 0x%x", 10936 mode, request_size, request_msg->Function)); 10937 mutex_enter(&mpt->m_mutex); 10938 10939 function = request_msg->Function; 10940 if (function == MPI2_FUNCTION_SCSI_TASK_MGMT) { 10941 pMpi2SCSITaskManagementRequest_t task; 10942 task = (pMpi2SCSITaskManagementRequest_t)request_msg; 10943 mptsas_setup_bus_reset_delay(mpt); 10944 rv = mptsas_ioc_task_management(mpt, task->TaskType, 10945 task->DevHandle, (int)task->LUN[1], reply, reply_size, 10946 mode); 10947 10948 if (rv != TRUE) { 10949 status = EIO; 10950 mptsas_log(mpt, CE_WARN, "task management failed"); 10951 } 10952 goto out; 10953 } 10954 10955 if (data_size != 0) { 10956 data_dma_state.size = data_size; 10957 if (mptsas_dma_alloc(mpt, &data_dma_state) != DDI_SUCCESS) { 10958 status = ENOMEM; 10959 mptsas_log(mpt, CE_WARN, "failed to alloc DMA " 10960 "resource"); 10961 goto out; 10962 } 10963 pt_flags |= MPTSAS_DATA_ALLOCATED; 10964 if (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE) { 10965 mutex_exit(&mpt->m_mutex); 10966 for (i = 0; i < data_size; i++) { 10967 if (ddi_copyin(data + i, (uint8_t *) 10968 data_dma_state.memp + i, 1, mode)) { 10969 mutex_enter(&mpt->m_mutex); 10970 status = EFAULT; 10971 mptsas_log(mpt, CE_WARN, "failed to " 10972 "copy read data"); 10973 goto out; 10974 } 10975 } 10976 mutex_enter(&mpt->m_mutex); 10977 } 10978 } else { 10979 bzero(&data_dma_state, sizeof (data_dma_state)); 10980 } 10981 10982 if (dataout_size != 0) { 10983 dataout_dma_state.size = dataout_size; 10984 if (mptsas_dma_alloc(mpt, &dataout_dma_state) != DDI_SUCCESS) { 10985 status = ENOMEM; 10986 mptsas_log(mpt, CE_WARN, "failed to alloc DMA " 10987 "resource"); 10988 goto out; 10989 } 10990 pt_flags |= MPTSAS_DATAOUT_ALLOCATED; 10991 mutex_exit(&mpt->m_mutex); 10992 for (i = 0; i < dataout_size; i++) { 10993 if (ddi_copyin(dataout + i, (uint8_t *) 10994 dataout_dma_state.memp + i, 1, mode)) { 10995 mutex_enter(&mpt->m_mutex); 10996 mptsas_log(mpt, CE_WARN, "failed to copy out" 10997 " data"); 10998 status = EFAULT; 10999 goto out; 11000 } 11001 } 11002 mutex_enter(&mpt->m_mutex); 11003 } else { 11004 bzero(&dataout_dma_state, sizeof (dataout_dma_state)); 11005 } 11006 11007 if ((rvalue = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) { 11008 status = EAGAIN; 11009 mptsas_log(mpt, CE_NOTE, "event ack command pool is full"); 11010 goto out; 11011 } 11012 pt_flags |= MPTSAS_REQUEST_POOL_CMD; 11013 11014 bzero((caddr_t)cmd, sizeof (*cmd)); 11015 bzero((caddr_t)pkt, scsi_pkt_size()); 11016 bzero((caddr_t)&pt, sizeof (pt)); 11017 11018 cmd->ioc_cmd_slot = (uint32_t)(rvalue); 11019 11020 pt.request = (uint8_t *)request_msg; 11021 pt.direction = direction; 11022 pt.simple = 0; 11023 pt.request_size = request_size; 11024 pt.data_size = data_size; 11025 pt.dataout_size = dataout_size; 11026 pt.data_cookie = data_dma_state.cookie; 11027 pt.dataout_cookie = dataout_dma_state.cookie; 11028 mptsas_prep_sgl_offset(mpt, &pt); 11029 11030 /* 11031 * Form a blank cmd/pkt to store the acknowledgement message 11032 */ 11033 pkt->pkt_cdbp = (opaque_t)&cmd->cmd_cdb[0]; 11034 pkt->pkt_scbp = (opaque_t)&cmd->cmd_scb; 11035 pkt->pkt_ha_private = (opaque_t)&pt; 11036 pkt->pkt_flags = FLAG_HEAD; 11037 pkt->pkt_time = timeout; 11038 cmd->cmd_pkt = pkt; 11039 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_PASSTHRU; 11040 11041 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) || 11042 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) { 11043 uint8_t com, cdb_group_id; 11044 boolean_t ret; 11045 11046 pkt->pkt_cdbp = ((pMpi2SCSIIORequest_t)request_msg)->CDB.CDB32; 11047 com = pkt->pkt_cdbp[0]; 11048 cdb_group_id = CDB_GROUPID(com); 11049 switch (cdb_group_id) { 11050 case CDB_GROUPID_0: cmd->cmd_cdblen = CDB_GROUP0; break; 11051 case CDB_GROUPID_1: cmd->cmd_cdblen = CDB_GROUP1; break; 11052 case CDB_GROUPID_2: cmd->cmd_cdblen = CDB_GROUP2; break; 11053 case CDB_GROUPID_4: cmd->cmd_cdblen = CDB_GROUP4; break; 11054 case CDB_GROUPID_5: cmd->cmd_cdblen = CDB_GROUP5; break; 11055 default: 11056 NDBG27(("mptsas_do_passthru: SCSI_IO, reserved " 11057 "CDBGROUP 0x%x requested!", cdb_group_id)); 11058 break; 11059 } 11060 11061 reply_len = sizeof (MPI2_SCSI_IO_REPLY); 11062 sense_len = reply_size - reply_len; 11063 ret = mptsas_cmdarqsize(mpt, cmd, sense_len, KM_SLEEP); 11064 VERIFY(ret == B_TRUE); 11065 } else { 11066 reply_len = reply_size; 11067 sense_len = 0; 11068 } 11069 11070 NDBG27(("mptsas_do_passthru: %s, dsz 0x%x, dosz 0x%x, replen 0x%x, " 11071 "snslen 0x%x", 11072 (direction == MPTSAS_PASS_THRU_DIRECTION_WRITE)?"Write":"Read", 11073 data_size, dataout_size, reply_len, sense_len)); 11074 11075 /* 11076 * Save the command in a slot 11077 */ 11078 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 11079 /* 11080 * Once passthru command get slot, set cmd_flags 11081 * CFLAG_PREPARED. 11082 */ 11083 cmd->cmd_flags |= CFLAG_PREPARED; 11084 mptsas_start_passthru(mpt, cmd); 11085 } else { 11086 mptsas_waitq_add(mpt, cmd); 11087 } 11088 11089 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) { 11090 cv_wait(&mpt->m_passthru_cv, &mpt->m_mutex); 11091 } 11092 11093 NDBG27(("mptsas_do_passthru: Cmd complete, flags 0x%x, rfm 0x%x " 11094 "pktreason 0x%x", cmd->cmd_flags, cmd->cmd_rfm, 11095 pkt->pkt_reason)); 11096 11097 if (cmd->cmd_flags & CFLAG_PREPARED) { 11098 memp = mpt->m_req_frame + (mpt->m_req_frame_size * 11099 cmd->cmd_slot); 11100 request_hdrp = (pMPI2RequestHeader_t)memp; 11101 } 11102 11103 if (cmd->cmd_flags & CFLAG_TIMEOUT) { 11104 status = ETIMEDOUT; 11105 mptsas_log(mpt, CE_WARN, "passthrough command timeout"); 11106 pt_flags |= MPTSAS_CMD_TIMEOUT; 11107 goto out; 11108 } 11109 11110 if (cmd->cmd_rfm) { 11111 /* 11112 * cmd_rfm is zero means the command reply is a CONTEXT 11113 * reply and no PCI Write to post the free reply SMFA 11114 * because no reply message frame is used. 11115 * cmd_rfm is non-zero means the reply is a ADDRESS 11116 * reply and reply message frame is used. 11117 */ 11118 pt_flags |= MPTSAS_ADDRESS_REPLY; 11119 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0, 11120 DDI_DMA_SYNC_FORCPU); 11121 reply_msg = (pMPI2DefaultReply_t) 11122 (mpt->m_reply_frame + (cmd->cmd_rfm - 11123 (mpt->m_reply_frame_dma_addr & 0xffffffffu))); 11124 } 11125 11126 mptsas_fma_check(mpt, cmd); 11127 if (pkt->pkt_reason == CMD_TRAN_ERR) { 11128 status = EAGAIN; 11129 mptsas_log(mpt, CE_WARN, "passthru fma error"); 11130 goto out; 11131 } 11132 if (pkt->pkt_reason == CMD_RESET) { 11133 status = EAGAIN; 11134 mptsas_log(mpt, CE_WARN, "ioc reset abort passthru"); 11135 goto out; 11136 } 11137 11138 if (pkt->pkt_reason == CMD_INCOMPLETE) { 11139 status = EIO; 11140 mptsas_log(mpt, CE_WARN, "passthrough command incomplete"); 11141 goto out; 11142 } 11143 11144 mutex_exit(&mpt->m_mutex); 11145 if (cmd->cmd_flags & CFLAG_PREPARED) { 11146 function = request_hdrp->Function; 11147 if ((function == MPI2_FUNCTION_SCSI_IO_REQUEST) || 11148 (function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH)) { 11149 reply_len = sizeof (MPI2_SCSI_IO_REPLY); 11150 sense_len = cmd->cmd_extrqslen ? 11151 min(sense_len, cmd->cmd_extrqslen) : 11152 min(sense_len, cmd->cmd_rqslen); 11153 } else { 11154 reply_len = reply_size; 11155 sense_len = 0; 11156 } 11157 11158 for (i = 0; i < reply_len; i++) { 11159 if (ddi_copyout((uint8_t *)reply_msg + i, reply + i, 1, 11160 mode)) { 11161 mutex_enter(&mpt->m_mutex); 11162 status = EFAULT; 11163 mptsas_log(mpt, CE_WARN, "failed to copy out " 11164 "reply data"); 11165 goto out; 11166 } 11167 } 11168 for (i = 0; i < sense_len; i++) { 11169 if (ddi_copyout((uint8_t *)request_hdrp + 64 + i, 11170 reply + reply_len + i, 1, mode)) { 11171 mutex_enter(&mpt->m_mutex); 11172 status = EFAULT; 11173 mptsas_log(mpt, CE_WARN, "failed to copy out " 11174 "sense data"); 11175 goto out; 11176 } 11177 } 11178 } 11179 11180 if (data_size) { 11181 if (direction != MPTSAS_PASS_THRU_DIRECTION_WRITE) { 11182 (void) ddi_dma_sync(data_dma_state.handle, 0, 0, 11183 DDI_DMA_SYNC_FORCPU); 11184 for (i = 0; i < data_size; i++) { 11185 if (ddi_copyout((uint8_t *)( 11186 data_dma_state.memp + i), data + i, 1, 11187 mode)) { 11188 mutex_enter(&mpt->m_mutex); 11189 status = EFAULT; 11190 mptsas_log(mpt, CE_WARN, "failed to " 11191 "copy out the reply data"); 11192 goto out; 11193 } 11194 } 11195 } 11196 } 11197 mutex_enter(&mpt->m_mutex); 11198 out: 11199 /* 11200 * Put the reply frame back on the free queue, increment the free 11201 * index, and write the new index to the free index register. But only 11202 * if this reply is an ADDRESS reply. 11203 */ 11204 if (pt_flags & MPTSAS_ADDRESS_REPLY) { 11205 ddi_put32(mpt->m_acc_free_queue_hdl, 11206 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], 11207 cmd->cmd_rfm); 11208 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 11209 DDI_DMA_SYNC_FORDEV); 11210 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 11211 mpt->m_free_index = 0; 11212 } 11213 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 11214 mpt->m_free_index); 11215 } 11216 if (cmd) { 11217 if (cmd->cmd_extrqslen != 0) { 11218 rmfree(mpt->m_erqsense_map, cmd->cmd_extrqschunks, 11219 cmd->cmd_extrqsidx + 1); 11220 } 11221 if (cmd->cmd_flags & CFLAG_PREPARED) { 11222 mptsas_remove_cmd(mpt, cmd); 11223 pt_flags &= (~MPTSAS_REQUEST_POOL_CMD); 11224 } 11225 } 11226 if (pt_flags & MPTSAS_REQUEST_POOL_CMD) 11227 mptsas_return_to_pool(mpt, cmd); 11228 if (pt_flags & MPTSAS_DATA_ALLOCATED) { 11229 if (mptsas_check_dma_handle(data_dma_state.handle) != 11230 DDI_SUCCESS) { 11231 ddi_fm_service_impact(mpt->m_dip, 11232 DDI_SERVICE_UNAFFECTED); 11233 status = EFAULT; 11234 } 11235 mptsas_dma_free(&data_dma_state); 11236 } 11237 if (pt_flags & MPTSAS_DATAOUT_ALLOCATED) { 11238 if (mptsas_check_dma_handle(dataout_dma_state.handle) != 11239 DDI_SUCCESS) { 11240 ddi_fm_service_impact(mpt->m_dip, 11241 DDI_SERVICE_UNAFFECTED); 11242 status = EFAULT; 11243 } 11244 mptsas_dma_free(&dataout_dma_state); 11245 } 11246 if (pt_flags & MPTSAS_CMD_TIMEOUT) { 11247 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) { 11248 mptsas_log(mpt, CE_WARN, "mptsas_restart_ioc failed"); 11249 } 11250 } 11251 if (request_msg) 11252 kmem_free(request_msg, request_size); 11253 NDBG27(("mptsas_do_passthru: Done status 0x%x", status)); 11254 11255 return (status); 11256 } 11257 11258 static int 11259 mptsas_pass_thru(mptsas_t *mpt, mptsas_pass_thru_t *data, int mode) 11260 { 11261 /* 11262 * If timeout is 0, set timeout to default of 60 seconds. 11263 */ 11264 if (data->Timeout == 0) { 11265 data->Timeout = MPTSAS_PASS_THRU_TIME_DEFAULT; 11266 } 11267 11268 if (((data->DataSize == 0) && 11269 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_NONE)) || 11270 ((data->DataSize != 0) && 11271 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_READ) || 11272 (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_WRITE) || 11273 ((data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) && 11274 (data->DataOutSize != 0))))) { 11275 if (data->DataDirection == MPTSAS_PASS_THRU_DIRECTION_BOTH) { 11276 data->DataDirection = MPTSAS_PASS_THRU_DIRECTION_READ; 11277 } else { 11278 data->DataOutSize = 0; 11279 } 11280 /* 11281 * Send passthru request messages 11282 */ 11283 return (mptsas_do_passthru(mpt, 11284 (uint8_t *)((uintptr_t)data->PtrRequest), 11285 (uint8_t *)((uintptr_t)data->PtrReply), 11286 (uint8_t *)((uintptr_t)data->PtrData), 11287 data->RequestSize, data->ReplySize, 11288 data->DataSize, data->DataDirection, 11289 (uint8_t *)((uintptr_t)data->PtrDataOut), 11290 data->DataOutSize, data->Timeout, mode)); 11291 } else { 11292 return (EINVAL); 11293 } 11294 } 11295 11296 static uint8_t 11297 mptsas_get_fw_diag_buffer_number(mptsas_t *mpt, uint32_t unique_id) 11298 { 11299 uint8_t index; 11300 11301 for (index = 0; index < MPI2_DIAG_BUF_TYPE_COUNT; index++) { 11302 if (mpt->m_fw_diag_buffer_list[index].unique_id == unique_id) { 11303 return (index); 11304 } 11305 } 11306 11307 return (MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND); 11308 } 11309 11310 static void 11311 mptsas_start_diag(mptsas_t *mpt, mptsas_cmd_t *cmd) 11312 { 11313 pMpi2DiagBufferPostRequest_t pDiag_post_msg; 11314 pMpi2DiagReleaseRequest_t pDiag_release_msg; 11315 struct scsi_pkt *pkt = cmd->cmd_pkt; 11316 mptsas_diag_request_t *diag = pkt->pkt_ha_private; 11317 uint32_t i; 11318 uint64_t request_desc; 11319 11320 ASSERT(mutex_owned(&mpt->m_mutex)); 11321 11322 /* 11323 * Form the diag message depending on the post or release function. 11324 */ 11325 if (diag->function == MPI2_FUNCTION_DIAG_BUFFER_POST) { 11326 pDiag_post_msg = (pMpi2DiagBufferPostRequest_t) 11327 (mpt->m_req_frame + (mpt->m_req_frame_size * 11328 cmd->cmd_slot)); 11329 bzero(pDiag_post_msg, mpt->m_req_frame_size); 11330 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->Function, 11331 diag->function); 11332 ddi_put8(mpt->m_acc_req_frame_hdl, &pDiag_post_msg->BufferType, 11333 diag->pBuffer->buffer_type); 11334 ddi_put8(mpt->m_acc_req_frame_hdl, 11335 &pDiag_post_msg->ExtendedType, 11336 diag->pBuffer->extended_type); 11337 ddi_put32(mpt->m_acc_req_frame_hdl, 11338 &pDiag_post_msg->BufferLength, 11339 diag->pBuffer->buffer_data.size); 11340 for (i = 0; i < (sizeof (pDiag_post_msg->ProductSpecific) / 4); 11341 i++) { 11342 ddi_put32(mpt->m_acc_req_frame_hdl, 11343 &pDiag_post_msg->ProductSpecific[i], 11344 diag->pBuffer->product_specific[i]); 11345 } 11346 ddi_put32(mpt->m_acc_req_frame_hdl, 11347 &pDiag_post_msg->BufferAddress.Low, 11348 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress 11349 & 0xffffffffull)); 11350 ddi_put32(mpt->m_acc_req_frame_hdl, 11351 &pDiag_post_msg->BufferAddress.High, 11352 (uint32_t)(diag->pBuffer->buffer_data.cookie.dmac_laddress 11353 >> 32)); 11354 } else { 11355 pDiag_release_msg = (pMpi2DiagReleaseRequest_t) 11356 (mpt->m_req_frame + (mpt->m_req_frame_size * 11357 cmd->cmd_slot)); 11358 bzero(pDiag_release_msg, mpt->m_req_frame_size); 11359 ddi_put8(mpt->m_acc_req_frame_hdl, 11360 &pDiag_release_msg->Function, diag->function); 11361 ddi_put8(mpt->m_acc_req_frame_hdl, 11362 &pDiag_release_msg->BufferType, 11363 diag->pBuffer->buffer_type); 11364 } 11365 11366 /* 11367 * Send the message 11368 */ 11369 (void) ddi_dma_sync(mpt->m_dma_req_frame_hdl, 0, 0, 11370 DDI_DMA_SYNC_FORDEV); 11371 request_desc = (cmd->cmd_slot << 16) + 11372 MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 11373 cmd->cmd_rfm = NULL; 11374 MPTSAS_START_CMD(mpt, request_desc); 11375 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) != 11376 DDI_SUCCESS) || 11377 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) != 11378 DDI_SUCCESS)) { 11379 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 11380 } 11381 } 11382 11383 static int 11384 mptsas_post_fw_diag_buffer(mptsas_t *mpt, 11385 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code) 11386 { 11387 mptsas_diag_request_t diag; 11388 int status, slot_num, post_flags = 0; 11389 mptsas_cmd_t *cmd = NULL; 11390 struct scsi_pkt *pkt; 11391 pMpi2DiagBufferPostReply_t reply; 11392 uint16_t iocstatus; 11393 uint32_t iocloginfo, transfer_length; 11394 11395 /* 11396 * If buffer is not enabled, just leave. 11397 */ 11398 *return_code = MPTSAS_FW_DIAG_ERROR_POST_FAILED; 11399 if (!pBuffer->enabled) { 11400 status = DDI_FAILURE; 11401 goto out; 11402 } 11403 11404 /* 11405 * Clear some flags initially. 11406 */ 11407 pBuffer->force_release = FALSE; 11408 pBuffer->valid_data = FALSE; 11409 pBuffer->owned_by_firmware = FALSE; 11410 11411 /* 11412 * Get a cmd buffer from the cmd buffer pool 11413 */ 11414 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) { 11415 status = DDI_FAILURE; 11416 mptsas_log(mpt, CE_NOTE, "command pool is full: Post FW Diag"); 11417 goto out; 11418 } 11419 post_flags |= MPTSAS_REQUEST_POOL_CMD; 11420 11421 bzero((caddr_t)cmd, sizeof (*cmd)); 11422 bzero((caddr_t)pkt, scsi_pkt_size()); 11423 11424 cmd->ioc_cmd_slot = (uint32_t)(slot_num); 11425 11426 diag.pBuffer = pBuffer; 11427 diag.function = MPI2_FUNCTION_DIAG_BUFFER_POST; 11428 11429 /* 11430 * Form a blank cmd/pkt to store the acknowledgement message 11431 */ 11432 pkt->pkt_ha_private = (opaque_t)&diag; 11433 pkt->pkt_flags = FLAG_HEAD; 11434 pkt->pkt_time = 60; 11435 cmd->cmd_pkt = pkt; 11436 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG; 11437 11438 /* 11439 * Save the command in a slot 11440 */ 11441 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 11442 /* 11443 * Once passthru command get slot, set cmd_flags 11444 * CFLAG_PREPARED. 11445 */ 11446 cmd->cmd_flags |= CFLAG_PREPARED; 11447 mptsas_start_diag(mpt, cmd); 11448 } else { 11449 mptsas_waitq_add(mpt, cmd); 11450 } 11451 11452 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) { 11453 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex); 11454 } 11455 11456 if (cmd->cmd_flags & CFLAG_TIMEOUT) { 11457 status = DDI_FAILURE; 11458 mptsas_log(mpt, CE_WARN, "Post FW Diag command timeout"); 11459 goto out; 11460 } 11461 11462 /* 11463 * cmd_rfm points to the reply message if a reply was given. Check the 11464 * IOCStatus to make sure everything went OK with the FW diag request 11465 * and set buffer flags. 11466 */ 11467 if (cmd->cmd_rfm) { 11468 post_flags |= MPTSAS_ADDRESS_REPLY; 11469 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0, 11470 DDI_DMA_SYNC_FORCPU); 11471 reply = (pMpi2DiagBufferPostReply_t)(mpt->m_reply_frame + 11472 (cmd->cmd_rfm - 11473 (mpt->m_reply_frame_dma_addr & 0xffffffffu))); 11474 11475 /* 11476 * Get the reply message data 11477 */ 11478 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 11479 &reply->IOCStatus); 11480 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl, 11481 &reply->IOCLogInfo); 11482 transfer_length = ddi_get32(mpt->m_acc_reply_frame_hdl, 11483 &reply->TransferLength); 11484 11485 /* 11486 * If post failed quit. 11487 */ 11488 if (iocstatus != MPI2_IOCSTATUS_SUCCESS) { 11489 status = DDI_FAILURE; 11490 NDBG13(("post FW Diag Buffer failed: IOCStatus=0x%x, " 11491 "IOCLogInfo=0x%x, TransferLength=0x%x", iocstatus, 11492 iocloginfo, transfer_length)); 11493 goto out; 11494 } 11495 11496 /* 11497 * Post was successful. 11498 */ 11499 pBuffer->valid_data = TRUE; 11500 pBuffer->owned_by_firmware = TRUE; 11501 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS; 11502 status = DDI_SUCCESS; 11503 } 11504 11505 out: 11506 /* 11507 * Put the reply frame back on the free queue, increment the free 11508 * index, and write the new index to the free index register. But only 11509 * if this reply is an ADDRESS reply. 11510 */ 11511 if (post_flags & MPTSAS_ADDRESS_REPLY) { 11512 ddi_put32(mpt->m_acc_free_queue_hdl, 11513 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], 11514 cmd->cmd_rfm); 11515 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 11516 DDI_DMA_SYNC_FORDEV); 11517 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 11518 mpt->m_free_index = 0; 11519 } 11520 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 11521 mpt->m_free_index); 11522 } 11523 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) { 11524 mptsas_remove_cmd(mpt, cmd); 11525 post_flags &= (~MPTSAS_REQUEST_POOL_CMD); 11526 } 11527 if (post_flags & MPTSAS_REQUEST_POOL_CMD) { 11528 mptsas_return_to_pool(mpt, cmd); 11529 } 11530 11531 return (status); 11532 } 11533 11534 static int 11535 mptsas_release_fw_diag_buffer(mptsas_t *mpt, 11536 mptsas_fw_diagnostic_buffer_t *pBuffer, uint32_t *return_code, 11537 uint32_t diag_type) 11538 { 11539 mptsas_diag_request_t diag; 11540 int status, slot_num, rel_flags = 0; 11541 mptsas_cmd_t *cmd = NULL; 11542 struct scsi_pkt *pkt; 11543 pMpi2DiagReleaseReply_t reply; 11544 uint16_t iocstatus; 11545 uint32_t iocloginfo; 11546 11547 /* 11548 * If buffer is not enabled, just leave. 11549 */ 11550 *return_code = MPTSAS_FW_DIAG_ERROR_RELEASE_FAILED; 11551 if (!pBuffer->enabled) { 11552 mptsas_log(mpt, CE_NOTE, "This buffer type is not supported " 11553 "by the IOC"); 11554 status = DDI_FAILURE; 11555 goto out; 11556 } 11557 11558 /* 11559 * Clear some flags initially. 11560 */ 11561 pBuffer->force_release = FALSE; 11562 pBuffer->valid_data = FALSE; 11563 pBuffer->owned_by_firmware = FALSE; 11564 11565 /* 11566 * Get a cmd buffer from the cmd buffer pool 11567 */ 11568 if ((slot_num = (mptsas_request_from_pool(mpt, &cmd, &pkt))) == -1) { 11569 status = DDI_FAILURE; 11570 mptsas_log(mpt, CE_NOTE, "command pool is full: Release FW " 11571 "Diag"); 11572 goto out; 11573 } 11574 rel_flags |= MPTSAS_REQUEST_POOL_CMD; 11575 11576 bzero((caddr_t)cmd, sizeof (*cmd)); 11577 bzero((caddr_t)pkt, scsi_pkt_size()); 11578 11579 cmd->ioc_cmd_slot = (uint32_t)(slot_num); 11580 11581 diag.pBuffer = pBuffer; 11582 diag.function = MPI2_FUNCTION_DIAG_RELEASE; 11583 11584 /* 11585 * Form a blank cmd/pkt to store the acknowledgement message 11586 */ 11587 pkt->pkt_ha_private = (opaque_t)&diag; 11588 pkt->pkt_flags = FLAG_HEAD; 11589 pkt->pkt_time = 60; 11590 cmd->cmd_pkt = pkt; 11591 cmd->cmd_flags = CFLAG_CMDIOC | CFLAG_FW_DIAG; 11592 11593 /* 11594 * Save the command in a slot 11595 */ 11596 if (mptsas_save_cmd(mpt, cmd) == TRUE) { 11597 /* 11598 * Once passthru command get slot, set cmd_flags 11599 * CFLAG_PREPARED. 11600 */ 11601 cmd->cmd_flags |= CFLAG_PREPARED; 11602 mptsas_start_diag(mpt, cmd); 11603 } else { 11604 mptsas_waitq_add(mpt, cmd); 11605 } 11606 11607 while ((cmd->cmd_flags & CFLAG_FINISHED) == 0) { 11608 cv_wait(&mpt->m_fw_diag_cv, &mpt->m_mutex); 11609 } 11610 11611 if (cmd->cmd_flags & CFLAG_TIMEOUT) { 11612 status = DDI_FAILURE; 11613 mptsas_log(mpt, CE_WARN, "Release FW Diag command timeout"); 11614 goto out; 11615 } 11616 11617 /* 11618 * cmd_rfm points to the reply message if a reply was given. Check the 11619 * IOCStatus to make sure everything went OK with the FW diag request 11620 * and set buffer flags. 11621 */ 11622 if (cmd->cmd_rfm) { 11623 rel_flags |= MPTSAS_ADDRESS_REPLY; 11624 (void) ddi_dma_sync(mpt->m_dma_reply_frame_hdl, 0, 0, 11625 DDI_DMA_SYNC_FORCPU); 11626 reply = (pMpi2DiagReleaseReply_t)(mpt->m_reply_frame + 11627 (cmd->cmd_rfm - 11628 (mpt->m_reply_frame_dma_addr & 0xffffffffu))); 11629 11630 /* 11631 * Get the reply message data 11632 */ 11633 iocstatus = ddi_get16(mpt->m_acc_reply_frame_hdl, 11634 &reply->IOCStatus); 11635 iocloginfo = ddi_get32(mpt->m_acc_reply_frame_hdl, 11636 &reply->IOCLogInfo); 11637 11638 /* 11639 * If release failed quit. 11640 */ 11641 if ((iocstatus != MPI2_IOCSTATUS_SUCCESS) || 11642 pBuffer->owned_by_firmware) { 11643 status = DDI_FAILURE; 11644 NDBG13(("release FW Diag Buffer failed: " 11645 "IOCStatus=0x%x, IOCLogInfo=0x%x", iocstatus, 11646 iocloginfo)); 11647 goto out; 11648 } 11649 11650 /* 11651 * Release was successful. 11652 */ 11653 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS; 11654 status = DDI_SUCCESS; 11655 11656 /* 11657 * If this was for an UNREGISTER diag type command, clear the 11658 * unique ID. 11659 */ 11660 if (diag_type == MPTSAS_FW_DIAG_TYPE_UNREGISTER) { 11661 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID; 11662 } 11663 } 11664 11665 out: 11666 /* 11667 * Put the reply frame back on the free queue, increment the free 11668 * index, and write the new index to the free index register. But only 11669 * if this reply is an ADDRESS reply. 11670 */ 11671 if (rel_flags & MPTSAS_ADDRESS_REPLY) { 11672 ddi_put32(mpt->m_acc_free_queue_hdl, 11673 &((uint32_t *)(void *)mpt->m_free_queue)[mpt->m_free_index], 11674 cmd->cmd_rfm); 11675 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 11676 DDI_DMA_SYNC_FORDEV); 11677 if (++mpt->m_free_index == mpt->m_free_queue_depth) { 11678 mpt->m_free_index = 0; 11679 } 11680 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, 11681 mpt->m_free_index); 11682 } 11683 if (cmd && (cmd->cmd_flags & CFLAG_PREPARED)) { 11684 mptsas_remove_cmd(mpt, cmd); 11685 rel_flags &= (~MPTSAS_REQUEST_POOL_CMD); 11686 } 11687 if (rel_flags & MPTSAS_REQUEST_POOL_CMD) { 11688 mptsas_return_to_pool(mpt, cmd); 11689 } 11690 11691 return (status); 11692 } 11693 11694 static int 11695 mptsas_diag_register(mptsas_t *mpt, mptsas_fw_diag_register_t *diag_register, 11696 uint32_t *return_code) 11697 { 11698 mptsas_fw_diagnostic_buffer_t *pBuffer; 11699 uint8_t extended_type, buffer_type, i; 11700 uint32_t buffer_size; 11701 uint32_t unique_id; 11702 int status; 11703 11704 ASSERT(mutex_owned(&mpt->m_mutex)); 11705 11706 extended_type = diag_register->ExtendedType; 11707 buffer_type = diag_register->BufferType; 11708 buffer_size = diag_register->RequestedBufferSize; 11709 unique_id = diag_register->UniqueId; 11710 11711 /* 11712 * Check for valid buffer type 11713 */ 11714 if (buffer_type >= MPI2_DIAG_BUF_TYPE_COUNT) { 11715 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 11716 return (DDI_FAILURE); 11717 } 11718 11719 /* 11720 * Get the current buffer and look up the unique ID. The unique ID 11721 * should not be found. If it is, the ID is already in use. 11722 */ 11723 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 11724 pBuffer = &mpt->m_fw_diag_buffer_list[buffer_type]; 11725 if (i != MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 11726 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 11727 return (DDI_FAILURE); 11728 } 11729 11730 /* 11731 * The buffer's unique ID should not be registered yet, and the given 11732 * unique ID cannot be 0. 11733 */ 11734 if ((pBuffer->unique_id != MPTSAS_FW_DIAG_INVALID_UID) || 11735 (unique_id == MPTSAS_FW_DIAG_INVALID_UID)) { 11736 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 11737 return (DDI_FAILURE); 11738 } 11739 11740 /* 11741 * If this buffer is already posted as immediate, just change owner. 11742 */ 11743 if (pBuffer->immediate && pBuffer->owned_by_firmware && 11744 (pBuffer->unique_id == MPTSAS_FW_DIAG_INVALID_UID)) { 11745 pBuffer->immediate = FALSE; 11746 pBuffer->unique_id = unique_id; 11747 return (DDI_SUCCESS); 11748 } 11749 11750 /* 11751 * Post a new buffer after checking if it's enabled. The DMA buffer 11752 * that is allocated will be contiguous (sgl_len = 1). 11753 */ 11754 if (!pBuffer->enabled) { 11755 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER; 11756 return (DDI_FAILURE); 11757 } 11758 bzero(&pBuffer->buffer_data, sizeof (mptsas_dma_alloc_state_t)); 11759 pBuffer->buffer_data.size = buffer_size; 11760 if (mptsas_dma_alloc(mpt, &pBuffer->buffer_data) != DDI_SUCCESS) { 11761 mptsas_log(mpt, CE_WARN, "failed to alloc DMA resource for " 11762 "diag buffer: size = %d bytes", buffer_size); 11763 *return_code = MPTSAS_FW_DIAG_ERROR_NO_BUFFER; 11764 return (DDI_FAILURE); 11765 } 11766 11767 /* 11768 * Copy the given info to the diag buffer and post the buffer. 11769 */ 11770 pBuffer->buffer_type = buffer_type; 11771 pBuffer->immediate = FALSE; 11772 if (buffer_type == MPI2_DIAG_BUF_TYPE_TRACE) { 11773 for (i = 0; i < (sizeof (pBuffer->product_specific) / 4); 11774 i++) { 11775 pBuffer->product_specific[i] = 11776 diag_register->ProductSpecific[i]; 11777 } 11778 } 11779 pBuffer->extended_type = extended_type; 11780 pBuffer->unique_id = unique_id; 11781 status = mptsas_post_fw_diag_buffer(mpt, pBuffer, return_code); 11782 11783 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) != 11784 DDI_SUCCESS) { 11785 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed in " 11786 "mptsas_diag_register."); 11787 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 11788 status = DDI_FAILURE; 11789 } 11790 11791 /* 11792 * In case there was a failure, free the DMA buffer. 11793 */ 11794 if (status == DDI_FAILURE) { 11795 mptsas_dma_free(&pBuffer->buffer_data); 11796 } 11797 11798 return (status); 11799 } 11800 11801 static int 11802 mptsas_diag_unregister(mptsas_t *mpt, 11803 mptsas_fw_diag_unregister_t *diag_unregister, uint32_t *return_code) 11804 { 11805 mptsas_fw_diagnostic_buffer_t *pBuffer; 11806 uint8_t i; 11807 uint32_t unique_id; 11808 int status; 11809 11810 ASSERT(mutex_owned(&mpt->m_mutex)); 11811 11812 unique_id = diag_unregister->UniqueId; 11813 11814 /* 11815 * Get the current buffer and look up the unique ID. The unique ID 11816 * should be there. 11817 */ 11818 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 11819 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 11820 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 11821 return (DDI_FAILURE); 11822 } 11823 11824 pBuffer = &mpt->m_fw_diag_buffer_list[i]; 11825 11826 /* 11827 * Try to release the buffer from FW before freeing it. If release 11828 * fails, don't free the DMA buffer in case FW tries to access it 11829 * later. If buffer is not owned by firmware, can't release it. 11830 */ 11831 if (!pBuffer->owned_by_firmware) { 11832 status = DDI_SUCCESS; 11833 } else { 11834 status = mptsas_release_fw_diag_buffer(mpt, pBuffer, 11835 return_code, MPTSAS_FW_DIAG_TYPE_UNREGISTER); 11836 } 11837 11838 /* 11839 * At this point, return the current status no matter what happens with 11840 * the DMA buffer. 11841 */ 11842 pBuffer->unique_id = MPTSAS_FW_DIAG_INVALID_UID; 11843 if (status == DDI_SUCCESS) { 11844 if (mptsas_check_dma_handle(pBuffer->buffer_data.handle) != 11845 DDI_SUCCESS) { 11846 mptsas_log(mpt, CE_WARN, "Check of DMA handle failed " 11847 "in mptsas_diag_unregister."); 11848 ddi_fm_service_impact(mpt->m_dip, 11849 DDI_SERVICE_UNAFFECTED); 11850 } 11851 mptsas_dma_free(&pBuffer->buffer_data); 11852 } 11853 11854 return (status); 11855 } 11856 11857 static int 11858 mptsas_diag_query(mptsas_t *mpt, mptsas_fw_diag_query_t *diag_query, 11859 uint32_t *return_code) 11860 { 11861 mptsas_fw_diagnostic_buffer_t *pBuffer; 11862 uint8_t i; 11863 uint32_t unique_id; 11864 11865 ASSERT(mutex_owned(&mpt->m_mutex)); 11866 11867 unique_id = diag_query->UniqueId; 11868 11869 /* 11870 * If ID is valid, query on ID. 11871 * If ID is invalid, query on buffer type. 11872 */ 11873 if (unique_id == MPTSAS_FW_DIAG_INVALID_UID) { 11874 i = diag_query->BufferType; 11875 if (i >= MPI2_DIAG_BUF_TYPE_COUNT) { 11876 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 11877 return (DDI_FAILURE); 11878 } 11879 } else { 11880 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 11881 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 11882 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 11883 return (DDI_FAILURE); 11884 } 11885 } 11886 11887 /* 11888 * Fill query structure with the diag buffer info. 11889 */ 11890 pBuffer = &mpt->m_fw_diag_buffer_list[i]; 11891 diag_query->BufferType = pBuffer->buffer_type; 11892 diag_query->ExtendedType = pBuffer->extended_type; 11893 if (diag_query->BufferType == MPI2_DIAG_BUF_TYPE_TRACE) { 11894 for (i = 0; i < (sizeof (diag_query->ProductSpecific) / 4); 11895 i++) { 11896 diag_query->ProductSpecific[i] = 11897 pBuffer->product_specific[i]; 11898 } 11899 } 11900 diag_query->TotalBufferSize = pBuffer->buffer_data.size; 11901 diag_query->DriverAddedBufferSize = 0; 11902 diag_query->UniqueId = pBuffer->unique_id; 11903 diag_query->ApplicationFlags = 0; 11904 diag_query->DiagnosticFlags = 0; 11905 11906 /* 11907 * Set/Clear application flags 11908 */ 11909 if (pBuffer->immediate) { 11910 diag_query->ApplicationFlags &= ~MPTSAS_FW_DIAG_FLAG_APP_OWNED; 11911 } else { 11912 diag_query->ApplicationFlags |= MPTSAS_FW_DIAG_FLAG_APP_OWNED; 11913 } 11914 if (pBuffer->valid_data || pBuffer->owned_by_firmware) { 11915 diag_query->ApplicationFlags |= 11916 MPTSAS_FW_DIAG_FLAG_BUFFER_VALID; 11917 } else { 11918 diag_query->ApplicationFlags &= 11919 ~MPTSAS_FW_DIAG_FLAG_BUFFER_VALID; 11920 } 11921 if (pBuffer->owned_by_firmware) { 11922 diag_query->ApplicationFlags |= 11923 MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS; 11924 } else { 11925 diag_query->ApplicationFlags &= 11926 ~MPTSAS_FW_DIAG_FLAG_FW_BUFFER_ACCESS; 11927 } 11928 11929 return (DDI_SUCCESS); 11930 } 11931 11932 static int 11933 mptsas_diag_read_buffer(mptsas_t *mpt, 11934 mptsas_diag_read_buffer_t *diag_read_buffer, uint8_t *ioctl_buf, 11935 uint32_t *return_code, int ioctl_mode) 11936 { 11937 mptsas_fw_diagnostic_buffer_t *pBuffer; 11938 uint8_t i, *pData; 11939 uint32_t unique_id, byte; 11940 int status; 11941 11942 ASSERT(mutex_owned(&mpt->m_mutex)); 11943 11944 unique_id = diag_read_buffer->UniqueId; 11945 11946 /* 11947 * Get the current buffer and look up the unique ID. The unique ID 11948 * should be there. 11949 */ 11950 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 11951 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 11952 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 11953 return (DDI_FAILURE); 11954 } 11955 11956 pBuffer = &mpt->m_fw_diag_buffer_list[i]; 11957 11958 /* 11959 * Make sure requested read is within limits 11960 */ 11961 if (diag_read_buffer->StartingOffset + diag_read_buffer->BytesToRead > 11962 pBuffer->buffer_data.size) { 11963 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 11964 return (DDI_FAILURE); 11965 } 11966 11967 /* 11968 * Copy the requested data from DMA to the diag_read_buffer. The DMA 11969 * buffer that was allocated is one contiguous buffer. 11970 */ 11971 pData = (uint8_t *)(pBuffer->buffer_data.memp + 11972 diag_read_buffer->StartingOffset); 11973 (void) ddi_dma_sync(pBuffer->buffer_data.handle, 0, 0, 11974 DDI_DMA_SYNC_FORCPU); 11975 for (byte = 0; byte < diag_read_buffer->BytesToRead; byte++) { 11976 if (ddi_copyout(pData + byte, ioctl_buf + byte, 1, ioctl_mode) 11977 != 0) { 11978 return (DDI_FAILURE); 11979 } 11980 } 11981 diag_read_buffer->Status = 0; 11982 11983 /* 11984 * Set or clear the Force Release flag. 11985 */ 11986 if (pBuffer->force_release) { 11987 diag_read_buffer->Flags |= MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE; 11988 } else { 11989 diag_read_buffer->Flags &= ~MPTSAS_FW_DIAG_FLAG_FORCE_RELEASE; 11990 } 11991 11992 /* 11993 * If buffer is to be reregistered, make sure it's not already owned by 11994 * firmware first. 11995 */ 11996 status = DDI_SUCCESS; 11997 if (!pBuffer->owned_by_firmware) { 11998 if (diag_read_buffer->Flags & MPTSAS_FW_DIAG_FLAG_REREGISTER) { 11999 status = mptsas_post_fw_diag_buffer(mpt, pBuffer, 12000 return_code); 12001 } 12002 } 12003 12004 return (status); 12005 } 12006 12007 static int 12008 mptsas_diag_release(mptsas_t *mpt, mptsas_fw_diag_release_t *diag_release, 12009 uint32_t *return_code) 12010 { 12011 mptsas_fw_diagnostic_buffer_t *pBuffer; 12012 uint8_t i; 12013 uint32_t unique_id; 12014 int status; 12015 12016 ASSERT(mutex_owned(&mpt->m_mutex)); 12017 12018 unique_id = diag_release->UniqueId; 12019 12020 /* 12021 * Get the current buffer and look up the unique ID. The unique ID 12022 * should be there. 12023 */ 12024 i = mptsas_get_fw_diag_buffer_number(mpt, unique_id); 12025 if (i == MPTSAS_FW_DIAGNOSTIC_UID_NOT_FOUND) { 12026 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_UID; 12027 return (DDI_FAILURE); 12028 } 12029 12030 pBuffer = &mpt->m_fw_diag_buffer_list[i]; 12031 12032 /* 12033 * If buffer is not owned by firmware, it's already been released. 12034 */ 12035 if (!pBuffer->owned_by_firmware) { 12036 *return_code = MPTSAS_FW_DIAG_ERROR_ALREADY_RELEASED; 12037 return (DDI_FAILURE); 12038 } 12039 12040 /* 12041 * Release the buffer. 12042 */ 12043 status = mptsas_release_fw_diag_buffer(mpt, pBuffer, return_code, 12044 MPTSAS_FW_DIAG_TYPE_RELEASE); 12045 return (status); 12046 } 12047 12048 static int 12049 mptsas_do_diag_action(mptsas_t *mpt, uint32_t action, uint8_t *diag_action, 12050 uint32_t length, uint32_t *return_code, int ioctl_mode) 12051 { 12052 mptsas_fw_diag_register_t diag_register; 12053 mptsas_fw_diag_unregister_t diag_unregister; 12054 mptsas_fw_diag_query_t diag_query; 12055 mptsas_diag_read_buffer_t diag_read_buffer; 12056 mptsas_fw_diag_release_t diag_release; 12057 int status = DDI_SUCCESS; 12058 uint32_t original_return_code, read_buf_len; 12059 12060 ASSERT(mutex_owned(&mpt->m_mutex)); 12061 12062 original_return_code = *return_code; 12063 *return_code = MPTSAS_FW_DIAG_ERROR_SUCCESS; 12064 12065 switch (action) { 12066 case MPTSAS_FW_DIAG_TYPE_REGISTER: 12067 if (!length) { 12068 *return_code = 12069 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 12070 status = DDI_FAILURE; 12071 break; 12072 } 12073 if (ddi_copyin(diag_action, &diag_register, 12074 sizeof (diag_register), ioctl_mode) != 0) { 12075 return (DDI_FAILURE); 12076 } 12077 status = mptsas_diag_register(mpt, &diag_register, 12078 return_code); 12079 break; 12080 12081 case MPTSAS_FW_DIAG_TYPE_UNREGISTER: 12082 if (length < sizeof (diag_unregister)) { 12083 *return_code = 12084 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 12085 status = DDI_FAILURE; 12086 break; 12087 } 12088 if (ddi_copyin(diag_action, &diag_unregister, 12089 sizeof (diag_unregister), ioctl_mode) != 0) { 12090 return (DDI_FAILURE); 12091 } 12092 status = mptsas_diag_unregister(mpt, &diag_unregister, 12093 return_code); 12094 break; 12095 12096 case MPTSAS_FW_DIAG_TYPE_QUERY: 12097 if (length < sizeof (diag_query)) { 12098 *return_code = 12099 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 12100 status = DDI_FAILURE; 12101 break; 12102 } 12103 if (ddi_copyin(diag_action, &diag_query, 12104 sizeof (diag_query), ioctl_mode) != 0) { 12105 return (DDI_FAILURE); 12106 } 12107 status = mptsas_diag_query(mpt, &diag_query, 12108 return_code); 12109 if (status == DDI_SUCCESS) { 12110 if (ddi_copyout(&diag_query, diag_action, 12111 sizeof (diag_query), ioctl_mode) != 0) { 12112 return (DDI_FAILURE); 12113 } 12114 } 12115 break; 12116 12117 case MPTSAS_FW_DIAG_TYPE_READ_BUFFER: 12118 if (ddi_copyin(diag_action, &diag_read_buffer, 12119 sizeof (diag_read_buffer) - 4, ioctl_mode) != 0) { 12120 return (DDI_FAILURE); 12121 } 12122 read_buf_len = sizeof (diag_read_buffer) - 12123 sizeof (diag_read_buffer.DataBuffer) + 12124 diag_read_buffer.BytesToRead; 12125 if (length < read_buf_len) { 12126 *return_code = 12127 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 12128 status = DDI_FAILURE; 12129 break; 12130 } 12131 status = mptsas_diag_read_buffer(mpt, 12132 &diag_read_buffer, diag_action + 12133 sizeof (diag_read_buffer) - 4, return_code, 12134 ioctl_mode); 12135 if (status == DDI_SUCCESS) { 12136 if (ddi_copyout(&diag_read_buffer, diag_action, 12137 sizeof (diag_read_buffer) - 4, ioctl_mode) 12138 != 0) { 12139 return (DDI_FAILURE); 12140 } 12141 } 12142 break; 12143 12144 case MPTSAS_FW_DIAG_TYPE_RELEASE: 12145 if (length < sizeof (diag_release)) { 12146 *return_code = 12147 MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 12148 status = DDI_FAILURE; 12149 break; 12150 } 12151 if (ddi_copyin(diag_action, &diag_release, 12152 sizeof (diag_release), ioctl_mode) != 0) { 12153 return (DDI_FAILURE); 12154 } 12155 status = mptsas_diag_release(mpt, &diag_release, 12156 return_code); 12157 break; 12158 12159 default: 12160 *return_code = MPTSAS_FW_DIAG_ERROR_INVALID_PARAMETER; 12161 status = DDI_FAILURE; 12162 break; 12163 } 12164 12165 if ((status == DDI_FAILURE) && 12166 (original_return_code == MPTSAS_FW_DIAG_NEW) && 12167 (*return_code != MPTSAS_FW_DIAG_ERROR_SUCCESS)) { 12168 status = DDI_SUCCESS; 12169 } 12170 12171 return (status); 12172 } 12173 12174 static int 12175 mptsas_diag_action(mptsas_t *mpt, mptsas_diag_action_t *user_data, int mode) 12176 { 12177 int status; 12178 mptsas_diag_action_t driver_data; 12179 12180 ASSERT(mutex_owned(&mpt->m_mutex)); 12181 12182 /* 12183 * Copy the user data to a driver data buffer. 12184 */ 12185 if (ddi_copyin(user_data, &driver_data, sizeof (mptsas_diag_action_t), 12186 mode) == 0) { 12187 /* 12188 * Send diag action request if Action is valid 12189 */ 12190 if (driver_data.Action == MPTSAS_FW_DIAG_TYPE_REGISTER || 12191 driver_data.Action == MPTSAS_FW_DIAG_TYPE_UNREGISTER || 12192 driver_data.Action == MPTSAS_FW_DIAG_TYPE_QUERY || 12193 driver_data.Action == MPTSAS_FW_DIAG_TYPE_READ_BUFFER || 12194 driver_data.Action == MPTSAS_FW_DIAG_TYPE_RELEASE) { 12195 status = mptsas_do_diag_action(mpt, driver_data.Action, 12196 (void *)(uintptr_t)driver_data.PtrDiagAction, 12197 driver_data.Length, &driver_data.ReturnCode, 12198 mode); 12199 if (status == DDI_SUCCESS) { 12200 if (ddi_copyout(&driver_data.ReturnCode, 12201 &user_data->ReturnCode, 12202 sizeof (user_data->ReturnCode), mode) 12203 != 0) { 12204 status = EFAULT; 12205 } else { 12206 status = 0; 12207 } 12208 } else { 12209 status = EIO; 12210 } 12211 } else { 12212 status = EINVAL; 12213 } 12214 } else { 12215 status = EFAULT; 12216 } 12217 12218 return (status); 12219 } 12220 12221 /* 12222 * This routine handles the "event query" ioctl. 12223 */ 12224 static int 12225 mptsas_event_query(mptsas_t *mpt, mptsas_event_query_t *data, int mode, 12226 int *rval) 12227 { 12228 int status; 12229 mptsas_event_query_t driverdata; 12230 uint8_t i; 12231 12232 driverdata.Entries = MPTSAS_EVENT_QUEUE_SIZE; 12233 12234 mutex_enter(&mpt->m_mutex); 12235 for (i = 0; i < 4; i++) { 12236 driverdata.Types[i] = mpt->m_event_mask[i]; 12237 } 12238 mutex_exit(&mpt->m_mutex); 12239 12240 if (ddi_copyout(&driverdata, data, sizeof (driverdata), mode) != 0) { 12241 status = EFAULT; 12242 } else { 12243 *rval = MPTIOCTL_STATUS_GOOD; 12244 status = 0; 12245 } 12246 12247 return (status); 12248 } 12249 12250 /* 12251 * This routine handles the "event enable" ioctl. 12252 */ 12253 static int 12254 mptsas_event_enable(mptsas_t *mpt, mptsas_event_enable_t *data, int mode, 12255 int *rval) 12256 { 12257 int status; 12258 mptsas_event_enable_t driverdata; 12259 uint8_t i; 12260 12261 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) { 12262 mutex_enter(&mpt->m_mutex); 12263 for (i = 0; i < 4; i++) { 12264 mpt->m_event_mask[i] = driverdata.Types[i]; 12265 } 12266 mutex_exit(&mpt->m_mutex); 12267 12268 *rval = MPTIOCTL_STATUS_GOOD; 12269 status = 0; 12270 } else { 12271 status = EFAULT; 12272 } 12273 return (status); 12274 } 12275 12276 /* 12277 * This routine handles the "event report" ioctl. 12278 */ 12279 static int 12280 mptsas_event_report(mptsas_t *mpt, mptsas_event_report_t *data, int mode, 12281 int *rval) 12282 { 12283 int status; 12284 mptsas_event_report_t driverdata; 12285 12286 mutex_enter(&mpt->m_mutex); 12287 12288 if (ddi_copyin(&data->Size, &driverdata.Size, sizeof (driverdata.Size), 12289 mode) == 0) { 12290 if (driverdata.Size >= sizeof (mpt->m_events)) { 12291 if (ddi_copyout(mpt->m_events, data->Events, 12292 sizeof (mpt->m_events), mode) != 0) { 12293 status = EFAULT; 12294 } else { 12295 if (driverdata.Size > sizeof (mpt->m_events)) { 12296 driverdata.Size = 12297 sizeof (mpt->m_events); 12298 if (ddi_copyout(&driverdata.Size, 12299 &data->Size, 12300 sizeof (driverdata.Size), 12301 mode) != 0) { 12302 status = EFAULT; 12303 } else { 12304 *rval = MPTIOCTL_STATUS_GOOD; 12305 status = 0; 12306 } 12307 } else { 12308 *rval = MPTIOCTL_STATUS_GOOD; 12309 status = 0; 12310 } 12311 } 12312 } else { 12313 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT; 12314 status = 0; 12315 } 12316 } else { 12317 status = EFAULT; 12318 } 12319 12320 mutex_exit(&mpt->m_mutex); 12321 return (status); 12322 } 12323 12324 static void 12325 mptsas_lookup_pci_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data) 12326 { 12327 int *reg_data; 12328 uint_t reglen; 12329 12330 /* 12331 * Lookup the 'reg' property and extract the other data 12332 */ 12333 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip, 12334 DDI_PROP_DONTPASS, "reg", ®_data, ®len) == 12335 DDI_PROP_SUCCESS) { 12336 /* 12337 * Extract the PCI data from the 'reg' property first DWORD. 12338 * The entry looks like the following: 12339 * First DWORD: 12340 * Bits 0 - 7 8-bit Register number 12341 * Bits 8 - 10 3-bit Function number 12342 * Bits 11 - 15 5-bit Device number 12343 * Bits 16 - 23 8-bit Bus number 12344 * Bits 24 - 25 2-bit Address Space type identifier 12345 * 12346 */ 12347 adapter_data->PciInformation.u.bits.BusNumber = 12348 (reg_data[0] & 0x00FF0000) >> 16; 12349 adapter_data->PciInformation.u.bits.DeviceNumber = 12350 (reg_data[0] & 0x0000F800) >> 11; 12351 adapter_data->PciInformation.u.bits.FunctionNumber = 12352 (reg_data[0] & 0x00000700) >> 8; 12353 ddi_prop_free((void *)reg_data); 12354 } else { 12355 /* 12356 * If we can't determine the PCI data then we fill in FF's for 12357 * the data to indicate this. 12358 */ 12359 adapter_data->PCIDeviceHwId = 0xFFFFFFFF; 12360 adapter_data->MpiPortNumber = 0xFFFFFFFF; 12361 adapter_data->PciInformation.u.AsDWORD = 0xFFFFFFFF; 12362 } 12363 12364 /* 12365 * Saved in the mpt->m_fwversion 12366 */ 12367 adapter_data->MpiFirmwareVersion = mpt->m_fwversion; 12368 } 12369 12370 static void 12371 mptsas_read_adapter_data(mptsas_t *mpt, mptsas_adapter_data_t *adapter_data) 12372 { 12373 char *driver_verstr = MPTSAS_MOD_STRING; 12374 12375 mptsas_lookup_pci_data(mpt, adapter_data); 12376 adapter_data->AdapterType = mpt->m_MPI25 ? 12377 MPTIOCTL_ADAPTER_TYPE_SAS3 : 12378 MPTIOCTL_ADAPTER_TYPE_SAS2; 12379 adapter_data->PCIDeviceHwId = (uint32_t)mpt->m_devid; 12380 adapter_data->PCIDeviceHwRev = (uint32_t)mpt->m_revid; 12381 adapter_data->SubSystemId = (uint32_t)mpt->m_ssid; 12382 adapter_data->SubsystemVendorId = (uint32_t)mpt->m_svid; 12383 (void) strcpy((char *)&adapter_data->DriverVersion[0], driver_verstr); 12384 adapter_data->BiosVersion = 0; 12385 (void) mptsas_get_bios_page3(mpt, &adapter_data->BiosVersion); 12386 } 12387 12388 static void 12389 mptsas_read_pci_info(mptsas_t *mpt, mptsas_pci_info_t *pci_info) 12390 { 12391 int *reg_data, i; 12392 uint_t reglen; 12393 12394 /* 12395 * Lookup the 'reg' property and extract the other data 12396 */ 12397 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, mpt->m_dip, 12398 DDI_PROP_DONTPASS, "reg", ®_data, ®len) == 12399 DDI_PROP_SUCCESS) { 12400 /* 12401 * Extract the PCI data from the 'reg' property first DWORD. 12402 * The entry looks like the following: 12403 * First DWORD: 12404 * Bits 8 - 10 3-bit Function number 12405 * Bits 11 - 15 5-bit Device number 12406 * Bits 16 - 23 8-bit Bus number 12407 */ 12408 pci_info->BusNumber = (reg_data[0] & 0x00FF0000) >> 16; 12409 pci_info->DeviceNumber = (reg_data[0] & 0x0000F800) >> 11; 12410 pci_info->FunctionNumber = (reg_data[0] & 0x00000700) >> 8; 12411 ddi_prop_free((void *)reg_data); 12412 } else { 12413 /* 12414 * If we can't determine the PCI info then we fill in FF's for 12415 * the data to indicate this. 12416 */ 12417 pci_info->BusNumber = 0xFFFFFFFF; 12418 pci_info->DeviceNumber = 0xFF; 12419 pci_info->FunctionNumber = 0xFF; 12420 } 12421 12422 /* 12423 * Now get the interrupt vector and the pci header. The vector can 12424 * only be 0 right now. The header is the first 256 bytes of config 12425 * space. 12426 */ 12427 pci_info->InterruptVector = 0; 12428 for (i = 0; i < sizeof (pci_info->PciHeader); i++) { 12429 pci_info->PciHeader[i] = pci_config_get8(mpt->m_config_handle, 12430 i); 12431 } 12432 } 12433 12434 static int 12435 mptsas_reg_access(mptsas_t *mpt, mptsas_reg_access_t *data, int mode) 12436 { 12437 int status = 0; 12438 mptsas_reg_access_t driverdata; 12439 12440 mutex_enter(&mpt->m_mutex); 12441 if (ddi_copyin(data, &driverdata, sizeof (driverdata), mode) == 0) { 12442 switch (driverdata.Command) { 12443 /* 12444 * IO access is not supported. 12445 */ 12446 case REG_IO_READ: 12447 case REG_IO_WRITE: 12448 mptsas_log(mpt, CE_WARN, "IO access is not " 12449 "supported. Use memory access."); 12450 status = EINVAL; 12451 break; 12452 12453 case REG_MEM_READ: 12454 driverdata.RegData = ddi_get32(mpt->m_datap, 12455 (uint32_t *)(void *)mpt->m_reg + 12456 driverdata.RegOffset); 12457 if (ddi_copyout(&driverdata.RegData, 12458 &data->RegData, 12459 sizeof (driverdata.RegData), mode) != 0) { 12460 mptsas_log(mpt, CE_WARN, "Register " 12461 "Read Failed"); 12462 status = EFAULT; 12463 } 12464 break; 12465 12466 case REG_MEM_WRITE: 12467 ddi_put32(mpt->m_datap, 12468 (uint32_t *)(void *)mpt->m_reg + 12469 driverdata.RegOffset, 12470 driverdata.RegData); 12471 break; 12472 12473 default: 12474 status = EINVAL; 12475 break; 12476 } 12477 } else { 12478 status = EFAULT; 12479 } 12480 12481 mutex_exit(&mpt->m_mutex); 12482 return (status); 12483 } 12484 12485 static int 12486 led_control(mptsas_t *mpt, intptr_t data, int mode) 12487 { 12488 int ret = 0; 12489 mptsas_led_control_t lc; 12490 mptsas_target_t *ptgt; 12491 12492 if (ddi_copyin((void *)data, &lc, sizeof (lc), mode) != 0) { 12493 return (EFAULT); 12494 } 12495 12496 if ((lc.Command != MPTSAS_LEDCTL_FLAG_SET && 12497 lc.Command != MPTSAS_LEDCTL_FLAG_GET) || 12498 lc.Led < MPTSAS_LEDCTL_LED_MIN || 12499 lc.Led > MPTSAS_LEDCTL_LED_MAX || 12500 (lc.Command == MPTSAS_LEDCTL_FLAG_SET && lc.LedStatus != 0 && 12501 lc.LedStatus != 1)) { 12502 return (EINVAL); 12503 } 12504 12505 if ((lc.Command == MPTSAS_LEDCTL_FLAG_SET && (mode & FWRITE) == 0) || 12506 (lc.Command == MPTSAS_LEDCTL_FLAG_GET && (mode & FREAD) == 0)) 12507 return (EACCES); 12508 12509 /* Locate the target we're interrogating... */ 12510 mutex_enter(&mpt->m_mutex); 12511 ptgt = refhash_linear_search(mpt->m_targets, 12512 mptsas_target_eval_slot, &lc); 12513 if (ptgt == NULL) { 12514 /* We could not find a target for that enclosure/slot. */ 12515 mutex_exit(&mpt->m_mutex); 12516 return (ENOENT); 12517 } 12518 12519 if (lc.Command == MPTSAS_LEDCTL_FLAG_SET) { 12520 /* Update our internal LED state. */ 12521 ptgt->m_led_status &= ~(1 << (lc.Led - 1)); 12522 ptgt->m_led_status |= lc.LedStatus << (lc.Led - 1); 12523 12524 /* Flush it to the controller. */ 12525 ret = mptsas_flush_led_status(mpt, ptgt); 12526 mutex_exit(&mpt->m_mutex); 12527 return (ret); 12528 } 12529 12530 /* Return our internal LED state. */ 12531 lc.LedStatus = (ptgt->m_led_status >> (lc.Led - 1)) & 1; 12532 mutex_exit(&mpt->m_mutex); 12533 12534 if (ddi_copyout(&lc, (void *)data, sizeof (lc), mode) != 0) { 12535 return (EFAULT); 12536 } 12537 12538 return (0); 12539 } 12540 12541 static int 12542 get_disk_info(mptsas_t *mpt, intptr_t data, int mode) 12543 { 12544 uint16_t i = 0; 12545 uint16_t count = 0; 12546 int ret = 0; 12547 mptsas_target_t *ptgt; 12548 mptsas_disk_info_t *di; 12549 STRUCT_DECL(mptsas_get_disk_info, gdi); 12550 12551 if ((mode & FREAD) == 0) 12552 return (EACCES); 12553 12554 STRUCT_INIT(gdi, get_udatamodel()); 12555 12556 if (ddi_copyin((void *)data, STRUCT_BUF(gdi), STRUCT_SIZE(gdi), 12557 mode) != 0) { 12558 return (EFAULT); 12559 } 12560 12561 /* Find out how many targets there are. */ 12562 mutex_enter(&mpt->m_mutex); 12563 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 12564 ptgt = refhash_next(mpt->m_targets, ptgt)) { 12565 count++; 12566 } 12567 mutex_exit(&mpt->m_mutex); 12568 12569 /* 12570 * If we haven't been asked to copy out information on each target, 12571 * then just return the count. 12572 */ 12573 STRUCT_FSET(gdi, DiskCount, count); 12574 if (STRUCT_FGETP(gdi, PtrDiskInfoArray) == NULL) 12575 goto copy_out; 12576 12577 /* 12578 * If we haven't been given a large enough buffer to copy out into, 12579 * let the caller know. 12580 */ 12581 if (STRUCT_FGET(gdi, DiskInfoArraySize) < 12582 count * sizeof (mptsas_disk_info_t)) { 12583 ret = ENOSPC; 12584 goto copy_out; 12585 } 12586 12587 di = kmem_zalloc(count * sizeof (mptsas_disk_info_t), KM_SLEEP); 12588 12589 mutex_enter(&mpt->m_mutex); 12590 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 12591 ptgt = refhash_next(mpt->m_targets, ptgt)) { 12592 if (i >= count) { 12593 /* 12594 * The number of targets changed while we weren't 12595 * looking, so give up. 12596 */ 12597 refhash_rele(mpt->m_targets, ptgt); 12598 mutex_exit(&mpt->m_mutex); 12599 kmem_free(di, count * sizeof (mptsas_disk_info_t)); 12600 return (EAGAIN); 12601 } 12602 di[i].Instance = mpt->m_instance; 12603 di[i].Enclosure = ptgt->m_enclosure; 12604 di[i].Slot = ptgt->m_slot_num; 12605 di[i].SasAddress = ptgt->m_addr.mta_wwn; 12606 i++; 12607 } 12608 mutex_exit(&mpt->m_mutex); 12609 STRUCT_FSET(gdi, DiskCount, i); 12610 12611 /* Copy out the disk information to the caller. */ 12612 if (ddi_copyout((void *)di, STRUCT_FGETP(gdi, PtrDiskInfoArray), 12613 i * sizeof (mptsas_disk_info_t), mode) != 0) { 12614 ret = EFAULT; 12615 } 12616 12617 kmem_free(di, count * sizeof (mptsas_disk_info_t)); 12618 12619 copy_out: 12620 if (ddi_copyout(STRUCT_BUF(gdi), (void *)data, STRUCT_SIZE(gdi), 12621 mode) != 0) { 12622 ret = EFAULT; 12623 } 12624 12625 return (ret); 12626 } 12627 12628 static int 12629 mptsas_ioctl(dev_t dev, int cmd, intptr_t data, int mode, cred_t *credp, 12630 int *rval) 12631 { 12632 int status = 0; 12633 mptsas_t *mpt; 12634 mptsas_update_flash_t flashdata; 12635 mptsas_pass_thru_t passthru_data; 12636 mptsas_adapter_data_t adapter_data; 12637 mptsas_pci_info_t pci_info; 12638 int copylen; 12639 12640 int iport_flag = 0; 12641 dev_info_t *dip = NULL; 12642 mptsas_phymask_t phymask = 0; 12643 struct devctl_iocdata *dcp = NULL; 12644 char *addr = NULL; 12645 mptsas_target_t *ptgt = NULL; 12646 12647 *rval = MPTIOCTL_STATUS_GOOD; 12648 if (secpolicy_sys_config(credp, B_FALSE) != 0) { 12649 return (EPERM); 12650 } 12651 12652 mpt = ddi_get_soft_state(mptsas_state, MINOR2INST(getminor(dev))); 12653 if (mpt == NULL) { 12654 /* 12655 * Called from iport node, get the states 12656 */ 12657 iport_flag = 1; 12658 dip = mptsas_get_dip_from_dev(dev, &phymask); 12659 if (dip == NULL) { 12660 return (ENXIO); 12661 } 12662 mpt = DIP2MPT(dip); 12663 } 12664 /* Make sure power level is D0 before accessing registers */ 12665 mutex_enter(&mpt->m_mutex); 12666 if (mpt->m_options & MPTSAS_OPT_PM) { 12667 (void) pm_busy_component(mpt->m_dip, 0); 12668 if (mpt->m_power_level != PM_LEVEL_D0) { 12669 mutex_exit(&mpt->m_mutex); 12670 if (pm_raise_power(mpt->m_dip, 0, PM_LEVEL_D0) != 12671 DDI_SUCCESS) { 12672 mptsas_log(mpt, CE_WARN, 12673 "mptsas%d: mptsas_ioctl: Raise power " 12674 "request failed.", mpt->m_instance); 12675 (void) pm_idle_component(mpt->m_dip, 0); 12676 return (ENXIO); 12677 } 12678 } else { 12679 mutex_exit(&mpt->m_mutex); 12680 } 12681 } else { 12682 mutex_exit(&mpt->m_mutex); 12683 } 12684 12685 if (iport_flag) { 12686 status = scsi_hba_ioctl(dev, cmd, data, mode, credp, rval); 12687 if (status != 0) { 12688 goto out; 12689 } 12690 /* 12691 * The following code control the OK2RM LED, it doesn't affect 12692 * the ioctl return status. 12693 */ 12694 if ((cmd == DEVCTL_DEVICE_ONLINE) || 12695 (cmd == DEVCTL_DEVICE_OFFLINE)) { 12696 if (ndi_dc_allochdl((void *)data, &dcp) != 12697 NDI_SUCCESS) { 12698 goto out; 12699 } 12700 addr = ndi_dc_getaddr(dcp); 12701 ptgt = mptsas_addr_to_ptgt(mpt, addr, phymask); 12702 if (ptgt == NULL) { 12703 NDBG14(("mptsas_ioctl led control: tgt %s not " 12704 "found", addr)); 12705 ndi_dc_freehdl(dcp); 12706 goto out; 12707 } 12708 mutex_enter(&mpt->m_mutex); 12709 if (cmd == DEVCTL_DEVICE_ONLINE) { 12710 ptgt->m_tgt_unconfigured = 0; 12711 } else if (cmd == DEVCTL_DEVICE_OFFLINE) { 12712 ptgt->m_tgt_unconfigured = 1; 12713 } 12714 if (cmd == DEVCTL_DEVICE_OFFLINE) { 12715 ptgt->m_led_status |= 12716 (1 << (MPTSAS_LEDCTL_LED_OK2RM - 1)); 12717 } else { 12718 ptgt->m_led_status &= 12719 ~(1 << (MPTSAS_LEDCTL_LED_OK2RM - 1)); 12720 } 12721 (void) mptsas_flush_led_status(mpt, ptgt); 12722 mutex_exit(&mpt->m_mutex); 12723 ndi_dc_freehdl(dcp); 12724 } 12725 goto out; 12726 } 12727 switch (cmd) { 12728 case MPTIOCTL_GET_DISK_INFO: 12729 status = get_disk_info(mpt, data, mode); 12730 break; 12731 case MPTIOCTL_LED_CONTROL: 12732 status = led_control(mpt, data, mode); 12733 break; 12734 case MPTIOCTL_UPDATE_FLASH: 12735 if (ddi_copyin((void *)data, &flashdata, 12736 sizeof (struct mptsas_update_flash), mode)) { 12737 status = EFAULT; 12738 break; 12739 } 12740 12741 mutex_enter(&mpt->m_mutex); 12742 if (mptsas_update_flash(mpt, 12743 (caddr_t)(long)flashdata.PtrBuffer, 12744 flashdata.ImageSize, flashdata.ImageType, mode)) { 12745 status = EFAULT; 12746 } 12747 12748 /* 12749 * Reset the chip to start using the new 12750 * firmware. Reset if failed also. 12751 */ 12752 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET; 12753 if (mptsas_restart_ioc(mpt) == DDI_FAILURE) { 12754 status = EFAULT; 12755 } 12756 mutex_exit(&mpt->m_mutex); 12757 break; 12758 case MPTIOCTL_PASS_THRU: 12759 /* 12760 * The user has requested to pass through a command to 12761 * be executed by the MPT firmware. Call our routine 12762 * which does this. Only allow one passthru IOCTL at 12763 * one time. Other threads will block on 12764 * m_passthru_mutex, which is of adaptive variant. 12765 */ 12766 if (ddi_copyin((void *)data, &passthru_data, 12767 sizeof (mptsas_pass_thru_t), mode)) { 12768 status = EFAULT; 12769 break; 12770 } 12771 mutex_enter(&mpt->m_passthru_mutex); 12772 mutex_enter(&mpt->m_mutex); 12773 status = mptsas_pass_thru(mpt, &passthru_data, mode); 12774 mutex_exit(&mpt->m_mutex); 12775 mutex_exit(&mpt->m_passthru_mutex); 12776 12777 break; 12778 case MPTIOCTL_GET_ADAPTER_DATA: 12779 /* 12780 * The user has requested to read adapter data. Call 12781 * our routine which does this. 12782 */ 12783 bzero(&adapter_data, sizeof (mptsas_adapter_data_t)); 12784 if (ddi_copyin((void *)data, (void *)&adapter_data, 12785 sizeof (mptsas_adapter_data_t), mode)) { 12786 status = EFAULT; 12787 break; 12788 } 12789 if (adapter_data.StructureLength >= 12790 sizeof (mptsas_adapter_data_t)) { 12791 adapter_data.StructureLength = (uint32_t) 12792 sizeof (mptsas_adapter_data_t); 12793 copylen = sizeof (mptsas_adapter_data_t); 12794 mutex_enter(&mpt->m_mutex); 12795 mptsas_read_adapter_data(mpt, &adapter_data); 12796 mutex_exit(&mpt->m_mutex); 12797 } else { 12798 adapter_data.StructureLength = (uint32_t) 12799 sizeof (mptsas_adapter_data_t); 12800 copylen = sizeof (adapter_data.StructureLength); 12801 *rval = MPTIOCTL_STATUS_LEN_TOO_SHORT; 12802 } 12803 if (ddi_copyout((void *)(&adapter_data), (void *)data, 12804 copylen, mode) != 0) { 12805 status = EFAULT; 12806 } 12807 break; 12808 case MPTIOCTL_GET_PCI_INFO: 12809 /* 12810 * The user has requested to read pci info. Call 12811 * our routine which does this. 12812 */ 12813 bzero(&pci_info, sizeof (mptsas_pci_info_t)); 12814 mutex_enter(&mpt->m_mutex); 12815 mptsas_read_pci_info(mpt, &pci_info); 12816 mutex_exit(&mpt->m_mutex); 12817 if (ddi_copyout((void *)(&pci_info), (void *)data, 12818 sizeof (mptsas_pci_info_t), mode) != 0) { 12819 status = EFAULT; 12820 } 12821 break; 12822 case MPTIOCTL_RESET_ADAPTER: 12823 mutex_enter(&mpt->m_mutex); 12824 mpt->m_softstate &= ~MPTSAS_SS_MSG_UNIT_RESET; 12825 if ((mptsas_restart_ioc(mpt)) == DDI_FAILURE) { 12826 mptsas_log(mpt, CE_WARN, "reset adapter IOCTL " 12827 "failed"); 12828 status = EFAULT; 12829 } 12830 mutex_exit(&mpt->m_mutex); 12831 break; 12832 case MPTIOCTL_DIAG_ACTION: 12833 /* 12834 * The user has done a diag buffer action. Call our 12835 * routine which does this. Only allow one diag action 12836 * at one time. 12837 */ 12838 mutex_enter(&mpt->m_mutex); 12839 if (mpt->m_diag_action_in_progress) { 12840 mutex_exit(&mpt->m_mutex); 12841 return (EBUSY); 12842 } 12843 mpt->m_diag_action_in_progress = 1; 12844 status = mptsas_diag_action(mpt, 12845 (mptsas_diag_action_t *)data, mode); 12846 mpt->m_diag_action_in_progress = 0; 12847 mutex_exit(&mpt->m_mutex); 12848 break; 12849 case MPTIOCTL_EVENT_QUERY: 12850 /* 12851 * The user has done an event query. Call our routine 12852 * which does this. 12853 */ 12854 status = mptsas_event_query(mpt, 12855 (mptsas_event_query_t *)data, mode, rval); 12856 break; 12857 case MPTIOCTL_EVENT_ENABLE: 12858 /* 12859 * The user has done an event enable. Call our routine 12860 * which does this. 12861 */ 12862 status = mptsas_event_enable(mpt, 12863 (mptsas_event_enable_t *)data, mode, rval); 12864 break; 12865 case MPTIOCTL_EVENT_REPORT: 12866 /* 12867 * The user has done an event report. Call our routine 12868 * which does this. 12869 */ 12870 status = mptsas_event_report(mpt, 12871 (mptsas_event_report_t *)data, mode, rval); 12872 break; 12873 case MPTIOCTL_REG_ACCESS: 12874 /* 12875 * The user has requested register access. Call our 12876 * routine which does this. 12877 */ 12878 status = mptsas_reg_access(mpt, 12879 (mptsas_reg_access_t *)data, mode); 12880 break; 12881 default: 12882 status = scsi_hba_ioctl(dev, cmd, data, mode, credp, 12883 rval); 12884 break; 12885 } 12886 12887 out: 12888 return (status); 12889 } 12890 12891 int 12892 mptsas_restart_ioc(mptsas_t *mpt) 12893 { 12894 int rval = DDI_SUCCESS; 12895 mptsas_target_t *ptgt = NULL; 12896 12897 ASSERT(mutex_owned(&mpt->m_mutex)); 12898 12899 /* 12900 * Set a flag telling I/O path that we're processing a reset. This is 12901 * needed because after the reset is complete, the hash table still 12902 * needs to be rebuilt. If I/Os are started before the hash table is 12903 * rebuilt, I/O errors will occur. This flag allows I/Os to be marked 12904 * so that they can be retried. 12905 */ 12906 mpt->m_in_reset = TRUE; 12907 12908 /* 12909 * Wait until all the allocated sense data buffers for DMA are freed. 12910 */ 12911 while (mpt->m_extreq_sense_refcount > 0) 12912 cv_wait(&mpt->m_extreq_sense_refcount_cv, &mpt->m_mutex); 12913 12914 /* 12915 * Set all throttles to HOLD 12916 */ 12917 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 12918 ptgt = refhash_next(mpt->m_targets, ptgt)) { 12919 mptsas_set_throttle(mpt, ptgt, HOLD_THROTTLE); 12920 } 12921 12922 /* 12923 * Disable interrupts 12924 */ 12925 MPTSAS_DISABLE_INTR(mpt); 12926 12927 /* 12928 * Abort all commands: outstanding commands, commands in waitq and 12929 * tx_waitq. 12930 */ 12931 mptsas_flush_hba(mpt); 12932 12933 /* 12934 * Reinitialize the chip. 12935 */ 12936 if (mptsas_init_chip(mpt, FALSE) == DDI_FAILURE) { 12937 rval = DDI_FAILURE; 12938 } 12939 12940 /* 12941 * Enable interrupts again 12942 */ 12943 MPTSAS_ENABLE_INTR(mpt); 12944 12945 /* 12946 * If mptsas_init_chip was successful, update the driver data. 12947 */ 12948 if (rval == DDI_SUCCESS) { 12949 mptsas_update_driver_data(mpt); 12950 } 12951 12952 /* 12953 * Reset the throttles 12954 */ 12955 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 12956 ptgt = refhash_next(mpt->m_targets, ptgt)) { 12957 mptsas_set_throttle(mpt, ptgt, MAX_THROTTLE); 12958 } 12959 12960 mptsas_doneq_empty(mpt); 12961 mptsas_restart_hba(mpt); 12962 12963 if (rval != DDI_SUCCESS) { 12964 mptsas_fm_ereport(mpt, DDI_FM_DEVICE_NO_RESPONSE); 12965 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_LOST); 12966 } 12967 12968 /* 12969 * Clear the reset flag so that I/Os can continue. 12970 */ 12971 mpt->m_in_reset = FALSE; 12972 12973 return (rval); 12974 } 12975 12976 static int 12977 mptsas_init_chip(mptsas_t *mpt, int first_time) 12978 { 12979 ddi_dma_cookie_t cookie; 12980 uint32_t i; 12981 int rval; 12982 12983 /* 12984 * Check to see if the firmware image is valid 12985 */ 12986 if (ddi_get32(mpt->m_datap, &mpt->m_reg->HostDiagnostic) & 12987 MPI2_DIAG_FLASH_BAD_SIG) { 12988 mptsas_log(mpt, CE_WARN, "mptsas bad flash signature!"); 12989 goto fail; 12990 } 12991 12992 /* 12993 * Reset the chip 12994 */ 12995 rval = mptsas_ioc_reset(mpt, first_time); 12996 if (rval == MPTSAS_RESET_FAIL) { 12997 mptsas_log(mpt, CE_WARN, "hard reset failed!"); 12998 goto fail; 12999 } 13000 13001 if ((rval == MPTSAS_SUCCESS_MUR) && (!first_time)) { 13002 goto mur; 13003 } 13004 /* 13005 * Setup configuration space 13006 */ 13007 if (mptsas_config_space_init(mpt) == FALSE) { 13008 mptsas_log(mpt, CE_WARN, "mptsas_config_space_init " 13009 "failed!"); 13010 goto fail; 13011 } 13012 13013 /* 13014 * IOC facts can change after a diag reset so all buffers that are 13015 * based on these numbers must be de-allocated and re-allocated. Get 13016 * new IOC facts each time chip is initialized. 13017 */ 13018 if (mptsas_ioc_get_facts(mpt) == DDI_FAILURE) { 13019 mptsas_log(mpt, CE_WARN, "mptsas_ioc_get_facts failed"); 13020 goto fail; 13021 } 13022 13023 if (mptsas_alloc_active_slots(mpt, KM_SLEEP)) { 13024 goto fail; 13025 } 13026 /* 13027 * Allocate request message frames, reply free queue, reply descriptor 13028 * post queue, and reply message frames using latest IOC facts. 13029 */ 13030 if (mptsas_alloc_request_frames(mpt) == DDI_FAILURE) { 13031 mptsas_log(mpt, CE_WARN, "mptsas_alloc_request_frames failed"); 13032 goto fail; 13033 } 13034 if (mptsas_alloc_sense_bufs(mpt) == DDI_FAILURE) { 13035 mptsas_log(mpt, CE_WARN, "mptsas_alloc_sense_bufs failed"); 13036 goto fail; 13037 } 13038 if (mptsas_alloc_free_queue(mpt) == DDI_FAILURE) { 13039 mptsas_log(mpt, CE_WARN, "mptsas_alloc_free_queue failed!"); 13040 goto fail; 13041 } 13042 if (mptsas_alloc_post_queue(mpt) == DDI_FAILURE) { 13043 mptsas_log(mpt, CE_WARN, "mptsas_alloc_post_queue failed!"); 13044 goto fail; 13045 } 13046 if (mptsas_alloc_reply_frames(mpt) == DDI_FAILURE) { 13047 mptsas_log(mpt, CE_WARN, "mptsas_alloc_reply_frames failed!"); 13048 goto fail; 13049 } 13050 13051 mur: 13052 /* 13053 * Re-Initialize ioc to operational state 13054 */ 13055 if (mptsas_ioc_init(mpt) == DDI_FAILURE) { 13056 mptsas_log(mpt, CE_WARN, "mptsas_ioc_init failed"); 13057 goto fail; 13058 } 13059 13060 mptsas_alloc_reply_args(mpt); 13061 13062 /* 13063 * Initialize reply post index. Reply free index is initialized after 13064 * the next loop. 13065 */ 13066 mpt->m_post_index = 0; 13067 13068 /* 13069 * Initialize the Reply Free Queue with the physical addresses of our 13070 * reply frames. 13071 */ 13072 cookie.dmac_address = mpt->m_reply_frame_dma_addr & 0xffffffffu; 13073 for (i = 0; i < mpt->m_max_replies; i++) { 13074 ddi_put32(mpt->m_acc_free_queue_hdl, 13075 &((uint32_t *)(void *)mpt->m_free_queue)[i], 13076 cookie.dmac_address); 13077 cookie.dmac_address += mpt->m_reply_frame_size; 13078 } 13079 (void) ddi_dma_sync(mpt->m_dma_free_queue_hdl, 0, 0, 13080 DDI_DMA_SYNC_FORDEV); 13081 13082 /* 13083 * Initialize the reply free index to one past the last frame on the 13084 * queue. This will signify that the queue is empty to start with. 13085 */ 13086 mpt->m_free_index = i; 13087 ddi_put32(mpt->m_datap, &mpt->m_reg->ReplyFreeHostIndex, i); 13088 13089 /* 13090 * Initialize the reply post queue to 0xFFFFFFFF,0xFFFFFFFF's. 13091 */ 13092 for (i = 0; i < mpt->m_post_queue_depth; i++) { 13093 ddi_put64(mpt->m_acc_post_queue_hdl, 13094 &((uint64_t *)(void *)mpt->m_post_queue)[i], 13095 0xFFFFFFFFFFFFFFFF); 13096 } 13097 (void) ddi_dma_sync(mpt->m_dma_post_queue_hdl, 0, 0, 13098 DDI_DMA_SYNC_FORDEV); 13099 13100 /* 13101 * Enable ports 13102 */ 13103 if (mptsas_ioc_enable_port(mpt) == DDI_FAILURE) { 13104 mptsas_log(mpt, CE_WARN, "mptsas_ioc_enable_port failed"); 13105 goto fail; 13106 } 13107 13108 /* 13109 * enable events 13110 */ 13111 if (mptsas_ioc_enable_event_notification(mpt)) { 13112 mptsas_log(mpt, CE_WARN, 13113 "mptsas_ioc_enable_event_notification failed"); 13114 goto fail; 13115 } 13116 13117 /* 13118 * We need checks in attach and these. 13119 * chip_init is called in mult. places 13120 */ 13121 13122 if ((mptsas_check_dma_handle(mpt->m_dma_req_frame_hdl) != 13123 DDI_SUCCESS) || 13124 (mptsas_check_dma_handle(mpt->m_dma_req_sense_hdl) != 13125 DDI_SUCCESS) || 13126 (mptsas_check_dma_handle(mpt->m_dma_reply_frame_hdl) != 13127 DDI_SUCCESS) || 13128 (mptsas_check_dma_handle(mpt->m_dma_free_queue_hdl) != 13129 DDI_SUCCESS) || 13130 (mptsas_check_dma_handle(mpt->m_dma_post_queue_hdl) != 13131 DDI_SUCCESS) || 13132 (mptsas_check_dma_handle(mpt->m_hshk_dma_hdl) != 13133 DDI_SUCCESS)) { 13134 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 13135 goto fail; 13136 } 13137 13138 /* Check all acc handles */ 13139 if ((mptsas_check_acc_handle(mpt->m_datap) != DDI_SUCCESS) || 13140 (mptsas_check_acc_handle(mpt->m_acc_req_frame_hdl) != 13141 DDI_SUCCESS) || 13142 (mptsas_check_acc_handle(mpt->m_acc_req_sense_hdl) != 13143 DDI_SUCCESS) || 13144 (mptsas_check_acc_handle(mpt->m_acc_reply_frame_hdl) != 13145 DDI_SUCCESS) || 13146 (mptsas_check_acc_handle(mpt->m_acc_free_queue_hdl) != 13147 DDI_SUCCESS) || 13148 (mptsas_check_acc_handle(mpt->m_acc_post_queue_hdl) != 13149 DDI_SUCCESS) || 13150 (mptsas_check_acc_handle(mpt->m_hshk_acc_hdl) != 13151 DDI_SUCCESS) || 13152 (mptsas_check_acc_handle(mpt->m_config_handle) != 13153 DDI_SUCCESS)) { 13154 ddi_fm_service_impact(mpt->m_dip, DDI_SERVICE_UNAFFECTED); 13155 goto fail; 13156 } 13157 13158 return (DDI_SUCCESS); 13159 13160 fail: 13161 return (DDI_FAILURE); 13162 } 13163 13164 static int 13165 mptsas_get_pci_cap(mptsas_t *mpt) 13166 { 13167 ushort_t caps_ptr, cap, cap_count; 13168 13169 if (mpt->m_config_handle == NULL) 13170 return (FALSE); 13171 /* 13172 * Check if capabilities list is supported and if so, 13173 * get initial capabilities pointer and clear bits 0,1. 13174 */ 13175 if (pci_config_get16(mpt->m_config_handle, PCI_CONF_STAT) 13176 & PCI_STAT_CAP) { 13177 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle, 13178 PCI_CONF_CAP_PTR), 4); 13179 } else { 13180 caps_ptr = PCI_CAP_NEXT_PTR_NULL; 13181 } 13182 13183 /* 13184 * Walk capabilities if supported. 13185 */ 13186 for (cap_count = 0; caps_ptr != PCI_CAP_NEXT_PTR_NULL; ) { 13187 13188 /* 13189 * Check that we haven't exceeded the maximum number of 13190 * capabilities and that the pointer is in a valid range. 13191 */ 13192 if (++cap_count > 48) { 13193 mptsas_log(mpt, CE_WARN, 13194 "too many device capabilities.\n"); 13195 break; 13196 } 13197 if (caps_ptr < 64) { 13198 mptsas_log(mpt, CE_WARN, 13199 "capabilities pointer 0x%x out of range.\n", 13200 caps_ptr); 13201 break; 13202 } 13203 13204 /* 13205 * Get next capability and check that it is valid. 13206 * For now, we only support power management. 13207 */ 13208 cap = pci_config_get8(mpt->m_config_handle, caps_ptr); 13209 switch (cap) { 13210 case PCI_CAP_ID_PM: 13211 mptsas_log(mpt, CE_NOTE, 13212 "?mptsas%d supports power management.\n", 13213 mpt->m_instance); 13214 mpt->m_options |= MPTSAS_OPT_PM; 13215 13216 /* Save PMCSR offset */ 13217 mpt->m_pmcsr_offset = caps_ptr + PCI_PMCSR; 13218 break; 13219 /* 13220 * The following capabilities are valid. Any others 13221 * will cause a message to be logged. 13222 */ 13223 case PCI_CAP_ID_VPD: 13224 case PCI_CAP_ID_MSI: 13225 case PCI_CAP_ID_PCIX: 13226 case PCI_CAP_ID_PCI_E: 13227 case PCI_CAP_ID_MSI_X: 13228 break; 13229 default: 13230 mptsas_log(mpt, CE_NOTE, 13231 "?mptsas%d unrecognized capability " 13232 "0x%x.\n", mpt->m_instance, cap); 13233 break; 13234 } 13235 13236 /* 13237 * Get next capabilities pointer and clear bits 0,1. 13238 */ 13239 caps_ptr = P2ALIGN(pci_config_get8(mpt->m_config_handle, 13240 (caps_ptr + PCI_CAP_NEXT_PTR)), 4); 13241 } 13242 return (TRUE); 13243 } 13244 13245 static int 13246 mptsas_init_pm(mptsas_t *mpt) 13247 { 13248 char pmc_name[16]; 13249 char *pmc[] = { 13250 NULL, 13251 "0=Off (PCI D3 State)", 13252 "3=On (PCI D0 State)", 13253 NULL 13254 }; 13255 uint16_t pmcsr_stat; 13256 13257 if (mptsas_get_pci_cap(mpt) == FALSE) { 13258 return (DDI_FAILURE); 13259 } 13260 /* 13261 * If PCI's capability does not support PM, then don't need 13262 * to registe the pm-components 13263 */ 13264 if (!(mpt->m_options & MPTSAS_OPT_PM)) 13265 return (DDI_SUCCESS); 13266 /* 13267 * If power management is supported by this chip, create 13268 * pm-components property for the power management framework 13269 */ 13270 (void) sprintf(pmc_name, "NAME=mptsas%d", mpt->m_instance); 13271 pmc[0] = pmc_name; 13272 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, mpt->m_dip, 13273 "pm-components", pmc, 3) != DDI_PROP_SUCCESS) { 13274 mpt->m_options &= ~MPTSAS_OPT_PM; 13275 mptsas_log(mpt, CE_WARN, 13276 "mptsas%d: pm-component property creation failed.", 13277 mpt->m_instance); 13278 return (DDI_FAILURE); 13279 } 13280 13281 /* 13282 * Power on device. 13283 */ 13284 (void) pm_busy_component(mpt->m_dip, 0); 13285 pmcsr_stat = pci_config_get16(mpt->m_config_handle, 13286 mpt->m_pmcsr_offset); 13287 if ((pmcsr_stat & PCI_PMCSR_STATE_MASK) != PCI_PMCSR_D0) { 13288 mptsas_log(mpt, CE_WARN, "mptsas%d: Power up the device", 13289 mpt->m_instance); 13290 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, 13291 PCI_PMCSR_D0); 13292 } 13293 if (pm_power_has_changed(mpt->m_dip, 0, PM_LEVEL_D0) != DDI_SUCCESS) { 13294 mptsas_log(mpt, CE_WARN, "pm_power_has_changed failed"); 13295 return (DDI_FAILURE); 13296 } 13297 mpt->m_power_level = PM_LEVEL_D0; 13298 /* 13299 * Set pm idle delay. 13300 */ 13301 mpt->m_pm_idle_delay = ddi_prop_get_int(DDI_DEV_T_ANY, 13302 mpt->m_dip, 0, "mptsas-pm-idle-delay", MPTSAS_PM_IDLE_TIMEOUT); 13303 13304 return (DDI_SUCCESS); 13305 } 13306 13307 static int 13308 mptsas_register_intrs(mptsas_t *mpt) 13309 { 13310 dev_info_t *dip; 13311 int intr_types; 13312 13313 dip = mpt->m_dip; 13314 13315 /* Get supported interrupt types */ 13316 if (ddi_intr_get_supported_types(dip, &intr_types) != DDI_SUCCESS) { 13317 mptsas_log(mpt, CE_WARN, "ddi_intr_get_supported_types " 13318 "failed\n"); 13319 return (FALSE); 13320 } 13321 13322 NDBG6(("ddi_intr_get_supported_types() returned: 0x%x", intr_types)); 13323 13324 /* 13325 * Try MSI, but fall back to FIXED 13326 */ 13327 if (mptsas_enable_msi && (intr_types & DDI_INTR_TYPE_MSI)) { 13328 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_MSI) == DDI_SUCCESS) { 13329 NDBG0(("Using MSI interrupt type")); 13330 mpt->m_intr_type = DDI_INTR_TYPE_MSI; 13331 return (TRUE); 13332 } 13333 } 13334 if (intr_types & DDI_INTR_TYPE_FIXED) { 13335 if (mptsas_add_intrs(mpt, DDI_INTR_TYPE_FIXED) == DDI_SUCCESS) { 13336 NDBG0(("Using FIXED interrupt type")); 13337 mpt->m_intr_type = DDI_INTR_TYPE_FIXED; 13338 return (TRUE); 13339 } else { 13340 NDBG0(("FIXED interrupt registration failed")); 13341 return (FALSE); 13342 } 13343 } 13344 13345 return (FALSE); 13346 } 13347 13348 static void 13349 mptsas_unregister_intrs(mptsas_t *mpt) 13350 { 13351 mptsas_rem_intrs(mpt); 13352 } 13353 13354 /* 13355 * mptsas_add_intrs: 13356 * 13357 * Register FIXED or MSI interrupts. 13358 */ 13359 static int 13360 mptsas_add_intrs(mptsas_t *mpt, int intr_type) 13361 { 13362 dev_info_t *dip = mpt->m_dip; 13363 int avail, actual, count = 0; 13364 int i, flag, ret; 13365 13366 NDBG6(("mptsas_add_intrs:interrupt type 0x%x", intr_type)); 13367 13368 /* Get number of interrupts */ 13369 ret = ddi_intr_get_nintrs(dip, intr_type, &count); 13370 if ((ret != DDI_SUCCESS) || (count <= 0)) { 13371 mptsas_log(mpt, CE_WARN, "ddi_intr_get_nintrs() failed, " 13372 "ret %d count %d\n", ret, count); 13373 13374 return (DDI_FAILURE); 13375 } 13376 13377 /* Get number of available interrupts */ 13378 ret = ddi_intr_get_navail(dip, intr_type, &avail); 13379 if ((ret != DDI_SUCCESS) || (avail == 0)) { 13380 mptsas_log(mpt, CE_WARN, "ddi_intr_get_navail() failed, " 13381 "ret %d avail %d\n", ret, avail); 13382 13383 return (DDI_FAILURE); 13384 } 13385 13386 if (avail < count) { 13387 mptsas_log(mpt, CE_NOTE, "ddi_intr_get_nvail returned %d, " 13388 "navail() returned %d", count, avail); 13389 } 13390 13391 /* Mpt only have one interrupt routine */ 13392 if ((intr_type == DDI_INTR_TYPE_MSI) && (count > 1)) { 13393 count = 1; 13394 } 13395 13396 /* Allocate an array of interrupt handles */ 13397 mpt->m_intr_size = count * sizeof (ddi_intr_handle_t); 13398 mpt->m_htable = kmem_alloc(mpt->m_intr_size, KM_SLEEP); 13399 13400 flag = DDI_INTR_ALLOC_NORMAL; 13401 13402 /* call ddi_intr_alloc() */ 13403 ret = ddi_intr_alloc(dip, mpt->m_htable, intr_type, 0, 13404 count, &actual, flag); 13405 13406 if ((ret != DDI_SUCCESS) || (actual == 0)) { 13407 mptsas_log(mpt, CE_WARN, "ddi_intr_alloc() failed, ret %d\n", 13408 ret); 13409 kmem_free(mpt->m_htable, mpt->m_intr_size); 13410 return (DDI_FAILURE); 13411 } 13412 13413 /* use interrupt count returned or abort? */ 13414 if (actual < count) { 13415 mptsas_log(mpt, CE_NOTE, "Requested: %d, Received: %d\n", 13416 count, actual); 13417 } 13418 13419 mpt->m_intr_cnt = actual; 13420 13421 /* 13422 * Get priority for first msi, assume remaining are all the same 13423 */ 13424 if ((ret = ddi_intr_get_pri(mpt->m_htable[0], 13425 &mpt->m_intr_pri)) != DDI_SUCCESS) { 13426 mptsas_log(mpt, CE_WARN, "ddi_intr_get_pri() failed %d\n", ret); 13427 13428 /* Free already allocated intr */ 13429 for (i = 0; i < actual; i++) { 13430 (void) ddi_intr_free(mpt->m_htable[i]); 13431 } 13432 13433 kmem_free(mpt->m_htable, mpt->m_intr_size); 13434 return (DDI_FAILURE); 13435 } 13436 13437 /* Test for high level mutex */ 13438 if (mpt->m_intr_pri >= ddi_intr_get_hilevel_pri()) { 13439 mptsas_log(mpt, CE_WARN, "mptsas_add_intrs: " 13440 "Hi level interrupt not supported\n"); 13441 13442 /* Free already allocated intr */ 13443 for (i = 0; i < actual; i++) { 13444 (void) ddi_intr_free(mpt->m_htable[i]); 13445 } 13446 13447 kmem_free(mpt->m_htable, mpt->m_intr_size); 13448 return (DDI_FAILURE); 13449 } 13450 13451 /* Call ddi_intr_add_handler() */ 13452 for (i = 0; i < actual; i++) { 13453 if ((ret = ddi_intr_add_handler(mpt->m_htable[i], mptsas_intr, 13454 (caddr_t)mpt, (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) { 13455 mptsas_log(mpt, CE_WARN, "ddi_intr_add_handler() " 13456 "failed %d\n", ret); 13457 13458 /* Free already allocated intr */ 13459 for (i = 0; i < actual; i++) { 13460 (void) ddi_intr_free(mpt->m_htable[i]); 13461 } 13462 13463 kmem_free(mpt->m_htable, mpt->m_intr_size); 13464 return (DDI_FAILURE); 13465 } 13466 } 13467 13468 if ((ret = ddi_intr_get_cap(mpt->m_htable[0], &mpt->m_intr_cap)) 13469 != DDI_SUCCESS) { 13470 mptsas_log(mpt, CE_WARN, "ddi_intr_get_cap() failed %d\n", ret); 13471 13472 /* Free already allocated intr */ 13473 for (i = 0; i < actual; i++) { 13474 (void) ddi_intr_free(mpt->m_htable[i]); 13475 } 13476 13477 kmem_free(mpt->m_htable, mpt->m_intr_size); 13478 return (DDI_FAILURE); 13479 } 13480 13481 /* 13482 * Enable interrupts 13483 */ 13484 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) { 13485 /* Call ddi_intr_block_enable() for MSI interrupts */ 13486 (void) ddi_intr_block_enable(mpt->m_htable, mpt->m_intr_cnt); 13487 } else { 13488 /* Call ddi_intr_enable for MSI or FIXED interrupts */ 13489 for (i = 0; i < mpt->m_intr_cnt; i++) { 13490 (void) ddi_intr_enable(mpt->m_htable[i]); 13491 } 13492 } 13493 return (DDI_SUCCESS); 13494 } 13495 13496 /* 13497 * mptsas_rem_intrs: 13498 * 13499 * Unregister FIXED or MSI interrupts 13500 */ 13501 static void 13502 mptsas_rem_intrs(mptsas_t *mpt) 13503 { 13504 int i; 13505 13506 NDBG6(("mptsas_rem_intrs")); 13507 13508 /* Disable all interrupts */ 13509 if (mpt->m_intr_cap & DDI_INTR_FLAG_BLOCK) { 13510 /* Call ddi_intr_block_disable() */ 13511 (void) ddi_intr_block_disable(mpt->m_htable, mpt->m_intr_cnt); 13512 } else { 13513 for (i = 0; i < mpt->m_intr_cnt; i++) { 13514 (void) ddi_intr_disable(mpt->m_htable[i]); 13515 } 13516 } 13517 13518 /* Call ddi_intr_remove_handler() */ 13519 for (i = 0; i < mpt->m_intr_cnt; i++) { 13520 (void) ddi_intr_remove_handler(mpt->m_htable[i]); 13521 (void) ddi_intr_free(mpt->m_htable[i]); 13522 } 13523 13524 kmem_free(mpt->m_htable, mpt->m_intr_size); 13525 } 13526 13527 /* 13528 * The IO fault service error handling callback function 13529 */ 13530 /*ARGSUSED*/ 13531 static int 13532 mptsas_fm_error_cb(dev_info_t *dip, ddi_fm_error_t *err, const void *impl_data) 13533 { 13534 /* 13535 * as the driver can always deal with an error in any dma or 13536 * access handle, we can just return the fme_status value. 13537 */ 13538 pci_ereport_post(dip, err, NULL); 13539 return (err->fme_status); 13540 } 13541 13542 /* 13543 * mptsas_fm_init - initialize fma capabilities and register with IO 13544 * fault services. 13545 */ 13546 static void 13547 mptsas_fm_init(mptsas_t *mpt) 13548 { 13549 /* 13550 * Need to change iblock to priority for new MSI intr 13551 */ 13552 ddi_iblock_cookie_t fm_ibc; 13553 13554 /* Only register with IO Fault Services if we have some capability */ 13555 if (mpt->m_fm_capabilities) { 13556 /* Adjust access and dma attributes for FMA */ 13557 mpt->m_reg_acc_attr.devacc_attr_access = DDI_FLAGERR_ACC; 13558 mpt->m_msg_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR; 13559 mpt->m_io_dma_attr.dma_attr_flags |= DDI_DMA_FLAGERR; 13560 13561 /* 13562 * Register capabilities with IO Fault Services. 13563 * mpt->m_fm_capabilities will be updated to indicate 13564 * capabilities actually supported (not requested.) 13565 */ 13566 ddi_fm_init(mpt->m_dip, &mpt->m_fm_capabilities, &fm_ibc); 13567 13568 /* 13569 * Initialize pci ereport capabilities if ereport 13570 * capable (should always be.) 13571 */ 13572 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) || 13573 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) { 13574 pci_ereport_setup(mpt->m_dip); 13575 } 13576 13577 /* 13578 * Register error callback if error callback capable. 13579 */ 13580 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) { 13581 ddi_fm_handler_register(mpt->m_dip, 13582 mptsas_fm_error_cb, (void *) mpt); 13583 } 13584 } 13585 } 13586 13587 /* 13588 * mptsas_fm_fini - Releases fma capabilities and un-registers with IO 13589 * fault services. 13590 * 13591 */ 13592 static void 13593 mptsas_fm_fini(mptsas_t *mpt) 13594 { 13595 /* Only unregister FMA capabilities if registered */ 13596 if (mpt->m_fm_capabilities) { 13597 13598 /* 13599 * Un-register error callback if error callback capable. 13600 */ 13601 13602 if (DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) { 13603 ddi_fm_handler_unregister(mpt->m_dip); 13604 } 13605 13606 /* 13607 * Release any resources allocated by pci_ereport_setup() 13608 */ 13609 13610 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities) || 13611 DDI_FM_ERRCB_CAP(mpt->m_fm_capabilities)) { 13612 pci_ereport_teardown(mpt->m_dip); 13613 } 13614 13615 /* Unregister from IO Fault Services */ 13616 ddi_fm_fini(mpt->m_dip); 13617 13618 /* Adjust access and dma attributes for FMA */ 13619 mpt->m_reg_acc_attr.devacc_attr_access = DDI_DEFAULT_ACC; 13620 mpt->m_msg_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR; 13621 mpt->m_io_dma_attr.dma_attr_flags &= ~DDI_DMA_FLAGERR; 13622 13623 } 13624 } 13625 13626 int 13627 mptsas_check_acc_handle(ddi_acc_handle_t handle) 13628 { 13629 ddi_fm_error_t de; 13630 13631 if (handle == NULL) 13632 return (DDI_FAILURE); 13633 ddi_fm_acc_err_get(handle, &de, DDI_FME_VER0); 13634 return (de.fme_status); 13635 } 13636 13637 int 13638 mptsas_check_dma_handle(ddi_dma_handle_t handle) 13639 { 13640 ddi_fm_error_t de; 13641 13642 if (handle == NULL) 13643 return (DDI_FAILURE); 13644 ddi_fm_dma_err_get(handle, &de, DDI_FME_VER0); 13645 return (de.fme_status); 13646 } 13647 13648 void 13649 mptsas_fm_ereport(mptsas_t *mpt, char *detail) 13650 { 13651 uint64_t ena; 13652 char buf[FM_MAX_CLASS]; 13653 13654 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", DDI_FM_DEVICE, detail); 13655 ena = fm_ena_generate(0, FM_ENA_FMT1); 13656 if (DDI_FM_EREPORT_CAP(mpt->m_fm_capabilities)) { 13657 ddi_fm_ereport_post(mpt->m_dip, buf, ena, DDI_NOSLEEP, 13658 FM_VERSION, DATA_TYPE_UINT8, FM_EREPORT_VERS0, NULL); 13659 } 13660 } 13661 13662 static int 13663 mptsas_get_target_device_info(mptsas_t *mpt, uint32_t page_address, 13664 uint16_t *dev_handle, mptsas_target_t **pptgt) 13665 { 13666 int rval; 13667 uint32_t dev_info; 13668 uint64_t sas_wwn; 13669 mptsas_phymask_t phymask; 13670 uint8_t physport, phynum, config, disk; 13671 uint64_t devicename; 13672 uint16_t pdev_hdl; 13673 mptsas_target_t *tmp_tgt = NULL; 13674 uint16_t bay_num, enclosure, io_flags; 13675 13676 ASSERT(*pptgt == NULL); 13677 13678 rval = mptsas_get_sas_device_page0(mpt, page_address, dev_handle, 13679 &sas_wwn, &dev_info, &physport, &phynum, &pdev_hdl, 13680 &bay_num, &enclosure, &io_flags); 13681 if (rval != DDI_SUCCESS) { 13682 rval = DEV_INFO_FAIL_PAGE0; 13683 return (rval); 13684 } 13685 13686 if ((dev_info & (MPI2_SAS_DEVICE_INFO_SSP_TARGET | 13687 MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 13688 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) == NULL) { 13689 rval = DEV_INFO_WRONG_DEVICE_TYPE; 13690 return (rval); 13691 } 13692 13693 /* 13694 * Check if the dev handle is for a Phys Disk. If so, set return value 13695 * and exit. Don't add Phys Disks to hash. 13696 */ 13697 for (config = 0; config < mpt->m_num_raid_configs; config++) { 13698 for (disk = 0; disk < MPTSAS_MAX_DISKS_IN_CONFIG; disk++) { 13699 if (*dev_handle == mpt->m_raidconfig[config]. 13700 m_physdisk_devhdl[disk]) { 13701 rval = DEV_INFO_PHYS_DISK; 13702 return (rval); 13703 } 13704 } 13705 } 13706 13707 /* 13708 * Get SATA Device Name from SAS device page0 for 13709 * sata device, if device name doesn't exist, set mta_wwn to 13710 * 0 for direct attached SATA. For the device behind the expander 13711 * we still can use STP address assigned by expander. 13712 */ 13713 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 13714 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 13715 /* alloc a temporary target to send the cmd to */ 13716 tmp_tgt = mptsas_tgt_alloc(mpt->m_tmp_targets, *dev_handle, 13717 0, dev_info, 0, 0); 13718 mutex_exit(&mpt->m_mutex); 13719 13720 devicename = mptsas_get_sata_guid(mpt, tmp_tgt, 0); 13721 13722 if (devicename == -1) { 13723 mutex_enter(&mpt->m_mutex); 13724 refhash_remove(mpt->m_tmp_targets, tmp_tgt); 13725 rval = DEV_INFO_FAIL_GUID; 13726 return (rval); 13727 } 13728 13729 if (devicename != 0 && (((devicename >> 56) & 0xf0) == 0x50)) { 13730 sas_wwn = devicename; 13731 } else if (dev_info & MPI2_SAS_DEVICE_INFO_DIRECT_ATTACH) { 13732 sas_wwn = 0; 13733 } 13734 13735 mutex_enter(&mpt->m_mutex); 13736 refhash_remove(mpt->m_tmp_targets, tmp_tgt); 13737 } 13738 13739 phymask = mptsas_physport_to_phymask(mpt, physport); 13740 *pptgt = mptsas_tgt_alloc(mpt->m_targets, *dev_handle, sas_wwn, 13741 dev_info, phymask, phynum); 13742 if (*pptgt == NULL) { 13743 mptsas_log(mpt, CE_WARN, "Failed to allocated target" 13744 "structure!"); 13745 rval = DEV_INFO_FAIL_ALLOC; 13746 return (rval); 13747 } 13748 (*pptgt)->m_io_flags = io_flags; 13749 (*pptgt)->m_enclosure = enclosure; 13750 (*pptgt)->m_slot_num = bay_num; 13751 return (DEV_INFO_SUCCESS); 13752 } 13753 13754 uint64_t 13755 mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun) 13756 { 13757 uint64_t sata_guid = 0, *pwwn = NULL; 13758 int target = ptgt->m_devhdl; 13759 uchar_t *inq83 = NULL; 13760 int inq83_len = 0xFF; 13761 uchar_t *dblk = NULL; 13762 int inq83_retry = 3; 13763 int rval = DDI_FAILURE; 13764 13765 inq83 = kmem_zalloc(inq83_len, KM_SLEEP); 13766 13767 inq83_retry: 13768 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83, 13769 inq83_len, NULL, 1); 13770 if (rval != DDI_SUCCESS) { 13771 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page " 13772 "0x83 for target:%x, lun:%x failed!", target, lun); 13773 sata_guid = -1; 13774 goto out; 13775 } 13776 /* According to SAT2, the first descriptor is logic unit name */ 13777 dblk = &inq83[4]; 13778 if ((dblk[1] & 0x30) != 0) { 13779 mptsas_log(mpt, CE_WARN, "!Descriptor is not lun associated."); 13780 goto out; 13781 } 13782 pwwn = (uint64_t *)(void *)(&dblk[4]); 13783 if ((dblk[4] & 0xf0) == 0x50) { 13784 sata_guid = BE_64(*pwwn); 13785 goto out; 13786 } else if (dblk[4] == 'A') { 13787 NDBG20(("SATA drive has no NAA format GUID.")); 13788 goto out; 13789 } else { 13790 /* The data is not ready, wait and retry */ 13791 inq83_retry--; 13792 if (inq83_retry <= 0) { 13793 goto out; 13794 } 13795 NDBG20(("The GUID is not ready, retry...")); 13796 delay(1 * drv_usectohz(1000000)); 13797 goto inq83_retry; 13798 } 13799 out: 13800 kmem_free(inq83, inq83_len); 13801 return (sata_guid); 13802 } 13803 13804 static int 13805 mptsas_inquiry(mptsas_t *mpt, mptsas_target_t *ptgt, int lun, uchar_t page, 13806 unsigned char *buf, int len, int *reallen, uchar_t evpd) 13807 { 13808 uchar_t cdb[CDB_GROUP0]; 13809 struct scsi_address ap; 13810 struct buf *data_bp = NULL; 13811 int resid = 0; 13812 int ret = DDI_FAILURE; 13813 13814 ASSERT(len <= 0xffff); 13815 13816 ap.a_target = MPTSAS_INVALID_DEVHDL; 13817 ap.a_lun = (uchar_t)(lun); 13818 ap.a_hba_tran = mpt->m_tran; 13819 13820 data_bp = scsi_alloc_consistent_buf(&ap, 13821 (struct buf *)NULL, len, B_READ, NULL_FUNC, NULL); 13822 if (data_bp == NULL) { 13823 return (ret); 13824 } 13825 bzero(cdb, CDB_GROUP0); 13826 cdb[0] = SCMD_INQUIRY; 13827 cdb[1] = evpd; 13828 cdb[2] = page; 13829 cdb[3] = (len & 0xff00) >> 8; 13830 cdb[4] = (len & 0x00ff); 13831 cdb[5] = 0; 13832 13833 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP0, data_bp, 13834 &resid); 13835 if (ret == DDI_SUCCESS) { 13836 if (reallen) { 13837 *reallen = len - resid; 13838 } 13839 bcopy((caddr_t)data_bp->b_un.b_addr, buf, len); 13840 } 13841 if (data_bp) { 13842 scsi_free_consistent_buf(data_bp); 13843 } 13844 return (ret); 13845 } 13846 13847 static int 13848 mptsas_send_scsi_cmd(mptsas_t *mpt, struct scsi_address *ap, 13849 mptsas_target_t *ptgt, uchar_t *cdb, int cdblen, struct buf *data_bp, 13850 int *resid) 13851 { 13852 struct scsi_pkt *pktp = NULL; 13853 scsi_hba_tran_t *tran_clone = NULL; 13854 mptsas_tgt_private_t *tgt_private = NULL; 13855 int ret = DDI_FAILURE; 13856 13857 /* 13858 * scsi_hba_tran_t->tran_tgt_private is used to pass the address 13859 * information to scsi_init_pkt, allocate a scsi_hba_tran structure 13860 * to simulate the cmds from sd 13861 */ 13862 tran_clone = kmem_alloc( 13863 sizeof (scsi_hba_tran_t), KM_SLEEP); 13864 if (tran_clone == NULL) { 13865 goto out; 13866 } 13867 bcopy((caddr_t)mpt->m_tran, 13868 (caddr_t)tran_clone, sizeof (scsi_hba_tran_t)); 13869 tgt_private = kmem_alloc( 13870 sizeof (mptsas_tgt_private_t), KM_SLEEP); 13871 if (tgt_private == NULL) { 13872 goto out; 13873 } 13874 tgt_private->t_lun = ap->a_lun; 13875 tgt_private->t_private = ptgt; 13876 tran_clone->tran_tgt_private = tgt_private; 13877 ap->a_hba_tran = tran_clone; 13878 13879 pktp = scsi_init_pkt(ap, (struct scsi_pkt *)NULL, 13880 data_bp, cdblen, sizeof (struct scsi_arq_status), 13881 0, PKT_CONSISTENT, NULL, NULL); 13882 if (pktp == NULL) { 13883 goto out; 13884 } 13885 bcopy(cdb, pktp->pkt_cdbp, cdblen); 13886 pktp->pkt_flags = FLAG_NOPARITY; 13887 if (scsi_poll(pktp) < 0) { 13888 goto out; 13889 } 13890 if (((struct scsi_status *)pktp->pkt_scbp)->sts_chk) { 13891 goto out; 13892 } 13893 if (resid != NULL) { 13894 *resid = pktp->pkt_resid; 13895 } 13896 13897 ret = DDI_SUCCESS; 13898 out: 13899 if (pktp) { 13900 scsi_destroy_pkt(pktp); 13901 } 13902 if (tran_clone) { 13903 kmem_free(tran_clone, sizeof (scsi_hba_tran_t)); 13904 } 13905 if (tgt_private) { 13906 kmem_free(tgt_private, sizeof (mptsas_tgt_private_t)); 13907 } 13908 return (ret); 13909 } 13910 static int 13911 mptsas_parse_address(char *name, uint64_t *wwid, uint8_t *phy, int *lun) 13912 { 13913 char *cp = NULL; 13914 char *ptr = NULL; 13915 size_t s = 0; 13916 char *wwid_str = NULL; 13917 char *lun_str = NULL; 13918 long lunnum; 13919 long phyid = -1; 13920 int rc = DDI_FAILURE; 13921 13922 ptr = name; 13923 ASSERT(ptr[0] == 'w' || ptr[0] == 'p'); 13924 ptr++; 13925 if ((cp = strchr(ptr, ',')) == NULL) { 13926 return (DDI_FAILURE); 13927 } 13928 13929 wwid_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 13930 s = (uintptr_t)cp - (uintptr_t)ptr; 13931 13932 bcopy(ptr, wwid_str, s); 13933 wwid_str[s] = '\0'; 13934 13935 ptr = ++cp; 13936 13937 if ((cp = strchr(ptr, '\0')) == NULL) { 13938 goto out; 13939 } 13940 lun_str = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 13941 s = (uintptr_t)cp - (uintptr_t)ptr; 13942 13943 bcopy(ptr, lun_str, s); 13944 lun_str[s] = '\0'; 13945 13946 if (name[0] == 'p') { 13947 rc = ddi_strtol(wwid_str, NULL, 0x10, &phyid); 13948 } else { 13949 rc = scsi_wwnstr_to_wwn(wwid_str, wwid); 13950 } 13951 if (rc != DDI_SUCCESS) 13952 goto out; 13953 13954 if (phyid != -1) { 13955 ASSERT(phyid < MPTSAS_MAX_PHYS); 13956 *phy = (uint8_t)phyid; 13957 } 13958 rc = ddi_strtol(lun_str, NULL, 0x10, &lunnum); 13959 if (rc != 0) 13960 goto out; 13961 13962 *lun = (int)lunnum; 13963 rc = DDI_SUCCESS; 13964 out: 13965 if (wwid_str) 13966 kmem_free(wwid_str, SCSI_MAXNAMELEN); 13967 if (lun_str) 13968 kmem_free(lun_str, SCSI_MAXNAMELEN); 13969 13970 return (rc); 13971 } 13972 13973 /* 13974 * mptsas_parse_smp_name() is to parse sas wwn string 13975 * which format is "wWWN" 13976 */ 13977 static int 13978 mptsas_parse_smp_name(char *name, uint64_t *wwn) 13979 { 13980 char *ptr = name; 13981 13982 if (*ptr != 'w') { 13983 return (DDI_FAILURE); 13984 } 13985 13986 ptr++; 13987 if (scsi_wwnstr_to_wwn(ptr, wwn)) { 13988 return (DDI_FAILURE); 13989 } 13990 return (DDI_SUCCESS); 13991 } 13992 13993 static int 13994 mptsas_bus_config(dev_info_t *pdip, uint_t flag, 13995 ddi_bus_config_op_t op, void *arg, dev_info_t **childp) 13996 { 13997 int ret = NDI_FAILURE; 13998 int circ = 0; 13999 int circ1 = 0; 14000 mptsas_t *mpt; 14001 char *ptr = NULL; 14002 char *devnm = NULL; 14003 uint64_t wwid = 0; 14004 uint8_t phy = 0xFF; 14005 int lun = 0; 14006 uint_t mflags = flag; 14007 int bconfig = TRUE; 14008 14009 if (scsi_hba_iport_unit_address(pdip) == 0) { 14010 return (DDI_FAILURE); 14011 } 14012 14013 mpt = DIP2MPT(pdip); 14014 if (!mpt) { 14015 return (DDI_FAILURE); 14016 } 14017 /* 14018 * Hold the nexus across the bus_config 14019 */ 14020 ndi_devi_enter(scsi_vhci_dip, &circ); 14021 ndi_devi_enter(pdip, &circ1); 14022 switch (op) { 14023 case BUS_CONFIG_ONE: 14024 /* parse wwid/target name out of name given */ 14025 if ((ptr = strchr((char *)arg, '@')) == NULL) { 14026 ret = NDI_FAILURE; 14027 break; 14028 } 14029 ptr++; 14030 if (strncmp((char *)arg, "smp", 3) == 0) { 14031 /* 14032 * This is a SMP target device 14033 */ 14034 ret = mptsas_parse_smp_name(ptr, &wwid); 14035 if (ret != DDI_SUCCESS) { 14036 ret = NDI_FAILURE; 14037 break; 14038 } 14039 ret = mptsas_config_smp(pdip, wwid, childp); 14040 } else if ((ptr[0] == 'w') || (ptr[0] == 'p')) { 14041 /* 14042 * OBP could pass down a non-canonical form 14043 * bootpath without LUN part when LUN is 0. 14044 * So driver need adjust the string. 14045 */ 14046 if (strchr(ptr, ',') == NULL) { 14047 devnm = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 14048 (void) sprintf(devnm, "%s,0", (char *)arg); 14049 ptr = strchr(devnm, '@'); 14050 ptr++; 14051 } 14052 14053 /* 14054 * The device path is wWWID format and the device 14055 * is not SMP target device. 14056 */ 14057 ret = mptsas_parse_address(ptr, &wwid, &phy, &lun); 14058 if (ret != DDI_SUCCESS) { 14059 ret = NDI_FAILURE; 14060 break; 14061 } 14062 *childp = NULL; 14063 if (ptr[0] == 'w') { 14064 ret = mptsas_config_one_addr(pdip, wwid, 14065 lun, childp); 14066 } else if (ptr[0] == 'p') { 14067 ret = mptsas_config_one_phy(pdip, phy, lun, 14068 childp); 14069 } 14070 14071 /* 14072 * If this is CD/DVD device in OBP path, the 14073 * ndi_busop_bus_config can be skipped as config one 14074 * operation is done above. 14075 */ 14076 if ((ret == NDI_SUCCESS) && (*childp != NULL) && 14077 (strcmp(ddi_node_name(*childp), "cdrom") == 0) && 14078 (strncmp((char *)arg, "disk", 4) == 0)) { 14079 bconfig = FALSE; 14080 ndi_hold_devi(*childp); 14081 } 14082 } else { 14083 ret = NDI_FAILURE; 14084 break; 14085 } 14086 14087 /* 14088 * DDI group instructed us to use this flag. 14089 */ 14090 mflags |= NDI_MDI_FALLBACK; 14091 break; 14092 case BUS_CONFIG_DRIVER: 14093 case BUS_CONFIG_ALL: 14094 mptsas_config_all(pdip); 14095 ret = NDI_SUCCESS; 14096 break; 14097 } 14098 14099 if ((ret == NDI_SUCCESS) && bconfig) { 14100 ret = ndi_busop_bus_config(pdip, mflags, op, 14101 (devnm == NULL) ? arg : devnm, childp, 0); 14102 } 14103 14104 ndi_devi_exit(pdip, circ1); 14105 ndi_devi_exit(scsi_vhci_dip, circ); 14106 if (devnm != NULL) 14107 kmem_free(devnm, SCSI_MAXNAMELEN); 14108 return (ret); 14109 } 14110 14111 static int 14112 mptsas_probe_lun(dev_info_t *pdip, int lun, dev_info_t **dip, 14113 mptsas_target_t *ptgt) 14114 { 14115 int rval = DDI_FAILURE; 14116 struct scsi_inquiry *sd_inq = NULL; 14117 mptsas_t *mpt = DIP2MPT(pdip); 14118 14119 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP); 14120 14121 rval = mptsas_inquiry(mpt, ptgt, lun, 0, (uchar_t *)sd_inq, 14122 SUN_INQSIZE, 0, (uchar_t)0); 14123 14124 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) { 14125 rval = mptsas_create_lun(pdip, sd_inq, dip, ptgt, lun); 14126 } else { 14127 rval = DDI_FAILURE; 14128 } 14129 14130 kmem_free(sd_inq, SUN_INQSIZE); 14131 return (rval); 14132 } 14133 14134 static int 14135 mptsas_config_one_addr(dev_info_t *pdip, uint64_t sasaddr, int lun, 14136 dev_info_t **lundip) 14137 { 14138 int rval; 14139 mptsas_t *mpt = DIP2MPT(pdip); 14140 int phymask; 14141 mptsas_target_t *ptgt = NULL; 14142 14143 /* 14144 * Get the physical port associated to the iport 14145 */ 14146 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0, 14147 "phymask", 0); 14148 14149 ptgt = mptsas_wwid_to_ptgt(mpt, phymask, sasaddr); 14150 if (ptgt == NULL) { 14151 /* 14152 * didn't match any device by searching 14153 */ 14154 return (DDI_FAILURE); 14155 } 14156 /* 14157 * If the LUN already exists and the status is online, 14158 * we just return the pointer to dev_info_t directly. 14159 * For the mdi_pathinfo node, we'll handle it in 14160 * mptsas_create_virt_lun() 14161 * TODO should be also in mptsas_handle_dr 14162 */ 14163 14164 *lundip = mptsas_find_child_addr(pdip, sasaddr, lun); 14165 if (*lundip != NULL) { 14166 /* 14167 * TODO Another senario is, we hotplug the same disk 14168 * on the same slot, the devhdl changed, is this 14169 * possible? 14170 * tgt_private->t_private != ptgt 14171 */ 14172 if (sasaddr != ptgt->m_addr.mta_wwn) { 14173 /* 14174 * The device has changed although the devhdl is the 14175 * same (Enclosure mapping mode, change drive on the 14176 * same slot) 14177 */ 14178 return (DDI_FAILURE); 14179 } 14180 return (DDI_SUCCESS); 14181 } 14182 14183 if (phymask == 0) { 14184 /* 14185 * Configure IR volume 14186 */ 14187 rval = mptsas_config_raid(pdip, ptgt->m_devhdl, lundip); 14188 return (rval); 14189 } 14190 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt); 14191 14192 return (rval); 14193 } 14194 14195 static int 14196 mptsas_config_one_phy(dev_info_t *pdip, uint8_t phy, int lun, 14197 dev_info_t **lundip) 14198 { 14199 int rval; 14200 mptsas_t *mpt = DIP2MPT(pdip); 14201 mptsas_phymask_t phymask; 14202 mptsas_target_t *ptgt = NULL; 14203 14204 /* 14205 * Get the physical port associated to the iport 14206 */ 14207 phymask = (mptsas_phymask_t)ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0, 14208 "phymask", 0); 14209 14210 ptgt = mptsas_phy_to_tgt(mpt, phymask, phy); 14211 if (ptgt == NULL) { 14212 /* 14213 * didn't match any device by searching 14214 */ 14215 return (DDI_FAILURE); 14216 } 14217 14218 /* 14219 * If the LUN already exists and the status is online, 14220 * we just return the pointer to dev_info_t directly. 14221 * For the mdi_pathinfo node, we'll handle it in 14222 * mptsas_create_virt_lun(). 14223 */ 14224 14225 *lundip = mptsas_find_child_phy(pdip, phy); 14226 if (*lundip != NULL) { 14227 return (DDI_SUCCESS); 14228 } 14229 14230 rval = mptsas_probe_lun(pdip, lun, lundip, ptgt); 14231 14232 return (rval); 14233 } 14234 14235 static int 14236 mptsas_retrieve_lundata(int lun_cnt, uint8_t *buf, uint16_t *lun_num, 14237 uint8_t *lun_addr_type) 14238 { 14239 uint32_t lun_idx = 0; 14240 14241 ASSERT(lun_num != NULL); 14242 ASSERT(lun_addr_type != NULL); 14243 14244 lun_idx = (lun_cnt + 1) * MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE; 14245 /* determine report luns addressing type */ 14246 switch (buf[lun_idx] & MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) { 14247 /* 14248 * Vendors in the field have been found to be concatenating 14249 * bus/target/lun to equal the complete lun value instead 14250 * of switching to flat space addressing 14251 */ 14252 /* 00b - peripheral device addressing method */ 14253 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL: 14254 /* FALLTHRU */ 14255 /* 10b - logical unit addressing method */ 14256 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT: 14257 /* FALLTHRU */ 14258 /* 01b - flat space addressing method */ 14259 case MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE: 14260 /* byte0 bit0-5=msb lun byte1 bit0-7=lsb lun */ 14261 *lun_addr_type = (buf[lun_idx] & 14262 MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK) >> 6; 14263 *lun_num = (buf[lun_idx] & 0x3F) << 8; 14264 *lun_num |= buf[lun_idx + 1]; 14265 return (DDI_SUCCESS); 14266 default: 14267 return (DDI_FAILURE); 14268 } 14269 } 14270 14271 static int 14272 mptsas_config_luns(dev_info_t *pdip, mptsas_target_t *ptgt) 14273 { 14274 struct buf *repluns_bp = NULL; 14275 struct scsi_address ap; 14276 uchar_t cdb[CDB_GROUP5]; 14277 int ret = DDI_FAILURE; 14278 int retry = 0; 14279 int lun_list_len = 0; 14280 uint16_t lun_num = 0; 14281 uint8_t lun_addr_type = 0; 14282 uint32_t lun_cnt = 0; 14283 uint32_t lun_total = 0; 14284 dev_info_t *cdip = NULL; 14285 uint16_t *saved_repluns = NULL; 14286 char *buffer = NULL; 14287 int buf_len = 128; 14288 mptsas_t *mpt = DIP2MPT(pdip); 14289 uint64_t sas_wwn = 0; 14290 uint8_t phy = 0xFF; 14291 uint32_t dev_info = 0; 14292 14293 mutex_enter(&mpt->m_mutex); 14294 sas_wwn = ptgt->m_addr.mta_wwn; 14295 phy = ptgt->m_phynum; 14296 dev_info = ptgt->m_deviceinfo; 14297 mutex_exit(&mpt->m_mutex); 14298 14299 if (sas_wwn == 0) { 14300 /* 14301 * It's a SATA without Device Name 14302 * So don't try multi-LUNs 14303 */ 14304 if (mptsas_find_child_phy(pdip, phy)) { 14305 return (DDI_SUCCESS); 14306 } else { 14307 /* 14308 * need configure and create node 14309 */ 14310 return (DDI_FAILURE); 14311 } 14312 } 14313 14314 /* 14315 * WWN (SAS address or Device Name exist) 14316 */ 14317 if (dev_info & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 14318 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 14319 /* 14320 * SATA device with Device Name 14321 * So don't try multi-LUNs 14322 */ 14323 if (mptsas_find_child_addr(pdip, sas_wwn, 0)) { 14324 return (DDI_SUCCESS); 14325 } else { 14326 return (DDI_FAILURE); 14327 } 14328 } 14329 14330 do { 14331 ap.a_target = MPTSAS_INVALID_DEVHDL; 14332 ap.a_lun = 0; 14333 ap.a_hba_tran = mpt->m_tran; 14334 repluns_bp = scsi_alloc_consistent_buf(&ap, 14335 (struct buf *)NULL, buf_len, B_READ, NULL_FUNC, NULL); 14336 if (repluns_bp == NULL) { 14337 retry++; 14338 continue; 14339 } 14340 bzero(cdb, CDB_GROUP5); 14341 cdb[0] = SCMD_REPORT_LUNS; 14342 cdb[6] = (buf_len & 0xff000000) >> 24; 14343 cdb[7] = (buf_len & 0x00ff0000) >> 16; 14344 cdb[8] = (buf_len & 0x0000ff00) >> 8; 14345 cdb[9] = (buf_len & 0x000000ff); 14346 14347 ret = mptsas_send_scsi_cmd(mpt, &ap, ptgt, &cdb[0], CDB_GROUP5, 14348 repluns_bp, NULL); 14349 if (ret != DDI_SUCCESS) { 14350 scsi_free_consistent_buf(repluns_bp); 14351 retry++; 14352 continue; 14353 } 14354 lun_list_len = BE_32(*(int *)((void *)( 14355 repluns_bp->b_un.b_addr))); 14356 if (buf_len >= lun_list_len + 8) { 14357 ret = DDI_SUCCESS; 14358 break; 14359 } 14360 scsi_free_consistent_buf(repluns_bp); 14361 buf_len = lun_list_len + 8; 14362 14363 } while (retry < 3); 14364 14365 if (ret != DDI_SUCCESS) 14366 return (ret); 14367 buffer = (char *)repluns_bp->b_un.b_addr; 14368 /* 14369 * find out the number of luns returned by the SCSI ReportLun call 14370 * and allocate buffer space 14371 */ 14372 lun_total = lun_list_len / MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE; 14373 saved_repluns = kmem_zalloc(sizeof (uint16_t) * lun_total, KM_SLEEP); 14374 if (saved_repluns == NULL) { 14375 scsi_free_consistent_buf(repluns_bp); 14376 return (DDI_FAILURE); 14377 } 14378 for (lun_cnt = 0; lun_cnt < lun_total; lun_cnt++) { 14379 if (mptsas_retrieve_lundata(lun_cnt, (uint8_t *)(buffer), 14380 &lun_num, &lun_addr_type) != DDI_SUCCESS) { 14381 continue; 14382 } 14383 saved_repluns[lun_cnt] = lun_num; 14384 if (cdip = mptsas_find_child_addr(pdip, sas_wwn, lun_num)) 14385 ret = DDI_SUCCESS; 14386 else 14387 ret = mptsas_probe_lun(pdip, lun_num, &cdip, 14388 ptgt); 14389 if ((ret == DDI_SUCCESS) && (cdip != NULL)) { 14390 (void) ndi_prop_remove(DDI_DEV_T_NONE, cdip, 14391 MPTSAS_DEV_GONE); 14392 } 14393 } 14394 mptsas_offline_missed_luns(pdip, saved_repluns, lun_total, ptgt); 14395 kmem_free(saved_repluns, sizeof (uint16_t) * lun_total); 14396 scsi_free_consistent_buf(repluns_bp); 14397 return (DDI_SUCCESS); 14398 } 14399 14400 static int 14401 mptsas_config_raid(dev_info_t *pdip, uint16_t target, dev_info_t **dip) 14402 { 14403 int rval = DDI_FAILURE; 14404 struct scsi_inquiry *sd_inq = NULL; 14405 mptsas_t *mpt = DIP2MPT(pdip); 14406 mptsas_target_t *ptgt = NULL; 14407 14408 mutex_enter(&mpt->m_mutex); 14409 ptgt = refhash_linear_search(mpt->m_targets, 14410 mptsas_target_eval_devhdl, &target); 14411 mutex_exit(&mpt->m_mutex); 14412 if (ptgt == NULL) { 14413 mptsas_log(mpt, CE_WARN, "Volume with VolDevHandle of 0x%x " 14414 "not found.", target); 14415 return (rval); 14416 } 14417 14418 sd_inq = (struct scsi_inquiry *)kmem_alloc(SUN_INQSIZE, KM_SLEEP); 14419 rval = mptsas_inquiry(mpt, ptgt, 0, 0, (uchar_t *)sd_inq, 14420 SUN_INQSIZE, 0, (uchar_t)0); 14421 14422 if ((rval == DDI_SUCCESS) && MPTSAS_VALID_LUN(sd_inq)) { 14423 rval = mptsas_create_phys_lun(pdip, sd_inq, NULL, dip, ptgt, 14424 0); 14425 } else { 14426 rval = DDI_FAILURE; 14427 } 14428 14429 kmem_free(sd_inq, SUN_INQSIZE); 14430 return (rval); 14431 } 14432 14433 /* 14434 * configure all RAID volumes for virtual iport 14435 */ 14436 static void 14437 mptsas_config_all_viport(dev_info_t *pdip) 14438 { 14439 mptsas_t *mpt = DIP2MPT(pdip); 14440 int config, vol; 14441 int target; 14442 dev_info_t *lundip = NULL; 14443 14444 /* 14445 * Get latest RAID info and search for any Volume DevHandles. If any 14446 * are found, configure the volume. 14447 */ 14448 mutex_enter(&mpt->m_mutex); 14449 for (config = 0; config < mpt->m_num_raid_configs; config++) { 14450 for (vol = 0; vol < MPTSAS_MAX_RAIDVOLS; vol++) { 14451 if (mpt->m_raidconfig[config].m_raidvol[vol].m_israid 14452 == 1) { 14453 target = mpt->m_raidconfig[config]. 14454 m_raidvol[vol].m_raidhandle; 14455 mutex_exit(&mpt->m_mutex); 14456 (void) mptsas_config_raid(pdip, target, 14457 &lundip); 14458 mutex_enter(&mpt->m_mutex); 14459 } 14460 } 14461 } 14462 mutex_exit(&mpt->m_mutex); 14463 } 14464 14465 static void 14466 mptsas_offline_missed_luns(dev_info_t *pdip, uint16_t *repluns, 14467 int lun_cnt, mptsas_target_t *ptgt) 14468 { 14469 dev_info_t *child = NULL, *savechild = NULL; 14470 mdi_pathinfo_t *pip = NULL, *savepip = NULL; 14471 uint64_t sas_wwn, wwid; 14472 uint8_t phy; 14473 int lun; 14474 int i; 14475 int find; 14476 char *addr; 14477 char *nodename; 14478 mptsas_t *mpt = DIP2MPT(pdip); 14479 14480 mutex_enter(&mpt->m_mutex); 14481 wwid = ptgt->m_addr.mta_wwn; 14482 mutex_exit(&mpt->m_mutex); 14483 14484 child = ddi_get_child(pdip); 14485 while (child) { 14486 find = 0; 14487 savechild = child; 14488 child = ddi_get_next_sibling(child); 14489 14490 nodename = ddi_node_name(savechild); 14491 if (strcmp(nodename, "smp") == 0) { 14492 continue; 14493 } 14494 14495 addr = ddi_get_name_addr(savechild); 14496 if (addr == NULL) { 14497 continue; 14498 } 14499 14500 if (mptsas_parse_address(addr, &sas_wwn, &phy, &lun) != 14501 DDI_SUCCESS) { 14502 continue; 14503 } 14504 14505 if (wwid == sas_wwn) { 14506 for (i = 0; i < lun_cnt; i++) { 14507 if (repluns[i] == lun) { 14508 find = 1; 14509 break; 14510 } 14511 } 14512 } else { 14513 continue; 14514 } 14515 if (find == 0) { 14516 /* 14517 * The lun has not been there already 14518 */ 14519 (void) mptsas_offline_lun(pdip, savechild, NULL, 14520 NDI_DEVI_REMOVE); 14521 } 14522 } 14523 14524 pip = mdi_get_next_client_path(pdip, NULL); 14525 while (pip) { 14526 find = 0; 14527 savepip = pip; 14528 addr = MDI_PI(pip)->pi_addr; 14529 14530 pip = mdi_get_next_client_path(pdip, pip); 14531 14532 if (addr == NULL) { 14533 continue; 14534 } 14535 14536 if (mptsas_parse_address(addr, &sas_wwn, &phy, 14537 &lun) != DDI_SUCCESS) { 14538 continue; 14539 } 14540 14541 if (sas_wwn == wwid) { 14542 for (i = 0; i < lun_cnt; i++) { 14543 if (repluns[i] == lun) { 14544 find = 1; 14545 break; 14546 } 14547 } 14548 } else { 14549 continue; 14550 } 14551 14552 if (find == 0) { 14553 /* 14554 * The lun has not been there already 14555 */ 14556 (void) mptsas_offline_lun(pdip, NULL, savepip, 14557 NDI_DEVI_REMOVE); 14558 } 14559 } 14560 } 14561 14562 /* 14563 * If this enclosure doesn't exist in the enclosure list, add it. If it does, 14564 * update it. 14565 */ 14566 static void 14567 mptsas_enclosure_update(mptsas_t *mpt, mptsas_enclosure_t *mep) 14568 { 14569 mptsas_enclosure_t *m; 14570 14571 ASSERT(MUTEX_HELD(&mpt->m_mutex)); 14572 m = mptsas_enc_lookup(mpt, mep->me_enchdl); 14573 if (m != NULL) { 14574 m->me_flags = mep->me_flags; 14575 return; 14576 } 14577 14578 m = kmem_zalloc(sizeof (*m), KM_SLEEP); 14579 m->me_enchdl = mep->me_enchdl; 14580 m->me_flags = mep->me_flags; 14581 list_insert_tail(&mpt->m_enclosures, m); 14582 } 14583 14584 static void 14585 mptsas_update_hashtab(struct mptsas *mpt) 14586 { 14587 uint32_t page_address; 14588 int rval = 0; 14589 uint16_t dev_handle; 14590 mptsas_target_t *ptgt = NULL; 14591 mptsas_smp_t smp_node; 14592 14593 /* 14594 * Get latest RAID info. 14595 */ 14596 (void) mptsas_get_raid_info(mpt); 14597 14598 dev_handle = mpt->m_smp_devhdl; 14599 while (mpt->m_done_traverse_smp == 0) { 14600 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL & 14601 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)dev_handle; 14602 if (mptsas_get_sas_expander_page0(mpt, page_address, &smp_node) 14603 != DDI_SUCCESS) { 14604 break; 14605 } 14606 mpt->m_smp_devhdl = dev_handle = smp_node.m_devhdl; 14607 (void) mptsas_smp_alloc(mpt, &smp_node); 14608 } 14609 14610 /* 14611 * Loop over enclosures so we can understand what's there. 14612 */ 14613 dev_handle = MPTSAS_INVALID_DEVHDL; 14614 while (mpt->m_done_traverse_enc == 0) { 14615 mptsas_enclosure_t me; 14616 14617 page_address = (MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE & 14618 MPI2_SAS_ENCLOS_PGAD_FORM_MASK) | (uint32_t)dev_handle; 14619 14620 if (mptsas_get_enclosure_page0(mpt, page_address, &me) != 14621 DDI_SUCCESS) { 14622 break; 14623 } 14624 dev_handle = me.me_enchdl; 14625 mptsas_enclosure_update(mpt, &me); 14626 } 14627 14628 /* 14629 * Config target devices 14630 */ 14631 dev_handle = mpt->m_dev_handle; 14632 14633 /* 14634 * Loop to get sas device page 0 by GetNextHandle till the 14635 * the last handle. If the sas device is a SATA/SSP target, 14636 * we try to config it. 14637 */ 14638 while (mpt->m_done_traverse_dev == 0) { 14639 ptgt = NULL; 14640 page_address = 14641 (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE & 14642 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 14643 (uint32_t)dev_handle; 14644 rval = mptsas_get_target_device_info(mpt, page_address, 14645 &dev_handle, &ptgt); 14646 if ((rval == DEV_INFO_FAIL_PAGE0) || 14647 (rval == DEV_INFO_FAIL_ALLOC) || 14648 (rval == DEV_INFO_FAIL_GUID)) { 14649 break; 14650 } 14651 14652 mpt->m_dev_handle = dev_handle; 14653 } 14654 14655 } 14656 14657 void 14658 mptsas_update_driver_data(struct mptsas *mpt) 14659 { 14660 mptsas_target_t *tp; 14661 mptsas_smp_t *sp; 14662 14663 ASSERT(MUTEX_HELD(&mpt->m_mutex)); 14664 14665 /* 14666 * TODO after hard reset, update the driver data structures 14667 * 1. update port/phymask mapping table mpt->m_phy_info 14668 * 2. invalid all the entries in hash table 14669 * m_devhdl = 0xffff and m_deviceinfo = 0 14670 * 3. call sas_device_page/expander_page to update hash table 14671 */ 14672 mptsas_update_phymask(mpt); 14673 14674 /* 14675 * Remove all the devhdls for existing entries but leave their 14676 * addresses alone. In update_hashtab() below, we'll find all 14677 * targets that are still present and reassociate them with 14678 * their potentially new devhdls. Leaving the targets around in 14679 * this fashion allows them to be used on the tx waitq even 14680 * while IOC reset is occurring. 14681 */ 14682 for (tp = refhash_first(mpt->m_targets); tp != NULL; 14683 tp = refhash_next(mpt->m_targets, tp)) { 14684 tp->m_devhdl = MPTSAS_INVALID_DEVHDL; 14685 tp->m_deviceinfo = 0; 14686 tp->m_dr_flag = MPTSAS_DR_INACTIVE; 14687 } 14688 for (sp = refhash_first(mpt->m_smp_targets); sp != NULL; 14689 sp = refhash_next(mpt->m_smp_targets, sp)) { 14690 sp->m_devhdl = MPTSAS_INVALID_DEVHDL; 14691 sp->m_deviceinfo = 0; 14692 } 14693 mpt->m_done_traverse_dev = 0; 14694 mpt->m_done_traverse_smp = 0; 14695 mpt->m_done_traverse_enc = 0; 14696 mpt->m_dev_handle = mpt->m_smp_devhdl = MPTSAS_INVALID_DEVHDL; 14697 mptsas_update_hashtab(mpt); 14698 } 14699 14700 static void 14701 mptsas_config_all(dev_info_t *pdip) 14702 { 14703 dev_info_t *smpdip = NULL; 14704 mptsas_t *mpt = DIP2MPT(pdip); 14705 int phymask = 0; 14706 mptsas_phymask_t phy_mask; 14707 mptsas_target_t *ptgt = NULL; 14708 mptsas_smp_t *psmp; 14709 14710 /* 14711 * Get the phymask associated to the iport 14712 */ 14713 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0, 14714 "phymask", 0); 14715 14716 /* 14717 * Enumerate RAID volumes here (phymask == 0). 14718 */ 14719 if (phymask == 0) { 14720 mptsas_config_all_viport(pdip); 14721 return; 14722 } 14723 14724 mutex_enter(&mpt->m_mutex); 14725 14726 if (!mpt->m_done_traverse_dev || !mpt->m_done_traverse_smp || 14727 !mpt->m_done_traverse_enc) { 14728 mptsas_update_hashtab(mpt); 14729 } 14730 14731 for (psmp = refhash_first(mpt->m_smp_targets); psmp != NULL; 14732 psmp = refhash_next(mpt->m_smp_targets, psmp)) { 14733 phy_mask = psmp->m_addr.mta_phymask; 14734 if (phy_mask == phymask) { 14735 smpdip = NULL; 14736 mutex_exit(&mpt->m_mutex); 14737 (void) mptsas_online_smp(pdip, psmp, &smpdip); 14738 mutex_enter(&mpt->m_mutex); 14739 } 14740 } 14741 14742 for (ptgt = refhash_first(mpt->m_targets); ptgt != NULL; 14743 ptgt = refhash_next(mpt->m_targets, ptgt)) { 14744 phy_mask = ptgt->m_addr.mta_phymask; 14745 if (phy_mask == phymask) { 14746 mutex_exit(&mpt->m_mutex); 14747 (void) mptsas_config_target(pdip, ptgt); 14748 mutex_enter(&mpt->m_mutex); 14749 } 14750 } 14751 mutex_exit(&mpt->m_mutex); 14752 } 14753 14754 static int 14755 mptsas_config_target(dev_info_t *pdip, mptsas_target_t *ptgt) 14756 { 14757 int rval = DDI_FAILURE; 14758 dev_info_t *tdip; 14759 14760 rval = mptsas_config_luns(pdip, ptgt); 14761 if (rval != DDI_SUCCESS) { 14762 /* 14763 * The return value means the SCMD_REPORT_LUNS 14764 * did not execute successfully. The target maybe 14765 * doesn't support such command. 14766 */ 14767 rval = mptsas_probe_lun(pdip, 0, &tdip, ptgt); 14768 } 14769 return (rval); 14770 } 14771 14772 /* 14773 * Return fail if not all the childs/paths are freed. 14774 * if there is any path under the HBA, the return value will be always fail 14775 * because we didn't call mdi_pi_free for path 14776 */ 14777 static int 14778 mptsas_offline_target(dev_info_t *pdip, char *name) 14779 { 14780 dev_info_t *child = NULL, *prechild = NULL; 14781 mdi_pathinfo_t *pip = NULL, *savepip = NULL; 14782 int tmp_rval, rval = DDI_SUCCESS; 14783 char *addr, *cp; 14784 size_t s; 14785 mptsas_t *mpt = DIP2MPT(pdip); 14786 14787 child = ddi_get_child(pdip); 14788 while (child) { 14789 addr = ddi_get_name_addr(child); 14790 prechild = child; 14791 child = ddi_get_next_sibling(child); 14792 14793 if (addr == NULL) { 14794 continue; 14795 } 14796 if ((cp = strchr(addr, ',')) == NULL) { 14797 continue; 14798 } 14799 14800 s = (uintptr_t)cp - (uintptr_t)addr; 14801 14802 if (strncmp(addr, name, s) != 0) { 14803 continue; 14804 } 14805 14806 tmp_rval = mptsas_offline_lun(pdip, prechild, NULL, 14807 NDI_DEVI_REMOVE); 14808 if (tmp_rval != DDI_SUCCESS) { 14809 rval = DDI_FAILURE; 14810 if (ndi_prop_create_boolean(DDI_DEV_T_NONE, 14811 prechild, MPTSAS_DEV_GONE) != 14812 DDI_PROP_SUCCESS) { 14813 mptsas_log(mpt, CE_WARN, "mptsas driver " 14814 "unable to create property for " 14815 "SAS %s (MPTSAS_DEV_GONE)", addr); 14816 } 14817 } 14818 } 14819 14820 pip = mdi_get_next_client_path(pdip, NULL); 14821 while (pip) { 14822 addr = MDI_PI(pip)->pi_addr; 14823 savepip = pip; 14824 pip = mdi_get_next_client_path(pdip, pip); 14825 if (addr == NULL) { 14826 continue; 14827 } 14828 14829 if ((cp = strchr(addr, ',')) == NULL) { 14830 continue; 14831 } 14832 14833 s = (uintptr_t)cp - (uintptr_t)addr; 14834 14835 if (strncmp(addr, name, s) != 0) { 14836 continue; 14837 } 14838 14839 (void) mptsas_offline_lun(pdip, NULL, savepip, 14840 NDI_DEVI_REMOVE); 14841 /* 14842 * driver will not invoke mdi_pi_free, so path will not 14843 * be freed forever, return DDI_FAILURE. 14844 */ 14845 rval = DDI_FAILURE; 14846 } 14847 return (rval); 14848 } 14849 14850 static int 14851 mptsas_offline_lun(dev_info_t *pdip, dev_info_t *rdip, 14852 mdi_pathinfo_t *rpip, uint_t flags) 14853 { 14854 int rval = DDI_FAILURE; 14855 char *devname; 14856 dev_info_t *cdip, *parent; 14857 14858 if (rpip != NULL) { 14859 parent = scsi_vhci_dip; 14860 cdip = mdi_pi_get_client(rpip); 14861 } else if (rdip != NULL) { 14862 parent = pdip; 14863 cdip = rdip; 14864 } else { 14865 return (DDI_FAILURE); 14866 } 14867 14868 /* 14869 * Make sure node is attached otherwise 14870 * it won't have related cache nodes to 14871 * clean up. i_ddi_devi_attached is 14872 * similiar to i_ddi_node_state(cdip) >= 14873 * DS_ATTACHED. 14874 */ 14875 if (i_ddi_devi_attached(cdip)) { 14876 14877 /* Get full devname */ 14878 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP); 14879 (void) ddi_deviname(cdip, devname); 14880 /* Clean cache */ 14881 (void) devfs_clean(parent, devname + 1, 14882 DV_CLEAN_FORCE); 14883 kmem_free(devname, MAXNAMELEN + 1); 14884 } 14885 if (rpip != NULL) { 14886 if (MDI_PI_IS_OFFLINE(rpip)) { 14887 rval = DDI_SUCCESS; 14888 } else { 14889 rval = mdi_pi_offline(rpip, 0); 14890 } 14891 } else { 14892 rval = ndi_devi_offline(cdip, flags); 14893 } 14894 14895 return (rval); 14896 } 14897 14898 static dev_info_t * 14899 mptsas_find_smp_child(dev_info_t *parent, char *str_wwn) 14900 { 14901 dev_info_t *child = NULL; 14902 char *smp_wwn = NULL; 14903 14904 child = ddi_get_child(parent); 14905 while (child) { 14906 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, child, 14907 DDI_PROP_DONTPASS, SMP_WWN, &smp_wwn) 14908 != DDI_SUCCESS) { 14909 child = ddi_get_next_sibling(child); 14910 continue; 14911 } 14912 14913 if (strcmp(smp_wwn, str_wwn) == 0) { 14914 ddi_prop_free(smp_wwn); 14915 break; 14916 } 14917 child = ddi_get_next_sibling(child); 14918 ddi_prop_free(smp_wwn); 14919 } 14920 return (child); 14921 } 14922 14923 static int 14924 mptsas_offline_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, uint_t flags) 14925 { 14926 int rval = DDI_FAILURE; 14927 char *devname; 14928 char wwn_str[MPTSAS_WWN_STRLEN]; 14929 dev_info_t *cdip; 14930 14931 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_addr.mta_wwn); 14932 14933 cdip = mptsas_find_smp_child(pdip, wwn_str); 14934 14935 if (cdip == NULL) 14936 return (DDI_SUCCESS); 14937 14938 /* 14939 * Make sure node is attached otherwise 14940 * it won't have related cache nodes to 14941 * clean up. i_ddi_devi_attached is 14942 * similiar to i_ddi_node_state(cdip) >= 14943 * DS_ATTACHED. 14944 */ 14945 if (i_ddi_devi_attached(cdip)) { 14946 14947 /* Get full devname */ 14948 devname = kmem_alloc(MAXNAMELEN + 1, KM_SLEEP); 14949 (void) ddi_deviname(cdip, devname); 14950 /* Clean cache */ 14951 (void) devfs_clean(pdip, devname + 1, 14952 DV_CLEAN_FORCE); 14953 kmem_free(devname, MAXNAMELEN + 1); 14954 } 14955 14956 rval = ndi_devi_offline(cdip, flags); 14957 14958 return (rval); 14959 } 14960 14961 static dev_info_t * 14962 mptsas_find_child(dev_info_t *pdip, char *name) 14963 { 14964 dev_info_t *child = NULL; 14965 char *rname = NULL; 14966 int rval = DDI_FAILURE; 14967 14968 rname = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 14969 14970 child = ddi_get_child(pdip); 14971 while (child) { 14972 rval = mptsas_name_child(child, rname, SCSI_MAXNAMELEN); 14973 if (rval != DDI_SUCCESS) { 14974 child = ddi_get_next_sibling(child); 14975 bzero(rname, SCSI_MAXNAMELEN); 14976 continue; 14977 } 14978 14979 if (strcmp(rname, name) == 0) { 14980 break; 14981 } 14982 child = ddi_get_next_sibling(child); 14983 bzero(rname, SCSI_MAXNAMELEN); 14984 } 14985 14986 kmem_free(rname, SCSI_MAXNAMELEN); 14987 14988 return (child); 14989 } 14990 14991 14992 static dev_info_t * 14993 mptsas_find_child_addr(dev_info_t *pdip, uint64_t sasaddr, int lun) 14994 { 14995 dev_info_t *child = NULL; 14996 char *name = NULL; 14997 char *addr = NULL; 14998 14999 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 15000 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 15001 (void) sprintf(name, "%016"PRIx64, sasaddr); 15002 (void) sprintf(addr, "w%s,%x", name, lun); 15003 child = mptsas_find_child(pdip, addr); 15004 kmem_free(name, SCSI_MAXNAMELEN); 15005 kmem_free(addr, SCSI_MAXNAMELEN); 15006 return (child); 15007 } 15008 15009 static dev_info_t * 15010 mptsas_find_child_phy(dev_info_t *pdip, uint8_t phy) 15011 { 15012 dev_info_t *child; 15013 char *addr; 15014 15015 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 15016 (void) sprintf(addr, "p%x,0", phy); 15017 child = mptsas_find_child(pdip, addr); 15018 kmem_free(addr, SCSI_MAXNAMELEN); 15019 return (child); 15020 } 15021 15022 static mdi_pathinfo_t * 15023 mptsas_find_path_phy(dev_info_t *pdip, uint8_t phy) 15024 { 15025 mdi_pathinfo_t *path; 15026 char *addr = NULL; 15027 15028 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 15029 (void) sprintf(addr, "p%x,0", phy); 15030 path = mdi_pi_find(pdip, NULL, addr); 15031 kmem_free(addr, SCSI_MAXNAMELEN); 15032 return (path); 15033 } 15034 15035 static mdi_pathinfo_t * 15036 mptsas_find_path_addr(dev_info_t *parent, uint64_t sasaddr, int lun) 15037 { 15038 mdi_pathinfo_t *path; 15039 char *name = NULL; 15040 char *addr = NULL; 15041 15042 name = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 15043 addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 15044 (void) sprintf(name, "%016"PRIx64, sasaddr); 15045 (void) sprintf(addr, "w%s,%x", name, lun); 15046 path = mdi_pi_find(parent, NULL, addr); 15047 kmem_free(name, SCSI_MAXNAMELEN); 15048 kmem_free(addr, SCSI_MAXNAMELEN); 15049 15050 return (path); 15051 } 15052 15053 static int 15054 mptsas_create_lun(dev_info_t *pdip, struct scsi_inquiry *sd_inq, 15055 dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun) 15056 { 15057 int i = 0; 15058 uchar_t *inq83 = NULL; 15059 int inq83_len1 = 0xFF; 15060 int inq83_len = 0; 15061 int rval = DDI_FAILURE; 15062 ddi_devid_t devid; 15063 char *guid = NULL; 15064 int target = ptgt->m_devhdl; 15065 mdi_pathinfo_t *pip = NULL; 15066 mptsas_t *mpt = DIP2MPT(pdip); 15067 15068 /* 15069 * For DVD/CD ROM and tape devices and optical 15070 * devices, we won't try to enumerate them under 15071 * scsi_vhci, so no need to try page83 15072 */ 15073 if (sd_inq && (sd_inq->inq_dtype == DTYPE_RODIRECT || 15074 sd_inq->inq_dtype == DTYPE_OPTICAL || 15075 sd_inq->inq_dtype == DTYPE_ESI)) 15076 goto create_lun; 15077 15078 /* 15079 * The LCA returns good SCSI status, but corrupt page 83 data the first 15080 * time it is queried. The solution is to keep trying to request page83 15081 * and verify the GUID is not (DDI_NOT_WELL_FORMED) in 15082 * mptsas_inq83_retry_timeout seconds. If the timeout expires, driver 15083 * give up to get VPD page at this stage and fail the enumeration. 15084 */ 15085 15086 inq83 = kmem_zalloc(inq83_len1, KM_SLEEP); 15087 15088 for (i = 0; i < mptsas_inq83_retry_timeout; i++) { 15089 rval = mptsas_inquiry(mpt, ptgt, lun, 0x83, inq83, 15090 inq83_len1, &inq83_len, 1); 15091 if (rval != 0) { 15092 mptsas_log(mpt, CE_WARN, "!mptsas request inquiry page " 15093 "0x83 for target:%x, lun:%x failed!", target, lun); 15094 if (mptsas_physical_bind_failed_page_83 != B_FALSE) 15095 goto create_lun; 15096 goto out; 15097 } 15098 /* 15099 * create DEVID from inquiry data 15100 */ 15101 if ((rval = ddi_devid_scsi_encode( 15102 DEVID_SCSI_ENCODE_VERSION_LATEST, NULL, (uchar_t *)sd_inq, 15103 sizeof (struct scsi_inquiry), NULL, 0, inq83, 15104 (size_t)inq83_len, &devid)) == DDI_SUCCESS) { 15105 /* 15106 * extract GUID from DEVID 15107 */ 15108 guid = ddi_devid_to_guid(devid); 15109 15110 /* 15111 * Do not enable MPXIO if the strlen(guid) is greater 15112 * than MPTSAS_MAX_GUID_LEN, this constrain would be 15113 * handled by framework later. 15114 */ 15115 if (guid && (strlen(guid) > MPTSAS_MAX_GUID_LEN)) { 15116 ddi_devid_free_guid(guid); 15117 guid = NULL; 15118 if (mpt->m_mpxio_enable == TRUE) { 15119 mptsas_log(mpt, CE_NOTE, "!Target:%x, " 15120 "lun:%x doesn't have a valid GUID, " 15121 "multipathing for this drive is " 15122 "not enabled", target, lun); 15123 } 15124 } 15125 15126 /* 15127 * devid no longer needed 15128 */ 15129 ddi_devid_free(devid); 15130 break; 15131 } else if (rval == DDI_NOT_WELL_FORMED) { 15132 /* 15133 * return value of ddi_devid_scsi_encode equal to 15134 * DDI_NOT_WELL_FORMED means DEVID_RETRY, it worth 15135 * to retry inquiry page 0x83 and get GUID. 15136 */ 15137 NDBG20(("Not well formed devid, retry...")); 15138 delay(1 * drv_usectohz(1000000)); 15139 continue; 15140 } else { 15141 mptsas_log(mpt, CE_WARN, "!Encode devid failed for " 15142 "path target:%x, lun:%x", target, lun); 15143 rval = DDI_FAILURE; 15144 goto create_lun; 15145 } 15146 } 15147 15148 if (i == mptsas_inq83_retry_timeout) { 15149 mptsas_log(mpt, CE_WARN, "!Repeated page83 requests timeout " 15150 "for path target:%x, lun:%x", target, lun); 15151 } 15152 15153 rval = DDI_FAILURE; 15154 15155 create_lun: 15156 if ((guid != NULL) && (mpt->m_mpxio_enable == TRUE)) { 15157 rval = mptsas_create_virt_lun(pdip, sd_inq, guid, lun_dip, &pip, 15158 ptgt, lun); 15159 } 15160 if (rval != DDI_SUCCESS) { 15161 rval = mptsas_create_phys_lun(pdip, sd_inq, guid, lun_dip, 15162 ptgt, lun); 15163 15164 } 15165 out: 15166 if (guid != NULL) { 15167 /* 15168 * guid no longer needed 15169 */ 15170 ddi_devid_free_guid(guid); 15171 } 15172 if (inq83 != NULL) 15173 kmem_free(inq83, inq83_len1); 15174 return (rval); 15175 } 15176 15177 static int 15178 mptsas_create_virt_lun(dev_info_t *pdip, struct scsi_inquiry *inq, char *guid, 15179 dev_info_t **lun_dip, mdi_pathinfo_t **pip, mptsas_target_t *ptgt, int lun) 15180 { 15181 int target; 15182 char *nodename = NULL; 15183 char **compatible = NULL; 15184 int ncompatible = 0; 15185 int mdi_rtn = MDI_FAILURE; 15186 int rval = DDI_FAILURE; 15187 char *old_guid = NULL; 15188 mptsas_t *mpt = DIP2MPT(pdip); 15189 char *lun_addr = NULL; 15190 char *wwn_str = NULL; 15191 char *attached_wwn_str = NULL; 15192 char *component = NULL; 15193 uint8_t phy = 0xFF; 15194 uint64_t sas_wwn; 15195 int64_t lun64 = 0; 15196 uint32_t devinfo; 15197 uint16_t dev_hdl; 15198 uint16_t pdev_hdl; 15199 uint64_t dev_sas_wwn; 15200 uint64_t pdev_sas_wwn; 15201 uint32_t pdev_info; 15202 uint8_t physport; 15203 uint8_t phy_id; 15204 uint32_t page_address; 15205 uint16_t bay_num, enclosure, io_flags; 15206 char pdev_wwn_str[MPTSAS_WWN_STRLEN]; 15207 uint32_t dev_info; 15208 15209 mutex_enter(&mpt->m_mutex); 15210 target = ptgt->m_devhdl; 15211 sas_wwn = ptgt->m_addr.mta_wwn; 15212 devinfo = ptgt->m_deviceinfo; 15213 phy = ptgt->m_phynum; 15214 mutex_exit(&mpt->m_mutex); 15215 15216 if (sas_wwn) { 15217 *pip = mptsas_find_path_addr(pdip, sas_wwn, lun); 15218 } else { 15219 *pip = mptsas_find_path_phy(pdip, phy); 15220 } 15221 15222 if (*pip != NULL) { 15223 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip; 15224 ASSERT(*lun_dip != NULL); 15225 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, *lun_dip, 15226 (DDI_PROP_DONTPASS | DDI_PROP_NOTPROM), 15227 MDI_CLIENT_GUID_PROP, &old_guid) == DDI_SUCCESS) { 15228 if (strncmp(guid, old_guid, strlen(guid)) == 0) { 15229 /* 15230 * Same path back online again. 15231 */ 15232 (void) ddi_prop_free(old_guid); 15233 if ((!MDI_PI_IS_ONLINE(*pip)) && 15234 (!MDI_PI_IS_STANDBY(*pip)) && 15235 (ptgt->m_tgt_unconfigured == 0)) { 15236 rval = mdi_pi_online(*pip, 0); 15237 mutex_enter(&mpt->m_mutex); 15238 ptgt->m_led_status = 0; 15239 (void) mptsas_flush_led_status(mpt, 15240 ptgt); 15241 mutex_exit(&mpt->m_mutex); 15242 } else { 15243 rval = DDI_SUCCESS; 15244 } 15245 if (rval != DDI_SUCCESS) { 15246 mptsas_log(mpt, CE_WARN, "path:target: " 15247 "%x, lun:%x online failed!", target, 15248 lun); 15249 *pip = NULL; 15250 *lun_dip = NULL; 15251 } 15252 return (rval); 15253 } else { 15254 /* 15255 * The GUID of the LUN has changed which maybe 15256 * because customer mapped another volume to the 15257 * same LUN. 15258 */ 15259 mptsas_log(mpt, CE_WARN, "The GUID of the " 15260 "target:%x, lun:%x was changed, maybe " 15261 "because someone mapped another volume " 15262 "to the same LUN", target, lun); 15263 (void) ddi_prop_free(old_guid); 15264 if (!MDI_PI_IS_OFFLINE(*pip)) { 15265 rval = mdi_pi_offline(*pip, 0); 15266 if (rval != MDI_SUCCESS) { 15267 mptsas_log(mpt, CE_WARN, "path:" 15268 "target:%x, lun:%x offline " 15269 "failed!", target, lun); 15270 *pip = NULL; 15271 *lun_dip = NULL; 15272 return (DDI_FAILURE); 15273 } 15274 } 15275 if (mdi_pi_free(*pip, 0) != MDI_SUCCESS) { 15276 mptsas_log(mpt, CE_WARN, "path:target:" 15277 "%x, lun:%x free failed!", target, 15278 lun); 15279 *pip = NULL; 15280 *lun_dip = NULL; 15281 return (DDI_FAILURE); 15282 } 15283 } 15284 } else { 15285 mptsas_log(mpt, CE_WARN, "Can't get client-guid " 15286 "property for path:target:%x, lun:%x", target, lun); 15287 *pip = NULL; 15288 *lun_dip = NULL; 15289 return (DDI_FAILURE); 15290 } 15291 } 15292 scsi_hba_nodename_compatible_get(inq, NULL, 15293 inq->inq_dtype, NULL, &nodename, &compatible, &ncompatible); 15294 15295 /* 15296 * if nodename can't be determined then print a message and skip it 15297 */ 15298 if (nodename == NULL) { 15299 mptsas_log(mpt, CE_WARN, "mptsas driver found no compatible " 15300 "driver for target%d lun %d dtype:0x%02x", target, lun, 15301 inq->inq_dtype); 15302 return (DDI_FAILURE); 15303 } 15304 15305 wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP); 15306 /* The property is needed by MPAPI */ 15307 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn); 15308 15309 lun_addr = kmem_zalloc(SCSI_MAXNAMELEN, KM_SLEEP); 15310 if (guid) { 15311 (void) sprintf(lun_addr, "w%s,%x", wwn_str, lun); 15312 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn); 15313 } else { 15314 (void) sprintf(lun_addr, "p%x,%x", phy, lun); 15315 (void) sprintf(wwn_str, "p%x", phy); 15316 } 15317 15318 mdi_rtn = mdi_pi_alloc_compatible(pdip, nodename, 15319 guid, lun_addr, compatible, ncompatible, 15320 0, pip); 15321 if (mdi_rtn == MDI_SUCCESS) { 15322 15323 if (mdi_prop_update_string(*pip, MDI_GUID, 15324 guid) != DDI_SUCCESS) { 15325 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 15326 "create prop for target %d lun %d (MDI_GUID)", 15327 target, lun); 15328 mdi_rtn = MDI_FAILURE; 15329 goto virt_create_done; 15330 } 15331 15332 if (mdi_prop_update_int(*pip, LUN_PROP, 15333 lun) != DDI_SUCCESS) { 15334 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 15335 "create prop for target %d lun %d (LUN_PROP)", 15336 target, lun); 15337 mdi_rtn = MDI_FAILURE; 15338 goto virt_create_done; 15339 } 15340 lun64 = (int64_t)lun; 15341 if (mdi_prop_update_int64(*pip, LUN64_PROP, 15342 lun64) != DDI_SUCCESS) { 15343 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 15344 "create prop for target %d (LUN64_PROP)", 15345 target); 15346 mdi_rtn = MDI_FAILURE; 15347 goto virt_create_done; 15348 } 15349 if (mdi_prop_update_string_array(*pip, "compatible", 15350 compatible, ncompatible) != 15351 DDI_PROP_SUCCESS) { 15352 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 15353 "create prop for target %d lun %d (COMPATIBLE)", 15354 target, lun); 15355 mdi_rtn = MDI_FAILURE; 15356 goto virt_create_done; 15357 } 15358 if (sas_wwn && (mdi_prop_update_string(*pip, 15359 SCSI_ADDR_PROP_TARGET_PORT, wwn_str) != DDI_PROP_SUCCESS)) { 15360 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 15361 "create prop for target %d lun %d " 15362 "(target-port)", target, lun); 15363 mdi_rtn = MDI_FAILURE; 15364 goto virt_create_done; 15365 } else if ((sas_wwn == 0) && (mdi_prop_update_int(*pip, 15366 "sata-phy", phy) != DDI_PROP_SUCCESS)) { 15367 /* 15368 * Direct attached SATA device without DeviceName 15369 */ 15370 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 15371 "create prop for SAS target %d lun %d " 15372 "(sata-phy)", target, lun); 15373 mdi_rtn = MDI_FAILURE; 15374 goto virt_create_done; 15375 } 15376 mutex_enter(&mpt->m_mutex); 15377 15378 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 15379 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 15380 (uint32_t)ptgt->m_devhdl; 15381 rval = mptsas_get_sas_device_page0(mpt, page_address, 15382 &dev_hdl, &dev_sas_wwn, &dev_info, &physport, 15383 &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags); 15384 if (rval != DDI_SUCCESS) { 15385 mutex_exit(&mpt->m_mutex); 15386 mptsas_log(mpt, CE_WARN, "mptsas unable to get " 15387 "parent device for handle %d", page_address); 15388 mdi_rtn = MDI_FAILURE; 15389 goto virt_create_done; 15390 } 15391 15392 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 15393 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl; 15394 rval = mptsas_get_sas_device_page0(mpt, page_address, 15395 &dev_hdl, &pdev_sas_wwn, &pdev_info, &physport, 15396 &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags); 15397 if (rval != DDI_SUCCESS) { 15398 mutex_exit(&mpt->m_mutex); 15399 mptsas_log(mpt, CE_WARN, "mptsas unable to get" 15400 "device info for handle %d", page_address); 15401 mdi_rtn = MDI_FAILURE; 15402 goto virt_create_done; 15403 } 15404 15405 mutex_exit(&mpt->m_mutex); 15406 15407 /* 15408 * If this device direct attached to the controller 15409 * set the attached-port to the base wwid 15410 */ 15411 if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) 15412 != DEVINFO_DIRECT_ATTACHED) { 15413 (void) sprintf(pdev_wwn_str, "w%016"PRIx64, 15414 pdev_sas_wwn); 15415 } else { 15416 /* 15417 * Update the iport's attached-port to guid 15418 */ 15419 if (sas_wwn == 0) { 15420 (void) sprintf(wwn_str, "p%x", phy); 15421 } else { 15422 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn); 15423 } 15424 if (ddi_prop_update_string(DDI_DEV_T_NONE, 15425 pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) != 15426 DDI_PROP_SUCCESS) { 15427 mptsas_log(mpt, CE_WARN, 15428 "mptsas unable to create " 15429 "property for iport target-port" 15430 " %s (sas_wwn)", 15431 wwn_str); 15432 mdi_rtn = MDI_FAILURE; 15433 goto virt_create_done; 15434 } 15435 15436 (void) sprintf(pdev_wwn_str, "w%016"PRIx64, 15437 mpt->un.m_base_wwid); 15438 } 15439 15440 if (mdi_prop_update_string(*pip, 15441 SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) != 15442 DDI_PROP_SUCCESS) { 15443 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 15444 "property for iport attached-port %s (sas_wwn)", 15445 attached_wwn_str); 15446 mdi_rtn = MDI_FAILURE; 15447 goto virt_create_done; 15448 } 15449 15450 15451 if (inq->inq_dtype == 0) { 15452 component = kmem_zalloc(MAXPATHLEN, KM_SLEEP); 15453 /* 15454 * set obp path for pathinfo 15455 */ 15456 (void) snprintf(component, MAXPATHLEN, 15457 "disk@%s", lun_addr); 15458 15459 if (mdi_pi_pathname_obp_set(*pip, component) != 15460 DDI_SUCCESS) { 15461 mptsas_log(mpt, CE_WARN, "mpt_sas driver " 15462 "unable to set obp-path for object %s", 15463 component); 15464 mdi_rtn = MDI_FAILURE; 15465 goto virt_create_done; 15466 } 15467 } 15468 15469 *lun_dip = MDI_PI(*pip)->pi_client->ct_dip; 15470 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 15471 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 15472 if ((ndi_prop_update_int(DDI_DEV_T_NONE, *lun_dip, 15473 "pm-capable", 1)) != 15474 DDI_PROP_SUCCESS) { 15475 mptsas_log(mpt, CE_WARN, "mptsas driver" 15476 "failed to create pm-capable " 15477 "property, target %d", target); 15478 mdi_rtn = MDI_FAILURE; 15479 goto virt_create_done; 15480 } 15481 } 15482 /* 15483 * Create the phy-num property 15484 */ 15485 if (mdi_prop_update_int(*pip, "phy-num", 15486 ptgt->m_phynum) != DDI_SUCCESS) { 15487 mptsas_log(mpt, CE_WARN, "mptsas driver unable to " 15488 "create phy-num property for target %d lun %d", 15489 target, lun); 15490 mdi_rtn = MDI_FAILURE; 15491 goto virt_create_done; 15492 } 15493 NDBG20(("new path:%s onlining,", MDI_PI(*pip)->pi_addr)); 15494 mdi_rtn = mdi_pi_online(*pip, 0); 15495 if (mdi_rtn == MDI_SUCCESS) { 15496 mutex_enter(&mpt->m_mutex); 15497 ptgt->m_led_status = 0; 15498 (void) mptsas_flush_led_status(mpt, ptgt); 15499 mutex_exit(&mpt->m_mutex); 15500 } 15501 if (mdi_rtn == MDI_NOT_SUPPORTED) { 15502 mdi_rtn = MDI_FAILURE; 15503 } 15504 virt_create_done: 15505 if (*pip && mdi_rtn != MDI_SUCCESS) { 15506 (void) mdi_pi_free(*pip, 0); 15507 *pip = NULL; 15508 *lun_dip = NULL; 15509 } 15510 } 15511 15512 scsi_hba_nodename_compatible_free(nodename, compatible); 15513 if (lun_addr != NULL) { 15514 kmem_free(lun_addr, SCSI_MAXNAMELEN); 15515 } 15516 if (wwn_str != NULL) { 15517 kmem_free(wwn_str, MPTSAS_WWN_STRLEN); 15518 } 15519 if (component != NULL) { 15520 kmem_free(component, MAXPATHLEN); 15521 } 15522 15523 return ((mdi_rtn == MDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE); 15524 } 15525 15526 static int 15527 mptsas_create_phys_lun(dev_info_t *pdip, struct scsi_inquiry *inq, 15528 char *guid, dev_info_t **lun_dip, mptsas_target_t *ptgt, int lun) 15529 { 15530 int target; 15531 int rval; 15532 int ndi_rtn = NDI_FAILURE; 15533 uint64_t be_sas_wwn; 15534 char *nodename = NULL; 15535 char **compatible = NULL; 15536 int ncompatible = 0; 15537 int instance = 0; 15538 mptsas_t *mpt = DIP2MPT(pdip); 15539 char *wwn_str = NULL; 15540 char *component = NULL; 15541 char *attached_wwn_str = NULL; 15542 uint8_t phy = 0xFF; 15543 uint64_t sas_wwn; 15544 uint32_t devinfo; 15545 uint16_t dev_hdl; 15546 uint16_t pdev_hdl; 15547 uint64_t pdev_sas_wwn; 15548 uint64_t dev_sas_wwn; 15549 uint32_t pdev_info; 15550 uint8_t physport; 15551 uint8_t phy_id; 15552 uint32_t page_address; 15553 uint16_t bay_num, enclosure, io_flags; 15554 char pdev_wwn_str[MPTSAS_WWN_STRLEN]; 15555 uint32_t dev_info; 15556 int64_t lun64 = 0; 15557 15558 mutex_enter(&mpt->m_mutex); 15559 target = ptgt->m_devhdl; 15560 sas_wwn = ptgt->m_addr.mta_wwn; 15561 devinfo = ptgt->m_deviceinfo; 15562 phy = ptgt->m_phynum; 15563 mutex_exit(&mpt->m_mutex); 15564 15565 /* 15566 * generate compatible property with binding-set "mpt" 15567 */ 15568 scsi_hba_nodename_compatible_get(inq, NULL, inq->inq_dtype, NULL, 15569 &nodename, &compatible, &ncompatible); 15570 15571 /* 15572 * if nodename can't be determined then print a message and skip it 15573 */ 15574 if (nodename == NULL) { 15575 mptsas_log(mpt, CE_WARN, "mptsas found no compatible driver " 15576 "for target %d lun %d", target, lun); 15577 return (DDI_FAILURE); 15578 } 15579 15580 ndi_rtn = ndi_devi_alloc(pdip, nodename, 15581 DEVI_SID_NODEID, lun_dip); 15582 15583 /* 15584 * if lun alloc success, set props 15585 */ 15586 if (ndi_rtn == NDI_SUCCESS) { 15587 15588 if (ndi_prop_update_int(DDI_DEV_T_NONE, 15589 *lun_dip, LUN_PROP, lun) != 15590 DDI_PROP_SUCCESS) { 15591 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 15592 "property for target %d lun %d (LUN_PROP)", 15593 target, lun); 15594 ndi_rtn = NDI_FAILURE; 15595 goto phys_create_done; 15596 } 15597 15598 lun64 = (int64_t)lun; 15599 if (ndi_prop_update_int64(DDI_DEV_T_NONE, 15600 *lun_dip, LUN64_PROP, lun64) != 15601 DDI_PROP_SUCCESS) { 15602 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 15603 "property for target %d lun64 %d (LUN64_PROP)", 15604 target, lun); 15605 ndi_rtn = NDI_FAILURE; 15606 goto phys_create_done; 15607 } 15608 if (ndi_prop_update_string_array(DDI_DEV_T_NONE, 15609 *lun_dip, "compatible", compatible, ncompatible) 15610 != DDI_PROP_SUCCESS) { 15611 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 15612 "property for target %d lun %d (COMPATIBLE)", 15613 target, lun); 15614 ndi_rtn = NDI_FAILURE; 15615 goto phys_create_done; 15616 } 15617 15618 /* 15619 * We need the SAS WWN for non-multipath devices, so 15620 * we'll use the same property as that multipathing 15621 * devices need to present for MPAPI. If we don't have 15622 * a WWN (e.g. parallel SCSI), don't create the prop. 15623 */ 15624 wwn_str = kmem_zalloc(MPTSAS_WWN_STRLEN, KM_SLEEP); 15625 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn); 15626 if (sas_wwn && ndi_prop_update_string(DDI_DEV_T_NONE, 15627 *lun_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str) 15628 != DDI_PROP_SUCCESS) { 15629 mptsas_log(mpt, CE_WARN, "mptsas unable to " 15630 "create property for SAS target %d lun %d " 15631 "(target-port)", target, lun); 15632 ndi_rtn = NDI_FAILURE; 15633 goto phys_create_done; 15634 } 15635 15636 be_sas_wwn = BE_64(sas_wwn); 15637 if (sas_wwn && ndi_prop_update_byte_array( 15638 DDI_DEV_T_NONE, *lun_dip, "port-wwn", 15639 (uchar_t *)&be_sas_wwn, 8) != DDI_PROP_SUCCESS) { 15640 mptsas_log(mpt, CE_WARN, "mptsas unable to " 15641 "create property for SAS target %d lun %d " 15642 "(port-wwn)", target, lun); 15643 ndi_rtn = NDI_FAILURE; 15644 goto phys_create_done; 15645 } else if ((sas_wwn == 0) && (ndi_prop_update_int( 15646 DDI_DEV_T_NONE, *lun_dip, "sata-phy", phy) != 15647 DDI_PROP_SUCCESS)) { 15648 /* 15649 * Direct attached SATA device without DeviceName 15650 */ 15651 mptsas_log(mpt, CE_WARN, "mptsas unable to " 15652 "create property for SAS target %d lun %d " 15653 "(sata-phy)", target, lun); 15654 ndi_rtn = NDI_FAILURE; 15655 goto phys_create_done; 15656 } 15657 15658 if (ndi_prop_create_boolean(DDI_DEV_T_NONE, 15659 *lun_dip, SAS_PROP) != DDI_PROP_SUCCESS) { 15660 mptsas_log(mpt, CE_WARN, "mptsas unable to" 15661 "create property for SAS target %d lun %d" 15662 " (SAS_PROP)", target, lun); 15663 ndi_rtn = NDI_FAILURE; 15664 goto phys_create_done; 15665 } 15666 if (guid && (ndi_prop_update_string(DDI_DEV_T_NONE, 15667 *lun_dip, NDI_GUID, guid) != DDI_SUCCESS)) { 15668 mptsas_log(mpt, CE_WARN, "mptsas unable " 15669 "to create guid property for target %d " 15670 "lun %d", target, lun); 15671 ndi_rtn = NDI_FAILURE; 15672 goto phys_create_done; 15673 } 15674 15675 /* 15676 * The following code is to set properties for SM-HBA support, 15677 * it doesn't apply to RAID volumes 15678 */ 15679 if (ptgt->m_addr.mta_phymask == 0) 15680 goto phys_raid_lun; 15681 15682 mutex_enter(&mpt->m_mutex); 15683 15684 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 15685 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 15686 (uint32_t)ptgt->m_devhdl; 15687 rval = mptsas_get_sas_device_page0(mpt, page_address, 15688 &dev_hdl, &dev_sas_wwn, &dev_info, 15689 &physport, &phy_id, &pdev_hdl, 15690 &bay_num, &enclosure, &io_flags); 15691 if (rval != DDI_SUCCESS) { 15692 mutex_exit(&mpt->m_mutex); 15693 mptsas_log(mpt, CE_WARN, "mptsas unable to get" 15694 "parent device for handle %d.", page_address); 15695 ndi_rtn = NDI_FAILURE; 15696 goto phys_create_done; 15697 } 15698 15699 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 15700 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)pdev_hdl; 15701 rval = mptsas_get_sas_device_page0(mpt, page_address, 15702 &dev_hdl, &pdev_sas_wwn, &pdev_info, &physport, 15703 &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags); 15704 if (rval != DDI_SUCCESS) { 15705 mutex_exit(&mpt->m_mutex); 15706 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 15707 "device for handle %d.", page_address); 15708 ndi_rtn = NDI_FAILURE; 15709 goto phys_create_done; 15710 } 15711 15712 mutex_exit(&mpt->m_mutex); 15713 15714 /* 15715 * If this device direct attached to the controller 15716 * set the attached-port to the base wwid 15717 */ 15718 if ((ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) 15719 != DEVINFO_DIRECT_ATTACHED) { 15720 (void) sprintf(pdev_wwn_str, "w%016"PRIx64, 15721 pdev_sas_wwn); 15722 } else { 15723 /* 15724 * Update the iport's attached-port to guid 15725 */ 15726 if (sas_wwn == 0) { 15727 (void) sprintf(wwn_str, "p%x", phy); 15728 } else { 15729 (void) sprintf(wwn_str, "w%016"PRIx64, sas_wwn); 15730 } 15731 if (ddi_prop_update_string(DDI_DEV_T_NONE, 15732 pdip, SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) != 15733 DDI_PROP_SUCCESS) { 15734 mptsas_log(mpt, CE_WARN, 15735 "mptsas unable to create " 15736 "property for iport target-port" 15737 " %s (sas_wwn)", 15738 wwn_str); 15739 ndi_rtn = NDI_FAILURE; 15740 goto phys_create_done; 15741 } 15742 15743 (void) sprintf(pdev_wwn_str, "w%016"PRIx64, 15744 mpt->un.m_base_wwid); 15745 } 15746 15747 if (ndi_prop_update_string(DDI_DEV_T_NONE, 15748 *lun_dip, SCSI_ADDR_PROP_ATTACHED_PORT, pdev_wwn_str) != 15749 DDI_PROP_SUCCESS) { 15750 mptsas_log(mpt, CE_WARN, 15751 "mptsas unable to create " 15752 "property for iport attached-port %s (sas_wwn)", 15753 attached_wwn_str); 15754 ndi_rtn = NDI_FAILURE; 15755 goto phys_create_done; 15756 } 15757 15758 if (IS_SATA_DEVICE(dev_info)) { 15759 if (ndi_prop_update_string(DDI_DEV_T_NONE, 15760 *lun_dip, MPTSAS_VARIANT, "sata") != 15761 DDI_PROP_SUCCESS) { 15762 mptsas_log(mpt, CE_WARN, 15763 "mptsas unable to create " 15764 "property for device variant "); 15765 ndi_rtn = NDI_FAILURE; 15766 goto phys_create_done; 15767 } 15768 } 15769 15770 if (IS_ATAPI_DEVICE(dev_info)) { 15771 if (ndi_prop_update_string(DDI_DEV_T_NONE, 15772 *lun_dip, MPTSAS_VARIANT, "atapi") != 15773 DDI_PROP_SUCCESS) { 15774 mptsas_log(mpt, CE_WARN, 15775 "mptsas unable to create " 15776 "property for device variant "); 15777 ndi_rtn = NDI_FAILURE; 15778 goto phys_create_done; 15779 } 15780 } 15781 15782 phys_raid_lun: 15783 /* 15784 * if this is a SAS controller, and the target is a SATA 15785 * drive, set the 'pm-capable' property for sd and if on 15786 * an OPL platform, also check if this is an ATAPI 15787 * device. 15788 */ 15789 instance = ddi_get_instance(mpt->m_dip); 15790 if (devinfo & (MPI2_SAS_DEVICE_INFO_SATA_DEVICE | 15791 MPI2_SAS_DEVICE_INFO_ATAPI_DEVICE)) { 15792 NDBG2(("mptsas%d: creating pm-capable property, " 15793 "target %d", instance, target)); 15794 15795 if ((ndi_prop_update_int(DDI_DEV_T_NONE, 15796 *lun_dip, "pm-capable", 1)) != 15797 DDI_PROP_SUCCESS) { 15798 mptsas_log(mpt, CE_WARN, "mptsas " 15799 "failed to create pm-capable " 15800 "property, target %d", target); 15801 ndi_rtn = NDI_FAILURE; 15802 goto phys_create_done; 15803 } 15804 15805 } 15806 15807 if ((inq->inq_dtype == 0) || (inq->inq_dtype == 5)) { 15808 /* 15809 * add 'obp-path' properties for devinfo 15810 */ 15811 bzero(wwn_str, sizeof (wwn_str)); 15812 (void) sprintf(wwn_str, "%016"PRIx64, sas_wwn); 15813 component = kmem_zalloc(MAXPATHLEN, KM_SLEEP); 15814 if (guid) { 15815 (void) snprintf(component, MAXPATHLEN, 15816 "disk@w%s,%x", wwn_str, lun); 15817 } else { 15818 (void) snprintf(component, MAXPATHLEN, 15819 "disk@p%x,%x", phy, lun); 15820 } 15821 if (ddi_pathname_obp_set(*lun_dip, component) 15822 != DDI_SUCCESS) { 15823 mptsas_log(mpt, CE_WARN, "mpt_sas driver " 15824 "unable to set obp-path for SAS " 15825 "object %s", component); 15826 ndi_rtn = NDI_FAILURE; 15827 goto phys_create_done; 15828 } 15829 } 15830 /* 15831 * Create the phy-num property for non-raid disk 15832 */ 15833 if (ptgt->m_addr.mta_phymask != 0) { 15834 if (ndi_prop_update_int(DDI_DEV_T_NONE, 15835 *lun_dip, "phy-num", ptgt->m_phynum) != 15836 DDI_PROP_SUCCESS) { 15837 mptsas_log(mpt, CE_WARN, "mptsas driver " 15838 "failed to create phy-num property for " 15839 "target %d", target); 15840 ndi_rtn = NDI_FAILURE; 15841 goto phys_create_done; 15842 } 15843 } 15844 phys_create_done: 15845 /* 15846 * If props were setup ok, online the lun 15847 */ 15848 if (ndi_rtn == NDI_SUCCESS) { 15849 /* 15850 * Try to online the new node 15851 */ 15852 ndi_rtn = ndi_devi_online(*lun_dip, NDI_ONLINE_ATTACH); 15853 } 15854 if (ndi_rtn == NDI_SUCCESS) { 15855 mutex_enter(&mpt->m_mutex); 15856 ptgt->m_led_status = 0; 15857 (void) mptsas_flush_led_status(mpt, ptgt); 15858 mutex_exit(&mpt->m_mutex); 15859 } 15860 15861 /* 15862 * If success set rtn flag, else unwire alloc'd lun 15863 */ 15864 if (ndi_rtn != NDI_SUCCESS) { 15865 NDBG12(("mptsas driver unable to online " 15866 "target %d lun %d", target, lun)); 15867 ndi_prop_remove_all(*lun_dip); 15868 (void) ndi_devi_free(*lun_dip); 15869 *lun_dip = NULL; 15870 } 15871 } 15872 15873 scsi_hba_nodename_compatible_free(nodename, compatible); 15874 15875 if (wwn_str != NULL) { 15876 kmem_free(wwn_str, MPTSAS_WWN_STRLEN); 15877 } 15878 if (component != NULL) { 15879 kmem_free(component, MAXPATHLEN); 15880 } 15881 15882 15883 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE); 15884 } 15885 15886 static int 15887 mptsas_probe_smp(dev_info_t *pdip, uint64_t wwn) 15888 { 15889 mptsas_t *mpt = DIP2MPT(pdip); 15890 struct smp_device smp_sd; 15891 15892 /* XXX An HBA driver should not be allocating an smp_device. */ 15893 bzero(&smp_sd, sizeof (struct smp_device)); 15894 smp_sd.smp_sd_address.smp_a_hba_tran = mpt->m_smptran; 15895 bcopy(&wwn, smp_sd.smp_sd_address.smp_a_wwn, SAS_WWN_BYTE_SIZE); 15896 15897 if (smp_probe(&smp_sd) != DDI_PROBE_SUCCESS) 15898 return (NDI_FAILURE); 15899 return (NDI_SUCCESS); 15900 } 15901 15902 static int 15903 mptsas_config_smp(dev_info_t *pdip, uint64_t sas_wwn, dev_info_t **smp_dip) 15904 { 15905 mptsas_t *mpt = DIP2MPT(pdip); 15906 mptsas_smp_t *psmp = NULL; 15907 int rval; 15908 int phymask; 15909 15910 /* 15911 * Get the physical port associated to the iport 15912 * PHYMASK TODO 15913 */ 15914 phymask = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 0, 15915 "phymask", 0); 15916 /* 15917 * Find the smp node in hash table with specified sas address and 15918 * physical port 15919 */ 15920 psmp = mptsas_wwid_to_psmp(mpt, phymask, sas_wwn); 15921 if (psmp == NULL) { 15922 return (DDI_FAILURE); 15923 } 15924 15925 rval = mptsas_online_smp(pdip, psmp, smp_dip); 15926 15927 return (rval); 15928 } 15929 15930 static int 15931 mptsas_online_smp(dev_info_t *pdip, mptsas_smp_t *smp_node, 15932 dev_info_t **smp_dip) 15933 { 15934 char wwn_str[MPTSAS_WWN_STRLEN]; 15935 char attached_wwn_str[MPTSAS_WWN_STRLEN]; 15936 int ndi_rtn = NDI_FAILURE; 15937 int rval = 0; 15938 mptsas_smp_t dev_info; 15939 uint32_t page_address; 15940 mptsas_t *mpt = DIP2MPT(pdip); 15941 uint16_t dev_hdl; 15942 uint64_t sas_wwn; 15943 uint64_t smp_sas_wwn; 15944 uint8_t physport; 15945 uint8_t phy_id; 15946 uint16_t pdev_hdl; 15947 uint8_t numphys = 0; 15948 uint16_t i = 0; 15949 char phymask[MPTSAS_MAX_PHYS]; 15950 char *iport = NULL; 15951 mptsas_phymask_t phy_mask = 0; 15952 uint16_t attached_devhdl; 15953 uint16_t bay_num, enclosure, io_flags; 15954 15955 (void) sprintf(wwn_str, "%"PRIx64, smp_node->m_addr.mta_wwn); 15956 15957 /* 15958 * Probe smp device, prevent the node of removed device from being 15959 * configured succesfully 15960 */ 15961 if (mptsas_probe_smp(pdip, smp_node->m_addr.mta_wwn) != NDI_SUCCESS) { 15962 return (DDI_FAILURE); 15963 } 15964 15965 if ((*smp_dip = mptsas_find_smp_child(pdip, wwn_str)) != NULL) { 15966 return (DDI_SUCCESS); 15967 } 15968 15969 ndi_rtn = ndi_devi_alloc(pdip, "smp", DEVI_SID_NODEID, smp_dip); 15970 15971 /* 15972 * if lun alloc success, set props 15973 */ 15974 if (ndi_rtn == NDI_SUCCESS) { 15975 /* 15976 * Set the flavor of the child to be SMP flavored 15977 */ 15978 ndi_flavor_set(*smp_dip, SCSA_FLAVOR_SMP); 15979 15980 if (ndi_prop_update_string(DDI_DEV_T_NONE, 15981 *smp_dip, SMP_WWN, wwn_str) != 15982 DDI_PROP_SUCCESS) { 15983 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 15984 "property for smp device %s (sas_wwn)", 15985 wwn_str); 15986 ndi_rtn = NDI_FAILURE; 15987 goto smp_create_done; 15988 } 15989 (void) sprintf(wwn_str, "w%"PRIx64, smp_node->m_addr.mta_wwn); 15990 if (ndi_prop_update_string(DDI_DEV_T_NONE, 15991 *smp_dip, SCSI_ADDR_PROP_TARGET_PORT, wwn_str) != 15992 DDI_PROP_SUCCESS) { 15993 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 15994 "property for iport target-port %s (sas_wwn)", 15995 wwn_str); 15996 ndi_rtn = NDI_FAILURE; 15997 goto smp_create_done; 15998 } 15999 16000 mutex_enter(&mpt->m_mutex); 16001 16002 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_HNDL & 16003 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | smp_node->m_devhdl; 16004 rval = mptsas_get_sas_expander_page0(mpt, page_address, 16005 &dev_info); 16006 if (rval != DDI_SUCCESS) { 16007 mutex_exit(&mpt->m_mutex); 16008 mptsas_log(mpt, CE_WARN, 16009 "mptsas unable to get expander " 16010 "parent device info for %x", page_address); 16011 ndi_rtn = NDI_FAILURE; 16012 goto smp_create_done; 16013 } 16014 16015 smp_node->m_pdevhdl = dev_info.m_pdevhdl; 16016 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 16017 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 16018 (uint32_t)dev_info.m_pdevhdl; 16019 rval = mptsas_get_sas_device_page0(mpt, page_address, 16020 &dev_hdl, &sas_wwn, &smp_node->m_pdevinfo, &physport, 16021 &phy_id, &pdev_hdl, &bay_num, &enclosure, &io_flags); 16022 if (rval != DDI_SUCCESS) { 16023 mutex_exit(&mpt->m_mutex); 16024 mptsas_log(mpt, CE_WARN, "mptsas unable to get " 16025 "device info for %x", page_address); 16026 ndi_rtn = NDI_FAILURE; 16027 goto smp_create_done; 16028 } 16029 16030 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_HANDLE & 16031 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | 16032 (uint32_t)dev_info.m_devhdl; 16033 rval = mptsas_get_sas_device_page0(mpt, page_address, 16034 &dev_hdl, &smp_sas_wwn, &smp_node->m_deviceinfo, 16035 &physport, &phy_id, &pdev_hdl, &bay_num, &enclosure, 16036 &io_flags); 16037 if (rval != DDI_SUCCESS) { 16038 mutex_exit(&mpt->m_mutex); 16039 mptsas_log(mpt, CE_WARN, "mptsas unable to get " 16040 "device info for %x", page_address); 16041 ndi_rtn = NDI_FAILURE; 16042 goto smp_create_done; 16043 } 16044 mutex_exit(&mpt->m_mutex); 16045 16046 /* 16047 * If this smp direct attached to the controller 16048 * set the attached-port to the base wwid 16049 */ 16050 if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) 16051 != DEVINFO_DIRECT_ATTACHED) { 16052 (void) sprintf(attached_wwn_str, "w%016"PRIx64, 16053 sas_wwn); 16054 } else { 16055 (void) sprintf(attached_wwn_str, "w%016"PRIx64, 16056 mpt->un.m_base_wwid); 16057 } 16058 16059 if (ndi_prop_update_string(DDI_DEV_T_NONE, 16060 *smp_dip, SCSI_ADDR_PROP_ATTACHED_PORT, attached_wwn_str) != 16061 DDI_PROP_SUCCESS) { 16062 mptsas_log(mpt, CE_WARN, "mptsas unable to create " 16063 "property for smp attached-port %s (sas_wwn)", 16064 attached_wwn_str); 16065 ndi_rtn = NDI_FAILURE; 16066 goto smp_create_done; 16067 } 16068 16069 if (ndi_prop_create_boolean(DDI_DEV_T_NONE, 16070 *smp_dip, SMP_PROP) != DDI_PROP_SUCCESS) { 16071 mptsas_log(mpt, CE_WARN, "mptsas unable to " 16072 "create property for SMP %s (SMP_PROP) ", 16073 wwn_str); 16074 ndi_rtn = NDI_FAILURE; 16075 goto smp_create_done; 16076 } 16077 16078 /* 16079 * check the smp to see whether it direct 16080 * attached to the controller 16081 */ 16082 if ((smp_node->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) 16083 != DEVINFO_DIRECT_ATTACHED) { 16084 goto smp_create_done; 16085 } 16086 numphys = ddi_prop_get_int(DDI_DEV_T_ANY, pdip, 16087 DDI_PROP_DONTPASS, MPTSAS_NUM_PHYS, -1); 16088 if (numphys > 0) { 16089 goto smp_create_done; 16090 } 16091 /* 16092 * this iport is an old iport, we need to 16093 * reconfig the props for it. 16094 */ 16095 if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip, 16096 MPTSAS_VIRTUAL_PORT, 0) != 16097 DDI_PROP_SUCCESS) { 16098 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip, 16099 MPTSAS_VIRTUAL_PORT); 16100 mptsas_log(mpt, CE_WARN, "mptsas virtual port " 16101 "prop update failed"); 16102 goto smp_create_done; 16103 } 16104 16105 mutex_enter(&mpt->m_mutex); 16106 numphys = 0; 16107 iport = ddi_get_name_addr(pdip); 16108 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 16109 bzero(phymask, sizeof (phymask)); 16110 (void) sprintf(phymask, 16111 "%x", mpt->m_phy_info[i].phy_mask); 16112 if (strcmp(phymask, iport) == 0) { 16113 phy_mask = mpt->m_phy_info[i].phy_mask; 16114 break; 16115 } 16116 } 16117 16118 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 16119 if ((phy_mask >> i) & 0x01) { 16120 numphys++; 16121 } 16122 } 16123 /* 16124 * Update PHY info for smhba 16125 */ 16126 if (mptsas_smhba_phy_init(mpt)) { 16127 mutex_exit(&mpt->m_mutex); 16128 mptsas_log(mpt, CE_WARN, "mptsas phy update " 16129 "failed"); 16130 goto smp_create_done; 16131 } 16132 mutex_exit(&mpt->m_mutex); 16133 16134 mptsas_smhba_set_all_phy_props(mpt, pdip, numphys, phy_mask, 16135 &attached_devhdl); 16136 16137 if (ddi_prop_update_int(DDI_DEV_T_NONE, pdip, 16138 MPTSAS_NUM_PHYS, numphys) != 16139 DDI_PROP_SUCCESS) { 16140 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip, 16141 MPTSAS_NUM_PHYS); 16142 mptsas_log(mpt, CE_WARN, "mptsas update " 16143 "num phys props failed"); 16144 goto smp_create_done; 16145 } 16146 /* 16147 * Add parent's props for SMHBA support 16148 */ 16149 if (ddi_prop_update_string(DDI_DEV_T_NONE, pdip, 16150 SCSI_ADDR_PROP_ATTACHED_PORT, wwn_str) != 16151 DDI_PROP_SUCCESS) { 16152 (void) ddi_prop_remove(DDI_DEV_T_NONE, pdip, 16153 SCSI_ADDR_PROP_ATTACHED_PORT); 16154 mptsas_log(mpt, CE_WARN, "mptsas update iport" 16155 "attached-port failed"); 16156 goto smp_create_done; 16157 } 16158 16159 smp_create_done: 16160 /* 16161 * If props were setup ok, online the lun 16162 */ 16163 if (ndi_rtn == NDI_SUCCESS) { 16164 /* 16165 * Try to online the new node 16166 */ 16167 ndi_rtn = ndi_devi_online(*smp_dip, NDI_ONLINE_ATTACH); 16168 } 16169 16170 /* 16171 * If success set rtn flag, else unwire alloc'd lun 16172 */ 16173 if (ndi_rtn != NDI_SUCCESS) { 16174 NDBG12(("mptsas unable to online " 16175 "SMP target %s", wwn_str)); 16176 ndi_prop_remove_all(*smp_dip); 16177 (void) ndi_devi_free(*smp_dip); 16178 } 16179 } 16180 16181 return ((ndi_rtn == NDI_SUCCESS) ? DDI_SUCCESS : DDI_FAILURE); 16182 } 16183 16184 /* smp transport routine */ 16185 static int mptsas_smp_start(struct smp_pkt *smp_pkt) 16186 { 16187 uint64_t wwn; 16188 Mpi2SmpPassthroughRequest_t req; 16189 Mpi2SmpPassthroughReply_t rep; 16190 uint32_t direction = 0; 16191 mptsas_t *mpt; 16192 int ret; 16193 uint64_t tmp64; 16194 16195 mpt = (mptsas_t *)smp_pkt->smp_pkt_address-> 16196 smp_a_hba_tran->smp_tran_hba_private; 16197 16198 bcopy(smp_pkt->smp_pkt_address->smp_a_wwn, &wwn, SAS_WWN_BYTE_SIZE); 16199 /* 16200 * Need to compose a SMP request message 16201 * and call mptsas_do_passthru() function 16202 */ 16203 bzero(&req, sizeof (req)); 16204 bzero(&rep, sizeof (rep)); 16205 req.PassthroughFlags = 0; 16206 req.PhysicalPort = 0xff; 16207 req.ChainOffset = 0; 16208 req.Function = MPI2_FUNCTION_SMP_PASSTHROUGH; 16209 16210 if ((smp_pkt->smp_pkt_reqsize & 0xffff0000ul) != 0) { 16211 smp_pkt->smp_pkt_reason = ERANGE; 16212 return (DDI_FAILURE); 16213 } 16214 req.RequestDataLength = LE_16((uint16_t)(smp_pkt->smp_pkt_reqsize - 4)); 16215 16216 req.MsgFlags = 0; 16217 tmp64 = LE_64(wwn); 16218 bcopy(&tmp64, &req.SASAddress, SAS_WWN_BYTE_SIZE); 16219 if (smp_pkt->smp_pkt_rspsize > 0) { 16220 direction |= MPTSAS_PASS_THRU_DIRECTION_READ; 16221 } 16222 if (smp_pkt->smp_pkt_reqsize > 0) { 16223 direction |= MPTSAS_PASS_THRU_DIRECTION_WRITE; 16224 } 16225 16226 mutex_enter(&mpt->m_mutex); 16227 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, 16228 (uint8_t *)smp_pkt->smp_pkt_rsp, 16229 offsetof(Mpi2SmpPassthroughRequest_t, SGL), sizeof (rep), 16230 smp_pkt->smp_pkt_rspsize - 4, direction, 16231 (uint8_t *)smp_pkt->smp_pkt_req, smp_pkt->smp_pkt_reqsize - 4, 16232 smp_pkt->smp_pkt_timeout, FKIOCTL); 16233 mutex_exit(&mpt->m_mutex); 16234 if (ret != 0) { 16235 cmn_err(CE_WARN, "smp_start do passthru error %d", ret); 16236 smp_pkt->smp_pkt_reason = (uchar_t)(ret); 16237 return (DDI_FAILURE); 16238 } 16239 /* do passthrough success, check the smp status */ 16240 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) { 16241 switch (LE_16(rep.IOCStatus)) { 16242 case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE: 16243 smp_pkt->smp_pkt_reason = ENODEV; 16244 break; 16245 case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN: 16246 smp_pkt->smp_pkt_reason = EOVERFLOW; 16247 break; 16248 case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED: 16249 smp_pkt->smp_pkt_reason = EIO; 16250 break; 16251 default: 16252 mptsas_log(mpt, CE_NOTE, "smp_start: get unknown ioc" 16253 "status:%x", LE_16(rep.IOCStatus)); 16254 smp_pkt->smp_pkt_reason = EIO; 16255 break; 16256 } 16257 return (DDI_FAILURE); 16258 } 16259 if (rep.SASStatus != MPI2_SASSTATUS_SUCCESS) { 16260 mptsas_log(mpt, CE_NOTE, "smp_start: get error SAS status:%x", 16261 rep.SASStatus); 16262 smp_pkt->smp_pkt_reason = EIO; 16263 return (DDI_FAILURE); 16264 } 16265 16266 return (DDI_SUCCESS); 16267 } 16268 16269 /* 16270 * If we didn't get a match, we need to get sas page0 for each device, and 16271 * untill we get a match. If failed, return NULL 16272 */ 16273 static mptsas_target_t * 16274 mptsas_phy_to_tgt(mptsas_t *mpt, mptsas_phymask_t phymask, uint8_t phy) 16275 { 16276 int i, j = 0; 16277 int rval = 0; 16278 uint16_t cur_handle; 16279 uint32_t page_address; 16280 mptsas_target_t *ptgt = NULL; 16281 16282 /* 16283 * PHY named device must be direct attached and attaches to 16284 * narrow port, if the iport is not parent of the device which 16285 * we are looking for. 16286 */ 16287 for (i = 0; i < MPTSAS_MAX_PHYS; i++) { 16288 if ((1 << i) & phymask) 16289 j++; 16290 } 16291 16292 if (j > 1) 16293 return (NULL); 16294 16295 /* 16296 * Must be a narrow port and single device attached to the narrow port 16297 * So the physical port num of device which is equal to the iport's 16298 * port num is the device what we are looking for. 16299 */ 16300 16301 if (mpt->m_phy_info[phy].phy_mask != phymask) 16302 return (NULL); 16303 16304 mutex_enter(&mpt->m_mutex); 16305 16306 ptgt = refhash_linear_search(mpt->m_targets, mptsas_target_eval_nowwn, 16307 &phy); 16308 if (ptgt != NULL) { 16309 mutex_exit(&mpt->m_mutex); 16310 return (ptgt); 16311 } 16312 16313 if (mpt->m_done_traverse_dev) { 16314 mutex_exit(&mpt->m_mutex); 16315 return (NULL); 16316 } 16317 16318 /* If didn't get a match, come here */ 16319 cur_handle = mpt->m_dev_handle; 16320 for (; ; ) { 16321 ptgt = NULL; 16322 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE & 16323 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | (uint32_t)cur_handle; 16324 rval = mptsas_get_target_device_info(mpt, page_address, 16325 &cur_handle, &ptgt); 16326 if ((rval == DEV_INFO_FAIL_PAGE0) || 16327 (rval == DEV_INFO_FAIL_ALLOC) || 16328 (rval == DEV_INFO_FAIL_GUID)) { 16329 break; 16330 } 16331 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) || 16332 (rval == DEV_INFO_PHYS_DISK)) { 16333 continue; 16334 } 16335 mpt->m_dev_handle = cur_handle; 16336 16337 if ((ptgt->m_addr.mta_wwn == 0) && (ptgt->m_phynum == phy)) { 16338 break; 16339 } 16340 } 16341 16342 mutex_exit(&mpt->m_mutex); 16343 return (ptgt); 16344 } 16345 16346 /* 16347 * The ptgt->m_addr.mta_wwn contains the wwid for each disk. 16348 * For Raid volumes, we need to check m_raidvol[x].m_raidwwid 16349 * If we didn't get a match, we need to get sas page0 for each device, and 16350 * untill we get a match 16351 * If failed, return NULL 16352 */ 16353 static mptsas_target_t * 16354 mptsas_wwid_to_ptgt(mptsas_t *mpt, mptsas_phymask_t phymask, uint64_t wwid) 16355 { 16356 int rval = 0; 16357 uint16_t cur_handle; 16358 uint32_t page_address; 16359 mptsas_target_t *tmp_tgt = NULL; 16360 mptsas_target_addr_t addr; 16361 16362 addr.mta_wwn = wwid; 16363 addr.mta_phymask = phymask; 16364 mutex_enter(&mpt->m_mutex); 16365 tmp_tgt = refhash_lookup(mpt->m_targets, &addr); 16366 if (tmp_tgt != NULL) { 16367 mutex_exit(&mpt->m_mutex); 16368 return (tmp_tgt); 16369 } 16370 16371 if (phymask == 0) { 16372 /* 16373 * It's IR volume 16374 */ 16375 rval = mptsas_get_raid_info(mpt); 16376 if (rval) { 16377 tmp_tgt = refhash_lookup(mpt->m_targets, &addr); 16378 } 16379 mutex_exit(&mpt->m_mutex); 16380 return (tmp_tgt); 16381 } 16382 16383 if (mpt->m_done_traverse_dev) { 16384 mutex_exit(&mpt->m_mutex); 16385 return (NULL); 16386 } 16387 16388 /* If didn't get a match, come here */ 16389 cur_handle = mpt->m_dev_handle; 16390 for (;;) { 16391 tmp_tgt = NULL; 16392 page_address = (MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE & 16393 MPI2_SAS_DEVICE_PGAD_FORM_MASK) | cur_handle; 16394 rval = mptsas_get_target_device_info(mpt, page_address, 16395 &cur_handle, &tmp_tgt); 16396 if ((rval == DEV_INFO_FAIL_PAGE0) || 16397 (rval == DEV_INFO_FAIL_ALLOC) || 16398 (rval == DEV_INFO_FAIL_GUID)) { 16399 tmp_tgt = NULL; 16400 break; 16401 } 16402 if ((rval == DEV_INFO_WRONG_DEVICE_TYPE) || 16403 (rval == DEV_INFO_PHYS_DISK)) { 16404 continue; 16405 } 16406 mpt->m_dev_handle = cur_handle; 16407 if ((tmp_tgt->m_addr.mta_wwn) && 16408 (tmp_tgt->m_addr.mta_wwn == wwid) && 16409 (tmp_tgt->m_addr.mta_phymask == phymask)) { 16410 break; 16411 } 16412 } 16413 16414 mutex_exit(&mpt->m_mutex); 16415 return (tmp_tgt); 16416 } 16417 16418 static mptsas_smp_t * 16419 mptsas_wwid_to_psmp(mptsas_t *mpt, mptsas_phymask_t phymask, uint64_t wwid) 16420 { 16421 int rval = 0; 16422 uint16_t cur_handle; 16423 uint32_t page_address; 16424 mptsas_smp_t smp_node, *psmp = NULL; 16425 mptsas_target_addr_t addr; 16426 16427 addr.mta_wwn = wwid; 16428 addr.mta_phymask = phymask; 16429 mutex_enter(&mpt->m_mutex); 16430 psmp = refhash_lookup(mpt->m_smp_targets, &addr); 16431 if (psmp != NULL) { 16432 mutex_exit(&mpt->m_mutex); 16433 return (psmp); 16434 } 16435 16436 if (mpt->m_done_traverse_smp) { 16437 mutex_exit(&mpt->m_mutex); 16438 return (NULL); 16439 } 16440 16441 /* If didn't get a match, come here */ 16442 cur_handle = mpt->m_smp_devhdl; 16443 for (;;) { 16444 psmp = NULL; 16445 page_address = (MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL & 16446 MPI2_SAS_EXPAND_PGAD_FORM_MASK) | (uint32_t)cur_handle; 16447 rval = mptsas_get_sas_expander_page0(mpt, page_address, 16448 &smp_node); 16449 if (rval != DDI_SUCCESS) { 16450 break; 16451 } 16452 mpt->m_smp_devhdl = cur_handle = smp_node.m_devhdl; 16453 psmp = mptsas_smp_alloc(mpt, &smp_node); 16454 ASSERT(psmp); 16455 if ((psmp->m_addr.mta_wwn) && (psmp->m_addr.mta_wwn == wwid) && 16456 (psmp->m_addr.mta_phymask == phymask)) { 16457 break; 16458 } 16459 } 16460 16461 mutex_exit(&mpt->m_mutex); 16462 return (psmp); 16463 } 16464 16465 mptsas_target_t * 16466 mptsas_tgt_alloc(refhash_t *refhash, uint16_t devhdl, uint64_t wwid, 16467 uint32_t devinfo, mptsas_phymask_t phymask, uint8_t phynum) 16468 { 16469 mptsas_target_t *tmp_tgt = NULL; 16470 mptsas_target_addr_t addr; 16471 16472 addr.mta_wwn = wwid; 16473 addr.mta_phymask = phymask; 16474 tmp_tgt = refhash_lookup(refhash, &addr); 16475 if (tmp_tgt != NULL) { 16476 NDBG20(("Hash item already exist")); 16477 tmp_tgt->m_deviceinfo = devinfo; 16478 tmp_tgt->m_devhdl = devhdl; /* XXX - duplicate? */ 16479 return (tmp_tgt); 16480 } 16481 tmp_tgt = kmem_zalloc(sizeof (struct mptsas_target), KM_SLEEP); 16482 if (tmp_tgt == NULL) { 16483 cmn_err(CE_WARN, "Fatal, allocated tgt failed"); 16484 return (NULL); 16485 } 16486 tmp_tgt->m_devhdl = devhdl; 16487 tmp_tgt->m_addr.mta_wwn = wwid; 16488 tmp_tgt->m_deviceinfo = devinfo; 16489 tmp_tgt->m_addr.mta_phymask = phymask; 16490 tmp_tgt->m_phynum = phynum; 16491 /* Initialized the tgt structure */ 16492 tmp_tgt->m_qfull_retries = QFULL_RETRIES; 16493 tmp_tgt->m_qfull_retry_interval = 16494 drv_usectohz(QFULL_RETRY_INTERVAL * 1000); 16495 tmp_tgt->m_t_throttle = MAX_THROTTLE; 16496 TAILQ_INIT(&tmp_tgt->m_active_cmdq); 16497 16498 refhash_insert(refhash, tmp_tgt); 16499 16500 return (tmp_tgt); 16501 } 16502 16503 static void 16504 mptsas_smp_target_copy(mptsas_smp_t *src, mptsas_smp_t *dst) 16505 { 16506 dst->m_devhdl = src->m_devhdl; 16507 dst->m_deviceinfo = src->m_deviceinfo; 16508 dst->m_pdevhdl = src->m_pdevhdl; 16509 dst->m_pdevinfo = src->m_pdevinfo; 16510 } 16511 16512 static mptsas_smp_t * 16513 mptsas_smp_alloc(mptsas_t *mpt, mptsas_smp_t *data) 16514 { 16515 mptsas_target_addr_t addr; 16516 mptsas_smp_t *ret_data; 16517 16518 addr.mta_wwn = data->m_addr.mta_wwn; 16519 addr.mta_phymask = data->m_addr.mta_phymask; 16520 ret_data = refhash_lookup(mpt->m_smp_targets, &addr); 16521 /* 16522 * If there's already a matching SMP target, update its fields 16523 * in place. Since the address is not changing, it's safe to do 16524 * this. We cannot just bcopy() here because the structure we've 16525 * been given has invalid hash links. 16526 */ 16527 if (ret_data != NULL) { 16528 mptsas_smp_target_copy(data, ret_data); 16529 return (ret_data); 16530 } 16531 16532 ret_data = kmem_alloc(sizeof (mptsas_smp_t), KM_SLEEP); 16533 bcopy(data, ret_data, sizeof (mptsas_smp_t)); 16534 refhash_insert(mpt->m_smp_targets, ret_data); 16535 return (ret_data); 16536 } 16537 16538 /* 16539 * Functions for SGPIO LED support 16540 */ 16541 static dev_info_t * 16542 mptsas_get_dip_from_dev(dev_t dev, mptsas_phymask_t *phymask) 16543 { 16544 dev_info_t *dip; 16545 int prop; 16546 dip = e_ddi_hold_devi_by_dev(dev, 0); 16547 if (dip == NULL) 16548 return (dip); 16549 prop = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 0, 16550 "phymask", 0); 16551 *phymask = (mptsas_phymask_t)prop; 16552 ddi_release_devi(dip); 16553 return (dip); 16554 } 16555 static mptsas_target_t * 16556 mptsas_addr_to_ptgt(mptsas_t *mpt, char *addr, mptsas_phymask_t phymask) 16557 { 16558 uint8_t phynum; 16559 uint64_t wwn; 16560 int lun; 16561 mptsas_target_t *ptgt = NULL; 16562 16563 if (mptsas_parse_address(addr, &wwn, &phynum, &lun) != DDI_SUCCESS) { 16564 return (NULL); 16565 } 16566 if (addr[0] == 'w') { 16567 ptgt = mptsas_wwid_to_ptgt(mpt, (int)phymask, wwn); 16568 } else { 16569 ptgt = mptsas_phy_to_tgt(mpt, (int)phymask, phynum); 16570 } 16571 return (ptgt); 16572 } 16573 16574 static int 16575 mptsas_flush_led_status(mptsas_t *mpt, mptsas_target_t *ptgt) 16576 { 16577 uint32_t slotstatus = 0; 16578 16579 /* Build an MPI2 Slot Status based on our view of the world */ 16580 if (ptgt->m_led_status & (1 << (MPTSAS_LEDCTL_LED_IDENT - 1))) 16581 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_IDENTIFY_REQUEST; 16582 if (ptgt->m_led_status & (1 << (MPTSAS_LEDCTL_LED_FAIL - 1))) 16583 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_PREDICTED_FAULT; 16584 if (ptgt->m_led_status & (1 << (MPTSAS_LEDCTL_LED_OK2RM - 1))) 16585 slotstatus |= MPI2_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE; 16586 16587 /* Write it to the controller */ 16588 NDBG14(("mptsas_ioctl: set LED status %x for slot %x", 16589 slotstatus, ptgt->m_slot_num)); 16590 return (mptsas_send_sep(mpt, ptgt, &slotstatus, 16591 MPI2_SEP_REQ_ACTION_WRITE_STATUS)); 16592 } 16593 16594 /* 16595 * send sep request, use enclosure/slot addressing 16596 */ 16597 static int 16598 mptsas_send_sep(mptsas_t *mpt, mptsas_target_t *ptgt, 16599 uint32_t *status, uint8_t act) 16600 { 16601 Mpi2SepRequest_t req; 16602 Mpi2SepReply_t rep; 16603 int ret; 16604 mptsas_enclosure_t *mep; 16605 uint16_t enctype; 16606 16607 ASSERT(mutex_owned(&mpt->m_mutex)); 16608 16609 /* 16610 * We only support SEP control of directly-attached targets, in which 16611 * case the "SEP" we're talking to is a virtual one contained within 16612 * the HBA itself. This is necessary because DA targets typically have 16613 * no other mechanism for LED control. Targets for which a separate 16614 * enclosure service processor exists should be controlled via ses(7d) 16615 * or sgen(7d). Furthermore, since such requests can time out, they 16616 * should be made in user context rather than in response to 16617 * asynchronous fabric changes. 16618 * 16619 * In addition, we do not support this operation for RAID volumes, 16620 * since there is no slot associated with them. 16621 */ 16622 if (!(ptgt->m_deviceinfo & DEVINFO_DIRECT_ATTACHED) || 16623 ptgt->m_addr.mta_phymask == 0) { 16624 return (ENOTTY); 16625 } 16626 16627 /* 16628 * Look through the enclosures and make sure that this enclosure is 16629 * something that is directly attached device. If we didn't find an 16630 * enclosure for this device, don't send the ioctl. 16631 */ 16632 mep = mptsas_enc_lookup(mpt, ptgt->m_enclosure); 16633 if (mep == NULL) 16634 return (ENOTTY); 16635 enctype = mep->me_flags & MPI2_SAS_ENCLS0_FLAGS_MNG_MASK; 16636 if (enctype != MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES && 16637 enctype != MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO && 16638 enctype != MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO) { 16639 return (ENOTTY); 16640 } 16641 16642 bzero(&req, sizeof (req)); 16643 bzero(&rep, sizeof (rep)); 16644 16645 req.Function = MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR; 16646 req.Action = act; 16647 req.Flags = MPI2_SEP_REQ_FLAGS_ENCLOSURE_SLOT_ADDRESS; 16648 req.EnclosureHandle = LE_16(ptgt->m_enclosure); 16649 req.Slot = LE_16(ptgt->m_slot_num); 16650 if (act == MPI2_SEP_REQ_ACTION_WRITE_STATUS) { 16651 req.SlotStatus = LE_32(*status); 16652 } 16653 ret = mptsas_do_passthru(mpt, (uint8_t *)&req, (uint8_t *)&rep, NULL, 16654 sizeof (req), sizeof (rep), NULL, 0, NULL, 0, 60, FKIOCTL); 16655 if (ret != 0) { 16656 mptsas_log(mpt, CE_NOTE, "mptsas_send_sep: passthru SEP " 16657 "Processor Request message error %d", ret); 16658 return (ret); 16659 } 16660 /* do passthrough success, check the ioc status */ 16661 if (LE_16(rep.IOCStatus) != MPI2_IOCSTATUS_SUCCESS) { 16662 mptsas_log(mpt, CE_NOTE, "send_sep act %x: ioc " 16663 "status:%x loginfo %x", act, LE_16(rep.IOCStatus), 16664 LE_32(rep.IOCLogInfo)); 16665 switch (LE_16(rep.IOCStatus) & MPI2_IOCSTATUS_MASK) { 16666 case MPI2_IOCSTATUS_INVALID_FUNCTION: 16667 case MPI2_IOCSTATUS_INVALID_VPID: 16668 case MPI2_IOCSTATUS_INVALID_FIELD: 16669 case MPI2_IOCSTATUS_INVALID_STATE: 16670 case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED: 16671 case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION: 16672 case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE: 16673 case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE: 16674 case MPI2_IOCSTATUS_CONFIG_INVALID_DATA: 16675 case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS: 16676 return (EINVAL); 16677 case MPI2_IOCSTATUS_BUSY: 16678 return (EBUSY); 16679 case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES: 16680 return (EAGAIN); 16681 case MPI2_IOCSTATUS_INVALID_SGL: 16682 case MPI2_IOCSTATUS_INTERNAL_ERROR: 16683 case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT: 16684 default: 16685 return (EIO); 16686 } 16687 } 16688 if (act != MPI2_SEP_REQ_ACTION_WRITE_STATUS) { 16689 *status = LE_32(rep.SlotStatus); 16690 } 16691 16692 return (0); 16693 } 16694 16695 int 16696 mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr, 16697 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp, 16698 uint32_t alloc_size, ddi_dma_cookie_t *cookiep) 16699 { 16700 ddi_dma_cookie_t new_cookie; 16701 size_t alloc_len; 16702 uint_t ncookie; 16703 16704 if (cookiep == NULL) 16705 cookiep = &new_cookie; 16706 16707 if (ddi_dma_alloc_handle(mpt->m_dip, &dma_attr, DDI_DMA_SLEEP, 16708 NULL, dma_hdp) != DDI_SUCCESS) { 16709 return (FALSE); 16710 } 16711 16712 if (ddi_dma_mem_alloc(*dma_hdp, alloc_size, &mpt->m_dev_acc_attr, 16713 DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL, dma_memp, &alloc_len, 16714 acc_hdp) != DDI_SUCCESS) { 16715 ddi_dma_free_handle(dma_hdp); 16716 *dma_hdp = NULL; 16717 return (FALSE); 16718 } 16719 16720 if (ddi_dma_addr_bind_handle(*dma_hdp, NULL, *dma_memp, alloc_len, 16721 (DDI_DMA_RDWR | DDI_DMA_CONSISTENT), DDI_DMA_SLEEP, NULL, 16722 cookiep, &ncookie) != DDI_DMA_MAPPED) { 16723 (void) ddi_dma_mem_free(acc_hdp); 16724 ddi_dma_free_handle(dma_hdp); 16725 *dma_hdp = NULL; 16726 return (FALSE); 16727 } 16728 16729 return (TRUE); 16730 } 16731 16732 void 16733 mptsas_dma_addr_destroy(ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp) 16734 { 16735 if (*dma_hdp == NULL) 16736 return; 16737 16738 (void) ddi_dma_unbind_handle(*dma_hdp); 16739 (void) ddi_dma_mem_free(acc_hdp); 16740 ddi_dma_free_handle(dma_hdp); 16741 *dma_hdp = NULL; 16742 } 16743