1*49ef7e06SGarrett D'Amore /* 2*49ef7e06SGarrett D'Amore * Copyright (c) 2007-2015 Solarflare Communications Inc. 3*49ef7e06SGarrett D'Amore * All rights reserved. 4*49ef7e06SGarrett D'Amore * 5*49ef7e06SGarrett D'Amore * Redistribution and use in source and binary forms, with or without 6*49ef7e06SGarrett D'Amore * modification, are permitted provided that the following conditions are met: 7*49ef7e06SGarrett D'Amore * 8*49ef7e06SGarrett D'Amore * 1. Redistributions of source code must retain the above copyright notice, 9*49ef7e06SGarrett D'Amore * this list of conditions and the following disclaimer. 10*49ef7e06SGarrett D'Amore * 2. Redistributions in binary form must reproduce the above copyright notice, 11*49ef7e06SGarrett D'Amore * this list of conditions and the following disclaimer in the documentation 12*49ef7e06SGarrett D'Amore * and/or other materials provided with the distribution. 13*49ef7e06SGarrett D'Amore * 14*49ef7e06SGarrett D'Amore * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15*49ef7e06SGarrett D'Amore * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16*49ef7e06SGarrett D'Amore * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17*49ef7e06SGarrett D'Amore * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18*49ef7e06SGarrett D'Amore * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19*49ef7e06SGarrett D'Amore * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20*49ef7e06SGarrett D'Amore * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21*49ef7e06SGarrett D'Amore * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22*49ef7e06SGarrett D'Amore * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23*49ef7e06SGarrett D'Amore * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24*49ef7e06SGarrett D'Amore * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25*49ef7e06SGarrett D'Amore * 26*49ef7e06SGarrett D'Amore * The views and conclusions contained in the software and documentation are 27*49ef7e06SGarrett D'Amore * those of the authors and should not be interpreted as representing official 28*49ef7e06SGarrett D'Amore * policies, either expressed or implied, of the FreeBSD Project. 29*49ef7e06SGarrett D'Amore */ 30*49ef7e06SGarrett D'Amore 31*49ef7e06SGarrett D'Amore #ifndef _SYS_EFX_REGS_PCI_H 32*49ef7e06SGarrett D'Amore #define _SYS_EFX_REGS_PCI_H 33*49ef7e06SGarrett D'Amore 34*49ef7e06SGarrett D'Amore #ifdef __cplusplus 35*49ef7e06SGarrett D'Amore extern "C" { 36*49ef7e06SGarrett D'Amore #endif 37*49ef7e06SGarrett D'Amore 38*49ef7e06SGarrett D'Amore /* 39*49ef7e06SGarrett D'Amore * PC_VEND_ID_REG(16bit): 40*49ef7e06SGarrett D'Amore * Vendor ID register 41*49ef7e06SGarrett D'Amore */ 42*49ef7e06SGarrett D'Amore 43*49ef7e06SGarrett D'Amore #define PCR_AZ_VEND_ID_REG 0x00000000 44*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 45*49ef7e06SGarrett D'Amore 46*49ef7e06SGarrett D'Amore #define PCRF_AZ_VEND_ID_LBN 0 47*49ef7e06SGarrett D'Amore #define PCRF_AZ_VEND_ID_WIDTH 16 48*49ef7e06SGarrett D'Amore 49*49ef7e06SGarrett D'Amore 50*49ef7e06SGarrett D'Amore /* 51*49ef7e06SGarrett D'Amore * PC_DEV_ID_REG(16bit): 52*49ef7e06SGarrett D'Amore * Device ID register 53*49ef7e06SGarrett D'Amore */ 54*49ef7e06SGarrett D'Amore 55*49ef7e06SGarrett D'Amore #define PCR_AZ_DEV_ID_REG 0x00000002 56*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 57*49ef7e06SGarrett D'Amore 58*49ef7e06SGarrett D'Amore #define PCRF_AZ_DEV_ID_LBN 0 59*49ef7e06SGarrett D'Amore #define PCRF_AZ_DEV_ID_WIDTH 16 60*49ef7e06SGarrett D'Amore 61*49ef7e06SGarrett D'Amore 62*49ef7e06SGarrett D'Amore /* 63*49ef7e06SGarrett D'Amore * PC_CMD_REG(16bit): 64*49ef7e06SGarrett D'Amore * Command register 65*49ef7e06SGarrett D'Amore */ 66*49ef7e06SGarrett D'Amore 67*49ef7e06SGarrett D'Amore #define PCR_AZ_CMD_REG 0x00000004 68*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 69*49ef7e06SGarrett D'Amore 70*49ef7e06SGarrett D'Amore #define PCRF_AZ_INTX_DIS_LBN 10 71*49ef7e06SGarrett D'Amore #define PCRF_AZ_INTX_DIS_WIDTH 1 72*49ef7e06SGarrett D'Amore #define PCRF_AZ_FB2B_EN_LBN 9 73*49ef7e06SGarrett D'Amore #define PCRF_AZ_FB2B_EN_WIDTH 1 74*49ef7e06SGarrett D'Amore #define PCRF_AZ_SERR_EN_LBN 8 75*49ef7e06SGarrett D'Amore #define PCRF_AZ_SERR_EN_WIDTH 1 76*49ef7e06SGarrett D'Amore #define PCRF_AZ_IDSEL_CTL_LBN 7 77*49ef7e06SGarrett D'Amore #define PCRF_AZ_IDSEL_CTL_WIDTH 1 78*49ef7e06SGarrett D'Amore #define PCRF_AZ_PERR_EN_LBN 6 79*49ef7e06SGarrett D'Amore #define PCRF_AZ_PERR_EN_WIDTH 1 80*49ef7e06SGarrett D'Amore #define PCRF_AZ_VGA_PAL_SNP_LBN 5 81*49ef7e06SGarrett D'Amore #define PCRF_AZ_VGA_PAL_SNP_WIDTH 1 82*49ef7e06SGarrett D'Amore #define PCRF_AZ_MWI_EN_LBN 4 83*49ef7e06SGarrett D'Amore #define PCRF_AZ_MWI_EN_WIDTH 1 84*49ef7e06SGarrett D'Amore #define PCRF_AZ_SPEC_CYC_LBN 3 85*49ef7e06SGarrett D'Amore #define PCRF_AZ_SPEC_CYC_WIDTH 1 86*49ef7e06SGarrett D'Amore #define PCRF_AZ_MST_EN_LBN 2 87*49ef7e06SGarrett D'Amore #define PCRF_AZ_MST_EN_WIDTH 1 88*49ef7e06SGarrett D'Amore #define PCRF_AZ_MEM_EN_LBN 1 89*49ef7e06SGarrett D'Amore #define PCRF_AZ_MEM_EN_WIDTH 1 90*49ef7e06SGarrett D'Amore #define PCRF_AZ_IO_EN_LBN 0 91*49ef7e06SGarrett D'Amore #define PCRF_AZ_IO_EN_WIDTH 1 92*49ef7e06SGarrett D'Amore 93*49ef7e06SGarrett D'Amore 94*49ef7e06SGarrett D'Amore /* 95*49ef7e06SGarrett D'Amore * PC_STAT_REG(16bit): 96*49ef7e06SGarrett D'Amore * Status register 97*49ef7e06SGarrett D'Amore */ 98*49ef7e06SGarrett D'Amore 99*49ef7e06SGarrett D'Amore #define PCR_AZ_STAT_REG 0x00000006 100*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 101*49ef7e06SGarrett D'Amore 102*49ef7e06SGarrett D'Amore #define PCRF_AZ_DET_PERR_LBN 15 103*49ef7e06SGarrett D'Amore #define PCRF_AZ_DET_PERR_WIDTH 1 104*49ef7e06SGarrett D'Amore #define PCRF_AZ_SIG_SERR_LBN 14 105*49ef7e06SGarrett D'Amore #define PCRF_AZ_SIG_SERR_WIDTH 1 106*49ef7e06SGarrett D'Amore #define PCRF_AZ_GOT_MABRT_LBN 13 107*49ef7e06SGarrett D'Amore #define PCRF_AZ_GOT_MABRT_WIDTH 1 108*49ef7e06SGarrett D'Amore #define PCRF_AZ_GOT_TABRT_LBN 12 109*49ef7e06SGarrett D'Amore #define PCRF_AZ_GOT_TABRT_WIDTH 1 110*49ef7e06SGarrett D'Amore #define PCRF_AZ_SIG_TABRT_LBN 11 111*49ef7e06SGarrett D'Amore #define PCRF_AZ_SIG_TABRT_WIDTH 1 112*49ef7e06SGarrett D'Amore #define PCRF_AZ_DEVSEL_TIM_LBN 9 113*49ef7e06SGarrett D'Amore #define PCRF_AZ_DEVSEL_TIM_WIDTH 2 114*49ef7e06SGarrett D'Amore #define PCRF_AZ_MDAT_PERR_LBN 8 115*49ef7e06SGarrett D'Amore #define PCRF_AZ_MDAT_PERR_WIDTH 1 116*49ef7e06SGarrett D'Amore #define PCRF_AZ_FB2B_CAP_LBN 7 117*49ef7e06SGarrett D'Amore #define PCRF_AZ_FB2B_CAP_WIDTH 1 118*49ef7e06SGarrett D'Amore #define PCRF_AZ_66MHZ_CAP_LBN 5 119*49ef7e06SGarrett D'Amore #define PCRF_AZ_66MHZ_CAP_WIDTH 1 120*49ef7e06SGarrett D'Amore #define PCRF_AZ_CAP_LIST_LBN 4 121*49ef7e06SGarrett D'Amore #define PCRF_AZ_CAP_LIST_WIDTH 1 122*49ef7e06SGarrett D'Amore #define PCRF_AZ_INTX_STAT_LBN 3 123*49ef7e06SGarrett D'Amore #define PCRF_AZ_INTX_STAT_WIDTH 1 124*49ef7e06SGarrett D'Amore 125*49ef7e06SGarrett D'Amore 126*49ef7e06SGarrett D'Amore /* 127*49ef7e06SGarrett D'Amore * PC_REV_ID_REG(8bit): 128*49ef7e06SGarrett D'Amore * Class code & revision ID register 129*49ef7e06SGarrett D'Amore */ 130*49ef7e06SGarrett D'Amore 131*49ef7e06SGarrett D'Amore #define PCR_AZ_REV_ID_REG 0x00000008 132*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 133*49ef7e06SGarrett D'Amore 134*49ef7e06SGarrett D'Amore #define PCRF_AZ_REV_ID_LBN 0 135*49ef7e06SGarrett D'Amore #define PCRF_AZ_REV_ID_WIDTH 8 136*49ef7e06SGarrett D'Amore 137*49ef7e06SGarrett D'Amore 138*49ef7e06SGarrett D'Amore /* 139*49ef7e06SGarrett D'Amore * PC_CC_REG(24bit): 140*49ef7e06SGarrett D'Amore * Class code register 141*49ef7e06SGarrett D'Amore */ 142*49ef7e06SGarrett D'Amore 143*49ef7e06SGarrett D'Amore #define PCR_AZ_CC_REG 0x00000009 144*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 145*49ef7e06SGarrett D'Amore 146*49ef7e06SGarrett D'Amore #define PCRF_AZ_BASE_CC_LBN 16 147*49ef7e06SGarrett D'Amore #define PCRF_AZ_BASE_CC_WIDTH 8 148*49ef7e06SGarrett D'Amore #define PCRF_AZ_SUB_CC_LBN 8 149*49ef7e06SGarrett D'Amore #define PCRF_AZ_SUB_CC_WIDTH 8 150*49ef7e06SGarrett D'Amore #define PCRF_AZ_PROG_IF_LBN 0 151*49ef7e06SGarrett D'Amore #define PCRF_AZ_PROG_IF_WIDTH 8 152*49ef7e06SGarrett D'Amore 153*49ef7e06SGarrett D'Amore 154*49ef7e06SGarrett D'Amore /* 155*49ef7e06SGarrett D'Amore * PC_CACHE_LSIZE_REG(8bit): 156*49ef7e06SGarrett D'Amore * Cache line size 157*49ef7e06SGarrett D'Amore */ 158*49ef7e06SGarrett D'Amore 159*49ef7e06SGarrett D'Amore #define PCR_AZ_CACHE_LSIZE_REG 0x0000000c 160*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 161*49ef7e06SGarrett D'Amore 162*49ef7e06SGarrett D'Amore #define PCRF_AZ_CACHE_LSIZE_LBN 0 163*49ef7e06SGarrett D'Amore #define PCRF_AZ_CACHE_LSIZE_WIDTH 8 164*49ef7e06SGarrett D'Amore 165*49ef7e06SGarrett D'Amore 166*49ef7e06SGarrett D'Amore /* 167*49ef7e06SGarrett D'Amore * PC_MST_LAT_REG(8bit): 168*49ef7e06SGarrett D'Amore * Master latency timer register 169*49ef7e06SGarrett D'Amore */ 170*49ef7e06SGarrett D'Amore 171*49ef7e06SGarrett D'Amore #define PCR_AZ_MST_LAT_REG 0x0000000d 172*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 173*49ef7e06SGarrett D'Amore 174*49ef7e06SGarrett D'Amore #define PCRF_AZ_MST_LAT_LBN 0 175*49ef7e06SGarrett D'Amore #define PCRF_AZ_MST_LAT_WIDTH 8 176*49ef7e06SGarrett D'Amore 177*49ef7e06SGarrett D'Amore 178*49ef7e06SGarrett D'Amore /* 179*49ef7e06SGarrett D'Amore * PC_HDR_TYPE_REG(8bit): 180*49ef7e06SGarrett D'Amore * Header type register 181*49ef7e06SGarrett D'Amore */ 182*49ef7e06SGarrett D'Amore 183*49ef7e06SGarrett D'Amore #define PCR_AZ_HDR_TYPE_REG 0x0000000e 184*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 185*49ef7e06SGarrett D'Amore 186*49ef7e06SGarrett D'Amore #define PCRF_AZ_MULT_FUNC_LBN 7 187*49ef7e06SGarrett D'Amore #define PCRF_AZ_MULT_FUNC_WIDTH 1 188*49ef7e06SGarrett D'Amore #define PCRF_AZ_TYPE_LBN 0 189*49ef7e06SGarrett D'Amore #define PCRF_AZ_TYPE_WIDTH 7 190*49ef7e06SGarrett D'Amore 191*49ef7e06SGarrett D'Amore 192*49ef7e06SGarrett D'Amore /* 193*49ef7e06SGarrett D'Amore * PC_BIST_REG(8bit): 194*49ef7e06SGarrett D'Amore * BIST register 195*49ef7e06SGarrett D'Amore */ 196*49ef7e06SGarrett D'Amore 197*49ef7e06SGarrett D'Amore #define PCR_AZ_BIST_REG 0x0000000f 198*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 199*49ef7e06SGarrett D'Amore 200*49ef7e06SGarrett D'Amore #define PCRF_AZ_BIST_LBN 0 201*49ef7e06SGarrett D'Amore #define PCRF_AZ_BIST_WIDTH 8 202*49ef7e06SGarrett D'Amore 203*49ef7e06SGarrett D'Amore 204*49ef7e06SGarrett D'Amore /* 205*49ef7e06SGarrett D'Amore * PC_BAR0_REG(32bit): 206*49ef7e06SGarrett D'Amore * Primary function base address register 0 207*49ef7e06SGarrett D'Amore */ 208*49ef7e06SGarrett D'Amore 209*49ef7e06SGarrett D'Amore #define PCR_AZ_BAR0_REG 0x00000010 210*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 211*49ef7e06SGarrett D'Amore 212*49ef7e06SGarrett D'Amore #define PCRF_AZ_BAR0_LBN 4 213*49ef7e06SGarrett D'Amore #define PCRF_AZ_BAR0_WIDTH 28 214*49ef7e06SGarrett D'Amore #define PCRF_AZ_BAR0_PREF_LBN 3 215*49ef7e06SGarrett D'Amore #define PCRF_AZ_BAR0_PREF_WIDTH 1 216*49ef7e06SGarrett D'Amore #define PCRF_AZ_BAR0_TYPE_LBN 1 217*49ef7e06SGarrett D'Amore #define PCRF_AZ_BAR0_TYPE_WIDTH 2 218*49ef7e06SGarrett D'Amore #define PCRF_AZ_BAR0_IOM_LBN 0 219*49ef7e06SGarrett D'Amore #define PCRF_AZ_BAR0_IOM_WIDTH 1 220*49ef7e06SGarrett D'Amore 221*49ef7e06SGarrett D'Amore 222*49ef7e06SGarrett D'Amore /* 223*49ef7e06SGarrett D'Amore * PC_BAR1_REG(32bit): 224*49ef7e06SGarrett D'Amore * Primary function base address register 1, BAR1 is not implemented so read only. 225*49ef7e06SGarrett D'Amore */ 226*49ef7e06SGarrett D'Amore 227*49ef7e06SGarrett D'Amore #define PCR_DZ_BAR1_REG 0x00000014 228*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 229*49ef7e06SGarrett D'Amore 230*49ef7e06SGarrett D'Amore #define PCRF_DZ_BAR1_LBN 0 231*49ef7e06SGarrett D'Amore #define PCRF_DZ_BAR1_WIDTH 32 232*49ef7e06SGarrett D'Amore 233*49ef7e06SGarrett D'Amore 234*49ef7e06SGarrett D'Amore /* 235*49ef7e06SGarrett D'Amore * PC_BAR2_LO_REG(32bit): 236*49ef7e06SGarrett D'Amore * Primary function base address register 2 low bits 237*49ef7e06SGarrett D'Amore */ 238*49ef7e06SGarrett D'Amore 239*49ef7e06SGarrett D'Amore #define PCR_AZ_BAR2_LO_REG 0x00000018 240*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 241*49ef7e06SGarrett D'Amore 242*49ef7e06SGarrett D'Amore #define PCRF_AZ_BAR2_LO_LBN 4 243*49ef7e06SGarrett D'Amore #define PCRF_AZ_BAR2_LO_WIDTH 28 244*49ef7e06SGarrett D'Amore #define PCRF_AZ_BAR2_PREF_LBN 3 245*49ef7e06SGarrett D'Amore #define PCRF_AZ_BAR2_PREF_WIDTH 1 246*49ef7e06SGarrett D'Amore #define PCRF_AZ_BAR2_TYPE_LBN 1 247*49ef7e06SGarrett D'Amore #define PCRF_AZ_BAR2_TYPE_WIDTH 2 248*49ef7e06SGarrett D'Amore #define PCRF_AZ_BAR2_IOM_LBN 0 249*49ef7e06SGarrett D'Amore #define PCRF_AZ_BAR2_IOM_WIDTH 1 250*49ef7e06SGarrett D'Amore 251*49ef7e06SGarrett D'Amore 252*49ef7e06SGarrett D'Amore /* 253*49ef7e06SGarrett D'Amore * PC_BAR2_HI_REG(32bit): 254*49ef7e06SGarrett D'Amore * Primary function base address register 2 high bits 255*49ef7e06SGarrett D'Amore */ 256*49ef7e06SGarrett D'Amore 257*49ef7e06SGarrett D'Amore #define PCR_AZ_BAR2_HI_REG 0x0000001c 258*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 259*49ef7e06SGarrett D'Amore 260*49ef7e06SGarrett D'Amore #define PCRF_AZ_BAR2_HI_LBN 0 261*49ef7e06SGarrett D'Amore #define PCRF_AZ_BAR2_HI_WIDTH 32 262*49ef7e06SGarrett D'Amore 263*49ef7e06SGarrett D'Amore 264*49ef7e06SGarrett D'Amore /* 265*49ef7e06SGarrett D'Amore * PC_BAR4_LO_REG(32bit): 266*49ef7e06SGarrett D'Amore * Primary function base address register 2 low bits 267*49ef7e06SGarrett D'Amore */ 268*49ef7e06SGarrett D'Amore 269*49ef7e06SGarrett D'Amore #define PCR_CZ_BAR4_LO_REG 0x00000020 270*49ef7e06SGarrett D'Amore /* sienaa0,hunta0=pci_f0_config */ 271*49ef7e06SGarrett D'Amore 272*49ef7e06SGarrett D'Amore #define PCRF_CZ_BAR4_LO_LBN 4 273*49ef7e06SGarrett D'Amore #define PCRF_CZ_BAR4_LO_WIDTH 28 274*49ef7e06SGarrett D'Amore #define PCRF_CZ_BAR4_PREF_LBN 3 275*49ef7e06SGarrett D'Amore #define PCRF_CZ_BAR4_PREF_WIDTH 1 276*49ef7e06SGarrett D'Amore #define PCRF_CZ_BAR4_TYPE_LBN 1 277*49ef7e06SGarrett D'Amore #define PCRF_CZ_BAR4_TYPE_WIDTH 2 278*49ef7e06SGarrett D'Amore #define PCRF_CZ_BAR4_IOM_LBN 0 279*49ef7e06SGarrett D'Amore #define PCRF_CZ_BAR4_IOM_WIDTH 1 280*49ef7e06SGarrett D'Amore 281*49ef7e06SGarrett D'Amore 282*49ef7e06SGarrett D'Amore /* 283*49ef7e06SGarrett D'Amore * PC_BAR4_HI_REG(32bit): 284*49ef7e06SGarrett D'Amore * Primary function base address register 2 high bits 285*49ef7e06SGarrett D'Amore */ 286*49ef7e06SGarrett D'Amore 287*49ef7e06SGarrett D'Amore #define PCR_CZ_BAR4_HI_REG 0x00000024 288*49ef7e06SGarrett D'Amore /* sienaa0,hunta0=pci_f0_config */ 289*49ef7e06SGarrett D'Amore 290*49ef7e06SGarrett D'Amore #define PCRF_CZ_BAR4_HI_LBN 0 291*49ef7e06SGarrett D'Amore #define PCRF_CZ_BAR4_HI_WIDTH 32 292*49ef7e06SGarrett D'Amore 293*49ef7e06SGarrett D'Amore 294*49ef7e06SGarrett D'Amore /* 295*49ef7e06SGarrett D'Amore * PC_SS_VEND_ID_REG(16bit): 296*49ef7e06SGarrett D'Amore * Sub-system vendor ID register 297*49ef7e06SGarrett D'Amore */ 298*49ef7e06SGarrett D'Amore 299*49ef7e06SGarrett D'Amore #define PCR_AZ_SS_VEND_ID_REG 0x0000002c 300*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 301*49ef7e06SGarrett D'Amore 302*49ef7e06SGarrett D'Amore #define PCRF_AZ_SS_VEND_ID_LBN 0 303*49ef7e06SGarrett D'Amore #define PCRF_AZ_SS_VEND_ID_WIDTH 16 304*49ef7e06SGarrett D'Amore 305*49ef7e06SGarrett D'Amore 306*49ef7e06SGarrett D'Amore /* 307*49ef7e06SGarrett D'Amore * PC_SS_ID_REG(16bit): 308*49ef7e06SGarrett D'Amore * Sub-system ID register 309*49ef7e06SGarrett D'Amore */ 310*49ef7e06SGarrett D'Amore 311*49ef7e06SGarrett D'Amore #define PCR_AZ_SS_ID_REG 0x0000002e 312*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 313*49ef7e06SGarrett D'Amore 314*49ef7e06SGarrett D'Amore #define PCRF_AZ_SS_ID_LBN 0 315*49ef7e06SGarrett D'Amore #define PCRF_AZ_SS_ID_WIDTH 16 316*49ef7e06SGarrett D'Amore 317*49ef7e06SGarrett D'Amore 318*49ef7e06SGarrett D'Amore /* 319*49ef7e06SGarrett D'Amore * PC_EXPROM_BAR_REG(32bit): 320*49ef7e06SGarrett D'Amore * Expansion ROM base address register 321*49ef7e06SGarrett D'Amore */ 322*49ef7e06SGarrett D'Amore 323*49ef7e06SGarrett D'Amore #define PCR_AZ_EXPROM_BAR_REG 0x00000030 324*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 325*49ef7e06SGarrett D'Amore 326*49ef7e06SGarrett D'Amore #define PCRF_AZ_EXPROM_BAR_LBN 11 327*49ef7e06SGarrett D'Amore #define PCRF_AZ_EXPROM_BAR_WIDTH 21 328*49ef7e06SGarrett D'Amore #define PCRF_AB_EXPROM_MIN_SIZE_LBN 2 329*49ef7e06SGarrett D'Amore #define PCRF_AB_EXPROM_MIN_SIZE_WIDTH 9 330*49ef7e06SGarrett D'Amore #define PCRF_CZ_EXPROM_MIN_SIZE_LBN 1 331*49ef7e06SGarrett D'Amore #define PCRF_CZ_EXPROM_MIN_SIZE_WIDTH 10 332*49ef7e06SGarrett D'Amore #define PCRF_AB_EXPROM_FEATURE_ENABLE_LBN 1 333*49ef7e06SGarrett D'Amore #define PCRF_AB_EXPROM_FEATURE_ENABLE_WIDTH 1 334*49ef7e06SGarrett D'Amore #define PCRF_AZ_EXPROM_EN_LBN 0 335*49ef7e06SGarrett D'Amore #define PCRF_AZ_EXPROM_EN_WIDTH 1 336*49ef7e06SGarrett D'Amore 337*49ef7e06SGarrett D'Amore 338*49ef7e06SGarrett D'Amore /* 339*49ef7e06SGarrett D'Amore * PC_CAP_PTR_REG(8bit): 340*49ef7e06SGarrett D'Amore * Capability pointer register 341*49ef7e06SGarrett D'Amore */ 342*49ef7e06SGarrett D'Amore 343*49ef7e06SGarrett D'Amore #define PCR_AZ_CAP_PTR_REG 0x00000034 344*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 345*49ef7e06SGarrett D'Amore 346*49ef7e06SGarrett D'Amore #define PCRF_AZ_CAP_PTR_LBN 0 347*49ef7e06SGarrett D'Amore #define PCRF_AZ_CAP_PTR_WIDTH 8 348*49ef7e06SGarrett D'Amore 349*49ef7e06SGarrett D'Amore 350*49ef7e06SGarrett D'Amore /* 351*49ef7e06SGarrett D'Amore * PC_INT_LINE_REG(8bit): 352*49ef7e06SGarrett D'Amore * Interrupt line register 353*49ef7e06SGarrett D'Amore */ 354*49ef7e06SGarrett D'Amore 355*49ef7e06SGarrett D'Amore #define PCR_AZ_INT_LINE_REG 0x0000003c 356*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 357*49ef7e06SGarrett D'Amore 358*49ef7e06SGarrett D'Amore #define PCRF_AZ_INT_LINE_LBN 0 359*49ef7e06SGarrett D'Amore #define PCRF_AZ_INT_LINE_WIDTH 8 360*49ef7e06SGarrett D'Amore 361*49ef7e06SGarrett D'Amore 362*49ef7e06SGarrett D'Amore /* 363*49ef7e06SGarrett D'Amore * PC_INT_PIN_REG(8bit): 364*49ef7e06SGarrett D'Amore * Interrupt pin register 365*49ef7e06SGarrett D'Amore */ 366*49ef7e06SGarrett D'Amore 367*49ef7e06SGarrett D'Amore #define PCR_AZ_INT_PIN_REG 0x0000003d 368*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 369*49ef7e06SGarrett D'Amore 370*49ef7e06SGarrett D'Amore #define PCRF_AZ_INT_PIN_LBN 0 371*49ef7e06SGarrett D'Amore #define PCRF_AZ_INT_PIN_WIDTH 8 372*49ef7e06SGarrett D'Amore #define PCFE_DZ_INTPIN_INTD 4 373*49ef7e06SGarrett D'Amore #define PCFE_DZ_INTPIN_INTC 3 374*49ef7e06SGarrett D'Amore #define PCFE_DZ_INTPIN_INTB 2 375*49ef7e06SGarrett D'Amore #define PCFE_DZ_INTPIN_INTA 1 376*49ef7e06SGarrett D'Amore 377*49ef7e06SGarrett D'Amore 378*49ef7e06SGarrett D'Amore /* 379*49ef7e06SGarrett D'Amore * PC_PM_CAP_ID_REG(8bit): 380*49ef7e06SGarrett D'Amore * Power management capability ID 381*49ef7e06SGarrett D'Amore */ 382*49ef7e06SGarrett D'Amore 383*49ef7e06SGarrett D'Amore #define PCR_AZ_PM_CAP_ID_REG 0x00000040 384*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 385*49ef7e06SGarrett D'Amore 386*49ef7e06SGarrett D'Amore #define PCRF_AZ_PM_CAP_ID_LBN 0 387*49ef7e06SGarrett D'Amore #define PCRF_AZ_PM_CAP_ID_WIDTH 8 388*49ef7e06SGarrett D'Amore 389*49ef7e06SGarrett D'Amore 390*49ef7e06SGarrett D'Amore /* 391*49ef7e06SGarrett D'Amore * PC_PM_NXT_PTR_REG(8bit): 392*49ef7e06SGarrett D'Amore * Power management next item pointer 393*49ef7e06SGarrett D'Amore */ 394*49ef7e06SGarrett D'Amore 395*49ef7e06SGarrett D'Amore #define PCR_AZ_PM_NXT_PTR_REG 0x00000041 396*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 397*49ef7e06SGarrett D'Amore 398*49ef7e06SGarrett D'Amore #define PCRF_AZ_PM_NXT_PTR_LBN 0 399*49ef7e06SGarrett D'Amore #define PCRF_AZ_PM_NXT_PTR_WIDTH 8 400*49ef7e06SGarrett D'Amore 401*49ef7e06SGarrett D'Amore 402*49ef7e06SGarrett D'Amore /* 403*49ef7e06SGarrett D'Amore * PC_PM_CAP_REG(16bit): 404*49ef7e06SGarrett D'Amore * Power management capabilities register 405*49ef7e06SGarrett D'Amore */ 406*49ef7e06SGarrett D'Amore 407*49ef7e06SGarrett D'Amore #define PCR_AZ_PM_CAP_REG 0x00000042 408*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 409*49ef7e06SGarrett D'Amore 410*49ef7e06SGarrett D'Amore #define PCRF_AZ_PM_PME_SUPT_LBN 11 411*49ef7e06SGarrett D'Amore #define PCRF_AZ_PM_PME_SUPT_WIDTH 5 412*49ef7e06SGarrett D'Amore #define PCRF_AZ_PM_D2_SUPT_LBN 10 413*49ef7e06SGarrett D'Amore #define PCRF_AZ_PM_D2_SUPT_WIDTH 1 414*49ef7e06SGarrett D'Amore #define PCRF_AZ_PM_D1_SUPT_LBN 9 415*49ef7e06SGarrett D'Amore #define PCRF_AZ_PM_D1_SUPT_WIDTH 1 416*49ef7e06SGarrett D'Amore #define PCRF_AZ_PM_AUX_CURR_LBN 6 417*49ef7e06SGarrett D'Amore #define PCRF_AZ_PM_AUX_CURR_WIDTH 3 418*49ef7e06SGarrett D'Amore #define PCRF_AZ_PM_DSI_LBN 5 419*49ef7e06SGarrett D'Amore #define PCRF_AZ_PM_DSI_WIDTH 1 420*49ef7e06SGarrett D'Amore #define PCRF_AZ_PM_PME_CLK_LBN 3 421*49ef7e06SGarrett D'Amore #define PCRF_AZ_PM_PME_CLK_WIDTH 1 422*49ef7e06SGarrett D'Amore #define PCRF_AZ_PM_PME_VER_LBN 0 423*49ef7e06SGarrett D'Amore #define PCRF_AZ_PM_PME_VER_WIDTH 3 424*49ef7e06SGarrett D'Amore 425*49ef7e06SGarrett D'Amore 426*49ef7e06SGarrett D'Amore /* 427*49ef7e06SGarrett D'Amore * PC_PM_CS_REG(16bit): 428*49ef7e06SGarrett D'Amore * Power management control & status register 429*49ef7e06SGarrett D'Amore */ 430*49ef7e06SGarrett D'Amore 431*49ef7e06SGarrett D'Amore #define PCR_AZ_PM_CS_REG 0x00000044 432*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 433*49ef7e06SGarrett D'Amore 434*49ef7e06SGarrett D'Amore #define PCRF_AZ_PM_PME_STAT_LBN 15 435*49ef7e06SGarrett D'Amore #define PCRF_AZ_PM_PME_STAT_WIDTH 1 436*49ef7e06SGarrett D'Amore #define PCRF_AZ_PM_DAT_SCALE_LBN 13 437*49ef7e06SGarrett D'Amore #define PCRF_AZ_PM_DAT_SCALE_WIDTH 2 438*49ef7e06SGarrett D'Amore #define PCRF_AZ_PM_DAT_SEL_LBN 9 439*49ef7e06SGarrett D'Amore #define PCRF_AZ_PM_DAT_SEL_WIDTH 4 440*49ef7e06SGarrett D'Amore #define PCRF_AZ_PM_PME_EN_LBN 8 441*49ef7e06SGarrett D'Amore #define PCRF_AZ_PM_PME_EN_WIDTH 1 442*49ef7e06SGarrett D'Amore #define PCRF_CZ_NO_SOFT_RESET_LBN 3 443*49ef7e06SGarrett D'Amore #define PCRF_CZ_NO_SOFT_RESET_WIDTH 1 444*49ef7e06SGarrett D'Amore #define PCRF_AZ_PM_PWR_ST_LBN 0 445*49ef7e06SGarrett D'Amore #define PCRF_AZ_PM_PWR_ST_WIDTH 2 446*49ef7e06SGarrett D'Amore 447*49ef7e06SGarrett D'Amore 448*49ef7e06SGarrett D'Amore /* 449*49ef7e06SGarrett D'Amore * PC_MSI_CAP_ID_REG(8bit): 450*49ef7e06SGarrett D'Amore * MSI capability ID 451*49ef7e06SGarrett D'Amore */ 452*49ef7e06SGarrett D'Amore 453*49ef7e06SGarrett D'Amore #define PCR_AZ_MSI_CAP_ID_REG 0x00000050 454*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 455*49ef7e06SGarrett D'Amore 456*49ef7e06SGarrett D'Amore #define PCRF_AZ_MSI_CAP_ID_LBN 0 457*49ef7e06SGarrett D'Amore #define PCRF_AZ_MSI_CAP_ID_WIDTH 8 458*49ef7e06SGarrett D'Amore 459*49ef7e06SGarrett D'Amore 460*49ef7e06SGarrett D'Amore /* 461*49ef7e06SGarrett D'Amore * PC_MSI_NXT_PTR_REG(8bit): 462*49ef7e06SGarrett D'Amore * MSI next item pointer 463*49ef7e06SGarrett D'Amore */ 464*49ef7e06SGarrett D'Amore 465*49ef7e06SGarrett D'Amore #define PCR_AZ_MSI_NXT_PTR_REG 0x00000051 466*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 467*49ef7e06SGarrett D'Amore 468*49ef7e06SGarrett D'Amore #define PCRF_AZ_MSI_NXT_PTR_LBN 0 469*49ef7e06SGarrett D'Amore #define PCRF_AZ_MSI_NXT_PTR_WIDTH 8 470*49ef7e06SGarrett D'Amore 471*49ef7e06SGarrett D'Amore 472*49ef7e06SGarrett D'Amore /* 473*49ef7e06SGarrett D'Amore * PC_MSI_CTL_REG(16bit): 474*49ef7e06SGarrett D'Amore * MSI control register 475*49ef7e06SGarrett D'Amore */ 476*49ef7e06SGarrett D'Amore 477*49ef7e06SGarrett D'Amore #define PCR_AZ_MSI_CTL_REG 0x00000052 478*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 479*49ef7e06SGarrett D'Amore 480*49ef7e06SGarrett D'Amore #define PCRF_AZ_MSI_64_EN_LBN 7 481*49ef7e06SGarrett D'Amore #define PCRF_AZ_MSI_64_EN_WIDTH 1 482*49ef7e06SGarrett D'Amore #define PCRF_AZ_MSI_MULT_MSG_EN_LBN 4 483*49ef7e06SGarrett D'Amore #define PCRF_AZ_MSI_MULT_MSG_EN_WIDTH 3 484*49ef7e06SGarrett D'Amore #define PCRF_AZ_MSI_MULT_MSG_CAP_LBN 1 485*49ef7e06SGarrett D'Amore #define PCRF_AZ_MSI_MULT_MSG_CAP_WIDTH 3 486*49ef7e06SGarrett D'Amore #define PCRF_AZ_MSI_EN_LBN 0 487*49ef7e06SGarrett D'Amore #define PCRF_AZ_MSI_EN_WIDTH 1 488*49ef7e06SGarrett D'Amore 489*49ef7e06SGarrett D'Amore 490*49ef7e06SGarrett D'Amore /* 491*49ef7e06SGarrett D'Amore * PC_MSI_ADR_LO_REG(32bit): 492*49ef7e06SGarrett D'Amore * MSI low 32 bits address register 493*49ef7e06SGarrett D'Amore */ 494*49ef7e06SGarrett D'Amore 495*49ef7e06SGarrett D'Amore #define PCR_AZ_MSI_ADR_LO_REG 0x00000054 496*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 497*49ef7e06SGarrett D'Amore 498*49ef7e06SGarrett D'Amore #define PCRF_AZ_MSI_ADR_LO_LBN 2 499*49ef7e06SGarrett D'Amore #define PCRF_AZ_MSI_ADR_LO_WIDTH 30 500*49ef7e06SGarrett D'Amore 501*49ef7e06SGarrett D'Amore 502*49ef7e06SGarrett D'Amore /* 503*49ef7e06SGarrett D'Amore * PC_MSI_ADR_HI_REG(32bit): 504*49ef7e06SGarrett D'Amore * MSI high 32 bits address register 505*49ef7e06SGarrett D'Amore */ 506*49ef7e06SGarrett D'Amore 507*49ef7e06SGarrett D'Amore #define PCR_AZ_MSI_ADR_HI_REG 0x00000058 508*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 509*49ef7e06SGarrett D'Amore 510*49ef7e06SGarrett D'Amore #define PCRF_AZ_MSI_ADR_HI_LBN 0 511*49ef7e06SGarrett D'Amore #define PCRF_AZ_MSI_ADR_HI_WIDTH 32 512*49ef7e06SGarrett D'Amore 513*49ef7e06SGarrett D'Amore 514*49ef7e06SGarrett D'Amore /* 515*49ef7e06SGarrett D'Amore * PC_MSI_DAT_REG(16bit): 516*49ef7e06SGarrett D'Amore * MSI data register 517*49ef7e06SGarrett D'Amore */ 518*49ef7e06SGarrett D'Amore 519*49ef7e06SGarrett D'Amore #define PCR_AZ_MSI_DAT_REG 0x0000005c 520*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 521*49ef7e06SGarrett D'Amore 522*49ef7e06SGarrett D'Amore #define PCRF_AZ_MSI_DAT_LBN 0 523*49ef7e06SGarrett D'Amore #define PCRF_AZ_MSI_DAT_WIDTH 16 524*49ef7e06SGarrett D'Amore 525*49ef7e06SGarrett D'Amore 526*49ef7e06SGarrett D'Amore /* 527*49ef7e06SGarrett D'Amore * PC_PCIE_CAP_LIST_REG(16bit): 528*49ef7e06SGarrett D'Amore * PCIe capability list register 529*49ef7e06SGarrett D'Amore */ 530*49ef7e06SGarrett D'Amore 531*49ef7e06SGarrett D'Amore #define PCR_AB_PCIE_CAP_LIST_REG 0x00000060 532*49ef7e06SGarrett D'Amore /* falcona0,falconb0=pci_f0_config */ 533*49ef7e06SGarrett D'Amore 534*49ef7e06SGarrett D'Amore #define PCR_CZ_PCIE_CAP_LIST_REG 0x00000070 535*49ef7e06SGarrett D'Amore /* sienaa0,hunta0=pci_f0_config */ 536*49ef7e06SGarrett D'Amore 537*49ef7e06SGarrett D'Amore #define PCRF_AZ_PCIE_NXT_PTR_LBN 8 538*49ef7e06SGarrett D'Amore #define PCRF_AZ_PCIE_NXT_PTR_WIDTH 8 539*49ef7e06SGarrett D'Amore #define PCRF_AZ_PCIE_CAP_ID_LBN 0 540*49ef7e06SGarrett D'Amore #define PCRF_AZ_PCIE_CAP_ID_WIDTH 8 541*49ef7e06SGarrett D'Amore 542*49ef7e06SGarrett D'Amore 543*49ef7e06SGarrett D'Amore /* 544*49ef7e06SGarrett D'Amore * PC_PCIE_CAP_REG(16bit): 545*49ef7e06SGarrett D'Amore * PCIe capability register 546*49ef7e06SGarrett D'Amore */ 547*49ef7e06SGarrett D'Amore 548*49ef7e06SGarrett D'Amore #define PCR_AB_PCIE_CAP_REG 0x00000062 549*49ef7e06SGarrett D'Amore /* falcona0,falconb0=pci_f0_config */ 550*49ef7e06SGarrett D'Amore 551*49ef7e06SGarrett D'Amore #define PCR_CZ_PCIE_CAP_REG 0x00000072 552*49ef7e06SGarrett D'Amore /* sienaa0,hunta0=pci_f0_config */ 553*49ef7e06SGarrett D'Amore 554*49ef7e06SGarrett D'Amore #define PCRF_AZ_PCIE_INT_MSG_NUM_LBN 9 555*49ef7e06SGarrett D'Amore #define PCRF_AZ_PCIE_INT_MSG_NUM_WIDTH 5 556*49ef7e06SGarrett D'Amore #define PCRF_AZ_PCIE_SLOT_IMP_LBN 8 557*49ef7e06SGarrett D'Amore #define PCRF_AZ_PCIE_SLOT_IMP_WIDTH 1 558*49ef7e06SGarrett D'Amore #define PCRF_AZ_PCIE_DEV_PORT_TYPE_LBN 4 559*49ef7e06SGarrett D'Amore #define PCRF_AZ_PCIE_DEV_PORT_TYPE_WIDTH 4 560*49ef7e06SGarrett D'Amore #define PCRF_AZ_PCIE_CAP_VER_LBN 0 561*49ef7e06SGarrett D'Amore #define PCRF_AZ_PCIE_CAP_VER_WIDTH 4 562*49ef7e06SGarrett D'Amore 563*49ef7e06SGarrett D'Amore 564*49ef7e06SGarrett D'Amore /* 565*49ef7e06SGarrett D'Amore * PC_DEV_CAP_REG(32bit): 566*49ef7e06SGarrett D'Amore * PCIe device capabilities register 567*49ef7e06SGarrett D'Amore */ 568*49ef7e06SGarrett D'Amore 569*49ef7e06SGarrett D'Amore #define PCR_AB_DEV_CAP_REG 0x00000064 570*49ef7e06SGarrett D'Amore /* falcona0,falconb0=pci_f0_config */ 571*49ef7e06SGarrett D'Amore 572*49ef7e06SGarrett D'Amore #define PCR_CZ_DEV_CAP_REG 0x00000074 573*49ef7e06SGarrett D'Amore /* sienaa0=pci_f0_config,hunta0=pci_f0_config */ 574*49ef7e06SGarrett D'Amore 575*49ef7e06SGarrett D'Amore #define PCRF_CZ_CAP_FN_LEVEL_RESET_LBN 28 576*49ef7e06SGarrett D'Amore #define PCRF_CZ_CAP_FN_LEVEL_RESET_WIDTH 1 577*49ef7e06SGarrett D'Amore #define PCRF_AZ_CAP_SLOT_PWR_SCL_LBN 26 578*49ef7e06SGarrett D'Amore #define PCRF_AZ_CAP_SLOT_PWR_SCL_WIDTH 2 579*49ef7e06SGarrett D'Amore #define PCRF_AZ_CAP_SLOT_PWR_VAL_LBN 18 580*49ef7e06SGarrett D'Amore #define PCRF_AZ_CAP_SLOT_PWR_VAL_WIDTH 8 581*49ef7e06SGarrett D'Amore #define PCRF_CZ_ROLE_BASE_ERR_REPORTING_LBN 15 582*49ef7e06SGarrett D'Amore #define PCRF_CZ_ROLE_BASE_ERR_REPORTING_WIDTH 1 583*49ef7e06SGarrett D'Amore #define PCRF_AB_PWR_IND_LBN 14 584*49ef7e06SGarrett D'Amore #define PCRF_AB_PWR_IND_WIDTH 1 585*49ef7e06SGarrett D'Amore #define PCRF_AB_ATTN_IND_LBN 13 586*49ef7e06SGarrett D'Amore #define PCRF_AB_ATTN_IND_WIDTH 1 587*49ef7e06SGarrett D'Amore #define PCRF_AB_ATTN_BUTTON_LBN 12 588*49ef7e06SGarrett D'Amore #define PCRF_AB_ATTN_BUTTON_WIDTH 1 589*49ef7e06SGarrett D'Amore #define PCRF_AZ_ENDPT_L1_LAT_LBN 9 590*49ef7e06SGarrett D'Amore #define PCRF_AZ_ENDPT_L1_LAT_WIDTH 3 591*49ef7e06SGarrett D'Amore #define PCRF_AZ_ENDPT_L0_LAT_LBN 6 592*49ef7e06SGarrett D'Amore #define PCRF_AZ_ENDPT_L0_LAT_WIDTH 3 593*49ef7e06SGarrett D'Amore #define PCRF_AZ_TAG_FIELD_LBN 5 594*49ef7e06SGarrett D'Amore #define PCRF_AZ_TAG_FIELD_WIDTH 1 595*49ef7e06SGarrett D'Amore #define PCRF_AZ_PHAN_FUNC_LBN 3 596*49ef7e06SGarrett D'Amore #define PCRF_AZ_PHAN_FUNC_WIDTH 2 597*49ef7e06SGarrett D'Amore #define PCRF_AZ_MAX_PAYL_SIZE_SUPT_LBN 0 598*49ef7e06SGarrett D'Amore #define PCRF_AZ_MAX_PAYL_SIZE_SUPT_WIDTH 3 599*49ef7e06SGarrett D'Amore 600*49ef7e06SGarrett D'Amore 601*49ef7e06SGarrett D'Amore /* 602*49ef7e06SGarrett D'Amore * PC_DEV_CTL_REG(16bit): 603*49ef7e06SGarrett D'Amore * PCIe device control register 604*49ef7e06SGarrett D'Amore */ 605*49ef7e06SGarrett D'Amore 606*49ef7e06SGarrett D'Amore #define PCR_AB_DEV_CTL_REG 0x00000068 607*49ef7e06SGarrett D'Amore /* falcona0,falconb0=pci_f0_config */ 608*49ef7e06SGarrett D'Amore 609*49ef7e06SGarrett D'Amore #define PCR_CZ_DEV_CTL_REG 0x00000078 610*49ef7e06SGarrett D'Amore /* sienaa0,hunta0=pci_f0_config */ 611*49ef7e06SGarrett D'Amore 612*49ef7e06SGarrett D'Amore #define PCRF_CZ_FN_LEVEL_RESET_LBN 15 613*49ef7e06SGarrett D'Amore #define PCRF_CZ_FN_LEVEL_RESET_WIDTH 1 614*49ef7e06SGarrett D'Amore #define PCRF_AZ_MAX_RD_REQ_SIZE_LBN 12 615*49ef7e06SGarrett D'Amore #define PCRF_AZ_MAX_RD_REQ_SIZE_WIDTH 3 616*49ef7e06SGarrett D'Amore #define PCFE_AZ_MAX_RD_REQ_SIZE_4096 5 617*49ef7e06SGarrett D'Amore #define PCFE_AZ_MAX_RD_REQ_SIZE_2048 4 618*49ef7e06SGarrett D'Amore #define PCFE_AZ_MAX_RD_REQ_SIZE_1024 3 619*49ef7e06SGarrett D'Amore #define PCFE_AZ_MAX_RD_REQ_SIZE_512 2 620*49ef7e06SGarrett D'Amore #define PCFE_AZ_MAX_RD_REQ_SIZE_256 1 621*49ef7e06SGarrett D'Amore #define PCFE_AZ_MAX_RD_REQ_SIZE_128 0 622*49ef7e06SGarrett D'Amore #define PCRF_AZ_EN_NO_SNOOP_LBN 11 623*49ef7e06SGarrett D'Amore #define PCRF_AZ_EN_NO_SNOOP_WIDTH 1 624*49ef7e06SGarrett D'Amore #define PCRF_AZ_AUX_PWR_PM_EN_LBN 10 625*49ef7e06SGarrett D'Amore #define PCRF_AZ_AUX_PWR_PM_EN_WIDTH 1 626*49ef7e06SGarrett D'Amore #define PCRF_AZ_PHAN_FUNC_EN_LBN 9 627*49ef7e06SGarrett D'Amore #define PCRF_AZ_PHAN_FUNC_EN_WIDTH 1 628*49ef7e06SGarrett D'Amore #define PCRF_AB_DEV_CAP_REG_RSVD0_LBN 8 629*49ef7e06SGarrett D'Amore #define PCRF_AB_DEV_CAP_REG_RSVD0_WIDTH 1 630*49ef7e06SGarrett D'Amore #define PCRF_CZ_EXTENDED_TAG_EN_LBN 8 631*49ef7e06SGarrett D'Amore #define PCRF_CZ_EXTENDED_TAG_EN_WIDTH 1 632*49ef7e06SGarrett D'Amore #define PCRF_AZ_MAX_PAYL_SIZE_LBN 5 633*49ef7e06SGarrett D'Amore #define PCRF_AZ_MAX_PAYL_SIZE_WIDTH 3 634*49ef7e06SGarrett D'Amore #define PCFE_AZ_MAX_PAYL_SIZE_4096 5 635*49ef7e06SGarrett D'Amore #define PCFE_AZ_MAX_PAYL_SIZE_2048 4 636*49ef7e06SGarrett D'Amore #define PCFE_AZ_MAX_PAYL_SIZE_1024 3 637*49ef7e06SGarrett D'Amore #define PCFE_AZ_MAX_PAYL_SIZE_512 2 638*49ef7e06SGarrett D'Amore #define PCFE_AZ_MAX_PAYL_SIZE_256 1 639*49ef7e06SGarrett D'Amore #define PCFE_AZ_MAX_PAYL_SIZE_128 0 640*49ef7e06SGarrett D'Amore #define PCRF_AZ_EN_RELAX_ORDER_LBN 4 641*49ef7e06SGarrett D'Amore #define PCRF_AZ_EN_RELAX_ORDER_WIDTH 1 642*49ef7e06SGarrett D'Amore #define PCRF_AZ_UNSUP_REQ_RPT_EN_LBN 3 643*49ef7e06SGarrett D'Amore #define PCRF_AZ_UNSUP_REQ_RPT_EN_WIDTH 1 644*49ef7e06SGarrett D'Amore #define PCRF_AZ_FATAL_ERR_RPT_EN_LBN 2 645*49ef7e06SGarrett D'Amore #define PCRF_AZ_FATAL_ERR_RPT_EN_WIDTH 1 646*49ef7e06SGarrett D'Amore #define PCRF_AZ_NONFATAL_ERR_RPT_EN_LBN 1 647*49ef7e06SGarrett D'Amore #define PCRF_AZ_NONFATAL_ERR_RPT_EN_WIDTH 1 648*49ef7e06SGarrett D'Amore #define PCRF_AZ_CORR_ERR_RPT_EN_LBN 0 649*49ef7e06SGarrett D'Amore #define PCRF_AZ_CORR_ERR_RPT_EN_WIDTH 1 650*49ef7e06SGarrett D'Amore 651*49ef7e06SGarrett D'Amore 652*49ef7e06SGarrett D'Amore /* 653*49ef7e06SGarrett D'Amore * PC_DEV_STAT_REG(16bit): 654*49ef7e06SGarrett D'Amore * PCIe device status register 655*49ef7e06SGarrett D'Amore */ 656*49ef7e06SGarrett D'Amore 657*49ef7e06SGarrett D'Amore #define PCR_AB_DEV_STAT_REG 0x0000006a 658*49ef7e06SGarrett D'Amore /* falcona0,falconb0=pci_f0_config */ 659*49ef7e06SGarrett D'Amore 660*49ef7e06SGarrett D'Amore #define PCR_CZ_DEV_STAT_REG 0x0000007a 661*49ef7e06SGarrett D'Amore /* sienaa0,hunta0=pci_f0_config */ 662*49ef7e06SGarrett D'Amore 663*49ef7e06SGarrett D'Amore #define PCRF_AZ_TRNS_PEND_LBN 5 664*49ef7e06SGarrett D'Amore #define PCRF_AZ_TRNS_PEND_WIDTH 1 665*49ef7e06SGarrett D'Amore #define PCRF_AZ_AUX_PWR_DET_LBN 4 666*49ef7e06SGarrett D'Amore #define PCRF_AZ_AUX_PWR_DET_WIDTH 1 667*49ef7e06SGarrett D'Amore #define PCRF_AZ_UNSUP_REQ_DET_LBN 3 668*49ef7e06SGarrett D'Amore #define PCRF_AZ_UNSUP_REQ_DET_WIDTH 1 669*49ef7e06SGarrett D'Amore #define PCRF_AZ_FATAL_ERR_DET_LBN 2 670*49ef7e06SGarrett D'Amore #define PCRF_AZ_FATAL_ERR_DET_WIDTH 1 671*49ef7e06SGarrett D'Amore #define PCRF_AZ_NONFATAL_ERR_DET_LBN 1 672*49ef7e06SGarrett D'Amore #define PCRF_AZ_NONFATAL_ERR_DET_WIDTH 1 673*49ef7e06SGarrett D'Amore #define PCRF_AZ_CORR_ERR_DET_LBN 0 674*49ef7e06SGarrett D'Amore #define PCRF_AZ_CORR_ERR_DET_WIDTH 1 675*49ef7e06SGarrett D'Amore 676*49ef7e06SGarrett D'Amore 677*49ef7e06SGarrett D'Amore /* 678*49ef7e06SGarrett D'Amore * PC_LNK_CAP_REG(32bit): 679*49ef7e06SGarrett D'Amore * PCIe link capabilities register 680*49ef7e06SGarrett D'Amore */ 681*49ef7e06SGarrett D'Amore 682*49ef7e06SGarrett D'Amore #define PCR_AB_LNK_CAP_REG 0x0000006c 683*49ef7e06SGarrett D'Amore /* falcona0,falconb0=pci_f0_config */ 684*49ef7e06SGarrett D'Amore 685*49ef7e06SGarrett D'Amore #define PCR_CZ_LNK_CAP_REG 0x0000007c 686*49ef7e06SGarrett D'Amore /* sienaa0,hunta0=pci_f0_config */ 687*49ef7e06SGarrett D'Amore 688*49ef7e06SGarrett D'Amore #define PCRF_AZ_PORT_NUM_LBN 24 689*49ef7e06SGarrett D'Amore #define PCRF_AZ_PORT_NUM_WIDTH 8 690*49ef7e06SGarrett D'Amore #define PCRF_DZ_ASPM_OPTIONALITY_CAP_LBN 22 691*49ef7e06SGarrett D'Amore #define PCRF_DZ_ASPM_OPTIONALITY_CAP_WIDTH 1 692*49ef7e06SGarrett D'Amore #define PCRF_CZ_LINK_BWDITH_NOTIF_CAP_LBN 21 693*49ef7e06SGarrett D'Amore #define PCRF_CZ_LINK_BWDITH_NOTIF_CAP_WIDTH 1 694*49ef7e06SGarrett D'Amore #define PCRF_CZ_DATA_LINK_ACTIVE_RPT_CAP_LBN 20 695*49ef7e06SGarrett D'Amore #define PCRF_CZ_DATA_LINK_ACTIVE_RPT_CAP_WIDTH 1 696*49ef7e06SGarrett D'Amore #define PCRF_CZ_SURPISE_DOWN_RPT_CAP_LBN 19 697*49ef7e06SGarrett D'Amore #define PCRF_CZ_SURPISE_DOWN_RPT_CAP_WIDTH 1 698*49ef7e06SGarrett D'Amore #define PCRF_CZ_CLOCK_PWR_MNGMNT_CAP_LBN 18 699*49ef7e06SGarrett D'Amore #define PCRF_CZ_CLOCK_PWR_MNGMNT_CAP_WIDTH 1 700*49ef7e06SGarrett D'Amore #define PCRF_AZ_DEF_L1_EXIT_LAT_LBN 15 701*49ef7e06SGarrett D'Amore #define PCRF_AZ_DEF_L1_EXIT_LAT_WIDTH 3 702*49ef7e06SGarrett D'Amore #define PCRF_AZ_DEF_L0_EXIT_LATPORT_NUM_LBN 12 703*49ef7e06SGarrett D'Amore #define PCRF_AZ_DEF_L0_EXIT_LATPORT_NUM_WIDTH 3 704*49ef7e06SGarrett D'Amore #define PCRF_AZ_AS_LNK_PM_SUPT_LBN 10 705*49ef7e06SGarrett D'Amore #define PCRF_AZ_AS_LNK_PM_SUPT_WIDTH 2 706*49ef7e06SGarrett D'Amore #define PCRF_AZ_MAX_LNK_WIDTH_LBN 4 707*49ef7e06SGarrett D'Amore #define PCRF_AZ_MAX_LNK_WIDTH_WIDTH 6 708*49ef7e06SGarrett D'Amore #define PCRF_AZ_MAX_LNK_SP_LBN 0 709*49ef7e06SGarrett D'Amore #define PCRF_AZ_MAX_LNK_SP_WIDTH 4 710*49ef7e06SGarrett D'Amore 711*49ef7e06SGarrett D'Amore 712*49ef7e06SGarrett D'Amore /* 713*49ef7e06SGarrett D'Amore * PC_LNK_CTL_REG(16bit): 714*49ef7e06SGarrett D'Amore * PCIe link control register 715*49ef7e06SGarrett D'Amore */ 716*49ef7e06SGarrett D'Amore 717*49ef7e06SGarrett D'Amore #define PCR_AB_LNK_CTL_REG 0x00000070 718*49ef7e06SGarrett D'Amore /* falcona0,falconb0=pci_f0_config */ 719*49ef7e06SGarrett D'Amore 720*49ef7e06SGarrett D'Amore #define PCR_CZ_LNK_CTL_REG 0x00000080 721*49ef7e06SGarrett D'Amore /* sienaa0,hunta0=pci_f0_config */ 722*49ef7e06SGarrett D'Amore 723*49ef7e06SGarrett D'Amore #define PCRF_AZ_EXT_SYNC_LBN 7 724*49ef7e06SGarrett D'Amore #define PCRF_AZ_EXT_SYNC_WIDTH 1 725*49ef7e06SGarrett D'Amore #define PCRF_AZ_COMM_CLK_CFG_LBN 6 726*49ef7e06SGarrett D'Amore #define PCRF_AZ_COMM_CLK_CFG_WIDTH 1 727*49ef7e06SGarrett D'Amore #define PCRF_AB_LNK_CTL_REG_RSVD0_LBN 5 728*49ef7e06SGarrett D'Amore #define PCRF_AB_LNK_CTL_REG_RSVD0_WIDTH 1 729*49ef7e06SGarrett D'Amore #define PCRF_CZ_LNK_RETRAIN_LBN 5 730*49ef7e06SGarrett D'Amore #define PCRF_CZ_LNK_RETRAIN_WIDTH 1 731*49ef7e06SGarrett D'Amore #define PCRF_AZ_LNK_DIS_LBN 4 732*49ef7e06SGarrett D'Amore #define PCRF_AZ_LNK_DIS_WIDTH 1 733*49ef7e06SGarrett D'Amore #define PCRF_AZ_RD_COM_BDRY_LBN 3 734*49ef7e06SGarrett D'Amore #define PCRF_AZ_RD_COM_BDRY_WIDTH 1 735*49ef7e06SGarrett D'Amore #define PCRF_AZ_ACT_ST_LNK_PM_CTL_LBN 0 736*49ef7e06SGarrett D'Amore #define PCRF_AZ_ACT_ST_LNK_PM_CTL_WIDTH 2 737*49ef7e06SGarrett D'Amore 738*49ef7e06SGarrett D'Amore 739*49ef7e06SGarrett D'Amore /* 740*49ef7e06SGarrett D'Amore * PC_LNK_STAT_REG(16bit): 741*49ef7e06SGarrett D'Amore * PCIe link status register 742*49ef7e06SGarrett D'Amore */ 743*49ef7e06SGarrett D'Amore 744*49ef7e06SGarrett D'Amore #define PCR_AB_LNK_STAT_REG 0x00000072 745*49ef7e06SGarrett D'Amore /* falcona0,falconb0=pci_f0_config */ 746*49ef7e06SGarrett D'Amore 747*49ef7e06SGarrett D'Amore #define PCR_CZ_LNK_STAT_REG 0x00000082 748*49ef7e06SGarrett D'Amore /* sienaa0,hunta0=pci_f0_config */ 749*49ef7e06SGarrett D'Amore 750*49ef7e06SGarrett D'Amore #define PCRF_AZ_SLOT_CLK_CFG_LBN 12 751*49ef7e06SGarrett D'Amore #define PCRF_AZ_SLOT_CLK_CFG_WIDTH 1 752*49ef7e06SGarrett D'Amore #define PCRF_AZ_LNK_TRAIN_LBN 11 753*49ef7e06SGarrett D'Amore #define PCRF_AZ_LNK_TRAIN_WIDTH 1 754*49ef7e06SGarrett D'Amore #define PCRF_AB_TRAIN_ERR_LBN 10 755*49ef7e06SGarrett D'Amore #define PCRF_AB_TRAIN_ERR_WIDTH 1 756*49ef7e06SGarrett D'Amore #define PCRF_AZ_LNK_WIDTH_LBN 4 757*49ef7e06SGarrett D'Amore #define PCRF_AZ_LNK_WIDTH_WIDTH 6 758*49ef7e06SGarrett D'Amore #define PCRF_AZ_LNK_SP_LBN 0 759*49ef7e06SGarrett D'Amore #define PCRF_AZ_LNK_SP_WIDTH 4 760*49ef7e06SGarrett D'Amore 761*49ef7e06SGarrett D'Amore 762*49ef7e06SGarrett D'Amore /* 763*49ef7e06SGarrett D'Amore * PC_SLOT_CAP_REG(32bit): 764*49ef7e06SGarrett D'Amore * PCIe slot capabilities register 765*49ef7e06SGarrett D'Amore */ 766*49ef7e06SGarrett D'Amore 767*49ef7e06SGarrett D'Amore #define PCR_AB_SLOT_CAP_REG 0x00000074 768*49ef7e06SGarrett D'Amore /* falcona0,falconb0=pci_f0_config */ 769*49ef7e06SGarrett D'Amore 770*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_NUM_LBN 19 771*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_NUM_WIDTH 13 772*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_PWR_LIM_SCL_LBN 15 773*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_PWR_LIM_SCL_WIDTH 2 774*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_PWR_LIM_VAL_LBN 7 775*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_PWR_LIM_VAL_WIDTH 8 776*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_HP_CAP_LBN 6 777*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_HP_CAP_WIDTH 1 778*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_HP_SURP_LBN 5 779*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_HP_SURP_WIDTH 1 780*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_PWR_IND_PRST_LBN 4 781*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_PWR_IND_PRST_WIDTH 1 782*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_ATTN_IND_PRST_LBN 3 783*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_ATTN_IND_PRST_WIDTH 1 784*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_MRL_SENS_PRST_LBN 2 785*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_MRL_SENS_PRST_WIDTH 1 786*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_PWR_CTL_PRST_LBN 1 787*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_PWR_CTL_PRST_WIDTH 1 788*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_ATTN_BUT_PRST_LBN 0 789*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_ATTN_BUT_PRST_WIDTH 1 790*49ef7e06SGarrett D'Amore 791*49ef7e06SGarrett D'Amore 792*49ef7e06SGarrett D'Amore /* 793*49ef7e06SGarrett D'Amore * PC_SLOT_CTL_REG(16bit): 794*49ef7e06SGarrett D'Amore * PCIe slot control register 795*49ef7e06SGarrett D'Amore */ 796*49ef7e06SGarrett D'Amore 797*49ef7e06SGarrett D'Amore #define PCR_AB_SLOT_CTL_REG 0x00000078 798*49ef7e06SGarrett D'Amore /* falcona0,falconb0=pci_f0_config */ 799*49ef7e06SGarrett D'Amore 800*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_PWR_CTLR_CTL_LBN 10 801*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_PWR_CTLR_CTL_WIDTH 1 802*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_PWR_IND_CTL_LBN 8 803*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_PWR_IND_CTL_WIDTH 2 804*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_ATT_IND_CTL_LBN 6 805*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_ATT_IND_CTL_WIDTH 2 806*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_HP_INT_EN_LBN 5 807*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_HP_INT_EN_WIDTH 1 808*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_CMD_COMP_INT_EN_LBN 4 809*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_CMD_COMP_INT_EN_WIDTH 1 810*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_PRES_DET_CHG_EN_LBN 3 811*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_PRES_DET_CHG_EN_WIDTH 1 812*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_MRL_SENS_CHG_EN_LBN 2 813*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_MRL_SENS_CHG_EN_WIDTH 1 814*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_PWR_FLTDET_EN_LBN 1 815*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_PWR_FLTDET_EN_WIDTH 1 816*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_ATTN_BUT_EN_LBN 0 817*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_ATTN_BUT_EN_WIDTH 1 818*49ef7e06SGarrett D'Amore 819*49ef7e06SGarrett D'Amore 820*49ef7e06SGarrett D'Amore /* 821*49ef7e06SGarrett D'Amore * PC_SLOT_STAT_REG(16bit): 822*49ef7e06SGarrett D'Amore * PCIe slot status register 823*49ef7e06SGarrett D'Amore */ 824*49ef7e06SGarrett D'Amore 825*49ef7e06SGarrett D'Amore #define PCR_AB_SLOT_STAT_REG 0x0000007a 826*49ef7e06SGarrett D'Amore /* falcona0,falconb0=pci_f0_config */ 827*49ef7e06SGarrett D'Amore 828*49ef7e06SGarrett D'Amore #define PCRF_AB_PRES_DET_ST_LBN 6 829*49ef7e06SGarrett D'Amore #define PCRF_AB_PRES_DET_ST_WIDTH 1 830*49ef7e06SGarrett D'Amore #define PCRF_AB_MRL_SENS_ST_LBN 5 831*49ef7e06SGarrett D'Amore #define PCRF_AB_MRL_SENS_ST_WIDTH 1 832*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_PWR_IND_LBN 4 833*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_PWR_IND_WIDTH 1 834*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_ATTN_IND_LBN 3 835*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_ATTN_IND_WIDTH 1 836*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_MRL_SENS_LBN 2 837*49ef7e06SGarrett D'Amore #define PCRF_AB_SLOT_MRL_SENS_WIDTH 1 838*49ef7e06SGarrett D'Amore #define PCRF_AB_PWR_FLTDET_LBN 1 839*49ef7e06SGarrett D'Amore #define PCRF_AB_PWR_FLTDET_WIDTH 1 840*49ef7e06SGarrett D'Amore #define PCRF_AB_ATTN_BUTDET_LBN 0 841*49ef7e06SGarrett D'Amore #define PCRF_AB_ATTN_BUTDET_WIDTH 1 842*49ef7e06SGarrett D'Amore 843*49ef7e06SGarrett D'Amore 844*49ef7e06SGarrett D'Amore /* 845*49ef7e06SGarrett D'Amore * PC_MSIX_CAP_ID_REG(8bit): 846*49ef7e06SGarrett D'Amore * MSIX Capability ID 847*49ef7e06SGarrett D'Amore */ 848*49ef7e06SGarrett D'Amore 849*49ef7e06SGarrett D'Amore #define PCR_BB_MSIX_CAP_ID_REG 0x00000090 850*49ef7e06SGarrett D'Amore /* falconb0=pci_f0_config */ 851*49ef7e06SGarrett D'Amore 852*49ef7e06SGarrett D'Amore #define PCR_CZ_MSIX_CAP_ID_REG 0x000000b0 853*49ef7e06SGarrett D'Amore /* sienaa0,hunta0=pci_f0_config */ 854*49ef7e06SGarrett D'Amore 855*49ef7e06SGarrett D'Amore #define PCRF_BZ_MSIX_CAP_ID_LBN 0 856*49ef7e06SGarrett D'Amore #define PCRF_BZ_MSIX_CAP_ID_WIDTH 8 857*49ef7e06SGarrett D'Amore 858*49ef7e06SGarrett D'Amore 859*49ef7e06SGarrett D'Amore /* 860*49ef7e06SGarrett D'Amore * PC_MSIX_NXT_PTR_REG(8bit): 861*49ef7e06SGarrett D'Amore * MSIX Capability Next Capability Ptr 862*49ef7e06SGarrett D'Amore */ 863*49ef7e06SGarrett D'Amore 864*49ef7e06SGarrett D'Amore #define PCR_BB_MSIX_NXT_PTR_REG 0x00000091 865*49ef7e06SGarrett D'Amore /* falconb0=pci_f0_config */ 866*49ef7e06SGarrett D'Amore 867*49ef7e06SGarrett D'Amore #define PCR_CZ_MSIX_NXT_PTR_REG 0x000000b1 868*49ef7e06SGarrett D'Amore /* sienaa0,hunta0=pci_f0_config */ 869*49ef7e06SGarrett D'Amore 870*49ef7e06SGarrett D'Amore #define PCRF_BZ_MSIX_NXT_PTR_LBN 0 871*49ef7e06SGarrett D'Amore #define PCRF_BZ_MSIX_NXT_PTR_WIDTH 8 872*49ef7e06SGarrett D'Amore 873*49ef7e06SGarrett D'Amore 874*49ef7e06SGarrett D'Amore /* 875*49ef7e06SGarrett D'Amore * PC_MSIX_CTL_REG(16bit): 876*49ef7e06SGarrett D'Amore * MSIX control register 877*49ef7e06SGarrett D'Amore */ 878*49ef7e06SGarrett D'Amore 879*49ef7e06SGarrett D'Amore #define PCR_BB_MSIX_CTL_REG 0x00000092 880*49ef7e06SGarrett D'Amore /* falconb0=pci_f0_config */ 881*49ef7e06SGarrett D'Amore 882*49ef7e06SGarrett D'Amore #define PCR_CZ_MSIX_CTL_REG 0x000000b2 883*49ef7e06SGarrett D'Amore /* sienaa0,hunta0=pci_f0_config */ 884*49ef7e06SGarrett D'Amore 885*49ef7e06SGarrett D'Amore #define PCRF_BZ_MSIX_EN_LBN 15 886*49ef7e06SGarrett D'Amore #define PCRF_BZ_MSIX_EN_WIDTH 1 887*49ef7e06SGarrett D'Amore #define PCRF_BZ_MSIX_FUNC_MASK_LBN 14 888*49ef7e06SGarrett D'Amore #define PCRF_BZ_MSIX_FUNC_MASK_WIDTH 1 889*49ef7e06SGarrett D'Amore #define PCRF_BZ_MSIX_TBL_SIZE_LBN 0 890*49ef7e06SGarrett D'Amore #define PCRF_BZ_MSIX_TBL_SIZE_WIDTH 11 891*49ef7e06SGarrett D'Amore 892*49ef7e06SGarrett D'Amore 893*49ef7e06SGarrett D'Amore /* 894*49ef7e06SGarrett D'Amore * PC_MSIX_TBL_BASE_REG(32bit): 895*49ef7e06SGarrett D'Amore * MSIX Capability Vector Table Base 896*49ef7e06SGarrett D'Amore */ 897*49ef7e06SGarrett D'Amore 898*49ef7e06SGarrett D'Amore #define PCR_BB_MSIX_TBL_BASE_REG 0x00000094 899*49ef7e06SGarrett D'Amore /* falconb0=pci_f0_config */ 900*49ef7e06SGarrett D'Amore 901*49ef7e06SGarrett D'Amore #define PCR_CZ_MSIX_TBL_BASE_REG 0x000000b4 902*49ef7e06SGarrett D'Amore /* sienaa0,hunta0=pci_f0_config */ 903*49ef7e06SGarrett D'Amore 904*49ef7e06SGarrett D'Amore #define PCRF_BZ_MSIX_TBL_OFF_LBN 3 905*49ef7e06SGarrett D'Amore #define PCRF_BZ_MSIX_TBL_OFF_WIDTH 29 906*49ef7e06SGarrett D'Amore #define PCRF_BZ_MSIX_TBL_BIR_LBN 0 907*49ef7e06SGarrett D'Amore #define PCRF_BZ_MSIX_TBL_BIR_WIDTH 3 908*49ef7e06SGarrett D'Amore 909*49ef7e06SGarrett D'Amore 910*49ef7e06SGarrett D'Amore /* 911*49ef7e06SGarrett D'Amore * PC_DEV_CAP2_REG(32bit): 912*49ef7e06SGarrett D'Amore * PCIe Device Capabilities 2 913*49ef7e06SGarrett D'Amore */ 914*49ef7e06SGarrett D'Amore 915*49ef7e06SGarrett D'Amore #define PCR_CZ_DEV_CAP2_REG 0x00000094 916*49ef7e06SGarrett D'Amore /* sienaa0=pci_f0_config,hunta0=pci_f0_config */ 917*49ef7e06SGarrett D'Amore 918*49ef7e06SGarrett D'Amore #define PCRF_DZ_OBFF_SUPPORTED_LBN 18 919*49ef7e06SGarrett D'Amore #define PCRF_DZ_OBFF_SUPPORTED_WIDTH 2 920*49ef7e06SGarrett D'Amore #define PCRF_DZ_TPH_CMPL_SUPPORTED_LBN 12 921*49ef7e06SGarrett D'Amore #define PCRF_DZ_TPH_CMPL_SUPPORTED_WIDTH 2 922*49ef7e06SGarrett D'Amore #define PCRF_DZ_LTR_M_SUPPORTED_LBN 11 923*49ef7e06SGarrett D'Amore #define PCRF_DZ_LTR_M_SUPPORTED_WIDTH 1 924*49ef7e06SGarrett D'Amore #define PCRF_CC_CMPL_TIMEOUT_DIS_LBN 4 925*49ef7e06SGarrett D'Amore #define PCRF_CC_CMPL_TIMEOUT_DIS_WIDTH 1 926*49ef7e06SGarrett D'Amore #define PCRF_DZ_CMPL_TIMEOUT_DIS_SUPPORTED_LBN 4 927*49ef7e06SGarrett D'Amore #define PCRF_DZ_CMPL_TIMEOUT_DIS_SUPPORTED_WIDTH 1 928*49ef7e06SGarrett D'Amore #define PCRF_CZ_CMPL_TIMEOUT_LBN 0 929*49ef7e06SGarrett D'Amore #define PCRF_CZ_CMPL_TIMEOUT_WIDTH 4 930*49ef7e06SGarrett D'Amore #define PCFE_CZ_CMPL_TIMEOUT_17000_TO_6400MS 14 931*49ef7e06SGarrett D'Amore #define PCFE_CZ_CMPL_TIMEOUT_4000_TO_1300MS 13 932*49ef7e06SGarrett D'Amore #define PCFE_CZ_CMPL_TIMEOUT_1000_TO_3500MS 10 933*49ef7e06SGarrett D'Amore #define PCFE_CZ_CMPL_TIMEOUT_260_TO_900MS 9 934*49ef7e06SGarrett D'Amore #define PCFE_CZ_CMPL_TIMEOUT_65_TO_210MS 6 935*49ef7e06SGarrett D'Amore #define PCFE_CZ_CMPL_TIMEOUT_16_TO_55MS 5 936*49ef7e06SGarrett D'Amore #define PCFE_CZ_CMPL_TIMEOUT_1_TO_10MS 2 937*49ef7e06SGarrett D'Amore #define PCFE_CZ_CMPL_TIMEOUT_50_TO_100US 1 938*49ef7e06SGarrett D'Amore #define PCFE_CZ_CMPL_TIMEOUT_DEFAULT 0 939*49ef7e06SGarrett D'Amore 940*49ef7e06SGarrett D'Amore 941*49ef7e06SGarrett D'Amore /* 942*49ef7e06SGarrett D'Amore * PC_DEV_CTL2_REG(16bit): 943*49ef7e06SGarrett D'Amore * PCIe Device Control 2 944*49ef7e06SGarrett D'Amore */ 945*49ef7e06SGarrett D'Amore 946*49ef7e06SGarrett D'Amore #define PCR_CZ_DEV_CTL2_REG 0x00000098 947*49ef7e06SGarrett D'Amore /* sienaa0,hunta0=pci_f0_config */ 948*49ef7e06SGarrett D'Amore 949*49ef7e06SGarrett D'Amore #define PCRF_DZ_OBFF_ENABLE_LBN 13 950*49ef7e06SGarrett D'Amore #define PCRF_DZ_OBFF_ENABLE_WIDTH 2 951*49ef7e06SGarrett D'Amore #define PCRF_DZ_LTR_ENABLE_LBN 10 952*49ef7e06SGarrett D'Amore #define PCRF_DZ_LTR_ENABLE_WIDTH 1 953*49ef7e06SGarrett D'Amore #define PCRF_DZ_IDO_COMPLETION_ENABLE_LBN 9 954*49ef7e06SGarrett D'Amore #define PCRF_DZ_IDO_COMPLETION_ENABLE_WIDTH 1 955*49ef7e06SGarrett D'Amore #define PCRF_DZ_IDO_REQUEST_ENABLE_LBN 8 956*49ef7e06SGarrett D'Amore #define PCRF_DZ_IDO_REQUEST_ENABLE_WIDTH 1 957*49ef7e06SGarrett D'Amore #define PCRF_CZ_CMPL_TIMEOUT_DIS_CTL_LBN 4 958*49ef7e06SGarrett D'Amore #define PCRF_CZ_CMPL_TIMEOUT_DIS_CTL_WIDTH 1 959*49ef7e06SGarrett D'Amore #define PCRF_CZ_CMPL_TIMEOUT_CTL_LBN 0 960*49ef7e06SGarrett D'Amore #define PCRF_CZ_CMPL_TIMEOUT_CTL_WIDTH 4 961*49ef7e06SGarrett D'Amore 962*49ef7e06SGarrett D'Amore 963*49ef7e06SGarrett D'Amore /* 964*49ef7e06SGarrett D'Amore * PC_MSIX_PBA_BASE_REG(32bit): 965*49ef7e06SGarrett D'Amore * MSIX Capability PBA Base 966*49ef7e06SGarrett D'Amore */ 967*49ef7e06SGarrett D'Amore 968*49ef7e06SGarrett D'Amore #define PCR_BB_MSIX_PBA_BASE_REG 0x00000098 969*49ef7e06SGarrett D'Amore /* falconb0=pci_f0_config */ 970*49ef7e06SGarrett D'Amore 971*49ef7e06SGarrett D'Amore #define PCR_CZ_MSIX_PBA_BASE_REG 0x000000b8 972*49ef7e06SGarrett D'Amore /* sienaa0,hunta0=pci_f0_config */ 973*49ef7e06SGarrett D'Amore 974*49ef7e06SGarrett D'Amore #define PCRF_BZ_MSIX_PBA_OFF_LBN 3 975*49ef7e06SGarrett D'Amore #define PCRF_BZ_MSIX_PBA_OFF_WIDTH 29 976*49ef7e06SGarrett D'Amore #define PCRF_BZ_MSIX_PBA_BIR_LBN 0 977*49ef7e06SGarrett D'Amore #define PCRF_BZ_MSIX_PBA_BIR_WIDTH 3 978*49ef7e06SGarrett D'Amore 979*49ef7e06SGarrett D'Amore 980*49ef7e06SGarrett D'Amore /* 981*49ef7e06SGarrett D'Amore * PC_LNK_CAP2_REG(32bit): 982*49ef7e06SGarrett D'Amore * PCIe Link Capability 2 983*49ef7e06SGarrett D'Amore */ 984*49ef7e06SGarrett D'Amore 985*49ef7e06SGarrett D'Amore #define PCR_DZ_LNK_CAP2_REG 0x0000009c 986*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 987*49ef7e06SGarrett D'Amore 988*49ef7e06SGarrett D'Amore #define PCRF_DZ_LNK_SPEED_SUP_LBN 1 989*49ef7e06SGarrett D'Amore #define PCRF_DZ_LNK_SPEED_SUP_WIDTH 7 990*49ef7e06SGarrett D'Amore 991*49ef7e06SGarrett D'Amore 992*49ef7e06SGarrett D'Amore /* 993*49ef7e06SGarrett D'Amore * PC_LNK_CTL2_REG(16bit): 994*49ef7e06SGarrett D'Amore * PCIe Link Control 2 995*49ef7e06SGarrett D'Amore */ 996*49ef7e06SGarrett D'Amore 997*49ef7e06SGarrett D'Amore #define PCR_CZ_LNK_CTL2_REG 0x000000a0 998*49ef7e06SGarrett D'Amore /* sienaa0,hunta0=pci_f0_config */ 999*49ef7e06SGarrett D'Amore 1000*49ef7e06SGarrett D'Amore #define PCRF_CZ_POLLING_DEEMPH_LVL_LBN 12 1001*49ef7e06SGarrett D'Amore #define PCRF_CZ_POLLING_DEEMPH_LVL_WIDTH 1 1002*49ef7e06SGarrett D'Amore #define PCRF_CZ_COMPLIANCE_SOS_CTL_LBN 11 1003*49ef7e06SGarrett D'Amore #define PCRF_CZ_COMPLIANCE_SOS_CTL_WIDTH 1 1004*49ef7e06SGarrett D'Amore #define PCRF_CZ_ENTER_MODIFIED_COMPLIANCE_CTL_LBN 10 1005*49ef7e06SGarrett D'Amore #define PCRF_CZ_ENTER_MODIFIED_COMPLIANCE_CTL_WIDTH 1 1006*49ef7e06SGarrett D'Amore #define PCRF_CZ_TRANSMIT_MARGIN_LBN 7 1007*49ef7e06SGarrett D'Amore #define PCRF_CZ_TRANSMIT_MARGIN_WIDTH 3 1008*49ef7e06SGarrett D'Amore #define PCRF_CZ_SELECT_DEEMPH_LBN 6 1009*49ef7e06SGarrett D'Amore #define PCRF_CZ_SELECT_DEEMPH_WIDTH 1 1010*49ef7e06SGarrett D'Amore #define PCRF_CZ_HW_AUTONOMOUS_SPEED_DIS_LBN 5 1011*49ef7e06SGarrett D'Amore #define PCRF_CZ_HW_AUTONOMOUS_SPEED_DIS_WIDTH 1 1012*49ef7e06SGarrett D'Amore #define PCRF_CZ_ENTER_COMPLIANCE_CTL_LBN 4 1013*49ef7e06SGarrett D'Amore #define PCRF_CZ_ENTER_COMPLIANCE_CTL_WIDTH 1 1014*49ef7e06SGarrett D'Amore #define PCRF_CZ_TGT_LNK_SPEED_CTL_LBN 0 1015*49ef7e06SGarrett D'Amore #define PCRF_CZ_TGT_LNK_SPEED_CTL_WIDTH 4 1016*49ef7e06SGarrett D'Amore #define PCFE_DZ_LCTL2_TGT_SPEED_GEN3 3 1017*49ef7e06SGarrett D'Amore #define PCFE_DZ_LCTL2_TGT_SPEED_GEN2 2 1018*49ef7e06SGarrett D'Amore #define PCFE_DZ_LCTL2_TGT_SPEED_GEN1 1 1019*49ef7e06SGarrett D'Amore 1020*49ef7e06SGarrett D'Amore 1021*49ef7e06SGarrett D'Amore /* 1022*49ef7e06SGarrett D'Amore * PC_LNK_STAT2_REG(16bit): 1023*49ef7e06SGarrett D'Amore * PCIe Link Status 2 1024*49ef7e06SGarrett D'Amore */ 1025*49ef7e06SGarrett D'Amore 1026*49ef7e06SGarrett D'Amore #define PCR_CZ_LNK_STAT2_REG 0x000000a2 1027*49ef7e06SGarrett D'Amore /* sienaa0,hunta0=pci_f0_config */ 1028*49ef7e06SGarrett D'Amore 1029*49ef7e06SGarrett D'Amore #define PCRF_CZ_CURRENT_DEEMPH_LBN 0 1030*49ef7e06SGarrett D'Amore #define PCRF_CZ_CURRENT_DEEMPH_WIDTH 1 1031*49ef7e06SGarrett D'Amore 1032*49ef7e06SGarrett D'Amore 1033*49ef7e06SGarrett D'Amore /* 1034*49ef7e06SGarrett D'Amore * PC_VPD_CAP_ID_REG(8bit): 1035*49ef7e06SGarrett D'Amore * VPD data register 1036*49ef7e06SGarrett D'Amore */ 1037*49ef7e06SGarrett D'Amore 1038*49ef7e06SGarrett D'Amore #define PCR_AB_VPD_CAP_ID_REG 0x000000b0 1039*49ef7e06SGarrett D'Amore /* falcona0,falconb0=pci_f0_config */ 1040*49ef7e06SGarrett D'Amore 1041*49ef7e06SGarrett D'Amore #define PCRF_AB_VPD_CAP_ID_LBN 0 1042*49ef7e06SGarrett D'Amore #define PCRF_AB_VPD_CAP_ID_WIDTH 8 1043*49ef7e06SGarrett D'Amore 1044*49ef7e06SGarrett D'Amore 1045*49ef7e06SGarrett D'Amore /* 1046*49ef7e06SGarrett D'Amore * PC_VPD_NXT_PTR_REG(8bit): 1047*49ef7e06SGarrett D'Amore * VPD next item pointer 1048*49ef7e06SGarrett D'Amore */ 1049*49ef7e06SGarrett D'Amore 1050*49ef7e06SGarrett D'Amore #define PCR_AB_VPD_NXT_PTR_REG 0x000000b1 1051*49ef7e06SGarrett D'Amore /* falcona0,falconb0=pci_f0_config */ 1052*49ef7e06SGarrett D'Amore 1053*49ef7e06SGarrett D'Amore #define PCRF_AB_VPD_NXT_PTR_LBN 0 1054*49ef7e06SGarrett D'Amore #define PCRF_AB_VPD_NXT_PTR_WIDTH 8 1055*49ef7e06SGarrett D'Amore 1056*49ef7e06SGarrett D'Amore 1057*49ef7e06SGarrett D'Amore /* 1058*49ef7e06SGarrett D'Amore * PC_VPD_ADDR_REG(16bit): 1059*49ef7e06SGarrett D'Amore * VPD address register 1060*49ef7e06SGarrett D'Amore */ 1061*49ef7e06SGarrett D'Amore 1062*49ef7e06SGarrett D'Amore #define PCR_AB_VPD_ADDR_REG 0x000000b2 1063*49ef7e06SGarrett D'Amore /* falcona0,falconb0=pci_f0_config */ 1064*49ef7e06SGarrett D'Amore 1065*49ef7e06SGarrett D'Amore #define PCRF_AB_VPD_FLAG_LBN 15 1066*49ef7e06SGarrett D'Amore #define PCRF_AB_VPD_FLAG_WIDTH 1 1067*49ef7e06SGarrett D'Amore #define PCRF_AB_VPD_ADDR_LBN 0 1068*49ef7e06SGarrett D'Amore #define PCRF_AB_VPD_ADDR_WIDTH 15 1069*49ef7e06SGarrett D'Amore 1070*49ef7e06SGarrett D'Amore 1071*49ef7e06SGarrett D'Amore /* 1072*49ef7e06SGarrett D'Amore * PC_VPD_CAP_DATA_REG(32bit): 1073*49ef7e06SGarrett D'Amore * documentation to be written for sum_PC_VPD_CAP_DATA_REG 1074*49ef7e06SGarrett D'Amore */ 1075*49ef7e06SGarrett D'Amore 1076*49ef7e06SGarrett D'Amore #define PCR_AB_VPD_CAP_DATA_REG 0x000000b4 1077*49ef7e06SGarrett D'Amore /* falcona0,falconb0=pci_f0_config */ 1078*49ef7e06SGarrett D'Amore 1079*49ef7e06SGarrett D'Amore #define PCR_CZ_VPD_CAP_DATA_REG 0x000000d4 1080*49ef7e06SGarrett D'Amore /* sienaa0,hunta0=pci_f0_config */ 1081*49ef7e06SGarrett D'Amore 1082*49ef7e06SGarrett D'Amore #define PCRF_AZ_VPD_DATA_LBN 0 1083*49ef7e06SGarrett D'Amore #define PCRF_AZ_VPD_DATA_WIDTH 32 1084*49ef7e06SGarrett D'Amore 1085*49ef7e06SGarrett D'Amore 1086*49ef7e06SGarrett D'Amore /* 1087*49ef7e06SGarrett D'Amore * PC_VPD_CAP_CTL_REG(8bit): 1088*49ef7e06SGarrett D'Amore * VPD control and capabilities register 1089*49ef7e06SGarrett D'Amore */ 1090*49ef7e06SGarrett D'Amore 1091*49ef7e06SGarrett D'Amore #define PCR_CZ_VPD_CAP_CTL_REG 0x000000d0 1092*49ef7e06SGarrett D'Amore /* sienaa0,hunta0=pci_f0_config */ 1093*49ef7e06SGarrett D'Amore 1094*49ef7e06SGarrett D'Amore #define PCRF_CZ_VPD_FLAG_LBN 31 1095*49ef7e06SGarrett D'Amore #define PCRF_CZ_VPD_FLAG_WIDTH 1 1096*49ef7e06SGarrett D'Amore #define PCRF_CZ_VPD_ADDR_LBN 16 1097*49ef7e06SGarrett D'Amore #define PCRF_CZ_VPD_ADDR_WIDTH 15 1098*49ef7e06SGarrett D'Amore #define PCRF_CZ_VPD_NXT_PTR_LBN 8 1099*49ef7e06SGarrett D'Amore #define PCRF_CZ_VPD_NXT_PTR_WIDTH 8 1100*49ef7e06SGarrett D'Amore #define PCRF_CZ_VPD_CAP_ID_LBN 0 1101*49ef7e06SGarrett D'Amore #define PCRF_CZ_VPD_CAP_ID_WIDTH 8 1102*49ef7e06SGarrett D'Amore 1103*49ef7e06SGarrett D'Amore 1104*49ef7e06SGarrett D'Amore /* 1105*49ef7e06SGarrett D'Amore * PC_AER_CAP_HDR_REG(32bit): 1106*49ef7e06SGarrett D'Amore * AER capability header register 1107*49ef7e06SGarrett D'Amore */ 1108*49ef7e06SGarrett D'Amore 1109*49ef7e06SGarrett D'Amore #define PCR_AZ_AER_CAP_HDR_REG 0x00000100 1110*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1111*49ef7e06SGarrett D'Amore 1112*49ef7e06SGarrett D'Amore #define PCRF_AZ_AERCAPHDR_NXT_PTR_LBN 20 1113*49ef7e06SGarrett D'Amore #define PCRF_AZ_AERCAPHDR_NXT_PTR_WIDTH 12 1114*49ef7e06SGarrett D'Amore #define PCRF_AZ_AERCAPHDR_VER_LBN 16 1115*49ef7e06SGarrett D'Amore #define PCRF_AZ_AERCAPHDR_VER_WIDTH 4 1116*49ef7e06SGarrett D'Amore #define PCRF_AZ_AERCAPHDR_ID_LBN 0 1117*49ef7e06SGarrett D'Amore #define PCRF_AZ_AERCAPHDR_ID_WIDTH 16 1118*49ef7e06SGarrett D'Amore 1119*49ef7e06SGarrett D'Amore 1120*49ef7e06SGarrett D'Amore /* 1121*49ef7e06SGarrett D'Amore * PC_AER_UNCORR_ERR_STAT_REG(32bit): 1122*49ef7e06SGarrett D'Amore * AER Uncorrectable error status register 1123*49ef7e06SGarrett D'Amore */ 1124*49ef7e06SGarrett D'Amore 1125*49ef7e06SGarrett D'Amore #define PCR_AZ_AER_UNCORR_ERR_STAT_REG 0x00000104 1126*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1127*49ef7e06SGarrett D'Amore 1128*49ef7e06SGarrett D'Amore #define PCRF_AZ_UNSUPT_REQ_ERR_STAT_LBN 20 1129*49ef7e06SGarrett D'Amore #define PCRF_AZ_UNSUPT_REQ_ERR_STAT_WIDTH 1 1130*49ef7e06SGarrett D'Amore #define PCRF_AZ_ECRC_ERR_STAT_LBN 19 1131*49ef7e06SGarrett D'Amore #define PCRF_AZ_ECRC_ERR_STAT_WIDTH 1 1132*49ef7e06SGarrett D'Amore #define PCRF_AZ_MALF_TLP_STAT_LBN 18 1133*49ef7e06SGarrett D'Amore #define PCRF_AZ_MALF_TLP_STAT_WIDTH 1 1134*49ef7e06SGarrett D'Amore #define PCRF_AZ_RX_OVF_STAT_LBN 17 1135*49ef7e06SGarrett D'Amore #define PCRF_AZ_RX_OVF_STAT_WIDTH 1 1136*49ef7e06SGarrett D'Amore #define PCRF_AZ_UNEXP_COMP_STAT_LBN 16 1137*49ef7e06SGarrett D'Amore #define PCRF_AZ_UNEXP_COMP_STAT_WIDTH 1 1138*49ef7e06SGarrett D'Amore #define PCRF_AZ_COMP_ABRT_STAT_LBN 15 1139*49ef7e06SGarrett D'Amore #define PCRF_AZ_COMP_ABRT_STAT_WIDTH 1 1140*49ef7e06SGarrett D'Amore #define PCRF_AZ_COMP_TIMEOUT_STAT_LBN 14 1141*49ef7e06SGarrett D'Amore #define PCRF_AZ_COMP_TIMEOUT_STAT_WIDTH 1 1142*49ef7e06SGarrett D'Amore #define PCRF_AZ_FC_PROTO_ERR_STAT_LBN 13 1143*49ef7e06SGarrett D'Amore #define PCRF_AZ_FC_PROTO_ERR_STAT_WIDTH 1 1144*49ef7e06SGarrett D'Amore #define PCRF_AZ_PSON_TLP_STAT_LBN 12 1145*49ef7e06SGarrett D'Amore #define PCRF_AZ_PSON_TLP_STAT_WIDTH 1 1146*49ef7e06SGarrett D'Amore #define PCRF_AZ_DL_PROTO_ERR_STAT_LBN 4 1147*49ef7e06SGarrett D'Amore #define PCRF_AZ_DL_PROTO_ERR_STAT_WIDTH 1 1148*49ef7e06SGarrett D'Amore #define PCRF_AB_TRAIN_ERR_STAT_LBN 0 1149*49ef7e06SGarrett D'Amore #define PCRF_AB_TRAIN_ERR_STAT_WIDTH 1 1150*49ef7e06SGarrett D'Amore 1151*49ef7e06SGarrett D'Amore 1152*49ef7e06SGarrett D'Amore /* 1153*49ef7e06SGarrett D'Amore * PC_AER_UNCORR_ERR_MASK_REG(32bit): 1154*49ef7e06SGarrett D'Amore * AER Uncorrectable error mask register 1155*49ef7e06SGarrett D'Amore */ 1156*49ef7e06SGarrett D'Amore 1157*49ef7e06SGarrett D'Amore #define PCR_AZ_AER_UNCORR_ERR_MASK_REG 0x00000108 1158*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1159*49ef7e06SGarrett D'Amore 1160*49ef7e06SGarrett D'Amore #define PCRF_DZ_ATOMIC_OP_EGR_BLOCKED_MASK_LBN 24 1161*49ef7e06SGarrett D'Amore #define PCRF_DZ_ATOMIC_OP_EGR_BLOCKED_MASK_WIDTH 1 1162*49ef7e06SGarrett D'Amore #define PCRF_DZ_UNCORR_INT_ERR_MASK_LBN 22 1163*49ef7e06SGarrett D'Amore #define PCRF_DZ_UNCORR_INT_ERR_MASK_WIDTH 1 1164*49ef7e06SGarrett D'Amore #define PCRF_AZ_UNSUPT_REQ_ERR_MASK_LBN 20 1165*49ef7e06SGarrett D'Amore #define PCRF_AZ_UNSUPT_REQ_ERR_MASK_WIDTH 1 1166*49ef7e06SGarrett D'Amore #define PCRF_AZ_ECRC_ERR_MASK_LBN 19 1167*49ef7e06SGarrett D'Amore #define PCRF_AZ_ECRC_ERR_MASK_WIDTH 1 1168*49ef7e06SGarrett D'Amore #define PCRF_AZ_MALF_TLP_MASK_LBN 18 1169*49ef7e06SGarrett D'Amore #define PCRF_AZ_MALF_TLP_MASK_WIDTH 1 1170*49ef7e06SGarrett D'Amore #define PCRF_AZ_RX_OVF_MASK_LBN 17 1171*49ef7e06SGarrett D'Amore #define PCRF_AZ_RX_OVF_MASK_WIDTH 1 1172*49ef7e06SGarrett D'Amore #define PCRF_AZ_UNEXP_COMP_MASK_LBN 16 1173*49ef7e06SGarrett D'Amore #define PCRF_AZ_UNEXP_COMP_MASK_WIDTH 1 1174*49ef7e06SGarrett D'Amore #define PCRF_AZ_COMP_ABRT_MASK_LBN 15 1175*49ef7e06SGarrett D'Amore #define PCRF_AZ_COMP_ABRT_MASK_WIDTH 1 1176*49ef7e06SGarrett D'Amore #define PCRF_AZ_COMP_TIMEOUT_MASK_LBN 14 1177*49ef7e06SGarrett D'Amore #define PCRF_AZ_COMP_TIMEOUT_MASK_WIDTH 1 1178*49ef7e06SGarrett D'Amore #define PCRF_AZ_FC_PROTO_ERR_MASK_LBN 13 1179*49ef7e06SGarrett D'Amore #define PCRF_AZ_FC_PROTO_ERR_MASK_WIDTH 1 1180*49ef7e06SGarrett D'Amore #define PCRF_AZ_PSON_TLP_MASK_LBN 12 1181*49ef7e06SGarrett D'Amore #define PCRF_AZ_PSON_TLP_MASK_WIDTH 1 1182*49ef7e06SGarrett D'Amore #define PCRF_AZ_DL_PROTO_ERR_MASK_LBN 4 1183*49ef7e06SGarrett D'Amore #define PCRF_AZ_DL_PROTO_ERR_MASK_WIDTH 1 1184*49ef7e06SGarrett D'Amore #define PCRF_AB_TRAIN_ERR_MASK_LBN 0 1185*49ef7e06SGarrett D'Amore #define PCRF_AB_TRAIN_ERR_MASK_WIDTH 1 1186*49ef7e06SGarrett D'Amore 1187*49ef7e06SGarrett D'Amore 1188*49ef7e06SGarrett D'Amore /* 1189*49ef7e06SGarrett D'Amore * PC_AER_UNCORR_ERR_SEV_REG(32bit): 1190*49ef7e06SGarrett D'Amore * AER Uncorrectable error severity register 1191*49ef7e06SGarrett D'Amore */ 1192*49ef7e06SGarrett D'Amore 1193*49ef7e06SGarrett D'Amore #define PCR_AZ_AER_UNCORR_ERR_SEV_REG 0x0000010c 1194*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1195*49ef7e06SGarrett D'Amore 1196*49ef7e06SGarrett D'Amore #define PCRF_AZ_UNSUPT_REQ_ERR_SEV_LBN 20 1197*49ef7e06SGarrett D'Amore #define PCRF_AZ_UNSUPT_REQ_ERR_SEV_WIDTH 1 1198*49ef7e06SGarrett D'Amore #define PCRF_AZ_ECRC_ERR_SEV_LBN 19 1199*49ef7e06SGarrett D'Amore #define PCRF_AZ_ECRC_ERR_SEV_WIDTH 1 1200*49ef7e06SGarrett D'Amore #define PCRF_AZ_MALF_TLP_SEV_LBN 18 1201*49ef7e06SGarrett D'Amore #define PCRF_AZ_MALF_TLP_SEV_WIDTH 1 1202*49ef7e06SGarrett D'Amore #define PCRF_AZ_RX_OVF_SEV_LBN 17 1203*49ef7e06SGarrett D'Amore #define PCRF_AZ_RX_OVF_SEV_WIDTH 1 1204*49ef7e06SGarrett D'Amore #define PCRF_AZ_UNEXP_COMP_SEV_LBN 16 1205*49ef7e06SGarrett D'Amore #define PCRF_AZ_UNEXP_COMP_SEV_WIDTH 1 1206*49ef7e06SGarrett D'Amore #define PCRF_AZ_COMP_ABRT_SEV_LBN 15 1207*49ef7e06SGarrett D'Amore #define PCRF_AZ_COMP_ABRT_SEV_WIDTH 1 1208*49ef7e06SGarrett D'Amore #define PCRF_AZ_COMP_TIMEOUT_SEV_LBN 14 1209*49ef7e06SGarrett D'Amore #define PCRF_AZ_COMP_TIMEOUT_SEV_WIDTH 1 1210*49ef7e06SGarrett D'Amore #define PCRF_AZ_FC_PROTO_ERR_SEV_LBN 13 1211*49ef7e06SGarrett D'Amore #define PCRF_AZ_FC_PROTO_ERR_SEV_WIDTH 1 1212*49ef7e06SGarrett D'Amore #define PCRF_AZ_PSON_TLP_SEV_LBN 12 1213*49ef7e06SGarrett D'Amore #define PCRF_AZ_PSON_TLP_SEV_WIDTH 1 1214*49ef7e06SGarrett D'Amore #define PCRF_AZ_DL_PROTO_ERR_SEV_LBN 4 1215*49ef7e06SGarrett D'Amore #define PCRF_AZ_DL_PROTO_ERR_SEV_WIDTH 1 1216*49ef7e06SGarrett D'Amore #define PCRF_AB_TRAIN_ERR_SEV_LBN 0 1217*49ef7e06SGarrett D'Amore #define PCRF_AB_TRAIN_ERR_SEV_WIDTH 1 1218*49ef7e06SGarrett D'Amore 1219*49ef7e06SGarrett D'Amore 1220*49ef7e06SGarrett D'Amore /* 1221*49ef7e06SGarrett D'Amore * PC_AER_CORR_ERR_STAT_REG(32bit): 1222*49ef7e06SGarrett D'Amore * AER Correctable error status register 1223*49ef7e06SGarrett D'Amore */ 1224*49ef7e06SGarrett D'Amore 1225*49ef7e06SGarrett D'Amore #define PCR_AZ_AER_CORR_ERR_STAT_REG 0x00000110 1226*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1227*49ef7e06SGarrett D'Amore 1228*49ef7e06SGarrett D'Amore #define PCRF_CZ_ADVSY_NON_FATAL_STAT_LBN 13 1229*49ef7e06SGarrett D'Amore #define PCRF_CZ_ADVSY_NON_FATAL_STAT_WIDTH 1 1230*49ef7e06SGarrett D'Amore #define PCRF_AZ_RPLY_TMR_TOUT_STAT_LBN 12 1231*49ef7e06SGarrett D'Amore #define PCRF_AZ_RPLY_TMR_TOUT_STAT_WIDTH 1 1232*49ef7e06SGarrett D'Amore #define PCRF_AZ_RPLAY_NUM_RO_STAT_LBN 8 1233*49ef7e06SGarrett D'Amore #define PCRF_AZ_RPLAY_NUM_RO_STAT_WIDTH 1 1234*49ef7e06SGarrett D'Amore #define PCRF_AZ_BAD_DLLP_STAT_LBN 7 1235*49ef7e06SGarrett D'Amore #define PCRF_AZ_BAD_DLLP_STAT_WIDTH 1 1236*49ef7e06SGarrett D'Amore #define PCRF_AZ_BAD_TLP_STAT_LBN 6 1237*49ef7e06SGarrett D'Amore #define PCRF_AZ_BAD_TLP_STAT_WIDTH 1 1238*49ef7e06SGarrett D'Amore #define PCRF_AZ_RX_ERR_STAT_LBN 0 1239*49ef7e06SGarrett D'Amore #define PCRF_AZ_RX_ERR_STAT_WIDTH 1 1240*49ef7e06SGarrett D'Amore 1241*49ef7e06SGarrett D'Amore 1242*49ef7e06SGarrett D'Amore /* 1243*49ef7e06SGarrett D'Amore * PC_AER_CORR_ERR_MASK_REG(32bit): 1244*49ef7e06SGarrett D'Amore * AER Correctable error status register 1245*49ef7e06SGarrett D'Amore */ 1246*49ef7e06SGarrett D'Amore 1247*49ef7e06SGarrett D'Amore #define PCR_AZ_AER_CORR_ERR_MASK_REG 0x00000114 1248*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1249*49ef7e06SGarrett D'Amore 1250*49ef7e06SGarrett D'Amore #define PCRF_CZ_ADVSY_NON_FATAL_MASK_LBN 13 1251*49ef7e06SGarrett D'Amore #define PCRF_CZ_ADVSY_NON_FATAL_MASK_WIDTH 1 1252*49ef7e06SGarrett D'Amore #define PCRF_AZ_RPLY_TMR_TOUT_MASK_LBN 12 1253*49ef7e06SGarrett D'Amore #define PCRF_AZ_RPLY_TMR_TOUT_MASK_WIDTH 1 1254*49ef7e06SGarrett D'Amore #define PCRF_AZ_RPLAY_NUM_RO_MASK_LBN 8 1255*49ef7e06SGarrett D'Amore #define PCRF_AZ_RPLAY_NUM_RO_MASK_WIDTH 1 1256*49ef7e06SGarrett D'Amore #define PCRF_AZ_BAD_DLLP_MASK_LBN 7 1257*49ef7e06SGarrett D'Amore #define PCRF_AZ_BAD_DLLP_MASK_WIDTH 1 1258*49ef7e06SGarrett D'Amore #define PCRF_AZ_BAD_TLP_MASK_LBN 6 1259*49ef7e06SGarrett D'Amore #define PCRF_AZ_BAD_TLP_MASK_WIDTH 1 1260*49ef7e06SGarrett D'Amore #define PCRF_AZ_RX_ERR_MASK_LBN 0 1261*49ef7e06SGarrett D'Amore #define PCRF_AZ_RX_ERR_MASK_WIDTH 1 1262*49ef7e06SGarrett D'Amore 1263*49ef7e06SGarrett D'Amore 1264*49ef7e06SGarrett D'Amore /* 1265*49ef7e06SGarrett D'Amore * PC_AER_CAP_CTL_REG(32bit): 1266*49ef7e06SGarrett D'Amore * AER capability and control register 1267*49ef7e06SGarrett D'Amore */ 1268*49ef7e06SGarrett D'Amore 1269*49ef7e06SGarrett D'Amore #define PCR_AZ_AER_CAP_CTL_REG 0x00000118 1270*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1271*49ef7e06SGarrett D'Amore 1272*49ef7e06SGarrett D'Amore #define PCRF_AZ_ECRC_CHK_EN_LBN 8 1273*49ef7e06SGarrett D'Amore #define PCRF_AZ_ECRC_CHK_EN_WIDTH 1 1274*49ef7e06SGarrett D'Amore #define PCRF_AZ_ECRC_CHK_CAP_LBN 7 1275*49ef7e06SGarrett D'Amore #define PCRF_AZ_ECRC_CHK_CAP_WIDTH 1 1276*49ef7e06SGarrett D'Amore #define PCRF_AZ_ECRC_GEN_EN_LBN 6 1277*49ef7e06SGarrett D'Amore #define PCRF_AZ_ECRC_GEN_EN_WIDTH 1 1278*49ef7e06SGarrett D'Amore #define PCRF_AZ_ECRC_GEN_CAP_LBN 5 1279*49ef7e06SGarrett D'Amore #define PCRF_AZ_ECRC_GEN_CAP_WIDTH 1 1280*49ef7e06SGarrett D'Amore #define PCRF_AZ_1ST_ERR_PTR_LBN 0 1281*49ef7e06SGarrett D'Amore #define PCRF_AZ_1ST_ERR_PTR_WIDTH 5 1282*49ef7e06SGarrett D'Amore 1283*49ef7e06SGarrett D'Amore 1284*49ef7e06SGarrett D'Amore /* 1285*49ef7e06SGarrett D'Amore * PC_AER_HDR_LOG_REG(128bit): 1286*49ef7e06SGarrett D'Amore * AER Header log register 1287*49ef7e06SGarrett D'Amore */ 1288*49ef7e06SGarrett D'Amore 1289*49ef7e06SGarrett D'Amore #define PCR_AZ_AER_HDR_LOG_REG 0x0000011c 1290*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0,hunta0=pci_f0_config */ 1291*49ef7e06SGarrett D'Amore 1292*49ef7e06SGarrett D'Amore #define PCRF_AZ_HDR_LOG_LBN 0 1293*49ef7e06SGarrett D'Amore #define PCRF_AZ_HDR_LOG_WIDTH 128 1294*49ef7e06SGarrett D'Amore 1295*49ef7e06SGarrett D'Amore 1296*49ef7e06SGarrett D'Amore /* 1297*49ef7e06SGarrett D'Amore * PC_DEVSN_CAP_HDR_REG(32bit): 1298*49ef7e06SGarrett D'Amore * Device serial number capability header register 1299*49ef7e06SGarrett D'Amore */ 1300*49ef7e06SGarrett D'Amore 1301*49ef7e06SGarrett D'Amore #define PCR_CZ_DEVSN_CAP_HDR_REG 0x00000140 1302*49ef7e06SGarrett D'Amore /* sienaa0,hunta0=pci_f0_config */ 1303*49ef7e06SGarrett D'Amore 1304*49ef7e06SGarrett D'Amore #define PCRF_CZ_DEVSNCAPHDR_NXT_PTR_LBN 20 1305*49ef7e06SGarrett D'Amore #define PCRF_CZ_DEVSNCAPHDR_NXT_PTR_WIDTH 12 1306*49ef7e06SGarrett D'Amore #define PCRF_CZ_DEVSNCAPHDR_VER_LBN 16 1307*49ef7e06SGarrett D'Amore #define PCRF_CZ_DEVSNCAPHDR_VER_WIDTH 4 1308*49ef7e06SGarrett D'Amore #define PCRF_CZ_DEVSNCAPHDR_ID_LBN 0 1309*49ef7e06SGarrett D'Amore #define PCRF_CZ_DEVSNCAPHDR_ID_WIDTH 16 1310*49ef7e06SGarrett D'Amore 1311*49ef7e06SGarrett D'Amore 1312*49ef7e06SGarrett D'Amore /* 1313*49ef7e06SGarrett D'Amore * PC_DEVSN_DWORD0_REG(32bit): 1314*49ef7e06SGarrett D'Amore * Device serial number DWORD0 1315*49ef7e06SGarrett D'Amore */ 1316*49ef7e06SGarrett D'Amore 1317*49ef7e06SGarrett D'Amore #define PCR_CZ_DEVSN_DWORD0_REG 0x00000144 1318*49ef7e06SGarrett D'Amore /* sienaa0,hunta0=pci_f0_config */ 1319*49ef7e06SGarrett D'Amore 1320*49ef7e06SGarrett D'Amore #define PCRF_CZ_DEVSN_DWORD0_LBN 0 1321*49ef7e06SGarrett D'Amore #define PCRF_CZ_DEVSN_DWORD0_WIDTH 32 1322*49ef7e06SGarrett D'Amore 1323*49ef7e06SGarrett D'Amore 1324*49ef7e06SGarrett D'Amore /* 1325*49ef7e06SGarrett D'Amore * PC_DEVSN_DWORD1_REG(32bit): 1326*49ef7e06SGarrett D'Amore * Device serial number DWORD0 1327*49ef7e06SGarrett D'Amore */ 1328*49ef7e06SGarrett D'Amore 1329*49ef7e06SGarrett D'Amore #define PCR_CZ_DEVSN_DWORD1_REG 0x00000148 1330*49ef7e06SGarrett D'Amore /* sienaa0,hunta0=pci_f0_config */ 1331*49ef7e06SGarrett D'Amore 1332*49ef7e06SGarrett D'Amore #define PCRF_CZ_DEVSN_DWORD1_LBN 0 1333*49ef7e06SGarrett D'Amore #define PCRF_CZ_DEVSN_DWORD1_WIDTH 32 1334*49ef7e06SGarrett D'Amore 1335*49ef7e06SGarrett D'Amore 1336*49ef7e06SGarrett D'Amore /* 1337*49ef7e06SGarrett D'Amore * PC_ARI_CAP_HDR_REG(32bit): 1338*49ef7e06SGarrett D'Amore * ARI capability header register 1339*49ef7e06SGarrett D'Amore */ 1340*49ef7e06SGarrett D'Amore 1341*49ef7e06SGarrett D'Amore #define PCR_CZ_ARI_CAP_HDR_REG 0x00000150 1342*49ef7e06SGarrett D'Amore /* sienaa0,hunta0=pci_f0_config */ 1343*49ef7e06SGarrett D'Amore 1344*49ef7e06SGarrett D'Amore #define PCRF_CZ_ARICAPHDR_NXT_PTR_LBN 20 1345*49ef7e06SGarrett D'Amore #define PCRF_CZ_ARICAPHDR_NXT_PTR_WIDTH 12 1346*49ef7e06SGarrett D'Amore #define PCRF_CZ_ARICAPHDR_VER_LBN 16 1347*49ef7e06SGarrett D'Amore #define PCRF_CZ_ARICAPHDR_VER_WIDTH 4 1348*49ef7e06SGarrett D'Amore #define PCRF_CZ_ARICAPHDR_ID_LBN 0 1349*49ef7e06SGarrett D'Amore #define PCRF_CZ_ARICAPHDR_ID_WIDTH 16 1350*49ef7e06SGarrett D'Amore 1351*49ef7e06SGarrett D'Amore 1352*49ef7e06SGarrett D'Amore /* 1353*49ef7e06SGarrett D'Amore * PC_ARI_CAP_REG(16bit): 1354*49ef7e06SGarrett D'Amore * ARI Capabilities 1355*49ef7e06SGarrett D'Amore */ 1356*49ef7e06SGarrett D'Amore 1357*49ef7e06SGarrett D'Amore #define PCR_CZ_ARI_CAP_REG 0x00000154 1358*49ef7e06SGarrett D'Amore /* sienaa0,hunta0=pci_f0_config */ 1359*49ef7e06SGarrett D'Amore 1360*49ef7e06SGarrett D'Amore #define PCRF_CZ_ARI_NXT_FN_NUM_LBN 8 1361*49ef7e06SGarrett D'Amore #define PCRF_CZ_ARI_NXT_FN_NUM_WIDTH 8 1362*49ef7e06SGarrett D'Amore #define PCRF_CZ_ARI_ACS_FNGRP_CAP_LBN 1 1363*49ef7e06SGarrett D'Amore #define PCRF_CZ_ARI_ACS_FNGRP_CAP_WIDTH 1 1364*49ef7e06SGarrett D'Amore #define PCRF_CZ_ARI_MFVC_FNGRP_CAP_LBN 0 1365*49ef7e06SGarrett D'Amore #define PCRF_CZ_ARI_MFVC_FNGRP_CAP_WIDTH 1 1366*49ef7e06SGarrett D'Amore 1367*49ef7e06SGarrett D'Amore 1368*49ef7e06SGarrett D'Amore /* 1369*49ef7e06SGarrett D'Amore * PC_ARI_CTL_REG(16bit): 1370*49ef7e06SGarrett D'Amore * ARI Control 1371*49ef7e06SGarrett D'Amore */ 1372*49ef7e06SGarrett D'Amore 1373*49ef7e06SGarrett D'Amore #define PCR_CZ_ARI_CTL_REG 0x00000156 1374*49ef7e06SGarrett D'Amore /* sienaa0,hunta0=pci_f0_config */ 1375*49ef7e06SGarrett D'Amore 1376*49ef7e06SGarrett D'Amore #define PCRF_CZ_ARI_FN_GRP_LBN 4 1377*49ef7e06SGarrett D'Amore #define PCRF_CZ_ARI_FN_GRP_WIDTH 3 1378*49ef7e06SGarrett D'Amore #define PCRF_CZ_ARI_ACS_FNGRP_EN_LBN 1 1379*49ef7e06SGarrett D'Amore #define PCRF_CZ_ARI_ACS_FNGRP_EN_WIDTH 1 1380*49ef7e06SGarrett D'Amore #define PCRF_CZ_ARI_MFVC_FNGRP_EN_LBN 0 1381*49ef7e06SGarrett D'Amore #define PCRF_CZ_ARI_MFVC_FNGRP_EN_WIDTH 1 1382*49ef7e06SGarrett D'Amore 1383*49ef7e06SGarrett D'Amore 1384*49ef7e06SGarrett D'Amore /* 1385*49ef7e06SGarrett D'Amore * PC_SEC_PCIE_CAP_REG(32bit): 1386*49ef7e06SGarrett D'Amore * Secondary PCIE Capability Register 1387*49ef7e06SGarrett D'Amore */ 1388*49ef7e06SGarrett D'Amore 1389*49ef7e06SGarrett D'Amore #define PCR_DZ_SEC_PCIE_CAP_REG 0x00000160 1390*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 1391*49ef7e06SGarrett D'Amore 1392*49ef7e06SGarrett D'Amore #define PCRF_DZ_SEC_NXT_PTR_LBN 20 1393*49ef7e06SGarrett D'Amore #define PCRF_DZ_SEC_NXT_PTR_WIDTH 12 1394*49ef7e06SGarrett D'Amore #define PCRF_DZ_SEC_VERSION_LBN 16 1395*49ef7e06SGarrett D'Amore #define PCRF_DZ_SEC_VERSION_WIDTH 4 1396*49ef7e06SGarrett D'Amore #define PCRF_DZ_SEC_EXT_CAP_ID_LBN 0 1397*49ef7e06SGarrett D'Amore #define PCRF_DZ_SEC_EXT_CAP_ID_WIDTH 16 1398*49ef7e06SGarrett D'Amore 1399*49ef7e06SGarrett D'Amore 1400*49ef7e06SGarrett D'Amore /* 1401*49ef7e06SGarrett D'Amore * PC_SRIOV_CAP_HDR_REG(32bit): 1402*49ef7e06SGarrett D'Amore * SRIOV capability header register 1403*49ef7e06SGarrett D'Amore */ 1404*49ef7e06SGarrett D'Amore 1405*49ef7e06SGarrett D'Amore #define PCR_CC_SRIOV_CAP_HDR_REG 0x00000160 1406*49ef7e06SGarrett D'Amore /* sienaa0=pci_f0_config */ 1407*49ef7e06SGarrett D'Amore 1408*49ef7e06SGarrett D'Amore #define PCR_DZ_SRIOV_CAP_HDR_REG 0x00000180 1409*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 1410*49ef7e06SGarrett D'Amore 1411*49ef7e06SGarrett D'Amore #define PCRF_CZ_SRIOVCAPHDR_NXT_PTR_LBN 20 1412*49ef7e06SGarrett D'Amore #define PCRF_CZ_SRIOVCAPHDR_NXT_PTR_WIDTH 12 1413*49ef7e06SGarrett D'Amore #define PCRF_CZ_SRIOVCAPHDR_VER_LBN 16 1414*49ef7e06SGarrett D'Amore #define PCRF_CZ_SRIOVCAPHDR_VER_WIDTH 4 1415*49ef7e06SGarrett D'Amore #define PCRF_CZ_SRIOVCAPHDR_ID_LBN 0 1416*49ef7e06SGarrett D'Amore #define PCRF_CZ_SRIOVCAPHDR_ID_WIDTH 16 1417*49ef7e06SGarrett D'Amore 1418*49ef7e06SGarrett D'Amore 1419*49ef7e06SGarrett D'Amore /* 1420*49ef7e06SGarrett D'Amore * PC_SRIOV_CAP_REG(32bit): 1421*49ef7e06SGarrett D'Amore * SRIOV Capabilities 1422*49ef7e06SGarrett D'Amore */ 1423*49ef7e06SGarrett D'Amore 1424*49ef7e06SGarrett D'Amore #define PCR_CC_SRIOV_CAP_REG 0x00000164 1425*49ef7e06SGarrett D'Amore /* sienaa0=pci_f0_config */ 1426*49ef7e06SGarrett D'Amore 1427*49ef7e06SGarrett D'Amore #define PCR_DZ_SRIOV_CAP_REG 0x00000184 1428*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 1429*49ef7e06SGarrett D'Amore 1430*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_MIGR_INT_MSG_NUM_LBN 21 1431*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_MIGR_INT_MSG_NUM_WIDTH 11 1432*49ef7e06SGarrett D'Amore #define PCRF_DZ_VF_ARI_CAP_PRESV_LBN 1 1433*49ef7e06SGarrett D'Amore #define PCRF_DZ_VF_ARI_CAP_PRESV_WIDTH 1 1434*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_MIGR_CAP_LBN 0 1435*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_MIGR_CAP_WIDTH 1 1436*49ef7e06SGarrett D'Amore 1437*49ef7e06SGarrett D'Amore 1438*49ef7e06SGarrett D'Amore /* 1439*49ef7e06SGarrett D'Amore * PC_LINK_CONTROL3_REG(32bit): 1440*49ef7e06SGarrett D'Amore * Link Control 3. 1441*49ef7e06SGarrett D'Amore */ 1442*49ef7e06SGarrett D'Amore 1443*49ef7e06SGarrett D'Amore #define PCR_DZ_LINK_CONTROL3_REG 0x00000164 1444*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 1445*49ef7e06SGarrett D'Amore 1446*49ef7e06SGarrett D'Amore #define PCRF_DZ_LINK_EQ_INT_EN_LBN 1 1447*49ef7e06SGarrett D'Amore #define PCRF_DZ_LINK_EQ_INT_EN_WIDTH 1 1448*49ef7e06SGarrett D'Amore #define PCRF_DZ_PERFORM_EQL_LBN 0 1449*49ef7e06SGarrett D'Amore #define PCRF_DZ_PERFORM_EQL_WIDTH 1 1450*49ef7e06SGarrett D'Amore 1451*49ef7e06SGarrett D'Amore 1452*49ef7e06SGarrett D'Amore /* 1453*49ef7e06SGarrett D'Amore * PC_LANE_ERROR_STAT_REG(32bit): 1454*49ef7e06SGarrett D'Amore * Lane Error Status Register. 1455*49ef7e06SGarrett D'Amore */ 1456*49ef7e06SGarrett D'Amore 1457*49ef7e06SGarrett D'Amore #define PCR_DZ_LANE_ERROR_STAT_REG 0x00000168 1458*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 1459*49ef7e06SGarrett D'Amore 1460*49ef7e06SGarrett D'Amore #define PCRF_DZ_LANE_STATUS_LBN 0 1461*49ef7e06SGarrett D'Amore #define PCRF_DZ_LANE_STATUS_WIDTH 8 1462*49ef7e06SGarrett D'Amore 1463*49ef7e06SGarrett D'Amore 1464*49ef7e06SGarrett D'Amore /* 1465*49ef7e06SGarrett D'Amore * PC_SRIOV_CTL_REG(16bit): 1466*49ef7e06SGarrett D'Amore * SRIOV Control 1467*49ef7e06SGarrett D'Amore */ 1468*49ef7e06SGarrett D'Amore 1469*49ef7e06SGarrett D'Amore #define PCR_CC_SRIOV_CTL_REG 0x00000168 1470*49ef7e06SGarrett D'Amore /* sienaa0=pci_f0_config */ 1471*49ef7e06SGarrett D'Amore 1472*49ef7e06SGarrett D'Amore #define PCR_DZ_SRIOV_CTL_REG 0x00000188 1473*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 1474*49ef7e06SGarrett D'Amore 1475*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_ARI_CAP_HRCHY_LBN 4 1476*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_ARI_CAP_HRCHY_WIDTH 1 1477*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_MSE_LBN 3 1478*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_MSE_WIDTH 1 1479*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_MIGR_INT_EN_LBN 2 1480*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_MIGR_INT_EN_WIDTH 1 1481*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_MIGR_EN_LBN 1 1482*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_MIGR_EN_WIDTH 1 1483*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_EN_LBN 0 1484*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_EN_WIDTH 1 1485*49ef7e06SGarrett D'Amore 1486*49ef7e06SGarrett D'Amore 1487*49ef7e06SGarrett D'Amore /* 1488*49ef7e06SGarrett D'Amore * PC_SRIOV_STAT_REG(16bit): 1489*49ef7e06SGarrett D'Amore * SRIOV Status 1490*49ef7e06SGarrett D'Amore */ 1491*49ef7e06SGarrett D'Amore 1492*49ef7e06SGarrett D'Amore #define PCR_CC_SRIOV_STAT_REG 0x0000016a 1493*49ef7e06SGarrett D'Amore /* sienaa0=pci_f0_config */ 1494*49ef7e06SGarrett D'Amore 1495*49ef7e06SGarrett D'Amore #define PCR_DZ_SRIOV_STAT_REG 0x0000018a 1496*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 1497*49ef7e06SGarrett D'Amore 1498*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_MIGR_STAT_LBN 0 1499*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_MIGR_STAT_WIDTH 1 1500*49ef7e06SGarrett D'Amore 1501*49ef7e06SGarrett D'Amore 1502*49ef7e06SGarrett D'Amore /* 1503*49ef7e06SGarrett D'Amore * PC_LANE01_EQU_CONTROL_REG(32bit): 1504*49ef7e06SGarrett D'Amore * Lanes 0,1 Equalization Control Register. 1505*49ef7e06SGarrett D'Amore */ 1506*49ef7e06SGarrett D'Amore 1507*49ef7e06SGarrett D'Amore #define PCR_DZ_LANE01_EQU_CONTROL_REG 0x0000016c 1508*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 1509*49ef7e06SGarrett D'Amore 1510*49ef7e06SGarrett D'Amore #define PCRF_DZ_LANE1_EQ_CTRL_LBN 16 1511*49ef7e06SGarrett D'Amore #define PCRF_DZ_LANE1_EQ_CTRL_WIDTH 16 1512*49ef7e06SGarrett D'Amore #define PCRF_DZ_LANE0_EQ_CTRL_LBN 0 1513*49ef7e06SGarrett D'Amore #define PCRF_DZ_LANE0_EQ_CTRL_WIDTH 16 1514*49ef7e06SGarrett D'Amore 1515*49ef7e06SGarrett D'Amore 1516*49ef7e06SGarrett D'Amore /* 1517*49ef7e06SGarrett D'Amore * PC_SRIOV_INITIALVFS_REG(16bit): 1518*49ef7e06SGarrett D'Amore * SRIOV Initial VFs 1519*49ef7e06SGarrett D'Amore */ 1520*49ef7e06SGarrett D'Amore 1521*49ef7e06SGarrett D'Amore #define PCR_CC_SRIOV_INITIALVFS_REG 0x0000016c 1522*49ef7e06SGarrett D'Amore /* sienaa0=pci_f0_config */ 1523*49ef7e06SGarrett D'Amore 1524*49ef7e06SGarrett D'Amore #define PCR_DZ_SRIOV_INITIALVFS_REG 0x0000018c 1525*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 1526*49ef7e06SGarrett D'Amore 1527*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_INITIALVFS_LBN 0 1528*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_INITIALVFS_WIDTH 16 1529*49ef7e06SGarrett D'Amore 1530*49ef7e06SGarrett D'Amore 1531*49ef7e06SGarrett D'Amore /* 1532*49ef7e06SGarrett D'Amore * PC_SRIOV_TOTALVFS_REG(10bit): 1533*49ef7e06SGarrett D'Amore * SRIOV Total VFs 1534*49ef7e06SGarrett D'Amore */ 1535*49ef7e06SGarrett D'Amore 1536*49ef7e06SGarrett D'Amore #define PCR_CC_SRIOV_TOTALVFS_REG 0x0000016e 1537*49ef7e06SGarrett D'Amore /* sienaa0=pci_f0_config */ 1538*49ef7e06SGarrett D'Amore 1539*49ef7e06SGarrett D'Amore #define PCR_DZ_SRIOV_TOTALVFS_REG 0x0000018e 1540*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 1541*49ef7e06SGarrett D'Amore 1542*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_TOTALVFS_LBN 0 1543*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_TOTALVFS_WIDTH 16 1544*49ef7e06SGarrett D'Amore 1545*49ef7e06SGarrett D'Amore 1546*49ef7e06SGarrett D'Amore /* 1547*49ef7e06SGarrett D'Amore * PC_SRIOV_NUMVFS_REG(16bit): 1548*49ef7e06SGarrett D'Amore * SRIOV Number of VFs 1549*49ef7e06SGarrett D'Amore */ 1550*49ef7e06SGarrett D'Amore 1551*49ef7e06SGarrett D'Amore #define PCR_CC_SRIOV_NUMVFS_REG 0x00000170 1552*49ef7e06SGarrett D'Amore /* sienaa0=pci_f0_config */ 1553*49ef7e06SGarrett D'Amore 1554*49ef7e06SGarrett D'Amore #define PCR_DZ_SRIOV_NUMVFS_REG 0x00000190 1555*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 1556*49ef7e06SGarrett D'Amore 1557*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_NUMVFS_LBN 0 1558*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_NUMVFS_WIDTH 16 1559*49ef7e06SGarrett D'Amore 1560*49ef7e06SGarrett D'Amore 1561*49ef7e06SGarrett D'Amore /* 1562*49ef7e06SGarrett D'Amore * PC_LANE23_EQU_CONTROL_REG(32bit): 1563*49ef7e06SGarrett D'Amore * Lanes 2,3 Equalization Control Register. 1564*49ef7e06SGarrett D'Amore */ 1565*49ef7e06SGarrett D'Amore 1566*49ef7e06SGarrett D'Amore #define PCR_DZ_LANE23_EQU_CONTROL_REG 0x00000170 1567*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 1568*49ef7e06SGarrett D'Amore 1569*49ef7e06SGarrett D'Amore #define PCRF_DZ_LANE3_EQ_CTRL_LBN 16 1570*49ef7e06SGarrett D'Amore #define PCRF_DZ_LANE3_EQ_CTRL_WIDTH 16 1571*49ef7e06SGarrett D'Amore #define PCRF_DZ_LANE2_EQ_CTRL_LBN 0 1572*49ef7e06SGarrett D'Amore #define PCRF_DZ_LANE2_EQ_CTRL_WIDTH 16 1573*49ef7e06SGarrett D'Amore 1574*49ef7e06SGarrett D'Amore 1575*49ef7e06SGarrett D'Amore /* 1576*49ef7e06SGarrett D'Amore * PC_SRIOV_FN_DPND_LNK_REG(16bit): 1577*49ef7e06SGarrett D'Amore * SRIOV Function dependency link 1578*49ef7e06SGarrett D'Amore */ 1579*49ef7e06SGarrett D'Amore 1580*49ef7e06SGarrett D'Amore #define PCR_CC_SRIOV_FN_DPND_LNK_REG 0x00000172 1581*49ef7e06SGarrett D'Amore /* sienaa0=pci_f0_config */ 1582*49ef7e06SGarrett D'Amore 1583*49ef7e06SGarrett D'Amore #define PCR_DZ_SRIOV_FN_DPND_LNK_REG 0x00000192 1584*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 1585*49ef7e06SGarrett D'Amore 1586*49ef7e06SGarrett D'Amore #define PCRF_CZ_SRIOV_FN_DPND_LNK_LBN 0 1587*49ef7e06SGarrett D'Amore #define PCRF_CZ_SRIOV_FN_DPND_LNK_WIDTH 8 1588*49ef7e06SGarrett D'Amore 1589*49ef7e06SGarrett D'Amore 1590*49ef7e06SGarrett D'Amore /* 1591*49ef7e06SGarrett D'Amore * PC_SRIOV_1STVF_OFFSET_REG(16bit): 1592*49ef7e06SGarrett D'Amore * SRIOV First VF Offset 1593*49ef7e06SGarrett D'Amore */ 1594*49ef7e06SGarrett D'Amore 1595*49ef7e06SGarrett D'Amore #define PCR_CC_SRIOV_1STVF_OFFSET_REG 0x00000174 1596*49ef7e06SGarrett D'Amore /* sienaa0=pci_f0_config */ 1597*49ef7e06SGarrett D'Amore 1598*49ef7e06SGarrett D'Amore #define PCR_DZ_SRIOV_1STVF_OFFSET_REG 0x00000194 1599*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 1600*49ef7e06SGarrett D'Amore 1601*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_1STVF_OFFSET_LBN 0 1602*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_1STVF_OFFSET_WIDTH 16 1603*49ef7e06SGarrett D'Amore 1604*49ef7e06SGarrett D'Amore 1605*49ef7e06SGarrett D'Amore /* 1606*49ef7e06SGarrett D'Amore * PC_LANE45_EQU_CONTROL_REG(32bit): 1607*49ef7e06SGarrett D'Amore * Lanes 4,5 Equalization Control Register. 1608*49ef7e06SGarrett D'Amore */ 1609*49ef7e06SGarrett D'Amore 1610*49ef7e06SGarrett D'Amore #define PCR_DZ_LANE45_EQU_CONTROL_REG 0x00000174 1611*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 1612*49ef7e06SGarrett D'Amore 1613*49ef7e06SGarrett D'Amore #define PCRF_DZ_LANE5_EQ_CTRL_LBN 16 1614*49ef7e06SGarrett D'Amore #define PCRF_DZ_LANE5_EQ_CTRL_WIDTH 16 1615*49ef7e06SGarrett D'Amore #define PCRF_DZ_LANE4_EQ_CTRL_LBN 0 1616*49ef7e06SGarrett D'Amore #define PCRF_DZ_LANE4_EQ_CTRL_WIDTH 16 1617*49ef7e06SGarrett D'Amore 1618*49ef7e06SGarrett D'Amore 1619*49ef7e06SGarrett D'Amore /* 1620*49ef7e06SGarrett D'Amore * PC_SRIOV_VFSTRIDE_REG(16bit): 1621*49ef7e06SGarrett D'Amore * SRIOV VF Stride 1622*49ef7e06SGarrett D'Amore */ 1623*49ef7e06SGarrett D'Amore 1624*49ef7e06SGarrett D'Amore #define PCR_CC_SRIOV_VFSTRIDE_REG 0x00000176 1625*49ef7e06SGarrett D'Amore /* sienaa0=pci_f0_config */ 1626*49ef7e06SGarrett D'Amore 1627*49ef7e06SGarrett D'Amore #define PCR_DZ_SRIOV_VFSTRIDE_REG 0x00000196 1628*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 1629*49ef7e06SGarrett D'Amore 1630*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_VFSTRIDE_LBN 0 1631*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_VFSTRIDE_WIDTH 16 1632*49ef7e06SGarrett D'Amore 1633*49ef7e06SGarrett D'Amore 1634*49ef7e06SGarrett D'Amore /* 1635*49ef7e06SGarrett D'Amore * PC_LANE67_EQU_CONTROL_REG(32bit): 1636*49ef7e06SGarrett D'Amore * Lanes 6,7 Equalization Control Register. 1637*49ef7e06SGarrett D'Amore */ 1638*49ef7e06SGarrett D'Amore 1639*49ef7e06SGarrett D'Amore #define PCR_DZ_LANE67_EQU_CONTROL_REG 0x00000178 1640*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 1641*49ef7e06SGarrett D'Amore 1642*49ef7e06SGarrett D'Amore #define PCRF_DZ_LANE7_EQ_CTRL_LBN 16 1643*49ef7e06SGarrett D'Amore #define PCRF_DZ_LANE7_EQ_CTRL_WIDTH 16 1644*49ef7e06SGarrett D'Amore #define PCRF_DZ_LANE6_EQ_CTRL_LBN 0 1645*49ef7e06SGarrett D'Amore #define PCRF_DZ_LANE6_EQ_CTRL_WIDTH 16 1646*49ef7e06SGarrett D'Amore 1647*49ef7e06SGarrett D'Amore 1648*49ef7e06SGarrett D'Amore /* 1649*49ef7e06SGarrett D'Amore * PC_SRIOV_DEVID_REG(16bit): 1650*49ef7e06SGarrett D'Amore * SRIOV VF Device ID 1651*49ef7e06SGarrett D'Amore */ 1652*49ef7e06SGarrett D'Amore 1653*49ef7e06SGarrett D'Amore #define PCR_CC_SRIOV_DEVID_REG 0x0000017a 1654*49ef7e06SGarrett D'Amore /* sienaa0=pci_f0_config */ 1655*49ef7e06SGarrett D'Amore 1656*49ef7e06SGarrett D'Amore #define PCR_DZ_SRIOV_DEVID_REG 0x0000019a 1657*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 1658*49ef7e06SGarrett D'Amore 1659*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_DEVID_LBN 0 1660*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_DEVID_WIDTH 16 1661*49ef7e06SGarrett D'Amore 1662*49ef7e06SGarrett D'Amore 1663*49ef7e06SGarrett D'Amore /* 1664*49ef7e06SGarrett D'Amore * PC_SRIOV_SUP_PAGESZ_REG(16bit): 1665*49ef7e06SGarrett D'Amore * SRIOV Supported Page Sizes 1666*49ef7e06SGarrett D'Amore */ 1667*49ef7e06SGarrett D'Amore 1668*49ef7e06SGarrett D'Amore #define PCR_CC_SRIOV_SUP_PAGESZ_REG 0x0000017c 1669*49ef7e06SGarrett D'Amore /* sienaa0=pci_f0_config */ 1670*49ef7e06SGarrett D'Amore 1671*49ef7e06SGarrett D'Amore #define PCR_DZ_SRIOV_SUP_PAGESZ_REG 0x0000019c 1672*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 1673*49ef7e06SGarrett D'Amore 1674*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_SUP_PAGESZ_LBN 0 1675*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_SUP_PAGESZ_WIDTH 16 1676*49ef7e06SGarrett D'Amore 1677*49ef7e06SGarrett D'Amore 1678*49ef7e06SGarrett D'Amore /* 1679*49ef7e06SGarrett D'Amore * PC_SRIOV_SYS_PAGESZ_REG(32bit): 1680*49ef7e06SGarrett D'Amore * SRIOV System Page Size 1681*49ef7e06SGarrett D'Amore */ 1682*49ef7e06SGarrett D'Amore 1683*49ef7e06SGarrett D'Amore #define PCR_CC_SRIOV_SYS_PAGESZ_REG 0x00000180 1684*49ef7e06SGarrett D'Amore /* sienaa0=pci_f0_config */ 1685*49ef7e06SGarrett D'Amore 1686*49ef7e06SGarrett D'Amore #define PCR_DZ_SRIOV_SYS_PAGESZ_REG 0x000001a0 1687*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 1688*49ef7e06SGarrett D'Amore 1689*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_SYS_PAGESZ_LBN 0 1690*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_SYS_PAGESZ_WIDTH 16 1691*49ef7e06SGarrett D'Amore 1692*49ef7e06SGarrett D'Amore 1693*49ef7e06SGarrett D'Amore /* 1694*49ef7e06SGarrett D'Amore * PC_SRIOV_BAR0_REG(32bit): 1695*49ef7e06SGarrett D'Amore * SRIOV VF Bar0 1696*49ef7e06SGarrett D'Amore */ 1697*49ef7e06SGarrett D'Amore 1698*49ef7e06SGarrett D'Amore #define PCR_CC_SRIOV_BAR0_REG 0x00000184 1699*49ef7e06SGarrett D'Amore /* sienaa0=pci_f0_config */ 1700*49ef7e06SGarrett D'Amore 1701*49ef7e06SGarrett D'Amore #define PCR_DZ_SRIOV_BAR0_REG 0x000001a4 1702*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 1703*49ef7e06SGarrett D'Amore 1704*49ef7e06SGarrett D'Amore #define PCRF_CC_VF_BAR_ADDRESS_LBN 0 1705*49ef7e06SGarrett D'Amore #define PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 1706*49ef7e06SGarrett D'Amore #define PCRF_DZ_VF_BAR0_ADDRESS_LBN 4 1707*49ef7e06SGarrett D'Amore #define PCRF_DZ_VF_BAR0_ADDRESS_WIDTH 28 1708*49ef7e06SGarrett D'Amore #define PCRF_DZ_VF_BAR0_PREF_LBN 3 1709*49ef7e06SGarrett D'Amore #define PCRF_DZ_VF_BAR0_PREF_WIDTH 1 1710*49ef7e06SGarrett D'Amore #define PCRF_DZ_VF_BAR0_TYPE_LBN 1 1711*49ef7e06SGarrett D'Amore #define PCRF_DZ_VF_BAR0_TYPE_WIDTH 2 1712*49ef7e06SGarrett D'Amore #define PCRF_DZ_VF_BAR0_IOM_LBN 0 1713*49ef7e06SGarrett D'Amore #define PCRF_DZ_VF_BAR0_IOM_WIDTH 1 1714*49ef7e06SGarrett D'Amore 1715*49ef7e06SGarrett D'Amore 1716*49ef7e06SGarrett D'Amore /* 1717*49ef7e06SGarrett D'Amore * PC_SRIOV_BAR1_REG(32bit): 1718*49ef7e06SGarrett D'Amore * SRIOV Bar1 1719*49ef7e06SGarrett D'Amore */ 1720*49ef7e06SGarrett D'Amore 1721*49ef7e06SGarrett D'Amore #define PCR_CC_SRIOV_BAR1_REG 0x00000188 1722*49ef7e06SGarrett D'Amore /* sienaa0=pci_f0_config */ 1723*49ef7e06SGarrett D'Amore 1724*49ef7e06SGarrett D'Amore #define PCR_DZ_SRIOV_BAR1_REG 0x000001a8 1725*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 1726*49ef7e06SGarrett D'Amore 1727*49ef7e06SGarrett D'Amore /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1728*49ef7e06SGarrett D'Amore /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1729*49ef7e06SGarrett D'Amore #define PCRF_DZ_VF_BAR1_ADDRESS_LBN 0 1730*49ef7e06SGarrett D'Amore #define PCRF_DZ_VF_BAR1_ADDRESS_WIDTH 32 1731*49ef7e06SGarrett D'Amore 1732*49ef7e06SGarrett D'Amore 1733*49ef7e06SGarrett D'Amore /* 1734*49ef7e06SGarrett D'Amore * PC_SRIOV_BAR2_REG(32bit): 1735*49ef7e06SGarrett D'Amore * SRIOV Bar2 1736*49ef7e06SGarrett D'Amore */ 1737*49ef7e06SGarrett D'Amore 1738*49ef7e06SGarrett D'Amore #define PCR_CC_SRIOV_BAR2_REG 0x0000018c 1739*49ef7e06SGarrett D'Amore /* sienaa0=pci_f0_config */ 1740*49ef7e06SGarrett D'Amore 1741*49ef7e06SGarrett D'Amore #define PCR_DZ_SRIOV_BAR2_REG 0x000001ac 1742*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 1743*49ef7e06SGarrett D'Amore 1744*49ef7e06SGarrett D'Amore /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1745*49ef7e06SGarrett D'Amore /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1746*49ef7e06SGarrett D'Amore #define PCRF_DZ_VF_BAR2_ADDRESS_LBN 4 1747*49ef7e06SGarrett D'Amore #define PCRF_DZ_VF_BAR2_ADDRESS_WIDTH 28 1748*49ef7e06SGarrett D'Amore #define PCRF_DZ_VF_BAR2_PREF_LBN 3 1749*49ef7e06SGarrett D'Amore #define PCRF_DZ_VF_BAR2_PREF_WIDTH 1 1750*49ef7e06SGarrett D'Amore #define PCRF_DZ_VF_BAR2_TYPE_LBN 1 1751*49ef7e06SGarrett D'Amore #define PCRF_DZ_VF_BAR2_TYPE_WIDTH 2 1752*49ef7e06SGarrett D'Amore #define PCRF_DZ_VF_BAR2_IOM_LBN 0 1753*49ef7e06SGarrett D'Amore #define PCRF_DZ_VF_BAR2_IOM_WIDTH 1 1754*49ef7e06SGarrett D'Amore 1755*49ef7e06SGarrett D'Amore 1756*49ef7e06SGarrett D'Amore /* 1757*49ef7e06SGarrett D'Amore * PC_SRIOV_BAR3_REG(32bit): 1758*49ef7e06SGarrett D'Amore * SRIOV Bar3 1759*49ef7e06SGarrett D'Amore */ 1760*49ef7e06SGarrett D'Amore 1761*49ef7e06SGarrett D'Amore #define PCR_CC_SRIOV_BAR3_REG 0x00000190 1762*49ef7e06SGarrett D'Amore /* sienaa0=pci_f0_config */ 1763*49ef7e06SGarrett D'Amore 1764*49ef7e06SGarrett D'Amore #define PCR_DZ_SRIOV_BAR3_REG 0x000001b0 1765*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 1766*49ef7e06SGarrett D'Amore 1767*49ef7e06SGarrett D'Amore /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1768*49ef7e06SGarrett D'Amore /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1769*49ef7e06SGarrett D'Amore #define PCRF_DZ_VF_BAR3_ADDRESS_LBN 0 1770*49ef7e06SGarrett D'Amore #define PCRF_DZ_VF_BAR3_ADDRESS_WIDTH 32 1771*49ef7e06SGarrett D'Amore 1772*49ef7e06SGarrett D'Amore 1773*49ef7e06SGarrett D'Amore /* 1774*49ef7e06SGarrett D'Amore * PC_SRIOV_BAR4_REG(32bit): 1775*49ef7e06SGarrett D'Amore * SRIOV Bar4 1776*49ef7e06SGarrett D'Amore */ 1777*49ef7e06SGarrett D'Amore 1778*49ef7e06SGarrett D'Amore #define PCR_CC_SRIOV_BAR4_REG 0x00000194 1779*49ef7e06SGarrett D'Amore /* sienaa0=pci_f0_config */ 1780*49ef7e06SGarrett D'Amore 1781*49ef7e06SGarrett D'Amore #define PCR_DZ_SRIOV_BAR4_REG 0x000001b4 1782*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 1783*49ef7e06SGarrett D'Amore 1784*49ef7e06SGarrett D'Amore /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1785*49ef7e06SGarrett D'Amore /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1786*49ef7e06SGarrett D'Amore #define PCRF_DZ_VF_BAR4_ADDRESS_LBN 0 1787*49ef7e06SGarrett D'Amore #define PCRF_DZ_VF_BAR4_ADDRESS_WIDTH 32 1788*49ef7e06SGarrett D'Amore 1789*49ef7e06SGarrett D'Amore 1790*49ef7e06SGarrett D'Amore /* 1791*49ef7e06SGarrett D'Amore * PC_SRIOV_BAR5_REG(32bit): 1792*49ef7e06SGarrett D'Amore * SRIOV Bar5 1793*49ef7e06SGarrett D'Amore */ 1794*49ef7e06SGarrett D'Amore 1795*49ef7e06SGarrett D'Amore #define PCR_CC_SRIOV_BAR5_REG 0x00000198 1796*49ef7e06SGarrett D'Amore /* sienaa0=pci_f0_config */ 1797*49ef7e06SGarrett D'Amore 1798*49ef7e06SGarrett D'Amore #define PCR_DZ_SRIOV_BAR5_REG 0x000001b8 1799*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 1800*49ef7e06SGarrett D'Amore 1801*49ef7e06SGarrett D'Amore /* defined as PCRF_CC_VF_BAR_ADDRESS_LBN 0; */ 1802*49ef7e06SGarrett D'Amore /* defined as PCRF_CC_VF_BAR_ADDRESS_WIDTH 32 */ 1803*49ef7e06SGarrett D'Amore #define PCRF_DZ_VF_BAR5_ADDRESS_LBN 0 1804*49ef7e06SGarrett D'Amore #define PCRF_DZ_VF_BAR5_ADDRESS_WIDTH 32 1805*49ef7e06SGarrett D'Amore 1806*49ef7e06SGarrett D'Amore 1807*49ef7e06SGarrett D'Amore /* 1808*49ef7e06SGarrett D'Amore * PC_SRIOV_RSVD_REG(16bit): 1809*49ef7e06SGarrett D'Amore * Reserved register 1810*49ef7e06SGarrett D'Amore */ 1811*49ef7e06SGarrett D'Amore 1812*49ef7e06SGarrett D'Amore #define PCR_DZ_SRIOV_RSVD_REG 0x00000198 1813*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 1814*49ef7e06SGarrett D'Amore 1815*49ef7e06SGarrett D'Amore #define PCRF_DZ_VF_RSVD_LBN 0 1816*49ef7e06SGarrett D'Amore #define PCRF_DZ_VF_RSVD_WIDTH 16 1817*49ef7e06SGarrett D'Amore 1818*49ef7e06SGarrett D'Amore 1819*49ef7e06SGarrett D'Amore /* 1820*49ef7e06SGarrett D'Amore * PC_SRIOV_MIBR_SARRAY_OFFSET_REG(32bit): 1821*49ef7e06SGarrett D'Amore * SRIOV VF Migration State Array Offset 1822*49ef7e06SGarrett D'Amore */ 1823*49ef7e06SGarrett D'Amore 1824*49ef7e06SGarrett D'Amore #define PCR_CC_SRIOV_MIBR_SARRAY_OFFSET_REG 0x0000019c 1825*49ef7e06SGarrett D'Amore /* sienaa0=pci_f0_config */ 1826*49ef7e06SGarrett D'Amore 1827*49ef7e06SGarrett D'Amore #define PCR_DZ_SRIOV_MIBR_SARRAY_OFFSET_REG 0x000001bc 1828*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 1829*49ef7e06SGarrett D'Amore 1830*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_MIGR_OFFSET_LBN 3 1831*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_MIGR_OFFSET_WIDTH 29 1832*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_MIGR_BIR_LBN 0 1833*49ef7e06SGarrett D'Amore #define PCRF_CZ_VF_MIGR_BIR_WIDTH 3 1834*49ef7e06SGarrett D'Amore 1835*49ef7e06SGarrett D'Amore 1836*49ef7e06SGarrett D'Amore /* 1837*49ef7e06SGarrett D'Amore * PC_TPH_CAP_HDR_REG(32bit): 1838*49ef7e06SGarrett D'Amore * TPH Capability Header Register 1839*49ef7e06SGarrett D'Amore */ 1840*49ef7e06SGarrett D'Amore 1841*49ef7e06SGarrett D'Amore #define PCR_DZ_TPH_CAP_HDR_REG 0x000001c0 1842*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 1843*49ef7e06SGarrett D'Amore 1844*49ef7e06SGarrett D'Amore #define PCRF_DZ_TPH_NXT_PTR_LBN 20 1845*49ef7e06SGarrett D'Amore #define PCRF_DZ_TPH_NXT_PTR_WIDTH 12 1846*49ef7e06SGarrett D'Amore #define PCRF_DZ_TPH_VERSION_LBN 16 1847*49ef7e06SGarrett D'Amore #define PCRF_DZ_TPH_VERSION_WIDTH 4 1848*49ef7e06SGarrett D'Amore #define PCRF_DZ_TPH_EXT_CAP_ID_LBN 0 1849*49ef7e06SGarrett D'Amore #define PCRF_DZ_TPH_EXT_CAP_ID_WIDTH 16 1850*49ef7e06SGarrett D'Amore 1851*49ef7e06SGarrett D'Amore 1852*49ef7e06SGarrett D'Amore /* 1853*49ef7e06SGarrett D'Amore * PC_TPH_REQ_CAP_REG(32bit): 1854*49ef7e06SGarrett D'Amore * TPH Requester Capability Register 1855*49ef7e06SGarrett D'Amore */ 1856*49ef7e06SGarrett D'Amore 1857*49ef7e06SGarrett D'Amore #define PCR_DZ_TPH_REQ_CAP_REG 0x000001c4 1858*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 1859*49ef7e06SGarrett D'Amore 1860*49ef7e06SGarrett D'Amore #define PCRF_DZ_ST_TBLE_SIZE_LBN 16 1861*49ef7e06SGarrett D'Amore #define PCRF_DZ_ST_TBLE_SIZE_WIDTH 11 1862*49ef7e06SGarrett D'Amore #define PCRF_DZ_ST_TBLE_LOC_LBN 9 1863*49ef7e06SGarrett D'Amore #define PCRF_DZ_ST_TBLE_LOC_WIDTH 2 1864*49ef7e06SGarrett D'Amore #define PCRF_DZ_EXT_TPH_MODE_SUP_LBN 8 1865*49ef7e06SGarrett D'Amore #define PCRF_DZ_EXT_TPH_MODE_SUP_WIDTH 1 1866*49ef7e06SGarrett D'Amore #define PCRF_DZ_TPH_DEV_MODE_SUP_LBN 2 1867*49ef7e06SGarrett D'Amore #define PCRF_DZ_TPH_DEV_MODE_SUP_WIDTH 1 1868*49ef7e06SGarrett D'Amore #define PCRF_DZ_TPH_INT_MODE_SUP_LBN 1 1869*49ef7e06SGarrett D'Amore #define PCRF_DZ_TPH_INT_MODE_SUP_WIDTH 1 1870*49ef7e06SGarrett D'Amore #define PCRF_DZ_TPH_NOST_MODE_SUP_LBN 0 1871*49ef7e06SGarrett D'Amore #define PCRF_DZ_TPH_NOST_MODE_SUP_WIDTH 1 1872*49ef7e06SGarrett D'Amore 1873*49ef7e06SGarrett D'Amore 1874*49ef7e06SGarrett D'Amore /* 1875*49ef7e06SGarrett D'Amore * PC_TPH_REQ_CTL_REG(32bit): 1876*49ef7e06SGarrett D'Amore * TPH Requester Control Register 1877*49ef7e06SGarrett D'Amore */ 1878*49ef7e06SGarrett D'Amore 1879*49ef7e06SGarrett D'Amore #define PCR_DZ_TPH_REQ_CTL_REG 0x000001c8 1880*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 1881*49ef7e06SGarrett D'Amore 1882*49ef7e06SGarrett D'Amore #define PCRF_DZ_TPH_REQ_ENABLE_LBN 8 1883*49ef7e06SGarrett D'Amore #define PCRF_DZ_TPH_REQ_ENABLE_WIDTH 2 1884*49ef7e06SGarrett D'Amore #define PCRF_DZ_TPH_ST_MODE_LBN 0 1885*49ef7e06SGarrett D'Amore #define PCRF_DZ_TPH_ST_MODE_WIDTH 3 1886*49ef7e06SGarrett D'Amore 1887*49ef7e06SGarrett D'Amore 1888*49ef7e06SGarrett D'Amore /* 1889*49ef7e06SGarrett D'Amore * PC_LTR_CAP_HDR_REG(32bit): 1890*49ef7e06SGarrett D'Amore * Latency Tolerance Reporting Cap Header Reg 1891*49ef7e06SGarrett D'Amore */ 1892*49ef7e06SGarrett D'Amore 1893*49ef7e06SGarrett D'Amore #define PCR_DZ_LTR_CAP_HDR_REG 0x00000290 1894*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 1895*49ef7e06SGarrett D'Amore 1896*49ef7e06SGarrett D'Amore #define PCRF_DZ_LTR_NXT_PTR_LBN 20 1897*49ef7e06SGarrett D'Amore #define PCRF_DZ_LTR_NXT_PTR_WIDTH 12 1898*49ef7e06SGarrett D'Amore #define PCRF_DZ_LTR_VERSION_LBN 16 1899*49ef7e06SGarrett D'Amore #define PCRF_DZ_LTR_VERSION_WIDTH 4 1900*49ef7e06SGarrett D'Amore #define PCRF_DZ_LTR_EXT_CAP_ID_LBN 0 1901*49ef7e06SGarrett D'Amore #define PCRF_DZ_LTR_EXT_CAP_ID_WIDTH 16 1902*49ef7e06SGarrett D'Amore 1903*49ef7e06SGarrett D'Amore 1904*49ef7e06SGarrett D'Amore /* 1905*49ef7e06SGarrett D'Amore * PC_LTR_MAX_SNOOP_REG(32bit): 1906*49ef7e06SGarrett D'Amore * LTR Maximum Snoop/No Snoop Register 1907*49ef7e06SGarrett D'Amore */ 1908*49ef7e06SGarrett D'Amore 1909*49ef7e06SGarrett D'Amore #define PCR_DZ_LTR_MAX_SNOOP_REG 0x00000294 1910*49ef7e06SGarrett D'Amore /* hunta0=pci_f0_config */ 1911*49ef7e06SGarrett D'Amore 1912*49ef7e06SGarrett D'Amore #define PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_LBN 26 1913*49ef7e06SGarrett D'Amore #define PCRF_DZ_LTR_MAX_NOSNOOP_SCALE_WIDTH 3 1914*49ef7e06SGarrett D'Amore #define PCRF_DZ_LTR_MAX_NOSNOOP_LAT_LBN 16 1915*49ef7e06SGarrett D'Amore #define PCRF_DZ_LTR_MAX_NOSNOOP_LAT_WIDTH 10 1916*49ef7e06SGarrett D'Amore #define PCRF_DZ_LTR_MAX_SNOOP_SCALE_LBN 10 1917*49ef7e06SGarrett D'Amore #define PCRF_DZ_LTR_MAX_SNOOP_SCALE_WIDTH 3 1918*49ef7e06SGarrett D'Amore #define PCRF_DZ_LTR_MAX_SNOOP_LAT_LBN 0 1919*49ef7e06SGarrett D'Amore #define PCRF_DZ_LTR_MAX_SNOOP_LAT_WIDTH 10 1920*49ef7e06SGarrett D'Amore 1921*49ef7e06SGarrett D'Amore 1922*49ef7e06SGarrett D'Amore /* 1923*49ef7e06SGarrett D'Amore * PC_ACK_LAT_TMR_REG(32bit): 1924*49ef7e06SGarrett D'Amore * ACK latency timer & replay timer register 1925*49ef7e06SGarrett D'Amore */ 1926*49ef7e06SGarrett D'Amore 1927*49ef7e06SGarrett D'Amore #define PCR_AC_ACK_LAT_TMR_REG 0x00000700 1928*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0=pci_f0_config */ 1929*49ef7e06SGarrett D'Amore 1930*49ef7e06SGarrett D'Amore #define PCRF_AC_RT_LBN 16 1931*49ef7e06SGarrett D'Amore #define PCRF_AC_RT_WIDTH 16 1932*49ef7e06SGarrett D'Amore #define PCRF_AC_ALT_LBN 0 1933*49ef7e06SGarrett D'Amore #define PCRF_AC_ALT_WIDTH 16 1934*49ef7e06SGarrett D'Amore 1935*49ef7e06SGarrett D'Amore 1936*49ef7e06SGarrett D'Amore /* 1937*49ef7e06SGarrett D'Amore * PC_OTHER_MSG_REG(32bit): 1938*49ef7e06SGarrett D'Amore * Other message register 1939*49ef7e06SGarrett D'Amore */ 1940*49ef7e06SGarrett D'Amore 1941*49ef7e06SGarrett D'Amore #define PCR_AC_OTHER_MSG_REG 0x00000704 1942*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0=pci_f0_config */ 1943*49ef7e06SGarrett D'Amore 1944*49ef7e06SGarrett D'Amore #define PCRF_AC_OM_CRPT3_LBN 24 1945*49ef7e06SGarrett D'Amore #define PCRF_AC_OM_CRPT3_WIDTH 8 1946*49ef7e06SGarrett D'Amore #define PCRF_AC_OM_CRPT2_LBN 16 1947*49ef7e06SGarrett D'Amore #define PCRF_AC_OM_CRPT2_WIDTH 8 1948*49ef7e06SGarrett D'Amore #define PCRF_AC_OM_CRPT1_LBN 8 1949*49ef7e06SGarrett D'Amore #define PCRF_AC_OM_CRPT1_WIDTH 8 1950*49ef7e06SGarrett D'Amore #define PCRF_AC_OM_CRPT0_LBN 0 1951*49ef7e06SGarrett D'Amore #define PCRF_AC_OM_CRPT0_WIDTH 8 1952*49ef7e06SGarrett D'Amore 1953*49ef7e06SGarrett D'Amore 1954*49ef7e06SGarrett D'Amore /* 1955*49ef7e06SGarrett D'Amore * PC_FORCE_LNK_REG(24bit): 1956*49ef7e06SGarrett D'Amore * Port force link register 1957*49ef7e06SGarrett D'Amore */ 1958*49ef7e06SGarrett D'Amore 1959*49ef7e06SGarrett D'Amore #define PCR_AC_FORCE_LNK_REG 0x00000708 1960*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0=pci_f0_config */ 1961*49ef7e06SGarrett D'Amore 1962*49ef7e06SGarrett D'Amore #define PCRF_AC_LFS_LBN 16 1963*49ef7e06SGarrett D'Amore #define PCRF_AC_LFS_WIDTH 6 1964*49ef7e06SGarrett D'Amore #define PCRF_AC_FL_LBN 15 1965*49ef7e06SGarrett D'Amore #define PCRF_AC_FL_WIDTH 1 1966*49ef7e06SGarrett D'Amore #define PCRF_AC_LN_LBN 0 1967*49ef7e06SGarrett D'Amore #define PCRF_AC_LN_WIDTH 8 1968*49ef7e06SGarrett D'Amore 1969*49ef7e06SGarrett D'Amore 1970*49ef7e06SGarrett D'Amore /* 1971*49ef7e06SGarrett D'Amore * PC_ACK_FREQ_REG(32bit): 1972*49ef7e06SGarrett D'Amore * ACK frequency register 1973*49ef7e06SGarrett D'Amore */ 1974*49ef7e06SGarrett D'Amore 1975*49ef7e06SGarrett D'Amore #define PCR_AC_ACK_FREQ_REG 0x0000070c 1976*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0=pci_f0_config */ 1977*49ef7e06SGarrett D'Amore 1978*49ef7e06SGarrett D'Amore #define PCRF_CC_ALLOW_L1_WITHOUT_L0S_LBN 30 1979*49ef7e06SGarrett D'Amore #define PCRF_CC_ALLOW_L1_WITHOUT_L0S_WIDTH 1 1980*49ef7e06SGarrett D'Amore #define PCRF_AC_L1_ENTR_LAT_LBN 27 1981*49ef7e06SGarrett D'Amore #define PCRF_AC_L1_ENTR_LAT_WIDTH 3 1982*49ef7e06SGarrett D'Amore #define PCRF_AC_L0_ENTR_LAT_LBN 24 1983*49ef7e06SGarrett D'Amore #define PCRF_AC_L0_ENTR_LAT_WIDTH 3 1984*49ef7e06SGarrett D'Amore #define PCRF_CC_COMM_NFTS_LBN 16 1985*49ef7e06SGarrett D'Amore #define PCRF_CC_COMM_NFTS_WIDTH 8 1986*49ef7e06SGarrett D'Amore #define PCRF_AB_ACK_FREQ_REG_RSVD0_LBN 16 1987*49ef7e06SGarrett D'Amore #define PCRF_AB_ACK_FREQ_REG_RSVD0_WIDTH 3 1988*49ef7e06SGarrett D'Amore #define PCRF_AC_MAX_FTS_LBN 8 1989*49ef7e06SGarrett D'Amore #define PCRF_AC_MAX_FTS_WIDTH 8 1990*49ef7e06SGarrett D'Amore #define PCRF_AC_ACK_FREQ_LBN 0 1991*49ef7e06SGarrett D'Amore #define PCRF_AC_ACK_FREQ_WIDTH 8 1992*49ef7e06SGarrett D'Amore 1993*49ef7e06SGarrett D'Amore 1994*49ef7e06SGarrett D'Amore /* 1995*49ef7e06SGarrett D'Amore * PC_PORT_LNK_CTL_REG(32bit): 1996*49ef7e06SGarrett D'Amore * Port link control register 1997*49ef7e06SGarrett D'Amore */ 1998*49ef7e06SGarrett D'Amore 1999*49ef7e06SGarrett D'Amore #define PCR_AC_PORT_LNK_CTL_REG 0x00000710 2000*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0=pci_f0_config */ 2001*49ef7e06SGarrett D'Amore 2002*49ef7e06SGarrett D'Amore #define PCRF_AB_LRE_LBN 27 2003*49ef7e06SGarrett D'Amore #define PCRF_AB_LRE_WIDTH 1 2004*49ef7e06SGarrett D'Amore #define PCRF_AB_ESYNC_LBN 26 2005*49ef7e06SGarrett D'Amore #define PCRF_AB_ESYNC_WIDTH 1 2006*49ef7e06SGarrett D'Amore #define PCRF_AB_CRPT_LBN 25 2007*49ef7e06SGarrett D'Amore #define PCRF_AB_CRPT_WIDTH 1 2008*49ef7e06SGarrett D'Amore #define PCRF_AB_XB_LBN 24 2009*49ef7e06SGarrett D'Amore #define PCRF_AB_XB_WIDTH 1 2010*49ef7e06SGarrett D'Amore #define PCRF_AC_LC_LBN 16 2011*49ef7e06SGarrett D'Amore #define PCRF_AC_LC_WIDTH 6 2012*49ef7e06SGarrett D'Amore #define PCRF_AC_LDR_LBN 8 2013*49ef7e06SGarrett D'Amore #define PCRF_AC_LDR_WIDTH 4 2014*49ef7e06SGarrett D'Amore #define PCRF_AC_FLM_LBN 7 2015*49ef7e06SGarrett D'Amore #define PCRF_AC_FLM_WIDTH 1 2016*49ef7e06SGarrett D'Amore #define PCRF_AC_LKD_LBN 6 2017*49ef7e06SGarrett D'Amore #define PCRF_AC_LKD_WIDTH 1 2018*49ef7e06SGarrett D'Amore #define PCRF_AC_DLE_LBN 5 2019*49ef7e06SGarrett D'Amore #define PCRF_AC_DLE_WIDTH 1 2020*49ef7e06SGarrett D'Amore #define PCRF_AB_PORT_LNK_CTL_REG_RSVD0_LBN 4 2021*49ef7e06SGarrett D'Amore #define PCRF_AB_PORT_LNK_CTL_REG_RSVD0_WIDTH 1 2022*49ef7e06SGarrett D'Amore #define PCRF_AC_RA_LBN 3 2023*49ef7e06SGarrett D'Amore #define PCRF_AC_RA_WIDTH 1 2024*49ef7e06SGarrett D'Amore #define PCRF_AC_LE_LBN 2 2025*49ef7e06SGarrett D'Amore #define PCRF_AC_LE_WIDTH 1 2026*49ef7e06SGarrett D'Amore #define PCRF_AC_SD_LBN 1 2027*49ef7e06SGarrett D'Amore #define PCRF_AC_SD_WIDTH 1 2028*49ef7e06SGarrett D'Amore #define PCRF_AC_OMR_LBN 0 2029*49ef7e06SGarrett D'Amore #define PCRF_AC_OMR_WIDTH 1 2030*49ef7e06SGarrett D'Amore 2031*49ef7e06SGarrett D'Amore 2032*49ef7e06SGarrett D'Amore /* 2033*49ef7e06SGarrett D'Amore * PC_LN_SKEW_REG(32bit): 2034*49ef7e06SGarrett D'Amore * Lane skew register 2035*49ef7e06SGarrett D'Amore */ 2036*49ef7e06SGarrett D'Amore 2037*49ef7e06SGarrett D'Amore #define PCR_AC_LN_SKEW_REG 0x00000714 2038*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0=pci_f0_config */ 2039*49ef7e06SGarrett D'Amore 2040*49ef7e06SGarrett D'Amore #define PCRF_AC_DIS_LBN 31 2041*49ef7e06SGarrett D'Amore #define PCRF_AC_DIS_WIDTH 1 2042*49ef7e06SGarrett D'Amore #define PCRF_AB_RST_LBN 30 2043*49ef7e06SGarrett D'Amore #define PCRF_AB_RST_WIDTH 1 2044*49ef7e06SGarrett D'Amore #define PCRF_AC_AD_LBN 25 2045*49ef7e06SGarrett D'Amore #define PCRF_AC_AD_WIDTH 1 2046*49ef7e06SGarrett D'Amore #define PCRF_AC_FCD_LBN 24 2047*49ef7e06SGarrett D'Amore #define PCRF_AC_FCD_WIDTH 1 2048*49ef7e06SGarrett D'Amore #define PCRF_AC_LS2_LBN 16 2049*49ef7e06SGarrett D'Amore #define PCRF_AC_LS2_WIDTH 8 2050*49ef7e06SGarrett D'Amore #define PCRF_AC_LS1_LBN 8 2051*49ef7e06SGarrett D'Amore #define PCRF_AC_LS1_WIDTH 8 2052*49ef7e06SGarrett D'Amore #define PCRF_AC_LS0_LBN 0 2053*49ef7e06SGarrett D'Amore #define PCRF_AC_LS0_WIDTH 8 2054*49ef7e06SGarrett D'Amore 2055*49ef7e06SGarrett D'Amore 2056*49ef7e06SGarrett D'Amore /* 2057*49ef7e06SGarrett D'Amore * PC_SYM_NUM_REG(16bit): 2058*49ef7e06SGarrett D'Amore * Symbol number register 2059*49ef7e06SGarrett D'Amore */ 2060*49ef7e06SGarrett D'Amore 2061*49ef7e06SGarrett D'Amore #define PCR_AC_SYM_NUM_REG 0x00000718 2062*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0=pci_f0_config */ 2063*49ef7e06SGarrett D'Amore 2064*49ef7e06SGarrett D'Amore #define PCRF_CC_MAX_FUNCTIONS_LBN 29 2065*49ef7e06SGarrett D'Amore #define PCRF_CC_MAX_FUNCTIONS_WIDTH 3 2066*49ef7e06SGarrett D'Amore #define PCRF_CC_FC_WATCHDOG_TMR_LBN 24 2067*49ef7e06SGarrett D'Amore #define PCRF_CC_FC_WATCHDOG_TMR_WIDTH 5 2068*49ef7e06SGarrett D'Amore #define PCRF_CC_ACK_NAK_TMR_MOD_LBN 19 2069*49ef7e06SGarrett D'Amore #define PCRF_CC_ACK_NAK_TMR_MOD_WIDTH 5 2070*49ef7e06SGarrett D'Amore #define PCRF_CC_REPLAY_TMR_MOD_LBN 14 2071*49ef7e06SGarrett D'Amore #define PCRF_CC_REPLAY_TMR_MOD_WIDTH 5 2072*49ef7e06SGarrett D'Amore #define PCRF_AB_ES_LBN 12 2073*49ef7e06SGarrett D'Amore #define PCRF_AB_ES_WIDTH 3 2074*49ef7e06SGarrett D'Amore #define PCRF_AB_SYM_NUM_REG_RSVD0_LBN 11 2075*49ef7e06SGarrett D'Amore #define PCRF_AB_SYM_NUM_REG_RSVD0_WIDTH 1 2076*49ef7e06SGarrett D'Amore #define PCRF_CC_NUM_SKP_SYMS_LBN 8 2077*49ef7e06SGarrett D'Amore #define PCRF_CC_NUM_SKP_SYMS_WIDTH 3 2078*49ef7e06SGarrett D'Amore #define PCRF_AB_TS2_LBN 4 2079*49ef7e06SGarrett D'Amore #define PCRF_AB_TS2_WIDTH 4 2080*49ef7e06SGarrett D'Amore #define PCRF_AC_TS1_LBN 0 2081*49ef7e06SGarrett D'Amore #define PCRF_AC_TS1_WIDTH 4 2082*49ef7e06SGarrett D'Amore 2083*49ef7e06SGarrett D'Amore 2084*49ef7e06SGarrett D'Amore /* 2085*49ef7e06SGarrett D'Amore * PC_SYM_TMR_FLT_MSK_REG(16bit): 2086*49ef7e06SGarrett D'Amore * Symbol timer and Filter Mask Register 2087*49ef7e06SGarrett D'Amore */ 2088*49ef7e06SGarrett D'Amore 2089*49ef7e06SGarrett D'Amore #define PCR_CC_SYM_TMR_FLT_MSK_REG 0x0000071c 2090*49ef7e06SGarrett D'Amore /* sienaa0=pci_f0_config */ 2091*49ef7e06SGarrett D'Amore 2092*49ef7e06SGarrett D'Amore #define PCRF_CC_DEFAULT_FLT_MSK1_LBN 16 2093*49ef7e06SGarrett D'Amore #define PCRF_CC_DEFAULT_FLT_MSK1_WIDTH 16 2094*49ef7e06SGarrett D'Amore #define PCRF_CC_FC_WDOG_TMR_DIS_LBN 15 2095*49ef7e06SGarrett D'Amore #define PCRF_CC_FC_WDOG_TMR_DIS_WIDTH 1 2096*49ef7e06SGarrett D'Amore #define PCRF_CC_SI1_LBN 8 2097*49ef7e06SGarrett D'Amore #define PCRF_CC_SI1_WIDTH 3 2098*49ef7e06SGarrett D'Amore #define PCRF_CC_SKIP_INT_VAL_LBN 0 2099*49ef7e06SGarrett D'Amore #define PCRF_CC_SKIP_INT_VAL_WIDTH 11 2100*49ef7e06SGarrett D'Amore #define PCRF_CC_SI0_LBN 0 2101*49ef7e06SGarrett D'Amore #define PCRF_CC_SI0_WIDTH 8 2102*49ef7e06SGarrett D'Amore 2103*49ef7e06SGarrett D'Amore 2104*49ef7e06SGarrett D'Amore /* 2105*49ef7e06SGarrett D'Amore * PC_SYM_TMR_REG(16bit): 2106*49ef7e06SGarrett D'Amore * Symbol timer register 2107*49ef7e06SGarrett D'Amore */ 2108*49ef7e06SGarrett D'Amore 2109*49ef7e06SGarrett D'Amore #define PCR_AB_SYM_TMR_REG 0x0000071c 2110*49ef7e06SGarrett D'Amore /* falcona0,falconb0=pci_f0_config */ 2111*49ef7e06SGarrett D'Amore 2112*49ef7e06SGarrett D'Amore #define PCRF_AB_ET_LBN 11 2113*49ef7e06SGarrett D'Amore #define PCRF_AB_ET_WIDTH 4 2114*49ef7e06SGarrett D'Amore #define PCRF_AB_SI1_LBN 8 2115*49ef7e06SGarrett D'Amore #define PCRF_AB_SI1_WIDTH 3 2116*49ef7e06SGarrett D'Amore #define PCRF_AB_SI0_LBN 0 2117*49ef7e06SGarrett D'Amore #define PCRF_AB_SI0_WIDTH 8 2118*49ef7e06SGarrett D'Amore 2119*49ef7e06SGarrett D'Amore 2120*49ef7e06SGarrett D'Amore /* 2121*49ef7e06SGarrett D'Amore * PC_FLT_MSK_REG(32bit): 2122*49ef7e06SGarrett D'Amore * Filter Mask Register 2 2123*49ef7e06SGarrett D'Amore */ 2124*49ef7e06SGarrett D'Amore 2125*49ef7e06SGarrett D'Amore #define PCR_CC_FLT_MSK_REG 0x00000720 2126*49ef7e06SGarrett D'Amore /* sienaa0=pci_f0_config */ 2127*49ef7e06SGarrett D'Amore 2128*49ef7e06SGarrett D'Amore #define PCRF_CC_DEFAULT_FLT_MSK2_LBN 0 2129*49ef7e06SGarrett D'Amore #define PCRF_CC_DEFAULT_FLT_MSK2_WIDTH 32 2130*49ef7e06SGarrett D'Amore 2131*49ef7e06SGarrett D'Amore 2132*49ef7e06SGarrett D'Amore /* 2133*49ef7e06SGarrett D'Amore * PC_PHY_STAT_REG(32bit): 2134*49ef7e06SGarrett D'Amore * PHY status register 2135*49ef7e06SGarrett D'Amore */ 2136*49ef7e06SGarrett D'Amore 2137*49ef7e06SGarrett D'Amore #define PCR_AB_PHY_STAT_REG 0x00000720 2138*49ef7e06SGarrett D'Amore /* falcona0,falconb0=pci_f0_config */ 2139*49ef7e06SGarrett D'Amore 2140*49ef7e06SGarrett D'Amore #define PCR_CC_PHY_STAT_REG 0x00000810 2141*49ef7e06SGarrett D'Amore /* sienaa0=pci_f0_config */ 2142*49ef7e06SGarrett D'Amore 2143*49ef7e06SGarrett D'Amore #define PCRF_AC_SSL_LBN 3 2144*49ef7e06SGarrett D'Amore #define PCRF_AC_SSL_WIDTH 1 2145*49ef7e06SGarrett D'Amore #define PCRF_AC_SSR_LBN 2 2146*49ef7e06SGarrett D'Amore #define PCRF_AC_SSR_WIDTH 1 2147*49ef7e06SGarrett D'Amore #define PCRF_AC_SSCL_LBN 1 2148*49ef7e06SGarrett D'Amore #define PCRF_AC_SSCL_WIDTH 1 2149*49ef7e06SGarrett D'Amore #define PCRF_AC_SSCD_LBN 0 2150*49ef7e06SGarrett D'Amore #define PCRF_AC_SSCD_WIDTH 1 2151*49ef7e06SGarrett D'Amore 2152*49ef7e06SGarrett D'Amore 2153*49ef7e06SGarrett D'Amore /* 2154*49ef7e06SGarrett D'Amore * PC_PHY_CTL_REG(32bit): 2155*49ef7e06SGarrett D'Amore * PHY control register 2156*49ef7e06SGarrett D'Amore */ 2157*49ef7e06SGarrett D'Amore 2158*49ef7e06SGarrett D'Amore #define PCR_AB_PHY_CTL_REG 0x00000724 2159*49ef7e06SGarrett D'Amore /* falcona0,falconb0=pci_f0_config */ 2160*49ef7e06SGarrett D'Amore 2161*49ef7e06SGarrett D'Amore #define PCR_CC_PHY_CTL_REG 0x00000814 2162*49ef7e06SGarrett D'Amore /* sienaa0=pci_f0_config */ 2163*49ef7e06SGarrett D'Amore 2164*49ef7e06SGarrett D'Amore #define PCRF_AC_BD_LBN 31 2165*49ef7e06SGarrett D'Amore #define PCRF_AC_BD_WIDTH 1 2166*49ef7e06SGarrett D'Amore #define PCRF_AC_CDS_LBN 30 2167*49ef7e06SGarrett D'Amore #define PCRF_AC_CDS_WIDTH 1 2168*49ef7e06SGarrett D'Amore #define PCRF_AC_DWRAP_LB_LBN 29 2169*49ef7e06SGarrett D'Amore #define PCRF_AC_DWRAP_LB_WIDTH 1 2170*49ef7e06SGarrett D'Amore #define PCRF_AC_EBD_LBN 28 2171*49ef7e06SGarrett D'Amore #define PCRF_AC_EBD_WIDTH 1 2172*49ef7e06SGarrett D'Amore #define PCRF_AC_SNR_LBN 27 2173*49ef7e06SGarrett D'Amore #define PCRF_AC_SNR_WIDTH 1 2174*49ef7e06SGarrett D'Amore #define PCRF_AC_RX_NOT_DET_LBN 2 2175*49ef7e06SGarrett D'Amore #define PCRF_AC_RX_NOT_DET_WIDTH 1 2176*49ef7e06SGarrett D'Amore #define PCRF_AC_FORCE_LOS_VAL_LBN 1 2177*49ef7e06SGarrett D'Amore #define PCRF_AC_FORCE_LOS_VAL_WIDTH 1 2178*49ef7e06SGarrett D'Amore #define PCRF_AC_FORCE_LOS_EN_LBN 0 2179*49ef7e06SGarrett D'Amore #define PCRF_AC_FORCE_LOS_EN_WIDTH 1 2180*49ef7e06SGarrett D'Amore 2181*49ef7e06SGarrett D'Amore 2182*49ef7e06SGarrett D'Amore /* 2183*49ef7e06SGarrett D'Amore * PC_DEBUG0_REG(32bit): 2184*49ef7e06SGarrett D'Amore * Debug register 0 2185*49ef7e06SGarrett D'Amore */ 2186*49ef7e06SGarrett D'Amore 2187*49ef7e06SGarrett D'Amore #define PCR_AC_DEBUG0_REG 0x00000728 2188*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0=pci_f0_config */ 2189*49ef7e06SGarrett D'Amore 2190*49ef7e06SGarrett D'Amore #define PCRF_AC_CDI03_LBN 24 2191*49ef7e06SGarrett D'Amore #define PCRF_AC_CDI03_WIDTH 8 2192*49ef7e06SGarrett D'Amore #define PCRF_AC_CDI0_LBN 0 2193*49ef7e06SGarrett D'Amore #define PCRF_AC_CDI0_WIDTH 32 2194*49ef7e06SGarrett D'Amore #define PCRF_AC_CDI02_LBN 16 2195*49ef7e06SGarrett D'Amore #define PCRF_AC_CDI02_WIDTH 8 2196*49ef7e06SGarrett D'Amore #define PCRF_AC_CDI01_LBN 8 2197*49ef7e06SGarrett D'Amore #define PCRF_AC_CDI01_WIDTH 8 2198*49ef7e06SGarrett D'Amore #define PCRF_AC_CDI00_LBN 0 2199*49ef7e06SGarrett D'Amore #define PCRF_AC_CDI00_WIDTH 8 2200*49ef7e06SGarrett D'Amore 2201*49ef7e06SGarrett D'Amore 2202*49ef7e06SGarrett D'Amore /* 2203*49ef7e06SGarrett D'Amore * PC_DEBUG1_REG(32bit): 2204*49ef7e06SGarrett D'Amore * Debug register 1 2205*49ef7e06SGarrett D'Amore */ 2206*49ef7e06SGarrett D'Amore 2207*49ef7e06SGarrett D'Amore #define PCR_AC_DEBUG1_REG 0x0000072c 2208*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0=pci_f0_config */ 2209*49ef7e06SGarrett D'Amore 2210*49ef7e06SGarrett D'Amore #define PCRF_AC_CDI13_LBN 24 2211*49ef7e06SGarrett D'Amore #define PCRF_AC_CDI13_WIDTH 8 2212*49ef7e06SGarrett D'Amore #define PCRF_AC_CDI1_LBN 0 2213*49ef7e06SGarrett D'Amore #define PCRF_AC_CDI1_WIDTH 32 2214*49ef7e06SGarrett D'Amore #define PCRF_AC_CDI12_LBN 16 2215*49ef7e06SGarrett D'Amore #define PCRF_AC_CDI12_WIDTH 8 2216*49ef7e06SGarrett D'Amore #define PCRF_AC_CDI11_LBN 8 2217*49ef7e06SGarrett D'Amore #define PCRF_AC_CDI11_WIDTH 8 2218*49ef7e06SGarrett D'Amore #define PCRF_AC_CDI10_LBN 0 2219*49ef7e06SGarrett D'Amore #define PCRF_AC_CDI10_WIDTH 8 2220*49ef7e06SGarrett D'Amore 2221*49ef7e06SGarrett D'Amore 2222*49ef7e06SGarrett D'Amore /* 2223*49ef7e06SGarrett D'Amore * PC_XPFCC_STAT_REG(24bit): 2224*49ef7e06SGarrett D'Amore * documentation to be written for sum_PC_XPFCC_STAT_REG 2225*49ef7e06SGarrett D'Amore */ 2226*49ef7e06SGarrett D'Amore 2227*49ef7e06SGarrett D'Amore #define PCR_AC_XPFCC_STAT_REG 0x00000730 2228*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0=pci_f0_config */ 2229*49ef7e06SGarrett D'Amore 2230*49ef7e06SGarrett D'Amore #define PCRF_AC_XPDC_LBN 12 2231*49ef7e06SGarrett D'Amore #define PCRF_AC_XPDC_WIDTH 8 2232*49ef7e06SGarrett D'Amore #define PCRF_AC_XPHC_LBN 0 2233*49ef7e06SGarrett D'Amore #define PCRF_AC_XPHC_WIDTH 12 2234*49ef7e06SGarrett D'Amore 2235*49ef7e06SGarrett D'Amore 2236*49ef7e06SGarrett D'Amore /* 2237*49ef7e06SGarrett D'Amore * PC_XNPFCC_STAT_REG(24bit): 2238*49ef7e06SGarrett D'Amore * documentation to be written for sum_PC_XNPFCC_STAT_REG 2239*49ef7e06SGarrett D'Amore */ 2240*49ef7e06SGarrett D'Amore 2241*49ef7e06SGarrett D'Amore #define PCR_AC_XNPFCC_STAT_REG 0x00000734 2242*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0=pci_f0_config */ 2243*49ef7e06SGarrett D'Amore 2244*49ef7e06SGarrett D'Amore #define PCRF_AC_XNPDC_LBN 12 2245*49ef7e06SGarrett D'Amore #define PCRF_AC_XNPDC_WIDTH 8 2246*49ef7e06SGarrett D'Amore #define PCRF_AC_XNPHC_LBN 0 2247*49ef7e06SGarrett D'Amore #define PCRF_AC_XNPHC_WIDTH 12 2248*49ef7e06SGarrett D'Amore 2249*49ef7e06SGarrett D'Amore 2250*49ef7e06SGarrett D'Amore /* 2251*49ef7e06SGarrett D'Amore * PC_XCFCC_STAT_REG(24bit): 2252*49ef7e06SGarrett D'Amore * documentation to be written for sum_PC_XCFCC_STAT_REG 2253*49ef7e06SGarrett D'Amore */ 2254*49ef7e06SGarrett D'Amore 2255*49ef7e06SGarrett D'Amore #define PCR_AC_XCFCC_STAT_REG 0x00000738 2256*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0=pci_f0_config */ 2257*49ef7e06SGarrett D'Amore 2258*49ef7e06SGarrett D'Amore #define PCRF_AC_XCDC_LBN 12 2259*49ef7e06SGarrett D'Amore #define PCRF_AC_XCDC_WIDTH 8 2260*49ef7e06SGarrett D'Amore #define PCRF_AC_XCHC_LBN 0 2261*49ef7e06SGarrett D'Amore #define PCRF_AC_XCHC_WIDTH 12 2262*49ef7e06SGarrett D'Amore 2263*49ef7e06SGarrett D'Amore 2264*49ef7e06SGarrett D'Amore /* 2265*49ef7e06SGarrett D'Amore * PC_Q_STAT_REG(8bit): 2266*49ef7e06SGarrett D'Amore * documentation to be written for sum_PC_Q_STAT_REG 2267*49ef7e06SGarrett D'Amore */ 2268*49ef7e06SGarrett D'Amore 2269*49ef7e06SGarrett D'Amore #define PCR_AC_Q_STAT_REG 0x0000073c 2270*49ef7e06SGarrett D'Amore /* falcona0,falconb0,sienaa0=pci_f0_config */ 2271*49ef7e06SGarrett D'Amore 2272*49ef7e06SGarrett D'Amore #define PCRF_AC_RQNE_LBN 2 2273*49ef7e06SGarrett D'Amore #define PCRF_AC_RQNE_WIDTH 1 2274*49ef7e06SGarrett D'Amore #define PCRF_AC_XRNE_LBN 1 2275*49ef7e06SGarrett D'Amore #define PCRF_AC_XRNE_WIDTH 1 2276*49ef7e06SGarrett D'Amore #define PCRF_AC_RCNR_LBN 0 2277*49ef7e06SGarrett D'Amore #define PCRF_AC_RCNR_WIDTH 1 2278*49ef7e06SGarrett D'Amore 2279*49ef7e06SGarrett D'Amore 2280*49ef7e06SGarrett D'Amore /* 2281*49ef7e06SGarrett D'Amore * PC_VC_XMIT_ARB1_REG(32bit): 2282*49ef7e06SGarrett D'Amore * VC Transmit Arbitration Register 1 2283*49ef7e06SGarrett D'Amore */ 2284*49ef7e06SGarrett D'Amore 2285*49ef7e06SGarrett D'Amore #define PCR_CC_VC_XMIT_ARB1_REG 0x00000740 2286*49ef7e06SGarrett D'Amore /* sienaa0=pci_f0_config */ 2287*49ef7e06SGarrett D'Amore 2288*49ef7e06SGarrett D'Amore 2289*49ef7e06SGarrett D'Amore 2290*49ef7e06SGarrett D'Amore /* 2291*49ef7e06SGarrett D'Amore * PC_VC_XMIT_ARB2_REG(32bit): 2292*49ef7e06SGarrett D'Amore * VC Transmit Arbitration Register 2 2293*49ef7e06SGarrett D'Amore */ 2294*49ef7e06SGarrett D'Amore 2295*49ef7e06SGarrett D'Amore #define PCR_CC_VC_XMIT_ARB2_REG 0x00000744 2296*49ef7e06SGarrett D'Amore /* sienaa0=pci_f0_config */ 2297*49ef7e06SGarrett D'Amore 2298*49ef7e06SGarrett D'Amore 2299*49ef7e06SGarrett D'Amore 2300*49ef7e06SGarrett D'Amore /* 2301*49ef7e06SGarrett D'Amore * PC_VC0_P_RQ_CTL_REG(32bit): 2302*49ef7e06SGarrett D'Amore * VC0 Posted Receive Queue Control 2303*49ef7e06SGarrett D'Amore */ 2304*49ef7e06SGarrett D'Amore 2305*49ef7e06SGarrett D'Amore #define PCR_CC_VC0_P_RQ_CTL_REG 0x00000748 2306*49ef7e06SGarrett D'Amore /* sienaa0=pci_f0_config */ 2307*49ef7e06SGarrett D'Amore 2308*49ef7e06SGarrett D'Amore 2309*49ef7e06SGarrett D'Amore 2310*49ef7e06SGarrett D'Amore /* 2311*49ef7e06SGarrett D'Amore * PC_VC0_NP_RQ_CTL_REG(32bit): 2312*49ef7e06SGarrett D'Amore * VC0 Non-Posted Receive Queue Control 2313*49ef7e06SGarrett D'Amore */ 2314*49ef7e06SGarrett D'Amore 2315*49ef7e06SGarrett D'Amore #define PCR_CC_VC0_NP_RQ_CTL_REG 0x0000074c 2316*49ef7e06SGarrett D'Amore /* sienaa0=pci_f0_config */ 2317*49ef7e06SGarrett D'Amore 2318*49ef7e06SGarrett D'Amore 2319*49ef7e06SGarrett D'Amore 2320*49ef7e06SGarrett D'Amore /* 2321*49ef7e06SGarrett D'Amore * PC_VC0_C_RQ_CTL_REG(32bit): 2322*49ef7e06SGarrett D'Amore * VC0 Completion Receive Queue Control 2323*49ef7e06SGarrett D'Amore */ 2324*49ef7e06SGarrett D'Amore 2325*49ef7e06SGarrett D'Amore #define PCR_CC_VC0_C_RQ_CTL_REG 0x00000750 2326*49ef7e06SGarrett D'Amore /* sienaa0=pci_f0_config */ 2327*49ef7e06SGarrett D'Amore 2328*49ef7e06SGarrett D'Amore 2329*49ef7e06SGarrett D'Amore 2330*49ef7e06SGarrett D'Amore /* 2331*49ef7e06SGarrett D'Amore * PC_GEN2_REG(32bit): 2332*49ef7e06SGarrett D'Amore * Gen2 Register 2333*49ef7e06SGarrett D'Amore */ 2334*49ef7e06SGarrett D'Amore 2335*49ef7e06SGarrett D'Amore #define PCR_CC_GEN2_REG 0x0000080c 2336*49ef7e06SGarrett D'Amore /* sienaa0=pci_f0_config */ 2337*49ef7e06SGarrett D'Amore 2338*49ef7e06SGarrett D'Amore #define PCRF_CC_SET_DE_EMPHASIS_LBN 20 2339*49ef7e06SGarrett D'Amore #define PCRF_CC_SET_DE_EMPHASIS_WIDTH 1 2340*49ef7e06SGarrett D'Amore #define PCRF_CC_CFG_TX_COMPLIANCE_LBN 19 2341*49ef7e06SGarrett D'Amore #define PCRF_CC_CFG_TX_COMPLIANCE_WIDTH 1 2342*49ef7e06SGarrett D'Amore #define PCRF_CC_CFG_TX_SWING_LBN 18 2343*49ef7e06SGarrett D'Amore #define PCRF_CC_CFG_TX_SWING_WIDTH 1 2344*49ef7e06SGarrett D'Amore #define PCRF_CC_DIR_SPEED_CHANGE_LBN 17 2345*49ef7e06SGarrett D'Amore #define PCRF_CC_DIR_SPEED_CHANGE_WIDTH 1 2346*49ef7e06SGarrett D'Amore #define PCRF_CC_LANE_ENABLE_LBN 8 2347*49ef7e06SGarrett D'Amore #define PCRF_CC_LANE_ENABLE_WIDTH 9 2348*49ef7e06SGarrett D'Amore #define PCRF_CC_NUM_FTS_LBN 0 2349*49ef7e06SGarrett D'Amore #define PCRF_CC_NUM_FTS_WIDTH 8 2350*49ef7e06SGarrett D'Amore 2351*49ef7e06SGarrett D'Amore 2352*49ef7e06SGarrett D'Amore #ifdef __cplusplus 2353*49ef7e06SGarrett D'Amore } 2354*49ef7e06SGarrett D'Amore #endif 2355*49ef7e06SGarrett D'Amore 2356*49ef7e06SGarrett D'Amore #endif /* _SYS_EFX_REGS_PCI_H */ 2357