1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * EHCI Host Controller Driver (EHCI) 30 * 31 * The EHCI driver is a software driver which interfaces to the Universal 32 * Serial Bus layer (USBA) and the Host Controller (HC). The interface to 33 * the Host Controller is defined by the EHCI Host Controller Interface. 34 * 35 * This module contains the main EHCI driver code which handles all USB 36 * transfers, bandwidth allocations and other general functionalities. 37 */ 38 39 #include <sys/usb/hcd/ehci/ehcid.h> 40 #include <sys/usb/hcd/ehci/ehci_isoch.h> 41 #include <sys/usb/hcd/ehci/ehci_xfer.h> 42 43 /* 44 * EHCI MSI tunable: 45 * 46 * By default MSI is enabled on all supported platforms except for the 47 * EHCI controller of ULI1575 South bridge. 48 */ 49 boolean_t ehci_enable_msi = B_TRUE; 50 51 /* Pointer to the state structure */ 52 extern void *ehci_statep; 53 54 extern void ehci_handle_endpoint_reclaimation(ehci_state_t *); 55 56 extern uint_t ehci_vt62x2_workaround; 57 extern int force_ehci_off; 58 59 /* Adjustable variables for the size of the pools */ 60 int ehci_qh_pool_size = EHCI_QH_POOL_SIZE; 61 int ehci_qtd_pool_size = EHCI_QTD_POOL_SIZE; 62 63 /* 64 * Initialize the values which the order of 32ms intr qh are executed 65 * by the host controller in the lattice tree. 66 */ 67 static uchar_t ehci_index[EHCI_NUM_INTR_QH_LISTS] = 68 {0x00, 0x10, 0x08, 0x18, 69 0x04, 0x14, 0x0c, 0x1c, 70 0x02, 0x12, 0x0a, 0x1a, 71 0x06, 0x16, 0x0e, 0x1e, 72 0x01, 0x11, 0x09, 0x19, 73 0x05, 0x15, 0x0d, 0x1d, 74 0x03, 0x13, 0x0b, 0x1b, 75 0x07, 0x17, 0x0f, 0x1f}; 76 77 /* 78 * Initialize the values which are used to calculate start split mask 79 * for the low/full/high speed interrupt and isochronous endpoints. 80 */ 81 static uint_t ehci_start_split_mask[15] = { 82 /* 83 * For high/full/low speed usb devices. For high speed 84 * device with polling interval greater than or equal 85 * to 8us (125us). 86 */ 87 0x01, /* 00000001 */ 88 0x02, /* 00000010 */ 89 0x04, /* 00000100 */ 90 0x08, /* 00001000 */ 91 0x10, /* 00010000 */ 92 0x20, /* 00100000 */ 93 0x40, /* 01000000 */ 94 0x80, /* 10000000 */ 95 96 /* Only for high speed devices with polling interval 4us */ 97 0x11, /* 00010001 */ 98 0x22, /* 00100010 */ 99 0x44, /* 01000100 */ 100 0x88, /* 10001000 */ 101 102 /* Only for high speed devices with polling interval 2us */ 103 0x55, /* 01010101 */ 104 0xaa, /* 10101010 */ 105 106 /* Only for high speed devices with polling interval 1us */ 107 0xff /* 11111111 */ 108 }; 109 110 /* 111 * Initialize the values which are used to calculate complete split mask 112 * for the low/full speed interrupt and isochronous endpoints. 113 */ 114 static uint_t ehci_intr_complete_split_mask[7] = { 115 /* Only full/low speed devices */ 116 0x1c, /* 00011100 */ 117 0x38, /* 00111000 */ 118 0x70, /* 01110000 */ 119 0xe0, /* 11100000 */ 120 0x00, /* Need FSTN feature */ 121 0x00, /* Need FSTN feature */ 122 0x00 /* Need FSTN feature */ 123 }; 124 125 126 /* 127 * EHCI Internal Function Prototypes 128 */ 129 130 /* Host Controller Driver (HCD) initialization functions */ 131 void ehci_set_dma_attributes(ehci_state_t *ehcip); 132 int ehci_allocate_pools(ehci_state_t *ehcip); 133 void ehci_decode_ddi_dma_addr_bind_handle_result( 134 ehci_state_t *ehcip, 135 int result); 136 int ehci_map_regs(ehci_state_t *ehcip); 137 int ehci_register_intrs_and_init_mutex( 138 ehci_state_t *ehcip); 139 static int ehci_add_intrs(ehci_state_t *ehcip, 140 int intr_type); 141 int ehci_init_ctlr(ehci_state_t *ehcip, 142 int init_type); 143 static int ehci_take_control(ehci_state_t *ehcip); 144 static int ehci_init_periodic_frame_lst_table( 145 ehci_state_t *ehcip); 146 static void ehci_build_interrupt_lattice( 147 ehci_state_t *ehcip); 148 usba_hcdi_ops_t *ehci_alloc_hcdi_ops(ehci_state_t *ehcip); 149 150 /* Host Controller Driver (HCD) deinitialization functions */ 151 int ehci_cleanup(ehci_state_t *ehcip); 152 static void ehci_rem_intrs(ehci_state_t *ehcip); 153 int ehci_cpr_suspend(ehci_state_t *ehcip); 154 int ehci_cpr_resume(ehci_state_t *ehcip); 155 156 /* Bandwidth Allocation functions */ 157 int ehci_allocate_bandwidth(ehci_state_t *ehcip, 158 usba_pipe_handle_data_t *ph, 159 uint_t *pnode, 160 uchar_t *smask, 161 uchar_t *cmask); 162 static int ehci_allocate_high_speed_bandwidth( 163 ehci_state_t *ehcip, 164 usba_pipe_handle_data_t *ph, 165 uint_t *hnode, 166 uchar_t *smask, 167 uchar_t *cmask); 168 static int ehci_allocate_classic_tt_bandwidth( 169 ehci_state_t *ehcip, 170 usba_pipe_handle_data_t *ph, 171 uint_t pnode); 172 void ehci_deallocate_bandwidth(ehci_state_t *ehcip, 173 usba_pipe_handle_data_t *ph, 174 uint_t pnode, 175 uchar_t smask, 176 uchar_t cmask); 177 static void ehci_deallocate_high_speed_bandwidth( 178 ehci_state_t *ehcip, 179 usba_pipe_handle_data_t *ph, 180 uint_t hnode, 181 uchar_t smask, 182 uchar_t cmask); 183 static void ehci_deallocate_classic_tt_bandwidth( 184 ehci_state_t *ehcip, 185 usba_pipe_handle_data_t *ph, 186 uint_t pnode); 187 static int ehci_compute_high_speed_bandwidth( 188 ehci_state_t *ehcip, 189 usb_ep_descr_t *endpoint, 190 usb_port_status_t port_status, 191 uint_t *sbandwidth, 192 uint_t *cbandwidth); 193 static int ehci_compute_classic_bandwidth( 194 usb_ep_descr_t *endpoint, 195 usb_port_status_t port_status, 196 uint_t *bandwidth); 197 int ehci_adjust_polling_interval( 198 ehci_state_t *ehcip, 199 usb_ep_descr_t *endpoint, 200 usb_port_status_t port_status); 201 static int ehci_adjust_high_speed_polling_interval( 202 ehci_state_t *ehcip, 203 usb_ep_descr_t *endpoint); 204 static uint_t ehci_lattice_height(uint_t interval); 205 static uint_t ehci_lattice_parent(uint_t node); 206 static uint_t ehci_find_periodic_node( 207 uint_t leaf, 208 int interval); 209 static uint_t ehci_leftmost_leaf(uint_t node, 210 uint_t height); 211 static uint_t ehci_pow_2(uint_t x); 212 static uint_t ehci_log_2(uint_t x); 213 static int ehci_find_bestfit_hs_mask( 214 ehci_state_t *ehcip, 215 uchar_t *smask, 216 uint_t *pnode, 217 usb_ep_descr_t *endpoint, 218 uint_t bandwidth, 219 int interval); 220 static int ehci_find_bestfit_ls_intr_mask( 221 ehci_state_t *ehcip, 222 uchar_t *smask, 223 uchar_t *cmask, 224 uint_t *pnode, 225 uint_t sbandwidth, 226 uint_t cbandwidth, 227 int interval); 228 static int ehci_find_bestfit_sitd_in_mask( 229 ehci_state_t *ehcip, 230 uchar_t *smask, 231 uchar_t *cmask, 232 uint_t *pnode, 233 uint_t sbandwidth, 234 uint_t cbandwidth, 235 int interval); 236 static int ehci_find_bestfit_sitd_out_mask( 237 ehci_state_t *ehcip, 238 uchar_t *smask, 239 uint_t *pnode, 240 uint_t sbandwidth, 241 int interval); 242 static uint_t ehci_calculate_bw_availability_mask( 243 ehci_state_t *ehcip, 244 uint_t bandwidth, 245 int leaf, 246 int leaf_count, 247 uchar_t *bw_mask); 248 static void ehci_update_bw_availability( 249 ehci_state_t *ehcip, 250 int bandwidth, 251 int leftmost_leaf, 252 int leaf_count, 253 uchar_t mask); 254 255 /* Miscellaneous functions */ 256 ehci_state_t *ehci_obtain_state( 257 dev_info_t *dip); 258 int ehci_state_is_operational( 259 ehci_state_t *ehcip); 260 int ehci_do_soft_reset( 261 ehci_state_t *ehcip); 262 usb_req_attrs_t ehci_get_xfer_attrs(ehci_state_t *ehcip, 263 ehci_pipe_private_t *pp, 264 ehci_trans_wrapper_t *tw); 265 usb_frame_number_t ehci_get_current_frame_number( 266 ehci_state_t *ehcip); 267 static void ehci_cpr_cleanup( 268 ehci_state_t *ehcip); 269 int ehci_wait_for_sof( 270 ehci_state_t *ehcip); 271 void ehci_toggle_scheduler( 272 ehci_state_t *ehcip); 273 void ehci_print_caps(ehci_state_t *ehcip); 274 void ehci_print_regs(ehci_state_t *ehcip); 275 void ehci_print_qh(ehci_state_t *ehcip, 276 ehci_qh_t *qh); 277 void ehci_print_qtd(ehci_state_t *ehcip, 278 ehci_qtd_t *qtd); 279 void ehci_create_stats(ehci_state_t *ehcip); 280 void ehci_destroy_stats(ehci_state_t *ehcip); 281 void ehci_do_intrs_stats(ehci_state_t *ehcip, 282 int val); 283 void ehci_do_byte_stats(ehci_state_t *ehcip, 284 size_t len, 285 uint8_t attr, 286 uint8_t addr); 287 288 /* 289 * check if this ehci controller can support PM 290 */ 291 int 292 ehci_hcdi_pm_support(dev_info_t *dip) 293 { 294 ehci_state_t *ehcip = ddi_get_soft_state(ehci_statep, 295 ddi_get_instance(dip)); 296 297 if (((ehcip->ehci_vendor_id == PCI_VENDOR_NEC_COMBO) && 298 (ehcip->ehci_device_id == PCI_DEVICE_NEC_COMBO)) || 299 300 ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) && 301 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575)) || 302 303 (ehcip->ehci_vendor_id == PCI_VENDOR_VIA)) { 304 305 return (USB_SUCCESS); 306 } 307 308 return (USB_FAILURE); 309 } 310 311 312 /* 313 * Host Controller Driver (HCD) initialization functions 314 */ 315 316 /* 317 * ehci_set_dma_attributes: 318 * 319 * Set the limits in the DMA attributes structure. Most of the values used 320 * in the DMA limit structures are the default values as specified by the 321 * Writing PCI device drivers document. 322 */ 323 void 324 ehci_set_dma_attributes(ehci_state_t *ehcip) 325 { 326 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 327 "ehci_set_dma_attributes:"); 328 329 /* Initialize the DMA attributes */ 330 ehcip->ehci_dma_attr.dma_attr_version = DMA_ATTR_V0; 331 ehcip->ehci_dma_attr.dma_attr_addr_lo = 0x00000000ull; 332 ehcip->ehci_dma_attr.dma_attr_addr_hi = 0xfffffffeull; 333 334 /* 32 bit addressing */ 335 ehcip->ehci_dma_attr.dma_attr_count_max = EHCI_DMA_ATTR_COUNT_MAX; 336 337 /* Byte alignment */ 338 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 339 340 /* 341 * Since PCI specification is byte alignment, the 342 * burst size field should be set to 1 for PCI devices. 343 */ 344 ehcip->ehci_dma_attr.dma_attr_burstsizes = 0x1; 345 346 ehcip->ehci_dma_attr.dma_attr_minxfer = 0x1; 347 ehcip->ehci_dma_attr.dma_attr_maxxfer = EHCI_DMA_ATTR_MAX_XFER; 348 ehcip->ehci_dma_attr.dma_attr_seg = 0xffffffffull; 349 ehcip->ehci_dma_attr.dma_attr_sgllen = 1; 350 ehcip->ehci_dma_attr.dma_attr_granular = EHCI_DMA_ATTR_GRANULAR; 351 ehcip->ehci_dma_attr.dma_attr_flags = 0; 352 } 353 354 355 /* 356 * ehci_allocate_pools: 357 * 358 * Allocate the system memory for the Endpoint Descriptor (QH) and for the 359 * Transfer Descriptor (QTD) pools. Both QH and QTD structures must be aligned 360 * to a 16 byte boundary. 361 */ 362 int 363 ehci_allocate_pools(ehci_state_t *ehcip) 364 { 365 ddi_device_acc_attr_t dev_attr; 366 size_t real_length; 367 int result; 368 uint_t ccount; 369 int i; 370 371 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 372 "ehci_allocate_pools:"); 373 374 /* The host controller will be little endian */ 375 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 376 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 377 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 378 379 /* Byte alignment */ 380 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_TD_QH_ALIGNMENT; 381 382 /* Allocate the QTD pool DMA handle */ 383 if (ddi_dma_alloc_handle(ehcip->ehci_dip, &ehcip->ehci_dma_attr, 384 DDI_DMA_SLEEP, 0, 385 &ehcip->ehci_qtd_pool_dma_handle) != DDI_SUCCESS) { 386 387 goto failure; 388 } 389 390 /* Allocate the memory for the QTD pool */ 391 if (ddi_dma_mem_alloc(ehcip->ehci_qtd_pool_dma_handle, 392 ehci_qtd_pool_size * sizeof (ehci_qtd_t), 393 &dev_attr, 394 DDI_DMA_CONSISTENT, 395 DDI_DMA_SLEEP, 396 0, 397 (caddr_t *)&ehcip->ehci_qtd_pool_addr, 398 &real_length, 399 &ehcip->ehci_qtd_pool_mem_handle)) { 400 401 goto failure; 402 } 403 404 /* Map the QTD pool into the I/O address space */ 405 result = ddi_dma_addr_bind_handle( 406 ehcip->ehci_qtd_pool_dma_handle, 407 NULL, 408 (caddr_t)ehcip->ehci_qtd_pool_addr, 409 real_length, 410 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 411 DDI_DMA_SLEEP, 412 NULL, 413 &ehcip->ehci_qtd_pool_cookie, 414 &ccount); 415 416 bzero((void *)ehcip->ehci_qtd_pool_addr, 417 ehci_qtd_pool_size * sizeof (ehci_qtd_t)); 418 419 /* Process the result */ 420 if (result == DDI_DMA_MAPPED) { 421 /* The cookie count should be 1 */ 422 if (ccount != 1) { 423 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 424 "ehci_allocate_pools: More than 1 cookie"); 425 426 goto failure; 427 } 428 } else { 429 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 430 "ehci_allocate_pools: Result = %d", result); 431 432 ehci_decode_ddi_dma_addr_bind_handle_result(ehcip, result); 433 434 goto failure; 435 } 436 437 /* 438 * DMA addresses for QTD pools are bound 439 */ 440 ehcip->ehci_dma_addr_bind_flag |= EHCI_QTD_POOL_BOUND; 441 442 /* Initialize the QTD pool */ 443 for (i = 0; i < ehci_qtd_pool_size; i ++) { 444 Set_QTD(ehcip->ehci_qtd_pool_addr[i]. 445 qtd_state, EHCI_QTD_FREE); 446 } 447 448 /* Allocate the QTD pool DMA handle */ 449 if (ddi_dma_alloc_handle(ehcip->ehci_dip, 450 &ehcip->ehci_dma_attr, 451 DDI_DMA_SLEEP, 452 0, 453 &ehcip->ehci_qh_pool_dma_handle) != DDI_SUCCESS) { 454 455 goto failure; 456 } 457 458 /* Allocate the memory for the QH pool */ 459 if (ddi_dma_mem_alloc(ehcip->ehci_qh_pool_dma_handle, 460 ehci_qh_pool_size * sizeof (ehci_qh_t), 461 &dev_attr, 462 DDI_DMA_CONSISTENT, 463 DDI_DMA_SLEEP, 464 0, 465 (caddr_t *)&ehcip->ehci_qh_pool_addr, 466 &real_length, 467 &ehcip->ehci_qh_pool_mem_handle) != DDI_SUCCESS) { 468 469 goto failure; 470 } 471 472 result = ddi_dma_addr_bind_handle(ehcip->ehci_qh_pool_dma_handle, 473 NULL, 474 (caddr_t)ehcip->ehci_qh_pool_addr, 475 real_length, 476 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 477 DDI_DMA_SLEEP, 478 NULL, 479 &ehcip->ehci_qh_pool_cookie, 480 &ccount); 481 482 bzero((void *)ehcip->ehci_qh_pool_addr, 483 ehci_qh_pool_size * sizeof (ehci_qh_t)); 484 485 /* Process the result */ 486 if (result == DDI_DMA_MAPPED) { 487 /* The cookie count should be 1 */ 488 if (ccount != 1) { 489 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 490 "ehci_allocate_pools: More than 1 cookie"); 491 492 goto failure; 493 } 494 } else { 495 ehci_decode_ddi_dma_addr_bind_handle_result(ehcip, result); 496 497 goto failure; 498 } 499 500 /* 501 * DMA addresses for QH pools are bound 502 */ 503 ehcip->ehci_dma_addr_bind_flag |= EHCI_QH_POOL_BOUND; 504 505 /* Initialize the QH pool */ 506 for (i = 0; i < ehci_qh_pool_size; i ++) { 507 Set_QH(ehcip->ehci_qh_pool_addr[i].qh_state, EHCI_QH_FREE); 508 } 509 510 /* Byte alignment */ 511 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 512 513 return (DDI_SUCCESS); 514 515 failure: 516 /* Byte alignment */ 517 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 518 519 return (DDI_FAILURE); 520 } 521 522 523 /* 524 * ehci_decode_ddi_dma_addr_bind_handle_result: 525 * 526 * Process the return values of ddi_dma_addr_bind_handle() 527 */ 528 void 529 ehci_decode_ddi_dma_addr_bind_handle_result( 530 ehci_state_t *ehcip, 531 int result) 532 { 533 USB_DPRINTF_L2(PRINT_MASK_ALLOC, ehcip->ehci_log_hdl, 534 "ehci_decode_ddi_dma_addr_bind_handle_result:"); 535 536 switch (result) { 537 case DDI_DMA_PARTIAL_MAP: 538 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 539 "Partial transfers not allowed"); 540 break; 541 case DDI_DMA_INUSE: 542 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 543 "Handle is in use"); 544 break; 545 case DDI_DMA_NORESOURCES: 546 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 547 "No resources"); 548 break; 549 case DDI_DMA_NOMAPPING: 550 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 551 "No mapping"); 552 break; 553 case DDI_DMA_TOOBIG: 554 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 555 "Object is too big"); 556 break; 557 default: 558 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 559 "Unknown dma error"); 560 } 561 } 562 563 564 /* 565 * ehci_map_regs: 566 * 567 * The Host Controller (HC) contains a set of on-chip operational registers 568 * and which should be mapped into a non-cacheable portion of the system 569 * addressable space. 570 */ 571 int 572 ehci_map_regs(ehci_state_t *ehcip) 573 { 574 ddi_device_acc_attr_t attr; 575 uint16_t cmd_reg; 576 uint_t length; 577 578 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, "ehci_map_regs:"); 579 580 /* Check to make sure we have memory access */ 581 if (pci_config_setup(ehcip->ehci_dip, 582 &ehcip->ehci_config_handle) != DDI_SUCCESS) { 583 584 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 585 "ehci_map_regs: Config error"); 586 587 return (DDI_FAILURE); 588 } 589 590 /* Make sure Memory Access Enable is set */ 591 cmd_reg = pci_config_get16(ehcip->ehci_config_handle, PCI_CONF_COMM); 592 593 if (!(cmd_reg & PCI_COMM_MAE)) { 594 595 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 596 "ehci_map_regs: Memory base address access disabled"); 597 598 return (DDI_FAILURE); 599 } 600 601 /* The host controller will be little endian */ 602 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 603 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 604 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 605 606 /* Map in EHCI Capability registers */ 607 if (ddi_regs_map_setup(ehcip->ehci_dip, 1, 608 (caddr_t *)&ehcip->ehci_capsp, 0, 609 sizeof (ehci_caps_t), &attr, 610 &ehcip->ehci_caps_handle) != DDI_SUCCESS) { 611 612 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 613 "ehci_map_regs: Map setup error"); 614 615 return (DDI_FAILURE); 616 } 617 618 length = ddi_get8(ehcip->ehci_caps_handle, 619 (uint8_t *)&ehcip->ehci_capsp->ehci_caps_length); 620 621 /* Free the original mapping */ 622 ddi_regs_map_free(&ehcip->ehci_caps_handle); 623 624 /* Re-map in EHCI Capability and Operational registers */ 625 if (ddi_regs_map_setup(ehcip->ehci_dip, 1, 626 (caddr_t *)&ehcip->ehci_capsp, 0, 627 length + sizeof (ehci_regs_t), &attr, 628 &ehcip->ehci_caps_handle) != DDI_SUCCESS) { 629 630 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 631 "ehci_map_regs: Map setup error"); 632 633 return (DDI_FAILURE); 634 } 635 636 /* Get the pointer to EHCI Operational Register */ 637 ehcip->ehci_regsp = (ehci_regs_t *) 638 ((uintptr_t)ehcip->ehci_capsp + length); 639 640 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 641 "ehci_map_regs: Capsp 0x%p Regsp 0x%p\n", 642 ehcip->ehci_capsp, ehcip->ehci_regsp); 643 644 return (DDI_SUCCESS); 645 } 646 647 /* 648 * The following simulated polling is for debugging purposes only. 649 * It is activated on x86 by setting usb-polling=true in GRUB or ehci.conf. 650 */ 651 static int 652 ehci_is_polled(dev_info_t *dip) 653 { 654 int ret; 655 char *propval; 656 657 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, dip, 0, 658 "usb-polling", &propval) != DDI_SUCCESS) 659 660 return (0); 661 662 ret = (strcmp(propval, "true") == 0); 663 ddi_prop_free(propval); 664 665 return (ret); 666 } 667 668 static void 669 ehci_poll_intr(void *arg) 670 { 671 /* poll every msec */ 672 for (;;) { 673 (void) ehci_intr(arg, NULL); 674 delay(drv_usectohz(1000)); 675 } 676 } 677 678 /* 679 * ehci_register_intrs_and_init_mutex: 680 * 681 * Register interrupts and initialize each mutex and condition variables 682 */ 683 int 684 ehci_register_intrs_and_init_mutex(ehci_state_t *ehcip) 685 { 686 int intr_types; 687 688 #if defined(__x86) 689 uint8_t iline; 690 #endif 691 692 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 693 "ehci_register_intrs_and_init_mutex:"); 694 695 /* 696 * There is a known MSI hardware bug with the EHCI controller 697 * of ULI1575 southbridge. Hence MSI is disabled for this chip. 698 */ 699 if ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) && 700 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575)) { 701 ehcip->ehci_msi_enabled = B_FALSE; 702 } else { 703 /* Set the MSI enable flag from the global EHCI MSI tunable */ 704 ehcip->ehci_msi_enabled = ehci_enable_msi; 705 } 706 707 /* launch polling thread instead of enabling pci interrupt */ 708 if (ehci_is_polled(ehcip->ehci_dip)) { 709 extern pri_t maxclsyspri; 710 711 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 712 "ehci_register_intrs_and_init_mutex: " 713 "running in simulated polled mode"); 714 715 (void) thread_create(NULL, 0, ehci_poll_intr, ehcip, 0, &p0, 716 TS_RUN, maxclsyspri); 717 718 goto skip_intr; 719 } 720 721 #if defined(__x86) 722 /* 723 * Make sure that the interrupt pin is connected to the 724 * interrupt controller on x86. Interrupt line 255 means 725 * "unknown" or "not connected" (PCI spec 6.2.4, footnote 43). 726 * If we would return failure when interrupt line equals 255, then 727 * high speed devices will be routed to companion host controllers. 728 * However, it is not necessary to return failure here, and 729 * o/uhci codes don't check the interrupt line either. 730 * But it's good to log a message here for debug purposes. 731 */ 732 iline = pci_config_get8(ehcip->ehci_config_handle, 733 PCI_CONF_ILINE); 734 735 if (iline == 255) { 736 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 737 "ehci_register_intrs_and_init_mutex: " 738 "interrupt line value out of range (%d)", 739 iline); 740 } 741 #endif /* __x86 */ 742 743 /* Get supported interrupt types */ 744 if (ddi_intr_get_supported_types(ehcip->ehci_dip, 745 &intr_types) != DDI_SUCCESS) { 746 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 747 "ehci_register_intrs_and_init_mutex: " 748 "ddi_intr_get_supported_types failed"); 749 750 return (DDI_FAILURE); 751 } 752 753 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 754 "ehci_register_intrs_and_init_mutex: " 755 "supported interrupt types 0x%x", intr_types); 756 757 if ((intr_types & DDI_INTR_TYPE_MSI) && ehcip->ehci_msi_enabled) { 758 if (ehci_add_intrs(ehcip, DDI_INTR_TYPE_MSI) 759 != DDI_SUCCESS) { 760 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 761 "ehci_register_intrs_and_init_mutex: MSI " 762 "registration failed, trying FIXED interrupt \n"); 763 } else { 764 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 765 "ehci_register_intrs_and_init_mutex: " 766 "Using MSI interrupt type\n"); 767 768 ehcip->ehci_intr_type = DDI_INTR_TYPE_MSI; 769 ehcip->ehci_flags |= EHCI_INTR; 770 } 771 } 772 773 if ((!(ehcip->ehci_flags & EHCI_INTR)) && 774 (intr_types & DDI_INTR_TYPE_FIXED)) { 775 if (ehci_add_intrs(ehcip, DDI_INTR_TYPE_FIXED) 776 != DDI_SUCCESS) { 777 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 778 "ehci_register_intrs_and_init_mutex: " 779 "FIXED interrupt registration failed\n"); 780 781 return (DDI_FAILURE); 782 } 783 784 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 785 "ehci_register_intrs_and_init_mutex: " 786 "Using FIXED interrupt type\n"); 787 788 ehcip->ehci_intr_type = DDI_INTR_TYPE_FIXED; 789 ehcip->ehci_flags |= EHCI_INTR; 790 } 791 792 skip_intr: 793 /* Create prototype for advance on async schedule */ 794 cv_init(&ehcip->ehci_async_schedule_advance_cv, 795 NULL, CV_DRIVER, NULL); 796 797 return (DDI_SUCCESS); 798 } 799 800 801 /* 802 * ehci_add_intrs: 803 * 804 * Register FIXED or MSI interrupts. 805 */ 806 static int 807 ehci_add_intrs(ehci_state_t *ehcip, 808 int intr_type) 809 { 810 int actual, avail, intr_size, count = 0; 811 int i, flag, ret; 812 813 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 814 "ehci_add_intrs: interrupt type 0x%x", intr_type); 815 816 /* Get number of interrupts */ 817 ret = ddi_intr_get_nintrs(ehcip->ehci_dip, intr_type, &count); 818 if ((ret != DDI_SUCCESS) || (count == 0)) { 819 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 820 "ehci_add_intrs: ddi_intr_get_nintrs() failure, " 821 "ret: %d, count: %d", ret, count); 822 823 return (DDI_FAILURE); 824 } 825 826 /* Get number of available interrupts */ 827 ret = ddi_intr_get_navail(ehcip->ehci_dip, intr_type, &avail); 828 if ((ret != DDI_SUCCESS) || (avail == 0)) { 829 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 830 "ehci_add_intrs: ddi_intr_get_navail() failure, " 831 "ret: %d, count: %d", ret, count); 832 833 return (DDI_FAILURE); 834 } 835 836 if (avail < count) { 837 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 838 "ehci_add_intrs: ehci_add_intrs: nintrs () " 839 "returned %d, navail returned %d\n", count, avail); 840 } 841 842 /* Allocate an array of interrupt handles */ 843 intr_size = count * sizeof (ddi_intr_handle_t); 844 ehcip->ehci_htable = kmem_zalloc(intr_size, KM_SLEEP); 845 846 flag = (intr_type == DDI_INTR_TYPE_MSI) ? 847 DDI_INTR_ALLOC_STRICT:DDI_INTR_ALLOC_NORMAL; 848 849 /* call ddi_intr_alloc() */ 850 ret = ddi_intr_alloc(ehcip->ehci_dip, ehcip->ehci_htable, 851 intr_type, 0, count, &actual, flag); 852 853 if ((ret != DDI_SUCCESS) || (actual == 0)) { 854 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 855 "ehci_add_intrs: ddi_intr_alloc() failed %d", ret); 856 857 kmem_free(ehcip->ehci_htable, intr_size); 858 859 return (DDI_FAILURE); 860 } 861 862 if (actual < count) { 863 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 864 "ehci_add_intrs: Requested: %d, Received: %d\n", 865 count, actual); 866 867 for (i = 0; i < actual; i++) 868 (void) ddi_intr_free(ehcip->ehci_htable[i]); 869 870 kmem_free(ehcip->ehci_htable, intr_size); 871 872 return (DDI_FAILURE); 873 } 874 875 ehcip->ehci_intr_cnt = actual; 876 877 if ((ret = ddi_intr_get_pri(ehcip->ehci_htable[0], 878 &ehcip->ehci_intr_pri)) != DDI_SUCCESS) { 879 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 880 "ehci_add_intrs: ddi_intr_get_pri() failed %d", ret); 881 882 for (i = 0; i < actual; i++) 883 (void) ddi_intr_free(ehcip->ehci_htable[i]); 884 885 kmem_free(ehcip->ehci_htable, intr_size); 886 887 return (DDI_FAILURE); 888 } 889 890 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 891 "ehci_add_intrs: Supported Interrupt priority 0x%x", 892 ehcip->ehci_intr_pri); 893 894 /* Test for high level mutex */ 895 if (ehcip->ehci_intr_pri >= ddi_intr_get_hilevel_pri()) { 896 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 897 "ehci_add_intrs: Hi level interrupt not supported"); 898 899 for (i = 0; i < actual; i++) 900 (void) ddi_intr_free(ehcip->ehci_htable[i]); 901 902 kmem_free(ehcip->ehci_htable, intr_size); 903 904 return (DDI_FAILURE); 905 } 906 907 /* Initialize the mutex */ 908 mutex_init(&ehcip->ehci_int_mutex, NULL, MUTEX_DRIVER, 909 DDI_INTR_PRI(ehcip->ehci_intr_pri)); 910 911 /* Call ddi_intr_add_handler() */ 912 for (i = 0; i < actual; i++) { 913 if ((ret = ddi_intr_add_handler(ehcip->ehci_htable[i], 914 ehci_intr, (caddr_t)ehcip, 915 (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) { 916 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 917 "ehci_add_intrs:ddi_intr_add_handler() " 918 "failed %d", ret); 919 920 for (i = 0; i < actual; i++) 921 (void) ddi_intr_free(ehcip->ehci_htable[i]); 922 923 mutex_destroy(&ehcip->ehci_int_mutex); 924 kmem_free(ehcip->ehci_htable, intr_size); 925 926 return (DDI_FAILURE); 927 } 928 } 929 930 if ((ret = ddi_intr_get_cap(ehcip->ehci_htable[0], 931 &ehcip->ehci_intr_cap)) != DDI_SUCCESS) { 932 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 933 "ehci_add_intrs: ddi_intr_get_cap() failed %d", ret); 934 935 for (i = 0; i < actual; i++) { 936 (void) ddi_intr_remove_handler(ehcip->ehci_htable[i]); 937 (void) ddi_intr_free(ehcip->ehci_htable[i]); 938 } 939 940 mutex_destroy(&ehcip->ehci_int_mutex); 941 kmem_free(ehcip->ehci_htable, intr_size); 942 943 return (DDI_FAILURE); 944 } 945 946 /* Enable all interrupts */ 947 if (ehcip->ehci_intr_cap & DDI_INTR_FLAG_BLOCK) { 948 /* Call ddi_intr_block_enable() for MSI interrupts */ 949 (void) ddi_intr_block_enable(ehcip->ehci_htable, 950 ehcip->ehci_intr_cnt); 951 } else { 952 /* Call ddi_intr_enable for MSI or FIXED interrupts */ 953 for (i = 0; i < ehcip->ehci_intr_cnt; i++) 954 (void) ddi_intr_enable(ehcip->ehci_htable[i]); 955 } 956 957 return (DDI_SUCCESS); 958 } 959 960 961 /* 962 * ehci_init_hardware 963 * 964 * take control from BIOS, reset EHCI host controller, and check version, etc. 965 */ 966 int 967 ehci_init_hardware(ehci_state_t *ehcip) 968 { 969 int revision; 970 uint16_t cmd_reg; 971 int abort_on_BIOS_take_over_failure; 972 973 /* Take control from the BIOS */ 974 if (ehci_take_control(ehcip) != USB_SUCCESS) { 975 976 /* read .conf file properties */ 977 abort_on_BIOS_take_over_failure = 978 ddi_prop_get_int(DDI_DEV_T_ANY, 979 ehcip->ehci_dip, DDI_PROP_DONTPASS, 980 "abort-on-BIOS-take-over-failure", 0); 981 982 if (abort_on_BIOS_take_over_failure) { 983 984 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 985 "Unable to take control from BIOS."); 986 987 return (DDI_FAILURE); 988 } 989 990 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 991 "Unable to take control from BIOS. Failure is ignored."); 992 } 993 994 /* set Memory Master Enable */ 995 cmd_reg = pci_config_get16(ehcip->ehci_config_handle, PCI_CONF_COMM); 996 cmd_reg |= (PCI_COMM_MAE | PCI_COMM_ME); 997 pci_config_put16(ehcip->ehci_config_handle, PCI_CONF_COMM, cmd_reg); 998 999 /* Reset the EHCI host controller */ 1000 Set_OpReg(ehci_command, 1001 Get_OpReg(ehci_command) | EHCI_CMD_HOST_CTRL_RESET); 1002 1003 /* Wait 10ms for reset to complete */ 1004 drv_usecwait(EHCI_RESET_TIMEWAIT); 1005 1006 ASSERT(Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED); 1007 1008 /* Verify the version number */ 1009 revision = Get_16Cap(ehci_version); 1010 1011 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1012 "ehci_init_hardware: Revision 0x%x", revision); 1013 1014 /* 1015 * EHCI driver supports EHCI host controllers compliant to 1016 * 0.95 and higher revisions of EHCI specifications. 1017 */ 1018 if (revision < EHCI_REVISION_0_95) { 1019 1020 USB_DPRINTF_L0(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1021 "Revision 0x%x is not supported", revision); 1022 1023 return (DDI_FAILURE); 1024 } 1025 1026 if (ehcip->ehci_hc_soft_state == EHCI_CTLR_INIT_STATE) { 1027 1028 /* Initialize the Frame list base address area */ 1029 if (ehci_init_periodic_frame_lst_table(ehcip) != DDI_SUCCESS) { 1030 1031 return (DDI_FAILURE); 1032 } 1033 1034 /* 1035 * For performance reasons, do not insert anything into the 1036 * asynchronous list or activate the asynch list schedule until 1037 * there is a valid QH. 1038 */ 1039 ehcip->ehci_head_of_async_sched_list = NULL; 1040 1041 if ((ehcip->ehci_vendor_id == PCI_VENDOR_VIA) && 1042 (ehci_vt62x2_workaround & EHCI_VIA_ASYNC_SCHEDULE)) { 1043 /* 1044 * The driver is unable to reliably stop the asynch 1045 * list schedule on VIA VT6202 controllers, so we 1046 * always keep a dummy QH on the list. 1047 */ 1048 ehci_qh_t *dummy_async_qh = 1049 ehci_alloc_qh(ehcip, NULL, NULL); 1050 1051 Set_QH(dummy_async_qh->qh_link_ptr, 1052 ((ehci_qh_cpu_to_iommu(ehcip, dummy_async_qh) & 1053 EHCI_QH_LINK_PTR) | EHCI_QH_LINK_REF_QH)); 1054 1055 /* Set this QH to be the "head" of the circular list */ 1056 Set_QH(dummy_async_qh->qh_ctrl, 1057 Get_QH(dummy_async_qh->qh_ctrl) | 1058 EHCI_QH_CTRL_RECLAIM_HEAD); 1059 1060 Set_QH(dummy_async_qh->qh_next_qtd, 1061 EHCI_QH_NEXT_QTD_PTR_VALID); 1062 Set_QH(dummy_async_qh->qh_alt_next_qtd, 1063 EHCI_QH_ALT_NEXT_QTD_PTR_VALID); 1064 1065 ehcip->ehci_head_of_async_sched_list = dummy_async_qh; 1066 ehcip->ehci_open_async_count++; 1067 } 1068 } 1069 1070 return (DDI_SUCCESS); 1071 } 1072 1073 1074 /* 1075 * ehci_init_workaround 1076 * 1077 * some workarounds during initializing ehci 1078 */ 1079 int 1080 ehci_init_workaround(ehci_state_t *ehcip) 1081 { 1082 /* 1083 * Acer Labs Inc. M5273 EHCI controller does not send 1084 * interrupts unless the Root hub ports are routed to the EHCI 1085 * host controller; so route the ports now, before we test for 1086 * the presence of SOFs interrupts. 1087 */ 1088 if (ehcip->ehci_vendor_id == PCI_VENDOR_ALI) { 1089 /* Route all Root hub ports to EHCI host controller */ 1090 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_EHCI); 1091 } 1092 1093 /* 1094 * VIA chips have some issues and may not work reliably. 1095 * Revisions >= 0x80 are part of a southbridge and appear 1096 * to be reliable with the workaround. 1097 * For revisions < 0x80, if we were bound using class 1098 * complain, else proceed. This will allow the user to 1099 * bind ehci specifically to this chip and not have the 1100 * warnings 1101 */ 1102 if (ehcip->ehci_vendor_id == PCI_VENDOR_VIA) { 1103 1104 if (ehcip->ehci_rev_id >= PCI_VIA_REVISION_6212) { 1105 1106 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1107 "ehci_init_workaround: Applying VIA workarounds " 1108 "for the 6212 chip."); 1109 1110 } else if (strcmp(DEVI(ehcip->ehci_dip)->devi_binding_name, 1111 "pciclass,0c0320") == 0) { 1112 1113 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1114 "Due to recently discovered incompatibilities"); 1115 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1116 "with this USB controller, USB2.x transfer"); 1117 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1118 "support has been disabled. This device will"); 1119 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1120 "continue to function as a USB1.x controller."); 1121 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1122 "If you are interested in enabling USB2.x"); 1123 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1124 "support please, refer to the ehci(7D) man page."); 1125 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1126 "Please also refer to www.sun.com/io for"); 1127 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1128 "Solaris Ready products and to"); 1129 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1130 "www.sun.com/bigadmin/hcl for additional"); 1131 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1132 "compatible USB products."); 1133 1134 return (DDI_FAILURE); 1135 1136 } else if (ehci_vt62x2_workaround) { 1137 1138 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1139 "Applying VIA workarounds"); 1140 } 1141 } 1142 1143 return (DDI_SUCCESS); 1144 } 1145 1146 1147 /* 1148 * ehci_init_check_status 1149 * 1150 * Check if EHCI host controller is running 1151 */ 1152 int 1153 ehci_init_check_status(ehci_state_t *ehcip) 1154 { 1155 clock_t sof_time_wait; 1156 1157 /* 1158 * Get the number of clock ticks to wait. 1159 * This is based on the maximum time it takes for a frame list rollover 1160 * and maximum time wait for SOFs to begin. 1161 */ 1162 sof_time_wait = drv_usectohz((EHCI_NUM_PERIODIC_FRAME_LISTS * 1000) + 1163 EHCI_SOF_TIMEWAIT); 1164 1165 /* Tell the ISR to broadcast ehci_async_schedule_advance_cv */ 1166 ehcip->ehci_flags |= EHCI_CV_INTR; 1167 1168 /* We need to add a delay to allow the chip time to start running */ 1169 (void) cv_timedwait(&ehcip->ehci_async_schedule_advance_cv, 1170 &ehcip->ehci_int_mutex, ddi_get_lbolt() + sof_time_wait); 1171 1172 /* 1173 * Check EHCI host controller is running, otherwise return failure. 1174 */ 1175 if ((ehcip->ehci_flags & EHCI_CV_INTR) || 1176 (Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED)) { 1177 1178 USB_DPRINTF_L0(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1179 "No SOF interrupts have been received, this USB EHCI host" 1180 "controller is unusable"); 1181 1182 /* 1183 * Route all Root hub ports to Classic host 1184 * controller, in case this is an unusable ALI M5273 1185 * EHCI controller. 1186 */ 1187 if (ehcip->ehci_vendor_id == PCI_VENDOR_ALI) { 1188 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_CLASSIC); 1189 } 1190 1191 return (DDI_FAILURE); 1192 } 1193 1194 return (DDI_SUCCESS); 1195 } 1196 1197 1198 /* 1199 * ehci_init_ctlr: 1200 * 1201 * Initialize the Host Controller (HC). 1202 */ 1203 int 1204 ehci_init_ctlr(ehci_state_t *ehcip, 1205 int init_type) 1206 { 1207 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, "ehci_init_ctlr:"); 1208 1209 if (init_type == EHCI_NORMAL_INITIALIZATION) { 1210 1211 if (ehci_init_hardware(ehcip) != DDI_SUCCESS) { 1212 1213 return (DDI_FAILURE); 1214 } 1215 } 1216 1217 /* 1218 * Check for Asynchronous schedule park capability feature. If this 1219 * feature is supported, then, program ehci command register with 1220 * appropriate values.. 1221 */ 1222 if (Get_Cap(ehci_hcc_params) & EHCI_HCC_ASYNC_SCHED_PARK_CAP) { 1223 1224 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1225 "ehci_init_ctlr: Async park mode is supported"); 1226 1227 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) | 1228 (EHCI_CMD_ASYNC_PARK_ENABLE | 1229 EHCI_CMD_ASYNC_PARK_COUNT_3))); 1230 } 1231 1232 /* 1233 * Check for programmable periodic frame list feature. If this 1234 * feature is supported, then, program ehci command register with 1235 * 1024 frame list value. 1236 */ 1237 if (Get_Cap(ehci_hcc_params) & EHCI_HCC_PROG_FRAME_LIST_FLAG) { 1238 1239 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1240 "ehci_init_ctlr: Variable programmable periodic " 1241 "frame list is supported"); 1242 1243 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) | 1244 EHCI_CMD_FRAME_1024_SIZE)); 1245 } 1246 1247 /* 1248 * Currently EHCI driver doesn't support 64 bit addressing. 1249 * 1250 * If we are using 64 bit addressing capability, then, program 1251 * ehci_ctrl_segment register with 4 Gigabyte segment where all 1252 * of the interface data structures are allocated. 1253 */ 1254 if (Get_Cap(ehci_hcc_params) & EHCI_HCC_64BIT_ADDR_CAP) { 1255 1256 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1257 "ehci_init_ctlr: EHCI driver doesn't support " 1258 "64 bit addressing"); 1259 } 1260 1261 /* 64 bit addressing is not support */ 1262 Set_OpReg(ehci_ctrl_segment, 0x00000000); 1263 1264 /* Turn on/off the schedulers */ 1265 ehci_toggle_scheduler(ehcip); 1266 1267 /* Set host controller soft state to operational */ 1268 ehcip->ehci_hc_soft_state = EHCI_CTLR_OPERATIONAL_STATE; 1269 1270 /* 1271 * Set the Periodic Frame List Base Address register with the 1272 * starting physical address of the Periodic Frame List. 1273 */ 1274 Set_OpReg(ehci_periodic_list_base, 1275 (uint32_t)(ehcip->ehci_pflt_cookie.dmac_address & 1276 EHCI_PERIODIC_LIST_BASE)); 1277 1278 /* 1279 * Set ehci_interrupt to enable all interrupts except Root 1280 * Hub Status change interrupt. 1281 */ 1282 Set_OpReg(ehci_interrupt, EHCI_INTR_HOST_SYSTEM_ERROR | 1283 EHCI_INTR_FRAME_LIST_ROLLOVER | EHCI_INTR_USB_ERROR | 1284 EHCI_INTR_USB); 1285 1286 /* 1287 * Set the desired interrupt threshold and turn on EHCI host controller. 1288 */ 1289 Set_OpReg(ehci_command, 1290 ((Get_OpReg(ehci_command) & ~EHCI_CMD_INTR_THRESHOLD) | 1291 (EHCI_CMD_01_INTR | EHCI_CMD_HOST_CTRL_RUN))); 1292 1293 ASSERT(Get_OpReg(ehci_command) & EHCI_CMD_HOST_CTRL_RUN); 1294 1295 if (init_type == EHCI_NORMAL_INITIALIZATION) { 1296 1297 if (ehci_init_workaround(ehcip) != DDI_SUCCESS) { 1298 1299 /* Set host controller soft state to error */ 1300 ehcip->ehci_hc_soft_state = EHCI_CTLR_ERROR_STATE; 1301 1302 return (DDI_FAILURE); 1303 } 1304 1305 if (ehci_init_check_status(ehcip) != DDI_SUCCESS) { 1306 1307 /* Set host controller soft state to error */ 1308 ehcip->ehci_hc_soft_state = EHCI_CTLR_ERROR_STATE; 1309 1310 return (DDI_FAILURE); 1311 } 1312 1313 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1314 "ehci_init_ctlr: SOF's have started"); 1315 } 1316 1317 /* Route all Root hub ports to EHCI host controller */ 1318 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_EHCI); 1319 1320 return (DDI_SUCCESS); 1321 } 1322 1323 /* 1324 * ehci_take_control: 1325 * 1326 * Handshake to take EHCI control from BIOS if necessary. Its only valid for 1327 * x86 machines, because sparc doesn't have a BIOS. 1328 * On x86 machine, the take control process includes 1329 * o get the base address of the extended capability list 1330 * o find out the capability for handoff synchronization in the list. 1331 * o check if BIOS has owned the host controller. 1332 * o set the OS Owned semaphore bit, ask the BIOS to release the ownership. 1333 * o wait for a constant time and check if BIOS has relinquished control. 1334 */ 1335 /* ARGSUSED */ 1336 static int 1337 ehci_take_control(ehci_state_t *ehcip) 1338 { 1339 #if defined(__x86) 1340 uint32_t extended_cap; 1341 uint32_t extended_cap_offset; 1342 uint32_t extended_cap_id; 1343 uint_t retry; 1344 1345 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1346 "ehci_take_control:"); 1347 1348 /* 1349 * According EHCI Spec 2.2.4, get EECP base address from HCCPARAMS 1350 * register. 1351 */ 1352 extended_cap_offset = (Get_Cap(ehci_hcc_params) & EHCI_HCC_EECP) >> 1353 EHCI_HCC_EECP_SHIFT; 1354 1355 /* 1356 * According EHCI Spec 2.2.4, if the extended capability offset is 1357 * less than 40h then its not valid. This means we don't need to 1358 * worry about BIOS handoff. 1359 */ 1360 if (extended_cap_offset < EHCI_HCC_EECP_MIN_OFFSET) { 1361 1362 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1363 "ehci_take_control: Hardware doesn't support legacy."); 1364 1365 goto success; 1366 } 1367 1368 /* 1369 * According EHCI Spec 2.1.7, A zero offset indicates the 1370 * end of the extended capability list. 1371 */ 1372 while (extended_cap_offset) { 1373 1374 /* Get the extended capability value. */ 1375 extended_cap = pci_config_get32(ehcip->ehci_config_handle, 1376 extended_cap_offset); 1377 1378 /* Get the capability ID */ 1379 extended_cap_id = (extended_cap & EHCI_EX_CAP_ID) >> 1380 EHCI_EX_CAP_ID_SHIFT; 1381 1382 /* Check if the card support legacy */ 1383 if (extended_cap_id == EHCI_EX_CAP_ID_BIOS_HANDOFF) { 1384 break; 1385 } 1386 1387 /* Get the offset of the next capability */ 1388 extended_cap_offset = (extended_cap & EHCI_EX_CAP_NEXT_PTR) >> 1389 EHCI_EX_CAP_NEXT_PTR_SHIFT; 1390 } 1391 1392 /* 1393 * Unable to find legacy support in hardware's extended capability list. 1394 * This means we don't need to worry about BIOS handoff. 1395 */ 1396 if (extended_cap_id != EHCI_EX_CAP_ID_BIOS_HANDOFF) { 1397 1398 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1399 "ehci_take_control: Hardware doesn't support legacy"); 1400 1401 goto success; 1402 } 1403 1404 /* Check if BIOS has owned it. */ 1405 if (!(extended_cap & EHCI_LEGSUP_BIOS_OWNED_SEM)) { 1406 1407 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1408 "ehci_take_control: BIOS does not own EHCI"); 1409 1410 goto success; 1411 } 1412 1413 /* 1414 * According EHCI Spec 5.1, The OS driver initiates an ownership 1415 * request by setting the OS Owned semaphore to a one. The OS 1416 * waits for the BIOS Owned bit to go to a zero before attempting 1417 * to use the EHCI controller. The time that OS must wait for BIOS 1418 * to respond to the request for ownership is beyond the scope of 1419 * this specification. 1420 * It waits up to EHCI_TAKEOVER_WAIT_COUNT*EHCI_TAKEOVER_DELAY ms 1421 * for BIOS to release the ownership. 1422 */ 1423 extended_cap |= EHCI_LEGSUP_OS_OWNED_SEM; 1424 pci_config_put32(ehcip->ehci_config_handle, extended_cap_offset, 1425 extended_cap); 1426 1427 for (retry = 0; retry < EHCI_TAKEOVER_WAIT_COUNT; retry++) { 1428 1429 /* wait a special interval */ 1430 #ifndef __lock_lint 1431 delay(drv_usectohz(EHCI_TAKEOVER_DELAY)); 1432 #endif 1433 /* Check to see if the BIOS has released the ownership */ 1434 extended_cap = pci_config_get32( 1435 ehcip->ehci_config_handle, extended_cap_offset); 1436 1437 if (!(extended_cap & EHCI_LEGSUP_BIOS_OWNED_SEM)) { 1438 1439 USB_DPRINTF_L3(PRINT_MASK_ATTA, 1440 ehcip->ehci_log_hdl, 1441 "ehci_take_control: BIOS has released " 1442 "the ownership. retry = %d", retry); 1443 1444 goto success; 1445 } 1446 1447 } 1448 1449 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1450 "ehci_take_control: take control from BIOS failed."); 1451 1452 return (USB_FAILURE); 1453 1454 success: 1455 1456 #endif /* __x86 */ 1457 return (USB_SUCCESS); 1458 } 1459 1460 1461 /* 1462 * ehci_init_periodic_frame_list_table : 1463 * 1464 * Allocate the system memory and initialize Host Controller 1465 * Periodic Frame List table area. The starting of the Periodic 1466 * Frame List Table area must be 4096 byte aligned. 1467 */ 1468 static int 1469 ehci_init_periodic_frame_lst_table(ehci_state_t *ehcip) 1470 { 1471 ddi_device_acc_attr_t dev_attr; 1472 size_t real_length; 1473 uint_t ccount; 1474 int result; 1475 1476 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 1477 1478 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1479 "ehci_init_periodic_frame_lst_table:"); 1480 1481 /* The host controller will be little endian */ 1482 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 1483 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 1484 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1485 1486 /* Force the required 4K restrictive alignment */ 1487 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_PFL_ALIGNMENT; 1488 1489 /* Create space for the Periodic Frame List */ 1490 if (ddi_dma_alloc_handle(ehcip->ehci_dip, &ehcip->ehci_dma_attr, 1491 DDI_DMA_SLEEP, 0, &ehcip->ehci_pflt_dma_handle) != DDI_SUCCESS) { 1492 1493 goto failure; 1494 } 1495 1496 if (ddi_dma_mem_alloc(ehcip->ehci_pflt_dma_handle, 1497 sizeof (ehci_periodic_frame_list_t), 1498 &dev_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, 1499 0, (caddr_t *)&ehcip->ehci_periodic_frame_list_tablep, 1500 &real_length, &ehcip->ehci_pflt_mem_handle)) { 1501 1502 goto failure; 1503 } 1504 1505 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1506 "ehci_init_periodic_frame_lst_table: " 1507 "Real length %lu", real_length); 1508 1509 /* Map the whole Periodic Frame List into the I/O address space */ 1510 result = ddi_dma_addr_bind_handle(ehcip->ehci_pflt_dma_handle, 1511 NULL, (caddr_t)ehcip->ehci_periodic_frame_list_tablep, 1512 real_length, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 1513 DDI_DMA_SLEEP, NULL, &ehcip->ehci_pflt_cookie, &ccount); 1514 1515 if (result == DDI_DMA_MAPPED) { 1516 /* The cookie count should be 1 */ 1517 if (ccount != 1) { 1518 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1519 "ehci_init_periodic_frame_lst_table: " 1520 "More than 1 cookie"); 1521 1522 goto failure; 1523 } 1524 } else { 1525 ehci_decode_ddi_dma_addr_bind_handle_result(ehcip, result); 1526 1527 goto failure; 1528 } 1529 1530 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1531 "ehci_init_periodic_frame_lst_table: virtual 0x%p physical 0x%x", 1532 (void *)ehcip->ehci_periodic_frame_list_tablep, 1533 ehcip->ehci_pflt_cookie.dmac_address); 1534 1535 /* 1536 * DMA addresses for Periodic Frame List are bound. 1537 */ 1538 ehcip->ehci_dma_addr_bind_flag |= EHCI_PFLT_DMA_BOUND; 1539 1540 bzero((void *)ehcip->ehci_periodic_frame_list_tablep, real_length); 1541 1542 /* Initialize the Periodic Frame List */ 1543 ehci_build_interrupt_lattice(ehcip); 1544 1545 /* Reset Byte Alignment to Default */ 1546 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 1547 1548 return (DDI_SUCCESS); 1549 failure: 1550 /* Byte alignment */ 1551 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 1552 1553 return (DDI_FAILURE); 1554 } 1555 1556 1557 /* 1558 * ehci_build_interrupt_lattice: 1559 * 1560 * Construct the interrupt lattice tree using static Endpoint Descriptors 1561 * (QH). This interrupt lattice tree will have total of 32 interrupt QH 1562 * lists and the Host Controller (HC) processes one interrupt QH list in 1563 * every frame. The Host Controller traverses the periodic schedule by 1564 * constructing an array offset reference from the Periodic List Base Address 1565 * register and bits 12 to 3 of Frame Index register. It fetches the element 1566 * and begins traversing the graph of linked schedule data structures. 1567 */ 1568 static void 1569 ehci_build_interrupt_lattice(ehci_state_t *ehcip) 1570 { 1571 ehci_qh_t *list_array = ehcip->ehci_qh_pool_addr; 1572 ushort_t ehci_index[EHCI_NUM_PERIODIC_FRAME_LISTS]; 1573 ehci_periodic_frame_list_t *periodic_frame_list = 1574 ehcip->ehci_periodic_frame_list_tablep; 1575 ushort_t *temp, num_of_nodes; 1576 uintptr_t addr; 1577 int i, j, k; 1578 1579 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1580 "ehci_build_interrupt_lattice:"); 1581 1582 /* 1583 * Reserve the first 63 Endpoint Descriptor (QH) structures 1584 * in the pool as static endpoints & these are required for 1585 * constructing interrupt lattice tree. 1586 */ 1587 for (i = 0; i < EHCI_NUM_STATIC_NODES; i++) { 1588 Set_QH(list_array[i].qh_state, EHCI_QH_STATIC); 1589 Set_QH(list_array[i].qh_status, EHCI_QH_STS_HALTED); 1590 Set_QH(list_array[i].qh_next_qtd, EHCI_QH_NEXT_QTD_PTR_VALID); 1591 Set_QH(list_array[i].qh_alt_next_qtd, 1592 EHCI_QH_ALT_NEXT_QTD_PTR_VALID); 1593 } 1594 1595 /* 1596 * Make sure that last Endpoint on the periodic frame list terminates 1597 * periodic schedule. 1598 */ 1599 Set_QH(list_array[0].qh_link_ptr, EHCI_QH_LINK_PTR_VALID); 1600 1601 /* Build the interrupt lattice tree */ 1602 for (i = 0; i < (EHCI_NUM_STATIC_NODES / 2); i++) { 1603 /* 1604 * The next pointer in the host controller endpoint 1605 * descriptor must contain an iommu address. Calculate 1606 * the offset into the cpu address and add this to the 1607 * starting iommu address. 1608 */ 1609 addr = ehci_qh_cpu_to_iommu(ehcip, (ehci_qh_t *)&list_array[i]); 1610 1611 Set_QH(list_array[2*i + 1].qh_link_ptr, 1612 addr | EHCI_QH_LINK_REF_QH); 1613 Set_QH(list_array[2*i + 2].qh_link_ptr, 1614 addr | EHCI_QH_LINK_REF_QH); 1615 } 1616 1617 /* Build the tree bottom */ 1618 temp = (unsigned short *) 1619 kmem_zalloc(EHCI_NUM_PERIODIC_FRAME_LISTS * 2, KM_SLEEP); 1620 1621 num_of_nodes = 1; 1622 1623 /* 1624 * Initialize the values which are used for setting up head pointers 1625 * for the 32ms scheduling lists which starts from the Periodic Frame 1626 * List. 1627 */ 1628 for (i = 0; i < ehci_log_2(EHCI_NUM_PERIODIC_FRAME_LISTS); i++) { 1629 for (j = 0, k = 0; k < num_of_nodes; k++, j++) { 1630 ehci_index[j++] = temp[k]; 1631 ehci_index[j] = temp[k] + ehci_pow_2(i); 1632 } 1633 1634 num_of_nodes *= 2; 1635 for (k = 0; k < num_of_nodes; k++) 1636 temp[k] = ehci_index[k]; 1637 } 1638 1639 kmem_free((void *)temp, (EHCI_NUM_PERIODIC_FRAME_LISTS * 2)); 1640 1641 /* 1642 * Initialize the interrupt list in the Periodic Frame List Table 1643 * so that it points to the bottom of the tree. 1644 */ 1645 for (i = 0, j = 0; i < ehci_pow_2(TREE_HEIGHT); i++) { 1646 addr = ehci_qh_cpu_to_iommu(ehcip, (ehci_qh_t *) 1647 (&list_array[((EHCI_NUM_STATIC_NODES + 1) / 2) + i - 1])); 1648 1649 ASSERT(addr); 1650 1651 for (k = 0; k < ehci_pow_2(TREE_HEIGHT); k++) { 1652 Set_PFLT(periodic_frame_list-> 1653 ehci_periodic_frame_list_table[ehci_index[j++]], 1654 (uint32_t)(addr | EHCI_QH_LINK_REF_QH)); 1655 } 1656 } 1657 } 1658 1659 1660 /* 1661 * ehci_alloc_hcdi_ops: 1662 * 1663 * The HCDI interfaces or entry points are the software interfaces used by 1664 * the Universal Serial Bus Driver (USBA) to access the services of the 1665 * Host Controller Driver (HCD). During HCD initialization, inform USBA 1666 * about all available HCDI interfaces or entry points. 1667 */ 1668 usba_hcdi_ops_t * 1669 ehci_alloc_hcdi_ops(ehci_state_t *ehcip) 1670 { 1671 usba_hcdi_ops_t *usba_hcdi_ops; 1672 1673 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1674 "ehci_alloc_hcdi_ops:"); 1675 1676 usba_hcdi_ops = usba_alloc_hcdi_ops(); 1677 1678 usba_hcdi_ops->usba_hcdi_ops_version = HCDI_OPS_VERSION; 1679 1680 usba_hcdi_ops->usba_hcdi_pm_support = ehci_hcdi_pm_support; 1681 usba_hcdi_ops->usba_hcdi_pipe_open = ehci_hcdi_pipe_open; 1682 usba_hcdi_ops->usba_hcdi_pipe_close = ehci_hcdi_pipe_close; 1683 1684 usba_hcdi_ops->usba_hcdi_pipe_reset = ehci_hcdi_pipe_reset; 1685 1686 usba_hcdi_ops->usba_hcdi_pipe_ctrl_xfer = ehci_hcdi_pipe_ctrl_xfer; 1687 usba_hcdi_ops->usba_hcdi_pipe_bulk_xfer = ehci_hcdi_pipe_bulk_xfer; 1688 usba_hcdi_ops->usba_hcdi_pipe_intr_xfer = ehci_hcdi_pipe_intr_xfer; 1689 usba_hcdi_ops->usba_hcdi_pipe_isoc_xfer = ehci_hcdi_pipe_isoc_xfer; 1690 1691 usba_hcdi_ops->usba_hcdi_bulk_transfer_size = 1692 ehci_hcdi_bulk_transfer_size; 1693 1694 usba_hcdi_ops->usba_hcdi_pipe_stop_intr_polling = 1695 ehci_hcdi_pipe_stop_intr_polling; 1696 usba_hcdi_ops->usba_hcdi_pipe_stop_isoc_polling = 1697 ehci_hcdi_pipe_stop_isoc_polling; 1698 1699 usba_hcdi_ops->usba_hcdi_get_current_frame_number = 1700 ehci_hcdi_get_current_frame_number; 1701 usba_hcdi_ops->usba_hcdi_get_max_isoc_pkts = 1702 ehci_hcdi_get_max_isoc_pkts; 1703 1704 usba_hcdi_ops->usba_hcdi_console_input_init = 1705 ehci_hcdi_polled_input_init; 1706 usba_hcdi_ops->usba_hcdi_console_input_enter = 1707 ehci_hcdi_polled_input_enter; 1708 usba_hcdi_ops->usba_hcdi_console_read = 1709 ehci_hcdi_polled_read; 1710 usba_hcdi_ops->usba_hcdi_console_input_exit = 1711 ehci_hcdi_polled_input_exit; 1712 usba_hcdi_ops->usba_hcdi_console_input_fini = 1713 ehci_hcdi_polled_input_fini; 1714 return (usba_hcdi_ops); 1715 } 1716 1717 1718 /* 1719 * Host Controller Driver (HCD) deinitialization functions 1720 */ 1721 1722 /* 1723 * ehci_cleanup: 1724 * 1725 * Cleanup on attach failure or detach 1726 */ 1727 int 1728 ehci_cleanup(ehci_state_t *ehcip) 1729 { 1730 ehci_trans_wrapper_t *tw; 1731 ehci_pipe_private_t *pp; 1732 ehci_qtd_t *qtd; 1733 int i, ctrl, rval; 1734 int flags = ehcip->ehci_flags; 1735 1736 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, "ehci_cleanup:"); 1737 1738 if (flags & EHCI_RHREG) { 1739 /* Unload the root hub driver */ 1740 if (ehci_unload_root_hub_driver(ehcip) != USB_SUCCESS) { 1741 1742 return (DDI_FAILURE); 1743 } 1744 } 1745 1746 if (flags & EHCI_USBAREG) { 1747 /* Unregister this HCD instance with USBA */ 1748 usba_hcdi_unregister(ehcip->ehci_dip); 1749 } 1750 1751 if (flags & EHCI_INTR) { 1752 1753 mutex_enter(&ehcip->ehci_int_mutex); 1754 1755 /* Disable all EHCI QH list processing */ 1756 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) & 1757 ~(EHCI_CMD_ASYNC_SCHED_ENABLE | 1758 EHCI_CMD_PERIODIC_SCHED_ENABLE))); 1759 1760 /* Disable all EHCI interrupts */ 1761 Set_OpReg(ehci_interrupt, 0); 1762 1763 /* wait for the next SOF */ 1764 (void) ehci_wait_for_sof(ehcip); 1765 1766 /* Route all Root hub ports to Classic host controller */ 1767 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_CLASSIC); 1768 1769 /* Stop the EHCI host controller */ 1770 Set_OpReg(ehci_command, 1771 Get_OpReg(ehci_command) & ~EHCI_CMD_HOST_CTRL_RUN); 1772 1773 mutex_exit(&ehcip->ehci_int_mutex); 1774 1775 /* Wait for sometime */ 1776 delay(drv_usectohz(EHCI_TIMEWAIT)); 1777 1778 ehci_rem_intrs(ehcip); 1779 } 1780 1781 /* Unmap the EHCI registers */ 1782 if (ehcip->ehci_caps_handle) { 1783 ddi_regs_map_free(&ehcip->ehci_caps_handle); 1784 } 1785 1786 if (ehcip->ehci_config_handle) { 1787 pci_config_teardown(&ehcip->ehci_config_handle); 1788 } 1789 1790 /* Free all the buffers */ 1791 if (ehcip->ehci_qtd_pool_addr && ehcip->ehci_qtd_pool_mem_handle) { 1792 for (i = 0; i < ehci_qtd_pool_size; i ++) { 1793 qtd = &ehcip->ehci_qtd_pool_addr[i]; 1794 ctrl = Get_QTD(ehcip-> 1795 ehci_qtd_pool_addr[i].qtd_state); 1796 1797 if ((ctrl != EHCI_QTD_FREE) && 1798 (ctrl != EHCI_QTD_DUMMY) && 1799 (qtd->qtd_trans_wrapper)) { 1800 1801 mutex_enter(&ehcip->ehci_int_mutex); 1802 1803 tw = (ehci_trans_wrapper_t *) 1804 EHCI_LOOKUP_ID((uint32_t) 1805 Get_QTD(qtd->qtd_trans_wrapper)); 1806 1807 /* Obtain the pipe private structure */ 1808 pp = tw->tw_pipe_private; 1809 1810 /* Stop the the transfer timer */ 1811 ehci_stop_xfer_timer(ehcip, tw, 1812 EHCI_REMOVE_XFER_ALWAYS); 1813 1814 ehci_deallocate_tw(ehcip, pp, tw); 1815 1816 mutex_exit(&ehcip->ehci_int_mutex); 1817 } 1818 } 1819 1820 /* 1821 * If EHCI_QTD_POOL_BOUND flag is set, then unbind 1822 * the handle for QTD pools. 1823 */ 1824 if ((ehcip->ehci_dma_addr_bind_flag & 1825 EHCI_QTD_POOL_BOUND) == EHCI_QTD_POOL_BOUND) { 1826 1827 rval = ddi_dma_unbind_handle( 1828 ehcip->ehci_qtd_pool_dma_handle); 1829 1830 ASSERT(rval == DDI_SUCCESS); 1831 } 1832 ddi_dma_mem_free(&ehcip->ehci_qtd_pool_mem_handle); 1833 } 1834 1835 /* Free the QTD pool */ 1836 if (ehcip->ehci_qtd_pool_dma_handle) { 1837 ddi_dma_free_handle(&ehcip->ehci_qtd_pool_dma_handle); 1838 } 1839 1840 if (ehcip->ehci_qh_pool_addr && ehcip->ehci_qh_pool_mem_handle) { 1841 /* 1842 * If EHCI_QH_POOL_BOUND flag is set, then unbind 1843 * the handle for QH pools. 1844 */ 1845 if ((ehcip->ehci_dma_addr_bind_flag & 1846 EHCI_QH_POOL_BOUND) == EHCI_QH_POOL_BOUND) { 1847 1848 rval = ddi_dma_unbind_handle( 1849 ehcip->ehci_qh_pool_dma_handle); 1850 1851 ASSERT(rval == DDI_SUCCESS); 1852 } 1853 1854 ddi_dma_mem_free(&ehcip->ehci_qh_pool_mem_handle); 1855 } 1856 1857 /* Free the QH pool */ 1858 if (ehcip->ehci_qh_pool_dma_handle) { 1859 ddi_dma_free_handle(&ehcip->ehci_qh_pool_dma_handle); 1860 } 1861 1862 /* Free the Periodic frame list table (PFLT) area */ 1863 if (ehcip->ehci_periodic_frame_list_tablep && 1864 ehcip->ehci_pflt_mem_handle) { 1865 /* 1866 * If EHCI_PFLT_DMA_BOUND flag is set, then unbind 1867 * the handle for PFLT. 1868 */ 1869 if ((ehcip->ehci_dma_addr_bind_flag & 1870 EHCI_PFLT_DMA_BOUND) == EHCI_PFLT_DMA_BOUND) { 1871 1872 rval = ddi_dma_unbind_handle( 1873 ehcip->ehci_pflt_dma_handle); 1874 1875 ASSERT(rval == DDI_SUCCESS); 1876 } 1877 1878 ddi_dma_mem_free(&ehcip->ehci_pflt_mem_handle); 1879 } 1880 1881 (void) ehci_isoc_cleanup(ehcip); 1882 1883 if (ehcip->ehci_pflt_dma_handle) { 1884 ddi_dma_free_handle(&ehcip->ehci_pflt_dma_handle); 1885 } 1886 1887 if (flags & EHCI_INTR) { 1888 /* Destroy the mutex */ 1889 mutex_destroy(&ehcip->ehci_int_mutex); 1890 1891 /* Destroy the async schedule advance condition variable */ 1892 cv_destroy(&ehcip->ehci_async_schedule_advance_cv); 1893 } 1894 1895 /* clean up kstat structs */ 1896 ehci_destroy_stats(ehcip); 1897 1898 /* Free ehci hcdi ops */ 1899 if (ehcip->ehci_hcdi_ops) { 1900 usba_free_hcdi_ops(ehcip->ehci_hcdi_ops); 1901 } 1902 1903 if (flags & EHCI_ZALLOC) { 1904 1905 usb_free_log_hdl(ehcip->ehci_log_hdl); 1906 1907 /* Remove all properties that might have been created */ 1908 ddi_prop_remove_all(ehcip->ehci_dip); 1909 1910 /* Free the soft state */ 1911 ddi_soft_state_free(ehci_statep, 1912 ddi_get_instance(ehcip->ehci_dip)); 1913 } 1914 1915 return (DDI_SUCCESS); 1916 } 1917 1918 1919 /* 1920 * ehci_rem_intrs: 1921 * 1922 * Unregister FIXED or MSI interrupts 1923 */ 1924 static void 1925 ehci_rem_intrs(ehci_state_t *ehcip) 1926 { 1927 int i; 1928 1929 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1930 "ehci_rem_intrs: interrupt type 0x%x", ehcip->ehci_intr_type); 1931 1932 /* Disable all interrupts */ 1933 if (ehcip->ehci_intr_cap & DDI_INTR_FLAG_BLOCK) { 1934 (void) ddi_intr_block_disable(ehcip->ehci_htable, 1935 ehcip->ehci_intr_cnt); 1936 } else { 1937 for (i = 0; i < ehcip->ehci_intr_cnt; i++) { 1938 (void) ddi_intr_disable(ehcip->ehci_htable[i]); 1939 } 1940 } 1941 1942 /* Call ddi_intr_remove_handler() */ 1943 for (i = 0; i < ehcip->ehci_intr_cnt; i++) { 1944 (void) ddi_intr_remove_handler(ehcip->ehci_htable[i]); 1945 (void) ddi_intr_free(ehcip->ehci_htable[i]); 1946 } 1947 1948 kmem_free(ehcip->ehci_htable, 1949 ehcip->ehci_intr_cnt * sizeof (ddi_intr_handle_t)); 1950 } 1951 1952 1953 /* 1954 * ehci_cpr_suspend 1955 */ 1956 int 1957 ehci_cpr_suspend(ehci_state_t *ehcip) 1958 { 1959 int i; 1960 1961 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1962 "ehci_cpr_suspend:"); 1963 1964 /* Call into the root hub and suspend it */ 1965 if (usba_hubdi_detach(ehcip->ehci_dip, DDI_SUSPEND) != DDI_SUCCESS) { 1966 1967 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1968 "ehci_cpr_suspend: root hub fails to suspend"); 1969 1970 return (DDI_FAILURE); 1971 } 1972 1973 /* Only root hub's intr pipe should be open at this time */ 1974 mutex_enter(&ehcip->ehci_int_mutex); 1975 1976 ASSERT(ehcip->ehci_open_pipe_count == 0); 1977 1978 /* Just wait till all resources are reclaimed */ 1979 i = 0; 1980 while ((ehcip->ehci_reclaim_list != NULL) && (i++ < 3)) { 1981 ehci_handle_endpoint_reclaimation(ehcip); 1982 (void) ehci_wait_for_sof(ehcip); 1983 } 1984 ASSERT(ehcip->ehci_reclaim_list == NULL); 1985 1986 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1987 "ehci_cpr_suspend: Disable HC QH list processing"); 1988 1989 /* Disable all EHCI QH list processing */ 1990 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) & 1991 ~(EHCI_CMD_ASYNC_SCHED_ENABLE | EHCI_CMD_PERIODIC_SCHED_ENABLE))); 1992 1993 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1994 "ehci_cpr_suspend: Disable HC interrupts"); 1995 1996 /* Disable all EHCI interrupts */ 1997 Set_OpReg(ehci_interrupt, 0); 1998 1999 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 2000 "ehci_cpr_suspend: Wait for the next SOF"); 2001 2002 /* Wait for the next SOF */ 2003 if (ehci_wait_for_sof(ehcip) != USB_SUCCESS) { 2004 2005 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 2006 "ehci_cpr_suspend: ehci host controller suspend failed"); 2007 2008 mutex_exit(&ehcip->ehci_int_mutex); 2009 return (DDI_FAILURE); 2010 } 2011 2012 /* 2013 * Stop the ehci host controller 2014 * if usb keyboard is not connected. 2015 */ 2016 if (ehcip->ehci_polled_kbd_count == 0 || force_ehci_off != 0) { 2017 Set_OpReg(ehci_command, 2018 Get_OpReg(ehci_command) & ~EHCI_CMD_HOST_CTRL_RUN); 2019 } 2020 2021 /* Set host controller soft state to suspend */ 2022 ehcip->ehci_hc_soft_state = EHCI_CTLR_SUSPEND_STATE; 2023 2024 mutex_exit(&ehcip->ehci_int_mutex); 2025 2026 return (DDI_SUCCESS); 2027 } 2028 2029 2030 /* 2031 * ehci_cpr_resume 2032 */ 2033 int 2034 ehci_cpr_resume(ehci_state_t *ehcip) 2035 { 2036 mutex_enter(&ehcip->ehci_int_mutex); 2037 2038 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 2039 "ehci_cpr_resume: Restart the controller"); 2040 2041 /* Cleanup ehci specific information across cpr */ 2042 ehci_cpr_cleanup(ehcip); 2043 2044 /* Restart the controller */ 2045 if (ehci_init_ctlr(ehcip, EHCI_NORMAL_INITIALIZATION) != DDI_SUCCESS) { 2046 2047 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 2048 "ehci_cpr_resume: ehci host controller resume failed "); 2049 2050 mutex_exit(&ehcip->ehci_int_mutex); 2051 2052 return (DDI_FAILURE); 2053 } 2054 2055 mutex_exit(&ehcip->ehci_int_mutex); 2056 2057 /* Now resume the root hub */ 2058 if (usba_hubdi_attach(ehcip->ehci_dip, DDI_RESUME) != DDI_SUCCESS) { 2059 2060 return (DDI_FAILURE); 2061 } 2062 2063 return (DDI_SUCCESS); 2064 } 2065 2066 2067 /* 2068 * Bandwidth Allocation functions 2069 */ 2070 2071 /* 2072 * ehci_allocate_bandwidth: 2073 * 2074 * Figure out whether or not this interval may be supported. Return the index 2075 * into the lattice if it can be supported. Return allocation failure if it 2076 * can not be supported. 2077 */ 2078 int 2079 ehci_allocate_bandwidth( 2080 ehci_state_t *ehcip, 2081 usba_pipe_handle_data_t *ph, 2082 uint_t *pnode, 2083 uchar_t *smask, 2084 uchar_t *cmask) 2085 { 2086 int error = USB_SUCCESS; 2087 2088 /* This routine is protected by the ehci_int_mutex */ 2089 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2090 2091 /* Reset the pnode to the last checked pnode */ 2092 *pnode = 0; 2093 2094 /* Allocate high speed bandwidth */ 2095 if ((error = ehci_allocate_high_speed_bandwidth(ehcip, 2096 ph, pnode, smask, cmask)) != USB_SUCCESS) { 2097 2098 return (error); 2099 } 2100 2101 /* 2102 * For low/full speed usb devices, allocate classic TT bandwidth 2103 * in additional to high speed bandwidth. 2104 */ 2105 if (ph->p_usba_device->usb_port_status != USBA_HIGH_SPEED_DEV) { 2106 2107 /* Allocate classic TT bandwidth */ 2108 if ((error = ehci_allocate_classic_tt_bandwidth( 2109 ehcip, ph, *pnode)) != USB_SUCCESS) { 2110 2111 /* Deallocate high speed bandwidth */ 2112 ehci_deallocate_high_speed_bandwidth( 2113 ehcip, ph, *pnode, *smask, *cmask); 2114 } 2115 } 2116 2117 return (error); 2118 } 2119 2120 2121 /* 2122 * ehci_allocate_high_speed_bandwidth: 2123 * 2124 * Allocate high speed bandwidth for the low/full/high speed interrupt and 2125 * isochronous endpoints. 2126 */ 2127 static int 2128 ehci_allocate_high_speed_bandwidth( 2129 ehci_state_t *ehcip, 2130 usba_pipe_handle_data_t *ph, 2131 uint_t *pnode, 2132 uchar_t *smask, 2133 uchar_t *cmask) 2134 { 2135 uint_t sbandwidth, cbandwidth; 2136 int interval; 2137 usb_ep_descr_t *endpoint = &ph->p_ep; 2138 usba_device_t *child_ud; 2139 usb_port_status_t port_status; 2140 int error; 2141 2142 /* This routine is protected by the ehci_int_mutex */ 2143 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2144 2145 /* Get child's usba device structure */ 2146 child_ud = ph->p_usba_device; 2147 2148 mutex_enter(&child_ud->usb_mutex); 2149 2150 /* Get the current usb device's port status */ 2151 port_status = ph->p_usba_device->usb_port_status; 2152 2153 mutex_exit(&child_ud->usb_mutex); 2154 2155 /* 2156 * Calculate the length in bytes of a transaction on this 2157 * periodic endpoint. Return failure if maximum packet is 2158 * zero. 2159 */ 2160 error = ehci_compute_high_speed_bandwidth(ehcip, endpoint, 2161 port_status, &sbandwidth, &cbandwidth); 2162 if (error != USB_SUCCESS) { 2163 2164 return (error); 2165 } 2166 2167 /* 2168 * Adjust polling interval to be a power of 2. 2169 * If this interval can't be supported, return 2170 * allocation failure. 2171 */ 2172 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2173 if (interval == USB_FAILURE) { 2174 2175 return (USB_FAILURE); 2176 } 2177 2178 if (port_status == USBA_HIGH_SPEED_DEV) { 2179 /* Allocate bandwidth for high speed devices */ 2180 if ((endpoint->bmAttributes & USB_EP_ATTR_MASK) == 2181 USB_EP_ATTR_ISOCH) { 2182 error = USB_SUCCESS; 2183 } else { 2184 2185 error = ehci_find_bestfit_hs_mask(ehcip, smask, pnode, 2186 endpoint, sbandwidth, interval); 2187 } 2188 2189 *cmask = 0x00; 2190 2191 } else { 2192 if ((endpoint->bmAttributes & USB_EP_ATTR_MASK) == 2193 USB_EP_ATTR_INTR) { 2194 2195 /* Allocate bandwidth for low speed interrupt */ 2196 error = ehci_find_bestfit_ls_intr_mask(ehcip, 2197 smask, cmask, pnode, sbandwidth, cbandwidth, 2198 interval); 2199 } else { 2200 if ((endpoint->bEndpointAddress & 2201 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2202 2203 /* Allocate bandwidth for sitd in */ 2204 error = ehci_find_bestfit_sitd_in_mask(ehcip, 2205 smask, cmask, pnode, sbandwidth, cbandwidth, 2206 interval); 2207 } else { 2208 2209 /* Allocate bandwidth for sitd out */ 2210 error = ehci_find_bestfit_sitd_out_mask(ehcip, 2211 smask, pnode, sbandwidth, interval); 2212 *cmask = 0x00; 2213 } 2214 } 2215 } 2216 2217 if (error != USB_SUCCESS) { 2218 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2219 "ehci_allocate_high_speed_bandwidth: Reached maximum " 2220 "bandwidth value and cannot allocate bandwidth for a " 2221 "given high-speed periodic endpoint"); 2222 2223 return (USB_NO_BANDWIDTH); 2224 } 2225 2226 return (error); 2227 } 2228 2229 2230 /* 2231 * ehci_allocate_classic_tt_speed_bandwidth: 2232 * 2233 * Allocate classic TT bandwidth for the low/full speed interrupt and 2234 * isochronous endpoints. 2235 */ 2236 static int 2237 ehci_allocate_classic_tt_bandwidth( 2238 ehci_state_t *ehcip, 2239 usba_pipe_handle_data_t *ph, 2240 uint_t pnode) 2241 { 2242 uint_t bandwidth, min; 2243 uint_t height, leftmost, list; 2244 usb_ep_descr_t *endpoint = &ph->p_ep; 2245 usba_device_t *child_ud, *parent_ud; 2246 usb_port_status_t port_status; 2247 int i, interval; 2248 2249 /* This routine is protected by the ehci_int_mutex */ 2250 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2251 2252 /* Get child's usba device structure */ 2253 child_ud = ph->p_usba_device; 2254 2255 mutex_enter(&child_ud->usb_mutex); 2256 2257 /* Get the current usb device's port status */ 2258 port_status = child_ud->usb_port_status; 2259 2260 /* Get the parent high speed hub's usba device structure */ 2261 parent_ud = child_ud->usb_hs_hub_usba_dev; 2262 2263 mutex_exit(&child_ud->usb_mutex); 2264 2265 USB_DPRINTF_L3(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2266 "ehci_allocate_classic_tt_bandwidth: " 2267 "child_ud 0x%p parent_ud 0x%p", child_ud, parent_ud); 2268 2269 /* 2270 * Calculate the length in bytes of a transaction on this 2271 * periodic endpoint. Return failure if maximum packet is 2272 * zero. 2273 */ 2274 if (ehci_compute_classic_bandwidth(endpoint, 2275 port_status, &bandwidth) != USB_SUCCESS) { 2276 2277 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2278 "ehci_allocate_classic_tt_bandwidth: Periodic endpoint " 2279 "with zero endpoint maximum packet size is not supported"); 2280 2281 return (USB_NOT_SUPPORTED); 2282 } 2283 2284 USB_DPRINTF_L3(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2285 "ehci_allocate_classic_tt_bandwidth: bandwidth %d", bandwidth); 2286 2287 mutex_enter(&parent_ud->usb_mutex); 2288 2289 /* 2290 * If the length in bytes plus the allocated bandwidth exceeds 2291 * the maximum, return bandwidth allocation failure. 2292 */ 2293 if ((parent_ud->usb_hs_hub_min_bandwidth + bandwidth) > 2294 FS_PERIODIC_BANDWIDTH) { 2295 2296 mutex_exit(&parent_ud->usb_mutex); 2297 2298 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2299 "ehci_allocate_classic_tt_bandwidth: Reached maximum " 2300 "bandwidth value and cannot allocate bandwidth for a " 2301 "given low/full speed periodic endpoint"); 2302 2303 return (USB_NO_BANDWIDTH); 2304 } 2305 2306 mutex_exit(&parent_ud->usb_mutex); 2307 2308 /* Adjust polling interval to be a power of 2 */ 2309 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2310 2311 /* Find the height in the tree */ 2312 height = ehci_lattice_height(interval); 2313 2314 /* Find the leftmost leaf in the subtree specified by the node. */ 2315 leftmost = ehci_leftmost_leaf(pnode, height); 2316 2317 mutex_enter(&parent_ud->usb_mutex); 2318 2319 for (i = 0; i < (EHCI_NUM_INTR_QH_LISTS/interval); i++) { 2320 list = ehci_index[leftmost + i]; 2321 2322 if ((parent_ud->usb_hs_hub_bandwidth[list] + 2323 bandwidth) > FS_PERIODIC_BANDWIDTH) { 2324 2325 mutex_exit(&parent_ud->usb_mutex); 2326 2327 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2328 "ehci_allocate_classic_tt_bandwidth: Reached " 2329 "maximum bandwidth value and cannot allocate " 2330 "bandwidth for low/full periodic endpoint"); 2331 2332 return (USB_NO_BANDWIDTH); 2333 } 2334 } 2335 2336 /* 2337 * All the leaves for this node must be updated with the bandwidth. 2338 */ 2339 for (i = 0; i < (EHCI_NUM_INTR_QH_LISTS/interval); i++) { 2340 list = ehci_index[leftmost + i]; 2341 parent_ud->usb_hs_hub_bandwidth[list] += bandwidth; 2342 } 2343 2344 /* Find the leaf with the smallest allocated bandwidth */ 2345 min = parent_ud->usb_hs_hub_bandwidth[0]; 2346 2347 for (i = 1; i < EHCI_NUM_INTR_QH_LISTS; i++) { 2348 if (parent_ud->usb_hs_hub_bandwidth[i] < min) { 2349 min = parent_ud->usb_hs_hub_bandwidth[i]; 2350 } 2351 } 2352 2353 /* Save the minimum for later use */ 2354 parent_ud->usb_hs_hub_min_bandwidth = min; 2355 2356 mutex_exit(&parent_ud->usb_mutex); 2357 2358 return (USB_SUCCESS); 2359 } 2360 2361 2362 /* 2363 * ehci_deallocate_bandwidth: 2364 * 2365 * Deallocate bandwidth for the given node in the lattice and the length 2366 * of transfer. 2367 */ 2368 void 2369 ehci_deallocate_bandwidth( 2370 ehci_state_t *ehcip, 2371 usba_pipe_handle_data_t *ph, 2372 uint_t pnode, 2373 uchar_t smask, 2374 uchar_t cmask) 2375 { 2376 /* This routine is protected by the ehci_int_mutex */ 2377 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2378 2379 ehci_deallocate_high_speed_bandwidth(ehcip, ph, pnode, smask, cmask); 2380 2381 /* 2382 * For low/full speed usb devices, deallocate classic TT bandwidth 2383 * in additional to high speed bandwidth. 2384 */ 2385 if (ph->p_usba_device->usb_port_status != USBA_HIGH_SPEED_DEV) { 2386 2387 /* Deallocate classic TT bandwidth */ 2388 ehci_deallocate_classic_tt_bandwidth(ehcip, ph, pnode); 2389 } 2390 } 2391 2392 2393 /* 2394 * ehci_deallocate_high_speed_bandwidth: 2395 * 2396 * Deallocate high speed bandwidth of a interrupt or isochronous endpoint. 2397 */ 2398 static void 2399 ehci_deallocate_high_speed_bandwidth( 2400 ehci_state_t *ehcip, 2401 usba_pipe_handle_data_t *ph, 2402 uint_t pnode, 2403 uchar_t smask, 2404 uchar_t cmask) 2405 { 2406 uint_t height, leftmost; 2407 uint_t list_count; 2408 uint_t sbandwidth, cbandwidth; 2409 int interval; 2410 usb_ep_descr_t *endpoint = &ph->p_ep; 2411 usba_device_t *child_ud; 2412 usb_port_status_t port_status; 2413 2414 /* This routine is protected by the ehci_int_mutex */ 2415 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2416 2417 /* Get child's usba device structure */ 2418 child_ud = ph->p_usba_device; 2419 2420 mutex_enter(&child_ud->usb_mutex); 2421 2422 /* Get the current usb device's port status */ 2423 port_status = ph->p_usba_device->usb_port_status; 2424 2425 mutex_exit(&child_ud->usb_mutex); 2426 2427 (void) ehci_compute_high_speed_bandwidth(ehcip, endpoint, 2428 port_status, &sbandwidth, &cbandwidth); 2429 2430 /* Adjust polling interval to be a power of 2 */ 2431 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2432 2433 /* Find the height in the tree */ 2434 height = ehci_lattice_height(interval); 2435 2436 /* 2437 * Find the leftmost leaf in the subtree specified by the node 2438 */ 2439 leftmost = ehci_leftmost_leaf(pnode, height); 2440 2441 list_count = EHCI_NUM_INTR_QH_LISTS/interval; 2442 2443 /* Delete the bandwidth from the appropriate lists */ 2444 if (port_status == USBA_HIGH_SPEED_DEV) { 2445 2446 ehci_update_bw_availability(ehcip, -sbandwidth, 2447 leftmost, list_count, smask); 2448 } else { 2449 if ((endpoint->bmAttributes & USB_EP_ATTR_MASK) == 2450 USB_EP_ATTR_INTR) { 2451 2452 ehci_update_bw_availability(ehcip, -sbandwidth, 2453 leftmost, list_count, smask); 2454 ehci_update_bw_availability(ehcip, -cbandwidth, 2455 leftmost, list_count, cmask); 2456 } else { 2457 if ((endpoint->bEndpointAddress & 2458 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2459 2460 ehci_update_bw_availability(ehcip, -sbandwidth, 2461 leftmost, list_count, smask); 2462 ehci_update_bw_availability(ehcip, 2463 -MAX_UFRAME_SITD_XFER, leftmost, 2464 list_count, cmask); 2465 } else { 2466 2467 ehci_update_bw_availability(ehcip, 2468 -MAX_UFRAME_SITD_XFER, leftmost, 2469 list_count, smask); 2470 } 2471 } 2472 } 2473 } 2474 2475 /* 2476 * ehci_deallocate_classic_tt_bandwidth: 2477 * 2478 * Deallocate high speed bandwidth of a interrupt or isochronous endpoint. 2479 */ 2480 static void 2481 ehci_deallocate_classic_tt_bandwidth( 2482 ehci_state_t *ehcip, 2483 usba_pipe_handle_data_t *ph, 2484 uint_t pnode) 2485 { 2486 uint_t bandwidth, height, leftmost, list, min; 2487 int i, interval; 2488 usb_ep_descr_t *endpoint = &ph->p_ep; 2489 usba_device_t *child_ud, *parent_ud; 2490 usb_port_status_t port_status; 2491 2492 /* This routine is protected by the ehci_int_mutex */ 2493 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2494 2495 /* Get child's usba device structure */ 2496 child_ud = ph->p_usba_device; 2497 2498 mutex_enter(&child_ud->usb_mutex); 2499 2500 /* Get the current usb device's port status */ 2501 port_status = child_ud->usb_port_status; 2502 2503 /* Get the parent high speed hub's usba device structure */ 2504 parent_ud = child_ud->usb_hs_hub_usba_dev; 2505 2506 mutex_exit(&child_ud->usb_mutex); 2507 2508 /* Obtain the bandwidth */ 2509 (void) ehci_compute_classic_bandwidth(endpoint, 2510 port_status, &bandwidth); 2511 2512 /* Adjust polling interval to be a power of 2 */ 2513 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2514 2515 /* Find the height in the tree */ 2516 height = ehci_lattice_height(interval); 2517 2518 /* Find the leftmost leaf in the subtree specified by the node */ 2519 leftmost = ehci_leftmost_leaf(pnode, height); 2520 2521 mutex_enter(&parent_ud->usb_mutex); 2522 2523 /* Delete the bandwidth from the appropriate lists */ 2524 for (i = 0; i < (EHCI_NUM_INTR_QH_LISTS/interval); i++) { 2525 list = ehci_index[leftmost + i]; 2526 parent_ud->usb_hs_hub_bandwidth[list] -= bandwidth; 2527 } 2528 2529 /* Find the leaf with the smallest allocated bandwidth */ 2530 min = parent_ud->usb_hs_hub_bandwidth[0]; 2531 2532 for (i = 1; i < EHCI_NUM_INTR_QH_LISTS; i++) { 2533 if (parent_ud->usb_hs_hub_bandwidth[i] < min) { 2534 min = parent_ud->usb_hs_hub_bandwidth[i]; 2535 } 2536 } 2537 2538 /* Save the minimum for later use */ 2539 parent_ud->usb_hs_hub_min_bandwidth = min; 2540 2541 mutex_exit(&parent_ud->usb_mutex); 2542 } 2543 2544 2545 /* 2546 * ehci_compute_high_speed_bandwidth: 2547 * 2548 * Given a periodic endpoint (interrupt or isochronous) determine the total 2549 * bandwidth for one transaction. The EHCI host controller traverses the 2550 * endpoint descriptor lists on a first-come-first-serve basis. When the HC 2551 * services an endpoint, only a single transaction attempt is made. The HC 2552 * moves to the next Endpoint Descriptor after the first transaction attempt 2553 * rather than finishing the entire Transfer Descriptor. Therefore, when a 2554 * Transfer Descriptor is inserted into the lattice, we will only count the 2555 * number of bytes for one transaction. 2556 * 2557 * The following are the formulas used for calculating bandwidth in terms 2558 * bytes and it is for the single USB high speed transaction. The protocol 2559 * overheads will be different for each of type of USB transfer & all these 2560 * formulas & protocol overheads are derived from the 5.11.3 section of the 2561 * USB 2.0 Specification. 2562 * 2563 * High-Speed: 2564 * Protocol overhead + ((MaxPktSz * 7)/6) + Host_Delay 2565 * 2566 * Split Transaction: (Low/Full speed devices connected behind usb2.0 hub) 2567 * 2568 * Protocol overhead + Split transaction overhead + 2569 * ((MaxPktSz * 7)/6) + Host_Delay; 2570 */ 2571 /* ARGSUSED */ 2572 static int 2573 ehci_compute_high_speed_bandwidth( 2574 ehci_state_t *ehcip, 2575 usb_ep_descr_t *endpoint, 2576 usb_port_status_t port_status, 2577 uint_t *sbandwidth, 2578 uint_t *cbandwidth) 2579 { 2580 ushort_t maxpacketsize = endpoint->wMaxPacketSize; 2581 2582 /* Return failure if endpoint maximum packet is zero */ 2583 if (maxpacketsize == 0) { 2584 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2585 "ehci_allocate_high_speed_bandwidth: Periodic endpoint " 2586 "with zero endpoint maximum packet size is not supported"); 2587 2588 return (USB_NOT_SUPPORTED); 2589 } 2590 2591 /* Add bit-stuffing overhead */ 2592 maxpacketsize = (ushort_t)((maxpacketsize * 7) / 6); 2593 2594 /* Add Host Controller specific delay to required bandwidth */ 2595 *sbandwidth = EHCI_HOST_CONTROLLER_DELAY; 2596 2597 /* Add xfer specific protocol overheads */ 2598 if ((endpoint->bmAttributes & 2599 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) { 2600 /* High speed interrupt transaction */ 2601 *sbandwidth += HS_NON_ISOC_PROTO_OVERHEAD; 2602 } else { 2603 /* Isochronous transaction */ 2604 *sbandwidth += HS_ISOC_PROTO_OVERHEAD; 2605 } 2606 2607 /* 2608 * For low/full speed devices, add split transaction specific 2609 * overheads. 2610 */ 2611 if (port_status != USBA_HIGH_SPEED_DEV) { 2612 /* 2613 * Add start and complete split transaction 2614 * tokens overheads. 2615 */ 2616 *cbandwidth = *sbandwidth + COMPLETE_SPLIT_OVERHEAD; 2617 *sbandwidth += START_SPLIT_OVERHEAD; 2618 2619 /* Add data overhead depending on data direction */ 2620 if ((endpoint->bEndpointAddress & 2621 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2622 *cbandwidth += maxpacketsize; 2623 } else { 2624 if ((endpoint->bmAttributes & 2625 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH) { 2626 /* There is no compete splits for out */ 2627 *cbandwidth = 0; 2628 } 2629 *sbandwidth += maxpacketsize; 2630 } 2631 } else { 2632 uint_t xactions; 2633 2634 /* Get the max transactions per microframe */ 2635 xactions = ((maxpacketsize & USB_EP_MAX_XACTS_MASK) >> 2636 USB_EP_MAX_XACTS_SHIFT) + 1; 2637 2638 /* High speed transaction */ 2639 *sbandwidth += maxpacketsize; 2640 2641 /* Calculate bandwidth per micro-frame */ 2642 *sbandwidth *= xactions; 2643 2644 *cbandwidth = 0; 2645 } 2646 2647 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2648 "ehci_allocate_high_speed_bandwidth: " 2649 "Start split bandwidth %d Complete split bandwidth %d", 2650 *sbandwidth, *cbandwidth); 2651 2652 return (USB_SUCCESS); 2653 } 2654 2655 2656 /* 2657 * ehci_compute_classic_bandwidth: 2658 * 2659 * Given a periodic endpoint (interrupt or isochronous) determine the total 2660 * bandwidth for one transaction. The EHCI host controller traverses the 2661 * endpoint descriptor lists on a first-come-first-serve basis. When the HC 2662 * services an endpoint, only a single transaction attempt is made. The HC 2663 * moves to the next Endpoint Descriptor after the first transaction attempt 2664 * rather than finishing the entire Transfer Descriptor. Therefore, when a 2665 * Transfer Descriptor is inserted into the lattice, we will only count the 2666 * number of bytes for one transaction. 2667 * 2668 * The following are the formulas used for calculating bandwidth in terms 2669 * bytes and it is for the single USB high speed transaction. The protocol 2670 * overheads will be different for each of type of USB transfer & all these 2671 * formulas & protocol overheads are derived from the 5.11.3 section of the 2672 * USB 2.0 Specification. 2673 * 2674 * Low-Speed: 2675 * Protocol overhead + Hub LS overhead + 2676 * (Low Speed clock * ((MaxPktSz * 7)/6)) + TT_Delay 2677 * 2678 * Full-Speed: 2679 * Protocol overhead + ((MaxPktSz * 7)/6) + TT_Delay 2680 */ 2681 /* ARGSUSED */ 2682 static int 2683 ehci_compute_classic_bandwidth( 2684 usb_ep_descr_t *endpoint, 2685 usb_port_status_t port_status, 2686 uint_t *bandwidth) 2687 { 2688 ushort_t maxpacketsize = endpoint->wMaxPacketSize; 2689 2690 /* 2691 * If endpoint maximum packet is zero, then return immediately. 2692 */ 2693 if (maxpacketsize == 0) { 2694 2695 return (USB_NOT_SUPPORTED); 2696 } 2697 2698 /* Add TT delay to required bandwidth */ 2699 *bandwidth = TT_DELAY; 2700 2701 /* Add bit-stuffing overhead */ 2702 maxpacketsize = (ushort_t)((maxpacketsize * 7) / 6); 2703 2704 switch (port_status) { 2705 case USBA_LOW_SPEED_DEV: 2706 /* Low speed interrupt transaction */ 2707 *bandwidth += (LOW_SPEED_PROTO_OVERHEAD + 2708 HUB_LOW_SPEED_PROTO_OVERHEAD + 2709 (LOW_SPEED_CLOCK * maxpacketsize)); 2710 break; 2711 case USBA_FULL_SPEED_DEV: 2712 /* Full speed transaction */ 2713 *bandwidth += maxpacketsize; 2714 2715 /* Add xfer specific protocol overheads */ 2716 if ((endpoint->bmAttributes & 2717 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) { 2718 /* Full speed interrupt transaction */ 2719 *bandwidth += FS_NON_ISOC_PROTO_OVERHEAD; 2720 } else { 2721 /* Isochronous and input transaction */ 2722 if ((endpoint->bEndpointAddress & 2723 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2724 *bandwidth += FS_ISOC_INPUT_PROTO_OVERHEAD; 2725 } else { 2726 /* Isochronous and output transaction */ 2727 *bandwidth += FS_ISOC_OUTPUT_PROTO_OVERHEAD; 2728 } 2729 } 2730 break; 2731 } 2732 2733 return (USB_SUCCESS); 2734 } 2735 2736 2737 /* 2738 * ehci_adjust_polling_interval: 2739 * 2740 * Adjust bandwidth according usb device speed. 2741 */ 2742 /* ARGSUSED */ 2743 int 2744 ehci_adjust_polling_interval( 2745 ehci_state_t *ehcip, 2746 usb_ep_descr_t *endpoint, 2747 usb_port_status_t port_status) 2748 { 2749 uint_t interval; 2750 int i = 0; 2751 2752 /* Get the polling interval */ 2753 interval = endpoint->bInterval; 2754 2755 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2756 "ehci_adjust_polling_interval: Polling interval 0x%x", interval); 2757 2758 /* 2759 * According USB 2.0 Specifications, a high-speed endpoint's 2760 * polling intervals are specified interms of 125us or micro 2761 * frame, where as full/low endpoint's polling intervals are 2762 * specified in milliseconds. 2763 * 2764 * A high speed interrupt/isochronous endpoints can specify 2765 * desired polling interval between 1 to 16 micro-frames, 2766 * where as full/low endpoints can specify between 1 to 255 2767 * milliseconds. 2768 */ 2769 switch (port_status) { 2770 case USBA_LOW_SPEED_DEV: 2771 /* 2772 * Low speed endpoints are limited to specifying 2773 * only 8ms to 255ms in this driver. If a device 2774 * reports a polling interval that is less than 8ms, 2775 * it will use 8 ms instead. 2776 */ 2777 if (interval < LS_MIN_POLL_INTERVAL) { 2778 2779 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2780 "Low speed endpoint's poll interval of %d ms " 2781 "is below threshold. Rounding up to %d ms", 2782 interval, LS_MIN_POLL_INTERVAL); 2783 2784 interval = LS_MIN_POLL_INTERVAL; 2785 } 2786 2787 /* 2788 * Return an error if the polling interval is greater 2789 * than 255ms. 2790 */ 2791 if (interval > LS_MAX_POLL_INTERVAL) { 2792 2793 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2794 "Low speed endpoint's poll interval is " 2795 "greater than %d ms", LS_MAX_POLL_INTERVAL); 2796 2797 return (USB_FAILURE); 2798 } 2799 break; 2800 2801 case USBA_FULL_SPEED_DEV: 2802 /* 2803 * Return an error if the polling interval is less 2804 * than 1ms and greater than 255ms. 2805 */ 2806 if ((interval < FS_MIN_POLL_INTERVAL) && 2807 (interval > FS_MAX_POLL_INTERVAL)) { 2808 2809 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2810 "Full speed endpoint's poll interval must " 2811 "be between %d and %d ms", FS_MIN_POLL_INTERVAL, 2812 FS_MAX_POLL_INTERVAL); 2813 2814 return (USB_FAILURE); 2815 } 2816 break; 2817 case USBA_HIGH_SPEED_DEV: 2818 /* 2819 * Return an error if the polling interval is less 1 2820 * and greater than 16. Convert this value to 125us 2821 * units using 2^(bInterval -1). refer usb 2.0 spec 2822 * page 51 for details. 2823 */ 2824 if ((interval < HS_MIN_POLL_INTERVAL) && 2825 (interval > HS_MAX_POLL_INTERVAL)) { 2826 2827 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2828 "High speed endpoint's poll interval " 2829 "must be between %d and %d units", 2830 HS_MIN_POLL_INTERVAL, HS_MAX_POLL_INTERVAL); 2831 2832 return (USB_FAILURE); 2833 } 2834 2835 /* Adjust high speed device polling interval */ 2836 interval = 2837 ehci_adjust_high_speed_polling_interval(ehcip, endpoint); 2838 2839 break; 2840 } 2841 2842 /* 2843 * If polling interval is greater than 32ms, 2844 * adjust polling interval equal to 32ms. 2845 */ 2846 if (interval > EHCI_NUM_INTR_QH_LISTS) { 2847 interval = EHCI_NUM_INTR_QH_LISTS; 2848 } 2849 2850 /* 2851 * Find the nearest power of 2 that's less 2852 * than interval. 2853 */ 2854 while ((ehci_pow_2(i)) <= interval) { 2855 i++; 2856 } 2857 2858 return (ehci_pow_2((i - 1))); 2859 } 2860 2861 2862 /* 2863 * ehci_adjust_high_speed_polling_interval: 2864 */ 2865 /* ARGSUSED */ 2866 static int 2867 ehci_adjust_high_speed_polling_interval( 2868 ehci_state_t *ehcip, 2869 usb_ep_descr_t *endpoint) 2870 { 2871 uint_t interval; 2872 2873 /* Get the polling interval */ 2874 interval = ehci_pow_2(endpoint->bInterval - 1); 2875 2876 /* 2877 * Convert polling interval from micro seconds 2878 * to milli seconds. 2879 */ 2880 if (interval <= EHCI_MAX_UFRAMES) { 2881 interval = 1; 2882 } else { 2883 interval = interval/EHCI_MAX_UFRAMES; 2884 } 2885 2886 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2887 "ehci_adjust_high_speed_polling_interval: " 2888 "High speed adjusted interval 0x%x", interval); 2889 2890 return (interval); 2891 } 2892 2893 2894 /* 2895 * ehci_lattice_height: 2896 * 2897 * Given the requested bandwidth, find the height in the tree at which the 2898 * nodes for this bandwidth fall. The height is measured as the number of 2899 * nodes from the leaf to the level specified by bandwidth The root of the 2900 * tree is at height TREE_HEIGHT. 2901 */ 2902 static uint_t 2903 ehci_lattice_height(uint_t interval) 2904 { 2905 return (TREE_HEIGHT - (ehci_log_2(interval))); 2906 } 2907 2908 2909 /* 2910 * ehci_lattice_parent: 2911 * 2912 * Given a node in the lattice, find the index of the parent node 2913 */ 2914 static uint_t 2915 ehci_lattice_parent(uint_t node) 2916 { 2917 if ((node % 2) == 0) { 2918 2919 return ((node/2) - 1); 2920 } else { 2921 2922 return ((node + 1)/2 - 1); 2923 } 2924 } 2925 2926 2927 /* 2928 * ehci_find_periodic_node: 2929 * 2930 * Based on the "real" array leaf node and interval, get the periodic node. 2931 */ 2932 static uint_t 2933 ehci_find_periodic_node(uint_t leaf, int interval) { 2934 uint_t lattice_leaf; 2935 uint_t height = ehci_lattice_height(interval); 2936 uint_t pnode; 2937 int i; 2938 2939 /* Get the leaf number in the lattice */ 2940 lattice_leaf = leaf + EHCI_NUM_INTR_QH_LISTS - 1; 2941 2942 /* Get the node in the lattice based on the height and leaf */ 2943 pnode = lattice_leaf; 2944 for (i = 0; i < height; i++) { 2945 pnode = ehci_lattice_parent(pnode); 2946 } 2947 2948 return (pnode); 2949 } 2950 2951 2952 /* 2953 * ehci_leftmost_leaf: 2954 * 2955 * Find the leftmost leaf in the subtree specified by the node. Height refers 2956 * to number of nodes from the bottom of the tree to the node, including the 2957 * node. 2958 * 2959 * The formula for a zero based tree is: 2960 * 2^H * Node + 2^H - 1 2961 * The leaf of the tree is an array, convert the number for the array. 2962 * Subtract the size of nodes not in the array 2963 * 2^H * Node + 2^H - 1 - (EHCI_NUM_INTR_QH_LISTS - 1) = 2964 * 2^H * Node + 2^H - EHCI_NUM_INTR_QH_LISTS = 2965 * 2^H * (Node + 1) - EHCI_NUM_INTR_QH_LISTS 2966 * 0 2967 * 1 2 2968 * 0 1 2 3 2969 */ 2970 static uint_t 2971 ehci_leftmost_leaf( 2972 uint_t node, 2973 uint_t height) 2974 { 2975 return ((ehci_pow_2(height) * (node + 1)) - EHCI_NUM_INTR_QH_LISTS); 2976 } 2977 2978 2979 /* 2980 * ehci_pow_2: 2981 * 2982 * Compute 2 to the power 2983 */ 2984 static uint_t 2985 ehci_pow_2(uint_t x) 2986 { 2987 if (x == 0) { 2988 2989 return (1); 2990 } else { 2991 2992 return (2 << (x - 1)); 2993 } 2994 } 2995 2996 2997 /* 2998 * ehci_log_2: 2999 * 3000 * Compute log base 2 of x 3001 */ 3002 static uint_t 3003 ehci_log_2(uint_t x) 3004 { 3005 int i = 0; 3006 3007 while (x != 1) { 3008 x = x >> 1; 3009 i++; 3010 } 3011 3012 return (i); 3013 } 3014 3015 3016 /* 3017 * ehci_find_bestfit_hs_mask: 3018 * 3019 * Find the smask and cmask in the bandwidth allocation, and update the 3020 * bandwidth allocation. 3021 */ 3022 static int 3023 ehci_find_bestfit_hs_mask( 3024 ehci_state_t *ehcip, 3025 uchar_t *smask, 3026 uint_t *pnode, 3027 usb_ep_descr_t *endpoint, 3028 uint_t bandwidth, 3029 int interval) 3030 { 3031 int i; 3032 uint_t elements, index; 3033 int array_leaf, best_array_leaf; 3034 uint_t node_bandwidth, best_node_bandwidth; 3035 uint_t leaf_count; 3036 uchar_t bw_mask; 3037 uchar_t best_smask; 3038 3039 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3040 "ehci_find_bestfit_hs_mask: "); 3041 3042 /* Get all the valid smasks */ 3043 switch (ehci_pow_2(endpoint->bInterval - 1)) { 3044 case EHCI_INTR_1US_POLL: 3045 index = EHCI_1US_MASK_INDEX; 3046 elements = EHCI_INTR_1US_POLL; 3047 break; 3048 case EHCI_INTR_2US_POLL: 3049 index = EHCI_2US_MASK_INDEX; 3050 elements = EHCI_INTR_2US_POLL; 3051 break; 3052 case EHCI_INTR_4US_POLL: 3053 index = EHCI_4US_MASK_INDEX; 3054 elements = EHCI_INTR_4US_POLL; 3055 break; 3056 case EHCI_INTR_XUS_POLL: 3057 default: 3058 index = EHCI_XUS_MASK_INDEX; 3059 elements = EHCI_INTR_XUS_POLL; 3060 break; 3061 } 3062 3063 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3064 3065 /* 3066 * Because of the way the leaves are setup, we will automatically 3067 * hit the leftmost leaf of every possible node with this interval. 3068 */ 3069 best_smask = 0x00; 3070 best_node_bandwidth = 0; 3071 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3072 /* Find the bandwidth mask */ 3073 node_bandwidth = ehci_calculate_bw_availability_mask(ehcip, 3074 bandwidth, ehci_index[array_leaf], leaf_count, &bw_mask); 3075 3076 /* 3077 * If this node cannot support our requirements skip to the 3078 * next leaf. 3079 */ 3080 if (bw_mask == 0x00) { 3081 continue; 3082 } 3083 3084 /* 3085 * Now make sure our bandwidth requirements can be 3086 * satisfied with one of smasks in this node. 3087 */ 3088 *smask = 0x00; 3089 for (i = index; i < (index + elements); i++) { 3090 /* Check the start split mask value */ 3091 if (ehci_start_split_mask[index] & bw_mask) { 3092 *smask = ehci_start_split_mask[index]; 3093 break; 3094 } 3095 } 3096 3097 /* 3098 * If an appropriate smask is found save the information if: 3099 * o best_smask has not been found yet. 3100 * - or - 3101 * o This is the node with the least amount of bandwidth 3102 */ 3103 if ((*smask != 0x00) && 3104 ((best_smask == 0x00) || 3105 (best_node_bandwidth > node_bandwidth))) { 3106 3107 best_node_bandwidth = node_bandwidth; 3108 best_array_leaf = array_leaf; 3109 best_smask = *smask; 3110 } 3111 } 3112 3113 /* 3114 * If we find node that can handle the bandwidth populate the 3115 * appropriate variables and return success. 3116 */ 3117 if (best_smask) { 3118 *smask = best_smask; 3119 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3120 interval); 3121 ehci_update_bw_availability(ehcip, bandwidth, 3122 ehci_index[best_array_leaf], leaf_count, best_smask); 3123 3124 return (USB_SUCCESS); 3125 } 3126 3127 return (USB_FAILURE); 3128 } 3129 3130 3131 /* 3132 * ehci_find_bestfit_ls_intr_mask: 3133 * 3134 * Find the smask and cmask in the bandwidth allocation. 3135 */ 3136 static int 3137 ehci_find_bestfit_ls_intr_mask( 3138 ehci_state_t *ehcip, 3139 uchar_t *smask, 3140 uchar_t *cmask, 3141 uint_t *pnode, 3142 uint_t sbandwidth, 3143 uint_t cbandwidth, 3144 int interval) 3145 { 3146 int i; 3147 uint_t elements, index; 3148 int array_leaf, best_array_leaf; 3149 uint_t node_sbandwidth, node_cbandwidth; 3150 uint_t best_node_bandwidth; 3151 uint_t leaf_count; 3152 uchar_t bw_smask, bw_cmask; 3153 uchar_t best_smask, best_cmask; 3154 3155 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3156 "ehci_find_bestfit_ls_intr_mask: "); 3157 3158 /* For low and full speed devices */ 3159 index = EHCI_XUS_MASK_INDEX; 3160 elements = EHCI_INTR_4MS_POLL; 3161 3162 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3163 3164 /* 3165 * Because of the way the leaves are setup, we will automatically 3166 * hit the leftmost leaf of every possible node with this interval. 3167 */ 3168 best_smask = 0x00; 3169 best_node_bandwidth = 0; 3170 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3171 /* Find the bandwidth mask */ 3172 node_sbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3173 sbandwidth, ehci_index[array_leaf], leaf_count, &bw_smask); 3174 node_cbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3175 cbandwidth, ehci_index[array_leaf], leaf_count, &bw_cmask); 3176 3177 /* 3178 * If this node cannot support our requirements skip to the 3179 * next leaf. 3180 */ 3181 if ((bw_smask == 0x00) || (bw_cmask == 0x00)) { 3182 continue; 3183 } 3184 3185 /* 3186 * Now make sure our bandwidth requirements can be 3187 * satisfied with one of smasks in this node. 3188 */ 3189 *smask = 0x00; 3190 *cmask = 0x00; 3191 for (i = index; i < (index + elements); i++) { 3192 /* Check the start split mask value */ 3193 if ((ehci_start_split_mask[index] & bw_smask) && 3194 (ehci_intr_complete_split_mask[index] & bw_cmask)) { 3195 *smask = ehci_start_split_mask[index]; 3196 *cmask = ehci_intr_complete_split_mask[index]; 3197 break; 3198 } 3199 } 3200 3201 /* 3202 * If an appropriate smask is found save the information if: 3203 * o best_smask has not been found yet. 3204 * - or - 3205 * o This is the node with the least amount of bandwidth 3206 */ 3207 if ((*smask != 0x00) && 3208 ((best_smask == 0x00) || 3209 (best_node_bandwidth > 3210 (node_sbandwidth + node_cbandwidth)))) { 3211 best_node_bandwidth = node_sbandwidth + node_cbandwidth; 3212 best_array_leaf = array_leaf; 3213 best_smask = *smask; 3214 best_cmask = *cmask; 3215 } 3216 } 3217 3218 /* 3219 * If we find node that can handle the bandwidth populate the 3220 * appropriate variables and return success. 3221 */ 3222 if (best_smask) { 3223 *smask = best_smask; 3224 *cmask = best_cmask; 3225 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3226 interval); 3227 ehci_update_bw_availability(ehcip, sbandwidth, 3228 ehci_index[best_array_leaf], leaf_count, best_smask); 3229 ehci_update_bw_availability(ehcip, cbandwidth, 3230 ehci_index[best_array_leaf], leaf_count, best_cmask); 3231 3232 return (USB_SUCCESS); 3233 } 3234 3235 return (USB_FAILURE); 3236 } 3237 3238 3239 /* 3240 * ehci_find_bestfit_sitd_in_mask: 3241 * 3242 * Find the smask and cmask in the bandwidth allocation. 3243 */ 3244 static int 3245 ehci_find_bestfit_sitd_in_mask( 3246 ehci_state_t *ehcip, 3247 uchar_t *smask, 3248 uchar_t *cmask, 3249 uint_t *pnode, 3250 uint_t sbandwidth, 3251 uint_t cbandwidth, 3252 int interval) 3253 { 3254 int i, uFrames, found; 3255 int array_leaf, best_array_leaf; 3256 uint_t node_sbandwidth, node_cbandwidth; 3257 uint_t best_node_bandwidth; 3258 uint_t leaf_count; 3259 uchar_t bw_smask, bw_cmask; 3260 uchar_t best_smask, best_cmask; 3261 3262 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3263 "ehci_find_bestfit_sitd_in_mask: "); 3264 3265 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3266 3267 /* 3268 * Because of the way the leaves are setup, we will automatically 3269 * hit the leftmost leaf of every possible node with this interval. 3270 * You may only send MAX_UFRAME_SITD_XFER raw bits per uFrame. 3271 */ 3272 /* 3273 * Need to add an additional 2 uFrames, if the "L"ast 3274 * complete split is before uFrame 6. See section 3275 * 11.8.4 in USB 2.0 Spec. Currently we do not support 3276 * the "Back Ptr" which means we support on IN of 3277 * ~4*MAX_UFRAME_SITD_XFER bandwidth/ 3278 */ 3279 uFrames = (cbandwidth / MAX_UFRAME_SITD_XFER) + 2; 3280 if (cbandwidth % MAX_UFRAME_SITD_XFER) { 3281 uFrames++; 3282 } 3283 if (uFrames > 6) { 3284 3285 return (USB_FAILURE); 3286 } 3287 *smask = 0x1; 3288 *cmask = 0x00; 3289 for (i = 0; i < uFrames; i++) { 3290 *cmask = *cmask << 1; 3291 *cmask |= 0x1; 3292 } 3293 /* cmask must start 2 frames after the smask */ 3294 *cmask = *cmask << 2; 3295 3296 found = 0; 3297 best_smask = 0x00; 3298 best_node_bandwidth = 0; 3299 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3300 node_sbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3301 sbandwidth, ehci_index[array_leaf], leaf_count, &bw_smask); 3302 node_cbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3303 MAX_UFRAME_SITD_XFER, ehci_index[array_leaf], leaf_count, 3304 &bw_cmask); 3305 3306 /* 3307 * If this node cannot support our requirements skip to the 3308 * next leaf. 3309 */ 3310 if ((bw_smask == 0x00) || (bw_cmask == 0x00)) { 3311 continue; 3312 } 3313 3314 for (i = 0; i < (EHCI_MAX_UFRAMES - uFrames - 2); i++) { 3315 if ((*smask & bw_smask) && (*cmask & bw_cmask)) { 3316 found = 1; 3317 break; 3318 } 3319 *smask = *smask << 1; 3320 *cmask = *cmask << 1; 3321 } 3322 3323 /* 3324 * If an appropriate smask is found save the information if: 3325 * o best_smask has not been found yet. 3326 * - or - 3327 * o This is the node with the least amount of bandwidth 3328 */ 3329 if (found && 3330 ((best_smask == 0x00) || 3331 (best_node_bandwidth > 3332 (node_sbandwidth + node_cbandwidth)))) { 3333 best_node_bandwidth = node_sbandwidth + node_cbandwidth; 3334 best_array_leaf = array_leaf; 3335 best_smask = *smask; 3336 best_cmask = *cmask; 3337 } 3338 } 3339 3340 /* 3341 * If we find node that can handle the bandwidth populate the 3342 * appropriate variables and return success. 3343 */ 3344 if (best_smask) { 3345 *smask = best_smask; 3346 *cmask = best_cmask; 3347 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3348 interval); 3349 ehci_update_bw_availability(ehcip, sbandwidth, 3350 ehci_index[best_array_leaf], leaf_count, best_smask); 3351 ehci_update_bw_availability(ehcip, MAX_UFRAME_SITD_XFER, 3352 ehci_index[best_array_leaf], leaf_count, best_cmask); 3353 3354 return (USB_SUCCESS); 3355 } 3356 3357 return (USB_FAILURE); 3358 } 3359 3360 3361 /* 3362 * ehci_find_bestfit_sitd_out_mask: 3363 * 3364 * Find the smask in the bandwidth allocation. 3365 */ 3366 static int 3367 ehci_find_bestfit_sitd_out_mask( 3368 ehci_state_t *ehcip, 3369 uchar_t *smask, 3370 uint_t *pnode, 3371 uint_t sbandwidth, 3372 int interval) 3373 { 3374 int i, uFrames, found; 3375 int array_leaf, best_array_leaf; 3376 uint_t node_sbandwidth; 3377 uint_t best_node_bandwidth; 3378 uint_t leaf_count; 3379 uchar_t bw_smask; 3380 uchar_t best_smask; 3381 3382 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3383 "ehci_find_bestfit_sitd_out_mask: "); 3384 3385 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3386 3387 /* 3388 * Because of the way the leaves are setup, we will automatically 3389 * hit the leftmost leaf of every possible node with this interval. 3390 * You may only send MAX_UFRAME_SITD_XFER raw bits per uFrame. 3391 */ 3392 *smask = 0x00; 3393 uFrames = sbandwidth / MAX_UFRAME_SITD_XFER; 3394 if (sbandwidth % MAX_UFRAME_SITD_XFER) { 3395 uFrames++; 3396 } 3397 for (i = 0; i < uFrames; i++) { 3398 *smask = *smask << 1; 3399 *smask |= 0x1; 3400 } 3401 3402 found = 0; 3403 best_smask = 0x00; 3404 best_node_bandwidth = 0; 3405 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3406 node_sbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3407 MAX_UFRAME_SITD_XFER, ehci_index[array_leaf], leaf_count, 3408 &bw_smask); 3409 3410 /* 3411 * If this node cannot support our requirements skip to the 3412 * next leaf. 3413 */ 3414 if (bw_smask == 0x00) { 3415 continue; 3416 } 3417 3418 /* You cannot have a start split on the 8th uFrame */ 3419 for (i = 0; (*smask & 0x80) == 0; i++) { 3420 if (*smask & bw_smask) { 3421 found = 1; 3422 break; 3423 } 3424 *smask = *smask << 1; 3425 } 3426 3427 /* 3428 * If an appropriate smask is found save the information if: 3429 * o best_smask has not been found yet. 3430 * - or - 3431 * o This is the node with the least amount of bandwidth 3432 */ 3433 if (found && 3434 ((best_smask == 0x00) || 3435 (best_node_bandwidth > node_sbandwidth))) { 3436 best_node_bandwidth = node_sbandwidth; 3437 best_array_leaf = array_leaf; 3438 best_smask = *smask; 3439 } 3440 } 3441 3442 /* 3443 * If we find node that can handle the bandwidth populate the 3444 * appropriate variables and return success. 3445 */ 3446 if (best_smask) { 3447 *smask = best_smask; 3448 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3449 interval); 3450 ehci_update_bw_availability(ehcip, MAX_UFRAME_SITD_XFER, 3451 ehci_index[best_array_leaf], leaf_count, best_smask); 3452 3453 return (USB_SUCCESS); 3454 } 3455 3456 return (USB_FAILURE); 3457 } 3458 3459 3460 /* 3461 * ehci_calculate_bw_availability_mask: 3462 * 3463 * Returns the "total bandwidth used" in this node. 3464 * Populates bw_mask with the uFrames that can support the bandwidth. 3465 * 3466 * If all the Frames cannot support this bandwidth, then bw_mask 3467 * will return 0x00 and the "total bandwidth used" will be invalid. 3468 */ 3469 static uint_t 3470 ehci_calculate_bw_availability_mask( 3471 ehci_state_t *ehcip, 3472 uint_t bandwidth, 3473 int leaf, 3474 int leaf_count, 3475 uchar_t *bw_mask) 3476 { 3477 int i, j; 3478 uchar_t bw_uframe; 3479 int uframe_total; 3480 ehci_frame_bandwidth_t *fbp; 3481 uint_t total_bandwidth = 0; 3482 3483 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3484 "ehci_calculate_bw_availability_mask: leaf %d leaf count %d", 3485 leaf, leaf_count); 3486 3487 /* Start by saying all uFrames are available */ 3488 *bw_mask = 0xFF; 3489 3490 for (i = 0; (i < leaf_count) || (*bw_mask == 0x00); i++) { 3491 fbp = &ehcip->ehci_frame_bandwidth[leaf + i]; 3492 3493 total_bandwidth += fbp->ehci_allocated_frame_bandwidth; 3494 3495 for (j = 0; j < EHCI_MAX_UFRAMES; j++) { 3496 /* 3497 * If the uFrame in bw_mask is available check to see if 3498 * it can support the additional bandwidth. 3499 */ 3500 bw_uframe = (*bw_mask & (0x1 << j)); 3501 uframe_total = 3502 fbp->ehci_micro_frame_bandwidth[j] + 3503 bandwidth; 3504 if ((bw_uframe) && 3505 (uframe_total > HS_PERIODIC_BANDWIDTH)) { 3506 *bw_mask = *bw_mask & ~bw_uframe; 3507 } 3508 } 3509 } 3510 3511 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3512 "ehci_calculate_bw_availability_mask: bandwidth mask 0x%x", 3513 *bw_mask); 3514 3515 return (total_bandwidth); 3516 } 3517 3518 3519 /* 3520 * ehci_update_bw_availability: 3521 * 3522 * The leftmost leaf needs to be in terms of array position and 3523 * not the actual lattice position. 3524 */ 3525 static void 3526 ehci_update_bw_availability( 3527 ehci_state_t *ehcip, 3528 int bandwidth, 3529 int leftmost_leaf, 3530 int leaf_count, 3531 uchar_t mask) 3532 { 3533 int i, j; 3534 ehci_frame_bandwidth_t *fbp; 3535 int uFrame_bandwidth[8]; 3536 3537 USB_DPRINTF_L4(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3538 "ehci_update_bw_availability: " 3539 "leaf %d count %d bandwidth 0x%x mask 0x%x", 3540 leftmost_leaf, leaf_count, bandwidth, mask); 3541 3542 ASSERT(leftmost_leaf < 32); 3543 ASSERT(leftmost_leaf >= 0); 3544 3545 for (j = 0; j < EHCI_MAX_UFRAMES; j++) { 3546 if (mask & 0x1) { 3547 uFrame_bandwidth[j] = bandwidth; 3548 } else { 3549 uFrame_bandwidth[j] = 0; 3550 } 3551 3552 mask = mask >> 1; 3553 } 3554 3555 /* Updated all the effected leafs with the bandwidth */ 3556 for (i = 0; i < leaf_count; i++) { 3557 fbp = &ehcip->ehci_frame_bandwidth[leftmost_leaf + i]; 3558 3559 for (j = 0; j < EHCI_MAX_UFRAMES; j++) { 3560 fbp->ehci_micro_frame_bandwidth[j] += 3561 uFrame_bandwidth[j]; 3562 fbp->ehci_allocated_frame_bandwidth += 3563 uFrame_bandwidth[j]; 3564 } 3565 } 3566 } 3567 3568 /* 3569 * Miscellaneous functions 3570 */ 3571 3572 /* 3573 * ehci_obtain_state: 3574 * 3575 * NOTE: This function is also called from POLLED MODE. 3576 */ 3577 ehci_state_t * 3578 ehci_obtain_state(dev_info_t *dip) 3579 { 3580 int instance = ddi_get_instance(dip); 3581 3582 ehci_state_t *state = ddi_get_soft_state(ehci_statep, instance); 3583 3584 ASSERT(state != NULL); 3585 3586 return (state); 3587 } 3588 3589 3590 /* 3591 * ehci_state_is_operational: 3592 * 3593 * Check the Host controller state and return proper values. 3594 */ 3595 int 3596 ehci_state_is_operational(ehci_state_t *ehcip) 3597 { 3598 int val; 3599 3600 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3601 3602 switch (ehcip->ehci_hc_soft_state) { 3603 case EHCI_CTLR_INIT_STATE: 3604 case EHCI_CTLR_SUSPEND_STATE: 3605 val = USB_FAILURE; 3606 break; 3607 case EHCI_CTLR_OPERATIONAL_STATE: 3608 val = USB_SUCCESS; 3609 break; 3610 case EHCI_CTLR_ERROR_STATE: 3611 val = USB_HC_HARDWARE_ERROR; 3612 break; 3613 default: 3614 val = USB_FAILURE; 3615 break; 3616 } 3617 3618 return (val); 3619 } 3620 3621 3622 /* 3623 * ehci_do_soft_reset 3624 * 3625 * Do soft reset of ehci host controller. 3626 */ 3627 int 3628 ehci_do_soft_reset(ehci_state_t *ehcip) 3629 { 3630 usb_frame_number_t before_frame_number, after_frame_number; 3631 ehci_regs_t *ehci_save_regs; 3632 3633 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3634 3635 /* Increment host controller error count */ 3636 ehcip->ehci_hc_error++; 3637 3638 USB_DPRINTF_L3(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3639 "ehci_do_soft_reset:" 3640 "Reset ehci host controller 0x%x", ehcip->ehci_hc_error); 3641 3642 /* 3643 * Allocate space for saving current Host Controller 3644 * registers. Don't do any recovery if allocation 3645 * fails. 3646 */ 3647 ehci_save_regs = (ehci_regs_t *) 3648 kmem_zalloc(sizeof (ehci_regs_t), KM_NOSLEEP); 3649 3650 if (ehci_save_regs == NULL) { 3651 USB_DPRINTF_L2(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3652 "ehci_do_soft_reset: kmem_zalloc failed"); 3653 3654 return (USB_FAILURE); 3655 } 3656 3657 /* Save current ehci registers */ 3658 ehci_save_regs->ehci_command = Get_OpReg(ehci_command); 3659 ehci_save_regs->ehci_interrupt = Get_OpReg(ehci_interrupt); 3660 ehci_save_regs->ehci_ctrl_segment = Get_OpReg(ehci_ctrl_segment); 3661 ehci_save_regs->ehci_async_list_addr = Get_OpReg(ehci_async_list_addr); 3662 ehci_save_regs->ehci_config_flag = Get_OpReg(ehci_config_flag); 3663 ehci_save_regs->ehci_periodic_list_base = 3664 Get_OpReg(ehci_periodic_list_base); 3665 3666 USB_DPRINTF_L3(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3667 "ehci_do_soft_reset: Save reg = 0x%p", ehci_save_regs); 3668 3669 /* Disable all list processing and interrupts */ 3670 Set_OpReg(ehci_command, Get_OpReg(ehci_command) & 3671 ~(EHCI_CMD_ASYNC_SCHED_ENABLE | EHCI_CMD_PERIODIC_SCHED_ENABLE)); 3672 3673 /* Disable all EHCI interrupts */ 3674 Set_OpReg(ehci_interrupt, 0); 3675 3676 /* Wait for few milliseconds */ 3677 drv_usecwait(EHCI_SOF_TIMEWAIT); 3678 3679 /* Do light soft reset of ehci host controller */ 3680 Set_OpReg(ehci_command, 3681 Get_OpReg(ehci_command) | EHCI_CMD_LIGHT_HC_RESET); 3682 3683 USB_DPRINTF_L3(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3684 "ehci_do_soft_reset: Reset in progress"); 3685 3686 /* Wait for reset to complete */ 3687 drv_usecwait(EHCI_RESET_TIMEWAIT); 3688 3689 /* 3690 * Restore previous saved EHCI register value 3691 * into the current EHCI registers. 3692 */ 3693 Set_OpReg(ehci_ctrl_segment, (uint32_t) 3694 ehci_save_regs->ehci_ctrl_segment); 3695 3696 Set_OpReg(ehci_periodic_list_base, (uint32_t) 3697 ehci_save_regs->ehci_periodic_list_base); 3698 3699 Set_OpReg(ehci_async_list_addr, (uint32_t) 3700 ehci_save_regs->ehci_async_list_addr); 3701 3702 /* 3703 * For some reason this register might get nulled out by 3704 * the Uli M1575 South Bridge. To workaround the hardware 3705 * problem, check the value after write and retry if the 3706 * last write fails. 3707 */ 3708 if ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) && 3709 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575) && 3710 (ehci_save_regs->ehci_async_list_addr != 3711 Get_OpReg(ehci_async_list_addr))) { 3712 int retry = 0; 3713 3714 Set_OpRegRetry(ehci_async_list_addr, (uint32_t) 3715 ehci_save_regs->ehci_async_list_addr, retry); 3716 if (retry >= EHCI_MAX_RETRY) { 3717 USB_DPRINTF_L2(PRINT_MASK_ATTA, 3718 ehcip->ehci_log_hdl, "ehci_do_soft_reset:" 3719 " ASYNCLISTADDR write failed."); 3720 3721 return (USB_FAILURE); 3722 } 3723 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3724 "ehci_do_soft_reset: ASYNCLISTADDR " 3725 "write failed, retry=%d", retry); 3726 } 3727 3728 Set_OpReg(ehci_config_flag, (uint32_t) 3729 ehci_save_regs->ehci_config_flag); 3730 3731 /* Enable both Asynchronous and Periodic Schedule if necessary */ 3732 ehci_toggle_scheduler(ehcip); 3733 3734 /* 3735 * Set ehci_interrupt to enable all interrupts except Root 3736 * Hub Status change and frame list rollover interrupts. 3737 */ 3738 Set_OpReg(ehci_interrupt, EHCI_INTR_HOST_SYSTEM_ERROR | 3739 EHCI_INTR_FRAME_LIST_ROLLOVER | 3740 EHCI_INTR_USB_ERROR | 3741 EHCI_INTR_USB); 3742 3743 /* 3744 * Deallocate the space that allocated for saving 3745 * HC registers. 3746 */ 3747 kmem_free((void *) ehci_save_regs, sizeof (ehci_regs_t)); 3748 3749 /* 3750 * Set the desired interrupt threshold, frame list size (if 3751 * applicable) and turn EHCI host controller. 3752 */ 3753 Set_OpReg(ehci_command, ((Get_OpReg(ehci_command) & 3754 ~EHCI_CMD_INTR_THRESHOLD) | 3755 (EHCI_CMD_01_INTR | EHCI_CMD_HOST_CTRL_RUN))); 3756 3757 /* Wait 10ms for EHCI to start sending SOF */ 3758 drv_usecwait(EHCI_RESET_TIMEWAIT); 3759 3760 /* 3761 * Get the current usb frame number before waiting for 3762 * few milliseconds. 3763 */ 3764 before_frame_number = ehci_get_current_frame_number(ehcip); 3765 3766 /* Wait for few milliseconds */ 3767 drv_usecwait(EHCI_SOF_TIMEWAIT); 3768 3769 /* 3770 * Get the current usb frame number after waiting for 3771 * few milliseconds. 3772 */ 3773 after_frame_number = ehci_get_current_frame_number(ehcip); 3774 3775 USB_DPRINTF_L4(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3776 "ehci_do_soft_reset: Before Frame Number 0x%llx " 3777 "After Frame Number 0x%llx", 3778 before_frame_number, after_frame_number); 3779 3780 if ((after_frame_number <= before_frame_number) && 3781 (Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED)) { 3782 3783 USB_DPRINTF_L2(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3784 "ehci_do_soft_reset: Soft reset failed"); 3785 3786 return (USB_FAILURE); 3787 } 3788 3789 return (USB_SUCCESS); 3790 } 3791 3792 3793 /* 3794 * ehci_get_xfer_attrs: 3795 * 3796 * Get the attributes of a particular xfer. 3797 * 3798 * NOTE: This function is also called from POLLED MODE. 3799 */ 3800 usb_req_attrs_t 3801 ehci_get_xfer_attrs( 3802 ehci_state_t *ehcip, 3803 ehci_pipe_private_t *pp, 3804 ehci_trans_wrapper_t *tw) 3805 { 3806 usb_ep_descr_t *eptd = &pp->pp_pipe_handle->p_ep; 3807 usb_req_attrs_t attrs = USB_ATTRS_NONE; 3808 3809 USB_DPRINTF_L4(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3810 "ehci_get_xfer_attrs:"); 3811 3812 switch (eptd->bmAttributes & USB_EP_ATTR_MASK) { 3813 case USB_EP_ATTR_CONTROL: 3814 attrs = ((usb_ctrl_req_t *) 3815 tw->tw_curr_xfer_reqp)->ctrl_attributes; 3816 break; 3817 case USB_EP_ATTR_BULK: 3818 attrs = ((usb_bulk_req_t *) 3819 tw->tw_curr_xfer_reqp)->bulk_attributes; 3820 break; 3821 case USB_EP_ATTR_INTR: 3822 attrs = ((usb_intr_req_t *) 3823 tw->tw_curr_xfer_reqp)->intr_attributes; 3824 break; 3825 } 3826 3827 return (attrs); 3828 } 3829 3830 3831 /* 3832 * ehci_get_current_frame_number: 3833 * 3834 * Get the current software based usb frame number. 3835 */ 3836 usb_frame_number_t 3837 ehci_get_current_frame_number(ehci_state_t *ehcip) 3838 { 3839 usb_frame_number_t usb_frame_number; 3840 usb_frame_number_t ehci_fno, micro_frame_number; 3841 3842 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3843 3844 ehci_fno = ehcip->ehci_fno; 3845 micro_frame_number = Get_OpReg(ehci_frame_index) & 0x3FFF; 3846 3847 /* 3848 * Calculate current software based usb frame number. 3849 * 3850 * This code accounts for the fact that frame number is 3851 * updated by the Host Controller before the ehci driver 3852 * gets an FrameListRollover interrupt that will adjust 3853 * Frame higher part. 3854 * 3855 * Refer ehci specification 1.0, section 2.3.2, page 21. 3856 */ 3857 micro_frame_number = ((micro_frame_number & 0x1FFF) | 3858 ehci_fno) + (((micro_frame_number & 0x3FFF) ^ 3859 ehci_fno) & 0x2000); 3860 3861 /* 3862 * Micro Frame number is equivalent to 125 usec. Eight 3863 * Micro Frame numbers are equivalent to one millsecond 3864 * or one usb frame number. 3865 */ 3866 usb_frame_number = micro_frame_number >> 3867 EHCI_uFRAMES_PER_USB_FRAME_SHIFT; 3868 3869 USB_DPRINTF_L4(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3870 "ehci_get_current_frame_number: " 3871 "Current usb uframe number = 0x%llx " 3872 "Current usb frame number = 0x%llx", 3873 micro_frame_number, usb_frame_number); 3874 3875 return (usb_frame_number); 3876 } 3877 3878 3879 /* 3880 * ehci_cpr_cleanup: 3881 * 3882 * Cleanup ehci state and other ehci specific informations across 3883 * Check Point Resume (CPR). 3884 */ 3885 static void 3886 ehci_cpr_cleanup(ehci_state_t *ehcip) 3887 { 3888 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3889 3890 /* Reset software part of usb frame number */ 3891 ehcip->ehci_fno = 0; 3892 } 3893 3894 3895 /* 3896 * ehci_wait_for_sof: 3897 * 3898 * Wait for couple of SOF interrupts 3899 */ 3900 int 3901 ehci_wait_for_sof(ehci_state_t *ehcip) 3902 { 3903 usb_frame_number_t before_frame_number, after_frame_number; 3904 int error = USB_SUCCESS; 3905 3906 USB_DPRINTF_L4(PRINT_MASK_LISTS, 3907 ehcip->ehci_log_hdl, "ehci_wait_for_sof"); 3908 3909 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3910 3911 error = ehci_state_is_operational(ehcip); 3912 3913 if (error != USB_SUCCESS) { 3914 3915 return (error); 3916 } 3917 3918 /* Get the current usb frame number before waiting for two SOFs */ 3919 before_frame_number = ehci_get_current_frame_number(ehcip); 3920 3921 mutex_exit(&ehcip->ehci_int_mutex); 3922 3923 /* Wait for few milliseconds */ 3924 delay(drv_usectohz(EHCI_SOF_TIMEWAIT)); 3925 3926 mutex_enter(&ehcip->ehci_int_mutex); 3927 3928 /* Get the current usb frame number after woken up */ 3929 after_frame_number = ehci_get_current_frame_number(ehcip); 3930 3931 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3932 "ehci_wait_for_sof: framenumber: before 0x%llx " 3933 "after 0x%llx", before_frame_number, after_frame_number); 3934 3935 /* Return failure, if usb frame number has not been changed */ 3936 if (after_frame_number <= before_frame_number) { 3937 3938 if ((ehci_do_soft_reset(ehcip)) != USB_SUCCESS) { 3939 3940 USB_DPRINTF_L0(PRINT_MASK_LISTS, 3941 ehcip->ehci_log_hdl, "No SOF interrupts"); 3942 3943 /* Set host controller soft state to error */ 3944 ehcip->ehci_hc_soft_state = EHCI_CTLR_ERROR_STATE; 3945 3946 return (USB_FAILURE); 3947 } 3948 3949 } 3950 3951 return (USB_SUCCESS); 3952 } 3953 3954 3955 /* 3956 * ehci_toggle_scheduler: 3957 * 3958 * Turn scheduler based on pipe open count. 3959 */ 3960 void 3961 ehci_toggle_scheduler(ehci_state_t *ehcip) { 3962 uint_t temp_reg, cmd_reg; 3963 3964 cmd_reg = Get_OpReg(ehci_command); 3965 temp_reg = cmd_reg; 3966 3967 /* 3968 * Enable/Disable asynchronous scheduler, and 3969 * turn on/off async list door bell 3970 */ 3971 if (ehcip->ehci_open_async_count) { 3972 if (!(cmd_reg & EHCI_CMD_ASYNC_SCHED_ENABLE)) { 3973 /* 3974 * For some reason this address might get nulled out by 3975 * the ehci chip. Set it here just in case it is null. 3976 */ 3977 Set_OpReg(ehci_async_list_addr, 3978 ehci_qh_cpu_to_iommu(ehcip, 3979 ehcip->ehci_head_of_async_sched_list)); 3980 3981 /* 3982 * For some reason this register might get nulled out by 3983 * the Uli M1575 Southbridge. To workaround the HW 3984 * problem, check the value after write and retry if the 3985 * last write fails. 3986 * 3987 * If the ASYNCLISTADDR remains "stuck" after 3988 * EHCI_MAX_RETRY retries, then the M1575 is broken 3989 * and is stuck in an inconsistent state and is about 3990 * to crash the machine with a trn_oor panic when it 3991 * does a DMA read from 0x0. It is better to panic 3992 * now rather than wait for the trn_oor crash; this 3993 * way Customer Service will have a clean signature 3994 * that indicts the M1575 chip rather than a 3995 * mysterious and hard-to-diagnose trn_oor panic. 3996 */ 3997 if ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) && 3998 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575) && 3999 (ehci_qh_cpu_to_iommu(ehcip, 4000 ehcip->ehci_head_of_async_sched_list) != 4001 Get_OpReg(ehci_async_list_addr))) { 4002 int retry = 0; 4003 4004 Set_OpRegRetry(ehci_async_list_addr, 4005 ehci_qh_cpu_to_iommu(ehcip, 4006 ehcip->ehci_head_of_async_sched_list), 4007 retry); 4008 if (retry >= EHCI_MAX_RETRY) 4009 cmn_err(CE_PANIC, 4010 "ehci_toggle_scheduler: " 4011 "ASYNCLISTADDR write failed."); 4012 4013 USB_DPRINTF_L2(PRINT_MASK_ATTA, 4014 ehcip->ehci_log_hdl, 4015 "ehci_toggle_scheduler: ASYNCLISTADDR " 4016 "write failed, retry=%d", retry); 4017 } 4018 } 4019 cmd_reg |= EHCI_CMD_ASYNC_SCHED_ENABLE; 4020 } else { 4021 cmd_reg &= ~EHCI_CMD_ASYNC_SCHED_ENABLE; 4022 } 4023 4024 if (ehcip->ehci_open_periodic_count) { 4025 if (!(cmd_reg & EHCI_CMD_PERIODIC_SCHED_ENABLE)) { 4026 /* 4027 * For some reason this address get's nulled out by 4028 * the ehci chip. Set it here just in case it is null. 4029 */ 4030 Set_OpReg(ehci_periodic_list_base, 4031 (uint32_t)(ehcip->ehci_pflt_cookie.dmac_address & 4032 0xFFFFF000)); 4033 } 4034 cmd_reg |= EHCI_CMD_PERIODIC_SCHED_ENABLE; 4035 } else { 4036 cmd_reg &= ~EHCI_CMD_PERIODIC_SCHED_ENABLE; 4037 } 4038 4039 /* Just an optimization */ 4040 if (temp_reg != cmd_reg) { 4041 Set_OpReg(ehci_command, cmd_reg); 4042 } 4043 } 4044 4045 /* 4046 * ehci print functions 4047 */ 4048 4049 /* 4050 * ehci_print_caps: 4051 */ 4052 void 4053 ehci_print_caps(ehci_state_t *ehcip) 4054 { 4055 uint_t i; 4056 4057 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4058 "\n\tUSB 2.0 Host Controller Characteristics\n"); 4059 4060 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4061 "Caps Length: 0x%x Version: 0x%x\n", 4062 Get_8Cap(ehci_caps_length), Get_16Cap(ehci_version)); 4063 4064 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4065 "Structural Parameters\n"); 4066 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4067 "Port indicators: %s", (Get_Cap(ehci_hcs_params) & 4068 EHCI_HCS_PORT_INDICATOR) ? "Yes" : "No"); 4069 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4070 "No of Classic host controllers: 0x%x", 4071 (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_COMP_CTRLS) 4072 >> EHCI_HCS_NUM_COMP_CTRL_SHIFT); 4073 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4074 "No of ports per Classic host controller: 0x%x", 4075 (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS_CC) 4076 >> EHCI_HCS_NUM_PORTS_CC_SHIFT); 4077 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4078 "Port routing rules: %s", (Get_Cap(ehci_hcs_params) & 4079 EHCI_HCS_PORT_ROUTING_RULES) ? "Yes" : "No"); 4080 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4081 "Port power control: %s", (Get_Cap(ehci_hcs_params) & 4082 EHCI_HCS_PORT_POWER_CONTROL) ? "Yes" : "No"); 4083 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4084 "No of root hub ports: 0x%x\n", 4085 Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS); 4086 4087 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4088 "Capability Parameters\n"); 4089 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4090 "EHCI extended capability: %s", (Get_Cap(ehci_hcc_params) & 4091 EHCI_HCC_EECP) ? "Yes" : "No"); 4092 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4093 "Isoch schedule threshold: 0x%x", 4094 Get_Cap(ehci_hcc_params) & EHCI_HCC_ISOCH_SCHED_THRESHOLD); 4095 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4096 "Async schedule park capability: %s", (Get_Cap(ehci_hcc_params) & 4097 EHCI_HCC_ASYNC_SCHED_PARK_CAP) ? "Yes" : "No"); 4098 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4099 "Programmable frame list flag: %s", (Get_Cap(ehci_hcc_params) & 4100 EHCI_HCC_PROG_FRAME_LIST_FLAG) ? "256/512/1024" : "1024"); 4101 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4102 "64bit addressing capability: %s\n", (Get_Cap(ehci_hcc_params) & 4103 EHCI_HCC_64BIT_ADDR_CAP) ? "Yes" : "No"); 4104 4105 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4106 "Classic Port Route Description"); 4107 4108 for (i = 0; i < (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS); i++) { 4109 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4110 "\tPort Route 0x%x: 0x%x", i, Get_8Cap(ehci_port_route[i])); 4111 } 4112 } 4113 4114 4115 /* 4116 * ehci_print_regs: 4117 */ 4118 void 4119 ehci_print_regs(ehci_state_t *ehcip) 4120 { 4121 uint_t i; 4122 4123 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4124 "\n\tEHCI%d Operational Registers\n", 4125 ddi_get_instance(ehcip->ehci_dip)); 4126 4127 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4128 "Command: 0x%x Status: 0x%x", 4129 Get_OpReg(ehci_command), Get_OpReg(ehci_status)); 4130 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4131 "Interrupt: 0x%x Frame Index: 0x%x", 4132 Get_OpReg(ehci_interrupt), Get_OpReg(ehci_frame_index)); 4133 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4134 "Control Segment: 0x%x Periodic List Base: 0x%x", 4135 Get_OpReg(ehci_ctrl_segment), Get_OpReg(ehci_periodic_list_base)); 4136 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4137 "Async List Addr: 0x%x Config Flag: 0x%x", 4138 Get_OpReg(ehci_async_list_addr), Get_OpReg(ehci_config_flag)); 4139 4140 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4141 "Root Hub Port Status"); 4142 4143 for (i = 0; i < (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS); i++) { 4144 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 4145 "\tPort Status 0x%x: 0x%x ", i, 4146 Get_OpReg(ehci_rh_port_status[i])); 4147 } 4148 } 4149 4150 4151 /* 4152 * ehci_print_qh: 4153 */ 4154 void 4155 ehci_print_qh( 4156 ehci_state_t *ehcip, 4157 ehci_qh_t *qh) 4158 { 4159 uint_t i; 4160 4161 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4162 "ehci_print_qh: qh = 0x%p", (void *)qh); 4163 4164 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4165 "\tqh_link_ptr: 0x%x ", Get_QH(qh->qh_link_ptr)); 4166 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4167 "\tqh_ctrl: 0x%x ", Get_QH(qh->qh_ctrl)); 4168 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4169 "\tqh_split_ctrl: 0x%x ", Get_QH(qh->qh_split_ctrl)); 4170 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4171 "\tqh_curr_qtd: 0x%x ", Get_QH(qh->qh_curr_qtd)); 4172 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4173 "\tqh_next_qtd: 0x%x ", Get_QH(qh->qh_next_qtd)); 4174 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4175 "\tqh_alt_next_qtd: 0x%x ", Get_QH(qh->qh_alt_next_qtd)); 4176 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4177 "\tqh_status: 0x%x ", Get_QH(qh->qh_status)); 4178 4179 for (i = 0; i < 5; i++) { 4180 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4181 "\tqh_buf[%d]: 0x%x ", i, Get_QH(qh->qh_buf[i])); 4182 } 4183 4184 for (i = 0; i < 5; i++) { 4185 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4186 "\tqh_buf_high[%d]: 0x%x ", 4187 i, Get_QH(qh->qh_buf_high[i])); 4188 } 4189 4190 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4191 "\tqh_dummy_qtd: 0x%x ", Get_QH(qh->qh_dummy_qtd)); 4192 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4193 "\tqh_prev: 0x%x ", Get_QH(qh->qh_prev)); 4194 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4195 "\tqh_state: 0x%x ", Get_QH(qh->qh_state)); 4196 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4197 "\tqh_reclaim_next: 0x%x ", Get_QH(qh->qh_reclaim_next)); 4198 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4199 "\tqh_reclaim_frame: 0x%x ", Get_QH(qh->qh_reclaim_frame)); 4200 } 4201 4202 4203 /* 4204 * ehci_print_qtd: 4205 */ 4206 void 4207 ehci_print_qtd( 4208 ehci_state_t *ehcip, 4209 ehci_qtd_t *qtd) 4210 { 4211 uint_t i; 4212 4213 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4214 "ehci_print_qtd: qtd = 0x%p", (void *)qtd); 4215 4216 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4217 "\tqtd_next_qtd: 0x%x ", Get_QTD(qtd->qtd_next_qtd)); 4218 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4219 "\tqtd_alt_next_qtd: 0x%x ", Get_QTD(qtd->qtd_alt_next_qtd)); 4220 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4221 "\tqtd_ctrl: 0x%x ", Get_QTD(qtd->qtd_ctrl)); 4222 4223 for (i = 0; i < 5; i++) { 4224 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4225 "\tqtd_buf[%d]: 0x%x ", i, Get_QTD(qtd->qtd_buf[i])); 4226 } 4227 4228 for (i = 0; i < 5; i++) { 4229 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4230 "\tqtd_buf_high[%d]: 0x%x ", 4231 i, Get_QTD(qtd->qtd_buf_high[i])); 4232 } 4233 4234 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4235 "\tqtd_trans_wrapper: 0x%x ", Get_QTD(qtd->qtd_trans_wrapper)); 4236 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4237 "\tqtd_tw_next_qtd: 0x%x ", Get_QTD(qtd->qtd_tw_next_qtd)); 4238 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4239 "\tqtd_active_qtd_next: 0x%x ", Get_QTD(qtd->qtd_active_qtd_next)); 4240 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4241 "\tqtd_active_qtd_prev: 0x%x ", Get_QTD(qtd->qtd_active_qtd_prev)); 4242 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4243 "\tqtd_state: 0x%x ", Get_QTD(qtd->qtd_state)); 4244 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4245 "\tqtd_ctrl_phase: 0x%x ", Get_QTD(qtd->qtd_ctrl_phase)); 4246 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4247 "\tqtd_xfer_offs: 0x%x ", Get_QTD(qtd->qtd_xfer_offs)); 4248 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4249 "\tqtd_xfer_len: 0x%x ", Get_QTD(qtd->qtd_xfer_len)); 4250 } 4251 4252 /* 4253 * ehci kstat functions 4254 */ 4255 4256 /* 4257 * ehci_create_stats: 4258 * 4259 * Allocate and initialize the ehci kstat structures 4260 */ 4261 void 4262 ehci_create_stats(ehci_state_t *ehcip) 4263 { 4264 char kstatname[KSTAT_STRLEN]; 4265 const char *dname = ddi_driver_name(ehcip->ehci_dip); 4266 char *usbtypes[USB_N_COUNT_KSTATS] = 4267 {"ctrl", "isoch", "bulk", "intr"}; 4268 uint_t instance = ehcip->ehci_instance; 4269 ehci_intrs_stats_t *isp; 4270 int i; 4271 4272 if (EHCI_INTRS_STATS(ehcip) == NULL) { 4273 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,intrs", 4274 dname, instance); 4275 EHCI_INTRS_STATS(ehcip) = kstat_create("usba", instance, 4276 kstatname, "usb_interrupts", KSTAT_TYPE_NAMED, 4277 sizeof (ehci_intrs_stats_t) / sizeof (kstat_named_t), 4278 KSTAT_FLAG_PERSISTENT); 4279 4280 if (EHCI_INTRS_STATS(ehcip)) { 4281 isp = EHCI_INTRS_STATS_DATA(ehcip); 4282 kstat_named_init(&isp->ehci_sts_total, 4283 "Interrupts Total", KSTAT_DATA_UINT64); 4284 kstat_named_init(&isp->ehci_sts_not_claimed, 4285 "Not Claimed", KSTAT_DATA_UINT64); 4286 kstat_named_init(&isp->ehci_sts_async_sched_status, 4287 "Async schedule status", KSTAT_DATA_UINT64); 4288 kstat_named_init(&isp->ehci_sts_periodic_sched_status, 4289 "Periodic sched status", KSTAT_DATA_UINT64); 4290 kstat_named_init(&isp->ehci_sts_empty_async_schedule, 4291 "Empty async schedule", KSTAT_DATA_UINT64); 4292 kstat_named_init(&isp->ehci_sts_host_ctrl_halted, 4293 "Host controller Halted", KSTAT_DATA_UINT64); 4294 kstat_named_init(&isp->ehci_sts_async_advance_intr, 4295 "Intr on async advance", KSTAT_DATA_UINT64); 4296 kstat_named_init(&isp->ehci_sts_host_system_error_intr, 4297 "Host system error", KSTAT_DATA_UINT64); 4298 kstat_named_init(&isp->ehci_sts_frm_list_rollover_intr, 4299 "Frame list rollover", KSTAT_DATA_UINT64); 4300 kstat_named_init(&isp->ehci_sts_rh_port_change_intr, 4301 "Port change detect", KSTAT_DATA_UINT64); 4302 kstat_named_init(&isp->ehci_sts_usb_error_intr, 4303 "USB error interrupt", KSTAT_DATA_UINT64); 4304 kstat_named_init(&isp->ehci_sts_usb_intr, 4305 "USB interrupt", KSTAT_DATA_UINT64); 4306 4307 EHCI_INTRS_STATS(ehcip)->ks_private = ehcip; 4308 EHCI_INTRS_STATS(ehcip)->ks_update = nulldev; 4309 kstat_install(EHCI_INTRS_STATS(ehcip)); 4310 } 4311 } 4312 4313 if (EHCI_TOTAL_STATS(ehcip) == NULL) { 4314 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,total", 4315 dname, instance); 4316 EHCI_TOTAL_STATS(ehcip) = kstat_create("usba", instance, 4317 kstatname, "usb_byte_count", KSTAT_TYPE_IO, 1, 4318 KSTAT_FLAG_PERSISTENT); 4319 4320 if (EHCI_TOTAL_STATS(ehcip)) { 4321 kstat_install(EHCI_TOTAL_STATS(ehcip)); 4322 } 4323 } 4324 4325 for (i = 0; i < USB_N_COUNT_KSTATS; i++) { 4326 if (ehcip->ehci_count_stats[i] == NULL) { 4327 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,%s", 4328 dname, instance, usbtypes[i]); 4329 ehcip->ehci_count_stats[i] = kstat_create("usba", 4330 instance, kstatname, "usb_byte_count", 4331 KSTAT_TYPE_IO, 1, KSTAT_FLAG_PERSISTENT); 4332 4333 if (ehcip->ehci_count_stats[i]) { 4334 kstat_install(ehcip->ehci_count_stats[i]); 4335 } 4336 } 4337 } 4338 } 4339 4340 4341 /* 4342 * ehci_destroy_stats: 4343 * 4344 * Clean up ehci kstat structures 4345 */ 4346 void 4347 ehci_destroy_stats(ehci_state_t *ehcip) 4348 { 4349 int i; 4350 4351 if (EHCI_INTRS_STATS(ehcip)) { 4352 kstat_delete(EHCI_INTRS_STATS(ehcip)); 4353 EHCI_INTRS_STATS(ehcip) = NULL; 4354 } 4355 4356 if (EHCI_TOTAL_STATS(ehcip)) { 4357 kstat_delete(EHCI_TOTAL_STATS(ehcip)); 4358 EHCI_TOTAL_STATS(ehcip) = NULL; 4359 } 4360 4361 for (i = 0; i < USB_N_COUNT_KSTATS; i++) { 4362 if (ehcip->ehci_count_stats[i]) { 4363 kstat_delete(ehcip->ehci_count_stats[i]); 4364 ehcip->ehci_count_stats[i] = NULL; 4365 } 4366 } 4367 } 4368 4369 4370 /* 4371 * ehci_do_intrs_stats: 4372 * 4373 * ehci status information 4374 */ 4375 void 4376 ehci_do_intrs_stats( 4377 ehci_state_t *ehcip, 4378 int val) 4379 { 4380 if (EHCI_INTRS_STATS(ehcip)) { 4381 EHCI_INTRS_STATS_DATA(ehcip)->ehci_sts_total.value.ui64++; 4382 switch (val) { 4383 case EHCI_STS_ASYNC_SCHED_STATUS: 4384 EHCI_INTRS_STATS_DATA(ehcip)-> 4385 ehci_sts_async_sched_status.value.ui64++; 4386 break; 4387 case EHCI_STS_PERIODIC_SCHED_STATUS: 4388 EHCI_INTRS_STATS_DATA(ehcip)-> 4389 ehci_sts_periodic_sched_status.value.ui64++; 4390 break; 4391 case EHCI_STS_EMPTY_ASYNC_SCHEDULE: 4392 EHCI_INTRS_STATS_DATA(ehcip)-> 4393 ehci_sts_empty_async_schedule.value.ui64++; 4394 break; 4395 case EHCI_STS_HOST_CTRL_HALTED: 4396 EHCI_INTRS_STATS_DATA(ehcip)-> 4397 ehci_sts_host_ctrl_halted.value.ui64++; 4398 break; 4399 case EHCI_STS_ASYNC_ADVANCE_INTR: 4400 EHCI_INTRS_STATS_DATA(ehcip)-> 4401 ehci_sts_async_advance_intr.value.ui64++; 4402 break; 4403 case EHCI_STS_HOST_SYSTEM_ERROR_INTR: 4404 EHCI_INTRS_STATS_DATA(ehcip)-> 4405 ehci_sts_host_system_error_intr.value.ui64++; 4406 break; 4407 case EHCI_STS_FRM_LIST_ROLLOVER_INTR: 4408 EHCI_INTRS_STATS_DATA(ehcip)-> 4409 ehci_sts_frm_list_rollover_intr.value.ui64++; 4410 break; 4411 case EHCI_STS_RH_PORT_CHANGE_INTR: 4412 EHCI_INTRS_STATS_DATA(ehcip)-> 4413 ehci_sts_rh_port_change_intr.value.ui64++; 4414 break; 4415 case EHCI_STS_USB_ERROR_INTR: 4416 EHCI_INTRS_STATS_DATA(ehcip)-> 4417 ehci_sts_usb_error_intr.value.ui64++; 4418 break; 4419 case EHCI_STS_USB_INTR: 4420 EHCI_INTRS_STATS_DATA(ehcip)-> 4421 ehci_sts_usb_intr.value.ui64++; 4422 break; 4423 default: 4424 EHCI_INTRS_STATS_DATA(ehcip)-> 4425 ehci_sts_not_claimed.value.ui64++; 4426 break; 4427 } 4428 } 4429 } 4430 4431 4432 /* 4433 * ehci_do_byte_stats: 4434 * 4435 * ehci data xfer information 4436 */ 4437 void 4438 ehci_do_byte_stats( 4439 ehci_state_t *ehcip, 4440 size_t len, 4441 uint8_t attr, 4442 uint8_t addr) 4443 { 4444 uint8_t type = attr & USB_EP_ATTR_MASK; 4445 uint8_t dir = addr & USB_EP_DIR_MASK; 4446 4447 if (dir == USB_EP_DIR_IN) { 4448 EHCI_TOTAL_STATS_DATA(ehcip)->reads++; 4449 EHCI_TOTAL_STATS_DATA(ehcip)->nread += len; 4450 switch (type) { 4451 case USB_EP_ATTR_CONTROL: 4452 EHCI_CTRL_STATS(ehcip)->reads++; 4453 EHCI_CTRL_STATS(ehcip)->nread += len; 4454 break; 4455 case USB_EP_ATTR_BULK: 4456 EHCI_BULK_STATS(ehcip)->reads++; 4457 EHCI_BULK_STATS(ehcip)->nread += len; 4458 break; 4459 case USB_EP_ATTR_INTR: 4460 EHCI_INTR_STATS(ehcip)->reads++; 4461 EHCI_INTR_STATS(ehcip)->nread += len; 4462 break; 4463 case USB_EP_ATTR_ISOCH: 4464 EHCI_ISOC_STATS(ehcip)->reads++; 4465 EHCI_ISOC_STATS(ehcip)->nread += len; 4466 break; 4467 } 4468 } else if (dir == USB_EP_DIR_OUT) { 4469 EHCI_TOTAL_STATS_DATA(ehcip)->writes++; 4470 EHCI_TOTAL_STATS_DATA(ehcip)->nwritten += len; 4471 switch (type) { 4472 case USB_EP_ATTR_CONTROL: 4473 EHCI_CTRL_STATS(ehcip)->writes++; 4474 EHCI_CTRL_STATS(ehcip)->nwritten += len; 4475 break; 4476 case USB_EP_ATTR_BULK: 4477 EHCI_BULK_STATS(ehcip)->writes++; 4478 EHCI_BULK_STATS(ehcip)->nwritten += len; 4479 break; 4480 case USB_EP_ATTR_INTR: 4481 EHCI_INTR_STATS(ehcip)->writes++; 4482 EHCI_INTR_STATS(ehcip)->nwritten += len; 4483 break; 4484 case USB_EP_ATTR_ISOCH: 4485 EHCI_ISOC_STATS(ehcip)->writes++; 4486 EHCI_ISOC_STATS(ehcip)->nwritten += len; 4487 break; 4488 } 4489 } 4490 } 4491