1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * EHCI Host Controller Driver (EHCI) 31 * 32 * The EHCI driver is a software driver which interfaces to the Universal 33 * Serial Bus layer (USBA) and the Host Controller (HC). The interface to 34 * the Host Controller is defined by the EHCI Host Controller Interface. 35 * 36 * This module contains the main EHCI driver code which handles all USB 37 * transfers, bandwidth allocations and other general functionalities. 38 */ 39 40 #include <sys/usb/hcd/ehci/ehcid.h> 41 #include <sys/usb/hcd/ehci/ehci_isoch.h> 42 #include <sys/usb/hcd/ehci/ehci_xfer.h> 43 44 /* 45 * EHCI MSI tunable: 46 * 47 * By default MSI is enabled on all supported platforms except for the 48 * EHCI controller of ULI1575 South bridge. 49 */ 50 boolean_t ehci_enable_msi = B_TRUE; 51 52 /* Pointer to the state structure */ 53 extern void *ehci_statep; 54 55 extern void ehci_handle_endpoint_reclaimation(ehci_state_t *); 56 57 extern uint_t ehci_vt62x2_workaround; 58 59 /* Adjustable variables for the size of the pools */ 60 int ehci_qh_pool_size = EHCI_QH_POOL_SIZE; 61 int ehci_qtd_pool_size = EHCI_QTD_POOL_SIZE; 62 63 /* 64 * Initialize the values which the order of 32ms intr qh are executed 65 * by the host controller in the lattice tree. 66 */ 67 static uchar_t ehci_index[EHCI_NUM_INTR_QH_LISTS] = 68 {0x00, 0x10, 0x08, 0x18, 69 0x04, 0x14, 0x0c, 0x1c, 70 0x02, 0x12, 0x0a, 0x1a, 71 0x06, 0x16, 0x0e, 0x1e, 72 0x01, 0x11, 0x09, 0x19, 73 0x05, 0x15, 0x0d, 0x1d, 74 0x03, 0x13, 0x0b, 0x1b, 75 0x07, 0x17, 0x0f, 0x1f}; 76 77 /* 78 * Initialize the values which are used to calculate start split mask 79 * for the low/full/high speed interrupt and isochronous endpoints. 80 */ 81 static uint_t ehci_start_split_mask[15] = { 82 /* 83 * For high/full/low speed usb devices. For high speed 84 * device with polling interval greater than or equal 85 * to 8us (125us). 86 */ 87 0x01, /* 00000001 */ 88 0x02, /* 00000010 */ 89 0x04, /* 00000100 */ 90 0x08, /* 00001000 */ 91 0x10, /* 00010000 */ 92 0x20, /* 00100000 */ 93 0x40, /* 01000000 */ 94 0x80, /* 10000000 */ 95 96 /* Only for high speed devices with polling interval 4us */ 97 0x11, /* 00010001 */ 98 0x22, /* 00100010 */ 99 0x44, /* 01000100 */ 100 0x88, /* 10001000 */ 101 102 /* Only for high speed devices with polling interval 2us */ 103 0x55, /* 01010101 */ 104 0xaa, /* 10101010 */ 105 106 /* Only for high speed devices with polling interval 1us */ 107 0xff /* 11111111 */ 108 }; 109 110 /* 111 * Initialize the values which are used to calculate complete split mask 112 * for the low/full speed interrupt and isochronous endpoints. 113 */ 114 static uint_t ehci_intr_complete_split_mask[7] = { 115 /* Only full/low speed devices */ 116 0x1c, /* 00011100 */ 117 0x38, /* 00111000 */ 118 0x70, /* 01110000 */ 119 0xe0, /* 11100000 */ 120 0x00, /* Need FSTN feature */ 121 0x00, /* Need FSTN feature */ 122 0x00 /* Need FSTN feature */ 123 }; 124 125 126 /* 127 * EHCI Internal Function Prototypes 128 */ 129 130 /* Host Controller Driver (HCD) initialization functions */ 131 void ehci_set_dma_attributes(ehci_state_t *ehcip); 132 int ehci_allocate_pools(ehci_state_t *ehcip); 133 void ehci_decode_ddi_dma_addr_bind_handle_result( 134 ehci_state_t *ehcip, 135 int result); 136 int ehci_map_regs(ehci_state_t *ehcip); 137 int ehci_register_intrs_and_init_mutex( 138 ehci_state_t *ehcip); 139 static int ehci_add_intrs(ehci_state_t *ehcip, 140 int intr_type); 141 int ehci_init_ctlr(ehci_state_t *ehcip); 142 static int ehci_take_control(ehci_state_t *ehcip); 143 static int ehci_init_periodic_frame_lst_table( 144 ehci_state_t *ehcip); 145 static void ehci_build_interrupt_lattice( 146 ehci_state_t *ehcip); 147 usba_hcdi_ops_t *ehci_alloc_hcdi_ops(ehci_state_t *ehcip); 148 149 /* Host Controller Driver (HCD) deinitialization functions */ 150 int ehci_cleanup(ehci_state_t *ehcip); 151 static void ehci_rem_intrs(ehci_state_t *ehcip); 152 int ehci_cpr_suspend(ehci_state_t *ehcip); 153 int ehci_cpr_resume(ehci_state_t *ehcip); 154 155 /* Bandwidth Allocation functions */ 156 int ehci_allocate_bandwidth(ehci_state_t *ehcip, 157 usba_pipe_handle_data_t *ph, 158 uint_t *pnode, 159 uchar_t *smask, 160 uchar_t *cmask); 161 static int ehci_allocate_high_speed_bandwidth( 162 ehci_state_t *ehcip, 163 usba_pipe_handle_data_t *ph, 164 uint_t *hnode, 165 uchar_t *smask, 166 uchar_t *cmask); 167 static int ehci_allocate_classic_tt_bandwidth( 168 ehci_state_t *ehcip, 169 usba_pipe_handle_data_t *ph, 170 uint_t pnode); 171 void ehci_deallocate_bandwidth(ehci_state_t *ehcip, 172 usba_pipe_handle_data_t *ph, 173 uint_t pnode, 174 uchar_t smask, 175 uchar_t cmask); 176 static void ehci_deallocate_high_speed_bandwidth( 177 ehci_state_t *ehcip, 178 usba_pipe_handle_data_t *ph, 179 uint_t hnode, 180 uchar_t smask, 181 uchar_t cmask); 182 static void ehci_deallocate_classic_tt_bandwidth( 183 ehci_state_t *ehcip, 184 usba_pipe_handle_data_t *ph, 185 uint_t pnode); 186 static int ehci_compute_high_speed_bandwidth( 187 ehci_state_t *ehcip, 188 usb_ep_descr_t *endpoint, 189 usb_port_status_t port_status, 190 uint_t *sbandwidth, 191 uint_t *cbandwidth); 192 static int ehci_compute_classic_bandwidth( 193 usb_ep_descr_t *endpoint, 194 usb_port_status_t port_status, 195 uint_t *bandwidth); 196 int ehci_adjust_polling_interval( 197 ehci_state_t *ehcip, 198 usb_ep_descr_t *endpoint, 199 usb_port_status_t port_status); 200 static int ehci_adjust_high_speed_polling_interval( 201 ehci_state_t *ehcip, 202 usb_ep_descr_t *endpoint); 203 static uint_t ehci_lattice_height(uint_t interval); 204 static uint_t ehci_lattice_parent(uint_t node); 205 static uint_t ehci_find_periodic_node( 206 uint_t leaf, 207 int interval); 208 static uint_t ehci_leftmost_leaf(uint_t node, 209 uint_t height); 210 static uint_t ehci_pow_2(uint_t x); 211 static uint_t ehci_log_2(uint_t x); 212 static int ehci_find_bestfit_hs_mask( 213 ehci_state_t *ehcip, 214 uchar_t *smask, 215 uint_t *pnode, 216 usb_ep_descr_t *endpoint, 217 uint_t bandwidth, 218 int interval); 219 static int ehci_find_bestfit_ls_intr_mask( 220 ehci_state_t *ehcip, 221 uchar_t *smask, 222 uchar_t *cmask, 223 uint_t *pnode, 224 uint_t sbandwidth, 225 uint_t cbandwidth, 226 int interval); 227 static int ehci_find_bestfit_sitd_in_mask( 228 ehci_state_t *ehcip, 229 uchar_t *smask, 230 uchar_t *cmask, 231 uint_t *pnode, 232 uint_t sbandwidth, 233 uint_t cbandwidth, 234 int interval); 235 static int ehci_find_bestfit_sitd_out_mask( 236 ehci_state_t *ehcip, 237 uchar_t *smask, 238 uint_t *pnode, 239 uint_t sbandwidth, 240 int interval); 241 static uint_t ehci_calculate_bw_availability_mask( 242 ehci_state_t *ehcip, 243 uint_t bandwidth, 244 int leaf, 245 int leaf_count, 246 uchar_t *bw_mask); 247 static void ehci_update_bw_availability( 248 ehci_state_t *ehcip, 249 int bandwidth, 250 int leftmost_leaf, 251 int leaf_count, 252 uchar_t mask); 253 254 /* Miscellaneous functions */ 255 ehci_state_t *ehci_obtain_state( 256 dev_info_t *dip); 257 int ehci_state_is_operational( 258 ehci_state_t *ehcip); 259 int ehci_do_soft_reset( 260 ehci_state_t *ehcip); 261 usb_req_attrs_t ehci_get_xfer_attrs(ehci_state_t *ehcip, 262 ehci_pipe_private_t *pp, 263 ehci_trans_wrapper_t *tw); 264 usb_frame_number_t ehci_get_current_frame_number( 265 ehci_state_t *ehcip); 266 static void ehci_cpr_cleanup( 267 ehci_state_t *ehcip); 268 int ehci_wait_for_sof( 269 ehci_state_t *ehcip); 270 void ehci_toggle_scheduler( 271 ehci_state_t *ehcip); 272 void ehci_print_caps(ehci_state_t *ehcip); 273 void ehci_print_regs(ehci_state_t *ehcip); 274 void ehci_print_qh(ehci_state_t *ehcip, 275 ehci_qh_t *qh); 276 void ehci_print_qtd(ehci_state_t *ehcip, 277 ehci_qtd_t *qtd); 278 void ehci_create_stats(ehci_state_t *ehcip); 279 void ehci_destroy_stats(ehci_state_t *ehcip); 280 void ehci_do_intrs_stats(ehci_state_t *ehcip, 281 int val); 282 void ehci_do_byte_stats(ehci_state_t *ehcip, 283 size_t len, 284 uint8_t attr, 285 uint8_t addr); 286 287 /* 288 * check if this ehci controller can support PM 289 */ 290 int 291 ehci_hcdi_pm_support(dev_info_t *dip) 292 { 293 ehci_state_t *ehcip = ddi_get_soft_state(ehci_statep, 294 ddi_get_instance(dip)); 295 296 if (((ehcip->ehci_vendor_id == PCI_VENDOR_NEC_COMBO) && 297 (ehcip->ehci_device_id == PCI_DEVICE_NEC_COMBO)) || 298 299 ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) && 300 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575)) || 301 302 (ehcip->ehci_vendor_id == PCI_VENDOR_VIA)) { 303 304 return (USB_SUCCESS); 305 } 306 307 return (USB_FAILURE); 308 } 309 310 311 /* 312 * Host Controller Driver (HCD) initialization functions 313 */ 314 315 /* 316 * ehci_set_dma_attributes: 317 * 318 * Set the limits in the DMA attributes structure. Most of the values used 319 * in the DMA limit structures are the default values as specified by the 320 * Writing PCI device drivers document. 321 */ 322 void 323 ehci_set_dma_attributes(ehci_state_t *ehcip) 324 { 325 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 326 "ehci_set_dma_attributes:"); 327 328 /* Initialize the DMA attributes */ 329 ehcip->ehci_dma_attr.dma_attr_version = DMA_ATTR_V0; 330 ehcip->ehci_dma_attr.dma_attr_addr_lo = 0x00000000ull; 331 ehcip->ehci_dma_attr.dma_attr_addr_hi = 0xfffffffeull; 332 333 /* 32 bit addressing */ 334 ehcip->ehci_dma_attr.dma_attr_count_max = EHCI_DMA_ATTR_COUNT_MAX; 335 336 /* Byte alignment */ 337 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 338 339 /* 340 * Since PCI specification is byte alignment, the 341 * burst size field should be set to 1 for PCI devices. 342 */ 343 ehcip->ehci_dma_attr.dma_attr_burstsizes = 0x1; 344 345 ehcip->ehci_dma_attr.dma_attr_minxfer = 0x1; 346 ehcip->ehci_dma_attr.dma_attr_maxxfer = EHCI_DMA_ATTR_MAX_XFER; 347 ehcip->ehci_dma_attr.dma_attr_seg = 0xffffffffull; 348 ehcip->ehci_dma_attr.dma_attr_sgllen = 1; 349 ehcip->ehci_dma_attr.dma_attr_granular = EHCI_DMA_ATTR_GRANULAR; 350 ehcip->ehci_dma_attr.dma_attr_flags = 0; 351 } 352 353 354 /* 355 * ehci_allocate_pools: 356 * 357 * Allocate the system memory for the Endpoint Descriptor (QH) and for the 358 * Transfer Descriptor (QTD) pools. Both QH and QTD structures must be aligned 359 * to a 16 byte boundary. 360 */ 361 int 362 ehci_allocate_pools(ehci_state_t *ehcip) 363 { 364 ddi_device_acc_attr_t dev_attr; 365 size_t real_length; 366 int result; 367 uint_t ccount; 368 int i; 369 370 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 371 "ehci_allocate_pools:"); 372 373 /* The host controller will be little endian */ 374 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 375 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 376 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 377 378 /* Byte alignment */ 379 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_TD_QH_ALIGNMENT; 380 381 /* Allocate the QTD pool DMA handle */ 382 if (ddi_dma_alloc_handle(ehcip->ehci_dip, &ehcip->ehci_dma_attr, 383 DDI_DMA_SLEEP, 0, 384 &ehcip->ehci_qtd_pool_dma_handle) != DDI_SUCCESS) { 385 386 goto failure; 387 } 388 389 /* Allocate the memory for the QTD pool */ 390 if (ddi_dma_mem_alloc(ehcip->ehci_qtd_pool_dma_handle, 391 ehci_qtd_pool_size * sizeof (ehci_qtd_t), 392 &dev_attr, 393 DDI_DMA_CONSISTENT, 394 DDI_DMA_SLEEP, 395 0, 396 (caddr_t *)&ehcip->ehci_qtd_pool_addr, 397 &real_length, 398 &ehcip->ehci_qtd_pool_mem_handle)) { 399 400 goto failure; 401 } 402 403 /* Map the QTD pool into the I/O address space */ 404 result = ddi_dma_addr_bind_handle( 405 ehcip->ehci_qtd_pool_dma_handle, 406 NULL, 407 (caddr_t)ehcip->ehci_qtd_pool_addr, 408 real_length, 409 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 410 DDI_DMA_SLEEP, 411 NULL, 412 &ehcip->ehci_qtd_pool_cookie, 413 &ccount); 414 415 bzero((void *)ehcip->ehci_qtd_pool_addr, 416 ehci_qtd_pool_size * sizeof (ehci_qtd_t)); 417 418 /* Process the result */ 419 if (result == DDI_DMA_MAPPED) { 420 /* The cookie count should be 1 */ 421 if (ccount != 1) { 422 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 423 "ehci_allocate_pools: More than 1 cookie"); 424 425 goto failure; 426 } 427 } else { 428 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 429 "ehci_allocate_pools: Result = %d", result); 430 431 ehci_decode_ddi_dma_addr_bind_handle_result(ehcip, result); 432 433 goto failure; 434 } 435 436 /* 437 * DMA addresses for QTD pools are bound 438 */ 439 ehcip->ehci_dma_addr_bind_flag |= EHCI_QTD_POOL_BOUND; 440 441 /* Initialize the QTD pool */ 442 for (i = 0; i < ehci_qtd_pool_size; i ++) { 443 Set_QTD(ehcip->ehci_qtd_pool_addr[i]. 444 qtd_state, EHCI_QTD_FREE); 445 } 446 447 /* Allocate the QTD pool DMA handle */ 448 if (ddi_dma_alloc_handle(ehcip->ehci_dip, 449 &ehcip->ehci_dma_attr, 450 DDI_DMA_SLEEP, 451 0, 452 &ehcip->ehci_qh_pool_dma_handle) != DDI_SUCCESS) { 453 454 goto failure; 455 } 456 457 /* Allocate the memory for the QH pool */ 458 if (ddi_dma_mem_alloc(ehcip->ehci_qh_pool_dma_handle, 459 ehci_qh_pool_size * sizeof (ehci_qh_t), 460 &dev_attr, 461 DDI_DMA_CONSISTENT, 462 DDI_DMA_SLEEP, 463 0, 464 (caddr_t *)&ehcip->ehci_qh_pool_addr, 465 &real_length, 466 &ehcip->ehci_qh_pool_mem_handle) != DDI_SUCCESS) { 467 468 goto failure; 469 } 470 471 result = ddi_dma_addr_bind_handle(ehcip->ehci_qh_pool_dma_handle, 472 NULL, 473 (caddr_t)ehcip->ehci_qh_pool_addr, 474 real_length, 475 DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 476 DDI_DMA_SLEEP, 477 NULL, 478 &ehcip->ehci_qh_pool_cookie, 479 &ccount); 480 481 bzero((void *)ehcip->ehci_qh_pool_addr, 482 ehci_qh_pool_size * sizeof (ehci_qh_t)); 483 484 /* Process the result */ 485 if (result == DDI_DMA_MAPPED) { 486 /* The cookie count should be 1 */ 487 if (ccount != 1) { 488 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 489 "ehci_allocate_pools: More than 1 cookie"); 490 491 goto failure; 492 } 493 } else { 494 ehci_decode_ddi_dma_addr_bind_handle_result(ehcip, result); 495 496 goto failure; 497 } 498 499 /* 500 * DMA addresses for QH pools are bound 501 */ 502 ehcip->ehci_dma_addr_bind_flag |= EHCI_QH_POOL_BOUND; 503 504 /* Initialize the QH pool */ 505 for (i = 0; i < ehci_qh_pool_size; i ++) { 506 Set_QH(ehcip->ehci_qh_pool_addr[i].qh_state, EHCI_QH_FREE); 507 } 508 509 /* Byte alignment */ 510 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 511 512 return (DDI_SUCCESS); 513 514 failure: 515 /* Byte alignment */ 516 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 517 518 return (DDI_FAILURE); 519 } 520 521 522 /* 523 * ehci_decode_ddi_dma_addr_bind_handle_result: 524 * 525 * Process the return values of ddi_dma_addr_bind_handle() 526 */ 527 void 528 ehci_decode_ddi_dma_addr_bind_handle_result( 529 ehci_state_t *ehcip, 530 int result) 531 { 532 USB_DPRINTF_L2(PRINT_MASK_ALLOC, ehcip->ehci_log_hdl, 533 "ehci_decode_ddi_dma_addr_bind_handle_result:"); 534 535 switch (result) { 536 case DDI_DMA_PARTIAL_MAP: 537 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 538 "Partial transfers not allowed"); 539 break; 540 case DDI_DMA_INUSE: 541 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 542 "Handle is in use"); 543 break; 544 case DDI_DMA_NORESOURCES: 545 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 546 "No resources"); 547 break; 548 case DDI_DMA_NOMAPPING: 549 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 550 "No mapping"); 551 break; 552 case DDI_DMA_TOOBIG: 553 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 554 "Object is too big"); 555 break; 556 default: 557 USB_DPRINTF_L2(PRINT_MASK_ALL, ehcip->ehci_log_hdl, 558 "Unknown dma error"); 559 } 560 } 561 562 563 /* 564 * ehci_map_regs: 565 * 566 * The Host Controller (HC) contains a set of on-chip operational registers 567 * and which should be mapped into a non-cacheable portion of the system 568 * addressable space. 569 */ 570 int 571 ehci_map_regs(ehci_state_t *ehcip) 572 { 573 ddi_device_acc_attr_t attr; 574 uint16_t cmd_reg; 575 uint_t length; 576 577 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, "ehci_map_regs:"); 578 579 /* Check to make sure we have memory access */ 580 if (pci_config_setup(ehcip->ehci_dip, 581 &ehcip->ehci_config_handle) != DDI_SUCCESS) { 582 583 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 584 "ehci_map_regs: Config error"); 585 586 return (DDI_FAILURE); 587 } 588 589 /* Make sure Memory Access Enable is set */ 590 cmd_reg = pci_config_get16(ehcip->ehci_config_handle, PCI_CONF_COMM); 591 592 if (!(cmd_reg & PCI_COMM_MAE)) { 593 594 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 595 "ehci_map_regs: Memory base address access disabled"); 596 597 return (DDI_FAILURE); 598 } 599 600 /* The host controller will be little endian */ 601 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 602 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 603 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 604 605 /* Map in EHCI Capability registers */ 606 if (ddi_regs_map_setup(ehcip->ehci_dip, 1, 607 (caddr_t *)&ehcip->ehci_capsp, 0, 608 sizeof (ehci_caps_t), &attr, 609 &ehcip->ehci_caps_handle) != DDI_SUCCESS) { 610 611 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 612 "ehci_map_regs: Map setup error"); 613 614 return (DDI_FAILURE); 615 } 616 617 length = ddi_get8(ehcip->ehci_caps_handle, 618 (uint8_t *)&ehcip->ehci_capsp->ehci_caps_length); 619 620 /* Free the original mapping */ 621 ddi_regs_map_free(&ehcip->ehci_caps_handle); 622 623 /* Re-map in EHCI Capability and Operational registers */ 624 if (ddi_regs_map_setup(ehcip->ehci_dip, 1, 625 (caddr_t *)&ehcip->ehci_capsp, 0, 626 length + sizeof (ehci_regs_t), &attr, 627 &ehcip->ehci_caps_handle) != DDI_SUCCESS) { 628 629 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 630 "ehci_map_regs: Map setup error"); 631 632 return (DDI_FAILURE); 633 } 634 635 /* Get the pointer to EHCI Operational Register */ 636 ehcip->ehci_regsp = (ehci_regs_t *) 637 ((uintptr_t)ehcip->ehci_capsp + length); 638 639 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 640 "ehci_map_regs: Capsp 0x%p Regsp 0x%p\n", 641 ehcip->ehci_capsp, ehcip->ehci_regsp); 642 643 return (DDI_SUCCESS); 644 } 645 646 647 /* 648 * ehci_register_intrs_and_init_mutex: 649 * 650 * Register interrupts and initialize each mutex and condition variables 651 */ 652 int 653 ehci_register_intrs_and_init_mutex(ehci_state_t *ehcip) 654 { 655 int intr_types; 656 657 #if defined(__x86) 658 uint8_t iline; 659 #endif 660 661 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 662 "ehci_register_intrs_and_init_mutex:"); 663 664 /* 665 * There is a known MSI hardware bug with the EHCI controller 666 * of ULI1575 southbridge. Hence MSI is disabled for this chip. 667 */ 668 if ((ehcip->ehci_vendor_id == PCI_VENDOR_ULi_M1575) && 669 (ehcip->ehci_device_id == PCI_DEVICE_ULi_M1575)) { 670 ehcip->ehci_msi_enabled = B_FALSE; 671 } else { 672 /* Set the MSI enable flag from the global EHCI MSI tunable */ 673 ehcip->ehci_msi_enabled = ehci_enable_msi; 674 } 675 676 #if defined(__x86) 677 /* 678 * Make sure that the interrupt pin is connected to the 679 * interrupt controller on x86. Interrupt line 255 means 680 * "unknown" or "not connected" (PCI spec 6.2.4, footnote 43). 681 * If we would return failure when interrupt line equals 255, then 682 * high speed devices will be routed to companion host controllers. 683 * However, it is not necessary to return failure here, and 684 * o/uhci codes don't check the interrupt line either. 685 * But it's good to log a message here for debug purposes. 686 */ 687 iline = pci_config_get8(ehcip->ehci_config_handle, 688 PCI_CONF_ILINE); 689 690 if (iline == 255) { 691 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 692 "ehci_register_intrs_and_init_mutex: " 693 "interrupt line value out of range (%d)", 694 iline); 695 } 696 #endif /* __x86 */ 697 698 /* Get supported interrupt types */ 699 if (ddi_intr_get_supported_types(ehcip->ehci_dip, 700 &intr_types) != DDI_SUCCESS) { 701 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 702 "ehci_register_intrs_and_init_mutex: " 703 "ddi_intr_get_supported_types failed"); 704 705 return (DDI_FAILURE); 706 } 707 708 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 709 "ehci_register_intrs_and_init_mutex: " 710 "supported interrupt types 0x%x", intr_types); 711 712 if ((intr_types & DDI_INTR_TYPE_MSI) && ehcip->ehci_msi_enabled) { 713 if (ehci_add_intrs(ehcip, DDI_INTR_TYPE_MSI) 714 != DDI_SUCCESS) { 715 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 716 "ehci_register_intrs_and_init_mutex: MSI " 717 "registration failed, trying FIXED interrupt \n"); 718 } else { 719 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 720 "ehci_register_intrs_and_init_mutex: " 721 "Using MSI interrupt type\n"); 722 723 ehcip->ehci_intr_type = DDI_INTR_TYPE_MSI; 724 ehcip->ehci_flags |= EHCI_INTR; 725 } 726 } 727 728 if ((!(ehcip->ehci_flags & EHCI_INTR)) && 729 (intr_types & DDI_INTR_TYPE_FIXED)) { 730 if (ehci_add_intrs(ehcip, DDI_INTR_TYPE_FIXED) 731 != DDI_SUCCESS) { 732 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 733 "ehci_register_intrs_and_init_mutex: " 734 "FIXED interrupt registration failed\n"); 735 736 return (DDI_FAILURE); 737 } 738 739 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 740 "ehci_register_intrs_and_init_mutex: " 741 "Using FIXED interrupt type\n"); 742 743 ehcip->ehci_intr_type = DDI_INTR_TYPE_FIXED; 744 ehcip->ehci_flags |= EHCI_INTR; 745 } 746 747 /* Create prototype for advance on async schedule */ 748 cv_init(&ehcip->ehci_async_schedule_advance_cv, 749 NULL, CV_DRIVER, NULL); 750 751 return (DDI_SUCCESS); 752 } 753 754 755 /* 756 * ehci_add_intrs: 757 * 758 * Register FIXED or MSI interrupts. 759 */ 760 static int 761 ehci_add_intrs(ehci_state_t *ehcip, 762 int intr_type) 763 { 764 int actual, avail, intr_size, count = 0; 765 int i, flag, ret; 766 767 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 768 "ehci_add_intrs: interrupt type 0x%x", intr_type); 769 770 /* Get number of interrupts */ 771 ret = ddi_intr_get_nintrs(ehcip->ehci_dip, intr_type, &count); 772 if ((ret != DDI_SUCCESS) || (count == 0)) { 773 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 774 "ehci_add_intrs: ddi_intr_get_nintrs() failure, " 775 "ret: %d, count: %d", ret, count); 776 777 return (DDI_FAILURE); 778 } 779 780 /* Get number of available interrupts */ 781 ret = ddi_intr_get_navail(ehcip->ehci_dip, intr_type, &avail); 782 if ((ret != DDI_SUCCESS) || (avail == 0)) { 783 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 784 "ehci_add_intrs: ddi_intr_get_navail() failure, " 785 "ret: %d, count: %d", ret, count); 786 787 return (DDI_FAILURE); 788 } 789 790 if (avail < count) { 791 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 792 "ehci_add_intrs: ehci_add_intrs: nintrs () " 793 "returned %d, navail returned %d\n", count, avail); 794 } 795 796 /* Allocate an array of interrupt handles */ 797 intr_size = count * sizeof (ddi_intr_handle_t); 798 ehcip->ehci_htable = kmem_zalloc(intr_size, KM_SLEEP); 799 800 flag = (intr_type == DDI_INTR_TYPE_MSI) ? 801 DDI_INTR_ALLOC_STRICT:DDI_INTR_ALLOC_NORMAL; 802 803 /* call ddi_intr_alloc() */ 804 ret = ddi_intr_alloc(ehcip->ehci_dip, ehcip->ehci_htable, 805 intr_type, 0, count, &actual, flag); 806 807 if ((ret != DDI_SUCCESS) || (actual == 0)) { 808 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 809 "ehci_add_intrs: ddi_intr_alloc() failed %d", ret); 810 811 kmem_free(ehcip->ehci_htable, intr_size); 812 813 return (DDI_FAILURE); 814 } 815 816 if (actual < count) { 817 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 818 "ehci_add_intrs: Requested: %d, Received: %d\n", 819 count, actual); 820 821 for (i = 0; i < actual; i++) 822 (void) ddi_intr_free(ehcip->ehci_htable[i]); 823 824 kmem_free(ehcip->ehci_htable, intr_size); 825 826 return (DDI_FAILURE); 827 } 828 829 ehcip->ehci_intr_cnt = actual; 830 831 if ((ret = ddi_intr_get_pri(ehcip->ehci_htable[0], 832 &ehcip->ehci_intr_pri)) != DDI_SUCCESS) { 833 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 834 "ehci_add_intrs: ddi_intr_get_pri() failed %d", ret); 835 836 for (i = 0; i < actual; i++) 837 (void) ddi_intr_free(ehcip->ehci_htable[i]); 838 839 kmem_free(ehcip->ehci_htable, intr_size); 840 841 return (DDI_FAILURE); 842 } 843 844 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 845 "ehci_add_intrs: Supported Interrupt priority 0x%x", 846 ehcip->ehci_intr_pri); 847 848 /* Test for high level mutex */ 849 if (ehcip->ehci_intr_pri >= ddi_intr_get_hilevel_pri()) { 850 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 851 "ehci_add_intrs: Hi level interrupt not supported"); 852 853 for (i = 0; i < actual; i++) 854 (void) ddi_intr_free(ehcip->ehci_htable[i]); 855 856 kmem_free(ehcip->ehci_htable, intr_size); 857 858 return (DDI_FAILURE); 859 } 860 861 /* Initialize the mutex */ 862 mutex_init(&ehcip->ehci_int_mutex, NULL, MUTEX_DRIVER, 863 DDI_INTR_PRI(ehcip->ehci_intr_pri)); 864 865 /* Call ddi_intr_add_handler() */ 866 for (i = 0; i < actual; i++) { 867 if ((ret = ddi_intr_add_handler(ehcip->ehci_htable[i], 868 ehci_intr, (caddr_t)ehcip, 869 (caddr_t)(uintptr_t)i)) != DDI_SUCCESS) { 870 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 871 "ehci_add_intrs:ddi_intr_add_handler() " 872 "failed %d", ret); 873 874 for (i = 0; i < actual; i++) 875 (void) ddi_intr_free(ehcip->ehci_htable[i]); 876 877 mutex_destroy(&ehcip->ehci_int_mutex); 878 kmem_free(ehcip->ehci_htable, intr_size); 879 880 return (DDI_FAILURE); 881 } 882 } 883 884 if ((ret = ddi_intr_get_cap(ehcip->ehci_htable[0], 885 &ehcip->ehci_intr_cap)) != DDI_SUCCESS) { 886 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 887 "ehci_add_intrs: ddi_intr_get_cap() failed %d", ret); 888 889 for (i = 0; i < actual; i++) { 890 (void) ddi_intr_remove_handler(ehcip->ehci_htable[i]); 891 (void) ddi_intr_free(ehcip->ehci_htable[i]); 892 } 893 894 mutex_destroy(&ehcip->ehci_int_mutex); 895 kmem_free(ehcip->ehci_htable, intr_size); 896 897 return (DDI_FAILURE); 898 } 899 900 /* Enable all interrupts */ 901 if (ehcip->ehci_intr_cap & DDI_INTR_FLAG_BLOCK) { 902 /* Call ddi_intr_block_enable() for MSI interrupts */ 903 (void) ddi_intr_block_enable(ehcip->ehci_htable, 904 ehcip->ehci_intr_cnt); 905 } else { 906 /* Call ddi_intr_enable for MSI or FIXED interrupts */ 907 for (i = 0; i < ehcip->ehci_intr_cnt; i++) 908 (void) ddi_intr_enable(ehcip->ehci_htable[i]); 909 } 910 911 return (DDI_SUCCESS); 912 } 913 914 915 /* 916 * ehci_init_ctlr: 917 * 918 * Initialize the Host Controller (HC). 919 */ 920 int 921 ehci_init_ctlr(ehci_state_t *ehcip) 922 { 923 int revision; 924 uint16_t cmd_reg; 925 clock_t sof_time_wait; 926 int abort_on_BIOS_take_over_failure; 927 928 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, "ehci_init_ctlr:"); 929 930 /* Take control from the BIOS */ 931 if (ehci_take_control(ehcip) != USB_SUCCESS) { 932 933 /* read .conf file properties */ 934 abort_on_BIOS_take_over_failure = 935 ddi_prop_get_int(DDI_DEV_T_ANY, 936 ehcip->ehci_dip, DDI_PROP_DONTPASS, 937 "abort-on-BIOS-take-over-failure", 0); 938 939 if (abort_on_BIOS_take_over_failure) { 940 941 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 942 "Unable to take control from BIOS."); 943 944 return (DDI_FAILURE); 945 } 946 947 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 948 "Unable to take control from BIOS. Failure is ignored."); 949 } 950 951 /* set Memory Master Enable */ 952 cmd_reg = pci_config_get16(ehcip->ehci_config_handle, PCI_CONF_COMM); 953 cmd_reg |= (PCI_COMM_MAE | PCI_COMM_ME); 954 pci_config_put16(ehcip->ehci_config_handle, PCI_CONF_COMM, cmd_reg); 955 956 /* Reset the EHCI host controller */ 957 Set_OpReg(ehci_command, 958 Get_OpReg(ehci_command) | EHCI_CMD_HOST_CTRL_RESET); 959 960 /* Wait 10ms for reset to complete */ 961 drv_usecwait(EHCI_RESET_TIMEWAIT); 962 963 ASSERT(Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED); 964 965 /* Verify the version number */ 966 revision = Get_16Cap(ehci_version); 967 968 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 969 "ehci_init_ctlr: Revision 0x%x", revision); 970 971 /* 972 * EHCI driver supports EHCI host controllers compliant to 973 * 0.95 and higher revisions of EHCI specifications. 974 */ 975 if (revision < EHCI_REVISION_0_95) { 976 977 USB_DPRINTF_L0(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 978 "Revision 0x%x is not supported", revision); 979 980 return (DDI_FAILURE); 981 } 982 983 if (ehcip->ehci_hc_soft_state == EHCI_CTLR_INIT_STATE) { 984 985 /* Initialize the Frame list base address area */ 986 if (ehci_init_periodic_frame_lst_table(ehcip) != DDI_SUCCESS) { 987 988 return (DDI_FAILURE); 989 } 990 991 /* 992 * For performance reasons, do not insert anything into the 993 * asynchronous list or activate the asynch list schedule until 994 * there is a valid QH. 995 */ 996 ehcip->ehci_head_of_async_sched_list = NULL; 997 998 if ((ehcip->ehci_vendor_id == PCI_VENDOR_VIA) && 999 (ehci_vt62x2_workaround & EHCI_VIA_ASYNC_SCHEDULE)) { 1000 /* 1001 * The driver is unable to reliably stop the asynch 1002 * list schedule on VIA VT6202 controllers, so we 1003 * always keep a dummy QH on the list. 1004 */ 1005 ehci_qh_t *dummy_async_qh = 1006 ehci_alloc_qh(ehcip, NULL, NULL); 1007 1008 Set_QH(dummy_async_qh->qh_link_ptr, 1009 ((ehci_qh_cpu_to_iommu(ehcip, dummy_async_qh) & 1010 EHCI_QH_LINK_PTR) | EHCI_QH_LINK_REF_QH)); 1011 1012 /* Set this QH to be the "head" of the circular list */ 1013 Set_QH(dummy_async_qh->qh_ctrl, 1014 Get_QH(dummy_async_qh->qh_ctrl) | 1015 EHCI_QH_CTRL_RECLAIM_HEAD); 1016 1017 Set_QH(dummy_async_qh->qh_next_qtd, 1018 EHCI_QH_NEXT_QTD_PTR_VALID); 1019 Set_QH(dummy_async_qh->qh_alt_next_qtd, 1020 EHCI_QH_ALT_NEXT_QTD_PTR_VALID); 1021 1022 ehcip->ehci_head_of_async_sched_list = dummy_async_qh; 1023 ehcip->ehci_open_async_count++; 1024 } 1025 } 1026 1027 /* 1028 * Check for Asynchronous schedule park capability feature. If this 1029 * feature is supported, then, program ehci command register with 1030 * appropriate values.. 1031 */ 1032 if (Get_Cap(ehci_hcc_params) & EHCI_HCC_ASYNC_SCHED_PARK_CAP) { 1033 1034 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1035 "ehci_init_ctlr: Async park mode is supported"); 1036 1037 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) | 1038 (EHCI_CMD_ASYNC_PARK_ENABLE | 1039 EHCI_CMD_ASYNC_PARK_COUNT_3))); 1040 } 1041 1042 /* 1043 * Check for programmable periodic frame list feature. If this 1044 * feature is supported, then, program ehci command register with 1045 * 1024 frame list value. 1046 */ 1047 if (Get_Cap(ehci_hcc_params) & EHCI_HCC_PROG_FRAME_LIST_FLAG) { 1048 1049 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1050 "ehci_init_ctlr: Variable programmable periodic " 1051 "frame list is supported"); 1052 1053 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) | 1054 EHCI_CMD_FRAME_1024_SIZE)); 1055 } 1056 1057 /* 1058 * Currently EHCI driver doesn't support 64 bit addressing. 1059 * 1060 * If we are using 64 bit addressing capability, then, program 1061 * ehci_ctrl_segment register with 4 Gigabyte segment where all 1062 * of the interface data structures are allocated. 1063 */ 1064 if (Get_Cap(ehci_hcc_params) & EHCI_HCC_64BIT_ADDR_CAP) { 1065 1066 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1067 "ehci_init_ctlr: EHCI driver doesn't support " 1068 "64 bit addressing"); 1069 } 1070 1071 /* 64 bit addressing is not support */ 1072 Set_OpReg(ehci_ctrl_segment, 0x00000000); 1073 1074 /* Turn on/off the schedulers */ 1075 ehci_toggle_scheduler(ehcip); 1076 1077 /* 1078 * Set the Periodic Frame List Base Address register with the 1079 * starting physical address of the Periodic Frame List. 1080 */ 1081 Set_OpReg(ehci_periodic_list_base, 1082 (uint32_t)(ehcip->ehci_pflt_cookie.dmac_address & 0xFFFFF000)); 1083 1084 /* 1085 * Set ehci_interrupt to enable all interrupts except Root 1086 * Hub Status change interrupt. 1087 */ 1088 Set_OpReg(ehci_interrupt, EHCI_INTR_HOST_SYSTEM_ERROR | 1089 EHCI_INTR_FRAME_LIST_ROLLOVER | EHCI_INTR_USB_ERROR | 1090 EHCI_INTR_USB); 1091 1092 /* 1093 * Set the desired interrupt threshold and turn on EHCI host controller. 1094 */ 1095 Set_OpReg(ehci_command, 1096 ((Get_OpReg(ehci_command) & ~EHCI_CMD_INTR_THRESHOLD) | 1097 (EHCI_CMD_01_INTR | EHCI_CMD_HOST_CTRL_RUN))); 1098 1099 ASSERT(Get_OpReg(ehci_command) & EHCI_CMD_HOST_CTRL_RUN); 1100 1101 /* 1102 * Acer Labs Inc. M5273 EHCI controller does not send 1103 * interrupts unless the Root hub ports are routed to the EHCI 1104 * host controller; so route the ports now, before we test for 1105 * the presence of SOFs interrupts. 1106 */ 1107 if (ehcip->ehci_vendor_id == PCI_VENDOR_ALI) { 1108 /* Route all Root hub ports to EHCI host controller */ 1109 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_EHCI); 1110 } 1111 1112 /* 1113 * VIA chips have some issues and may not work reliably. 1114 * Revisions >= 0x80 are part of a southbridge and appear 1115 * to be reliable with the workaround. 1116 * For revisions < 0x80, if we were bound using class 1117 * complain, else proceed. This will allow the user to 1118 * bind ehci specifically to this chip and not have the 1119 * warnings 1120 */ 1121 if (ehcip->ehci_vendor_id == PCI_VENDOR_VIA) { 1122 1123 if (ehcip->ehci_rev_id >= PCI_VIA_REVISION_6212) { 1124 1125 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1126 "ehci_init_ctlr: Applying VIA workarounds for " 1127 "the 6212 chip."); 1128 1129 } else if (strcmp(DEVI(ehcip->ehci_dip)->devi_binding_name, 1130 "pciclass,0c0320") == 0) { 1131 1132 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1133 "Due to recently discovered incompatibilities"); 1134 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1135 "with this USB controller, USB2.x transfer"); 1136 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1137 "support has been disabled. This device will"); 1138 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1139 "continue to function as a USB1.x controller."); 1140 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1141 "If you are interested in enabling USB2.x"); 1142 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1143 "support please, refer to the ehci(7D) man page."); 1144 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1145 "Please also refer to www.sun.com/io for"); 1146 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1147 "Solaris Ready products and to"); 1148 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1149 "www.sun.com/bigadmin/hcl for additional"); 1150 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1151 "compatible USB products."); 1152 1153 return (DDI_FAILURE); 1154 1155 } else if (ehci_vt62x2_workaround) { 1156 1157 USB_DPRINTF_L1(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1158 "Applying VIA workarounds"); 1159 } 1160 } 1161 1162 /* 1163 * Get the number of clock ticks to wait. 1164 * This is based on the maximum time it takes for a frame list rollover 1165 * and maximum time wait for SOFs to begin. 1166 */ 1167 sof_time_wait = drv_usectohz((EHCI_NUM_PERIODIC_FRAME_LISTS * 1000) + 1168 EHCI_SOF_TIMEWAIT); 1169 1170 /* Tell the ISR to broadcast ehci_async_schedule_advance_cv */ 1171 ehcip->ehci_flags |= EHCI_CV_INTR; 1172 1173 /* We need to add a delay to allow the chip time to start running */ 1174 (void) cv_timedwait(&ehcip->ehci_async_schedule_advance_cv, 1175 &ehcip->ehci_int_mutex, ddi_get_lbolt() + sof_time_wait); 1176 1177 /* 1178 * Check EHCI host controller is running, otherwise return failure. 1179 */ 1180 if ((ehcip->ehci_flags & EHCI_CV_INTR) || 1181 (Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED)) { 1182 1183 USB_DPRINTF_L0(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1184 "No SOF interrupts have been received, this USB EHCI host" 1185 "controller is unusable"); 1186 1187 /* 1188 * Route all Root hub ports to Classic host 1189 * controller, in case this is an unusable ALI M5273 1190 * EHCI controller. 1191 */ 1192 if (ehcip->ehci_vendor_id == PCI_VENDOR_ALI) { 1193 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_CLASSIC); 1194 } 1195 1196 return (DDI_FAILURE); 1197 } 1198 1199 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1200 "ehci_init_ctlr: SOF's have started"); 1201 1202 /* Route all Root hub ports to EHCI host controller */ 1203 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_EHCI); 1204 1205 /* Set host controller soft state to operational */ 1206 ehcip->ehci_hc_soft_state = EHCI_CTLR_OPERATIONAL_STATE; 1207 1208 return (DDI_SUCCESS); 1209 } 1210 1211 /* 1212 * ehci_take_control: 1213 * 1214 * Handshake to take EHCI control from BIOS if necessary. Its only valid for 1215 * x86 machines, because sparc doesn't have a BIOS. 1216 * On x86 machine, the take control process includes 1217 * o get the base address of the extended capability list 1218 * o find out the capability for handoff synchronization in the list. 1219 * o check if BIOS has owned the host controller. 1220 * o set the OS Owned semaphore bit, ask the BIOS to release the ownership. 1221 * o wait for a constant time and check if BIOS has relinquished control. 1222 */ 1223 /* ARGSUSED */ 1224 static int 1225 ehci_take_control(ehci_state_t *ehcip) 1226 { 1227 #if defined(__x86) 1228 uint32_t extended_cap; 1229 uint32_t extended_cap_offset; 1230 uint32_t extended_cap_id; 1231 uint_t retry; 1232 1233 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1234 "ehci_take_control:"); 1235 1236 /* 1237 * According EHCI Spec 2.2.4, get EECP base address from HCCPARAMS 1238 * register. 1239 */ 1240 extended_cap_offset = (Get_Cap(ehci_hcc_params) & EHCI_HCC_EECP) >> 1241 EHCI_HCC_EECP_SHIFT; 1242 1243 /* 1244 * According EHCI Spec 2.2.4, if the extended capability offset is 1245 * less than 40h then its not valid. This means we don't need to 1246 * worry about BIOS handoff. 1247 */ 1248 if (extended_cap_offset < EHCI_HCC_EECP_MIN_OFFSET) { 1249 1250 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1251 "ehci_take_control: Hardware doesn't support legacy."); 1252 1253 goto success; 1254 } 1255 1256 /* 1257 * According EHCI Spec 2.1.7, A zero offset indicates the 1258 * end of the extended capability list. 1259 */ 1260 while (extended_cap_offset) { 1261 1262 /* Get the extended capability value. */ 1263 extended_cap = pci_config_get32(ehcip->ehci_config_handle, 1264 extended_cap_offset); 1265 1266 /* Get the capability ID */ 1267 extended_cap_id = (extended_cap & EHCI_EX_CAP_ID) >> 1268 EHCI_EX_CAP_ID_SHIFT; 1269 1270 /* Check if the card support legacy */ 1271 if (extended_cap_id == EHCI_EX_CAP_ID_BIOS_HANDOFF) { 1272 break; 1273 } 1274 1275 /* Get the offset of the next capability */ 1276 extended_cap_offset = (extended_cap & EHCI_EX_CAP_NEXT_PTR) >> 1277 EHCI_EX_CAP_NEXT_PTR_SHIFT; 1278 } 1279 1280 /* 1281 * Unable to find legacy support in hardware's extended capability list. 1282 * This means we don't need to worry about BIOS handoff. 1283 */ 1284 if (extended_cap_id != EHCI_EX_CAP_ID_BIOS_HANDOFF) { 1285 1286 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1287 "ehci_take_control: Hardware doesn't support legacy"); 1288 1289 goto success; 1290 } 1291 1292 /* Check if BIOS has owned it. */ 1293 if (!(extended_cap & EHCI_LEGSUP_BIOS_OWNED_SEM)) { 1294 1295 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1296 "ehci_take_control: BIOS does not own EHCI"); 1297 1298 goto success; 1299 } 1300 1301 /* 1302 * According EHCI Spec 5.1, The OS driver initiates an ownership 1303 * request by setting the OS Owned semaphore to a one. The OS 1304 * waits for the BIOS Owned bit to go to a zero before attempting 1305 * to use the EHCI controller. The time that OS must wait for BIOS 1306 * to respond to the request for ownership is beyond the scope of 1307 * this specification. 1308 * It waits up to EHCI_TAKEOVER_WAIT_COUNT*EHCI_TAKEOVER_DELAY ms 1309 * for BIOS to release the ownership. 1310 */ 1311 extended_cap |= EHCI_LEGSUP_OS_OWNED_SEM; 1312 pci_config_put32(ehcip->ehci_config_handle, extended_cap_offset, 1313 extended_cap); 1314 1315 for (retry = 0; retry < EHCI_TAKEOVER_WAIT_COUNT; retry++) { 1316 1317 /* wait a special interval */ 1318 delay(drv_usectohz(EHCI_TAKEOVER_DELAY)); 1319 1320 /* Check to see if the BIOS has released the ownership */ 1321 extended_cap = pci_config_get32( 1322 ehcip->ehci_config_handle, extended_cap_offset); 1323 1324 if (!(extended_cap & EHCI_LEGSUP_BIOS_OWNED_SEM)) { 1325 1326 USB_DPRINTF_L3(PRINT_MASK_ATTA, 1327 ehcip->ehci_log_hdl, 1328 "ehci_take_control: BIOS has released " 1329 "the ownership. retry = %d", retry); 1330 1331 goto success; 1332 } 1333 1334 } 1335 1336 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1337 "ehci_take_control: take control from BIOS failed."); 1338 1339 return (USB_FAILURE); 1340 1341 success: 1342 1343 #endif /* __x86 */ 1344 return (USB_SUCCESS); 1345 } 1346 1347 1348 /* 1349 * ehci_init_periodic_frame_list_table : 1350 * 1351 * Allocate the system memory and initialize Host Controller 1352 * Periodic Frame List table area. The starting of the Periodic 1353 * Frame List Table area must be 4096 byte aligned. 1354 */ 1355 static int 1356 ehci_init_periodic_frame_lst_table(ehci_state_t *ehcip) 1357 { 1358 ddi_device_acc_attr_t dev_attr; 1359 size_t real_length; 1360 uint_t ccount; 1361 int result; 1362 1363 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 1364 1365 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1366 "ehci_init_periodic_frame_lst_table:"); 1367 1368 /* The host controller will be little endian */ 1369 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 1370 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 1371 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1372 1373 /* Force the required 4K restrictive alignment */ 1374 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_PFL_ALIGNMENT; 1375 1376 /* Create space for the Periodic Frame List */ 1377 if (ddi_dma_alloc_handle(ehcip->ehci_dip, &ehcip->ehci_dma_attr, 1378 DDI_DMA_SLEEP, 0, &ehcip->ehci_pflt_dma_handle) != DDI_SUCCESS) { 1379 1380 goto failure; 1381 } 1382 1383 if (ddi_dma_mem_alloc(ehcip->ehci_pflt_dma_handle, 1384 sizeof (ehci_periodic_frame_list_t), 1385 &dev_attr, DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, 1386 0, (caddr_t *)&ehcip->ehci_periodic_frame_list_tablep, 1387 &real_length, &ehcip->ehci_pflt_mem_handle)) { 1388 1389 goto failure; 1390 } 1391 1392 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1393 "ehci_init_periodic_frame_lst_table: " 1394 "Real length %lu", real_length); 1395 1396 /* Map the whole Periodic Frame List into the I/O address space */ 1397 result = ddi_dma_addr_bind_handle(ehcip->ehci_pflt_dma_handle, 1398 NULL, (caddr_t)ehcip->ehci_periodic_frame_list_tablep, 1399 real_length, DDI_DMA_RDWR | DDI_DMA_CONSISTENT, 1400 DDI_DMA_SLEEP, NULL, &ehcip->ehci_pflt_cookie, &ccount); 1401 1402 if (result == DDI_DMA_MAPPED) { 1403 /* The cookie count should be 1 */ 1404 if (ccount != 1) { 1405 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1406 "ehci_init_periodic_frame_lst_table: " 1407 "More than 1 cookie"); 1408 1409 goto failure; 1410 } 1411 } else { 1412 ehci_decode_ddi_dma_addr_bind_handle_result(ehcip, result); 1413 1414 goto failure; 1415 } 1416 1417 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1418 "ehci_init_periodic_frame_lst_table: virtual 0x%p physical 0x%x", 1419 (void *)ehcip->ehci_periodic_frame_list_tablep, 1420 ehcip->ehci_pflt_cookie.dmac_address); 1421 1422 /* 1423 * DMA addresses for Periodic Frame List are bound. 1424 */ 1425 ehcip->ehci_dma_addr_bind_flag |= EHCI_PFLT_DMA_BOUND; 1426 1427 bzero((void *)ehcip->ehci_periodic_frame_list_tablep, real_length); 1428 1429 /* Initialize the Periodic Frame List */ 1430 ehci_build_interrupt_lattice(ehcip); 1431 1432 /* Reset Byte Alignment to Default */ 1433 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 1434 1435 return (DDI_SUCCESS); 1436 failure: 1437 /* Byte alignment */ 1438 ehcip->ehci_dma_attr.dma_attr_align = EHCI_DMA_ATTR_ALIGNMENT; 1439 1440 return (DDI_FAILURE); 1441 } 1442 1443 1444 /* 1445 * ehci_build_interrupt_lattice: 1446 * 1447 * Construct the interrupt lattice tree using static Endpoint Descriptors 1448 * (QH). This interrupt lattice tree will have total of 32 interrupt QH 1449 * lists and the Host Controller (HC) processes one interrupt QH list in 1450 * every frame. The Host Controller traverses the periodic schedule by 1451 * constructing an array offset reference from the Periodic List Base Address 1452 * register and bits 12 to 3 of Frame Index register. It fetches the element 1453 * and begins traversing the graph of linked schedule data structures. 1454 */ 1455 static void 1456 ehci_build_interrupt_lattice(ehci_state_t *ehcip) 1457 { 1458 ehci_qh_t *list_array = ehcip->ehci_qh_pool_addr; 1459 ushort_t ehci_index[EHCI_NUM_PERIODIC_FRAME_LISTS]; 1460 ehci_periodic_frame_list_t *periodic_frame_list = 1461 ehcip->ehci_periodic_frame_list_tablep; 1462 ushort_t *temp, num_of_nodes; 1463 uintptr_t addr; 1464 int i, j, k; 1465 1466 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1467 "ehci_build_interrupt_lattice:"); 1468 1469 /* 1470 * Reserve the first 63 Endpoint Descriptor (QH) structures 1471 * in the pool as static endpoints & these are required for 1472 * constructing interrupt lattice tree. 1473 */ 1474 for (i = 0; i < EHCI_NUM_STATIC_NODES; i++) { 1475 Set_QH(list_array[i].qh_state, EHCI_QH_STATIC); 1476 Set_QH(list_array[i].qh_status, EHCI_QH_STS_HALTED); 1477 Set_QH(list_array[i].qh_next_qtd, EHCI_QH_NEXT_QTD_PTR_VALID); 1478 Set_QH(list_array[i].qh_alt_next_qtd, 1479 EHCI_QH_ALT_NEXT_QTD_PTR_VALID); 1480 } 1481 1482 /* 1483 * Make sure that last Endpoint on the periodic frame list terminates 1484 * periodic schedule. 1485 */ 1486 Set_QH(list_array[0].qh_link_ptr, EHCI_QH_LINK_PTR_VALID); 1487 1488 /* Build the interrupt lattice tree */ 1489 for (i = 0; i < (EHCI_NUM_STATIC_NODES / 2); i++) { 1490 /* 1491 * The next pointer in the host controller endpoint 1492 * descriptor must contain an iommu address. Calculate 1493 * the offset into the cpu address and add this to the 1494 * starting iommu address. 1495 */ 1496 addr = ehci_qh_cpu_to_iommu(ehcip, (ehci_qh_t *)&list_array[i]); 1497 1498 Set_QH(list_array[2*i + 1].qh_link_ptr, 1499 addr | EHCI_QH_LINK_REF_QH); 1500 Set_QH(list_array[2*i + 2].qh_link_ptr, 1501 addr | EHCI_QH_LINK_REF_QH); 1502 } 1503 1504 /* Build the tree bottom */ 1505 temp = (unsigned short *) 1506 kmem_zalloc(EHCI_NUM_PERIODIC_FRAME_LISTS * 2, KM_SLEEP); 1507 1508 num_of_nodes = 1; 1509 1510 /* 1511 * Initialize the values which are used for setting up head pointers 1512 * for the 32ms scheduling lists which starts from the Periodic Frame 1513 * List. 1514 */ 1515 for (i = 0; i < ehci_log_2(EHCI_NUM_PERIODIC_FRAME_LISTS); i++) { 1516 for (j = 0, k = 0; k < num_of_nodes; k++, j++) { 1517 ehci_index[j++] = temp[k]; 1518 ehci_index[j] = temp[k] + ehci_pow_2(i); 1519 } 1520 1521 num_of_nodes *= 2; 1522 for (k = 0; k < num_of_nodes; k++) 1523 temp[k] = ehci_index[k]; 1524 } 1525 1526 kmem_free((void *)temp, (EHCI_NUM_PERIODIC_FRAME_LISTS * 2)); 1527 1528 /* 1529 * Initialize the interrupt list in the Periodic Frame List Table 1530 * so that it points to the bottom of the tree. 1531 */ 1532 for (i = 0, j = 0; i < ehci_pow_2(TREE_HEIGHT); i++) { 1533 addr = ehci_qh_cpu_to_iommu(ehcip, (ehci_qh_t *) 1534 (&list_array[((EHCI_NUM_STATIC_NODES + 1) / 2) + i - 1])); 1535 1536 ASSERT(addr); 1537 1538 for (k = 0; k < ehci_pow_2(TREE_HEIGHT); k++) { 1539 Set_PFLT(periodic_frame_list-> 1540 ehci_periodic_frame_list_table[ehci_index[j++]], 1541 (uint32_t)(addr | EHCI_QH_LINK_REF_QH)); 1542 } 1543 } 1544 } 1545 1546 1547 /* 1548 * ehci_alloc_hcdi_ops: 1549 * 1550 * The HCDI interfaces or entry points are the software interfaces used by 1551 * the Universal Serial Bus Driver (USBA) to access the services of the 1552 * Host Controller Driver (HCD). During HCD initialization, inform USBA 1553 * about all available HCDI interfaces or entry points. 1554 */ 1555 usba_hcdi_ops_t * 1556 ehci_alloc_hcdi_ops(ehci_state_t *ehcip) 1557 { 1558 usba_hcdi_ops_t *usba_hcdi_ops; 1559 1560 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1561 "ehci_alloc_hcdi_ops:"); 1562 1563 usba_hcdi_ops = usba_alloc_hcdi_ops(); 1564 1565 usba_hcdi_ops->usba_hcdi_ops_version = HCDI_OPS_VERSION; 1566 1567 usba_hcdi_ops->usba_hcdi_pm_support = ehci_hcdi_pm_support; 1568 usba_hcdi_ops->usba_hcdi_pipe_open = ehci_hcdi_pipe_open; 1569 usba_hcdi_ops->usba_hcdi_pipe_close = ehci_hcdi_pipe_close; 1570 1571 usba_hcdi_ops->usba_hcdi_pipe_reset = ehci_hcdi_pipe_reset; 1572 1573 usba_hcdi_ops->usba_hcdi_pipe_ctrl_xfer = ehci_hcdi_pipe_ctrl_xfer; 1574 usba_hcdi_ops->usba_hcdi_pipe_bulk_xfer = ehci_hcdi_pipe_bulk_xfer; 1575 usba_hcdi_ops->usba_hcdi_pipe_intr_xfer = ehci_hcdi_pipe_intr_xfer; 1576 usba_hcdi_ops->usba_hcdi_pipe_isoc_xfer = ehci_hcdi_pipe_isoc_xfer; 1577 1578 usba_hcdi_ops->usba_hcdi_bulk_transfer_size = 1579 ehci_hcdi_bulk_transfer_size; 1580 1581 usba_hcdi_ops->usba_hcdi_pipe_stop_intr_polling = 1582 ehci_hcdi_pipe_stop_intr_polling; 1583 usba_hcdi_ops->usba_hcdi_pipe_stop_isoc_polling = 1584 ehci_hcdi_pipe_stop_isoc_polling; 1585 1586 usba_hcdi_ops->usba_hcdi_get_current_frame_number = 1587 ehci_hcdi_get_current_frame_number; 1588 usba_hcdi_ops->usba_hcdi_get_max_isoc_pkts = 1589 ehci_hcdi_get_max_isoc_pkts; 1590 1591 usba_hcdi_ops->usba_hcdi_console_input_init = 1592 ehci_hcdi_polled_input_init; 1593 usba_hcdi_ops->usba_hcdi_console_input_enter = 1594 ehci_hcdi_polled_input_enter; 1595 usba_hcdi_ops->usba_hcdi_console_read = 1596 ehci_hcdi_polled_read; 1597 usba_hcdi_ops->usba_hcdi_console_input_exit = 1598 ehci_hcdi_polled_input_exit; 1599 usba_hcdi_ops->usba_hcdi_console_input_fini = 1600 ehci_hcdi_polled_input_fini; 1601 return (usba_hcdi_ops); 1602 } 1603 1604 1605 /* 1606 * Host Controller Driver (HCD) deinitialization functions 1607 */ 1608 1609 /* 1610 * ehci_cleanup: 1611 * 1612 * Cleanup on attach failure or detach 1613 */ 1614 int 1615 ehci_cleanup(ehci_state_t *ehcip) 1616 { 1617 ehci_trans_wrapper_t *tw; 1618 ehci_pipe_private_t *pp; 1619 ehci_qtd_t *qtd; 1620 int i, ctrl, rval; 1621 int flags = ehcip->ehci_flags; 1622 1623 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, "ehci_cleanup:"); 1624 1625 if (flags & EHCI_RHREG) { 1626 /* Unload the root hub driver */ 1627 if (ehci_unload_root_hub_driver(ehcip) != USB_SUCCESS) { 1628 1629 return (DDI_FAILURE); 1630 } 1631 } 1632 1633 if (flags & EHCI_USBAREG) { 1634 /* Unregister this HCD instance with USBA */ 1635 usba_hcdi_unregister(ehcip->ehci_dip); 1636 } 1637 1638 if (flags & EHCI_INTR) { 1639 1640 mutex_enter(&ehcip->ehci_int_mutex); 1641 1642 /* Disable all EHCI QH list processing */ 1643 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) & 1644 ~(EHCI_CMD_ASYNC_SCHED_ENABLE | 1645 EHCI_CMD_PERIODIC_SCHED_ENABLE))); 1646 1647 /* Disable all EHCI interrupts */ 1648 Set_OpReg(ehci_interrupt, 0); 1649 1650 /* wait for the next SOF */ 1651 (void) ehci_wait_for_sof(ehcip); 1652 1653 /* Route all Root hub ports to Classic host controller */ 1654 Set_OpReg(ehci_config_flag, EHCI_CONFIG_FLAG_CLASSIC); 1655 1656 /* Stop the EHCI host controller */ 1657 Set_OpReg(ehci_command, 1658 Get_OpReg(ehci_command) & ~EHCI_CMD_HOST_CTRL_RUN); 1659 1660 /* Wait for sometime */ 1661 drv_usecwait(EHCI_TIMEWAIT); 1662 1663 mutex_exit(&ehcip->ehci_int_mutex); 1664 1665 ehci_rem_intrs(ehcip); 1666 } 1667 1668 /* Unmap the EHCI registers */ 1669 if (ehcip->ehci_caps_handle) { 1670 ddi_regs_map_free(&ehcip->ehci_caps_handle); 1671 } 1672 1673 if (ehcip->ehci_config_handle) { 1674 pci_config_teardown(&ehcip->ehci_config_handle); 1675 } 1676 1677 /* Free all the buffers */ 1678 if (ehcip->ehci_qtd_pool_addr && ehcip->ehci_qtd_pool_mem_handle) { 1679 for (i = 0; i < ehci_qtd_pool_size; i ++) { 1680 qtd = &ehcip->ehci_qtd_pool_addr[i]; 1681 ctrl = Get_QTD(ehcip-> 1682 ehci_qtd_pool_addr[i].qtd_state); 1683 1684 if ((ctrl != EHCI_QTD_FREE) && 1685 (ctrl != EHCI_QTD_DUMMY) && 1686 (qtd->qtd_trans_wrapper)) { 1687 1688 mutex_enter(&ehcip->ehci_int_mutex); 1689 1690 tw = (ehci_trans_wrapper_t *) 1691 EHCI_LOOKUP_ID((uint32_t) 1692 Get_QTD(qtd->qtd_trans_wrapper)); 1693 1694 /* Obtain the pipe private structure */ 1695 pp = tw->tw_pipe_private; 1696 1697 /* Stop the the transfer timer */ 1698 ehci_stop_xfer_timer(ehcip, tw, 1699 EHCI_REMOVE_XFER_ALWAYS); 1700 1701 ehci_deallocate_tw(ehcip, pp, tw); 1702 1703 mutex_exit(&ehcip->ehci_int_mutex); 1704 } 1705 } 1706 1707 /* 1708 * If EHCI_QTD_POOL_BOUND flag is set, then unbind 1709 * the handle for QTD pools. 1710 */ 1711 if ((ehcip->ehci_dma_addr_bind_flag & 1712 EHCI_QTD_POOL_BOUND) == EHCI_QTD_POOL_BOUND) { 1713 1714 rval = ddi_dma_unbind_handle( 1715 ehcip->ehci_qtd_pool_dma_handle); 1716 1717 ASSERT(rval == DDI_SUCCESS); 1718 } 1719 ddi_dma_mem_free(&ehcip->ehci_qtd_pool_mem_handle); 1720 } 1721 1722 /* Free the QTD pool */ 1723 if (ehcip->ehci_qtd_pool_dma_handle) { 1724 ddi_dma_free_handle(&ehcip->ehci_qtd_pool_dma_handle); 1725 } 1726 1727 if (ehcip->ehci_qh_pool_addr && ehcip->ehci_qh_pool_mem_handle) { 1728 /* 1729 * If EHCI_QH_POOL_BOUND flag is set, then unbind 1730 * the handle for QH pools. 1731 */ 1732 if ((ehcip->ehci_dma_addr_bind_flag & 1733 EHCI_QH_POOL_BOUND) == EHCI_QH_POOL_BOUND) { 1734 1735 rval = ddi_dma_unbind_handle( 1736 ehcip->ehci_qh_pool_dma_handle); 1737 1738 ASSERT(rval == DDI_SUCCESS); 1739 } 1740 1741 ddi_dma_mem_free(&ehcip->ehci_qh_pool_mem_handle); 1742 } 1743 1744 /* Free the QH pool */ 1745 if (ehcip->ehci_qh_pool_dma_handle) { 1746 ddi_dma_free_handle(&ehcip->ehci_qh_pool_dma_handle); 1747 } 1748 1749 /* Free the Periodic frame list table (PFLT) area */ 1750 if (ehcip->ehci_periodic_frame_list_tablep && 1751 ehcip->ehci_pflt_mem_handle) { 1752 /* 1753 * If EHCI_PFLT_DMA_BOUND flag is set, then unbind 1754 * the handle for PFLT. 1755 */ 1756 if ((ehcip->ehci_dma_addr_bind_flag & 1757 EHCI_PFLT_DMA_BOUND) == EHCI_PFLT_DMA_BOUND) { 1758 1759 rval = ddi_dma_unbind_handle( 1760 ehcip->ehci_pflt_dma_handle); 1761 1762 ASSERT(rval == DDI_SUCCESS); 1763 } 1764 1765 ddi_dma_mem_free(&ehcip->ehci_pflt_mem_handle); 1766 } 1767 1768 (void) ehci_isoc_cleanup(ehcip); 1769 1770 if (ehcip->ehci_pflt_dma_handle) { 1771 ddi_dma_free_handle(&ehcip->ehci_pflt_dma_handle); 1772 } 1773 1774 if (flags & EHCI_INTR) { 1775 /* Destroy the mutex */ 1776 mutex_destroy(&ehcip->ehci_int_mutex); 1777 1778 /* Destroy the async schedule advance condition variable */ 1779 cv_destroy(&ehcip->ehci_async_schedule_advance_cv); 1780 } 1781 1782 /* clean up kstat structs */ 1783 ehci_destroy_stats(ehcip); 1784 1785 /* Free ehci hcdi ops */ 1786 if (ehcip->ehci_hcdi_ops) { 1787 usba_free_hcdi_ops(ehcip->ehci_hcdi_ops); 1788 } 1789 1790 if (flags & EHCI_ZALLOC) { 1791 1792 usb_free_log_hdl(ehcip->ehci_log_hdl); 1793 1794 /* Remove all properties that might have been created */ 1795 ddi_prop_remove_all(ehcip->ehci_dip); 1796 1797 /* Free the soft state */ 1798 ddi_soft_state_free(ehci_statep, 1799 ddi_get_instance(ehcip->ehci_dip)); 1800 } 1801 1802 return (DDI_SUCCESS); 1803 } 1804 1805 1806 /* 1807 * ehci_rem_intrs: 1808 * 1809 * Unregister FIXED or MSI interrupts 1810 */ 1811 static void 1812 ehci_rem_intrs(ehci_state_t *ehcip) 1813 { 1814 int i; 1815 1816 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1817 "ehci_rem_intrs: interrupt type 0x%x", ehcip->ehci_intr_type); 1818 1819 /* Disable all interrupts */ 1820 if (ehcip->ehci_intr_cap & DDI_INTR_FLAG_BLOCK) { 1821 (void) ddi_intr_block_disable(ehcip->ehci_htable, 1822 ehcip->ehci_intr_cnt); 1823 } else { 1824 for (i = 0; i < ehcip->ehci_intr_cnt; i++) { 1825 (void) ddi_intr_disable(ehcip->ehci_htable[i]); 1826 } 1827 } 1828 1829 /* Call ddi_intr_remove_handler() */ 1830 for (i = 0; i < ehcip->ehci_intr_cnt; i++) { 1831 (void) ddi_intr_remove_handler(ehcip->ehci_htable[i]); 1832 (void) ddi_intr_free(ehcip->ehci_htable[i]); 1833 } 1834 1835 kmem_free(ehcip->ehci_htable, 1836 ehcip->ehci_intr_cnt * sizeof (ddi_intr_handle_t)); 1837 } 1838 1839 1840 /* 1841 * ehci_cpr_suspend 1842 */ 1843 int 1844 ehci_cpr_suspend(ehci_state_t *ehcip) 1845 { 1846 int i; 1847 1848 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1849 "ehci_cpr_suspend:"); 1850 1851 /* Call into the root hub and suspend it */ 1852 if (usba_hubdi_detach(ehcip->ehci_dip, DDI_SUSPEND) != DDI_SUCCESS) { 1853 1854 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1855 "ehci_cpr_suspend: root hub fails to suspend"); 1856 1857 return (DDI_FAILURE); 1858 } 1859 1860 /* Only root hub's intr pipe should be open at this time */ 1861 mutex_enter(&ehcip->ehci_int_mutex); 1862 1863 ASSERT(ehcip->ehci_open_pipe_count == 0); 1864 1865 /* Just wait till all resources are reclaimed */ 1866 i = 0; 1867 while ((ehcip->ehci_reclaim_list != NULL) && (i++ < 3)) { 1868 ehci_handle_endpoint_reclaimation(ehcip); 1869 (void) ehci_wait_for_sof(ehcip); 1870 } 1871 ASSERT(ehcip->ehci_reclaim_list == NULL); 1872 1873 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1874 "ehci_cpr_suspend: Disable HC QH list processing"); 1875 1876 /* Disable all EHCI QH list processing */ 1877 Set_OpReg(ehci_command, (Get_OpReg(ehci_command) & 1878 ~(EHCI_CMD_ASYNC_SCHED_ENABLE | EHCI_CMD_PERIODIC_SCHED_ENABLE))); 1879 1880 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1881 "ehci_cpr_suspend: Disable HC interrupts"); 1882 1883 /* Disable all EHCI interrupts */ 1884 Set_OpReg(ehci_interrupt, 0); 1885 1886 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1887 "ehci_cpr_suspend: Wait for the next SOF"); 1888 1889 /* Wait for the next SOF */ 1890 if (ehci_wait_for_sof(ehcip) != USB_SUCCESS) { 1891 1892 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1893 "ehci_cpr_suspend: ehci host controller suspend failed"); 1894 1895 mutex_exit(&ehcip->ehci_int_mutex); 1896 return (DDI_FAILURE); 1897 } 1898 1899 /* 1900 * Stop the ehci host controller 1901 * if usb keyboard is not connected. 1902 */ 1903 if (ehcip->ehci_polled_kbd_count == 0) { 1904 Set_OpReg(ehci_command, 1905 Get_OpReg(ehci_command) & ~EHCI_CMD_HOST_CTRL_RUN); 1906 } 1907 1908 /* Set host controller soft state to suspend */ 1909 ehcip->ehci_hc_soft_state = EHCI_CTLR_SUSPEND_STATE; 1910 1911 mutex_exit(&ehcip->ehci_int_mutex); 1912 1913 return (DDI_SUCCESS); 1914 } 1915 1916 1917 /* 1918 * ehci_cpr_resume 1919 */ 1920 int 1921 ehci_cpr_resume(ehci_state_t *ehcip) 1922 { 1923 mutex_enter(&ehcip->ehci_int_mutex); 1924 1925 USB_DPRINTF_L4(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1926 "ehci_cpr_resume: Restart the controller"); 1927 1928 /* Cleanup ehci specific information across cpr */ 1929 ehci_cpr_cleanup(ehcip); 1930 1931 /* Restart the controller */ 1932 if (ehci_init_ctlr(ehcip) != DDI_SUCCESS) { 1933 1934 USB_DPRINTF_L2(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 1935 "ehci_cpr_resume: ehci host controller resume failed "); 1936 1937 mutex_exit(&ehcip->ehci_int_mutex); 1938 1939 return (DDI_FAILURE); 1940 } 1941 1942 mutex_exit(&ehcip->ehci_int_mutex); 1943 1944 /* Now resume the root hub */ 1945 if (usba_hubdi_attach(ehcip->ehci_dip, DDI_RESUME) != DDI_SUCCESS) { 1946 1947 return (DDI_FAILURE); 1948 } 1949 1950 return (DDI_SUCCESS); 1951 } 1952 1953 1954 /* 1955 * Bandwidth Allocation functions 1956 */ 1957 1958 /* 1959 * ehci_allocate_bandwidth: 1960 * 1961 * Figure out whether or not this interval may be supported. Return the index 1962 * into the lattice if it can be supported. Return allocation failure if it 1963 * can not be supported. 1964 */ 1965 int 1966 ehci_allocate_bandwidth( 1967 ehci_state_t *ehcip, 1968 usba_pipe_handle_data_t *ph, 1969 uint_t *pnode, 1970 uchar_t *smask, 1971 uchar_t *cmask) 1972 { 1973 int error = USB_SUCCESS; 1974 1975 /* This routine is protected by the ehci_int_mutex */ 1976 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 1977 1978 /* Reset the pnode to the last checked pnode */ 1979 *pnode = 0; 1980 1981 /* Allocate high speed bandwidth */ 1982 if ((error = ehci_allocate_high_speed_bandwidth(ehcip, 1983 ph, pnode, smask, cmask)) != USB_SUCCESS) { 1984 1985 return (error); 1986 } 1987 1988 /* 1989 * For low/full speed usb devices, allocate classic TT bandwidth 1990 * in additional to high speed bandwidth. 1991 */ 1992 if (ph->p_usba_device->usb_port_status != USBA_HIGH_SPEED_DEV) { 1993 1994 /* Allocate classic TT bandwidth */ 1995 if ((error = ehci_allocate_classic_tt_bandwidth( 1996 ehcip, ph, *pnode)) != USB_SUCCESS) { 1997 1998 /* Deallocate high speed bandwidth */ 1999 ehci_deallocate_high_speed_bandwidth( 2000 ehcip, ph, *pnode, *smask, *cmask); 2001 } 2002 } 2003 2004 return (error); 2005 } 2006 2007 2008 /* 2009 * ehci_allocate_high_speed_bandwidth: 2010 * 2011 * Allocate high speed bandwidth for the low/full/high speed interrupt and 2012 * isochronous endpoints. 2013 */ 2014 static int 2015 ehci_allocate_high_speed_bandwidth( 2016 ehci_state_t *ehcip, 2017 usba_pipe_handle_data_t *ph, 2018 uint_t *pnode, 2019 uchar_t *smask, 2020 uchar_t *cmask) 2021 { 2022 uint_t sbandwidth, cbandwidth; 2023 int interval; 2024 usb_ep_descr_t *endpoint = &ph->p_ep; 2025 usba_device_t *child_ud; 2026 usb_port_status_t port_status; 2027 int error; 2028 2029 /* This routine is protected by the ehci_int_mutex */ 2030 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2031 2032 /* Get child's usba device structure */ 2033 child_ud = ph->p_usba_device; 2034 2035 mutex_enter(&child_ud->usb_mutex); 2036 2037 /* Get the current usb device's port status */ 2038 port_status = ph->p_usba_device->usb_port_status; 2039 2040 mutex_exit(&child_ud->usb_mutex); 2041 2042 /* 2043 * Calculate the length in bytes of a transaction on this 2044 * periodic endpoint. Return failure if maximum packet is 2045 * zero. 2046 */ 2047 error = ehci_compute_high_speed_bandwidth(ehcip, endpoint, 2048 port_status, &sbandwidth, &cbandwidth); 2049 if (error != USB_SUCCESS) { 2050 2051 return (error); 2052 } 2053 2054 /* 2055 * Adjust polling interval to be a power of 2. 2056 * If this interval can't be supported, return 2057 * allocation failure. 2058 */ 2059 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2060 if (interval == USB_FAILURE) { 2061 2062 return (USB_FAILURE); 2063 } 2064 2065 if (port_status == USBA_HIGH_SPEED_DEV) { 2066 /* Allocate bandwidth for high speed devices, except ITD */ 2067 error = ehci_find_bestfit_hs_mask(ehcip, smask, pnode, 2068 endpoint, sbandwidth, interval); 2069 *cmask = 0x00; 2070 2071 } else { 2072 if ((endpoint->bmAttributes & USB_EP_ATTR_MASK) == 2073 USB_EP_ATTR_INTR) { 2074 2075 /* Allocate bandwidth for low speed interrupt */ 2076 error = ehci_find_bestfit_ls_intr_mask(ehcip, 2077 smask, cmask, pnode, sbandwidth, cbandwidth, 2078 interval); 2079 } else { 2080 if ((endpoint->bEndpointAddress & 2081 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2082 2083 /* Allocate bandwidth for sitd in */ 2084 error = ehci_find_bestfit_sitd_in_mask(ehcip, 2085 smask, cmask, pnode, sbandwidth, cbandwidth, 2086 interval); 2087 } else { 2088 2089 /* Allocate bandwidth for sitd out */ 2090 error = ehci_find_bestfit_sitd_out_mask(ehcip, 2091 smask, pnode, sbandwidth, interval); 2092 *cmask = 0x00; 2093 } 2094 } 2095 } 2096 2097 if (error != USB_SUCCESS) { 2098 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2099 "ehci_allocate_high_speed_bandwidth: Reached maximum " 2100 "bandwidth value and cannot allocate bandwidth for a " 2101 "given high-speed periodic endpoint"); 2102 2103 return (USB_NO_BANDWIDTH); 2104 } 2105 2106 return (error); 2107 } 2108 2109 2110 /* 2111 * ehci_allocate_classic_tt_speed_bandwidth: 2112 * 2113 * Allocate classic TT bandwidth for the low/full speed interrupt and 2114 * isochronous endpoints. 2115 */ 2116 static int 2117 ehci_allocate_classic_tt_bandwidth( 2118 ehci_state_t *ehcip, 2119 usba_pipe_handle_data_t *ph, 2120 uint_t pnode) 2121 { 2122 uint_t bandwidth, min; 2123 uint_t height, leftmost, list; 2124 usb_ep_descr_t *endpoint = &ph->p_ep; 2125 usba_device_t *child_ud, *parent_ud; 2126 usb_port_status_t port_status; 2127 int i, interval; 2128 2129 /* This routine is protected by the ehci_int_mutex */ 2130 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2131 2132 /* Get child's usba device structure */ 2133 child_ud = ph->p_usba_device; 2134 2135 mutex_enter(&child_ud->usb_mutex); 2136 2137 /* Get the current usb device's port status */ 2138 port_status = child_ud->usb_port_status; 2139 2140 /* Get the parent high speed hub's usba device structure */ 2141 parent_ud = child_ud->usb_hs_hub_usba_dev; 2142 2143 mutex_exit(&child_ud->usb_mutex); 2144 2145 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2146 "ehci_allocate_classic_tt_bandwidth: " 2147 "child_ud 0x%p parent_ud 0x%p", child_ud, parent_ud); 2148 2149 /* 2150 * Calculate the length in bytes of a transaction on this 2151 * periodic endpoint. Return failure if maximum packet is 2152 * zero. 2153 */ 2154 if (ehci_compute_classic_bandwidth(endpoint, 2155 port_status, &bandwidth) != USB_SUCCESS) { 2156 2157 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2158 "ehci_allocate_classic_tt_bandwidth: Periodic endpoint " 2159 "with zero endpoint maximum packet size is not supported"); 2160 2161 return (USB_NOT_SUPPORTED); 2162 } 2163 2164 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2165 "ehci_allocate_classic_tt_bandwidth: bandwidth %d", bandwidth); 2166 2167 mutex_enter(&parent_ud->usb_mutex); 2168 2169 /* 2170 * If the length in bytes plus the allocated bandwidth exceeds 2171 * the maximum, return bandwidth allocation failure. 2172 */ 2173 if ((parent_ud->usb_hs_hub_min_bandwidth + bandwidth) > 2174 FS_PERIODIC_BANDWIDTH) { 2175 2176 mutex_exit(&parent_ud->usb_mutex); 2177 2178 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2179 "ehci_allocate_classic_tt_bandwidth: Reached maximum " 2180 "bandwidth value and cannot allocate bandwidth for a " 2181 "given low/full speed periodic endpoint"); 2182 2183 return (USB_NO_BANDWIDTH); 2184 } 2185 2186 mutex_exit(&parent_ud->usb_mutex); 2187 2188 /* Adjust polling interval to be a power of 2 */ 2189 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2190 2191 /* Find the height in the tree */ 2192 height = ehci_lattice_height(interval); 2193 2194 /* Find the leftmost leaf in the subtree specified by the node. */ 2195 leftmost = ehci_leftmost_leaf(pnode, height); 2196 2197 mutex_enter(&parent_ud->usb_mutex); 2198 2199 for (i = 0; i < (EHCI_NUM_INTR_QH_LISTS/interval); i++) { 2200 list = ehci_index[leftmost + i]; 2201 2202 if ((parent_ud->usb_hs_hub_bandwidth[list] + 2203 bandwidth) > FS_PERIODIC_BANDWIDTH) { 2204 2205 mutex_exit(&parent_ud->usb_mutex); 2206 2207 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2208 "ehci_allocate_classic_tt_bandwidth: Reached " 2209 "maximum bandwidth value and cannot allocate " 2210 "bandwidth for low/full periodic endpoint"); 2211 2212 return (USB_NO_BANDWIDTH); 2213 } 2214 } 2215 2216 /* 2217 * All the leaves for this node must be updated with the bandwidth. 2218 */ 2219 for (i = 0; i < (EHCI_NUM_INTR_QH_LISTS/interval); i++) { 2220 list = ehci_index[leftmost + i]; 2221 parent_ud->usb_hs_hub_bandwidth[list] += bandwidth; 2222 } 2223 2224 /* Find the leaf with the smallest allocated bandwidth */ 2225 min = parent_ud->usb_hs_hub_bandwidth[0]; 2226 2227 for (i = 1; i < EHCI_NUM_INTR_QH_LISTS; i++) { 2228 if (parent_ud->usb_hs_hub_bandwidth[i] < min) { 2229 min = parent_ud->usb_hs_hub_bandwidth[i]; 2230 } 2231 } 2232 2233 /* Save the minimum for later use */ 2234 parent_ud->usb_hs_hub_min_bandwidth = min; 2235 2236 mutex_exit(&parent_ud->usb_mutex); 2237 2238 return (USB_SUCCESS); 2239 } 2240 2241 2242 /* 2243 * ehci_deallocate_bandwidth: 2244 * 2245 * Deallocate bandwidth for the given node in the lattice and the length 2246 * of transfer. 2247 */ 2248 void 2249 ehci_deallocate_bandwidth( 2250 ehci_state_t *ehcip, 2251 usba_pipe_handle_data_t *ph, 2252 uint_t pnode, 2253 uchar_t smask, 2254 uchar_t cmask) 2255 { 2256 /* This routine is protected by the ehci_int_mutex */ 2257 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2258 2259 ehci_deallocate_high_speed_bandwidth(ehcip, ph, pnode, smask, cmask); 2260 2261 /* 2262 * For low/full speed usb devices, deallocate classic TT bandwidth 2263 * in additional to high speed bandwidth. 2264 */ 2265 if (ph->p_usba_device->usb_port_status != USBA_HIGH_SPEED_DEV) { 2266 2267 /* Deallocate classic TT bandwidth */ 2268 ehci_deallocate_classic_tt_bandwidth(ehcip, ph, pnode); 2269 } 2270 } 2271 2272 2273 /* 2274 * ehci_deallocate_high_speed_bandwidth: 2275 * 2276 * Deallocate high speed bandwidth of a interrupt or isochronous endpoint. 2277 */ 2278 static void 2279 ehci_deallocate_high_speed_bandwidth( 2280 ehci_state_t *ehcip, 2281 usba_pipe_handle_data_t *ph, 2282 uint_t pnode, 2283 uchar_t smask, 2284 uchar_t cmask) 2285 { 2286 uint_t height, leftmost; 2287 uint_t list_count; 2288 uint_t sbandwidth, cbandwidth; 2289 int interval; 2290 usb_ep_descr_t *endpoint = &ph->p_ep; 2291 usba_device_t *child_ud; 2292 usb_port_status_t port_status; 2293 2294 /* This routine is protected by the ehci_int_mutex */ 2295 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2296 2297 /* Get child's usba device structure */ 2298 child_ud = ph->p_usba_device; 2299 2300 mutex_enter(&child_ud->usb_mutex); 2301 2302 /* Get the current usb device's port status */ 2303 port_status = ph->p_usba_device->usb_port_status; 2304 2305 mutex_exit(&child_ud->usb_mutex); 2306 2307 (void) ehci_compute_high_speed_bandwidth(ehcip, endpoint, 2308 port_status, &sbandwidth, &cbandwidth); 2309 2310 /* Adjust polling interval to be a power of 2 */ 2311 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2312 2313 /* Find the height in the tree */ 2314 height = ehci_lattice_height(interval); 2315 2316 /* 2317 * Find the leftmost leaf in the subtree specified by the node 2318 */ 2319 leftmost = ehci_leftmost_leaf(pnode, height); 2320 2321 list_count = EHCI_NUM_INTR_QH_LISTS/interval; 2322 2323 /* Delete the bandwidth from the appropriate lists */ 2324 if (port_status == USBA_HIGH_SPEED_DEV) { 2325 2326 ehci_update_bw_availability(ehcip, -sbandwidth, 2327 leftmost, list_count, smask); 2328 } else { 2329 if ((endpoint->bmAttributes & USB_EP_ATTR_MASK) == 2330 USB_EP_ATTR_INTR) { 2331 2332 ehci_update_bw_availability(ehcip, -sbandwidth, 2333 leftmost, list_count, smask); 2334 ehci_update_bw_availability(ehcip, -cbandwidth, 2335 leftmost, list_count, cmask); 2336 } else { 2337 if ((endpoint->bEndpointAddress & 2338 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2339 2340 ehci_update_bw_availability(ehcip, -sbandwidth, 2341 leftmost, list_count, smask); 2342 ehci_update_bw_availability(ehcip, 2343 -MAX_UFRAME_SITD_XFER, leftmost, 2344 list_count, cmask); 2345 } else { 2346 2347 ehci_update_bw_availability(ehcip, 2348 -MAX_UFRAME_SITD_XFER, leftmost, 2349 list_count, smask); 2350 } 2351 } 2352 } 2353 } 2354 2355 /* 2356 * ehci_deallocate_classic_tt_bandwidth: 2357 * 2358 * Deallocate high speed bandwidth of a interrupt or isochronous endpoint. 2359 */ 2360 static void 2361 ehci_deallocate_classic_tt_bandwidth( 2362 ehci_state_t *ehcip, 2363 usba_pipe_handle_data_t *ph, 2364 uint_t pnode) 2365 { 2366 uint_t bandwidth, height, leftmost, list, min; 2367 int i, interval; 2368 usb_ep_descr_t *endpoint = &ph->p_ep; 2369 usba_device_t *child_ud, *parent_ud; 2370 usb_port_status_t port_status; 2371 2372 /* This routine is protected by the ehci_int_mutex */ 2373 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 2374 2375 /* Get child's usba device structure */ 2376 child_ud = ph->p_usba_device; 2377 2378 mutex_enter(&child_ud->usb_mutex); 2379 2380 /* Get the current usb device's port status */ 2381 port_status = child_ud->usb_port_status; 2382 2383 /* Get the parent high speed hub's usba device structure */ 2384 parent_ud = child_ud->usb_hs_hub_usba_dev; 2385 2386 mutex_exit(&child_ud->usb_mutex); 2387 2388 /* Obtain the bandwidth */ 2389 (void) ehci_compute_classic_bandwidth(endpoint, 2390 port_status, &bandwidth); 2391 2392 /* Adjust polling interval to be a power of 2 */ 2393 interval = ehci_adjust_polling_interval(ehcip, endpoint, port_status); 2394 2395 /* Find the height in the tree */ 2396 height = ehci_lattice_height(interval); 2397 2398 /* Find the leftmost leaf in the subtree specified by the node */ 2399 leftmost = ehci_leftmost_leaf(pnode, height); 2400 2401 mutex_enter(&parent_ud->usb_mutex); 2402 2403 /* Delete the bandwidth from the appropriate lists */ 2404 for (i = 0; i < (EHCI_NUM_INTR_QH_LISTS/interval); i++) { 2405 list = ehci_index[leftmost + i]; 2406 parent_ud->usb_hs_hub_bandwidth[list] -= bandwidth; 2407 } 2408 2409 /* Find the leaf with the smallest allocated bandwidth */ 2410 min = parent_ud->usb_hs_hub_bandwidth[0]; 2411 2412 for (i = 1; i < EHCI_NUM_INTR_QH_LISTS; i++) { 2413 if (parent_ud->usb_hs_hub_bandwidth[i] < min) { 2414 min = parent_ud->usb_hs_hub_bandwidth[i]; 2415 } 2416 } 2417 2418 /* Save the minimum for later use */ 2419 parent_ud->usb_hs_hub_min_bandwidth = min; 2420 2421 mutex_exit(&parent_ud->usb_mutex); 2422 } 2423 2424 2425 /* 2426 * ehci_compute_high_speed_bandwidth: 2427 * 2428 * Given a periodic endpoint (interrupt or isochronous) determine the total 2429 * bandwidth for one transaction. The EHCI host controller traverses the 2430 * endpoint descriptor lists on a first-come-first-serve basis. When the HC 2431 * services an endpoint, only a single transaction attempt is made. The HC 2432 * moves to the next Endpoint Descriptor after the first transaction attempt 2433 * rather than finishing the entire Transfer Descriptor. Therefore, when a 2434 * Transfer Descriptor is inserted into the lattice, we will only count the 2435 * number of bytes for one transaction. 2436 * 2437 * The following are the formulas used for calculating bandwidth in terms 2438 * bytes and it is for the single USB high speed transaction. The protocol 2439 * overheads will be different for each of type of USB transfer & all these 2440 * formulas & protocol overheads are derived from the 5.11.3 section of the 2441 * USB 2.0 Specification. 2442 * 2443 * High-Speed: 2444 * Protocol overhead + ((MaxPktSz * 7)/6) + Host_Delay 2445 * 2446 * Split Transaction: (Low/Full speed devices connected behind usb2.0 hub) 2447 * 2448 * Protocol overhead + Split transaction overhead + 2449 * ((MaxPktSz * 7)/6) + Host_Delay; 2450 */ 2451 /* ARGSUSED */ 2452 static int 2453 ehci_compute_high_speed_bandwidth( 2454 ehci_state_t *ehcip, 2455 usb_ep_descr_t *endpoint, 2456 usb_port_status_t port_status, 2457 uint_t *sbandwidth, 2458 uint_t *cbandwidth) 2459 { 2460 ushort_t maxpacketsize = endpoint->wMaxPacketSize; 2461 2462 /* Return failure if endpoint maximum packet is zero */ 2463 if (maxpacketsize == 0) { 2464 USB_DPRINTF_L2(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2465 "ehci_allocate_high_speed_bandwidth: Periodic endpoint " 2466 "with zero endpoint maximum packet size is not supported"); 2467 2468 return (USB_NOT_SUPPORTED); 2469 } 2470 2471 /* Add bit-stuffing overhead */ 2472 maxpacketsize = (ushort_t)((maxpacketsize * 7) / 6); 2473 2474 /* Add Host Controller specific delay to required bandwidth */ 2475 *sbandwidth = EHCI_HOST_CONTROLLER_DELAY; 2476 2477 /* Add xfer specific protocol overheads */ 2478 if ((endpoint->bmAttributes & 2479 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) { 2480 /* High speed interrupt transaction */ 2481 *sbandwidth += HS_NON_ISOC_PROTO_OVERHEAD; 2482 } else { 2483 /* Isochronous transaction */ 2484 *sbandwidth += HS_ISOC_PROTO_OVERHEAD; 2485 } 2486 2487 /* 2488 * For low/full speed devices, add split transaction specific 2489 * overheads. 2490 */ 2491 if (port_status != USBA_HIGH_SPEED_DEV) { 2492 /* 2493 * Add start and complete split transaction 2494 * tokens overheads. 2495 */ 2496 *cbandwidth = *sbandwidth + COMPLETE_SPLIT_OVERHEAD; 2497 *sbandwidth += START_SPLIT_OVERHEAD; 2498 2499 /* Add data overhead depending on data direction */ 2500 if ((endpoint->bEndpointAddress & 2501 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2502 *cbandwidth += maxpacketsize; 2503 } else { 2504 if ((endpoint->bmAttributes & 2505 USB_EP_ATTR_MASK) == USB_EP_ATTR_ISOCH) { 2506 /* There is no compete splits for out */ 2507 *cbandwidth = 0; 2508 } 2509 *sbandwidth += maxpacketsize; 2510 } 2511 } else { 2512 uint_t xactions; 2513 2514 /* Get the max transactions per microframe */ 2515 xactions = ((maxpacketsize & USB_EP_MAX_XACTS_MASK) >> 2516 USB_EP_MAX_XACTS_SHIFT) + 1; 2517 2518 /* High speed transaction */ 2519 *sbandwidth += maxpacketsize; 2520 2521 /* Calculate bandwidth per micro-frame */ 2522 *sbandwidth *= xactions; 2523 2524 *cbandwidth = 0; 2525 } 2526 2527 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2528 "ehci_allocate_high_speed_bandwidth: " 2529 "Start split bandwidth %d Complete split bandwidth %d", 2530 *sbandwidth, *cbandwidth); 2531 2532 return (USB_SUCCESS); 2533 } 2534 2535 2536 /* 2537 * ehci_compute_classic_bandwidth: 2538 * 2539 * Given a periodic endpoint (interrupt or isochronous) determine the total 2540 * bandwidth for one transaction. The EHCI host controller traverses the 2541 * endpoint descriptor lists on a first-come-first-serve basis. When the HC 2542 * services an endpoint, only a single transaction attempt is made. The HC 2543 * moves to the next Endpoint Descriptor after the first transaction attempt 2544 * rather than finishing the entire Transfer Descriptor. Therefore, when a 2545 * Transfer Descriptor is inserted into the lattice, we will only count the 2546 * number of bytes for one transaction. 2547 * 2548 * The following are the formulas used for calculating bandwidth in terms 2549 * bytes and it is for the single USB high speed transaction. The protocol 2550 * overheads will be different for each of type of USB transfer & all these 2551 * formulas & protocol overheads are derived from the 5.11.3 section of the 2552 * USB 2.0 Specification. 2553 * 2554 * Low-Speed: 2555 * Protocol overhead + Hub LS overhead + 2556 * (Low Speed clock * ((MaxPktSz * 7)/6)) + TT_Delay 2557 * 2558 * Full-Speed: 2559 * Protocol overhead + ((MaxPktSz * 7)/6) + TT_Delay 2560 */ 2561 /* ARGSUSED */ 2562 static int 2563 ehci_compute_classic_bandwidth( 2564 usb_ep_descr_t *endpoint, 2565 usb_port_status_t port_status, 2566 uint_t *bandwidth) 2567 { 2568 ushort_t maxpacketsize = endpoint->wMaxPacketSize; 2569 2570 /* 2571 * If endpoint maximum packet is zero, then return immediately. 2572 */ 2573 if (maxpacketsize == 0) { 2574 2575 return (USB_NOT_SUPPORTED); 2576 } 2577 2578 /* Add TT delay to required bandwidth */ 2579 *bandwidth = TT_DELAY; 2580 2581 /* Add bit-stuffing overhead */ 2582 maxpacketsize = (ushort_t)((maxpacketsize * 7) / 6); 2583 2584 switch (port_status) { 2585 case USBA_LOW_SPEED_DEV: 2586 /* Low speed interrupt transaction */ 2587 *bandwidth += (LOW_SPEED_PROTO_OVERHEAD + 2588 HUB_LOW_SPEED_PROTO_OVERHEAD + 2589 (LOW_SPEED_CLOCK * maxpacketsize)); 2590 break; 2591 case USBA_FULL_SPEED_DEV: 2592 /* Full speed transaction */ 2593 *bandwidth += maxpacketsize; 2594 2595 /* Add xfer specific protocol overheads */ 2596 if ((endpoint->bmAttributes & 2597 USB_EP_ATTR_MASK) == USB_EP_ATTR_INTR) { 2598 /* Full speed interrupt transaction */ 2599 *bandwidth += FS_NON_ISOC_PROTO_OVERHEAD; 2600 } else { 2601 /* Isochronous and input transaction */ 2602 if ((endpoint->bEndpointAddress & 2603 USB_EP_DIR_MASK) == USB_EP_DIR_IN) { 2604 *bandwidth += FS_ISOC_INPUT_PROTO_OVERHEAD; 2605 } else { 2606 /* Isochronous and output transaction */ 2607 *bandwidth += FS_ISOC_OUTPUT_PROTO_OVERHEAD; 2608 } 2609 } 2610 break; 2611 } 2612 2613 return (USB_SUCCESS); 2614 } 2615 2616 2617 /* 2618 * ehci_adjust_polling_interval: 2619 * 2620 * Adjust bandwidth according usb device speed. 2621 */ 2622 /* ARGSUSED */ 2623 int 2624 ehci_adjust_polling_interval( 2625 ehci_state_t *ehcip, 2626 usb_ep_descr_t *endpoint, 2627 usb_port_status_t port_status) 2628 { 2629 uint_t interval; 2630 int i = 0; 2631 2632 /* Get the polling interval */ 2633 interval = endpoint->bInterval; 2634 2635 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2636 "ehci_adjust_polling_interval: Polling interval 0x%x", interval); 2637 2638 /* 2639 * According USB 2.0 Specifications, a high-speed endpoint's 2640 * polling intervals are specified interms of 125us or micro 2641 * frame, where as full/low endpoint's polling intervals are 2642 * specified in milliseconds. 2643 * 2644 * A high speed interrupt/isochronous endpoints can specify 2645 * desired polling interval between 1 to 16 micro-frames, 2646 * where as full/low endpoints can specify between 1 to 255 2647 * milliseconds. 2648 */ 2649 switch (port_status) { 2650 case USBA_LOW_SPEED_DEV: 2651 /* 2652 * Low speed endpoints are limited to specifying 2653 * only 8ms to 255ms in this driver. If a device 2654 * reports a polling interval that is less than 8ms, 2655 * it will use 8 ms instead. 2656 */ 2657 if (interval < LS_MIN_POLL_INTERVAL) { 2658 2659 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2660 "Low speed endpoint's poll interval of %d ms " 2661 "is below threshold. Rounding up to %d ms", 2662 interval, LS_MIN_POLL_INTERVAL); 2663 2664 interval = LS_MIN_POLL_INTERVAL; 2665 } 2666 2667 /* 2668 * Return an error if the polling interval is greater 2669 * than 255ms. 2670 */ 2671 if (interval > LS_MAX_POLL_INTERVAL) { 2672 2673 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2674 "Low speed endpoint's poll interval is " 2675 "greater than %d ms", LS_MAX_POLL_INTERVAL); 2676 2677 return (USB_FAILURE); 2678 } 2679 break; 2680 2681 case USBA_FULL_SPEED_DEV: 2682 /* 2683 * Return an error if the polling interval is less 2684 * than 1ms and greater than 255ms. 2685 */ 2686 if ((interval < FS_MIN_POLL_INTERVAL) && 2687 (interval > FS_MAX_POLL_INTERVAL)) { 2688 2689 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2690 "Full speed endpoint's poll interval must " 2691 "be between %d and %d ms", FS_MIN_POLL_INTERVAL, 2692 FS_MAX_POLL_INTERVAL); 2693 2694 return (USB_FAILURE); 2695 } 2696 break; 2697 case USBA_HIGH_SPEED_DEV: 2698 /* 2699 * Return an error if the polling interval is less 1 2700 * and greater than 16. Convert this value to 125us 2701 * units using 2^(bInterval -1). refer usb 2.0 spec 2702 * page 51 for details. 2703 */ 2704 if ((interval < HS_MIN_POLL_INTERVAL) && 2705 (interval > HS_MAX_POLL_INTERVAL)) { 2706 2707 USB_DPRINTF_L1(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2708 "High speed endpoint's poll interval " 2709 "must be between %d and %d units", 2710 HS_MIN_POLL_INTERVAL, HS_MAX_POLL_INTERVAL); 2711 2712 return (USB_FAILURE); 2713 } 2714 2715 /* Adjust high speed device polling interval */ 2716 interval = 2717 ehci_adjust_high_speed_polling_interval(ehcip, endpoint); 2718 2719 break; 2720 } 2721 2722 /* 2723 * If polling interval is greater than 32ms, 2724 * adjust polling interval equal to 32ms. 2725 */ 2726 if (interval > EHCI_NUM_INTR_QH_LISTS) { 2727 interval = EHCI_NUM_INTR_QH_LISTS; 2728 } 2729 2730 /* 2731 * Find the nearest power of 2 that's less 2732 * than interval. 2733 */ 2734 while ((ehci_pow_2(i)) <= interval) { 2735 i++; 2736 } 2737 2738 return (ehci_pow_2((i - 1))); 2739 } 2740 2741 2742 /* 2743 * ehci_adjust_high_speed_polling_interval: 2744 */ 2745 /* ARGSUSED */ 2746 static int 2747 ehci_adjust_high_speed_polling_interval( 2748 ehci_state_t *ehcip, 2749 usb_ep_descr_t *endpoint) 2750 { 2751 uint_t interval; 2752 2753 /* Get the polling interval */ 2754 interval = ehci_pow_2(endpoint->bInterval - 1); 2755 2756 /* 2757 * Convert polling interval from micro seconds 2758 * to milli seconds. 2759 */ 2760 if (interval <= EHCI_MAX_UFRAMES) { 2761 interval = 1; 2762 } else { 2763 interval = interval/EHCI_MAX_UFRAMES; 2764 } 2765 2766 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2767 "ehci_adjust_high_speed_polling_interval: " 2768 "High speed adjusted interval 0x%x", interval); 2769 2770 return (interval); 2771 } 2772 2773 2774 /* 2775 * ehci_lattice_height: 2776 * 2777 * Given the requested bandwidth, find the height in the tree at which the 2778 * nodes for this bandwidth fall. The height is measured as the number of 2779 * nodes from the leaf to the level specified by bandwidth The root of the 2780 * tree is at height TREE_HEIGHT. 2781 */ 2782 static uint_t 2783 ehci_lattice_height(uint_t interval) 2784 { 2785 return (TREE_HEIGHT - (ehci_log_2(interval))); 2786 } 2787 2788 2789 /* 2790 * ehci_lattice_parent: 2791 * 2792 * Given a node in the lattice, find the index of the parent node 2793 */ 2794 static uint_t 2795 ehci_lattice_parent(uint_t node) 2796 { 2797 if ((node % 2) == 0) { 2798 2799 return ((node/2) - 1); 2800 } else { 2801 2802 return ((node + 1)/2 - 1); 2803 } 2804 } 2805 2806 2807 /* 2808 * ehci_find_periodic_node: 2809 * 2810 * Based on the "real" array leaf node and interval, get the periodic node. 2811 */ 2812 static uint_t 2813 ehci_find_periodic_node(uint_t leaf, int interval) { 2814 uint_t lattice_leaf; 2815 uint_t height = ehci_lattice_height(interval); 2816 uint_t pnode; 2817 int i; 2818 2819 /* Get the leaf number in the lattice */ 2820 lattice_leaf = leaf + EHCI_NUM_INTR_QH_LISTS - 1; 2821 2822 /* Get the node in the lattice based on the height and leaf */ 2823 pnode = lattice_leaf; 2824 for (i = 0; i < height; i++) { 2825 pnode = ehci_lattice_parent(pnode); 2826 } 2827 2828 return (pnode); 2829 } 2830 2831 2832 /* 2833 * ehci_leftmost_leaf: 2834 * 2835 * Find the leftmost leaf in the subtree specified by the node. Height refers 2836 * to number of nodes from the bottom of the tree to the node, including the 2837 * node. 2838 * 2839 * The formula for a zero based tree is: 2840 * 2^H * Node + 2^H - 1 2841 * The leaf of the tree is an array, convert the number for the array. 2842 * Subtract the size of nodes not in the array 2843 * 2^H * Node + 2^H - 1 - (EHCI_NUM_INTR_QH_LISTS - 1) = 2844 * 2^H * Node + 2^H - EHCI_NUM_INTR_QH_LISTS = 2845 * 2^H * (Node + 1) - EHCI_NUM_INTR_QH_LISTS 2846 * 0 2847 * 1 2 2848 * 0 1 2 3 2849 */ 2850 static uint_t 2851 ehci_leftmost_leaf( 2852 uint_t node, 2853 uint_t height) 2854 { 2855 return ((ehci_pow_2(height) * (node + 1)) - EHCI_NUM_INTR_QH_LISTS); 2856 } 2857 2858 2859 /* 2860 * ehci_pow_2: 2861 * 2862 * Compute 2 to the power 2863 */ 2864 static uint_t 2865 ehci_pow_2(uint_t x) 2866 { 2867 if (x == 0) { 2868 2869 return (1); 2870 } else { 2871 2872 return (2 << (x - 1)); 2873 } 2874 } 2875 2876 2877 /* 2878 * ehci_log_2: 2879 * 2880 * Compute log base 2 of x 2881 */ 2882 static uint_t 2883 ehci_log_2(uint_t x) 2884 { 2885 int i = 0; 2886 2887 while (x != 1) { 2888 x = x >> 1; 2889 i++; 2890 } 2891 2892 return (i); 2893 } 2894 2895 2896 /* 2897 * ehci_find_bestfit_hs_mask: 2898 * 2899 * Find the smask and cmask in the bandwidth allocation, and update the 2900 * bandwidth allocation. 2901 */ 2902 static int 2903 ehci_find_bestfit_hs_mask( 2904 ehci_state_t *ehcip, 2905 uchar_t *smask, 2906 uint_t *pnode, 2907 usb_ep_descr_t *endpoint, 2908 uint_t bandwidth, 2909 int interval) 2910 { 2911 int i; 2912 uint_t elements, index; 2913 int array_leaf, best_array_leaf; 2914 uint_t node_bandwidth, best_node_bandwidth; 2915 uint_t leaf_count; 2916 uchar_t bw_mask; 2917 uchar_t best_smask; 2918 2919 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 2920 "ehci_find_bestfit_hs_mask: "); 2921 2922 /* Get all the valid smasks */ 2923 switch (ehci_pow_2(endpoint->bInterval - 1)) { 2924 case EHCI_INTR_1US_POLL: 2925 index = EHCI_1US_MASK_INDEX; 2926 elements = EHCI_INTR_1US_POLL; 2927 break; 2928 case EHCI_INTR_2US_POLL: 2929 index = EHCI_2US_MASK_INDEX; 2930 elements = EHCI_INTR_2US_POLL; 2931 break; 2932 case EHCI_INTR_4US_POLL: 2933 index = EHCI_4US_MASK_INDEX; 2934 elements = EHCI_INTR_4US_POLL; 2935 break; 2936 case EHCI_INTR_XUS_POLL: 2937 default: 2938 index = EHCI_XUS_MASK_INDEX; 2939 elements = EHCI_INTR_XUS_POLL; 2940 break; 2941 } 2942 2943 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 2944 2945 /* 2946 * Because of the way the leaves are setup, we will automatically 2947 * hit the leftmost leaf of every possible node with this interval. 2948 */ 2949 best_smask = 0x00; 2950 best_node_bandwidth = 0; 2951 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 2952 /* Find the bandwidth mask */ 2953 node_bandwidth = ehci_calculate_bw_availability_mask(ehcip, 2954 bandwidth, ehci_index[array_leaf], leaf_count, &bw_mask); 2955 2956 /* 2957 * If this node cannot support our requirements skip to the 2958 * next leaf. 2959 */ 2960 if (bw_mask == 0x00) { 2961 continue; 2962 } 2963 2964 /* 2965 * Now make sure our bandwidth requirements can be 2966 * satisfied with one of smasks in this node. 2967 */ 2968 *smask = 0x00; 2969 for (i = index; i < (index + elements); i++) { 2970 /* Check the start split mask value */ 2971 if (ehci_start_split_mask[index] & bw_mask) { 2972 *smask = ehci_start_split_mask[index]; 2973 break; 2974 } 2975 } 2976 2977 /* 2978 * If an appropriate smask is found save the information if: 2979 * o best_smask has not been found yet. 2980 * - or - 2981 * o This is the node with the least amount of bandwidth 2982 */ 2983 if ((*smask != 0x00) && 2984 ((best_smask == 0x00) || 2985 (best_node_bandwidth > node_bandwidth))) { 2986 2987 best_node_bandwidth = node_bandwidth; 2988 best_array_leaf = array_leaf; 2989 best_smask = *smask; 2990 } 2991 } 2992 2993 /* 2994 * If we find node that can handle the bandwidth populate the 2995 * appropriate variables and return success. 2996 */ 2997 if (best_smask) { 2998 *smask = best_smask; 2999 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3000 interval); 3001 ehci_update_bw_availability(ehcip, bandwidth, 3002 ehci_index[best_array_leaf], leaf_count, best_smask); 3003 3004 return (USB_SUCCESS); 3005 } 3006 3007 return (USB_FAILURE); 3008 } 3009 3010 3011 /* 3012 * ehci_find_bestfit_ls_intr_mask: 3013 * 3014 * Find the smask and cmask in the bandwidth allocation. 3015 */ 3016 static int 3017 ehci_find_bestfit_ls_intr_mask( 3018 ehci_state_t *ehcip, 3019 uchar_t *smask, 3020 uchar_t *cmask, 3021 uint_t *pnode, 3022 uint_t sbandwidth, 3023 uint_t cbandwidth, 3024 int interval) 3025 { 3026 int i; 3027 uint_t elements, index; 3028 int array_leaf, best_array_leaf; 3029 uint_t node_sbandwidth, node_cbandwidth; 3030 uint_t best_node_bandwidth; 3031 uint_t leaf_count; 3032 uchar_t bw_smask, bw_cmask; 3033 uchar_t best_smask, best_cmask; 3034 3035 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3036 "ehci_find_bestfit_ls_intr_mask: "); 3037 3038 /* For low and full speed devices */ 3039 index = EHCI_XUS_MASK_INDEX; 3040 elements = EHCI_INTR_4MS_POLL; 3041 3042 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3043 3044 /* 3045 * Because of the way the leaves are setup, we will automatically 3046 * hit the leftmost leaf of every possible node with this interval. 3047 */ 3048 best_smask = 0x00; 3049 best_node_bandwidth = 0; 3050 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3051 /* Find the bandwidth mask */ 3052 node_sbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3053 sbandwidth, ehci_index[array_leaf], leaf_count, &bw_smask); 3054 node_cbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3055 cbandwidth, ehci_index[array_leaf], leaf_count, &bw_cmask); 3056 3057 /* 3058 * If this node cannot support our requirements skip to the 3059 * next leaf. 3060 */ 3061 if ((bw_smask == 0x00) || (bw_cmask == 0x00)) { 3062 continue; 3063 } 3064 3065 /* 3066 * Now make sure our bandwidth requirements can be 3067 * satisfied with one of smasks in this node. 3068 */ 3069 *smask = 0x00; 3070 *cmask = 0x00; 3071 for (i = index; i < (index + elements); i++) { 3072 /* Check the start split mask value */ 3073 if ((ehci_start_split_mask[index] & bw_smask) && 3074 (ehci_intr_complete_split_mask[index] & bw_cmask)) { 3075 *smask = ehci_start_split_mask[index]; 3076 *cmask = ehci_intr_complete_split_mask[index]; 3077 break; 3078 } 3079 } 3080 3081 /* 3082 * If an appropriate smask is found save the information if: 3083 * o best_smask has not been found yet. 3084 * - or - 3085 * o This is the node with the least amount of bandwidth 3086 */ 3087 if ((*smask != 0x00) && 3088 ((best_smask == 0x00) || 3089 (best_node_bandwidth > 3090 (node_sbandwidth + node_cbandwidth)))) { 3091 best_node_bandwidth = node_sbandwidth + node_cbandwidth; 3092 best_array_leaf = array_leaf; 3093 best_smask = *smask; 3094 best_cmask = *cmask; 3095 } 3096 } 3097 3098 /* 3099 * If we find node that can handle the bandwidth populate the 3100 * appropriate variables and return success. 3101 */ 3102 if (best_smask) { 3103 *smask = best_smask; 3104 *cmask = best_cmask; 3105 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3106 interval); 3107 ehci_update_bw_availability(ehcip, sbandwidth, 3108 ehci_index[best_array_leaf], leaf_count, best_smask); 3109 ehci_update_bw_availability(ehcip, cbandwidth, 3110 ehci_index[best_array_leaf], leaf_count, best_cmask); 3111 3112 return (USB_SUCCESS); 3113 } 3114 3115 return (USB_FAILURE); 3116 } 3117 3118 3119 /* 3120 * ehci_find_bestfit_sitd_in_mask: 3121 * 3122 * Find the smask and cmask in the bandwidth allocation. 3123 */ 3124 static int 3125 ehci_find_bestfit_sitd_in_mask( 3126 ehci_state_t *ehcip, 3127 uchar_t *smask, 3128 uchar_t *cmask, 3129 uint_t *pnode, 3130 uint_t sbandwidth, 3131 uint_t cbandwidth, 3132 int interval) 3133 { 3134 int i, uFrames, found; 3135 int array_leaf, best_array_leaf; 3136 uint_t node_sbandwidth, node_cbandwidth; 3137 uint_t best_node_bandwidth; 3138 uint_t leaf_count; 3139 uchar_t bw_smask, bw_cmask; 3140 uchar_t best_smask, best_cmask; 3141 3142 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3143 "ehci_find_bestfit_sitd_in_mask: "); 3144 3145 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3146 3147 /* 3148 * Because of the way the leaves are setup, we will automatically 3149 * hit the leftmost leaf of every possible node with this interval. 3150 * You may only send MAX_UFRAME_SITD_XFER raw bits per uFrame. 3151 */ 3152 /* 3153 * Need to add an additional 2 uFrames, if the "L"ast 3154 * complete split is before uFrame 6. See section 3155 * 11.8.4 in USB 2.0 Spec. Currently we do not support 3156 * the "Back Ptr" which means we support on IN of 3157 * ~4*MAX_UFRAME_SITD_XFER bandwidth/ 3158 */ 3159 uFrames = (cbandwidth / MAX_UFRAME_SITD_XFER) + 2; 3160 if (cbandwidth % MAX_UFRAME_SITD_XFER) { 3161 uFrames++; 3162 } 3163 if (uFrames > 6) { 3164 3165 return (USB_FAILURE); 3166 } 3167 *smask = 0x1; 3168 *cmask = 0x00; 3169 for (i = 0; i < uFrames; i++) { 3170 *cmask = *cmask << 1; 3171 *cmask |= 0x1; 3172 } 3173 /* cmask must start 2 frames after the smask */ 3174 *cmask = *cmask << 2; 3175 3176 found = 0; 3177 best_smask = 0x00; 3178 best_node_bandwidth = 0; 3179 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3180 node_sbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3181 sbandwidth, ehci_index[array_leaf], leaf_count, &bw_smask); 3182 node_cbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3183 MAX_UFRAME_SITD_XFER, ehci_index[array_leaf], leaf_count, 3184 &bw_cmask); 3185 3186 /* 3187 * If this node cannot support our requirements skip to the 3188 * next leaf. 3189 */ 3190 if ((bw_smask == 0x00) || (bw_cmask == 0x00)) { 3191 continue; 3192 } 3193 3194 for (i = 0; i < (EHCI_MAX_UFRAMES - uFrames - 2); i++) { 3195 if ((*smask & bw_smask) && (*cmask & bw_cmask)) { 3196 found = 1; 3197 break; 3198 } 3199 *smask = *smask << 1; 3200 *cmask = *cmask << 1; 3201 } 3202 3203 /* 3204 * If an appropriate smask is found save the information if: 3205 * o best_smask has not been found yet. 3206 * - or - 3207 * o This is the node with the least amount of bandwidth 3208 */ 3209 if (found && 3210 ((best_smask == 0x00) || 3211 (best_node_bandwidth > 3212 (node_sbandwidth + node_cbandwidth)))) { 3213 best_node_bandwidth = node_sbandwidth + node_cbandwidth; 3214 best_array_leaf = array_leaf; 3215 best_smask = *smask; 3216 best_cmask = *cmask; 3217 } 3218 } 3219 3220 /* 3221 * If we find node that can handle the bandwidth populate the 3222 * appropriate variables and return success. 3223 */ 3224 if (best_smask) { 3225 *smask = best_smask; 3226 *cmask = best_cmask; 3227 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3228 interval); 3229 ehci_update_bw_availability(ehcip, sbandwidth, 3230 ehci_index[best_array_leaf], leaf_count, best_smask); 3231 ehci_update_bw_availability(ehcip, MAX_UFRAME_SITD_XFER, 3232 ehci_index[best_array_leaf], leaf_count, best_cmask); 3233 3234 return (USB_SUCCESS); 3235 } 3236 3237 return (USB_FAILURE); 3238 } 3239 3240 3241 /* 3242 * ehci_find_bestfit_sitd_out_mask: 3243 * 3244 * Find the smask in the bandwidth allocation. 3245 */ 3246 static int 3247 ehci_find_bestfit_sitd_out_mask( 3248 ehci_state_t *ehcip, 3249 uchar_t *smask, 3250 uint_t *pnode, 3251 uint_t sbandwidth, 3252 int interval) 3253 { 3254 int i, uFrames, found; 3255 int array_leaf, best_array_leaf; 3256 uint_t node_sbandwidth; 3257 uint_t best_node_bandwidth; 3258 uint_t leaf_count; 3259 uchar_t bw_smask; 3260 uchar_t best_smask; 3261 3262 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3263 "ehci_find_bestfit_sitd_out_mask: "); 3264 3265 leaf_count = EHCI_NUM_INTR_QH_LISTS/interval; 3266 3267 /* 3268 * Because of the way the leaves are setup, we will automatically 3269 * hit the leftmost leaf of every possible node with this interval. 3270 * You may only send MAX_UFRAME_SITD_XFER raw bits per uFrame. 3271 */ 3272 *smask = 0x00; 3273 uFrames = sbandwidth / MAX_UFRAME_SITD_XFER; 3274 if (sbandwidth % MAX_UFRAME_SITD_XFER) { 3275 uFrames++; 3276 } 3277 for (i = 0; i < uFrames; i++) { 3278 *smask = *smask << 1; 3279 *smask |= 0x1; 3280 } 3281 3282 found = 0; 3283 best_smask = 0x00; 3284 best_node_bandwidth = 0; 3285 for (array_leaf = 0; array_leaf < interval; array_leaf++) { 3286 node_sbandwidth = ehci_calculate_bw_availability_mask(ehcip, 3287 MAX_UFRAME_SITD_XFER, ehci_index[array_leaf], leaf_count, 3288 &bw_smask); 3289 3290 /* 3291 * If this node cannot support our requirements skip to the 3292 * next leaf. 3293 */ 3294 if (bw_smask == 0x00) { 3295 continue; 3296 } 3297 3298 /* You cannot have a start split on the 8th uFrame */ 3299 for (i = 0; (*smask & 0x80) == 0; i++) { 3300 if (*smask & bw_smask) { 3301 found = 1; 3302 break; 3303 } 3304 *smask = *smask << 1; 3305 } 3306 3307 /* 3308 * If an appropriate smask is found save the information if: 3309 * o best_smask has not been found yet. 3310 * - or - 3311 * o This is the node with the least amount of bandwidth 3312 */ 3313 if (found && 3314 ((best_smask == 0x00) || 3315 (best_node_bandwidth > node_sbandwidth))) { 3316 best_node_bandwidth = node_sbandwidth; 3317 best_array_leaf = array_leaf; 3318 best_smask = *smask; 3319 } 3320 } 3321 3322 /* 3323 * If we find node that can handle the bandwidth populate the 3324 * appropriate variables and return success. 3325 */ 3326 if (best_smask) { 3327 *smask = best_smask; 3328 *pnode = ehci_find_periodic_node(ehci_index[best_array_leaf], 3329 interval); 3330 ehci_update_bw_availability(ehcip, MAX_UFRAME_SITD_XFER, 3331 ehci_index[best_array_leaf], leaf_count, best_smask); 3332 3333 return (USB_SUCCESS); 3334 } 3335 3336 return (USB_FAILURE); 3337 } 3338 3339 3340 /* 3341 * ehci_calculate_bw_availability_mask: 3342 * 3343 * Returns the "total bandwidth used" in this node. 3344 * Populates bw_mask with the uFrames that can support the bandwidth. 3345 * 3346 * If all the Frames cannot support this bandwidth, then bw_mask 3347 * will return 0x00 and the "total bandwidth used" will be invalid. 3348 */ 3349 static uint_t 3350 ehci_calculate_bw_availability_mask( 3351 ehci_state_t *ehcip, 3352 uint_t bandwidth, 3353 int leaf, 3354 int leaf_count, 3355 uchar_t *bw_mask) 3356 { 3357 int i, j; 3358 uchar_t bw_uframe; 3359 int uframe_total; 3360 ehci_frame_bandwidth_t *fbp; 3361 uint_t total_bandwidth = 0; 3362 3363 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3364 "ehci_calculate_bw_availability_mask: leaf %d leaf count %d", 3365 leaf, leaf_count); 3366 3367 /* Start by saying all uFrames are available */ 3368 *bw_mask = 0xFF; 3369 3370 for (i = 0; (i < leaf_count) || (*bw_mask == 0x00); i++) { 3371 fbp = &ehcip->ehci_frame_bandwidth[leaf + i]; 3372 3373 total_bandwidth += fbp->ehci_allocated_frame_bandwidth; 3374 3375 for (j = 0; j < EHCI_MAX_UFRAMES; j++) { 3376 /* 3377 * If the uFrame in bw_mask is available check to see if 3378 * it can support the additional bandwidth. 3379 */ 3380 bw_uframe = (*bw_mask & (0x1 << j)); 3381 uframe_total = 3382 fbp->ehci_micro_frame_bandwidth[j] + 3383 bandwidth; 3384 if ((bw_uframe) && 3385 (uframe_total > HS_PERIODIC_BANDWIDTH)) { 3386 *bw_mask = *bw_mask & ~bw_uframe; 3387 } 3388 } 3389 } 3390 3391 USB_DPRINTF_L4(PRINT_MASK_BW, ehcip->ehci_log_hdl, 3392 "ehci_calculate_bw_availability_mask: bandwidth mask 0x%x", 3393 *bw_mask); 3394 3395 return (total_bandwidth); 3396 } 3397 3398 3399 /* 3400 * ehci_update_bw_availability: 3401 * 3402 * The leftmost leaf needs to be in terms of array position and 3403 * not the actual lattice position. 3404 */ 3405 static void 3406 ehci_update_bw_availability( 3407 ehci_state_t *ehcip, 3408 int bandwidth, 3409 int leftmost_leaf, 3410 int leaf_count, 3411 uchar_t mask) 3412 { 3413 int i, j; 3414 ehci_frame_bandwidth_t *fbp; 3415 int uFrame_bandwidth[8]; 3416 3417 USB_DPRINTF_L4(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3418 "ehci_update_bw_availability: " 3419 "leaf %d count %d bandwidth 0x%x mask 0x%x", 3420 leftmost_leaf, leaf_count, bandwidth, mask); 3421 3422 ASSERT(leftmost_leaf < 32); 3423 ASSERT(leftmost_leaf >= 0); 3424 3425 for (j = 0; j < EHCI_MAX_UFRAMES; j++) { 3426 if (mask & 0x1) { 3427 uFrame_bandwidth[j] = bandwidth; 3428 } else { 3429 uFrame_bandwidth[j] = 0; 3430 } 3431 3432 mask = mask >> 1; 3433 } 3434 3435 /* Updated all the effected leafs with the bandwidth */ 3436 for (i = 0; i < leaf_count; i++) { 3437 fbp = &ehcip->ehci_frame_bandwidth[leftmost_leaf + i]; 3438 3439 for (j = 0; j < EHCI_MAX_UFRAMES; j++) { 3440 fbp->ehci_micro_frame_bandwidth[j] += 3441 uFrame_bandwidth[j]; 3442 fbp->ehci_allocated_frame_bandwidth += 3443 uFrame_bandwidth[j]; 3444 } 3445 } 3446 } 3447 3448 /* 3449 * Miscellaneous functions 3450 */ 3451 3452 /* 3453 * ehci_obtain_state: 3454 * 3455 * NOTE: This function is also called from POLLED MODE. 3456 */ 3457 ehci_state_t * 3458 ehci_obtain_state(dev_info_t *dip) 3459 { 3460 int instance = ddi_get_instance(dip); 3461 3462 ehci_state_t *state = ddi_get_soft_state(ehci_statep, instance); 3463 3464 ASSERT(state != NULL); 3465 3466 return (state); 3467 } 3468 3469 3470 /* 3471 * ehci_state_is_operational: 3472 * 3473 * Check the Host controller state and return proper values. 3474 */ 3475 int 3476 ehci_state_is_operational(ehci_state_t *ehcip) 3477 { 3478 int val; 3479 3480 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3481 3482 switch (ehcip->ehci_hc_soft_state) { 3483 case EHCI_CTLR_INIT_STATE: 3484 case EHCI_CTLR_SUSPEND_STATE: 3485 val = USB_FAILURE; 3486 break; 3487 case EHCI_CTLR_OPERATIONAL_STATE: 3488 val = USB_SUCCESS; 3489 break; 3490 case EHCI_CTLR_ERROR_STATE: 3491 val = USB_HC_HARDWARE_ERROR; 3492 break; 3493 default: 3494 val = USB_FAILURE; 3495 break; 3496 } 3497 3498 return (val); 3499 } 3500 3501 3502 /* 3503 * ehci_do_soft_reset 3504 * 3505 * Do soft reset of ehci host controller. 3506 */ 3507 int 3508 ehci_do_soft_reset(ehci_state_t *ehcip) 3509 { 3510 usb_frame_number_t before_frame_number, after_frame_number; 3511 ehci_regs_t *ehci_save_regs; 3512 3513 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3514 3515 /* Increment host controller error count */ 3516 ehcip->ehci_hc_error++; 3517 3518 USB_DPRINTF_L3(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3519 "ehci_do_soft_reset:" 3520 "Reset ehci host controller 0x%x", ehcip->ehci_hc_error); 3521 3522 /* 3523 * Allocate space for saving current Host Controller 3524 * registers. Don't do any recovery if allocation 3525 * fails. 3526 */ 3527 ehci_save_regs = (ehci_regs_t *) 3528 kmem_zalloc(sizeof (ehci_regs_t), KM_NOSLEEP); 3529 3530 if (ehci_save_regs == NULL) { 3531 USB_DPRINTF_L2(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3532 "ehci_do_soft_reset: kmem_zalloc failed"); 3533 3534 return (USB_FAILURE); 3535 } 3536 3537 /* Save current ehci registers */ 3538 ehci_save_regs->ehci_command = Get_OpReg(ehci_command); 3539 ehci_save_regs->ehci_interrupt = Get_OpReg(ehci_interrupt); 3540 ehci_save_regs->ehci_ctrl_segment = Get_OpReg(ehci_ctrl_segment); 3541 ehci_save_regs->ehci_async_list_addr = Get_OpReg(ehci_async_list_addr); 3542 ehci_save_regs->ehci_config_flag = Get_OpReg(ehci_config_flag); 3543 ehci_save_regs->ehci_periodic_list_base = 3544 Get_OpReg(ehci_periodic_list_base); 3545 3546 USB_DPRINTF_L4(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3547 "ehci_do_soft_reset: Save reg = 0x%p", ehci_save_regs); 3548 3549 /* Disable all list processing and interrupts */ 3550 Set_OpReg(ehci_command, Get_OpReg(ehci_command) & 3551 ~(EHCI_CMD_ASYNC_SCHED_ENABLE | EHCI_CMD_PERIODIC_SCHED_ENABLE)); 3552 3553 /* Disable all EHCI interrupts */ 3554 Set_OpReg(ehci_interrupt, 0); 3555 3556 /* Wait for few milliseconds */ 3557 drv_usecwait(EHCI_SOF_TIMEWAIT); 3558 3559 /* Do light soft reset of ehci host controller */ 3560 Set_OpReg(ehci_command, 3561 Get_OpReg(ehci_command) | EHCI_CMD_LIGHT_HC_RESET); 3562 3563 USB_DPRINTF_L4(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3564 "ehci_do_soft_reset: Reset in progress"); 3565 3566 /* Wait for reset to complete */ 3567 drv_usecwait(EHCI_RESET_TIMEWAIT); 3568 3569 /* 3570 * Restore previous saved EHCI register value 3571 * into the current EHCI registers. 3572 */ 3573 Set_OpReg(ehci_ctrl_segment, (uint32_t) 3574 ehci_save_regs->ehci_ctrl_segment); 3575 3576 Set_OpReg(ehci_periodic_list_base, (uint32_t) 3577 ehci_save_regs->ehci_periodic_list_base); 3578 3579 Set_OpReg(ehci_async_list_addr, (uint32_t) 3580 ehci_save_regs->ehci_async_list_addr); 3581 3582 Set_OpReg(ehci_config_flag, (uint32_t) 3583 ehci_save_regs->ehci_config_flag); 3584 3585 /* Enable both Asynchronous and Periodic Schedule if necessary */ 3586 ehci_toggle_scheduler(ehcip); 3587 3588 /* 3589 * Set ehci_interrupt to enable all interrupts except Root 3590 * Hub Status change and frame list rollover interrupts. 3591 */ 3592 Set_OpReg(ehci_interrupt, EHCI_INTR_HOST_SYSTEM_ERROR | 3593 EHCI_INTR_FRAME_LIST_ROLLOVER | 3594 EHCI_INTR_USB_ERROR | 3595 EHCI_INTR_USB); 3596 3597 /* 3598 * Deallocate the space that allocated for saving 3599 * HC registers. 3600 */ 3601 kmem_free((void *) ehci_save_regs, sizeof (ehci_regs_t)); 3602 3603 /* 3604 * Set the desired interrupt threshold, frame list size (if 3605 * applicable) and turn EHCI host controller. 3606 */ 3607 Set_OpReg(ehci_command, ((Get_OpReg(ehci_command) & 3608 ~EHCI_CMD_INTR_THRESHOLD) | 3609 (EHCI_CMD_01_INTR | EHCI_CMD_HOST_CTRL_RUN))); 3610 3611 /* Wait 10ms for EHCI to start sending SOF */ 3612 drv_usecwait(EHCI_RESET_TIMEWAIT); 3613 3614 /* 3615 * Get the current usb frame number before waiting for 3616 * few milliseconds. 3617 */ 3618 before_frame_number = ehci_get_current_frame_number(ehcip); 3619 3620 /* Wait for few milliseconds */ 3621 drv_usecwait(EHCI_SOF_TIMEWAIT); 3622 3623 /* 3624 * Get the current usb frame number after waiting for 3625 * few milliseconds. 3626 */ 3627 after_frame_number = ehci_get_current_frame_number(ehcip); 3628 3629 USB_DPRINTF_L4(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3630 "ehci_do_soft_reset: Before Frame Number 0x%llx " 3631 "After Frame Number 0x%llx", 3632 before_frame_number, after_frame_number); 3633 3634 if ((after_frame_number <= before_frame_number) && 3635 (Get_OpReg(ehci_status) & EHCI_STS_HOST_CTRL_HALTED)) { 3636 3637 USB_DPRINTF_L2(PRINT_MASK_INTR, ehcip->ehci_log_hdl, 3638 "ehci_do_soft_reset: Soft reset failed"); 3639 3640 return (USB_FAILURE); 3641 } 3642 3643 return (USB_SUCCESS); 3644 } 3645 3646 3647 /* 3648 * ehci_get_xfer_attrs: 3649 * 3650 * Get the attributes of a particular xfer. 3651 * 3652 * NOTE: This function is also called from POLLED MODE. 3653 */ 3654 usb_req_attrs_t 3655 ehci_get_xfer_attrs( 3656 ehci_state_t *ehcip, 3657 ehci_pipe_private_t *pp, 3658 ehci_trans_wrapper_t *tw) 3659 { 3660 usb_ep_descr_t *eptd = &pp->pp_pipe_handle->p_ep; 3661 usb_req_attrs_t attrs = USB_ATTRS_NONE; 3662 3663 USB_DPRINTF_L4(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3664 "ehci_get_xfer_attrs:"); 3665 3666 switch (eptd->bmAttributes & USB_EP_ATTR_MASK) { 3667 case USB_EP_ATTR_CONTROL: 3668 attrs = ((usb_ctrl_req_t *) 3669 tw->tw_curr_xfer_reqp)->ctrl_attributes; 3670 break; 3671 case USB_EP_ATTR_BULK: 3672 attrs = ((usb_bulk_req_t *) 3673 tw->tw_curr_xfer_reqp)->bulk_attributes; 3674 break; 3675 case USB_EP_ATTR_INTR: 3676 attrs = ((usb_intr_req_t *) 3677 tw->tw_curr_xfer_reqp)->intr_attributes; 3678 break; 3679 } 3680 3681 return (attrs); 3682 } 3683 3684 3685 /* 3686 * ehci_get_current_frame_number: 3687 * 3688 * Get the current software based usb frame number. 3689 */ 3690 usb_frame_number_t 3691 ehci_get_current_frame_number(ehci_state_t *ehcip) 3692 { 3693 usb_frame_number_t usb_frame_number; 3694 usb_frame_number_t ehci_fno, micro_frame_number; 3695 3696 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3697 3698 ehci_fno = ehcip->ehci_fno; 3699 micro_frame_number = Get_OpReg(ehci_frame_index) & 0x3FFF; 3700 3701 /* 3702 * Calculate current software based usb frame number. 3703 * 3704 * This code accounts for the fact that frame number is 3705 * updated by the Host Controller before the ehci driver 3706 * gets an FrameListRollover interrupt that will adjust 3707 * Frame higher part. 3708 * 3709 * Refer ehci specification 1.0, section 2.3.2, page 21. 3710 */ 3711 micro_frame_number = ((micro_frame_number & 0x1FFF) | 3712 ehci_fno) + (((micro_frame_number & 0x3FFF) ^ 3713 ehci_fno) & 0x2000); 3714 3715 /* 3716 * Micro Frame number is equivalent to 125 usec. Eight 3717 * Micro Frame numbers are equivalent to one millsecond 3718 * or one usb frame number. 3719 */ 3720 usb_frame_number = micro_frame_number >> 3721 EHCI_uFRAMES_PER_USB_FRAME_SHIFT; 3722 3723 USB_DPRINTF_L4(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3724 "ehci_get_current_frame_number: " 3725 "Current usb uframe number = 0x%llx " 3726 "Current usb frame number = 0x%llx", 3727 micro_frame_number, usb_frame_number); 3728 3729 return (usb_frame_number); 3730 } 3731 3732 3733 /* 3734 * ehci_cpr_cleanup: 3735 * 3736 * Cleanup ehci state and other ehci specific informations across 3737 * Check Point Resume (CPR). 3738 */ 3739 static void 3740 ehci_cpr_cleanup(ehci_state_t *ehcip) 3741 { 3742 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3743 3744 /* Reset software part of usb frame number */ 3745 ehcip->ehci_fno = 0; 3746 } 3747 3748 3749 /* 3750 * ehci_wait_for_sof: 3751 * 3752 * Wait for couple of SOF interrupts 3753 */ 3754 int 3755 ehci_wait_for_sof(ehci_state_t *ehcip) 3756 { 3757 usb_frame_number_t before_frame_number, after_frame_number; 3758 int error = USB_SUCCESS; 3759 3760 USB_DPRINTF_L4(PRINT_MASK_LISTS, 3761 ehcip->ehci_log_hdl, "ehci_wait_for_sof"); 3762 3763 ASSERT(mutex_owned(&ehcip->ehci_int_mutex)); 3764 3765 error = ehci_state_is_operational(ehcip); 3766 3767 if (error != USB_SUCCESS) { 3768 3769 return (error); 3770 } 3771 3772 /* Get the current usb frame number before waiting for two SOFs */ 3773 before_frame_number = ehci_get_current_frame_number(ehcip); 3774 3775 mutex_exit(&ehcip->ehci_int_mutex); 3776 3777 /* Wait for few milliseconds */ 3778 delay(drv_usectohz(EHCI_SOF_TIMEWAIT)); 3779 3780 mutex_enter(&ehcip->ehci_int_mutex); 3781 3782 /* Get the current usb frame number after woken up */ 3783 after_frame_number = ehci_get_current_frame_number(ehcip); 3784 3785 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3786 "ehci_wait_for_sof: framenumber: before 0x%llx " 3787 "after 0x%llx", before_frame_number, after_frame_number); 3788 3789 /* Return failure, if usb frame number has not been changed */ 3790 if (after_frame_number <= before_frame_number) { 3791 3792 if ((ehci_do_soft_reset(ehcip)) != USB_SUCCESS) { 3793 3794 USB_DPRINTF_L0(PRINT_MASK_LISTS, 3795 ehcip->ehci_log_hdl, "No SOF interrupts"); 3796 3797 /* Set host controller soft state to error */ 3798 ehcip->ehci_hc_soft_state = EHCI_CTLR_ERROR_STATE; 3799 3800 return (USB_FAILURE); 3801 } 3802 3803 /* Get new usb frame number */ 3804 after_frame_number = before_frame_number = 3805 ehci_get_current_frame_number(ehcip); 3806 } 3807 3808 ASSERT(after_frame_number > before_frame_number); 3809 3810 return (USB_SUCCESS); 3811 } 3812 3813 3814 /* 3815 * ehci_toggle_scheduler: 3816 * 3817 * Turn scheduler based on pipe open count. 3818 */ 3819 void 3820 ehci_toggle_scheduler(ehci_state_t *ehcip) { 3821 uint_t temp_reg, cmd_reg; 3822 3823 cmd_reg = Get_OpReg(ehci_command); 3824 temp_reg = cmd_reg; 3825 3826 /* 3827 * Enable/Disable asynchronous scheduler, and 3828 * turn on/off async list door bell 3829 */ 3830 if (ehcip->ehci_open_async_count) { 3831 if (!(cmd_reg & EHCI_CMD_ASYNC_SCHED_ENABLE)) { 3832 /* 3833 * For some reason this address might get nulled out by 3834 * the ehci chip. Set it here just in case it is null. 3835 */ 3836 Set_OpReg(ehci_async_list_addr, 3837 ehci_qh_cpu_to_iommu(ehcip, 3838 ehcip->ehci_head_of_async_sched_list)); 3839 } 3840 cmd_reg |= EHCI_CMD_ASYNC_SCHED_ENABLE; 3841 } else { 3842 cmd_reg &= ~EHCI_CMD_ASYNC_SCHED_ENABLE; 3843 } 3844 3845 if (ehcip->ehci_open_periodic_count) { 3846 if (!(cmd_reg & EHCI_CMD_PERIODIC_SCHED_ENABLE)) { 3847 /* 3848 * For some reason this address get's nulled out by 3849 * the ehci chip. Set it here just in case it is null. 3850 */ 3851 Set_OpReg(ehci_periodic_list_base, 3852 (uint32_t)(ehcip->ehci_pflt_cookie.dmac_address & 3853 0xFFFFF000)); 3854 } 3855 cmd_reg |= EHCI_CMD_PERIODIC_SCHED_ENABLE; 3856 } else { 3857 cmd_reg &= ~EHCI_CMD_PERIODIC_SCHED_ENABLE; 3858 } 3859 3860 /* Just an optimization */ 3861 if (temp_reg != cmd_reg) { 3862 Set_OpReg(ehci_command, cmd_reg); 3863 } 3864 } 3865 3866 /* 3867 * ehci print functions 3868 */ 3869 3870 /* 3871 * ehci_print_caps: 3872 */ 3873 void 3874 ehci_print_caps(ehci_state_t *ehcip) 3875 { 3876 uint_t i; 3877 3878 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3879 "\n\tUSB 2.0 Host Controller Characteristics\n"); 3880 3881 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3882 "Caps Length: 0x%x Version: 0x%x\n", 3883 Get_8Cap(ehci_caps_length), Get_16Cap(ehci_version)); 3884 3885 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3886 "Structural Parameters\n"); 3887 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3888 "Port indicators: %s", (Get_Cap(ehci_hcs_params) & 3889 EHCI_HCS_PORT_INDICATOR) ? "Yes" : "No"); 3890 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3891 "No of Classic host controllers: 0x%x", 3892 (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_COMP_CTRLS) 3893 >> EHCI_HCS_NUM_COMP_CTRL_SHIFT); 3894 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3895 "No of ports per Classic host controller: 0x%x", 3896 (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS_CC) 3897 >> EHCI_HCS_NUM_PORTS_CC_SHIFT); 3898 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3899 "Port routing rules: %s", (Get_Cap(ehci_hcs_params) & 3900 EHCI_HCS_PORT_ROUTING_RULES) ? "Yes" : "No"); 3901 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3902 "Port power control: %s", (Get_Cap(ehci_hcs_params) & 3903 EHCI_HCS_PORT_POWER_CONTROL) ? "Yes" : "No"); 3904 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3905 "No of root hub ports: 0x%x\n", 3906 Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS); 3907 3908 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3909 "Capability Parameters\n"); 3910 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3911 "EHCI extended capability: %s", (Get_Cap(ehci_hcc_params) & 3912 EHCI_HCC_EECP) ? "Yes" : "No"); 3913 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3914 "Isoch schedule threshold: 0x%x", 3915 Get_Cap(ehci_hcc_params) & EHCI_HCC_ISOCH_SCHED_THRESHOLD); 3916 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3917 "Async schedule park capability: %s", (Get_Cap(ehci_hcc_params) & 3918 EHCI_HCC_ASYNC_SCHED_PARK_CAP) ? "Yes" : "No"); 3919 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3920 "Programmable frame list flag: %s", (Get_Cap(ehci_hcc_params) & 3921 EHCI_HCC_PROG_FRAME_LIST_FLAG) ? "256/512/1024" : "1024"); 3922 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3923 "64bit addressing capability: %s\n", (Get_Cap(ehci_hcc_params) & 3924 EHCI_HCC_64BIT_ADDR_CAP) ? "Yes" : "No"); 3925 3926 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3927 "Classic Port Route Description"); 3928 3929 for (i = 0; i < (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS); i++) { 3930 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3931 "\tPort Route 0x%x: 0x%x", i, Get_8Cap(ehci_port_route[i])); 3932 } 3933 } 3934 3935 3936 /* 3937 * ehci_print_regs: 3938 */ 3939 void 3940 ehci_print_regs(ehci_state_t *ehcip) 3941 { 3942 uint_t i; 3943 3944 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3945 "\n\tEHCI%d Operational Registers\n", 3946 ddi_get_instance(ehcip->ehci_dip)); 3947 3948 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3949 "Command: 0x%x Status: 0x%x", 3950 Get_OpReg(ehci_command), Get_OpReg(ehci_status)); 3951 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3952 "Interrupt: 0x%x Frame Index: 0x%x", 3953 Get_OpReg(ehci_interrupt), Get_OpReg(ehci_frame_index)); 3954 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3955 "Control Segment: 0x%x Periodic List Base: 0x%x", 3956 Get_OpReg(ehci_ctrl_segment), Get_OpReg(ehci_periodic_list_base)); 3957 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3958 "Async List Addr: 0x%x Config Flag: 0x%x", 3959 Get_OpReg(ehci_async_list_addr), Get_OpReg(ehci_config_flag)); 3960 3961 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3962 "Root Hub Port Status"); 3963 3964 for (i = 0; i < (Get_Cap(ehci_hcs_params) & EHCI_HCS_NUM_PORTS); i++) { 3965 USB_DPRINTF_L3(PRINT_MASK_ATTA, ehcip->ehci_log_hdl, 3966 "\tPort Status 0x%x: 0x%x ", i, 3967 Get_OpReg(ehci_rh_port_status[i])); 3968 } 3969 } 3970 3971 3972 /* 3973 * ehci_print_qh: 3974 */ 3975 void 3976 ehci_print_qh( 3977 ehci_state_t *ehcip, 3978 ehci_qh_t *qh) 3979 { 3980 uint_t i; 3981 3982 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3983 "ehci_print_qh: qh = 0x%p", (void *)qh); 3984 3985 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3986 "\tqh_link_ptr: 0x%x ", Get_QH(qh->qh_link_ptr)); 3987 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3988 "\tqh_ctrl: 0x%x ", Get_QH(qh->qh_ctrl)); 3989 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3990 "\tqh_split_ctrl: 0x%x ", Get_QH(qh->qh_split_ctrl)); 3991 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3992 "\tqh_curr_qtd: 0x%x ", Get_QH(qh->qh_curr_qtd)); 3993 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3994 "\tqh_next_qtd: 0x%x ", Get_QH(qh->qh_next_qtd)); 3995 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3996 "\tqh_alt_next_qtd: 0x%x ", Get_QH(qh->qh_alt_next_qtd)); 3997 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 3998 "\tqh_status: 0x%x ", Get_QH(qh->qh_status)); 3999 4000 for (i = 0; i < 5; i++) { 4001 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4002 "\tqh_buf[%d]: 0x%x ", i, Get_QH(qh->qh_buf[i])); 4003 } 4004 4005 for (i = 0; i < 5; i++) { 4006 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4007 "\tqh_buf_high[%d]: 0x%x ", 4008 i, Get_QH(qh->qh_buf_high[i])); 4009 } 4010 4011 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4012 "\tqh_dummy_qtd: 0x%x ", Get_QH(qh->qh_dummy_qtd)); 4013 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4014 "\tqh_prev: 0x%x ", Get_QH(qh->qh_prev)); 4015 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4016 "\tqh_state: 0x%x ", Get_QH(qh->qh_state)); 4017 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4018 "\tqh_reclaim_next: 0x%x ", Get_QH(qh->qh_reclaim_next)); 4019 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4020 "\tqh_reclaim_frame: 0x%x ", Get_QH(qh->qh_reclaim_frame)); 4021 } 4022 4023 4024 /* 4025 * ehci_print_qtd: 4026 */ 4027 void 4028 ehci_print_qtd( 4029 ehci_state_t *ehcip, 4030 ehci_qtd_t *qtd) 4031 { 4032 uint_t i; 4033 4034 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4035 "ehci_print_qtd: qtd = 0x%p", (void *)qtd); 4036 4037 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4038 "\tqtd_next_qtd: 0x%x ", Get_QTD(qtd->qtd_next_qtd)); 4039 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4040 "\tqtd_alt_next_qtd: 0x%x ", Get_QTD(qtd->qtd_alt_next_qtd)); 4041 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4042 "\tqtd_ctrl: 0x%x ", Get_QTD(qtd->qtd_ctrl)); 4043 4044 for (i = 0; i < 5; i++) { 4045 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4046 "\tqtd_buf[%d]: 0x%x ", i, Get_QTD(qtd->qtd_buf[i])); 4047 } 4048 4049 for (i = 0; i < 5; i++) { 4050 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4051 "\tqtd_buf_high[%d]: 0x%x ", 4052 i, Get_QTD(qtd->qtd_buf_high[i])); 4053 } 4054 4055 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4056 "\tqtd_trans_wrapper: 0x%x ", Get_QTD(qtd->qtd_trans_wrapper)); 4057 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4058 "\tqtd_tw_next_qtd: 0x%x ", Get_QTD(qtd->qtd_tw_next_qtd)); 4059 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4060 "\tqtd_active_qtd_next: 0x%x ", Get_QTD(qtd->qtd_active_qtd_next)); 4061 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4062 "\tqtd_active_qtd_prev: 0x%x ", Get_QTD(qtd->qtd_active_qtd_prev)); 4063 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4064 "\tqtd_state: 0x%x ", Get_QTD(qtd->qtd_state)); 4065 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4066 "\tqtd_ctrl_phase: 0x%x ", Get_QTD(qtd->qtd_ctrl_phase)); 4067 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4068 "\tqtd_xfer_addr: 0x%x ", Get_QTD(qtd->qtd_xfer_addr)); 4069 USB_DPRINTF_L3(PRINT_MASK_LISTS, ehcip->ehci_log_hdl, 4070 "\tqtd_xfer_len: 0x%x ", Get_QTD(qtd->qtd_xfer_len)); 4071 } 4072 4073 /* 4074 * ehci kstat functions 4075 */ 4076 4077 /* 4078 * ehci_create_stats: 4079 * 4080 * Allocate and initialize the ehci kstat structures 4081 */ 4082 void 4083 ehci_create_stats(ehci_state_t *ehcip) 4084 { 4085 char kstatname[KSTAT_STRLEN]; 4086 const char *dname = ddi_driver_name(ehcip->ehci_dip); 4087 char *usbtypes[USB_N_COUNT_KSTATS] = 4088 {"ctrl", "isoch", "bulk", "intr"}; 4089 uint_t instance = ehcip->ehci_instance; 4090 ehci_intrs_stats_t *isp; 4091 int i; 4092 4093 if (EHCI_INTRS_STATS(ehcip) == NULL) { 4094 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,intrs", 4095 dname, instance); 4096 EHCI_INTRS_STATS(ehcip) = kstat_create("usba", instance, 4097 kstatname, "usb_interrupts", KSTAT_TYPE_NAMED, 4098 sizeof (ehci_intrs_stats_t) / sizeof (kstat_named_t), 4099 KSTAT_FLAG_PERSISTENT); 4100 4101 if (EHCI_INTRS_STATS(ehcip)) { 4102 isp = EHCI_INTRS_STATS_DATA(ehcip); 4103 kstat_named_init(&isp->ehci_sts_total, 4104 "Interrupts Total", KSTAT_DATA_UINT64); 4105 kstat_named_init(&isp->ehci_sts_not_claimed, 4106 "Not Claimed", KSTAT_DATA_UINT64); 4107 kstat_named_init(&isp->ehci_sts_async_sched_status, 4108 "Async schedule status", KSTAT_DATA_UINT64); 4109 kstat_named_init(&isp->ehci_sts_periodic_sched_status, 4110 "Periodic sched status", KSTAT_DATA_UINT64); 4111 kstat_named_init(&isp->ehci_sts_empty_async_schedule, 4112 "Empty async schedule", KSTAT_DATA_UINT64); 4113 kstat_named_init(&isp->ehci_sts_host_ctrl_halted, 4114 "Host controller Halted", KSTAT_DATA_UINT64); 4115 kstat_named_init(&isp->ehci_sts_async_advance_intr, 4116 "Intr on async advance", KSTAT_DATA_UINT64); 4117 kstat_named_init(&isp->ehci_sts_host_system_error_intr, 4118 "Host system error", KSTAT_DATA_UINT64); 4119 kstat_named_init(&isp->ehci_sts_frm_list_rollover_intr, 4120 "Frame list rollover", KSTAT_DATA_UINT64); 4121 kstat_named_init(&isp->ehci_sts_rh_port_change_intr, 4122 "Port change detect", KSTAT_DATA_UINT64); 4123 kstat_named_init(&isp->ehci_sts_usb_error_intr, 4124 "USB error interrupt", KSTAT_DATA_UINT64); 4125 kstat_named_init(&isp->ehci_sts_usb_intr, 4126 "USB interrupt", KSTAT_DATA_UINT64); 4127 4128 EHCI_INTRS_STATS(ehcip)->ks_private = ehcip; 4129 EHCI_INTRS_STATS(ehcip)->ks_update = nulldev; 4130 kstat_install(EHCI_INTRS_STATS(ehcip)); 4131 } 4132 } 4133 4134 if (EHCI_TOTAL_STATS(ehcip) == NULL) { 4135 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,total", 4136 dname, instance); 4137 EHCI_TOTAL_STATS(ehcip) = kstat_create("usba", instance, 4138 kstatname, "usb_byte_count", KSTAT_TYPE_IO, 1, 4139 KSTAT_FLAG_PERSISTENT); 4140 4141 if (EHCI_TOTAL_STATS(ehcip)) { 4142 kstat_install(EHCI_TOTAL_STATS(ehcip)); 4143 } 4144 } 4145 4146 for (i = 0; i < USB_N_COUNT_KSTATS; i++) { 4147 if (ehcip->ehci_count_stats[i] == NULL) { 4148 (void) snprintf(kstatname, KSTAT_STRLEN, "%s%d,%s", 4149 dname, instance, usbtypes[i]); 4150 ehcip->ehci_count_stats[i] = kstat_create("usba", 4151 instance, kstatname, "usb_byte_count", 4152 KSTAT_TYPE_IO, 1, KSTAT_FLAG_PERSISTENT); 4153 4154 if (ehcip->ehci_count_stats[i]) { 4155 kstat_install(ehcip->ehci_count_stats[i]); 4156 } 4157 } 4158 } 4159 } 4160 4161 4162 /* 4163 * ehci_destroy_stats: 4164 * 4165 * Clean up ehci kstat structures 4166 */ 4167 void 4168 ehci_destroy_stats(ehci_state_t *ehcip) 4169 { 4170 int i; 4171 4172 if (EHCI_INTRS_STATS(ehcip)) { 4173 kstat_delete(EHCI_INTRS_STATS(ehcip)); 4174 EHCI_INTRS_STATS(ehcip) = NULL; 4175 } 4176 4177 if (EHCI_TOTAL_STATS(ehcip)) { 4178 kstat_delete(EHCI_TOTAL_STATS(ehcip)); 4179 EHCI_TOTAL_STATS(ehcip) = NULL; 4180 } 4181 4182 for (i = 0; i < USB_N_COUNT_KSTATS; i++) { 4183 if (ehcip->ehci_count_stats[i]) { 4184 kstat_delete(ehcip->ehci_count_stats[i]); 4185 ehcip->ehci_count_stats[i] = NULL; 4186 } 4187 } 4188 } 4189 4190 4191 /* 4192 * ehci_do_intrs_stats: 4193 * 4194 * ehci status information 4195 */ 4196 void 4197 ehci_do_intrs_stats( 4198 ehci_state_t *ehcip, 4199 int val) 4200 { 4201 if (EHCI_INTRS_STATS(ehcip)) { 4202 EHCI_INTRS_STATS_DATA(ehcip)->ehci_sts_total.value.ui64++; 4203 switch (val) { 4204 case EHCI_STS_ASYNC_SCHED_STATUS: 4205 EHCI_INTRS_STATS_DATA(ehcip)-> 4206 ehci_sts_async_sched_status.value.ui64++; 4207 break; 4208 case EHCI_STS_PERIODIC_SCHED_STATUS: 4209 EHCI_INTRS_STATS_DATA(ehcip)-> 4210 ehci_sts_periodic_sched_status.value.ui64++; 4211 break; 4212 case EHCI_STS_EMPTY_ASYNC_SCHEDULE: 4213 EHCI_INTRS_STATS_DATA(ehcip)-> 4214 ehci_sts_empty_async_schedule.value.ui64++; 4215 break; 4216 case EHCI_STS_HOST_CTRL_HALTED: 4217 EHCI_INTRS_STATS_DATA(ehcip)-> 4218 ehci_sts_host_ctrl_halted.value.ui64++; 4219 break; 4220 case EHCI_STS_ASYNC_ADVANCE_INTR: 4221 EHCI_INTRS_STATS_DATA(ehcip)-> 4222 ehci_sts_async_advance_intr.value.ui64++; 4223 break; 4224 case EHCI_STS_HOST_SYSTEM_ERROR_INTR: 4225 EHCI_INTRS_STATS_DATA(ehcip)-> 4226 ehci_sts_host_system_error_intr.value.ui64++; 4227 break; 4228 case EHCI_STS_FRM_LIST_ROLLOVER_INTR: 4229 EHCI_INTRS_STATS_DATA(ehcip)-> 4230 ehci_sts_frm_list_rollover_intr.value.ui64++; 4231 break; 4232 case EHCI_STS_RH_PORT_CHANGE_INTR: 4233 EHCI_INTRS_STATS_DATA(ehcip)-> 4234 ehci_sts_rh_port_change_intr.value.ui64++; 4235 break; 4236 case EHCI_STS_USB_ERROR_INTR: 4237 EHCI_INTRS_STATS_DATA(ehcip)-> 4238 ehci_sts_usb_error_intr.value.ui64++; 4239 break; 4240 case EHCI_STS_USB_INTR: 4241 EHCI_INTRS_STATS_DATA(ehcip)-> 4242 ehci_sts_usb_intr.value.ui64++; 4243 break; 4244 default: 4245 EHCI_INTRS_STATS_DATA(ehcip)-> 4246 ehci_sts_not_claimed.value.ui64++; 4247 break; 4248 } 4249 } 4250 } 4251 4252 4253 /* 4254 * ehci_do_byte_stats: 4255 * 4256 * ehci data xfer information 4257 */ 4258 void 4259 ehci_do_byte_stats( 4260 ehci_state_t *ehcip, 4261 size_t len, 4262 uint8_t attr, 4263 uint8_t addr) 4264 { 4265 uint8_t type = attr & USB_EP_ATTR_MASK; 4266 uint8_t dir = addr & USB_EP_DIR_MASK; 4267 4268 if (dir == USB_EP_DIR_IN) { 4269 EHCI_TOTAL_STATS_DATA(ehcip)->reads++; 4270 EHCI_TOTAL_STATS_DATA(ehcip)->nread += len; 4271 switch (type) { 4272 case USB_EP_ATTR_CONTROL: 4273 EHCI_CTRL_STATS(ehcip)->reads++; 4274 EHCI_CTRL_STATS(ehcip)->nread += len; 4275 break; 4276 case USB_EP_ATTR_BULK: 4277 EHCI_BULK_STATS(ehcip)->reads++; 4278 EHCI_BULK_STATS(ehcip)->nread += len; 4279 break; 4280 case USB_EP_ATTR_INTR: 4281 EHCI_INTR_STATS(ehcip)->reads++; 4282 EHCI_INTR_STATS(ehcip)->nread += len; 4283 break; 4284 case USB_EP_ATTR_ISOCH: 4285 EHCI_ISOC_STATS(ehcip)->reads++; 4286 EHCI_ISOC_STATS(ehcip)->nread += len; 4287 break; 4288 } 4289 } else if (dir == USB_EP_DIR_OUT) { 4290 EHCI_TOTAL_STATS_DATA(ehcip)->writes++; 4291 EHCI_TOTAL_STATS_DATA(ehcip)->nwritten += len; 4292 switch (type) { 4293 case USB_EP_ATTR_CONTROL: 4294 EHCI_CTRL_STATS(ehcip)->writes++; 4295 EHCI_CTRL_STATS(ehcip)->nwritten += len; 4296 break; 4297 case USB_EP_ATTR_BULK: 4298 EHCI_BULK_STATS(ehcip)->writes++; 4299 EHCI_BULK_STATS(ehcip)->nwritten += len; 4300 break; 4301 case USB_EP_ATTR_INTR: 4302 EHCI_INTR_STATS(ehcip)->writes++; 4303 EHCI_INTR_STATS(ehcip)->nwritten += len; 4304 break; 4305 case USB_EP_ATTR_ISOCH: 4306 EHCI_ISOC_STATS(ehcip)->writes++; 4307 EHCI_ISOC_STATS(ehcip)->nwritten += len; 4308 break; 4309 } 4310 } 4311 } 4312