1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Emulex. All rights reserved. 24 * Use is subject to License terms. 25 */ 26 27 28 #ifndef _EMLXS_DFCLIB_H 29 #define _EMLXS_DFCLIB_H 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #define MAX_DFC_EVENTS 16 36 #define MAX_EMLXS_BRDS 128 37 #define MAX_CFG_PARAM 64 38 #define MAX_NODES 4096 39 40 41 #ifndef MAX_VPORTS 42 #ifdef NPIV_SUPPORT 43 #define MAX_VPORTS 256 44 #else 45 #define MAX_VPORTS 1 46 #endif /* NPIV_SUPPORT */ 47 #endif /* MAX_VPORTS */ 48 49 #ifdef EMLXS_SPARC 50 #define EMLXS_BIG_ENDIAN 51 #endif /* EMLXS_SPARC */ 52 53 #ifdef EMLXS_I386 54 #define EMLXS_LITTLE_ENDIAN 55 #endif /* EMLXS_I386 */ 56 57 58 typedef struct brdinfo 59 { 60 uint32_t a_mem_hi; /* memory identifier for adapter access */ 61 uint32_t a_mem_low; /* memory identifier for adapter access */ 62 uint32_t a_flash_hi; /* memory identifier for adapter access */ 63 uint32_t a_flash_low; /* memory identifier for adapter access */ 64 uint32_t a_ctlreg_hi; /* memory identifier for adapter access */ 65 uint32_t a_ctlreg_low; /* memory identifier for adapter access */ 66 uint32_t a_intrlvl; /* interrupt level for adapter */ 67 uint32_t a_pci; /* PCI identifier (device / vendor id) */ 68 uint32_t a_busid; /* identifier of PCI bus adapter is on */ 69 uint32_t a_devid; /* identifier of PCI device number */ 70 uint8_t a_rsvd1; /* reserved for future use */ 71 uint8_t a_rsvd2; /* reserved for future use */ 72 uint8_t a_siglvl; /* signal handler used by library */ 73 uint8_t a_ddi; /* identifier device driver instance number */ 74 uint32_t a_onmask; /* mask of ONDI primatives supported */ 75 uint32_t a_offmask; /* mask of OFFDI primatives supported */ 76 uint8_t a_drvrid[16]; /* driver version */ 77 uint8_t a_fwname[32]; /* firmware version */ 78 } brdinfo_t; 79 80 81 typedef struct dfc_brdinfo 82 { 83 uint32_t a_mem_hi; /* memory identifier for adapter access */ 84 uint32_t a_mem_low; /* memory identifier for adapter access */ 85 uint32_t a_flash_hi; /* memory identifier for adapter access */ 86 uint32_t a_flash_low; /* memory identifier for adapter access */ 87 uint32_t a_ctlreg_hi; /* memory identifier for adapter access */ 88 uint32_t a_ctlreg_low; /* memory identifier for adapter access */ 89 uint32_t a_intrlvl; /* interrupt level for adapter */ 90 uint32_t a_pci; /* PCI identifier (device / vendor id) */ 91 uint32_t a_busid; /* identifier of PCI bus adapter is on */ 92 uint32_t a_devid; /* identifier of PCI device number */ 93 uint8_t a_rsvd; /* reserved for word alignment */ 94 uint8_t a_siglvl; /* signal handler used by library */ 95 uint16_t a_ddi; /* identifier device driver instance number */ 96 uint32_t a_onmask; /* mask of ONDI primatives supported */ 97 uint32_t a_offmask; /* mask of OFFDI primatives supported */ 98 uint8_t a_drvrid[16]; /* driver version */ 99 uint8_t a_fwname[32]; /* firmware version */ 100 uint8_t a_wwpn[8]; /* worldwide portname */ 101 } dfc_brdinfo_t; 102 103 104 #define putPaddrLow(addr) ((uint32_t)(((unsigned long)(addr)) \ 105 & 0xffffffff)) 106 #define putPaddrHigh(addr) ((uint32_t)(((uint64_t)(unsigned long)(addr)) \ 107 >> 32)) 108 #define getPaddr(high, low) ((uint64_t)((((uint64_t)(high)) << 32) \ 109 | (((uint64_t)(low)) & 0xffffffff))) 110 111 typedef struct ulp_bde 112 { 113 uint32_t bdeAddress; 114 115 #ifdef EMLXS_BIG_ENDIAN 116 uint32_t bdeReserved:4; 117 uint32_t bdeAddrHigh:4; 118 uint32_t bdeSize:24; 119 #endif 120 #ifdef EMLXS_LITTLE_ENDIAN 121 uint32_t bdeSize:24; 122 uint32_t bdeAddrHigh:4; 123 uint32_t bdeReserved:4; 124 #endif 125 } ulp_bde_t; 126 127 typedef struct ulp_bde64 128 { 129 union 130 { 131 uint32_t w; 132 struct 133 { 134 #ifdef EMLXS_BIG_ENDIAN 135 uint32_t bdeFlags:8; 136 uint32_t bdeSize:24; 137 #endif 138 #ifdef EMLXS_LITTLE_ENDIAN 139 uint32_t bdeSize:24; 140 uint32_t bdeFlags:8; 141 #endif 142 143 #define BUFF_USE_RSVD 0x01 /* bdeFlags */ 144 #define BUFF_USE_INTRPT 0x02 /* Not Implemented with LP6000 */ 145 #define BUFF_USE_CMND 0x04 /* Optional, 1=cmd/rsp 0=data buffer */ 146 #define BUFF_USE_RCV 0x08 /* "" "", 1=rcv buffer, 0=xmit buffer */ 147 #define BUFF_TYPE_32BIT 0x10 /* "" "", 1=32 bit addr 0=64 bit addr */ 148 #define BUFF_TYPE_SPECIAL 0x20 /* Not Implemented with LP6000 */ 149 #define BUFF_TYPE_BDL 0x40 /* Optional, may be set in BDL */ 150 #define BUFF_TYPE_INVALID 0x80 /* "" "" */ 151 } f; 152 } tus; 153 154 uint32_t addrLow; 155 uint32_t addrHigh; 156 } ulp_bde64_t; 157 158 typedef struct read_sparm_var 159 { 160 uint32_t rsvd1; 161 uint32_t rsvd2; 162 union 163 { 164 ulp_bde_t sp; 165 ulp_bde64_t sp64; 166 } un; 167 } read_sparm_var_t; 168 169 typedef struct read_rev_var 170 { 171 #ifdef EMLXS_BIG_ENDIAN 172 uint32_t cv:1; 173 uint32_t rr:1; 174 uint32_t rsvd1:29; 175 uint32_t rv:1; 176 #endif 177 #ifdef EMLXS_LITTLE_ENDIAN 178 uint32_t rv:1; 179 uint32_t rsvd1:29; 180 uint32_t rr:1; 181 uint32_t cv:1; 182 #endif 183 uint32_t biuRev; 184 uint32_t smRev; 185 union 186 { 187 uint32_t smFwRev; 188 struct 189 { 190 #ifdef EMLXS_BIG_ENDIAN 191 uint8_t ProgType; 192 uint8_t ProgId; 193 uint16_t ProgVer:4; 194 uint16_t ProgRev:4; 195 uint16_t ProgFixLvl:2; 196 uint16_t ProgDistType:2; 197 uint16_t DistCnt:4; 198 #endif 199 #ifdef EMLXS_LITTLE_ENDIAN 200 uint16_t DistCnt:4; 201 uint16_t ProgDistType:2; 202 uint16_t ProgFixLvl:2; 203 uint16_t ProgRev:4; 204 uint16_t ProgVer:4; 205 uint8_t ProgId; 206 uint8_t ProgType; 207 #endif 208 } b; 209 } un; 210 uint32_t endecRev; 211 212 #ifdef EMLXS_BIG_ENDIAN 213 uint8_t feaLevelHigh; 214 uint8_t feaLevelLow; 215 uint8_t fcphHigh; 216 uint8_t fcphLow; 217 #endif 218 #ifdef EMLXS_LITTLE_ENDIAN 219 uint8_t fcphLow; 220 uint8_t fcphHigh; 221 uint8_t feaLevelLow; 222 uint8_t feaLevelHigh; 223 #endif 224 uint32_t postKernRev; 225 uint32_t opFwRev; 226 uint8_t opFwName[16]; 227 uint32_t sli1FwRev; 228 uint8_t sli1FwName[16]; 229 uint32_t sli2FwRev; 230 uint8_t sli2FwName[16]; 231 } read_rev_var_t; 232 233 234 typedef struct dump_var 235 { 236 #ifdef EMLXS_BIG_ENDIAN 237 uint32_t rsvd:25; 238 uint32_t ra:1; 239 uint32_t co:1; 240 uint32_t cv:1; 241 uint32_t type:4; 242 243 uint32_t entry_index:16; 244 uint32_t region_id:16; 245 #endif 246 #ifdef EMLXS_LITTLE_ENDIAN 247 uint32_t type:4; 248 uint32_t cv:1; 249 uint32_t co:1; 250 uint32_t ra:1; 251 uint32_t rsvd:25; 252 253 uint32_t region_id:16; 254 uint32_t entry_index:16; 255 #endif 256 uint32_t base_adr; 257 uint32_t word_cnt; 258 uint32_t resp_offset; 259 } dump_var_t; 260 261 262 typedef struct read_cfg_var 263 { 264 #ifdef EMLXS_BIG_ENDIAN 265 uint32_t cr:1; 266 uint32_t ci:1; 267 uint32_t cr_delay:6; 268 uint32_t cr_count:8; 269 uint32_t InitBBC:8; 270 uint32_t MaxBBC:8; 271 #endif 272 #ifdef EMLXS_LITTLE_ENDIAN 273 uint32_t MaxBBC:8; 274 uint32_t InitBBC:8; 275 uint32_t cr_count:8; 276 uint32_t cr_delay:6; 277 uint32_t ci:1; 278 uint32_t cr:1; 279 #endif 280 #ifdef EMLXS_BIG_ENDIAN 281 uint32_t topology:8; 282 uint32_t myDid:24; 283 #endif 284 #ifdef EMLXS_LITTLE_ENDIAN 285 uint32_t myDid:24; 286 uint32_t topology:8; 287 #endif 288 /* Defines for topology (defined previously) */ 289 #ifdef EMLXS_BIG_ENDIAN 290 uint32_t AR:1; 291 uint32_t IR:1; 292 uint32_t rsvd1:29; 293 uint32_t ack0:1; 294 #endif 295 #ifdef EMLXS_LITTLE_ENDIAN 296 uint32_t ack0:1; 297 uint32_t rsvd1:29; 298 uint32_t IR:1; 299 uint32_t AR:1; 300 #endif 301 uint32_t edtov; 302 uint32_t arbtov; 303 uint32_t ratov; 304 uint32_t rttov; 305 uint32_t altov; 306 uint32_t lmt; 307 308 #define LMT_1GB_CAPABLE 0x0004 309 #define LMT_2GB_CAPABLE 0x0008 310 #define LMT_4GB_CAPABLE 0x0040 311 #define LMT_8GB_CAPABLE 0x0080 312 #define LMT_10GB_CAPABLE 0x0100 313 314 uint32_t rsvd2; 315 uint32_t rsvd3; 316 uint32_t max_xri; 317 uint32_t max_iocb; 318 uint32_t max_rpi; 319 uint32_t avail_xri; 320 uint32_t avail_iocb; 321 uint32_t avail_rpi; 322 uint32_t default_rpi; 323 } read_cfg_var_t; 324 325 326 typedef struct read_log_var 327 { 328 #ifdef EMLXS_BIG_ENDIAN 329 uint32_t type:8; 330 uint32_t byte_count:8; 331 uint32_t write:1; 332 uint32_t resv:3; 333 uint32_t offset:12; 334 #endif 335 #ifdef EMLXS_LITTLE_ENDIAN 336 uint32_t offset:12; 337 uint32_t resv:3; 338 uint32_t write:1; 339 uint32_t byte_count:8; 340 uint32_t type:8; 341 #endif 342 343 uint32_t data; 344 } read_log_var_t; 345 346 347 typedef struct log_status_var 348 { 349 350 #ifdef EMLXS_BIG_ENDIAN 351 uint16_t split_log_next; 352 uint16_t log_next; 353 354 uint32_t size; 355 356 uint32_t format:8; 357 uint32_t resv2:22; 358 uint32_t log_level:1; 359 uint32_t split_log:1; 360 #endif 361 #ifdef EMLXS_LITTLE_ENDIAN 362 uint16_t log_next; 363 uint16_t split_log_next; 364 365 uint32_t size; 366 367 uint32_t split_log:1; 368 uint32_t log_level:1; 369 uint32_t resv2:22; 370 uint32_t format:8; 371 #endif 372 373 uint32_t offset; 374 } log_status_var_t; 375 376 377 typedef struct read_evt_log_var 378 { 379 #ifdef EMLXS_BIG_ENDIAN 380 uint32_t read_log:1; 381 uint32_t clear_log:1; 382 uint32_t mbox_rsp:1; 383 uint32_t resv:28; 384 #endif 385 #ifdef EMLXS_LITTLE_ENDIAN 386 uint32_t resv:28; 387 uint32_t mbox_rsp:1; 388 uint32_t clear_log:1; 389 uint32_t read_log:1; 390 #endif 391 392 uint32_t offset; 393 394 union 395 { 396 ulp_bde_t sp; 397 ulp_bde64_t sp64; 398 } un; 399 } read_evt_log_var_t; 400 401 402 typedef struct dfc_mailbox 403 { 404 #ifdef EMLXS_BIG_ENDIAN 405 uint16_t mbxStatus; 406 uint8_t mbxCommand; 407 uint8_t mbxReserved:6; 408 uint8_t mbxHc:1; 409 uint8_t mbxOwner:1; /* Low order bit first word */ 410 #endif 411 #ifdef EMLXS_LITTLE_ENDIAN 412 uint8_t mbxOwner:1; /* Low order bit first word */ 413 uint8_t mbxHc:1; 414 uint8_t mbxReserved:6; 415 uint8_t mbxCommand; 416 uint16_t mbxStatus; 417 #endif 418 419 union 420 { 421 uint32_t varWords[31]; 422 read_sparm_var_t varRdSparm; 423 read_rev_var_t varRdRev; 424 read_cfg_var_t varRdCfg; 425 dump_var_t varDmp; 426 read_log_var_t varRdLog; 427 log_status_var_t varLogStat; 428 read_evt_log_var_t varRdEvtLog; 429 430 } un; 431 } dfc_mailbox_t; 432 433 434 typedef struct dfc_ioinfo 435 { 436 uint32_t a_mboxCmd; /* mailbox commands issued */ 437 uint32_t a_mboxCmpl; /* mailbox commands completed */ 438 uint32_t a_mboxErr; /* mailbox commands completed, error status */ 439 uint32_t a_iocbCmd; /* iocb command ring issued */ 440 uint32_t a_iocbRsp; /* iocb rsp ring received */ 441 uint32_t a_adapterIntr; /* adapter interrupt events */ 442 uint32_t a_fcpCmd; /* FCP commands issued */ 443 uint32_t a_fcpCmpl; /* FCP command completions received */ 444 uint32_t a_fcpErr; /* FCP command completions errors */ 445 uint32_t a_seqXmit; /* IP xmit sequences sent */ 446 uint32_t a_seqRcv; /* IP sequences received */ 447 uint32_t a_bcastXmit; /* cnt of successful xmit bcast cmds issued */ 448 uint32_t a_bcastRcv; /* cnt of receive bcast cmds received */ 449 uint32_t a_elsXmit; /* cnt of successful ELS req cmds issued */ 450 uint32_t a_elsRcv; /* cnt of ELS request commands received */ 451 uint32_t a_RSCNRcv; /* cnt of RSCN commands received */ 452 uint32_t a_seqXmitErr; /* cnt of unsuccessful xmit bcast cmds issued */ 453 uint32_t a_elsXmitErr; /* cnt of unsuccessful ELS req cmds issued */ 454 uint32_t a_elsBufPost; /* cnt of ELS buffers posted to adapter */ 455 uint32_t a_ipBufPost; /* cnt of IP buffers posted to adapter */ 456 uint32_t a_cnt1; /* generic counter */ 457 uint32_t a_cnt2; /* generic counter */ 458 uint32_t a_cnt3; /* generic counter */ 459 uint32_t a_cnt4; /* generic counter */ 460 461 } dfc_ioinfo_t; 462 463 464 typedef struct dfc_linkinfo 465 { 466 uint32_t a_linkEventTag; 467 uint32_t a_linkUp; 468 uint32_t a_linkDown; 469 uint32_t a_linkMulti; 470 uint32_t a_DID; 471 uint8_t a_topology; 472 uint8_t a_linkState; 473 uint8_t a_alpa; 474 uint8_t a_alpaCnt; 475 uint8_t a_alpaMap[128]; 476 uint8_t a_wwpName[8]; 477 uint8_t a_wwnName[8]; 478 } dfc_linkinfo_t; 479 480 /* values for a_topology */ 481 #define LNK_LOOP 0x1 482 #define LNK_PUBLIC_LOOP 0x2 483 #define LNK_FABRIC 0x3 484 #define LNK_PT2PT 0x4 485 #define LNK_MENLO_MAINTENANCE 0x5 486 487 /* values for a_linkState */ 488 #define LNK_DOWN 0x1 489 #define LNK_UP 0x2 490 #define LNK_FLOGI 0x3 491 #define LNK_DISCOVERY 0x4 492 #define LNK_REDISCOVERY 0x5 493 #define LNK_READY 0x6 494 495 496 typedef struct dfc_traceinfo 497 { 498 uint8_t a_event; 499 uint8_t a_cmd; 500 uint16_t a_status; 501 uint32_t a_information; 502 } dfc_traceinfo_t; 503 504 505 typedef struct dfc_cfgparam 506 { 507 char a_string[32]; 508 uint32_t a_low; 509 uint32_t a_hi; 510 uint32_t a_default; 511 uint32_t a_current; 512 uint16_t a_flag; 513 #define CFG_EXPORT 0x1 /* Export this parameter to end user */ 514 #define CFG_IGNORE 0x2 /* Ignore this parameter */ 515 516 uint16_t a_changestate; 517 #define CFG_REBOOT 0x0 /* Changes effective after system */ 518 /* reboot */ 519 #define CFG_DYMANIC 0x1 /* Changes effective immediately */ 520 #define CFG_RESTART 0x2 /* Changes effective after adapter */ 521 /* restart */ 522 #define CFG_LINKRESET 0x3 /* Changes effective after link reset */ 523 524 char a_help[80]; 525 } dfc_cfgparam_t; 526 527 528 529 typedef struct dfc_nodeinfo 530 { 531 uint16_t a_flag; 532 uint16_t a_state; 533 uint32_t a_did; 534 uint8_t a_wwpn[8]; 535 uint8_t a_wwnn[8]; 536 uint32_t a_targetid; 537 } dfc_nodeinfo_t; 538 539 /* Defines for a_state */ 540 #define NODE_UNUSED 0 /* unused NL_PORT entry */ 541 #define NODE_LIMBO 0x1 /* entry needs to hang around for wwpn / sid */ 542 #define NODE_LOGOUT 0x2 /* NL_PORT is not logged in - entry is cached */ 543 #define NODE_PLOGI 0x3 /* PLOGI was sent to NL_PORT */ 544 #define NODE_LOGIN 0x4 /* NL_PORT is logged in / login REG_LOGINed */ 545 #define NODE_PRLI 0x5 /* PRLI was sent to NL_PORT */ 546 #define NODE_ALLOC 0x6 /* NL_PORT is ready to initiate adapter I/O */ 547 #define NODE_SEED 0x7 /* seed scsi id bind in table */ 548 549 /* Defines for a_flag */ 550 #define NODE_RPI_XRI 0x1 /* creating xri for entry */ 551 #define NODE_REQ_SND 0x2 /* sent ELS request for this entry */ 552 #define NODE_ADDR_AUTH 0x4 /* Authenticating addr for this entry */ 553 #define NODE_RM_ENTRY 0x8 /* Remove this entry */ 554 #define NODE_FARP_SND 0x10 /* sent FARP request for this entry */ 555 #define NODE_FABRIC 0x20 /* this entry represents the Fabric */ 556 #define NODE_FCP_TARGET 0x40 /* this entry is an FCP target */ 557 #define NODE_IP_NODE 0x80 /* this entry is an IP node */ 558 #define NODE_DISC_START 0x100 /* start discovery on this entry */ 559 #define NODE_SEED_WWPN 0x200 /* Entry scsi id is seeded for WWPN */ 560 #define NODE_SEED_WWNN 0x400 /* Entry scsi id is seeded for WWNN */ 561 #define NODE_SEED_DID 0x800 /* Entry scsi id is seeded for DID */ 562 #define NODE_SEED_MASK 0xe00 /* mask for seeded flags */ 563 #define NODE_AUTOMAP 0x1000 /* This entry was automap'ed */ 564 #define NODE_NS_REMOVED 0x2000 /* This entry removed from NameServer */ 565 566 567 typedef struct dfc_vpd 568 { 569 uint32_t version; 570 #define DFC_VPD_VERSION 1 571 572 char ModelDescription[256]; /* VPD field V1 */ 573 char Model[80]; /* VPD field V2 */ 574 char ProgramType[256]; /* VPD field V3 */ 575 char PortNum[20]; /* VPD field V4 */ 576 } dfc_vpd_t; 577 578 typedef struct dfc_destid 579 { 580 uint32_t idType; /* 0 - wwpn, 1 - d_id */ 581 uint32_t d_id; 582 uint8_t wwpn[8]; 583 } dfc_destid_t; 584 585 586 typedef struct dfc_loopback 587 { 588 uint32_t bufSize; 589 uint8_t *XmitBuffer; 590 uint8_t *RcvBuffer; 591 } dfc_loopback_t; 592 593 594 typedef struct dfc_drvinfo 595 { 596 uint8_t drvInfoVer; /* Version of this structure */ 597 #define DFC_DRVINFO_VERSION2 0x02 598 #define DFC_DRVINFO_VERSION3 0x03 /* NPIV */ 599 #define DFC_DRVINFO_VERSION4 0x04 /* DHCHAP */ 600 #define DFC_DRVINFO_VERSION DFC_DRVINFO_VERSION2 601 602 #ifdef NPIV_SUPPORT 603 #undef DFC_DRVINFO_VERSION 604 #define DFC_DRVINFO_VERSION DFC_DRVINFO_VERSION3 605 #endif /* NPIV_SUPPORT */ 606 607 #ifdef DHCHAP_SUPPORT 608 #undef DFC_DRVINFO_VERSION 609 #define DFC_DRVINFO_VERSION DFC_DRVINFO_VERSION4 610 #endif /* DHCHAP_SUPPORT */ 611 612 uint8_t drvType; 613 #define DFC_DRVINFO_SOLARIS 0x11 /* Solaris */ 614 #define DFC_DRVINFO_LEADVILLE 0x14 /* Solaris Leadville ULP */ 615 #define DFC_DRVINFO_COMSTAR 0x16 /* Solaris Comstar ULP */ 616 617 uint16_t reserved; 618 uint8_t rmLevel; /* Remote Management (HBAnyware) */ 619 /* Support Level */ 620 #define DFC_DRVINFO_RMLEVEL 0x02 /* HBAnyware v2.3 */ 621 622 uint8_t mpLevel; /* MultiPulse support Level */ 623 uint8_t hbaapiLevel; /* HBAAPI support level */ 624 #define DFC_DRVINFO_HBAAPI 0x01 /* HBAAPI v1.0 */ 625 626 uint8_t reserved1; 627 char drvVer[16]; /* Driver Version string */ 628 char drvName[8]; /* Driver Name */ 629 char ftrDrvVer[16]; /* Filter/IOCtl Driver Version string */ 630 char ftrDrvName[8]; /* Filter/IOCtl Driver Name */ 631 char ipDrvVer[16]; /* IP Driver/component Version string */ 632 char ipDrvName[8]; /* IP Driver/component Name */ 633 uint32_t d_id; 634 uint8_t wwpn[8]; 635 uint8_t wwnn[8]; 636 uint8_t hostname[32]; /* IP node hostname from uname -n */ 637 638 #if (DFC_DRVINFO_VERSION >= DFC_DRVINFO_VERSION3) 639 uint32_t NPIVsupport; 640 #define DFC_DRVINFO_NPIV_DRV 0x00000001 641 #define DFC_DRVINFO_NPIV_MODS 0x00000002 642 #define DFC_DRVINFO_NPIV_PARMS 0x00000004 643 #define DFC_DRVINFO_NPIV_FW 0x00000008 644 645 #endif /* >= DFC_DRVINFO_VERSION3 */ 646 647 #if (DFC_DRVINFO_VERSION >= DFC_DRVINFO_VERSION4) 648 uint32_t sliMode; 649 uint64_t featureList; 650 #define DFC_DRVINFO_FEATURE_DIAG 0x00000001 651 #define DFC_DRVINFO_FEATURE_MAPPING 0x00000002 652 #define DFC_DRVINFO_FEATURE_DHCHAP 0x00000004 653 #define DFC_DRVINFO_FEATURE_IKE 0x00000008 654 #define DFC_DRVINFO_FEATURE_NPIV 0x00000010 655 #define DFC_DRVINFO_FEATURE_RESET_WWN 0x00000020 656 #define DFC_DRVINFO_FEATURE_VOLATILE_WWN 0x00000040 657 #define DFC_DRVINFO_FEATURE_E2E_AUTH 0x00000080 658 #define DFC_DRVINFO_FEATURE_TARGET_MODE 0x00000100 659 660 #endif /* >= DFC_DRVINFO_VERSION4 */ 661 } dfc_drvinfo_t; 662 663 664 665 typedef struct dfc_regevent 666 { 667 uint32_t ppid; 668 uint32_t cpid; 669 670 uint32_t event; 671 uint32_t type; 672 uint32_t outsz; 673 void *ctx; 674 void (*func) (); 675 676 uint32_t cindex; /* Set only by child */ 677 uint32_t state; /* Set only by child */ 678 679 /* state */ 680 #define CHILD_UNKNOWN 0 681 #define CHILD_UNBORN 1 682 #define CHILD_ALIVE 2 683 #define CHILD_REGISTERED 3 684 #define CHILD_ASLEEP 4 685 #define CHILD_AWAKE 5 686 #define CHILD_DIED 6 687 688 uint32_t pindex; /* Set only by parent */ 689 uint32_t flags; /* Set only by parent */ 690 691 /* flags */ 692 #define EVENT_REGISTERED 0x01 693 #define EVENT_SERVICE_ACTIVE 0x02 694 695 #ifdef SAN_DIAG_SUPPORT 696 HBA_WWN portname; 697 #endif /* SAN_DIAG_SUPPORT */ 698 } dfc_regevent_t; 699 700 701 /* Defines for RegisterForEvent mask */ 702 #define FC_REG_LINK_EVENT 0x01 /* Register for link up/down */ 703 /* events */ 704 #define FC_REG_RSCN_EVENT 0x02 /* Register for RSCN events */ 705 #define FC_REG_CT_EVENT 0x04 /* Register for CT request */ 706 /* events */ 707 #define FC_REG_MULTIPULSE_EVENT 0x08 /* Register for MultiPulse */ 708 /* events */ 709 #define FC_REG_DUMP_EVENT 0x10 /* Register for Diagnostic */ 710 /* Dump events */ 711 #define FC_REG_TEMP_EVENT 0x20 /* Register for Temperature */ 712 /* events */ 713 #define FC_REG_VPORTRSCN_EVENT 0x40 /* Register for VPort RSCN */ 714 /* events */ 715 #ifdef SAN_DIAG_SUPPORT 716 #define FC_REG_SD_ELS_EVENT 0x1000 /* Register for SANDiag ELS */ 717 /* events */ 718 #define FC_REG_SD_FABRIC_EVENT 0x2000 /* Register for SANDiag */ 719 /* Fabric events */ 720 #define FC_REG_SD_SCSI_EVENT 0x4000 /* Register for SANDiag SCSI */ 721 /* events */ 722 #define FC_REG_SD_BOARD_EVENT 0x8000 /* Register for SANDiag Board */ 723 /* events */ 724 #endif /* SAN_DIAG_SUPPORT */ 725 #define FC_REG_FCOE_EVENT 0x80000000 /* (Unofficial) Register for */ 726 /* FCOE events */ 727 728 #define MAX_RSCN_PAYLOAD 1024 729 #define MAX_CT_PAYLOAD (1024*320) 730 731 /* Temperature event types */ 732 #define DFC_TEMP_CRITICAL 1 733 #define DFC_TEMP_WARNING 2 734 #define DFC_TEMP_SAFE 3 735 736 /* bits in a_onmask */ 737 #define ONDI_MBOX 0x1 /* allows non-destructive mailbox */ 738 /* commands */ 739 #define ONDI_IOINFO 0x2 /* supports retrieval of I/O info */ 740 #define ONDI_LNKINFO 0x4 /* supports retrieval of link info */ 741 #define ONDI_NODEINFO 0x8 /* supports retrieval of node info */ 742 #define ONDI_TRACEINFO 0x10 /* supports retrieval of trace info */ 743 #define ONDI_SETTRACE 0x20 /* supports configuration of trace */ 744 /* info */ 745 #define ONDI_SLI1 0x40 /* hardware supports SLI-1 interface */ 746 #define ONDI_SLI2 0x80 /* hardware supports SLI-2 interface */ 747 #define ONDI_BIG_ENDIAN 0x100 /* DDI interface is BIG Endian */ 748 #define ONDI_LTL_ENDIAN 0x200 /* DDI interface is LITTLE Endian */ 749 #define ONDI_RMEM 0x400 /* allows reading of adapter shared */ 750 /* memory */ 751 #define ONDI_RFLASH 0x800 /* allows reading of adapter flash */ 752 #define ONDI_RPCI 0x1000 /* allows reading of adapter pci */ 753 /* registers */ 754 #define ONDI_RCTLREG 0x2000 /* allows reading of adapter cntrol */ 755 /* registers */ 756 #define ONDI_CFGPARAM 0x4000 /* supports get/set configuration */ 757 /* parameters */ 758 #define ONDI_CT 0x8000 /* supports passthru CT interface */ 759 #define ONDI_HBAAPI 0x10000 /* supports HBA API interface */ 760 #define ONDI_SBUS 0x20000 /* supports SBUS adapter interface */ 761 762 /* bits in a_offmask */ 763 #define OFFDI_MBOX 0x1 /* allows all mailbox commands */ 764 #define OFFDI_RMEM 0x2 /* allows reading of adapter shared */ 765 /* memory */ 766 #define OFFDI_WMEM 0x4 /* allows writing of adapter shared */ 767 /* memory */ 768 #define OFFDI_RFLASH 0x8 /* allows reading of adapter flash */ 769 #define OFFDI_WFLASH 0x10 /* allows writing of adapter flash */ 770 #define OFFDI_RPCI 0x20 /* allows reading of adapter pci */ 771 /* registers */ 772 #define OFFDI_WPCI 0x40 /* allows writing of adapter pci */ 773 /* registers */ 774 #define OFFDI_RCTLREG 0x80 /* allows reading of adapter cntrol */ 775 /* registers */ 776 #define OFFDI_WCTLREG 0x100 /* allows writing of adapter cntrol */ 777 /* registers */ 778 #define OFFDI_OFFLINE 0x80000000 /* if set, adapter is in offline */ 779 /* state */ 780 781 782 #define DDI_SHOW 0x0 783 #define DDI_ONDI 0x1 784 #define DDI_OFFDI 0x2 785 #define DDI_WARMDI 0x3 786 #define DDI_DIAGDI 0x4 787 788 /* mbxStatus */ 789 #define DFC_MBX_SUCCESS 0x00 790 #define DFC_MBXERR_NUM_RINGS 0x01 791 #define DFC_MBXERR_NUM_IOCBS 0x02 792 #define DFC_MBXERR_IOCBS_EXCEEDED 0x03 793 #define DFC_MBXERR_BAD_RING_NUMBER 0x04 794 #define DFC_MBXERR_MASK_ENTRIES_RANGE 0x05 795 #define DFC_MBXERR_MASKS_EXCEEDED 0x06 796 #define DFC_MBXERR_BAD_PROFILE 0x07 797 #define DFC_MBXERR_BAD_DEF_CLASS 0x08 798 #define DFC_MBXERR_BAD_MAX_RESPONDER 0x09 799 #define DFC_MBXERR_BAD_MAX_ORIGINATOR 0x0A 800 #define DFC_MBXERR_RPI_REGISTERED 0x0B 801 #define DFC_MBXERR_RPI_FULL 0x0C 802 #define DFC_MBXERR_NO_RESOURCES 0x0D 803 #define DFC_MBXERR_BAD_RCV_LENGTH 0x0E 804 #define DFC_MBXERR_DMA_ERROR 0x0F 805 #define DFC_MBXERR_ERROR 0x10 806 807 #define DFC_MBXERR_OVERTEMP_ERROR 0xFA 808 #define DFC_MBXERR_HARDWARE_ERROR 0xFB 809 #define DFC_MBXERR_DRVR_ERROR 0xFC 810 #define DFC_MBXERR_BUSY 0xFD 811 #define DFC_MBXERR_TIMEOUT 0xFE 812 #define DFC_MBX_NOT_FINISHED 0xFF 813 814 815 816 /* Error codes for library calls */ 817 #define DFC_ERR_GENERAL_ERROR 0x1 818 819 #define DFC_ERR_MBOX_ERROR 0x2 820 #define DFC_ERR_LINK_DOWN 0x2 821 #define DFC_ERR_INCORRECT_VER 0x2 822 #define DFC_ERR_INVALID_ID 0x2 823 #define DFC_ERR_TIMEOUT 0x2 824 #define DFC_ERR_NOT_SUPPORTED 0x2 825 #define DFC_ERR_NPIV_ACTIVE 0x2 826 827 #define DFC_ERR_NO_RPI 0x3 828 #define DFC_ERR_BUFFER_OVERFLOW 0x3 829 #define DFC_ERR_INVALID_LOOPBACK_TYPE 0x3 830 #define DFC_ERR_OVERTEMP 0x3 831 832 #define DFC_ERR_LOOPBACK_BUSY 0x4 833 #define DFC_ERR_INVALID_RESET_TYPE 0x4 834 #define DFC_ERR_MENLO_LINKDOWN 0x4 835 836 #define DFC_ERR_SEQ_TIMEOUT 0x5 837 838 #define DFC_ERR_NO_XMIT 0x6 839 #define DFC_ERR_INVALID_NUMBER 0x6 840 841 #define DFC_ERR_RESET_RECV 0x7 842 843 844 845 846 /* type definitions for GetBindList function */ 847 typedef enum dfc_bindtype 848 { 849 BIND_NONE, 850 BIND_WWNN, 851 BIND_WWPN, 852 BIND_DID, 853 BIND_ALPA 854 } dfc_bindtype_t; 855 856 857 typedef struct dfc_bind_entry 858 { 859 dfc_bindtype_t bind_type; 860 uint32_t scsi_id; 861 uint32_t did; 862 uint8_t wwnn[8]; 863 uint8_t wwpn[8]; 864 uint32_t flags; 865 866 /* Bind Entry flags */ 867 #define DFC_BIND_AUTOMAP 0x1 /* Node is automapped */ 868 #define DFC_BIND_BINDLIST 0x2 /* entry in bind list not mapped */ 869 #define DFC_BIND_MAPPED 0x4 /* Node is mapped to a scsiid */ 870 #define DFC_BIND_UNMAPPED 0x8 /* Node is unmapped */ 871 #define DFC_BIND_NODEVTMO 0x10 /* NODEVTMO flag of the node */ 872 #define DFC_BIND_NOSCSIID 0x20 /* No scsi id is assigned yet */ 873 #define DFC_BIND_RPTLUNST 0x40 /* Node is in report lun cmpl st */ 874 } dfc_bind_entry_t; 875 876 typedef struct dfc_bind_list 877 { 878 uint32_t NumberOfEntries; 879 dfc_bind_entry_t entry[1]; /* Variable length array */ 880 } dfc_bind_list_t; 881 882 883 884 /* Defines for error codes -OLD- */ 885 #define FC_ERROR_BUFFER_OVERFLOW 0xff 886 #define FC_ERROR_RESPONSE_TIMEOUT 0xfe 887 #define FC_ERROR_LINK_UNAVAILABLE 0xfd 888 #define FC_ERROR_INSUFFICIENT_RESOURCES 0xfc 889 #define FC_ERROR_EXISTING_REGISTRATION 0xfb 890 #define FC_ERROR_INVALID_TAG 0xfa 891 #define FC_ERROR_INVALID_WWN 0xf9 892 #define FC_ERROR_CREATEVENT_FAILED 0xf8 893 894 895 896 typedef union dfc_ct_rev 897 { 898 /* Structure is in Big Endian format */ 899 struct 900 { 901 uint32_t Revision:8; 902 uint32_t InId:24; 903 } bits; 904 uint32_t word; 905 } dfc_ct_rev_t; 906 907 typedef union dfc_ct_resp 908 { 909 /* Structure is in Big Endian format */ 910 struct 911 { 912 uint32_t CmdRsp:16; 913 uint32_t Size:16; 914 } bits; 915 uint32_t word; 916 } dfc_ct_resp_t; 917 918 typedef struct dfc_ct_request 919 { 920 /* Structure is in Big Endian format */ 921 dfc_ct_rev_t RevisionId; 922 uint8_t FsType; 923 uint8_t FsSubType; 924 uint8_t Options; 925 uint8_t Rsrvd1; 926 dfc_ct_resp_t CommandResponse; 927 uint8_t Rsrvd2; 928 uint8_t ReasonCode; 929 uint8_t Explanation; 930 uint8_t VendorUnique; 931 } dfc_ct_request_t; 932 933 #define SLI_CT_REVISION 1 934 935 #define FC_FSTYPE_ALL 0xffff /* match on all fsTypes */ 936 937 /* Emulex Vendor-Unique CT Request Command Codes */ 938 #define CT_OP_GSAT 0x0101 /* Get Server Attributes */ 939 #define CT_OP_GHAT 0x0102 /* Get HBA Attributes */ 940 #define CT_OP_GPAT 0x0103 /* Get Port Attributes */ 941 #define CT_OP_GDAT 0x0104 /* Get Driver Attributes */ 942 #define CT_OP_GPST 0x0105 /* Get Port Statistics */ 943 /* 0x0106 is reserved */ 944 #define CT_OP_GDP 0x0107 /* Get Driver Parameters */ 945 #define CT_OP_GDPG 0x0108 /* Get Driver Parameters Global */ 946 #define CT_OP_GEPS 0x0109 /* Get Extended Port Statistics */ 947 #define CT_OP_GLAT 0x010A /* Get Lun Attributes */ 948 949 #define CT_OP_SSAT 0x0111 /* Set Server Attributes */ 950 #define CT_OP_SHAT 0x0112 /* Set HBA Attributes */ 951 #define CT_OP_SPAT 0x0113 /* Set Port Attributes */ 952 #define CT_OP_SDAT 0x0114 /* Set Driver Attributes */ 953 /* 0x0115 is reserved */ 954 /* 0x0116 is reserved */ 955 #define CT_OP_SDP 0x0117 /* Set Driver Parameter */ 956 #define CT_OP_SBBS 0x0118 /* Set Boot Bios State */ 957 958 #define CT_OP_RPST 0x0121 /* Reset Port Statistics */ 959 #define CT_OP_VFW 0x0122 /* Verify Firmware */ 960 #define CT_OP_DFW 0x0123 /* Download Firmware */ 961 #define CT_OP_RES 0x0124 /* Reset HBA */ 962 #define CT_OP_RHD 0x0125 /* Run HBA Diagnostic */ 963 #define CT_OP_UFW 0x0126 /* Upgrade Firmware */ 964 #define CT_OP_RDP 0x0127 /* Reset Driver Parameters */ 965 #define CT_OP_GHDR 0x0128 /* Get HBA Diagnotic Results */ 966 #define CT_OP_CHD 0x0129 /* Cancel HBA Diagnostic */ 967 968 /* 0x0131 is reserved */ 969 /* 0x0132 is reserved */ 970 #define CT_OP_SSR 0x0133 /* Send Software Resource */ 971 972 #define CT_OP_RSAT 0x0141 /* Read SA Table */ 973 #define CT_OP_WSAT 0x0142 /* Write SA Table */ 974 #define CT_OP_RSAH 0x0143 /* Read SA Table Header */ 975 #define CT_OP_WSAH 0x0144 /* Write SA Table Header */ 976 #define CT_OP_RACT 0x0145 /* Read Access Control Table */ 977 #define CT_OP_WACT 0x0146 /* Write Access Control Table */ 978 #define CT_OP_RKT 0x0147 /* Read Key Table Table */ 979 #define CT_OP_WKT 0x0148 /* Write Key Table Table */ 980 #define CT_OP_SSC 0x0149 /* Cause SA Table re-read;sync */ 981 982 #define CT_OP_QHBA 0x0151 /* Query HBA */ 983 #define CT_OP_GST 0x0152 /* Get Status */ 984 985 #define CT_OP_GFTM 0x0161 /* Get FCP Target Mapping */ 986 #define CT_OP_SRL 0x0162 /* SCSI Report Luns */ 987 #define CT_OP_SI 0x0163 /* SCSI Inquiry */ 988 #define CT_OP_SRC 0x0164 /* SCSI Read Capacity */ 989 990 #define CT_OP_GPB 0x0171 /* Get FCP Persistent Binding */ 991 #define CT_OP_SPB 0x0172 /* Set FCP Persistent Binding */ 992 #define CT_OP_RPB 0x0173 /* Remove FCP Persistent Binding */ 993 #define CT_OP_RAPB 0x0174 /* Remove All FCP Persistent Bindings */ 994 #define CT_OP_GBC 0x0175 /* Get Binding Capability */ 995 #define CT_OP_GBS 0x0176 /* Get Binding Support */ 996 #define CT_OP_SBS 0x0177 /* Set Binding Support */ 997 #define CT_OP_GANI 0x0178 /* Get All Nodes Info */ 998 #define CT_OP_GRV 0x0179 /* Get Range Value for Bus#, Target#, Lun# */ 999 #define CT_OP_GAPBS 0x017A /* Get AutoPB service state */ 1000 /* (AutoPilotManager) */ 1001 #define CT_OP_APBC 0x017B /* Configure AutoPB service */ 1002 /* (AutoPilotManager) */ 1003 1004 #define CT_OP_GDT 0x0180 /* Get Driver Type */ 1005 #define CT_OP_GDLMI 0x0181 /* Get Drive Letter Mapping */ 1006 /* Information [GDLM] */ 1007 #define CT_OP_GANA 0x0182 /* Get All Node Addresses */ 1008 #define CT_OP_GDLV 0x0183 /* Get Driver Library Version */ 1009 #define CT_OP_GWUP 0x0184 /* Get Adapter Wakeup Parameters */ 1010 #define CT_OP_GLM 0x0185 /* Get Adapter Loopmap */ 1011 #define CT_OP_GABS 0x0186 /* Get Adapter Beacon State */ 1012 #define CT_OP_SABS 0x0187 /* Set Adapter Beacon State */ 1013 #define CT_OP_RPR 0x0188 /* Read Adapter PCI Registers */ 1014 1015 1016 #ifdef NPIV_SUPPORT 1017 1018 /* NPIV return codes */ 1019 #define DFC_NPIV_SUCCESS 0 1020 #define DFC_NPIV_GENERAL_ERROR 1 1021 #define DFC_NPIV_NOT_SUPPORTED 2 1022 #define DFC_NPIV_NO_RESOURCES 3 1023 #define DFC_NPIV_INVALID_HANDLE 3 1024 #define DFC_NPIV_ILLEGAL_WWPN 4 1025 #define DFC_NPIV_TOO_MANY_VPORTS 4 1026 #define DFC_NPIV_ILLEGAL_WWN 5 1027 #define DFC_NPIV_BUSY 5 1028 #define DFC_NPIV_INVALID_WWN 6 1029 #define DFC_NPIV_LINK_DOWN 7 1030 #define DFC_NPIV_MORE_DATA 7 1031 #define DFC_NPIV_FABRIC_NOT_SUPPORTED 8 1032 #define DFC_NPIV_FABRIC_OUT_OF_RESOURCE 9 1033 #define DFC_NPIV_INVALID_ACCESS_KEY 10 1034 #define DFC_NPIV_INVALID_HANDLE_AT_CREATE 11 1035 #define DFC_NPIV_UNSUPPORTED_OPTION 12 1036 1037 typedef struct dfc_vport_QoS 1038 { 1039 uint32_t resv; 1040 } dfc_vport_QoS_t; 1041 1042 1043 /* VPORT type */ 1044 #define VPORT_TYPE_PHYSICAL 0 1045 #define VPORT_TYPE_VIRTUAL 1 1046 1047 /* VPORT States */ 1048 #define VPORT_STATE_UNKNOWN 0 1049 #define VPORT_STATE_LINKDOWN 1 1050 #define VPORT_STATE_INIT 2 1051 #define VPORT_STATE_NO_FABRIC_SUPPORT 3 1052 #define VPORT_STATE_NO_FABRIC_RESOURCE 4 1053 #define VPORT_STATE_FABRIC_LOGOUT 5 1054 #define VPORT_STATE_FABRIC_REJECT_WWN 6 1055 #define VPORT_STATE_FABRIC_LOGIN_FAIL 7 1056 #define VPORT_STATE_ACTIVE 8 1057 #define VPORT_STATE_AUTH_FAILED 9 1058 1059 /* VPORT Options */ 1060 #define VPORT_OPT_AUTORETRY 0x00000001 1061 #define VPORT_OPT_AUTOWWN 0x00000002 1062 #define VPORT_OPT_ACTIVATE 0x00000004 1063 1064 #define VPORT_OPT_SAVE_CREATE_ONLY 0x00000000 1065 #define VPORT_OPT_SAVE_CREATE_UPDATE 0x00000010 1066 #define VPORT_OPT_SAVE_UPDATE_ONLY 0x00000018 1067 #define VPORT_OPT_SAVE_MASK 0x00000018 1068 1069 #define VPORT_OPT_RESTRICT 0x00000020 1070 #define VPORT_OPT_UNRESTRICT 0x00000040 1071 #define VPORT_OPT_RESTRICT_MASK 0x00000060 1072 1073 #define VPORT_OPT_FAILOVER 0x00000080 1074 1075 /* Check list bit-mapped value */ 1076 #define CL_NPIV_PARM_ENABLE 0x00000001 1077 #define CL_SLI3_ENABLE 0x00000002 1078 #define CL_HBA_SUPPORT_NPIV 0x00000004 1079 #define CL_HBA_HAS_RESOURCES 0x00000008 1080 #define CL_HBA_LINKUP 0x00000010 1081 #define CL_P2P_TOPOLOGY 0x00000020 1082 #define CL_FABRIC_SUPPORTS_NPIV 0x00000040 1083 #define CL_FABRIC_HAS_RESOURCES 0x00000080 1084 #define CL_NPIV_READY 0x000000FF 1085 1086 1087 1088 1089 #define DFC_VPORT_ATTR_VERSION 2 1090 typedef struct dfc_vport_attrs 1091 { 1092 uint8_t version; /* 2 = version of this structure, */ 1093 /* for compatibility check */ 1094 uint8_t reserved1[3]; 1095 1096 uint8_t wwpn[8]; /* virtual port WWPN */ 1097 uint8_t wwnn[8]; /* virtual port WWNN */ 1098 char name[256]; /* name to be register with the */ 1099 /* fabric */ 1100 1101 uint32_t options; 1102 1103 uint32_t portFcId; /* D-ID; set when the N-port is */ 1104 /* created successfully */ 1105 1106 uint8_t state; /* VPORT state */ 1107 uint8_t restrictLogin; 1108 uint8_t reserved2[2]; 1109 uint64_t buf; /* Used for VPI */ 1110 1111 uint8_t fabric_wwn[8]; /* Fabric WWN (WWNN) */ 1112 uint32_t checklist; 1113 uint8_t accessKey[32]; 1114 } dfc_vport_attrs_t; 1115 1116 1117 typedef struct dfc_vport_entry 1118 { 1119 uint8_t wwpn[8]; /* wwpn of the virtual port */ 1120 uint8_t wwnn[8]; /* wwnn of the virtual port */ 1121 uint32_t PortFcId; /* FC port ID assigned to this */ 1122 /* virtual port */ 1123 } dfc_vport_entry_t; 1124 1125 1126 typedef struct dfc_vport_entry_list 1127 { 1128 uint32_t NumberOfEntries; 1129 dfc_vport_entry_t entry[MAX_VPORTS]; 1130 } dfc_vport_entry_list_t; 1131 1132 1133 typedef struct dfc_vport_nodeinfo_entry 1134 { 1135 uint32_t bind_type; 1136 #define VPORT_NODE_BINDDID 0x0000 1137 #define VPORT_NODE_BINDWWNN 0x0001 1138 #define VPORT_NODE_BINDWWPN 0x0002 1139 #define VPORT_NODE_AUTOMAP 0x0004 1140 #define VPORT_NODE_UNMASK_ALL_LUN 0x0008 1141 #define VPORT_NODE_DISABLE_LUN_AUTOMAP 0x0010 1142 #define VPORT_NODE_ALPA 0x0020 1143 1144 HBA_SCSIID scsiId; 1145 HBA_FCPID fcpId; 1146 1147 uint32_t nodeState; 1148 #define VPORT_NODESTATE_EXIST 0x0001 1149 #define VPORT_NODESTATE_READY 0x0002 1150 #define VPORT_NODESTATE_LINKDOWN 0x0004 1151 #define VPORT_NODESTATE_UNMAPPED 0x0008 1152 #define VPORT_NODESTATE_BOUND 0x0010 1153 1154 uint32_t reserved; 1155 } dfc_vport_nodeinfo_entry_t; 1156 1157 typedef struct dfc_vport_get_nodeinfo 1158 { 1159 uint32_t NumberOfEntries; /* number of nodes */ 1160 dfc_vport_nodeinfo_entry_t entry[MAX_NODES]; /* start of array */ 1161 } dfc_vport_get_nodeinfo_t; 1162 1163 1164 typedef struct dfc_vport_resource 1165 { 1166 uint32_t vpi_max; 1167 uint32_t vpi_inuse; 1168 uint32_t rpi_max; 1169 uint32_t rpi_inuse; 1170 } dfc_vport_resource_t; 1171 1172 1173 typedef struct dfc_vlinkinfo 1174 { 1175 uint32_t api_versions; 1176 1177 uint8_t linktype; 1178 uint8_t state; 1179 uint8_t fail_reason; 1180 uint8_t prev_fail_reason; 1181 #define VPORT_FAIL_UNKNOWN 0 1182 #define VPORT_FAIL_LINKDOWN 1 1183 #define VPORT_FAIL_FAB_UNSUPPORTED 2 1184 #define VPORT_FAIL_FAB_NORESOURCES 3 1185 #define VPORT_FAIL_FAB_LOGOUT 4 1186 #define VPORT_FAIL_HBA_NORESOURCES 5 1187 1188 uint8_t wwnn[8]; 1189 uint8_t wwpn[8]; 1190 1191 void *vlink; 1192 1193 uint32_t vpi_max; 1194 uint32_t vpi_inuse; 1195 uint32_t rpi_max; 1196 uint32_t rpi_inuse; 1197 } dfc_vlinkinfo_t; 1198 1199 #endif /* NPIV_SUPPORT */ 1200 1201 1202 #ifdef DHCHAP_SUPPORT 1203 1204 /* DHCHAP return code */ 1205 #define DFC_AUTH_STATUS_NOT_CONFIGURED 0x8001 1206 #define DFC_AUTH_STATUS_AUTH_FAILED_NO_SA_FOUND 0x8002 1207 #define DFC_AUTH_STATUS_AUTH_INIT_OK_AUTH_FAILED 0x8003 1208 #define DFC_AUTH_STATUS_COMPARE_FAILED 0x8004 1209 #define DFC_AUTH_STATUS_WWN_NOT_FOUND 0x8005 1210 #define DFC_AUTH_STATUS_PASSWORD_INVALID 0x8006 1211 #define DFC_AUTH_STATUS_INVALID_ENTITY 0x8007 1212 #define DFC_AUTH_STATUS_ENTITY_NOT_ACTIVE 0x8008 1213 #define DFC_AUTH_STATUS_INVALID_OPERATION 0x8009 1214 #define DFC_AUTH_STATUS_OUT_OF_RESOURCES 0x800a 1215 #define DFC_AUTH_STATUS_AUTHENTICATION_GOINGON 0x800b 1216 #define DFC_AUTH_STATUS_INVALID_BOARD_NO 0x800c 1217 #define DFC_AUTH_STATUS_IO_ERROR 0x800d 1218 #define DFC_AUTH_STATUS_CREATE_STORKEY_ERROR 0x800e 1219 #define DFC_AUTH_STATUS_CREATE_PARMKEY_ERROR 0x800f 1220 #define DFC_AUTH_STATUS_CREATE_AUTHKEY_ERROR 0x8010 1221 #define DFC_AUTH_STATUS_LOCAL_REMOTE_PASSWORD_SAME 0x8011 1222 #define DFC_AUTH_STATUS_CREATE_BORDKEY_ERROR 0x8020 1223 #define DFC_AUTH_STATUS_DRVTYPE_NOT_SUPPORTED 0x8030 1224 #define DFC_AUTH_STATUS_AUTHENTICATION_NOT_SUPPORTED 0x8031 1225 #define DFC_AUTH_STATUS_GENERAL_ERROR 0x8032 1226 #define DFC_AUTH_STATUS_CONFIG_NOT_FOUND 0x8034 1227 #define DFC_AUTH_STATUS_NOT_PRIVILEGE_USER 0x8040 1228 1229 1230 typedef struct dfc_fcsp_config 1231 { 1232 HBA_WWN lwwpn; 1233 HBA_WWN rwwpn; 1234 1235 uint16_t auth_tov; /* seconds */ 1236 #define DFC_AUTH_TOV_MIN 20 1237 #define DFC_AUTH_TOV_MAX 1000 1238 #define DFC_AUTH_TOV_DEFAULT 45 1239 1240 uint8_t auth_mode; 1241 #define DFC_AUTH_MODE_DISABLED 1 1242 #define DFC_AUTH_MODE_ACTIVE 2 1243 #define DFC_AUTH_MODE_PASSIVE 3 1244 #define DFC_AUTH_MODE_DEFAULT DFC_AUTH_MODE_DISABLED 1245 1246 uint8_t auth_bidir:1; 1247 #define DFC_AUTH_BIDIR_DISABLED 0 1248 #define DFC_AUTH_BIDIR_ENABLED 1 1249 #define DFC_AUTH_BIDIR_DEFAULT DFC_AUTH_BIDIR_DISABLED 1250 uint8_t reserved:7; 1251 1252 uint8_t type_priority[4]; 1253 #define DFC_AUTH_TYPE_DHCHAP 1 /* Only one currently supported */ 1254 #define DFC_AUTH_TYPE_FCAP 2 1255 #define DFC_AUTH_TYPE_FCPAP 3 1256 #define DFC_AUTH_TYPE_KERBEROS 4 1257 #define DFC_AUTH_TYPE_MAX 4 1258 #define DFC_AUTH_TYPE_DEFAULT0 DFC_AUTH_TYPE_DHCHAP 1259 #define DFC_AUTH_TYPE_DEFAULT1 0 1260 #define DFC_AUTH_TYPE_DEFAULT2 0 1261 #define DFC_AUTH_TYPE_DEFAULT3 0 1262 1263 uint8_t hash_priority[4]; 1264 #define DFC_AUTH_HASH_MD5 1 1265 #define DFC_AUTH_HASH_SHA1 2 1266 #define DFC_AUTH_HASH_MAX 2 1267 #define DFC_AUTH_HASH_DEFAULT0 DFC_AUTH_HASH_MD5 1268 #define DFC_AUTH_HASH_DEFAULT1 DFC_AUTH_HASH_SHA1 1269 #define DFC_AUTH_HASH_DEFAULT2 0 1270 #define DFC_AUTH_HASH_DEFAULT3 0 1271 1272 uint8_t group_priority[8]; 1273 #define DFC_AUTH_GROUP_NULL 1 1274 #define DFC_AUTH_GROUP_1024 2 1275 #define DFC_AUTH_GROUP_1280 3 1276 #define DFC_AUTH_GROUP_1536 4 1277 #define DFC_AUTH_GROUP_2048 5 1278 #define DFC_AUTH_GROUP_MAX 5 1279 1280 #define DFC_AUTH_GROUP_DEFAULT0 DFC_AUTH_GROUP_NULL 1281 #define DFC_AUTH_GROUP_DEFAULT1 DFC_AUTH_GROUP_1024 1282 #define DFC_AUTH_GROUP_DEFAULT2 DFC_AUTH_GROUP_1280 1283 #define DFC_AUTH_GROUP_DEFAULT3 DFC_AUTH_GROUP_1536 1284 #define DFC_AUTH_GROUP_DEFAULT4 DFC_AUTH_GROUP_2048 1285 #define DFC_AUTH_GROUP_DEFAULT5 0 1286 #define DFC_AUTH_GROUP_DEFAULT6 0 1287 #define DFC_AUTH_GROUP_DEFAULT7 0 1288 1289 uint32_t reauth_tov; /* minutes */ 1290 #define DFC_REAUTH_TOV_MIN 0 1291 #define DFC_REAUTH_TOV_MAX 7200 1292 #define DFC_REAUTH_TOV_DEFAULT 1440 1293 } dfc_fcsp_config_t; 1294 1295 1296 typedef struct dfc_password 1297 { 1298 uint16_t length; 1299 #define DFC_PASSWORD_LENGTH_MIN 8 1300 #define DFC_PASSWORD_LENGTH_MAX 128 1301 1302 uint16_t type; 1303 #define DFC_PASSWORD_TYPE_ASCII 1 1304 #define DFC_PASSWORD_TYPE_BINARY 2 1305 #define DFC_PASSWORD_TYPE_IGNORE 3 1306 1307 uint8_t password[DFC_PASSWORD_LENGTH_MAX]; 1308 } dfc_password_t; 1309 1310 typedef struct dfc_auth_password 1311 { 1312 HBA_WWN lwwpn; 1313 HBA_WWN rwwpn; 1314 1315 dfc_password_t lpw; 1316 dfc_password_t rpw; 1317 1318 dfc_password_t lpw_new; 1319 dfc_password_t rpw_new; 1320 } dfc_auth_password_t; 1321 1322 1323 typedef struct dfc_auth_cfglist 1324 { 1325 uint32_t cnt; 1326 HBA_WWN rwwpn[1]; 1327 } dfc_auth_cfglist_t; 1328 1329 1330 typedef struct dfc_auth_status 1331 { 1332 HBA_WWN lwwpn; 1333 HBA_WWN rwwpn; 1334 1335 uint8_t auth_state; 1336 #define DFC_AUTH_STATE_OFF 1 1337 #define DFC_AUTH_STATE_INP 2 1338 #define DFC_AUTH_STATE_ON 3 1339 #define DFC_AUTH_STATE_FAILED 4 1340 1341 uint8_t auth_failReason; 1342 #define DFC_AUTH_FAIL_GENERIC 1 1343 #define DFC_AUTH_FAIL_ELS_TMO 2 1344 #define DFC_AUTH_FAIL_XACT_TMO 3 1345 #define DFC_AUTH_FAIL_LS_RJT 4 1346 #define DFC_AUTH_FAIL_BSY_LS_RJT 5 1347 #define DFC_AUTH_FAIL_REJECTED 6 1348 1349 uint8_t type_priority; 1350 uint8_t group_priority; 1351 1352 uint8_t hash_priority; 1353 uint8_t localAuth :1; 1354 uint8_t remoteAuth :1; 1355 uint8_t pad :6; 1356 uint16_t reserved0; 1357 1358 uint32_t time_from_last_auth; /* seconds */ 1359 uint32_t time_until_next_auth; /* seconds */ 1360 1361 uint32_t reserved1; 1362 uint32_t reserved2; 1363 } dfc_auth_status_t; 1364 1365 #endif /* DHCHAP_SUPPORT */ 1366 1367 /* 1368 * Start of FCP specific structures 1369 */ 1370 1371 #ifndef MAX_FCP_SNS 1372 typedef struct emlxs_fcp_rsp 1373 { 1374 uint32_t rspRsvd1; /* FC Word 0, byte 0:3 */ 1375 uint32_t rspRsvd2; /* FC Word 1, byte 0:3 */ 1376 1377 uint8_t rspStatus0; /* FCP_STATUS byte 0 (reserved) */ 1378 uint8_t rspStatus1; /* FCP_STATUS byte 1 (reserved) */ 1379 uint8_t rspStatus2; /* FCP_STATUS byte 2 field validity */ 1380 #define RSP_LEN_VALID 0x01 /* bit 0 */ 1381 #define SNS_LEN_VALID 0x02 /* bit 1 */ 1382 #define RESID_OVER 0x04 /* bit 2 */ 1383 #define RESID_UNDER 0x08 /* bit 3 */ 1384 uint8_t rspStatus3; /* FCP_STATUS byte 3 SCSI status byte */ 1385 #define SCSI_STAT_GOOD 0x00 1386 #define SCSI_STAT_CHECK_COND 0x02 1387 #define SCSI_STAT_COND_MET 0x04 1388 #define SCSI_STAT_BUSY 0x08 1389 #define SCSI_STAT_INTERMED 0x10 1390 #define SCSI_STAT_INTERMED_CM 0x14 1391 #define SCSI_STAT_RES_CNFLCT 0x18 1392 #define SCSI_STAT_CMD_TERM 0x22 1393 #define SCSI_STAT_QUE_FULL 0x28 1394 #define SCSI_STAT_ACA_ACTIVE 0x30 1395 #define SCSI_STAT_TASK_ABORT 0x40 1396 1397 uint32_t rspResId; /* Residual xfer if RESID_xxxx set in */ 1398 /* fcpStatus2 */ 1399 /* Received in Big Endian format */ 1400 uint32_t rspSnsLen; /* Length of sense data in fcpSnsInfo */ 1401 /* received in Big Endian format */ 1402 uint32_t rspRspLen; /* Length of FCP response data in */ 1403 /* fcpRspInfo */ 1404 /* Received In Big Endian format */ 1405 1406 uint8_t rspInfo0; /* FCP_RSP_INFO byte 0 (reserved) */ 1407 uint8_t rspInfo1; /* FCP_RSP_INFO byte 1 (reserved) */ 1408 uint8_t rspInfo2; /* FCP_RSP_INFO byte 2 (reserved) */ 1409 uint8_t rspInfo3; /* FCP_RSP_INFO RSP_CODE byte 3 */ 1410 1411 #define RSP_NO_FAILURE 0x00 1412 #define RSP_DATA_BURST_ERR 0x01 1413 #define RSP_CMD_FIELD_ERR 0x02 1414 #define RSP_RO_MISMATCH_ERR 0x03 1415 #define RSP_TM_NOT_SUPPORTED 0x04 /* Task mgmt function not supported */ 1416 #define RSP_TM_NOT_COMPLETED 0x05 /* Task mgmt function not performed */ 1417 1418 uint32_t rspInfoRsvd; /* FCP_RSP_INFO bytes 4-7 (reserved) */ 1419 1420 /* 1421 * Define maximum size of SCSI Sense buffer. 1422 * Seagate never issues more than 18 bytes of Sense data. 1423 */ 1424 #define MAX_FCP_SNS 128 1425 uint8_t rspSnsInfo[MAX_FCP_SNS]; 1426 } emlxs_fcp_rsp; 1427 typedef emlxs_fcp_rsp FCP_RSP; 1428 #endif /* MAX_FCP_SNS */ 1429 1430 1431 #ifndef FC_LUN_SHIFT 1432 typedef struct emlxs_fcp_cmd 1433 { 1434 uint32_t fcpLunMsl; /* most significant word (32 bits) */ 1435 uint32_t fcpLunLsl; /* least significant word (32 bits) */ 1436 1437 /* 1438 * # of bits to shift lun id to end up in right payload word, 1439 * little endian = 8, big = 16. 1440 */ 1441 #ifdef EMLXS_LITTLE_ENDIAN 1442 #define FC_LUN_SHIFT 8 1443 #define FC_ADDR_MODE_SHIFT 0 1444 #endif 1445 #ifdef EMLXS_BIG_ENDIAN 1446 #define FC_LUN_SHIFT 16 1447 #define FC_ADDR_MODE_SHIFT 24 1448 #endif 1449 1450 uint8_t fcpCntl0; /* FCP_CNTL byte 0 (reserved) */ 1451 uint8_t fcpCntl1; /* FCP_CNTL byte 1 task codes */ 1452 #define SIMPLE_Q 0x00 1453 #define HEAD_OF_Q 0x01 1454 #define ORDERED_Q 0x02 1455 #define ACA_Q 0x04 1456 #define UNTAGGED 0x05 1457 1458 uint8_t fcpCntl2; /* FCP_CTL byte 2 task management */ 1459 /* codes */ 1460 #define ABORT_TASK_SET 0x02 /* Bit 1 */ 1461 #define CLEAR_TASK_SET 0x04 /* bit 2 */ 1462 #define LUN_RESET 0x10 /* bit 4 */ 1463 #define TARGET_RESET 0x20 /* bit 5 */ 1464 #define CLEAR_ACA 0x40 /* bit 6 */ 1465 #define TERMINATE_TASK 0x80 /* bit 7 */ 1466 1467 uint8_t fcpCntl3; 1468 #define WRITE_DATA 0x01 /* Bit 0 */ 1469 #define READ_DATA 0x02 /* Bit 1 */ 1470 1471 uint8_t fcpCdb[16]; /* SRB cdb field is copied here */ 1472 uint32_t fcpDl; /* Total transfer length */ 1473 } emlxs_fcp_cmd_t; 1474 typedef emlxs_fcp_cmd_t FCP_CMND; 1475 #endif /* FC_LUN_SHIFT */ 1476 1477 1478 /* 1479 * Used by libdfc (SendScsiCmd, SendFcpCmd, DFC_SendScsiCmdV2, DFC_SendFcpCmdV2 1480 * and emlxs_dfc_send_scsi_fcp functions 1481 */ 1482 typedef struct dfc_send_scsi_fcp_cmd_info 1483 { 1484 HBA_WWN src_wwn; 1485 HBA_WWN dst_wwn; 1486 uint32_t cnt1; 1487 uint32_t cnt2; 1488 uint32_t ver; 1489 } dfc_send_scsi_fcp_cmd_info_t; 1490 1491 #define SCSI_RSP_CNT(x) x.cnt1 1492 #define SCSI_SNS_CNT(x) x.cnt2 1493 #define FC_DATA_CNT(x) x.cnt1 1494 #define FC_RSP_CNT(x) x.cnt2 1495 #define DFC_SEND_SCSI_FCP_V1 1 1496 #define DFC_SEND_SCSI_FCP_V2 2 1497 1498 #ifdef __cplusplus 1499 } 1500 #endif 1501 1502 #endif /* _EMLXS_DFCLIB_H */ 1503