1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Emulex. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * Header file containing the command structures for Hardware 29 */ 30 31 #ifndef _OCE_HW_H_ 32 #define _OCE_HW_H_ 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #include <sys/types.h> 39 40 #pragma pack(1) 41 42 /* PCI CSR offsets */ 43 #define PCICFG_F1_CSR 0x0 /* F1 for NIC */ 44 #define PCICFG_SEMAPHORE 0xbc 45 #define PCICFG_SOFT_RESET 0x5c 46 #define PCICFG_UE_STATUS_HI_MASK 0xac 47 #define PCICFG_UE_STATUS_LO_MASK 0xa8 48 #define PCICFG_ONLINE0 0xb0 49 #define PCICFG_ONLINE1 0xb4 50 #define INTR_EN 0x20000000 51 #define IMAGE_TRANSFER_SIZE (32 * 1024) /* 32K at a time */ 52 53 /* CSR register offsets */ 54 #define MPU_EP_CONTROL 0 55 #define MPU_EP_SEMAPHORE 0xac 56 #define PCICFG_INTR_CTRL 0xfc 57 #define HOSTINTR_MASK (1 << 29) 58 #define HOSTINTR_PFUNC_SHIFT 26 59 #define HOSTINTR_PFUNC_MASK 7 60 61 /* POST status reg struct */ 62 #define POST_STAGE_POWER_ON_RESET 0x00 63 #define POST_STAGE_AWAITING_HOST_RDY 0x01 64 #define POST_STAGE_HOST_RDY 0x02 65 #define POST_STAGE_CHIP_RESET 0x03 66 #define POST_STAGE_ARMFW_READY 0xc000 67 #define POST_STAGE_ARMFW_UE 0xf000 68 69 /* DOORBELL registers */ 70 #define PD_RXULP_DB 0x0100 71 #define PD_TXULP_DB 0x0060 72 #define DB_RQ_ID_MASK 0x3FF 73 74 #define PD_CQ_DB 0x0120 75 #define PD_EQ_DB PD_CQ_DB 76 #define PD_MPU_MBOX_DB 0x0160 77 #define PD_MQ_DB 0x0140 78 79 /* EQE completion types */ 80 #define EQ_MINOR_CODE_COMPLETION 0x00 81 #define EQ_MINOR_CODE_OTHER 0x01 82 #define EQ_MAJOR_CODE_COMPLETION 0x00 83 84 /* Link Status field values */ 85 #define PHY_LINK_FAULT_NONE 0x0 86 #define PHY_LINK_FAULT_LOCAL 0x01 87 #define PHY_LINK_FAULT_REMOTE 0x02 88 89 #define PHY_LINK_SPEED_ZERO 0x0 /* No link */ 90 #define PHY_LINK_SPEED_10MBPS 0x1 /* (10 Mbps) */ 91 #define PHY_LINK_SPEED_100MBPS 0x2 /* (100 Mbps) */ 92 #define PHY_LINK_SPEED_1GBPS 0x3 /* (1 Gbps) */ 93 #define PHY_LINK_SPEED_10GBPS 0x4 /* (10 Gbps) */ 94 95 #define PHY_LINK_DUPLEX_NONE 0x0 96 #define PHY_LINK_DUPLEX_HALF 0x1 97 #define PHY_LINK_DUPLEX_FULL 0x2 98 99 #define NTWK_PORT_A 0x0 /* (Port A) */ 100 #define NTWK_PORT_B 0x1 /* (Port B) */ 101 102 #define PHY_LINK_SPEED_ZERO 0x0 /* (No link.) */ 103 #define PHY_LINK_SPEED_10MBPS 0x1 /* (10 Mbps) */ 104 #define PHY_LINK_SPEED_100MBPS 0x2 /* (100 Mbps) */ 105 #define PHY_LINK_SPEED_1GBPS 0x3 /* (1 Gbps) */ 106 #define PHY_LINK_SPEED_10GBPS 0x4 /* (10 Gbps) */ 107 108 /* Hardware Address types */ 109 #define MAC_ADDRESS_TYPE_STORAGE 0x0 /* (Storage MAC Address) */ 110 #define MAC_ADDRESS_TYPE_NETWORK 0x1 /* (Network MAC Address) */ 111 #define MAC_ADDRESS_TYPE_PD 0x2 /* (Protection Domain MAC Addr) */ 112 #define MAC_ADDRESS_TYPE_MANAGEMENT 0x3 /* (Management MAC Address) */ 113 #define MAC_ADDRESS_TYPE_FCOE 0x4 /* (FCoE MAC Address) */ 114 115 /* CREATE_IFACE capability and cap_en flags */ 116 #define MBX_RX_IFACE_FLAGS_RSS 0x4 117 #define MBX_RX_IFACE_FLAGS_PROMISCUOUS 0x8 118 #define MBX_RX_IFACE_FLAGS_BROADCAST 0x10 119 #define MBX_RX_IFACE_FLAGS_UNTAGGED 0x20 120 #define MBX_RX_IFACE_FLAGS_ULP 0x40 121 #define MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS 0x80 122 #define MBX_RX_IFACE_FLAGS_VLAN 0x100 123 #define MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS 0x200 124 #define MBX_RX_IFACE_FLAGS_PASS_L2 0x400 125 #define MBX_RX_IFACE_FLAGS_PASS_L3L4 0x800 126 127 #define MQ_RING_CONTEXT_SIZE_16 0x5 /* (16 entries) */ 128 #define MQ_RING_CONTEXT_SIZE_32 0x6 /* (32 entries) */ 129 #define MQ_RING_CONTEXT_SIZE_64 0x7 /* (64 entries) */ 130 #define MQ_RING_CONTEXT_SIZE_128 0x8 /* (128 entries) */ 131 132 133 #define MBX_DB_READY_BIT 0x1 134 #define MBX_DB_HI_BIT 0x2 135 #define ASYNC_EVENT_CODE_LINK_STATE 0x1 136 #define ASYNC_EVENT_LINK_UP 0x1 137 #define ASYNC_EVENT_LINK_DOWN 0x0 138 139 /* port link_status */ 140 #define ASYNC_EVENT_LOGICAL 0x02 141 142 /* Logical Link Status */ 143 #define NTWK_LOGICAL_LINK_DOWN 0 144 #define NTWK_LOGICAL_LINK_UP 1 145 146 /* Rx filter bits */ 147 #define NTWK_RX_FILTER_IP_CKSUM 0x1 148 #define NTWK_RX_FILTER_TCP_CKSUM 0x2 149 #define NTWK_RX_FILTER_UDP_CKSUM 0x4 150 #define NTWK_RX_FILTER_STRIP_CRC 0x8 151 152 /* max SGE per mbx */ 153 #define MAX_MBX_SGE 19 154 155 /* physical address structure to be used in MBX */ 156 struct phys_addr { 157 /* dw0 */ 158 uint32_t lo; 159 /* dw1 */ 160 uint32_t hi; 161 }; 162 163 typedef union pcicfg_intr_ctl_u { 164 uint32_t dw0; 165 struct { 166 #ifdef _BIG_ENDIAN 167 uint32_t winselect:2; 168 uint32_t hostintr:1; 169 uint32_t pfnum:3; 170 uint32_t vf_cev_int_line_en:1; 171 uint32_t winaddr:23; 172 uint32_t membarwinen:1; 173 #else 174 uint32_t membarwinen:1; 175 uint32_t winaddr:23; 176 uint32_t vf_cev_int_line_en:1; 177 uint32_t pfnum:3; 178 uint32_t hostintr:1; 179 uint32_t winselect:2; 180 #endif 181 } bits; 182 }pcicfg_intr_ctl_t; 183 184 typedef union pcicfg_semaphore_u { 185 uint32_t dw0; 186 struct { 187 #ifdef _BIG_ENDIAN 188 uint32_t rsvd:31; 189 uint32_t lock:1; 190 #else 191 uint32_t lock:1; 192 uint32_t rsvd:31; 193 #endif 194 }bits; 195 }pcicfg_semaphore_t; 196 197 typedef union pcicfg_soft_reset_u { 198 uint32_t dw0; 199 struct { 200 #ifdef _BIG_ENDIAN 201 uint32_t nec_ll_rcvdetect:8; 202 uint32_t dbg_all_reqs_62_49:14; 203 uint32_t scratchpad0:1; 204 uint32_t exception_oe:1; 205 uint32_t soft_reset:1; 206 uint32_t rsvd0:7; 207 #else 208 uint32_t rsvd0:7; 209 uint32_t soft_reset:1; 210 uint32_t exception_oe:1; 211 uint32_t scratchpad0:1; 212 uint32_t dbg_all_reqs_62_49:14; 213 uint32_t nec_ll_rcvdetect:8; 214 #endif 215 }bits; 216 }pcicfg_soft_reset_t; 217 218 typedef union pcicfg_online1_u { 219 uint32_t dw0; 220 struct { 221 #ifdef _BIG_ENDIAN 222 uint32_t host8_online:1; 223 uint32_t host7_online:1; 224 uint32_t host6_online:1; 225 uint32_t host5_online:1; 226 uint32_t host4_online:1; 227 uint32_t host3_online:1; 228 uint32_t host2_online:1; 229 uint32_t ipc_online:1; 230 uint32_t arm_online:1; 231 uint32_t txp_online:1; 232 uint32_t xaui_online:1; 233 uint32_t rxpp_online:1; 234 uint32_t txpb_online:1; 235 uint32_t rr_online:1; 236 uint32_t pmem_online:1; 237 uint32_t pctl1_online:1; 238 uint32_t pctl0_online:1; 239 uint32_t pcs1online_online:1; 240 uint32_t mpu_iram_online:1; 241 uint32_t pcs0online_online:1; 242 uint32_t mgmt_mac_online:1; 243 uint32_t lpcmemhost_online:1; 244 #else 245 uint32_t lpcmemhost_online:1; 246 uint32_t mgmt_mac_online:1; 247 uint32_t pcs0online_online:1; 248 uint32_t mpu_iram_online:1; 249 uint32_t pcs1online_online:1; 250 uint32_t pctl0_online:1; 251 uint32_t pctl1_online:1; 252 uint32_t pmem_online:1; 253 uint32_t rr_online:1; 254 uint32_t txpb_online:1; 255 uint32_t rxpp_online:1; 256 uint32_t xaui_online:1; 257 uint32_t txp_online:1; 258 uint32_t arm_online:1; 259 uint32_t ipc_online:1; 260 uint32_t host2_online:1; 261 uint32_t host3_online:1; 262 uint32_t host4_online:1; 263 uint32_t host5_online:1; 264 uint32_t host6_online:1; 265 uint32_t host7_online:1; 266 uint32_t host8_online:1; 267 #endif 268 }bits; 269 }pcicfg_online1_t; 270 271 typedef union mpu_ep_semaphore_u { 272 uint32_t dw0; 273 struct { 274 #ifdef _BIG_ENDIAN 275 uint32_t error:1; 276 uint32_t backup_fw:1; 277 uint32_t iscsi_no_ip:1; 278 uint32_t iscsi_ip_conflict:1; 279 uint32_t option_rom_installed:1; 280 uint32_t iscsi_drv_loaded:1; 281 uint32_t rsvd0:10; 282 uint32_t stage:16; 283 #else 284 uint32_t stage:16; 285 uint32_t rsvd0:10; 286 uint32_t iscsi_drv_loaded:1; 287 uint32_t option_rom_installed:1; 288 uint32_t iscsi_ip_conflict:1; 289 uint32_t iscsi_no_ip:1; 290 uint32_t backup_fw:1; 291 uint32_t error:1; 292 #endif 293 }bits; 294 }mpu_ep_semaphore_t; 295 296 typedef union mpu_ep_control_u { 297 uint32_t dw0; 298 struct { 299 #ifdef _BIG_ENDIAN 300 uint32_t cpu_reset:1; 301 uint32_t rsvd1:15; 302 uint32_t ep_ram_init_status:1; 303 uint32_t rsvd0:12; 304 uint32_t m2_rxpbuf:1; 305 uint32_t m1_rxpbuf:1; 306 uint32_t m0_rxpbuf:1; 307 #else 308 uint32_t m0_rxpbuf:1; 309 uint32_t m1_rxpbuf:1; 310 uint32_t m2_rxpbuf:1; 311 uint32_t rsvd0:12; 312 uint32_t ep_ram_init_status:1; 313 uint32_t rsvd1:15; 314 uint32_t cpu_reset:1; 315 #endif 316 }bits; 317 }mpu_ep_control_t; 318 319 /* RX doorbell */ 320 typedef union pd_rxulp_db_u { 321 uint32_t dw0; 322 struct { 323 #ifdef _BIG_ENDIAN 324 uint32_t num_posted:8; 325 uint32_t invalidate:1; 326 uint32_t rsvd1:13; 327 uint32_t qid:10; 328 #else 329 uint32_t qid:10; 330 uint32_t rsvd1:13; 331 uint32_t invalidate:1; 332 uint32_t num_posted:8; 333 #endif 334 }bits; 335 }pd_rxulp_db_t; 336 337 /* TX doorbell */ 338 typedef union pd_txulp_db_u { 339 uint32_t dw0; 340 struct { 341 #ifdef _BIG_ENDIAN 342 uint32_t rsvd1:2; 343 uint32_t num_posted:14; 344 uint32_t rsvd0:6; 345 uint32_t qid:10; 346 #else 347 uint32_t qid:10; 348 uint32_t rsvd0:6; 349 uint32_t num_posted:14; 350 uint32_t rsvd1:2; 351 #endif 352 }bits; 353 }pd_txulp_db_t; 354 355 /* CQ doorbell */ 356 typedef union cq_db_u { 357 uint32_t dw0; 358 struct { 359 #ifdef _BIG_ENDIAN 360 uint32_t rsvd1:2; 361 uint32_t rearm:1; 362 uint32_t num_popped:13; 363 uint32_t rsvd0:5; 364 uint32_t event:1; 365 uint32_t qid:10; 366 #else 367 uint32_t qid:10; 368 uint32_t event:1; 369 uint32_t rsvd0:5; 370 uint32_t num_popped:13; 371 uint32_t rearm:1; 372 uint32_t rsvd1:2; 373 #endif 374 }bits; 375 }cq_db_t; 376 377 /* EQ doorbell */ 378 typedef union eq_db_u { 379 uint32_t dw0; 380 struct { 381 #ifdef _BIG_ENDIAN 382 uint32_t rsvd1:2; 383 uint32_t rearm:1; 384 uint32_t num_popped:13; 385 uint32_t rsvd0:5; 386 uint32_t event:1; 387 uint32_t clrint:1; 388 uint32_t qid:9; 389 #else 390 uint32_t qid:9; 391 uint32_t clrint:1; 392 uint32_t event:1; 393 uint32_t rsvd0:5; 394 uint32_t num_popped:13; 395 uint32_t rearm:1; 396 uint32_t rsvd1:2; 397 #endif 398 }bits; 399 }eq_db_t; 400 401 /* bootstrap mbox doorbell */ 402 typedef union pd_mpu_mbox_db_u { 403 uint32_t dw0; 404 struct { 405 #ifdef _BIG_ENDIAN 406 uint32_t address:30; 407 uint32_t hi:1; 408 uint32_t ready:1; 409 #else 410 uint32_t ready:1; 411 uint32_t hi:1; 412 uint32_t address:30; 413 #endif 414 }bits; 415 }pd_mpu_mbox_db_t; 416 417 418 /* MQ ring doorbell */ 419 typedef union pd_mq_db_u { 420 uint32_t dw0; 421 struct { 422 #ifdef _BIG_ENDIAN 423 uint32_t rsvd1:2; 424 uint32_t num_posted:14; 425 uint32_t rsvd0:5; 426 uint32_t mq_id:11; 427 #else 428 uint32_t mq_id:11; 429 uint32_t rsvd0:5; 430 uint32_t num_posted:14; 431 uint32_t rsvd1:2; 432 #endif 433 }bits; 434 }pd_mq_db_t; 435 436 /* 437 * Event Queue Entry 438 */ 439 struct oce_eqe { 440 union { 441 struct { 442 #ifdef _BIG_ENDIAN 443 uint32_t resource_id:16; 444 uint32_t minor_code:12; 445 uint32_t major_code:3; 446 uint32_t valid:1; 447 #else 448 uint32_t valid:1; 449 uint32_t major_code:3; 450 uint32_t minor_code:12; 451 uint32_t resource_id:16; 452 #endif 453 }s; 454 uint32_t dw0; 455 }u0; 456 }; 457 458 /* MQ scatter gather entry. Array of these make an SGL */ 459 struct oce_mq_sge { 460 uint32_t pa_lo; 461 uint32_t pa_hi; 462 uint32_t length; 463 }; 464 465 /* 466 * payload can contain an SGL or an embedded array of upto 59 dwords 467 */ 468 struct oce_mbx_payload { 469 union { 470 union { 471 struct oce_mq_sge sgl[MAX_MBX_SGE]; 472 uint32_t embedded[59]; 473 }u1; 474 uint32_t dw[59]; 475 }u0; 476 }; 477 478 /* 479 * MQ MBX structure 480 */ 481 struct oce_mbx { 482 union { 483 struct { 484 #ifdef _BIG_ENDIAN 485 uint32_t special : 8; 486 uint32_t rsvd1 : 16; 487 uint32_t sge_count : 5; 488 uint32_t rsvd0 : 2; 489 uint32_t embedded : 1; 490 #else 491 uint32_t embedded:1; 492 uint32_t rsvd0:2; 493 uint32_t sge_count:5; 494 uint32_t rsvd1:16; 495 uint32_t special:8; 496 #endif 497 }s; 498 uint32_t dw0; 499 }u0; 500 501 uint32_t payload_length; 502 uint32_t tag[2]; 503 uint32_t rsvd2[1]; 504 struct oce_mbx_payload payload; 505 }; 506 507 /* completion queue entry for MQ */ 508 struct oce_mq_cqe { 509 union { 510 struct { 511 #ifdef _BIG_ENDIAN 512 /* dw0 */ 513 uint32_t extended_status:16; 514 uint32_t completion_status:16; 515 /* dw1 dw2 */ 516 uint32_t mq_tag[2]; 517 /* dw3 */ 518 uint32_t valid:1; 519 uint32_t async_event:1; 520 uint32_t hpi_buffer_cmpl:1; 521 uint32_t completed:1; 522 uint32_t consumed:1; 523 uint32_t rsvd0:27; 524 #else 525 /* dw0 */ 526 uint32_t completion_status:16; 527 uint32_t extended_status:16; 528 /* dw1 dw2 */ 529 uint32_t mq_tag[2]; 530 /* dw3 */ 531 uint32_t rsvd0:27; 532 uint32_t consumed:1; 533 uint32_t completed:1; 534 uint32_t hpi_buffer_cmpl:1; 535 uint32_t async_event:1; 536 uint32_t valid:1; 537 #endif 538 }s; 539 uint32_t dw[4]; 540 }u0; 541 }; 542 543 struct oce_async_cqe_link_state { 544 union { 545 struct { 546 #ifdef _BIG_ENDIAN 547 /* dw0 */ 548 uint8_t speed; 549 uint8_t duplex; 550 uint8_t link_status; 551 uint8_t phy_port; 552 /* dw1 */ 553 uint8_t rsvd0[3]; 554 uint8_t fault; 555 /* dw2 */ 556 uint32_t event_tag; 557 /* dw3 */ 558 uint32_t valid:1; 559 uint32_t async_event:1; 560 uint32_t rsvd2:6; 561 uint32_t event_type:8; 562 uint32_t event_code:8; 563 uint32_t rsvd1:8; 564 #else 565 /* dw0 */ 566 uint8_t phy_port; 567 uint8_t link_status; 568 uint8_t duplex; 569 uint8_t speed; 570 /* dw1 */ 571 uint8_t fault; 572 uint8_t rsvd0[3]; 573 /* dw2 */ 574 uint32_t event_tag; 575 /* dw3 */ 576 uint32_t rsvd1:8; 577 uint32_t event_code:8; 578 uint32_t event_type:8; 579 uint32_t rsvd2:6; 580 uint32_t async_event:1; 581 uint32_t valid:1; 582 #endif 583 }s; 584 uint32_t dw[4]; 585 }u0; 586 }; 587 588 /* MQ mailbox structure */ 589 struct oce_bmbx { 590 struct oce_mbx mbx; 591 struct oce_mq_cqe cqe; 592 }; 593 594 /* ---[ MBXs start here ]---------------------------------------------- */ 595 /* MBXs sub system codes */ 596 enum { 597 MBX_SUBSYSTEM_RSVD = 0, 598 MBX_SUBSYSTEM_COMMON = 1, 599 MBX_SUBSYSTEM_COMMON_ISCSI = 2, 600 MBX_SUBSYSTEM_NIC = 3, 601 MBX_SUBSYSTEM_TOE = 4, 602 MBX_SUBSYSTEM_PXE_UNDI = 5, 603 MBX_SUBSYSTEM_ISCSI_INI = 6, 604 MBX_SUBSYSTEM_ISCSI_TGT = 7, 605 MBX_SUBSYSTEM_MILI_PTL = 8, 606 MBX_SUBSYSTEM_MILI_TMD = 9, 607 MBX_SUBSYSTEM_RDMA = 10, 608 MBX_SUBSYSTEM_LOWLEVEL = 11, 609 MBX_SUBSYSTEM_LRO = 13, 610 IOCBMBX_SUBSYSTEM_DCBX = 15, 611 IOCBMBX_SUBSYSTEM_DIAG = 16, 612 IOCBMBX_SUBSYSTEM_VENDOR = 17 613 }; 614 615 /* common ioctl opcodes */ 616 enum { 617 OPCODE_QUERY_COMMON_IFACE_MAC = 1, 618 OPCODE_SET_COMMON_IFACE_MAC = 2, 619 OPCODE_SET_COMMON_IFACE_MULTICAST = 3, 620 OPCODE_CONFIG_COMMON_IFACE_VLAN = 4, 621 OPCODE_QUERY_COMMON_LINK_STATUS = 5, 622 OPCODE_READ_COMMON_FLASHROM = 6, 623 OPCODE_WRITE_COMMON_FLASHROM = 7, 624 OPCODE_QUERY_COMMON_MAX_MBX_BUFFER_SIZE = 8, 625 OPCODE_ADD_COMMON_PAGE_TABLES = 9, 626 OPCODE_REMOVE_COMMON_PAGE_TABLES = 10, 627 OPCODE_CREATE_COMMON_CQ = 12, 628 OPCODE_CREATE_COMMON_EQ = 13, 629 OPCODE_CREATE_COMMON_MQ = 21, 630 OPCODE_COMMON_JELL_CONFIG = 22, 631 OPCODE_COMMON_ADD_TEMPLATE_HEADER_BUFFERS = 24, 632 OPCODE_COMMON_REMOVE_TEMPLATE_HEADER_BUFFERS = 25, 633 OPCODE_COMMON_POST_ZERO_BUFFER = 26, 634 OPCODE_COMMON_GET_QOS = 27, 635 OPCODE_COMMON_SET_QOS = 28, 636 OPCODE_COMMON_TCP_GET_STATISTICS = 29, 637 OPCODE_READ_COMMON_SEEPROM = 30, 638 OPCODE_COMMON_TCP_STATE_QUERY = 31, 639 OPCODE_GET_COMMON_CNTL_ATTRIBUTES = 32, 640 OPCODE_COMMON_NOP = 33, 641 OPCODE_COMMON_NTWK_RX_FILTER = 34, 642 OPCODE_GET_COMMON_FW_VERSION = 35, 643 OPCODE_SET_COMMON_FLOW_CONTROL = 36, 644 OPCODE_GET_COMMON_FLOW_CONTROL = 37, 645 OPCODE_COMMON_SET_TCP_PARAMETERS = 38, 646 OPCODE_SET_COMMON_FRAME_SIZE = 39, 647 OPCODE_COMMON_GET_FAT = 40, 648 OPCODE_MODIFY_COMMON_EQ_DELAY = 41, 649 OPCODE_COMMON_FIRMWARE_CONFIG = 42, 650 OPCODE_COMMON_ENABLE_DISABLE_DOMAINS = 43, 651 OPCODE_COMMON_GET_DOMAIN_CONFIG = 44, 652 OPCODE_COMMON_GET_PORT_EQUALIZATION = 47, 653 OPCODE_COMMON_SET_PORT_EQUALIZATION = 48, 654 OPCODE_COMMON_RED_CONFIG = 49, 655 OPCODE_CREATE_COMMON_IFACE = 50, 656 OPCODE_DESTROY_COMMON_IFACE = 51, 657 OPCODE_COMMON_CEV_MODIFY_MSI_MESSAGES = 52, 658 OPCODE_DESTROY_COMMON_MQ = 53, 659 OPCODE_DESTROY_COMMON_CQ = 54, 660 OPCODE_DESTROY_COMMON_EQ = 55, 661 OPCODE_COMMON_TCP_UPL_OAD = 56, 662 OPCODE_SET_COMMON_LINK_SPEED = 57, 663 OPCODE_QUERY_COMMON_FIRMWARE_CONFIG = 58, 664 OPCODE_ADD_COMMON_IFACE_MAC = 59, 665 OPCODE_DEL_COMMON_IFACE_MAC = 60, 666 OPCODE_COMMON_FUNCTION_RESET = 61, 667 OPCODE_COMMON_FUNCTION_LINK_CONFIG = 80 668 }; 669 670 /* common ioctl header */ 671 struct mbx_hdr { 672 union { 673 struct { 674 #ifdef _BIG_ENDIAN 675 uint8_t domain; 676 uint8_t port_number; 677 uint8_t subsystem; 678 uint8_t opcode; 679 #else 680 uint8_t opcode; 681 uint8_t subsystem; 682 uint8_t port_number; 683 uint8_t domain; 684 #endif 685 uint32_t timeout; 686 uint32_t request_length; 687 uint32_t rsvd0; 688 }req; 689 690 struct { 691 /* dw 0 */ 692 uint8_t opcode; 693 uint8_t subsystem; 694 uint8_t rsvd0; 695 uint8_t domain; 696 /* dw 1 */ 697 uint8_t status; 698 uint8_t additional_status; 699 uint16_t rsvd1; 700 701 uint32_t rsp_length; 702 uint32_t actual_rsp_length; 703 }rsp; 704 uint32_t dw[4]; 705 }u0; 706 }; 707 #define OCE_BMBX_RHDR_SZ 20 708 #define OCE_MBX_RRHDR_SZ sizeof (struct mbx_hdr) 709 #define OCE_MBX_ADDL_STATUS(_MHDR) ((_MHDR)->u0.rsp.additional_status) 710 #define OCE_MBX_STATUS(_MHDR) ((_MHDR)->u0.rsp.status) 711 712 /* [05] OPCODE_QUERY_COMMON_LINK_STATUS */ 713 struct mbx_query_common_link_status { 714 struct mbx_hdr hdr; 715 union { 716 struct { 717 uint32_t rsvd0; 718 }req; 719 720 struct { 721 /* dw 0 */ 722 uint8_t physical_port; 723 uint8_t mac_duplex; 724 uint8_t mac_speed; 725 uint8_t mac_fault; 726 /* dw 1 */ 727 uint8_t mgmt_mac_duplex; 728 uint8_t mgmt_mac_speed; 729 uint16_t qos_link_speed; 730 uint32_t logical_link_status; 731 }rsp; 732 }params; 733 }; 734 735 /* [57] OPCODE_SET_COMMON_LINK_SPEED */ 736 struct mbx_set_common_link_speed { 737 struct mbx_hdr hdr; 738 union { 739 struct { 740 #ifdef _BIG_ENDIAN 741 uint8_t rsvd0; 742 uint8_t mac_speed; 743 uint8_t virtual_port; 744 uint8_t physical_port; 745 #else 746 uint8_t physical_port; 747 uint8_t virtual_port; 748 uint8_t mac_speed; 749 uint8_t rsvd0; 750 #endif 751 }req; 752 753 struct { 754 uint32_t rsvd0; 755 }rsp; 756 757 uint32_t dw; 758 }params; 759 }; 760 761 struct mac_address_format { 762 uint16_t size_of_struct; 763 uint8_t mac_addr[6]; 764 }; 765 766 /* [01] OPCODE_QUERY_COMMON_IFACE_MAC */ 767 struct mbx_query_common_iface_mac { 768 struct mbx_hdr hdr; 769 union { 770 struct { 771 #ifdef _BIG_ENDIAN 772 uint16_t if_id; 773 uint8_t permanent; 774 uint8_t type; 775 #else 776 uint8_t type; 777 uint8_t permanent; 778 uint16_t if_id; 779 #endif 780 781 }req; 782 783 struct { 784 struct mac_address_format mac; 785 }rsp; 786 }params; 787 }; 788 789 /* [02] OPCODE_SET_COMMON_IFACE_MAC */ 790 struct mbx_set_common_iface_mac { 791 struct mbx_hdr hdr; 792 union { 793 struct { 794 #ifdef _BIG_ENDIAN 795 /* dw 0 */ 796 uint16_t if_id; 797 uint8_t invalidate; 798 uint8_t type; 799 #else 800 /* dw 0 */ 801 uint8_t type; 802 uint8_t invalidate; 803 uint16_t if_id; 804 #endif 805 /* dw 1 */ 806 struct mac_address_format mac; 807 }req; 808 809 struct { 810 uint32_t rsvd0; 811 }rsp; 812 813 uint32_t dw[2]; 814 }params; 815 }; 816 817 /* [03] OPCODE_SET_COMMON_IFACE_MULTICAST */ 818 struct mbx_set_common_iface_multicast { 819 struct mbx_hdr hdr; 820 union { 821 struct { 822 /* dw 0 */ 823 uint16_t num_mac; 824 uint8_t promiscuous; 825 uint8_t if_id; 826 /* dw 1-48 */ 827 struct { 828 uint8_t byte[6]; 829 } mac[32]; 830 831 }req; 832 833 struct { 834 uint32_t rsvd0; 835 }rsp; 836 837 uint32_t dw[49]; 838 }params; 839 }; 840 841 struct qinq_vlan { 842 #ifdef _BIG_ENDIAN 843 uint16_t inner; 844 uint16_t outer; 845 #else 846 uint16_t outer; 847 uint16_t inner; 848 #endif 849 }; 850 851 struct normal_vlan { 852 uint16_t vtag; 853 }; 854 855 struct ntwk_if_vlan_tag { 856 union { 857 struct normal_vlan normal; 858 struct qinq_vlan qinq; 859 }u0; 860 }; 861 862 /* [50] OPCODE_CREATE_COMMON_IFACE */ 863 struct mbx_create_common_iface { 864 struct mbx_hdr hdr; 865 union { 866 struct { 867 uint32_t version; 868 uint32_t cap_flags; 869 uint32_t enable_flags; 870 uint8_t mac_addr[6]; 871 uint8_t rsvd0; 872 uint8_t mac_invalid; 873 struct ntwk_if_vlan_tag vlan_tag; 874 }req; 875 876 struct { 877 uint32_t if_id; 878 uint32_t pmac_id; 879 }rsp; 880 uint32_t dw[4]; 881 }params; 882 }; 883 884 /* [51] OPCODE_DESTROY_COMMON_IFACE */ 885 struct mbx_destroy_common_iface { 886 struct mbx_hdr hdr; 887 union { 888 struct { 889 uint32_t if_id; 890 }req; 891 892 struct { 893 uint32_t rsvd0; 894 }rsp; 895 896 uint32_t dw; 897 }params; 898 }; 899 900 /* event queue context structure */ 901 struct oce_eq_ctx { 902 #ifdef _BIG_ENDIAN 903 /* dw0 */ 904 uint32_t size:1; 905 uint32_t rsvd1:1; 906 uint32_t valid:1; 907 uint32_t epidx:13; 908 uint32_t rsvd0:3; 909 uint32_t cidx:13; 910 911 /* dw1 */ 912 uint32_t armed:1; 913 uint32_t stalled:1; 914 uint32_t sol_event:1; 915 uint32_t count:3; 916 uint32_t pd:10; 917 uint32_t rsvd2:3; 918 uint32_t pidx:13; 919 920 /* dw2 */ 921 uint32_t rsvd6:4; 922 uint32_t nodelay:1; 923 uint32_t phase:2; 924 uint32_t rsvd5:2; 925 uint32_t delay_mult:10; 926 uint32_t rsvd4:1; 927 uint32_t function:8; 928 uint32_t rsvd3:4; 929 930 /* dw 3 */ 931 uint32_t rsvd7; 932 #else 933 /* dw0 */ 934 uint32_t cidx:13; 935 uint32_t rsvd0:3; 936 uint32_t epidx:13; 937 uint32_t valid:1; 938 uint32_t rsvd1:1; 939 uint32_t size:1; 940 941 /* dw1 */ 942 uint32_t pidx:13; 943 uint32_t rsvd2:3; 944 uint32_t pd:10; 945 uint32_t count:3; 946 uint32_t sol_event:1; 947 uint32_t stalled:1; 948 uint32_t armed:1; 949 950 /* dw2 */ 951 uint32_t rsvd3:4; 952 uint32_t function:8; 953 uint32_t rsvd4:1; 954 uint32_t delay_mult:10; 955 uint32_t rsvd5:2; 956 uint32_t phase:2; 957 uint32_t nodelay:1; 958 uint32_t rsvd6:4; 959 960 /* dw3 */ 961 uint32_t rsvd7; 962 #endif 963 }; 964 965 /* [13] OPCODE_CREATE_COMMON_EQ */ 966 struct mbx_create_common_eq { 967 struct mbx_hdr hdr; 968 union { 969 struct { 970 #ifdef _BIG_ENDIAN 971 uint16_t rsvd0; 972 uint16_t num_pages; 973 #else 974 uint16_t num_pages; 975 uint16_t rsvd0; 976 #endif 977 struct oce_eq_ctx eq_ctx; 978 struct phys_addr pages[8]; 979 }req; 980 981 struct { 982 uint16_t eq_id; 983 uint16_t rsvd0; 984 }rsp; 985 }params; 986 }; 987 988 /* [55] OPCODE_DESTROY_COMMON_EQ */ 989 struct mbx_destroy_common_eq { 990 struct mbx_hdr hdr; 991 union { 992 struct { 993 #ifdef _BIG_ENDIAN 994 uint16_t rsvd0; 995 uint16_t id; 996 #else 997 uint16_t id; 998 uint16_t rsvd0; 999 #endif 1000 }req; 1001 1002 struct { 1003 uint32_t rsvd0; 1004 }rsp; 1005 }params; 1006 }; 1007 1008 struct oce_cq_ctx { 1009 #ifdef _BIG_ENDIAN 1010 /* dw0 */ 1011 uint32_t eventable:1; 1012 uint32_t sol_event:1; 1013 uint32_t valid:1; 1014 uint32_t count:2; 1015 uint32_t rsvd1:1; 1016 uint32_t epidx:11; 1017 uint32_t nodelay:1; 1018 uint32_t coalesce_wm:2; 1019 uint32_t rsvd0:1; 1020 uint32_t cidx:11; 1021 1022 /* dw1 */ 1023 uint32_t armed:1; 1024 uint32_t stalled:1; 1025 uint32_t eq_id:8; 1026 uint32_t pd:10; 1027 uint32_t rsvd2:1; 1028 uint32_t pidx:11; 1029 1030 /* dw2 */ 1031 uint32_t rsvd4:20; 1032 uint32_t function:8; 1033 uint32_t rsvd3:4; 1034 #else 1035 /* dw0 */ 1036 uint32_t cidx:11; 1037 uint32_t rsvd0:1; 1038 uint32_t coalesce_wm:2; 1039 uint32_t nodelay:1; 1040 uint32_t epidx:11; 1041 uint32_t rsvd1:1; 1042 uint32_t count:2; 1043 uint32_t valid:1; 1044 uint32_t sol_event:1; 1045 uint32_t eventable:1; 1046 1047 /* dw1 */ 1048 uint32_t pidx:11; 1049 uint32_t rsvd2:1; 1050 uint32_t pd:10; 1051 uint32_t eq_id:8; 1052 uint32_t stalled:1; 1053 uint32_t armed:1; 1054 1055 /* dw2 */ 1056 uint32_t rsvd3:4; 1057 uint32_t function:8; 1058 uint32_t rsvd4:20; 1059 #endif 1060 uint32_t rsvd5; 1061 }; 1062 1063 /* [12] OPCODE_CREATE_COMMON_CQ */ 1064 struct mbx_create_common_cq { 1065 struct mbx_hdr hdr; 1066 union { 1067 struct { 1068 #ifdef _BIG_ENDIAN 1069 uint16_t rsvd0; 1070 uint16_t num_pages; 1071 #else 1072 uint16_t num_pages; 1073 uint16_t rsvd0; 1074 #endif 1075 struct oce_cq_ctx cq_ctx; 1076 struct phys_addr pages[4]; 1077 }req; 1078 1079 struct { 1080 uint16_t cq_id; 1081 uint16_t rsvd0; 1082 }rsp; 1083 }params; 1084 }; 1085 1086 /* [54] OPCODE_DESTROY_COMMON_CQ */ 1087 struct mbx_destroy_common_cq { 1088 struct mbx_hdr hdr; 1089 union { 1090 struct { 1091 #ifdef _BIG_ENDIAN 1092 uint16_t rsvd0; 1093 uint16_t id; 1094 #else 1095 uint16_t id; 1096 uint16_t rsvd0; 1097 #endif 1098 }req; 1099 1100 struct { 1101 uint32_t rsvd0; 1102 }rsp; 1103 }params; 1104 }; 1105 1106 struct mq_ring_ctx { 1107 union { 1108 struct { 1109 #ifdef _BIG_ENDIAN 1110 /* dw 0 */ 1111 uint32_t cq_id:10; 1112 uint32_t fetch_r2t:1; 1113 uint32_t fetch_wrb:1; 1114 uint32_t ring_size:4; 1115 uint32_t rsvd0:2; 1116 uint32_t con_index:14; 1117 1118 /* dw1 */ 1119 uint32_t valid:1; 1120 uint32_t pdid:9; 1121 uint32_t fid:8; 1122 uint32_t prod_index:14; 1123 1124 /* dw 2 */ 1125 uint32_t rsvd1:21; 1126 uint32_t async_cq_id:10; 1127 uint32_t async_cq_valid:1; 1128 #else 1129 /* dw 0 */ 1130 uint32_t con_index:14; 1131 uint32_t rsvd0:2; 1132 uint32_t ring_size:4; 1133 uint32_t fetch_wrb:1; 1134 uint32_t fetch_r2t:1; 1135 uint32_t cq_id:10; 1136 1137 /* dw1 */ 1138 uint32_t prod_index:14; 1139 uint32_t fid:8; 1140 uint32_t pdid:9; 1141 uint32_t valid:1; 1142 1143 /* dw 2 */ 1144 uint32_t async_cq_valid:1; 1145 uint32_t async_cq_id:10; 1146 uint32_t rsvd1:21; 1147 #endif 1148 /* dw3 */ 1149 uint32_t rsvd3; 1150 }s; 1151 uint32_t dw[4]; 1152 }u0; 1153 }; 1154 1155 /* [21] OPCODE_CREATE_COMMON_MQ */ 1156 struct mbx_create_common_mq { 1157 struct mbx_hdr hdr; 1158 union { 1159 struct { 1160 #ifdef _BIG_ENDIAN 1161 uint16_t rsvd0; 1162 uint16_t num_pages; 1163 #else 1164 uint16_t num_pages; 1165 uint16_t rsvd0; 1166 #endif 1167 struct mq_ring_ctx context; 1168 struct phys_addr pages[8]; 1169 }req; 1170 1171 struct { 1172 uint32_t mq_id:16; 1173 uint32_t rsvd0:16; 1174 }rsp; 1175 }params; 1176 }; 1177 1178 /* [53] OPCODE_DESTROY_COMMON_MQ */ 1179 struct mbx_destroy_common_mq { 1180 struct mbx_hdr hdr; 1181 union { 1182 struct { 1183 #ifdef _BIG_ENDIAN 1184 uint16_t rsvd0; 1185 uint16_t id; 1186 #else 1187 uint16_t id; 1188 uint16_t rsvd0; 1189 #endif 1190 }req; 1191 1192 struct { 1193 uint32_t rsvd0; 1194 }rsp; 1195 }params; 1196 }; 1197 1198 /* [35] OPCODE_GET_COMMON_ FW_VERSION */ 1199 struct mbx_get_common_fw_version { 1200 struct mbx_hdr hdr; 1201 union { 1202 struct { 1203 uint32_t rsvd0; 1204 }req; 1205 1206 struct { 1207 uint8_t fw_ver_str[32]; 1208 uint8_t fw_on_flash_ver_str[32]; 1209 }rsp; 1210 }params; 1211 }; 1212 1213 /* [52] OPCODE_COMMON_CEV_MODIFY_MSI_MESSAGES */ 1214 struct mbx_common_cev_modify_msi_messages { 1215 struct mbx_hdr hdr; 1216 union { 1217 struct { 1218 uint32_t num_msi_msgs; 1219 }req; 1220 1221 struct { 1222 uint32_t rsvd0; 1223 }rsp; 1224 }params; 1225 }; 1226 1227 /* [36] OPCODE_SET_COMMON_FLOW_CONTROL */ 1228 /* [37] OPCODE_GET_COMMON_FLOW_CONTROL */ 1229 struct mbx_common_get_set_flow_control { 1230 struct mbx_hdr hdr; 1231 #ifdef _BIG_ENDIAN 1232 uint16_t tx_flow_control; 1233 uint16_t rx_flow_control; 1234 #else 1235 uint16_t rx_flow_control; 1236 uint16_t tx_flow_control; 1237 #endif 1238 }; 1239 1240 enum e_flash_opcode { 1241 MGMT_FLASHROM_OPCODE_FLASH = 1, 1242 MGMT_FLASHROM_OPCODE_SAVE = 2 1243 }; 1244 1245 /* [06] OPCODE_READ_COMMON_FLASHROM */ 1246 /* [07] OPCODE_WRITE_COMMON_FLASHROM */ 1247 1248 struct mbx_common_read_write_flashrom { 1249 struct mbx_hdr hdr; 1250 uint32_t flash_op_code; 1251 uint32_t flash_op_type; 1252 uint32_t data_buffer_size; 1253 uint32_t data_offset; 1254 uint8_t data_buffer[4]; /* + IMAGE_TRANSFER_SIZE */ 1255 }; 1256 1257 /* ULP MODE SUPPORTED */ 1258 enum { 1259 ULP_TOE_MODE = 0x1, 1260 ULP_NIC_MODE = 0x2, 1261 ULP_RDMA_MODE = 0x4, 1262 ULP_ISCSI_INI_MODE = 0x10, 1263 ULP_ISCSI_TGT_MODE = 0x20, 1264 ULP_FCOE_INI_MODE = 0x40, 1265 ULP_FCOE_TGT_MODE = 0x80, 1266 ULP_DAL_MODE = 0x100, 1267 ULP_LRO_MODE = 0x200 1268 }; 1269 1270 /* Function Mode Supported */ 1271 enum { 1272 TOE_MODE = 0x1, /* TCP offload */ 1273 NIC_MODE = 0x2, /* Raw Ethernet */ 1274 RDMA_MODE = 0x4, /* RDMA */ 1275 VM_MODE = 0x8, /* VM */ 1276 ISCSI_INI_MODE = 0x10, /* iSCSI initiator */ 1277 ISCSI_TGT_MODE = 0x20, /* iSCSI target plus initiator */ 1278 FCOE_INI_MODE = 0x40, /* FCoE Initiator */ 1279 FCOE_TGT_MODE = 0x80, /* FCoE target */ 1280 DAL_MODE = 0x100, /* DAL */ 1281 LRO_MODE = 0x200, /* LRO */ 1282 FLEX10_MODE = 0x400, /* FLEX-10 or VNIC */ 1283 NCSI_MODE = 0x800, /* NCSI */ 1284 INVALID_MODE = 0x8000 /* Invalid */ 1285 }; 1286 1287 struct mbx_common_query_fw_config { 1288 struct mbx_hdr hdr; 1289 union { 1290 struct { 1291 uint32_t rsvd0[30]; 1292 }req; 1293 1294 struct { 1295 uint32_t config_number; 1296 uint32_t asic_revision; 1297 uint32_t port_id; /* used for stats retrieval */ 1298 uint32_t function_mode; 1299 struct { 1300 1301 uint32_t mode; 1302 uint32_t wq_base; 1303 uint32_t wq_count; 1304 uint32_t sq_base; 1305 uint32_t sq_count; 1306 uint32_t rq_base; 1307 uint32_t rq_count; 1308 uint32_t dq_base; 1309 uint32_t dq_count; 1310 uint32_t lro_base; 1311 uint32_t lro_count; 1312 uint32_t icd_base; 1313 uint32_t icd_count; 1314 } ulp[2]; 1315 uint32_t function_caps; 1316 }rsp; 1317 }params; 1318 }; 1319 1320 struct mbx_common_config_vlan { 1321 struct mbx_hdr hdr; 1322 union { 1323 struct { 1324 #ifdef _BIG_ENDIAN 1325 uint8_t num_vlans; 1326 uint8_t untagged; 1327 uint8_t promisc; 1328 uint8_t if_id; 1329 #else 1330 uint8_t if_id; 1331 uint8_t promisc; 1332 uint8_t untagged; 1333 uint8_t num_vlans; 1334 #endif 1335 union { 1336 struct normal_vlan normal_vlans[64]; 1337 struct qinq_vlan qinq_vlans[32]; 1338 }tags; 1339 }req; 1340 1341 struct { 1342 uint32_t rsvd; 1343 }rsp; 1344 }params; 1345 }; 1346 1347 /* [34] OPCODE_COMMON_NTWK_RX_FILTER */ 1348 struct mbx_set_common_ntwk_rx_filter { 1349 struct mbx_hdr hdr; 1350 uint32_t global_flags_mask; 1351 uint32_t global_flags; 1352 uint32_t iface_flags_mask; 1353 uint32_t iface_flags; 1354 uint32_t if_id; 1355 uint32_t num_mcast; 1356 struct { 1357 uint8_t byte[6]; 1358 }mac[32]; 1359 }; 1360 /* [41] OPCODE_MODIFY_COMMON_EQ_DELAY */ 1361 struct mbx_modify_common_eq_delay { 1362 struct mbx_hdr hdr; 1363 union { 1364 struct { 1365 uint32_t num_eq; 1366 struct { 1367 uint32_t eq_id; 1368 uint32_t phase; 1369 uint32_t dm; 1370 }delay[8]; 1371 }req; 1372 1373 struct { 1374 uint32_t rsvd0; 1375 }rsp; 1376 }params; 1377 }; 1378 /* [59] OPCODE_ADD_COMMON_IFACE_MAC */ 1379 struct mbx_add_common_iface_mac { 1380 struct mbx_hdr hdr; 1381 union { 1382 struct { 1383 uint32_t if_id; 1384 uint8_t mac_address[6]; 1385 uint8_t rsvd0[2]; 1386 }req; 1387 struct { 1388 uint32_t pmac_id; 1389 }rsp; 1390 } params; 1391 }; 1392 1393 /* [60] OPCODE_DEL_COMMON_IFACE_MAC */ 1394 struct mbx_del_common_iface_mac { 1395 struct mbx_hdr hdr; 1396 union { 1397 struct { 1398 uint32_t if_id; 1399 uint32_t pmac_id; 1400 }req; 1401 struct { 1402 uint32_t rsvd0; 1403 }rsp; 1404 } params; 1405 }; 1406 1407 /* [8] OPCODE_QUERY_COMMON_MAX_MBX_BUFFER_SIZE */ 1408 struct mbx_query_common_max_mbx_buffer_size { 1409 struct mbx_hdr hdr; 1410 struct { 1411 uint32_t max_ioctl_bufsz; 1412 } rsp; 1413 }; 1414 1415 /* [61] OPCODE_COMMON_FUNCTION_RESET */ 1416 struct ioctl_common_function_reset { 1417 struct mbx_hdr hdr; 1418 }; 1419 1420 /* [80] OPCODE_COMMON_FUNCTION_LINK_CONFIG */ 1421 struct mbx_common_func_link_cfg { 1422 struct mbx_hdr hdr; 1423 union { 1424 struct { 1425 uint32_t enable; 1426 }req; 1427 struct { 1428 uint32_t rsvd0; 1429 }rsp; 1430 } params; 1431 }; 1432 1433 #pragma pack() 1434 1435 #ifdef __cplusplus 1436 } 1437 #endif 1438 1439 #endif /* _OCE_HW_H_ */ 1440