1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2009 Emulex.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 /*
28  * Header file containing the command structures for Hardware
29  */
30 
31 #ifndef _OCE_HW_H_
32 #define	_OCE_HW_H_
33 
34 #ifdef __cplusplus
35 extern "C" {
36 #endif
37 
38 #include <sys/types.h>
39 
40 #pragma pack(1)
41 
42 /* PCI CSR offsets */
43 #define	PCICFG_F1_CSR		0x0 /* F1 for NIC */
44 #define	PCICFG_SEMAPHORE	0xbc
45 #define	PCICFG_SOFT_RESET	0x5c
46 #define	PCICFG_UE_STATUS_HI_MASK	0xac
47 #define	PCICFG_UE_STATUS_LO_MASK	0xa8
48 #define	PCICFG_ONLINE0		0xb0
49 #define	PCICFG_ONLINE1		0xb4
50 #define	INTR_EN				0x20000000
51 #define	IMAGE_TRANSFER_SIZE	(32 * 1024) /* 32K at a time */
52 
53 /* CSR register offsets */
54 #define	MPU_EP_CONTROL		0
55 #define	MPU_EP_SEMAPHORE	0xac
56 #define	PCICFG_INTR_CTRL	0xfc
57 #define	HOSTINTR_MASK		(1 << 29)
58 #define	HOSTINTR_PFUNC_SHIFT	26
59 #define	HOSTINTR_PFUNC_MASK	7
60 
61 /* POST status reg struct */
62 #define	POST_STAGE_POWER_ON_RESET	0x00
63 #define	POST_STAGE_AWAITING_HOST_RDY	0x01
64 #define	POST_STAGE_HOST_RDY		0x02
65 #define	POST_STAGE_CHIP_RESET		0x03
66 #define	POST_STAGE_ARMFW_READY		0xc000
67 #define	POST_STAGE_ARMFW_UE		0xf000
68 
69 /* DOORBELL registers */
70 #define	PD_RXULP_DB	0x0100
71 #define	PD_TXULP_DB	0x0060
72 #define	DB_RQ_ID_MASK	0x3FF
73 
74 #define	PD_CQ_DB	0x0120
75 #define	PD_EQ_DB	PD_CQ_DB
76 #define	PD_MPU_MBOX_DB	0x0160
77 #define	PD_MQ_DB	0x0140
78 
79 /* EQE completion types */
80 #define	EQ_MINOR_CODE_COMPLETION 	0x00
81 #define	EQ_MINOR_CODE_OTHER			0x01
82 #define	EQ_MAJOR_CODE_COMPLETION 	0x00
83 
84 /* Link Status field values */
85 #define	PHY_LINK_FAULT_NONE			0x0
86 #define	PHY_LINK_FAULT_LOCAL		0x01
87 #define	PHY_LINK_FAULT_REMOTE		0x02
88 
89 #define	PHY_LINK_SPEED_ZERO			0x0 /* No link */
90 #define	PHY_LINK_SPEED_10MBPS		0x1 /* (10 Mbps) */
91 #define	PHY_LINK_SPEED_100MBPS		0x2 /* (100 Mbps) */
92 #define	PHY_LINK_SPEED_1GBPS		0x3 /* (1 Gbps) */
93 #define	PHY_LINK_SPEED_10GBPS		0x4 /* (10 Gbps) */
94 
95 #define	PHY_LINK_DUPLEX_NONE		0x0
96 #define	PHY_LINK_DUPLEX_HALF		0x1
97 #define	PHY_LINK_DUPLEX_FULL		0x2
98 
99 #define	NTWK_PORT_A			0x0 /* (Port A) */
100 #define	NTWK_PORT_B			0x1 /* (Port B) */
101 
102 #define	PHY_LINK_SPEED_ZERO			0x0 /* (No link.) */
103 #define	PHY_LINK_SPEED_10MBPS		0x1 /* (10 Mbps) */
104 #define	PHY_LINK_SPEED_100MBPS		0x2 /* (100 Mbps) */
105 #define	PHY_LINK_SPEED_1GBPS		0x3 /* (1 Gbps) */
106 #define	PHY_LINK_SPEED_10GBPS		0x4 /* (10 Gbps) */
107 
108 /* Hardware Address types */
109 #define	MAC_ADDRESS_TYPE_STORAGE	0x0 /* (Storage MAC Address) */
110 #define	MAC_ADDRESS_TYPE_NETWORK	0x1 /* (Network MAC Address) */
111 #define	MAC_ADDRESS_TYPE_PD		0x2 /* (Protection Domain MAC Addr) */
112 #define	MAC_ADDRESS_TYPE_MANAGEMENT	0x3 /* (Management MAC Address) */
113 #define	MAC_ADDRESS_TYPE_FCOE		0x4 /* (FCoE MAC Address) */
114 
115 /* CREATE_IFACE capability and cap_en flags */
116 #define	MBX_RX_IFACE_FLAGS_RSS				0x4
117 #define	MBX_RX_IFACE_FLAGS_PROMISCUOUS		0x8
118 #define	MBX_RX_IFACE_FLAGS_BROADCAST 		0x10
119 #define	MBX_RX_IFACE_FLAGS_UNTAGGED			0x20
120 #define	MBX_RX_IFACE_FLAGS_ULP				0x40
121 #define	MBX_RX_IFACE_FLAGS_VLAN_PROMISCUOUS 0x80
122 #define	MBX_RX_IFACE_FLAGS_VLAN				0x100
123 #define	MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS	0x200
124 #define	MBX_RX_IFACE_FLAGS_PASS_L2				0x400
125 #define	MBX_RX_IFACE_FLAGS_PASS_L3L4			0x800
126 
127 #define	MQ_RING_CONTEXT_SIZE_16		0x5 /* (16 entries) */
128 #define	MQ_RING_CONTEXT_SIZE_32		0x6 /* (32 entries) */
129 #define	MQ_RING_CONTEXT_SIZE_64		0x7 /* (64 entries) */
130 #define	MQ_RING_CONTEXT_SIZE_128	0x8 /* (128 entries) */
131 
132 
133 #define	MBX_DB_READY_BIT	0x1
134 #define	MBX_DB_HI_BIT		0x2
135 #define	ASYNC_EVENT_CODE_LINK_STATE	0x1
136 #define	ASYNC_EVENT_LINK_UP			0x1
137 #define	ASYNC_EVENT_LINK_DOWN		0x0
138 
139 /* Rx filter bits */
140 #define	NTWK_RX_FILTER_IP_CKSUM 	0x1
141 #define	NTWK_RX_FILTER_TCP_CKSUM	0x2
142 #define	NTWK_RX_FILTER_UDP_CKSUM	0x4
143 #define	NTWK_RX_FILTER_STRIP_CRC	0x8
144 
145 /* max SGE per mbx */
146 #define	MAX_MBX_SGE	19
147 
148 /* physical address structure to be used in MBX */
149 struct phys_addr {
150 	/* dw0 */
151 	uint32_t lo;
152 	/* dw1 */
153 	uint32_t hi;
154 };
155 
156 typedef union pcicfg_intr_ctl_u {
157 	uint32_t dw0;
158 	struct {
159 #ifdef _BIG_ENDIAN
160 		uint32_t winselect:2;
161 		uint32_t hostintr:1;
162 		uint32_t pfnum:3;
163 		uint32_t vf_cev_int_line_en:1;
164 		uint32_t winaddr:23;
165 		uint32_t membarwinen:1;
166 #else
167 		uint32_t membarwinen:1;
168 		uint32_t winaddr:23;
169 		uint32_t vf_cev_int_line_en:1;
170 		uint32_t pfnum:3;
171 		uint32_t hostintr:1;
172 		uint32_t winselect:2;
173 #endif
174 	} bits;
175 }pcicfg_intr_ctl_t;
176 
177 typedef union  pcicfg_semaphore_u {
178 	uint32_t dw0;
179 	struct {
180 #ifdef _BIG_ENDIAN
181 		uint32_t rsvd:31;
182 		uint32_t lock:1;
183 #else
184 		uint32_t lock:1;
185 		uint32_t rsvd:31;
186 #endif
187 	}bits;
188 }pcicfg_semaphore_t;
189 
190 typedef union pcicfg_soft_reset_u {
191 	uint32_t dw0;
192 	struct {
193 #ifdef _BIG_ENDIAN
194 		uint32_t nec_ll_rcvdetect:8;
195 		uint32_t dbg_all_reqs_62_49:14;
196 		uint32_t scratchpad0:1;
197 		uint32_t exception_oe:1;
198 		uint32_t soft_reset:1;
199 		uint32_t rsvd0:7;
200 #else
201 		uint32_t rsvd0:7;
202 		uint32_t soft_reset:1;
203 		uint32_t exception_oe:1;
204 		uint32_t scratchpad0:1;
205 		uint32_t dbg_all_reqs_62_49:14;
206 		uint32_t nec_ll_rcvdetect:8;
207 #endif
208 	}bits;
209 }pcicfg_soft_reset_t;
210 
211 typedef union pcicfg_online1_u {
212 	uint32_t dw0;
213 	struct {
214 #ifdef _BIG_ENDIAN
215 		uint32_t host8_online:1;
216 		uint32_t host7_online:1;
217 		uint32_t host6_online:1;
218 		uint32_t host5_online:1;
219 		uint32_t host4_online:1;
220 		uint32_t host3_online:1;
221 		uint32_t host2_online:1;
222 		uint32_t ipc_online:1;
223 		uint32_t arm_online:1;
224 		uint32_t txp_online:1;
225 		uint32_t xaui_online:1;
226 		uint32_t rxpp_online:1;
227 		uint32_t txpb_online:1;
228 		uint32_t rr_online:1;
229 		uint32_t pmem_online:1;
230 		uint32_t pctl1_online:1;
231 		uint32_t pctl0_online:1;
232 		uint32_t pcs1online_online:1;
233 		uint32_t mpu_iram_online:1;
234 		uint32_t pcs0online_online:1;
235 		uint32_t mgmt_mac_online:1;
236 		uint32_t lpcmemhost_online:1;
237 #else
238 		uint32_t lpcmemhost_online:1;
239 		uint32_t mgmt_mac_online:1;
240 		uint32_t pcs0online_online:1;
241 		uint32_t mpu_iram_online:1;
242 		uint32_t pcs1online_online:1;
243 		uint32_t pctl0_online:1;
244 		uint32_t pctl1_online:1;
245 		uint32_t pmem_online:1;
246 		uint32_t rr_online:1;
247 		uint32_t txpb_online:1;
248 		uint32_t rxpp_online:1;
249 		uint32_t xaui_online:1;
250 		uint32_t txp_online:1;
251 		uint32_t arm_online:1;
252 		uint32_t ipc_online:1;
253 		uint32_t host2_online:1;
254 		uint32_t host3_online:1;
255 		uint32_t host4_online:1;
256 		uint32_t host5_online:1;
257 		uint32_t host6_online:1;
258 		uint32_t host7_online:1;
259 		uint32_t host8_online:1;
260 #endif
261 	}bits;
262 }pcicfg_online1_t;
263 
264 typedef union mpu_ep_semaphore_u {
265 	uint32_t dw0;
266 	struct {
267 #ifdef _BIG_ENDIAN
268 		uint32_t error:1;
269 		uint32_t backup_fw:1;
270 		uint32_t iscsi_no_ip:1;
271 		uint32_t iscsi_ip_conflict:1;
272 		uint32_t option_rom_installed:1;
273 		uint32_t iscsi_drv_loaded:1;
274 		uint32_t rsvd0:10;
275 		uint32_t stage:16;
276 #else
277 		uint32_t stage:16;
278 		uint32_t rsvd0:10;
279 		uint32_t iscsi_drv_loaded:1;
280 		uint32_t option_rom_installed:1;
281 		uint32_t iscsi_ip_conflict:1;
282 		uint32_t iscsi_no_ip:1;
283 		uint32_t backup_fw:1;
284 		uint32_t error:1;
285 #endif
286 	}bits;
287 }mpu_ep_semaphore_t;
288 
289 typedef union mpu_ep_control_u {
290 	uint32_t dw0;
291 	struct {
292 #ifdef _BIG_ENDIAN
293 		uint32_t cpu_reset:1;
294 		uint32_t rsvd1:15;
295 		uint32_t ep_ram_init_status:1;
296 		uint32_t rsvd0:12;
297 		uint32_t m2_rxpbuf:1;
298 		uint32_t m1_rxpbuf:1;
299 		uint32_t m0_rxpbuf:1;
300 #else
301 		uint32_t m0_rxpbuf:1;
302 		uint32_t m1_rxpbuf:1;
303 		uint32_t m2_rxpbuf:1;
304 		uint32_t rsvd0:12;
305 		uint32_t ep_ram_init_status:1;
306 		uint32_t rsvd1:15;
307 		uint32_t cpu_reset:1;
308 #endif
309 	}bits;
310 }mpu_ep_control_t;
311 
312 /* RX doorbell */
313 typedef union pd_rxulp_db_u {
314 	uint32_t dw0;
315 	struct {
316 #ifdef _BIG_ENDIAN
317 		uint32_t num_posted:8;
318 		uint32_t invalidate:1;
319 		uint32_t rsvd1:13;
320 		uint32_t qid:10;
321 #else
322 		uint32_t qid:10;
323 		uint32_t rsvd1:13;
324 		uint32_t invalidate:1;
325 		uint32_t num_posted:8;
326 #endif
327 	}bits;
328 }pd_rxulp_db_t;
329 
330 /* TX doorbell */
331 typedef union pd_txulp_db_u {
332 	uint32_t dw0;
333 	struct {
334 #ifdef _BIG_ENDIAN
335 		uint32_t rsvd1:2;
336 		uint32_t num_posted:14;
337 		uint32_t rsvd0:6;
338 		uint32_t qid:10;
339 #else
340 		uint32_t qid:10;
341 		uint32_t rsvd0:6;
342 		uint32_t num_posted:14;
343 		uint32_t rsvd1:2;
344 #endif
345 	}bits;
346 }pd_txulp_db_t;
347 
348 /* CQ doorbell */
349 typedef union cq_db_u {
350 	uint32_t dw0;
351 	struct {
352 #ifdef _BIG_ENDIAN
353 		uint32_t rsvd1:2;
354 		uint32_t rearm:1;
355 		uint32_t num_popped:13;
356 		uint32_t rsvd0:5;
357 		uint32_t event:1;
358 		uint32_t qid:10;
359 #else
360 		uint32_t qid:10;
361 		uint32_t event:1;
362 		uint32_t rsvd0:5;
363 		uint32_t num_popped:13;
364 		uint32_t rearm:1;
365 		uint32_t rsvd1:2;
366 #endif
367 	}bits;
368 }cq_db_t;
369 
370 /* EQ doorbell */
371 typedef union eq_db_u {
372 	uint32_t dw0;
373 	struct {
374 #ifdef _BIG_ENDIAN
375 		uint32_t rsvd1:2;
376 		uint32_t rearm:1;
377 		uint32_t num_popped:13;
378 		uint32_t rsvd0:5;
379 		uint32_t event:1;
380 		uint32_t clrint:1;
381 		uint32_t qid:9;
382 #else
383 		uint32_t qid:9;
384 		uint32_t clrint:1;
385 		uint32_t event:1;
386 		uint32_t rsvd0:5;
387 		uint32_t num_popped:13;
388 		uint32_t rearm:1;
389 		uint32_t rsvd1:2;
390 #endif
391 	}bits;
392 }eq_db_t;
393 
394 /* bootstrap mbox doorbell */
395 typedef union pd_mpu_mbox_db_u {
396 	uint32_t dw0;
397 	struct {
398 #ifdef _BIG_ENDIAN
399 		uint32_t address:30;
400 		uint32_t hi:1;
401 		uint32_t ready:1;
402 #else
403 		uint32_t ready:1;
404 		uint32_t hi:1;
405 		uint32_t address:30;
406 #endif
407 	}bits;
408 }pd_mpu_mbox_db_t;
409 
410 
411 /* MQ ring doorbell */
412 typedef union pd_mq_db_u {
413 	uint32_t dw0;
414 	struct {
415 #ifdef _BIG_ENDIAN
416 		uint32_t rsvd1:2;
417 		uint32_t num_posted:14;
418 		uint32_t rsvd0:5;
419 		uint32_t mq_id:11;
420 #else
421 		uint32_t mq_id:11;
422 		uint32_t rsvd0:5;
423 		uint32_t num_posted:14;
424 		uint32_t rsvd1:2;
425 #endif
426 	}bits;
427 }pd_mq_db_t;
428 
429 /*
430  * Event Queue Entry
431  */
432 struct oce_eqe {
433 	union {
434 		struct {
435 #ifdef _BIG_ENDIAN
436 			uint32_t resource_id:16;
437 			uint32_t minor_code:12;
438 			uint32_t major_code:3;
439 			uint32_t valid:1;
440 #else
441 			uint32_t valid:1;
442 			uint32_t major_code:3;
443 			uint32_t minor_code:12;
444 			uint32_t resource_id:16;
445 #endif
446 		}s;
447 		uint32_t dw0;
448 	}u0;
449 };
450 
451 /* MQ scatter gather entry. Array of these make an SGL */
452 struct oce_mq_sge {
453 	uint32_t pa_lo;
454 	uint32_t pa_hi;
455 	uint32_t length;
456 };
457 
458 /*
459  * payload can contain an SGL or an embedded array of upto 59 dwords
460  */
461 struct oce_mbx_payload {
462 	union {
463 		union {
464 			struct oce_mq_sge sgl[MAX_MBX_SGE];
465 			uint32_t embedded[59];
466 		}u1;
467 		uint32_t dw[59];
468 	}u0;
469 };
470 
471 /*
472  * MQ MBX structure
473  */
474 struct oce_mbx {
475 	union {
476 		struct {
477 #ifdef _BIG_ENDIAN
478 			uint32_t special : 8;
479 			uint32_t rsvd1 : 16;
480 			uint32_t sge_count : 5;
481 			uint32_t rsvd0 : 2;
482 			uint32_t embedded : 1;
483 #else
484 			uint32_t embedded:1;
485 			uint32_t rsvd0:2;
486 			uint32_t sge_count:5;
487 			uint32_t rsvd1:16;
488 			uint32_t special:8;
489 #endif
490 		}s;
491 		uint32_t dw0;
492 	}u0;
493 
494 	uint32_t payload_length;
495 	uint32_t tag[2];
496 	uint32_t rsvd2[1];
497 	struct oce_mbx_payload payload;
498 };
499 
500 /* completion queue entry for MQ */
501 struct oce_mq_cqe {
502 	union {
503 		struct {
504 #ifdef _BIG_ENDIAN
505 			/* dw0 */
506 			uint32_t extended_status:16;
507 			uint32_t completion_status:16;
508 			/* dw1 dw2 */
509 			uint32_t mq_tag[2];
510 			/* dw3 */
511 			uint32_t valid:1;
512 			uint32_t async_event:1;
513 			uint32_t hpi_buffer_cmpl:1;
514 			uint32_t completed:1;
515 			uint32_t consumed:1;
516 			uint32_t rsvd0:27;
517 #else
518 			/* dw0 */
519 			uint32_t completion_status:16;
520 			uint32_t extended_status:16;
521 			/* dw1 dw2 */
522 			uint32_t mq_tag[2];
523 			/* dw3 */
524 			uint32_t rsvd0:27;
525 			uint32_t consumed:1;
526 			uint32_t completed:1;
527 			uint32_t hpi_buffer_cmpl:1;
528 			uint32_t async_event:1;
529 			uint32_t valid:1;
530 #endif
531 		}s;
532 		uint32_t dw[4];
533 	}u0;
534 };
535 
536 struct oce_async_cqe_link_state {
537 	union {
538 		struct {
539 #ifdef _BIG_ENDIAN
540 			/* dw0 */
541 			uint8_t speed;
542 			uint8_t duplex;
543 			uint8_t link_status;
544 			uint8_t phy_port;
545 			/* dw1 */
546 			uint8_t rsvd0[3];
547 			uint8_t fault;
548 			/* dw2 */
549 			uint32_t event_tag;
550 			/* dw3 */
551 			uint32_t valid:1;
552 			uint32_t async_event:1;
553 			uint32_t rsvd2:6;
554 			uint32_t event_type:8;
555 			uint32_t event_code:8;
556 			uint32_t rsvd1:8;
557 #else
558 			/* dw0 */
559 			uint8_t phy_port;
560 			uint8_t link_status;
561 			uint8_t duplex;
562 			uint8_t speed;
563 			/* dw1 */
564 			uint8_t fault;
565 			uint8_t rsvd0[3];
566 			/* dw2 */
567 			uint32_t event_tag;
568 			/* dw3 */
569 			uint32_t rsvd1:8;
570 			uint32_t event_code:8;
571 			uint32_t event_type:8;
572 			uint32_t rsvd2:6;
573 			uint32_t async_event:1;
574 			uint32_t valid:1;
575 #endif
576 		}s;
577 		uint32_t dw[4];
578 	}u0;
579 };
580 
581 /* MQ mailbox structure */
582 struct oce_bmbx {
583 	struct oce_mbx mbx;
584 	struct oce_mq_cqe cqe;
585 };
586 
587 /* ---[ MBXs start here ]---------------------------------------------- */
588 /* MBXs sub system codes */
589 enum {
590 	MBX_SUBSYSTEM_RSVD = 0,
591 	MBX_SUBSYSTEM_COMMON = 1,
592 	MBX_SUBSYSTEM_COMMON_ISCSI = 2,
593 	MBX_SUBSYSTEM_NIC = 3,
594 	MBX_SUBSYSTEM_TOE = 4,
595 	MBX_SUBSYSTEM_PXE_UNDI = 5,
596 	MBX_SUBSYSTEM_ISCSI_INI	= 6,
597 	MBX_SUBSYSTEM_ISCSI_TGT	= 7,
598 	MBX_SUBSYSTEM_MILI_PTL = 8,
599 	MBX_SUBSYSTEM_MILI_TMD = 9,
600 	MBX_SUBSYSTEM_RDMA = 10,
601 	MBX_SUBSYSTEM_LOWLEVEL = 11,
602 	MBX_SUBSYSTEM_LRO = 13,
603 	IOCBMBX_SUBSYSTEM_DCBX = 15,
604 	IOCBMBX_SUBSYSTEM_DIAG = 16,
605 	IOCBMBX_SUBSYSTEM_VENDOR = 17
606 };
607 
608 /* common ioctl opcodes */
609 enum {
610 	OPCODE_QUERY_COMMON_IFACE_MAC = 1,
611 	OPCODE_SET_COMMON_IFACE_MAC = 2,
612 	OPCODE_SET_COMMON_IFACE_MULTICAST = 3,
613 	OPCODE_CONFIG_COMMON_IFACE_VLAN	= 4,
614 	OPCODE_QUERY_COMMON_LINK_STATUS = 5,
615 	OPCODE_READ_COMMON_FLASHROM = 6,
616 	OPCODE_WRITE_COMMON_FLASHROM = 7,
617 	OPCODE_QUERY_COMMON_MAX_MBX_BUFFER_SIZE = 8,
618 	OPCODE_ADD_COMMON_PAGE_TABLES = 9,
619 	OPCODE_REMOVE_COMMON_PAGE_TABLES = 10,
620 	OPCODE_CREATE_COMMON_CQ = 12,
621 	OPCODE_CREATE_COMMON_EQ = 13,
622 	OPCODE_CREATE_COMMON_MQ = 21,
623 	OPCODE_COMMON_JELL_CONFIG = 22,
624 	OPCODE_COMMON_ADD_TEMPLATE_HEADER_BUFFERS = 24,
625 	OPCODE_COMMON_REMOVE_TEMPLATE_HEADER_BUFFERS = 25,
626 	OPCODE_COMMON_POST_ZERO_BUFFER = 26,
627 	OPCODE_COMMON_GET_QOS = 27,
628 	OPCODE_COMMON_SET_QOS = 28,
629 	OPCODE_COMMON_TCP_GET_STATISTICS = 29,
630 	OPCODE_READ_COMMON_SEEPROM = 30,
631 	OPCODE_COMMON_TCP_STATE_QUERY = 31,
632 	OPCODE_GET_COMMON_CNTL_ATTRIBUTES = 32,
633 	OPCODE_COMMON_NOP = 33,
634 	OPCODE_COMMON_NTWK_RX_FILTER = 34,
635 	OPCODE_GET_COMMON_FW_VERSION = 35,
636 	OPCODE_SET_COMMON_FLOW_CONTROL = 36,
637 	OPCODE_GET_COMMON_FLOW_CONTROL = 37,
638 	OPCODE_COMMON_SET_TCP_PARAMETERS = 38,
639 	OPCODE_SET_COMMON_FRAME_SIZE = 39,
640 	OPCODE_COMMON_GET_FAT = 40,
641 	OPCODE_MODIFY_COMMON_EQ_DELAY = 41,
642 	OPCODE_COMMON_FIRMWARE_CONFIG = 42,
643 	OPCODE_COMMON_ENABLE_DISABLE_DOMAINS = 43,
644 	OPCODE_COMMON_GET_DOMAIN_CONFIG = 44,
645 	OPCODE_COMMON_GET_PORT_EQUALIZATION = 47,
646 	OPCODE_COMMON_SET_PORT_EQUALIZATION = 48,
647 	OPCODE_COMMON_RED_CONFIG = 49,
648 	OPCODE_CREATE_COMMON_IFACE = 50,
649 	OPCODE_DESTROY_COMMON_IFACE = 51,
650 	OPCODE_COMMON_CEV_MODIFY_MSI_MESSAGES = 52,
651 	OPCODE_DESTROY_COMMON_MQ = 53,
652 	OPCODE_DESTROY_COMMON_CQ = 54,
653 	OPCODE_DESTROY_COMMON_EQ = 55,
654 	OPCODE_COMMON_TCP_UPL_OAD = 56,
655 	OPCODE_SET_COMMON_LINK_SPEED = 57,
656 	OPCODE_QUERY_COMMON_FIRMWARE_CONFIG = 58,
657 	OPCODE_ADD_COMMON_IFACE_MAC = 59,
658 	OPCODE_DEL_COMMON_IFACE_MAC = 60,
659 	OPCODE_COMMON_FUNCTION_RESET = 61,
660 	OPCODE_COMMON_FUNCTION_LINK_CONFIG = 80
661 };
662 
663 /* common ioctl header */
664 struct mbx_hdr {
665 	union {
666 		struct {
667 #ifdef _BIG_ENDIAN
668 			uint8_t domain;
669 			uint8_t port_number;
670 			uint8_t subsystem;
671 			uint8_t opcode;
672 #else
673 			uint8_t opcode;
674 			uint8_t subsystem;
675 			uint8_t port_number;
676 			uint8_t domain;
677 #endif
678 			uint32_t timeout;
679 			uint32_t request_length;
680 			uint32_t rsvd0;
681 		}req;
682 
683 		struct {
684 			/* dw 0 */
685 			uint8_t opcode;
686 			uint8_t subsystem;
687 			uint8_t rsvd0;
688 			uint8_t domain;
689 			/* dw 1 */
690 			uint8_t status;
691 			uint8_t additional_status;
692 			uint16_t rsvd1;
693 
694 			uint32_t rsp_length;
695 			uint32_t actual_rsp_length;
696 		}rsp;
697 		uint32_t dw[4];
698 	}u0;
699 };
700 #define	OCE_BMBX_RHDR_SZ 20
701 #define	OCE_MBX_RRHDR_SZ sizeof (struct mbx_hdr)
702 #define	OCE_MBX_ADDL_STATUS(_MHDR) ((_MHDR)->u0.rsp.additional_status)
703 #define	OCE_MBX_STATUS(_MHDR) ((_MHDR)->u0.rsp.status)
704 
705 /* [05] OPCODE_QUERY_COMMON_LINK_STATUS */
706 struct mbx_query_common_link_status {
707 	struct mbx_hdr hdr;
708 	union {
709 		struct {
710 			uint32_t rsvd0;
711 		}req;
712 
713 		struct {
714 			/* dw 0 */
715 			uint8_t physical_port;
716 			uint8_t mac_duplex;
717 			uint8_t mac_speed;
718 			uint8_t mac_fault;
719 			/* dw 1 */
720 			uint8_t mgmt_mac_duplex;
721 			uint8_t mgmt_mac_speed;
722 			uint16_t qos_link_speed;
723 			uint32_t logical_link_status;
724 		}rsp;
725 	}params;
726 };
727 
728 /* [57] OPCODE_SET_COMMON_LINK_SPEED */
729 struct mbx_set_common_link_speed {
730 	struct mbx_hdr hdr;
731 	union {
732 		struct {
733 #ifdef _BIG_ENDIAN
734 			uint8_t rsvd0;
735 			uint8_t mac_speed;
736 			uint8_t virtual_port;
737 			uint8_t physical_port;
738 #else
739 			uint8_t physical_port;
740 			uint8_t virtual_port;
741 			uint8_t mac_speed;
742 			uint8_t rsvd0;
743 #endif
744 		}req;
745 
746 		struct {
747 			uint32_t rsvd0;
748 		}rsp;
749 
750 		uint32_t dw;
751 	}params;
752 };
753 
754 struct mac_address_format {
755 	uint16_t size_of_struct;
756 	uint8_t	mac_addr[6];
757 };
758 
759 /* [01] OPCODE_QUERY_COMMON_IFACE_MAC */
760 struct mbx_query_common_iface_mac {
761 	struct mbx_hdr hdr;
762 	union {
763 		struct {
764 #ifdef _BIG_ENDIAN
765 			uint16_t if_id;
766 			uint8_t	permanent;
767 			uint8_t type;
768 #else
769 			uint8_t type;
770 			uint8_t	permanent;
771 			uint16_t if_id;
772 #endif
773 
774 		}req;
775 
776 		struct {
777 			struct mac_address_format mac;
778 		}rsp;
779 	}params;
780 };
781 
782 /* [02] OPCODE_SET_COMMON_IFACE_MAC */
783 struct mbx_set_common_iface_mac {
784 	struct mbx_hdr hdr;
785 	union {
786 		struct {
787 #ifdef _BIG_ENDIAN
788 			/* dw 0 */
789 			uint16_t if_id;
790 			uint8_t invalidate;
791 			uint8_t type;
792 #else
793 			/* dw 0 */
794 			uint8_t type;
795 			uint8_t invalidate;
796 			uint16_t if_id;
797 #endif
798 			/* dw 1 */
799 			struct mac_address_format mac;
800 		}req;
801 
802 		struct {
803 			uint32_t rsvd0;
804 		}rsp;
805 
806 		uint32_t dw[2];
807 	}params;
808 };
809 
810 /* [03] OPCODE_SET_COMMON_IFACE_MULTICAST */
811 struct mbx_set_common_iface_multicast {
812 	struct mbx_hdr hdr;
813 	union {
814 		struct {
815 #ifdef _BIG_ENDIAN
816 			/* dw 0 */
817 			uint8_t if_id;
818 			uint8_t promiscuous;
819 			uint16_t num_mac;
820 #else
821 			/* dw 0 */
822 			uint16_t num_mac;
823 			uint8_t promiscuous;
824 			uint8_t if_id;
825 #endif
826 			/* dw 1-48 */
827 			struct {
828 				uint8_t byte[6];
829 			} mac[32];
830 
831 		}req;
832 
833 		struct {
834 			uint32_t rsvd0;
835 		}rsp;
836 
837 		uint32_t dw[49];
838 	}params;
839 };
840 
841 struct qinq_vlan {
842 #ifdef _BIG_ENDIAN
843 	uint16_t inner;
844 	uint16_t outer;
845 #else
846 	uint16_t outer;
847 	uint16_t inner;
848 #endif
849 };
850 
851 struct normal_vlan {
852 	uint16_t vtag;
853 };
854 
855 struct ntwk_if_vlan_tag {
856 	union {
857 		struct normal_vlan normal;
858 		struct qinq_vlan qinq;
859 	}u0;
860 };
861 
862 /* [50] OPCODE_CREATE_COMMON_IFACE */
863 struct mbx_create_common_iface {
864 	struct mbx_hdr hdr;
865 	union {
866 		struct {
867 			uint32_t version;
868 			uint32_t cap_flags;
869 			uint32_t enable_flags;
870 			uint8_t mac_addr[6];
871 			uint8_t rsvd0;
872 			uint8_t mac_invalid;
873 			struct ntwk_if_vlan_tag vlan_tag;
874 		}req;
875 
876 		struct {
877 			uint32_t if_id;
878 			uint32_t pmac_id;
879 		}rsp;
880 		uint32_t dw[4];
881 	}params;
882 };
883 
884 /* [51] OPCODE_DESTROY_COMMON_IFACE */
885 struct mbx_destroy_common_iface {
886 	struct mbx_hdr hdr;
887 	union {
888 		struct {
889 			uint32_t if_id;
890 		}req;
891 
892 		struct {
893 			uint32_t rsvd0;
894 		}rsp;
895 
896 		uint32_t dw;
897 	}params;
898 };
899 
900 /* event queue context structure */
901 struct   oce_eq_ctx {
902 #ifdef _BIG_ENDIAN
903 	/* dw0 */
904 	uint32_t size:1;
905 	uint32_t rsvd1:1;
906 	uint32_t valid:1;
907 	uint32_t epidx:13;
908 	uint32_t rsvd0:3;
909 	uint32_t cidx:13;
910 
911 	/* dw1 */
912 	uint32_t armed:1;
913 	uint32_t stalled:1;
914 	uint32_t sol_event:1;
915 	uint32_t count:3;
916 	uint32_t pd:10;
917 	uint32_t rsvd2:3;
918 	uint32_t pidx:13;
919 
920 	/* dw2 */
921 	uint32_t rsvd6:4;
922 	uint32_t nodelay:1;
923 	uint32_t phase:2;
924 	uint32_t rsvd5:2;
925 	uint32_t delay_mult:10;
926 	uint32_t rsvd4:1;
927 	uint32_t function:8;
928 	uint32_t rsvd3:4;
929 
930 	/* dw 3 */
931 	uint32_t rsvd7;
932 #else
933 	/* dw0 */
934 	uint32_t cidx:13;
935 	uint32_t rsvd0:3;
936 	uint32_t epidx:13;
937 	uint32_t valid:1;
938 	uint32_t rsvd1:1;
939 	uint32_t size:1;
940 
941 	/* dw1 */
942 	uint32_t pidx:13;
943 	uint32_t rsvd2:3;
944 	uint32_t pd:10;
945 	uint32_t count:3;
946 	uint32_t sol_event:1;
947 	uint32_t stalled:1;
948 	uint32_t armed:1;
949 
950 	/* dw2 */
951 	uint32_t rsvd3:4;
952 	uint32_t function:8;
953 	uint32_t rsvd4:1;
954 	uint32_t delay_mult:10;
955 	uint32_t rsvd5:2;
956 	uint32_t phase:2;
957 	uint32_t nodelay:1;
958 	uint32_t rsvd6:4;
959 
960 	/* dw3 */
961 	uint32_t rsvd7;
962 #endif
963 };
964 
965 /* [13] OPCODE_CREATE_COMMON_EQ */
966 	struct mbx_create_common_eq {
967 	struct mbx_hdr hdr;
968 	union {
969 		struct {
970 #ifdef _BIG_ENDIAN
971 			uint16_t rsvd0;
972 			uint16_t num_pages;
973 #else
974 			uint16_t num_pages;
975 			uint16_t rsvd0;
976 #endif
977 			struct oce_eq_ctx eq_ctx;
978 			struct phys_addr pages[8];
979 		}req;
980 
981 		struct {
982 			uint16_t eq_id;
983 			uint16_t rsvd0;
984 		}rsp;
985 	}params;
986 };
987 
988 /* [55] OPCODE_DESTROY_COMMON_EQ */
989 struct mbx_destroy_common_eq {
990 	struct mbx_hdr hdr;
991 	union {
992 		struct {
993 #ifdef _BIG_ENDIAN
994 			uint16_t rsvd0;
995 			uint16_t id;
996 #else
997 			uint16_t id;
998 			uint16_t rsvd0;
999 #endif
1000 		}req;
1001 
1002 		struct {
1003 			uint32_t rsvd0;
1004 		}rsp;
1005 	}params;
1006 };
1007 
1008 struct oce_cq_ctx {
1009 #ifdef _BIG_ENDIAN
1010 	/* dw0 */
1011 	uint32_t eventable:1;
1012 	uint32_t sol_event:1;
1013 	uint32_t valid:1;
1014 	uint32_t count:2;
1015 	uint32_t rsvd1:1;
1016 	uint32_t epidx:11;
1017 	uint32_t nodelay:1;
1018 	uint32_t coalesce_wm:2;
1019 	uint32_t rsvd0:1;
1020 	uint32_t cidx:11;
1021 
1022 	/* dw1 */
1023 	uint32_t armed:1;
1024 	uint32_t stalled:1;
1025 	uint32_t eq_id:8;
1026 	uint32_t pd:10;
1027 	uint32_t rsvd2:1;
1028 	uint32_t pidx:11;
1029 
1030 	/* dw2 */
1031 	uint32_t rsvd4:20;
1032 	uint32_t function:8;
1033 	uint32_t rsvd3:4;
1034 #else
1035 	/* dw0 */
1036 	uint32_t cidx:11;
1037 	uint32_t rsvd0:1;
1038 	uint32_t coalesce_wm:2;
1039 	uint32_t nodelay:1;
1040 	uint32_t epidx:11;
1041 	uint32_t rsvd1:1;
1042 	uint32_t count:2;
1043 	uint32_t valid:1;
1044 	uint32_t sol_event:1;
1045 	uint32_t eventable:1;
1046 
1047 	/* dw1 */
1048 	uint32_t pidx:11;
1049 	uint32_t rsvd2:1;
1050 	uint32_t pd:10;
1051 	uint32_t eq_id:8;
1052 	uint32_t stalled:1;
1053 	uint32_t armed:1;
1054 
1055 	/* dw2 */
1056 	uint32_t rsvd3:4;
1057 	uint32_t function:8;
1058 	uint32_t rsvd4:20;
1059 #endif
1060 	uint32_t rsvd5;
1061 };
1062 
1063 /* [12] OPCODE_CREATE_COMMON_CQ */
1064 struct mbx_create_common_cq {
1065 	struct mbx_hdr hdr;
1066 	union {
1067 		struct {
1068 #ifdef _BIG_ENDIAN
1069 			uint16_t rsvd0;
1070 			uint16_t num_pages;
1071 #else
1072 			uint16_t num_pages;
1073 			uint16_t rsvd0;
1074 #endif
1075 			struct oce_cq_ctx cq_ctx;
1076 			struct phys_addr pages[4];
1077 		}req;
1078 
1079 		struct {
1080 			uint16_t cq_id;
1081 			uint16_t rsvd0;
1082 		}rsp;
1083 	}params;
1084 };
1085 
1086 /* [54] OPCODE_DESTROY_COMMON_CQ */
1087 struct mbx_destroy_common_cq {
1088 	struct mbx_hdr hdr;
1089 	union {
1090 		struct {
1091 #ifdef _BIG_ENDIAN
1092 			uint16_t rsvd0;
1093 			uint16_t id;
1094 #else
1095 			uint16_t id;
1096 			uint16_t rsvd0;
1097 #endif
1098 		}req;
1099 
1100 		struct {
1101 			uint32_t rsvd0;
1102 		}rsp;
1103 	}params;
1104 };
1105 
1106 struct mq_ring_ctx {
1107 	union {
1108 		struct {
1109 #ifdef _BIG_ENDIAN
1110 			/* dw 0 */
1111 			uint32_t cq_id:10;
1112 			uint32_t fetch_r2t:1;
1113 			uint32_t fetch_wrb:1;
1114 			uint32_t ring_size:4;
1115 			uint32_t rsvd0:2;
1116 			uint32_t con_index:14;
1117 
1118 			/* dw1 */
1119 			uint32_t valid:1;
1120 			uint32_t pdid:9;
1121 			uint32_t fid:8;
1122 			uint32_t prod_index:14;
1123 
1124 			/* dw 2 */
1125 			uint32_t rsvd1:21;
1126 			uint32_t async_cq_id:10;
1127 			uint32_t async_cq_valid:1;
1128 #else
1129 			/* dw 0 */
1130 			uint32_t con_index:14;
1131 			uint32_t rsvd0:2;
1132 			uint32_t ring_size:4;
1133 			uint32_t fetch_wrb:1;
1134 			uint32_t fetch_r2t:1;
1135 			uint32_t cq_id:10;
1136 
1137 			/* dw1 */
1138 			uint32_t prod_index:14;
1139 			uint32_t fid:8;
1140 			uint32_t pdid:9;
1141 			uint32_t valid:1;
1142 
1143 			/* dw 2 */
1144 			uint32_t async_cq_valid:1;
1145 			uint32_t async_cq_id:10;
1146 			uint32_t rsvd1:21;
1147 #endif
1148 			/* dw3 */
1149 			uint32_t rsvd3;
1150 		}s;
1151 		uint32_t dw[4];
1152 	}u0;
1153 };
1154 
1155 /* [21] OPCODE_CREATE_COMMON_MQ */
1156 struct mbx_create_common_mq {
1157 	struct mbx_hdr hdr;
1158 	union {
1159 		struct {
1160 #ifdef _BIG_ENDIAN
1161 			uint16_t rsvd0;
1162 			uint16_t num_pages;
1163 #else
1164 			uint16_t num_pages;
1165 			uint16_t rsvd0;
1166 #endif
1167 			struct mq_ring_ctx context;
1168 			struct phys_addr pages[8];
1169 		}req;
1170 
1171 		struct {
1172 			uint32_t mq_id:16;
1173 			uint32_t rsvd0:16;
1174 		}rsp;
1175 	}params;
1176 };
1177 
1178 /* [53] OPCODE_DESTROY_COMMON_MQ */
1179 struct mbx_destroy_common_mq {
1180 	struct mbx_hdr hdr;
1181 	union {
1182 		struct {
1183 #ifdef _BIG_ENDIAN
1184 			uint16_t rsvd0;
1185 			uint16_t id;
1186 #else
1187 			uint16_t id;
1188 			uint16_t rsvd0;
1189 #endif
1190 		}req;
1191 
1192 		struct {
1193 			uint32_t rsvd0;
1194 		}rsp;
1195 	}params;
1196 };
1197 
1198 /* [35] OPCODE_GET_COMMON_ FW_VERSION */
1199 struct mbx_get_common_fw_version {
1200 	struct mbx_hdr hdr;
1201 	union {
1202 		struct {
1203 			uint32_t rsvd0;
1204 		}req;
1205 
1206 		struct {
1207 			uint8_t fw_ver_str[32];
1208 			uint8_t fw_on_flash_ver_str[32];
1209 		}rsp;
1210 	}params;
1211 };
1212 
1213 /* [52] OPCODE_COMMON_CEV_MODIFY_MSI_MESSAGES */
1214 struct mbx_common_cev_modify_msi_messages {
1215 	struct mbx_hdr hdr;
1216 	union {
1217 		struct {
1218 			uint32_t num_msi_msgs;
1219 		}req;
1220 
1221 		struct {
1222 			uint32_t rsvd0;
1223 		}rsp;
1224 	}params;
1225 };
1226 
1227 /* [36] OPCODE_SET_COMMON_FLOW_CONTROL */
1228 /* [37] OPCODE_GET_COMMON_FLOW_CONTROL */
1229 struct mbx_common_get_set_flow_control {
1230 	struct mbx_hdr hdr;
1231 #ifdef _BIG_ENDIAN
1232 	uint16_t tx_flow_control;
1233 	uint16_t rx_flow_control;
1234 #else
1235 	uint16_t rx_flow_control;
1236 	uint16_t tx_flow_control;
1237 #endif
1238 };
1239 
1240 enum e_flash_opcode {
1241 	MGMT_FLASHROM_OPCODE_FLASH = 1,
1242 	MGMT_FLASHROM_OPCODE_SAVE = 2
1243 };
1244 
1245 /* [06]	OPCODE_READ_COMMON_FLASHROM */
1246 /* [07]	OPCODE_WRITE_COMMON_FLASHROM */
1247 
1248 struct mbx_common_read_write_flashrom {
1249 	struct mbx_hdr hdr;
1250 	uint32_t    flash_op_code;
1251 	uint32_t    flash_op_type;
1252 	uint32_t    data_buffer_size;
1253 	uint32_t    data_offset;
1254 	uint8_t		data_buffer[4];  /* + IMAGE_TRANSFER_SIZE */
1255 };
1256 
1257 struct mbx_common_query_fw_config {
1258 	struct mbx_hdr hdr;
1259 	union {
1260 		struct {
1261 			uint32_t rsvd0[30];
1262 		}req;
1263 
1264 		struct {
1265 			uint32_t    config_number;
1266 			uint32_t    asic_revision;
1267 			uint32_t    port_id; /* used for stats retrieval */
1268 			uint32_t    function_mode;
1269 			uint32_t    ulp0_mode;
1270 			uint32_t    ulp0_nic_wqid_base;
1271 			uint32_t    ulp0_nic_wq_tot;
1272 			uint32_t    ulp0_toe_wqid_base;
1273 			uint32_t    ulp0_toe_wq_tot;
1274 			uint32_t    ulp0_toe_rqid_base;
1275 			uint32_t    ulp0_toe_rqid_tot;
1276 			uint32_t    ulp0_toe_defrqid_base;
1277 			uint32_t    ulp0_toe_defrq_tot;
1278 			uint32_t    ulp0_lro_rqid_base;
1279 			uint32_t    ulp0_lro_rqid_tot;
1280 			uint32_t    ulp0_iscsi_icd_base;
1281 			uint32_t    ulp0_iscsi_icd_tot;
1282 			uint32_t    ulp1_mode;
1283 			uint32_t    ulp1_nic_wqid_base;
1284 			uint32_t    ulp1_wq_tot;
1285 			uint32_t    ulp1_toe_wqid_base;
1286 			uint32_t    ulp1_toe_wq_tot;
1287 			uint32_t    ulp1_toe_rqid_base;
1288 			uint32_t    ulp1_toe_rqid_tot;
1289 			uint32_t    ulp1_toe_defrqid_base;
1290 			uint32_t    ulp1_toe_defrq_tot;
1291 			uint32_t    ulp1_lro_rqid_base;
1292 			uint32_t    ulp1_lro_rqid_tot;
1293 			uint32_t    ulp1_iscsi_icd_base;
1294 			uint32_t    ulp1_iscsi_icd_tot;
1295 		}rsp;
1296 	}params;
1297 };
1298 
1299 struct mbx_common_config_vlan {
1300 	struct mbx_hdr hdr;
1301 	union {
1302 		struct {
1303 #ifdef _BIG_ENDIAN
1304 			uint8_t num_vlans;
1305 			uint8_t untagged;
1306 			uint8_t promisc;
1307 			uint8_t if_id;
1308 #else
1309 			uint8_t if_id;
1310 			uint8_t promisc;
1311 			uint8_t untagged;
1312 			uint8_t num_vlans;
1313 #endif
1314 			union {
1315 				struct normal_vlan normal_vlans[64];
1316 				struct qinq_vlan  qinq_vlans[32];
1317 			}tags;
1318 		}req;
1319 
1320 		struct {
1321 			uint32_t rsvd;
1322 		}rsp;
1323 	}params;
1324 };
1325 
1326 /* [34] OPCODE_COMMON_NTWK_RX_FILTER */
1327 struct mbx_set_common_ntwk_rx_filter {
1328 	struct mbx_hdr hdr;
1329 	uint32_t global_flags_mask;
1330 	uint32_t global_flags;
1331 	uint32_t iface_flags_mask;
1332 	uint32_t iface_flags;
1333 	uint32_t if_id;
1334 	uint32_t num_mcast;
1335 	struct {
1336 		uint8_t byte[6];
1337 	}mac[32];
1338 };
1339 /* [41] OPCODE_MODIFY_COMMON_EQ_DELAY */
1340 struct mbx_modify_common_eq_delay {
1341 	struct mbx_hdr hdr;
1342 	union {
1343 		struct {
1344 			uint32_t num_eq;
1345 			struct {
1346 				uint32_t eq_id;
1347 				uint32_t phase;
1348 				uint32_t dm;
1349 			}delay[8];
1350 		}req;
1351 
1352 		struct {
1353 			uint32_t rsvd0;
1354 		}rsp;
1355 	}params;
1356 };
1357 /* [59] OPCODE_ADD_COMMON_IFACE_MAC */
1358 struct mbx_add_common_iface_mac {
1359 	struct mbx_hdr hdr;
1360 	union {
1361 		struct {
1362 			uint32_t if_id;
1363 			uint8_t mac_address[6];
1364 			uint8_t rsvd0[2];
1365 		}req;
1366 		struct {
1367 			uint32_t pmac_id;
1368 		}rsp;
1369 	} params;
1370 };
1371 
1372 /* [60] OPCODE_DEL_COMMON_IFACE_MAC */
1373 struct mbx_del_common_iface_mac {
1374 	struct mbx_hdr hdr;
1375 	union {
1376 		struct {
1377 			uint32_t if_id;
1378 			uint32_t pmac_id;
1379 		}req;
1380 		struct {
1381 			uint32_t rsvd0;
1382 		}rsp;
1383 	} params;
1384 };
1385 
1386 /* [8] OPCODE_QUERY_COMMON_MAX_MBX_BUFFER_SIZE */
1387 struct mbx_query_common_max_mbx_buffer_size {
1388 	struct mbx_hdr hdr;
1389 	struct {
1390 		uint32_t max_ioctl_bufsz;
1391 	} rsp;
1392 };
1393 
1394 /* [61] OPCODE_COMMON_FUNCTION_RESET */
1395 struct ioctl_common_function_reset {
1396 	struct mbx_hdr hdr;
1397 };
1398 
1399 /* [80] OPCODE_COMMON_FUNCTION_LINK_CONFIG */
1400 struct mbx_common_func_link_cfg {
1401 	struct mbx_hdr hdr;
1402 	union {
1403 		struct {
1404 			uint32_t enable;
1405 		}req;
1406 		struct {
1407 			uint32_t rsvd0;
1408 		}rsp;
1409 	} params;
1410 };
1411 
1412 #pragma pack()
1413 
1414 #ifdef __cplusplus
1415 }
1416 #endif
1417 
1418 #endif /* _OCE_HW_H_ */
1419