1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2010 Emulex. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * Driver specific data structures and function prototypes 29 */ 30 31 #ifndef _OCE_IMPL_H_ 32 #define _OCE_IMPL_H_ 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 #include <sys/types.h> 39 #include <sys/dditypes.h> 40 #include <sys/kstat.h> 41 #include <sys/ddi_intr.h> 42 #include <sys/cmn_err.h> 43 #include <sys/byteorder.h> 44 #include <sys/mac_provider.h> 45 #include <sys/mac_ether.h> 46 #include <sys/vlan.h> 47 #include <sys/bitmap.h> 48 #include <sys/ddidmareq.h> 49 #include <sys/kmem.h> 50 #include <sys/ddi.h> 51 #include <sys/sunddi.h> 52 #include <sys/modctl.h> 53 #include <sys/devops.h> 54 #include <sys/systm.h> 55 #include <sys/conf.h> 56 #include <sys/dlpi.h> 57 #include <sys/ethernet.h> 58 #include <sys/strsun.h> 59 #include <sys/pattr.h> 60 #include <sys/strsubr.h> 61 #include <sys/ddifm.h> 62 #include <sys/fm/protocol.h> 63 #include <sys/fm/util.h> 64 #include <sys/fm/io/ddi.h> 65 #include <sys/note.h> 66 #include <sys/pci.h> 67 #include <sys/random.h> 68 #include <oce_hw.h> 69 #include <oce_hw_eth.h> 70 #include <oce_io.h> 71 #include <oce_buf.h> 72 #include <oce_utils.h> 73 #include <oce_version.h> 74 75 #define SIZE_128 128 76 #define SIZE_256 256 77 #define SIZE_512 512 78 #define SIZE_1K 1024 79 #define SIZE_2K (2 * 1024) 80 #define SIZE_4K (4 * 1024) 81 #define SIZE_8K (8 * 1024) 82 83 #define END 0xdeadface 84 85 #define OCE_MAX_ETH_FRAME_SIZE 1500 86 #define OCE_MAX_JUMBO_FRAME_SIZE 9018 87 #define OCE_MIN_ETH_FRAME_SIZE 64 88 #define OCE_LLC_SNAP_HDR_LEN 8 89 90 #define OCE_MIN_MTU 1500 91 #define OCE_MAX_MTU 9000 92 #define OCE_MAX_MCA 32 93 #define OCE_RQ_MAX_FRAME_SZ 9018 94 95 #define OCE_MAX_EQ 8 96 #define OCE_MAX_CQ 1024 97 #define OCE_MAX_WQ 8 98 #define OCE_MAX_RQ 5 99 100 #define OCE_WQ_NUM_BUFFERS 2048 101 #define OCE_WQ_BUF_SIZE 2048 102 #define OCE_LSO_MAX_SIZE (64 * 1024) 103 #define OCE_DEFAULT_TX_BCOPY_LIMIT 512 104 #define OCE_DEFAULT_RX_BCOPY_LIMIT 128 105 #define OCE_DEFAULT_WQ_EQD 16 106 107 #define OCE_DEFAULT_TX_RING_SIZE 2048 108 #define OCE_DEFAULT_RX_RING_SIZE 1024 109 #define OCE_DEFAULT_WQS 1 110 #define OCE_DEFAULT_RQS 1 111 #define OCE_MAX_RQS 5 112 113 #define OCE_DEFAULT_RX_PKT_PER_INTR (OCE_DEFAULT_RX_RING_SIZE / 2) 114 #define OCE_DEFAULT_TX_RECLAIM_THRESHOLD 1024 115 #define OCE_MAX_RQ_POSTS 255 116 #define OCE_RQ_NUM_BUFFERS 2048 117 #define OCE_RQ_BUF_SIZE 8192 118 #define OCE_DEFAULT_RECHARGE_THRESHOLD OCE_MAX_RQ_POSTS 119 #define OCE_NUM_USED_VECTORS 2 120 #define OCE_ITBL_SIZE 64 121 #define OCE_HKEY_SIZE 40 122 #define OCE_DMA_ALIGNMENT 0x1000ull 123 124 #define OCE_MIN_VECTORS 1 125 126 #define OCE_CAPAB_FLAGS (MBX_RX_IFACE_FLAGS_BROADCAST | \ 127 MBX_RX_IFACE_FLAGS_PROMISCUOUS | \ 128 MBX_RX_IFACE_FLAGS_UNTAGGED | \ 129 MBX_RX_IFACE_FLAGS_MCAST_PROMISCUOUS | \ 130 MBX_RX_IFACE_FLAGS_PASS_L3L4) 131 132 #define OCE_CAPAB_ENABLE (MBX_RX_IFACE_FLAGS_BROADCAST | \ 133 MBX_RX_IFACE_FLAGS_UNTAGGED | \ 134 MBX_RX_IFACE_FLAGS_PASS_L3L4) 135 136 #define OCE_FM_CAPABILITY (DDI_FM_EREPORT_CAPABLE | \ 137 DDI_FM_ACCCHK_CAPABLE | \ 138 DDI_FM_DMACHK_CAPABLE) 139 140 141 #define OCE_DEFAULT_RSS_TYPE (RSS_ENABLE_IPV4|RSS_ENABLE_TCP_IPV4) 142 143 /* flow control definitions */ 144 #define OCE_FC_NONE 0x00000000 145 #define OCE_FC_TX 0x00000001 146 #define OCE_FC_RX 0x00000002 147 #define OCE_DEFAULT_FLOW_CONTROL (OCE_FC_TX | OCE_FC_RX) 148 149 /* PCI Information */ 150 #define OCE_DEV_CFG_BAR 0x01 151 #define OCE_PCI_CSR_BAR 0x02 152 #define OCE_PCI_DB_BAR 0x03 153 154 /* macros for device IO */ 155 #define OCE_READ_REG32(handle, addr) ddi_get32(handle, addr) 156 #define OCE_WRITE_REG32(handle, addr, value) ddi_put32(handle, addr, value) 157 158 #define OCE_CSR_READ32(dev, offset) \ 159 OCE_READ_REG32((dev)->csr_handle, \ 160 (uint32_t *)(void *)((dev)->csr_addr + offset)) 161 162 #define OCE_CSR_WRITE32(dev, offset, value) \ 163 OCE_WRITE_REG32((dev)->csr_handle, \ 164 (uint32_t *)(void *)((dev)->csr_addr + offset), value) 165 166 #define OCE_DB_READ32(dev, offset) \ 167 OCE_READ_REG32((dev)->db_handle, \ 168 (uint32_t *)(void *)((dev)->db_addr + offset)) 169 170 #define OCE_DB_WRITE32(dev, offset, value) \ 171 OCE_WRITE_REG32((dev)->db_handle, \ 172 (uint32_t *)(void *)((dev)->db_addr + offset), value) 173 174 #define OCE_CFG_READ32(dev, offset) \ 175 OCE_READ_REG32((dev)->dev_cfg_handle, \ 176 (uint32_t *)(void *)((dev)->dev_cfg_addr + offset)) 177 178 #define OCE_CFG_WRITE32(dev, offset, value) \ 179 OCE_WRITE_REG32((dev)->dev_cfg_handle, \ 180 (uint32_t *)(void *)((dev)->dev_cfg_addr + offset), value) 181 182 #define OCE_PCI_FUNC(dev) \ 183 ((OCE_CFG_READ32(dev, PCICFG_INTR_CTRL) \ 184 >> HOSTINTR_PFUNC_SHIFT) & HOSTINTR_PFUNC_MASK) 185 186 #define DEV_LOCK(dev) mutex_enter(&dev->dev_lock) 187 188 #define DEV_UNLOCK(dev) mutex_exit(&dev->dev_lock) 189 190 enum oce_ring_size { 191 RING_SIZE_256 = 256, 192 RING_SIZE_512 = 512, 193 RING_SIZE_1024 = 1024, 194 RING_SIZE_2048 = 2048 195 }; 196 197 enum oce_driver_state { 198 STATE_INIT = 0x2, 199 STATE_MAC_STARTED = 0x4, 200 STATE_QUIESCE = 0x8, 201 STATE_MAC_STOPPING = 0x10 202 }; 203 204 struct oce_dev { 205 kmutex_t bmbx_lock; /* Bootstrap Lock */ 206 kmutex_t dev_lock; /* lock for device */ 207 208 /* Queues relarted */ 209 struct oce_wq *wq[OCE_MAX_WQ]; /* TXQ Array */ 210 struct oce_rq *rq[OCE_MAX_RQ]; /* RXQ Array */ 211 struct oce_cq *cq[OCE_MAX_CQ]; /* Completion Queues */ 212 struct oce_eq *eq[OCE_MAX_EQ]; /* Event Queues */ 213 struct oce_mq *mq; /* MQ ring */ 214 215 /* driver state machine */ 216 enum oce_driver_state state; /* state */ 217 boolean_t suspended; /* CPR */ 218 uint32_t attach_state; /* attach progress */ 219 220 oce_dma_buf_t *bmbx; /* Bootstrap MailBox */ 221 222 uint32_t tx_bcopy_limit; /* TX BCOPY Limit */ 223 uint32_t rx_bcopy_limit; /* RX BCOPY Limit */ 224 uint32_t tx_reclaim_threshold; /* Tx reclaim */ 225 uint32_t rx_pkt_per_intr; /* Rx pkts processed per intr */ 226 227 /* BARS */ 228 int num_bars; 229 ddi_acc_handle_t pci_cfg_handle; /* Config space handle */ 230 ddi_acc_handle_t cfg_handle; /* MMIO PCI Config Space Regs */ 231 ddi_acc_handle_t csr_handle; /* MMIO Control Status Regs */ 232 caddr_t csr_addr; 233 caddr_t db_addr; 234 caddr_t dev_cfg_addr; 235 ddi_acc_handle_t db_handle; /* MMIO DoorBell Area */ 236 ddi_acc_handle_t dev_cfg_handle; /* MMIO CONFIG SPACE */ 237 mac_handle_t mac_handle; /* MAC HANDLE */ 238 239 /* device stats */ 240 kstat_t *oce_kstats; /* NIC STATS */ 241 oce_dma_buf_t *stats_dbuf; /* STATS BUFFER */ 242 struct mbx_get_nic_stats *hw_stats; 243 /* dev stats */ 244 uint32_t tx_errors; 245 uint32_t tx_noxmtbuf; 246 247 /* link status */ 248 link_state_t link_status; 249 int32_t link_speed; /* Link speed in Mbps */ 250 251 /* OS */ 252 uint32_t dev_id; /* device ID or instance number */ 253 dev_info_t *dip; /* device info structure for device tree node */ 254 255 /* Interrupt related */ 256 int intr_type; /* INTR TYPE USED */ 257 int num_vectors; /* number of vectors used */ 258 uint_t intr_pri; /* interrupt priority */ 259 int intr_cap; 260 ddi_intr_handle_t *htable; /* intr handler table */ 261 int32_t hsize; 262 263 /* device configuration */ 264 uint32_t rq_max_bufs; /* maximum prealloced buffers */ 265 uint32_t rq_frag_size; /* Rxq fragment size */ 266 enum oce_ring_size tx_ring_size; 267 enum oce_ring_size rx_ring_size; 268 uint32_t neqs; /* No of event queues */ 269 uint32_t nwqs; /* No of Work Queues */ 270 uint32_t nrqs; /* No of Receive Queues */ 271 uint32_t nifs; /* No of interfaces created */ 272 uint32_t tx_rings; 273 uint32_t rx_rings; 274 uint32_t pmac_id; /* used to add or remove mac */ 275 uint8_t unicast_addr[ETHERADDRL]; 276 uint32_t mtu; 277 int32_t fm_caps; 278 boolean_t rss_enable; /* RSS support */ 279 boolean_t lso_capable; /* LSO */ 280 boolean_t promisc; /* PROMISC MODE */ 281 uint32_t if_cap_flags; /* IF CAPAB */ 282 uint32_t flow_control; /* flow control settings */ 283 uint8_t mac_addr[ETHERADDRL]; /* hardware mac address */ 284 uint16_t num_mca; /* MCA supported */ 285 struct ether_addr multi_cast[OCE_MAX_MCA]; /* MC TABLE */ 286 uint32_t cookie; /* used during fw download */ 287 288 /* fw config: only relevant fields */ 289 uint32_t config_number; 290 uint32_t asic_revision; 291 uint32_t port_id; 292 uint32_t function_mode; 293 uint32_t function_caps; 294 uint32_t max_tx_rings; /* Max Rx rings available */ 295 uint32_t max_rx_rings; /* Max rx rings available */ 296 int32_t if_id; /* IF ID */ 297 uint8_t fn; /* function number */ 298 uint8_t fw_version[32]; /* fw version string */ 299 300 /* Logging related */ 301 uint16_t mod_mask; /* Log Mask */ 302 int16_t severity; /* Log level */ 303 }; 304 305 /* GLD handler functions */ 306 int oce_m_start(void *arg); 307 void oce_m_stop(void *arg); 308 mblk_t *oce_m_send(void *arg, mblk_t *pkt); 309 int oce_m_promiscuous(void *arg, boolean_t enable); 310 int oce_m_multicast(void *arg, boolean_t add, const uint8_t *mca); 311 int oce_m_unicast(void *arg, const uint8_t *uca); 312 boolean_t oce_m_getcap(void *arg, mac_capab_t cap, void *data); 313 void oce_m_ioctl(void *arg, queue_t *wq, mblk_t *mp); 314 int oce_m_setprop(void *arg, const char *name, mac_prop_id_t id, 315 uint_t size, const void *val); 316 int oce_m_getprop(void *arg, const char *name, mac_prop_id_t id, 317 uint_t size, void *val); 318 void oce_m_propinfo(void *arg, const char *pr_name, mac_prop_id_t pr_num, 319 mac_prop_info_handle_t prh); 320 321 int oce_m_stat(void *arg, uint_t stat, uint64_t *val); 322 323 /* Hardware start/stop functions */ 324 int oce_start(struct oce_dev *dev); 325 void oce_stop(struct oce_dev *dev); 326 327 /* FMA support Functions */ 328 void oce_fm_init(struct oce_dev *dev); 329 void oce_fm_fini(struct oce_dev *dev); 330 void oce_set_dma_fma_flags(int fm_caps); 331 void oce_set_reg_fma_flags(int fm_caps); 332 void oce_set_tx_map_dma_fma_flags(int fm_caps); 333 void oce_fm_ereport(struct oce_dev *dev, char *detail); 334 int oce_fm_check_acc_handle(struct oce_dev *dev, 335 ddi_acc_handle_t acc_handle); 336 int oce_fm_check_dma_handle(struct oce_dev *dev, 337 ddi_dma_handle_t dma_handle); 338 339 /* Interrupt handling */ 340 int oce_setup_intr(struct oce_dev *dev); 341 int oce_teardown_intr(struct oce_dev *dev); 342 int oce_setup_handlers(struct oce_dev *dev); 343 void oce_remove_handler(struct oce_dev *dev); 344 void oce_ei(struct oce_dev *dev); 345 void oce_di(struct oce_dev *dev); 346 void oce_chip_ei(struct oce_dev *dev); 347 void oce_chip_di(struct oce_dev *dev); 348 349 /* HW initialisation */ 350 int oce_hw_init(struct oce_dev *dev); 351 void oce_hw_fini(struct oce_dev *dev); 352 int oce_setup_adapter(struct oce_dev *dev); 353 void oce_unsetup_adapter(struct oce_dev *dev); 354 355 #ifdef __cplusplus 356 } 357 #endif 358 359 #endif /* _OCE_IMPL_H_ */ 360