1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /* Copyright 2008 QLogic Corporation */
23 
24 /*
25  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
26  * Use is subject to license terms.
27  */
28 
29 #ifndef	_QL_INIT_H
30 #define	_QL_INIT_H
31 
32 
33 /*
34  * ISP2xxx Solaris Fibre Channel Adapter (FCA) driver header file.
35  *
36  * ***********************************************************************
37  * *									**
38  * *				NOTICE					**
39  * *		COPYRIGHT (C) 1996-2008 QLOGIC CORPORATION		**
40  * *			ALL RIGHTS RESERVED				**
41  * *									**
42  * ***********************************************************************
43  *
44  */
45 
46 #ifdef	__cplusplus
47 extern "C" {
48 #endif
49 
50 /*
51  * ISP2200 NVRAM structure definition.
52  * Little endian except where noted.
53  */
54 typedef struct nvram {
55 	/*
56 	 * NVRAM header
57 	 */
58 	uint8_t	 id[4];
59 	uint8_t	 nvram_version;
60 	uint8_t	 reserved_0;
61 
62 	/*
63 	 * NVRAM RISC parameter block
64 	 */
65 	uint8_t	 parameter_block_version;
66 	uint8_t	 reserved_1;
67 
68 	/*
69 	 * LSB BIT 0  = enable_hard_loop_id
70 	 * LSB BIT 1  = enable_fairness
71 	 * LSB BIT 2  = enable_full_duplex
72 	 * LSB BIT 3  = enable_fast_posting
73 	 * LSB BIT 4  = enable_target_mode
74 	 * LSB BIT 5  = disable_initiator_mode
75 	 * LSB BIT 6  = enable_adisc
76 	 * LSB BIT 7  = enable_target_inquiry_data
77 	 *
78 	 * MSB BIT 0  = enable_port_update_ae
79 	 * MSB BIT 1  = disable_initial_lip
80 	 * MSB BIT 2  = enable_decending_soft_assign
81 	 * MSB BIT 3  = previous_assigned_addressing
82 	 * MSB BIT 4  = enable_stop_q_on_full
83 	 * MSB BIT 5  = enable_full_login_on_lip
84 	 * MSB BIT 6  = enable_node_name
85 	 * MSB BIT 7  = extended_control_block
86 	 */
87 	uint8_t	 firmware_options[2];
88 
89 	uint8_t	 max_frame_length[2];
90 	uint8_t	 max_iocb_allocation[2];
91 	uint8_t	 execution_throttle[2];
92 	uint8_t	 login_retry_count;
93 	uint8_t	 retry_delay;			/* unused */
94 	uint8_t	 port_name[8];			/* Big endian. */
95 	uint8_t	 hard_address[2];
96 	uint8_t	 inquiry;
97 	uint8_t	 login_timeout;
98 	uint8_t	 node_name[8];			/* Big endian. */
99 
100 	/*
101 	 * LSB BIT 0 = Timer operation mode bit 0
102 	 * LSB BIT 1 = Timer operation mode bit 1
103 	 * LSB BIT 2 = Timer operation mode bit 2
104 	 * LSB BIT 3 = Timer operation mode bit 3
105 	 * LSB BIT 4 = P2P Connection option bit 0
106 	 * LSB BIT 5 = P2P Connection option bit 1
107 	 * LSB BIT 6 = P2P Connection option bit 2
108 	 * LSB BIT 7 = Enable Non part on LIHA failure
109 	 *
110 	 * MSB BIT 0 = Enable class 2
111 	 * MSB BIT 1 = Enable ACK0
112 	 * MSB BIT 2 =
113 	 * MSB BIT 3 =
114 	 * MSB BIT 4 = FC Tape Enable
115 	 * MSB BIT 5 = Enable FC Confirm
116 	 * MSB BIT 6 = Enable command queuing in target mode
117 	 * MSB BIT 7 = No Logo On Link Down
118 	 */
119 	uint8_t	 add_fw_opt[2];
120 	uint8_t	 response_accumulation_timer;
121 	uint8_t	 interrupt_delay_timer;
122 
123 	/*
124 	 * LSB BIT 0 = Enable Read xfr_rdy
125 	 * LSB BIT 1 = Soft ID only
126 	 * LSB BIT 2 =
127 	 * LSB BIT 3 =
128 	 * LSB BIT 4 = FCP RSP Payload [0]
129 	 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
130 	 * LSB BIT 6 =
131 	 * LSB BIT 7 =
132 	 *
133 	 * MSB BIT 0 = Sbus enable - 2300
134 	 * MSB BIT 1 =
135 	 * MSB BIT 2 =
136 	 * MSB BIT 3 =
137 	 * MSB BIT 4 =
138 	 * MSB BIT 5 = Enable 50 ohm termination
139 	 * MSB BIT 6 = Data Rate (2300 only)
140 	 * MSB BIT 7 = Data Rate (2300 only)
141 	 */
142 	uint8_t	 special_options[2];
143 
144 	/* Reserved for expanded RISC parameter block */
145 	uint8_t reserved_4[26];
146 
147 	/*
148 	 * NVRAM host parameter block
149 	 *
150 	 * LSB BIT 0 = unused
151 	 * LSB BIT 1 = disable_bios
152 	 * LSB BIT 2 = disable_luns
153 	 * LSB BIT 3 = enable_selectable_boot
154 	 * LSB BIT 4 = disable_risc_code_load
155 	 * LSB BIT 5 = set_cache_line_size_1
156 	 * LSB BIT 6 = pci_parity_disable
157 	 * LSB BIT 7 = enable_extended_logging
158 	 *
159 	 * MSB BIT 0 = enable_64bit_addressing
160 	 * MSB BIT 1 = enable_lip_reset
161 	 * MSB BIT 2 = enable_lip_full_login
162 	 * MSB BIT 3 = enable_target_reset
163 	 * MSB BIT 4 = enable_database_storage
164 	 * MSB BIT 5 = unused
165 	 * MSB BIT 6 = unused
166 	 * MSB BIT 7 = unused
167 	 */
168 	uint8_t	 host_p[2];
169 
170 	uint8_t	 boot_node_name[8];
171 	uint8_t	 boot_lun_number;
172 	uint8_t	 reset_delay;
173 	uint8_t	 port_down_retry_count;
174 	uint8_t	 reserved_5;
175 
176 	uint8_t  maximum_luns_per_target[2];
177 
178 	uint8_t reserved_6[14];
179 
180 	/* Offset 100 */
181 	uint8_t reverved_7[12];
182 
183 	/* offset 112 */
184 	uint8_t adapInfo[16];	/* Sun OEM HBA's 23xx only */
185 
186 	uint8_t reserved_8[22];
187 
188 	/* Offset 150 */
189 	uint8_t reserved_9[50];
190 
191 	/* Offset 200 */
192 	uint8_t reserved_10[32];
193 
194 	/*
195 	 * NVRAM Adapter Features offset 232-239
196 	 *
197 	 * LSB BIT 0 = External GBIC
198 	 * LSB BIT 1 = Risc RAM parity
199 	 * LSB BIT 2 = Buffer Plus Module
200 	 * LSB BIT 3 = Multi Chip Adapter
201 	 * LSB BIT 4 =
202 	 * LSB BIT 5 =
203 	 * LSB BIT 6 =
204 	 * LSB BIT 7 =
205 	 *
206 	 * MSB BIT 0 =
207 	 * MSB BIT 1 =
208 	 * MSB BIT 2 =
209 	 * MSB BIT 3 =
210 	 * MSB BIT 4 =
211 	 * MSB BIT 5 =
212 	 * MSB BIT 6 =
213 	 * MSB BIT 7 =
214 	 */
215 	uint8_t adapter_features[2];
216 	uint8_t reserved_11[6];
217 
218 	/*
219 	 * Resrved for use with ISP2300 - offset 240
220 	 */
221 	uint8_t reserved_12[4];
222 
223 	/* Subsystem ID must be at offset 244 */
224 	uint8_t subsystem_vendor_id[2];
225 
226 	uint8_t reserved_13[2];
227 
228 	/* Subsystem device ID must be at offset 248 */
229 	uint8_t subsystem_device_id[2];
230 
231 	/* Subsystem vendor ID for ISP2200 */
232 	uint8_t subsystem_vendor_id_2200[2];
233 
234 	/* Subsystem device ID for ISP2200 */
235 	uint8_t subsystem_device_id_2200[2];
236 
237 	uint8_t	 reserved_14;
238 	uint8_t	 checksum;
239 } nvram_t;
240 
241 /*
242  * NVRAM structure definition.
243  */
244 typedef struct nvram_24xx {
245 	/* NVRAM header. */
246 	uint8_t id[4];
247 	uint8_t nvram_version[2];
248 	uint8_t reserved_0[2];
249 
250 	/* Firmware Initialization Control Block. */
251 	uint8_t version[2];
252 	uint8_t reserved_1[2];
253 	uint8_t max_frame_length[2];
254 	uint8_t execution_throttle[2];
255 	uint8_t exchange_count[2];
256 	uint8_t hard_address[2];
257 	uint8_t port_name[8];
258 	uint8_t node_name[8];
259 	uint8_t login_retry_count[2];
260 	uint8_t link_down_on_nos[2];
261 	uint8_t interrupt_delay_timer[2];
262 	uint8_t login_timeout[2];
263 
264 	/*
265 	 * BIT 0  = Hard Assigned Loop ID
266 	 * BIT 1  = Enable Fairness
267 	 * BIT 2  = Enable Full-Duplex
268 	 * BIT 3  = Reserved
269 	 * BIT 4  = Target Mode Enable
270 	 * BIT 5  = Initiator Mode Disable
271 	 * BIT 6  = Reserved
272 	 * BIT 7  = Reserved
273 	 *
274 	 * BIT 8  = Reserved
275 	 * BIT 9  = Disable Initial LIP
276 	 * BIT 10 = Descending Loop ID Search
277 	 * BIT 11 = Previous Assigned Loop ID
278 	 * BIT 12 = Reserved
279 	 * BIT 13 = Full Login after LIP
280 	 * BIT 14 = Node Name Option
281 	 * BIT 15-31 = Reserved
282 	 */
283 	uint8_t firmware_options_1[4];
284 
285 	/*
286 	 * BIT 0  = Operation Mode bit 0
287 	 * BIT 1  = Operation Mode bit 1
288 	 * BIT 2  = Operation Mode bit 2
289 	 * BIT 3  = Operation Mode bit 3
290 	 * BIT 4  = Connection Options bit 0
291 	 * BIT 5  = Connection Options bit 1
292 	 * BIT 6  = Connection Options bit 2
293 	 * BIT 7  = Enable Non part on LIHA failure
294 	 *
295 	 * BIT 8  = Enable Class 2
296 	 * BIT 9  = Enable ACK0
297 	 * BIT 10 = Reserved
298 	 * BIT 11 = Enable FC-SP Security
299 	 * BIT 12 = FC Tape Enable
300 	 * BIT 13-31 = Reserved
301 	 */
302 	uint8_t firmware_options_2[4];
303 
304 	/*
305 	 * BIT 0  = Reserved
306 	 * BIT 1  = Soft ID only
307 	 * BIT 2  = Reserved
308 	 * BIT 3  = Reserved
309 	 * BIT 4  = FCP RSP Payload bit 0
310 	 * BIT 5  = FCP RSP Payload bit 1
311 	 * BIT 6  = Enable Rec Out-of-Order data frame handling
312 	 * BIT 7  = Disable Automatic PLOGI on Local Loop
313 	 *
314 	 * BIT 8  = Reserved
315 	 * BIT 9  = Enable Out-of-Order FCP_XFER_RDY relative
316 	 *	    offset handling
317 	 * BIT 10 = Reserved
318 	 * BIT 11 = Reserved
319 	 * BIT 12 = Reserved
320 	 * BIT 13 = Data Rate bit 0
321 	 * BIT 14 = Data Rate bit 1
322 	 * BIT 15 = Data Rate bit 2
323 	 * BIT 16 = 75-ohm Termination Select
324 	 * BIT 17-31 = Reserved
325 	 */
326 	uint8_t firmware_options_3[4];
327 
328 	/*
329 	 * Serial Link Control (offset 56)
330 	 * BIT 0  = control enable
331 	 * BIT 1-15 = Reserved
332 	 */
333 	uint8_t swing_opt[2];
334 
335 	/*
336 	 * Serial Link Control 1G (offset 58)
337 	 * BIT 0-7   = Reserved
338 	 *
339 	 * BIT 8-10  = output swing
340 	 * BIT 11-13 = output emphasis
341 	 * BIT 14-15 = Reserved
342 	 */
343 	uint8_t swing_1g[2];
344 
345 	/*
346 	 * Serial Link Control 2G (offset 60)
347 	 * BIT 0-7   = Reserved
348 	 *
349 	 * BIT 8-10  = output swing
350 	 * BIT 11-13 = output emphasis
351 	 * BIT 14-15 = Reserved
352 	 */
353 	uint8_t swing_2g[2];
354 
355 	/*
356 	 * Serial Link Control 4G (offset 62)
357 	 * BIT 0-7   = Reserved
358 	 *
359 	 * BIT 8-10  = output swing
360 	 * BIT 11-13 = output emphasis
361 	 * BIT 14-15 = Reserved
362 	 */
363 	uint8_t swing_4g[2];
364 
365 	/* Offset 64. */
366 	uint8_t reserved_2[32];
367 
368 	/* Offset 96. */
369 	uint8_t reserved_3[32];
370 
371 	/* PCIe table entries. */
372 	uint8_t reserved_4[32];
373 
374 	/* Offset 160. */
375 	uint8_t reserved_5[32];
376 
377 	/* Offset 192. */
378 	uint8_t reserved_6[32];
379 
380 	/* Offset 224. */
381 	uint8_t reserved_7[32];
382 
383 	/*
384 	 * BIT 0  = Enable spinup delay
385 	 * BIT 1  = Disable BIOS
386 	 * BIT 2  = Enable Memory Map BIOS
387 	 * BIT 3  = Enable Selectable Boot
388 	 * BIT 4  = Disable RISC code load
389 	 * BIT 5  = Disable serdes
390 	 * BIT 6  = Enable opt boot mode
391 	 * BIT 7  = Enable int mode BIOS
392 	 *
393 	 * BIT 8  =
394 	 * BIT 9  =
395 	 * BIT 10 = Enable lip full login
396 	 * BIT 11 = Enable target reset
397 	 * BIT 12 =
398 	 * BIT 13 = Default Node Name Option
399 	 * BIT 14 = Default valid
400 	 * BIT 15 = Enable alternate WWN
401 	 *
402 	 * BIT 16-31 =
403 	 */
404 	uint8_t host_p[4];
405 
406 	uint8_t alternate_port_name[8];
407 	uint8_t alternate_node_name[8];
408 
409 	uint8_t boot_port_name[8];
410 	uint8_t boot_lun_number[2];
411 	uint8_t reserved_8[2];
412 
413 	uint8_t alt1_boot_port_name[8];
414 	uint8_t alt1_boot_lun_number[2];
415 	uint8_t reserved_9[2];
416 
417 	uint8_t alt2_boot_port_name[8];
418 	uint8_t alt2_boot_lun_number[2];
419 	uint8_t reserved_10[2];
420 
421 	uint8_t alt3_boot_port_name[8];
422 	uint8_t alt3_boot_lun_number[2];
423 	uint8_t reserved_11[2];
424 
425 	/*
426 	 * BIT 0 = Selective Login
427 	 * BIT 1 = Alt-Boot Enable
428 	 * BIT 2 = Reserved
429 	 * BIT 3 = Enable Boot Order List
430 	 * BIT 4 = Reserved
431 	 * BIT 5 = Enable Selective LUN
432 	 * BIT 6 = Reserved
433 	 * BIT 7-31 =
434 	 */
435 	uint8_t efi_parameters[4];
436 
437 	uint8_t reset_delay;
438 	uint8_t reserved_12;
439 	uint8_t reserved_13[2];
440 
441 	uint8_t boot_id_number[2];
442 	uint8_t reserved_14[2];
443 
444 	uint8_t max_luns_per_target[2];
445 	uint8_t reserved_15[2];
446 
447 	uint8_t port_down_retry_count[2];
448 	uint8_t link_down_timeout[2];
449 
450 	/*
451 	 * FCode parameters word (offset 344)
452 	 *
453 	 * BIT 0 = Enable BIOS pathname
454 	 * BIT 1 = fcode qlc
455 	 * BIT 2 = fcode host
456 	 * BIT 3-7 =
457 	 */
458 	uint8_t	fcode_p0;
459 	uint8_t reserved_16[7];
460 
461 	/* Offset 352. */
462 	uint8_t prev_drv_ver_major;
463 	uint8_t prev_drv_ver_submajob;
464 	uint8_t prev_drv_ver_minor;
465 	uint8_t prev_drv_ver_subminor;
466 
467 	uint8_t prev_bios_ver_major[2];
468 	uint8_t prev_bios_ver_minor[2];
469 
470 	uint8_t prev_efi_ver_major[2];
471 	uint8_t prev_efi_ver_minor[2];
472 
473 	uint8_t prev_fw_ver_major[2];
474 	uint8_t prev_fw_ver_minor;
475 	uint8_t prev_fw_ver_subminor;
476 
477 	uint8_t reserved_17[16];
478 
479 	/* Offset 384. */
480 	uint8_t	def_port_name[8];
481 	uint8_t def_node_name[8];
482 
483 	uint8_t reserved_18[16];
484 
485 	/* Offset 416. */
486 	uint8_t reserved_19[32];
487 
488 	/* Offset 448. */
489 	uint8_t reserved_20[28];
490 
491 	/* Offset 476. */
492 	uint8_t	fw_table_offset[2];
493 	uint8_t fw_table_sig[2];
494 
495 	/* Offset 480. */
496 	uint8_t model_name[8];
497 
498 	/* Offset 488. */
499 	uint8_t power_table[16];
500 
501 	uint8_t subsystem_vendor_id[2];
502 	uint8_t subsystem_device_id[2];
503 
504 	uint8_t checksum[4];
505 } nvram_24xx_t;
506 
507 /*
508  * Firmware Dump structure definition
509  */
510 #define	QL_2200_FW_DUMP_SIZE	0x68000		/* bytes */
511 #define	QL_2300_FW_DUMP_SIZE	0xE2000		/* bytes */
512 #define	QL_6322_FW_DUMP_SIZE	0xE2000		/* bytes */
513 #define	QL_24XX_FW_DUMP_SIZE	0x02b0000	/* bytes */
514 #define	QL_25XX_FW_DUMP_SIZE	0x02df000	/* bytes */
515 
516 #define	QL_24XX_VPD_SIZE	0x200		/* bytes */
517 #define	QL_24XX_SFP_SIZE	0x200		/* bytes */
518 
519 /*
520  * firmware dump struct for 2300 is a superset of firmware dump struct
521  * for 2200. Fields which are 2300 only or are enhanced for 2300 are
522  * marked below.
523  */
524 typedef struct ql_fw_dump {
525 	uint16_t pbiu_reg[8];
526 	uint16_t risc_host_reg[8];	/* 2300 only. */
527 	uint16_t mailbox_reg[16];	/* 2200 only needs 8 */
528 	uint16_t resp_dma_reg[32];	/* 2300 only. */
529 	uint16_t dma_reg[48];
530 	uint16_t risc_hdw_reg[16];
531 	uint16_t risc_gp0_reg[16];
532 	uint16_t risc_gp1_reg[16];
533 	uint16_t risc_gp2_reg[16];
534 	uint16_t risc_gp3_reg[16];
535 	uint16_t risc_gp4_reg[16];
536 	uint16_t risc_gp5_reg[16];
537 	uint16_t risc_gp6_reg[16];
538 	uint16_t risc_gp7_reg[16];
539 	uint16_t frame_buf_hdw_reg[64];	/* 2200 has only 16 */
540 	uint16_t fpm_b0_reg[64];
541 	uint16_t fpm_b1_reg[64];
542 	uint16_t risc_ram[0xf800];	/* 2200 needs only 0xf000 */
543 	uint16_t stack_ram[0x800];	/* 2300 only */
544 	uint16_t data_ram[0xf800];	/* 2300 only */
545 } ql_fw_dump_t;
546 
547 typedef struct ql_24xx_fw_dump {
548 	uint32_t hccr;
549 	uint32_t host_reg[32];
550 	uint16_t mailbox_reg[32];
551 	uint32_t xseq_gp_reg[128];
552 	uint32_t xseq_0_reg[16];
553 	uint32_t xseq_1_reg[16];
554 	uint32_t rseq_gp_reg[128];
555 	uint32_t rseq_0_reg[16];
556 	uint32_t rseq_1_reg[16];
557 	uint32_t rseq_2_reg[16];
558 	uint32_t cmd_dma_reg[16];
559 	uint32_t req0_dma_reg[15];
560 	uint32_t resp0_dma_reg[15];
561 	uint32_t req1_dma_reg[15];
562 	uint32_t xmt0_dma_reg[32];
563 	uint32_t xmt1_dma_reg[32];
564 	uint32_t xmt2_dma_reg[32];
565 	uint32_t xmt3_dma_reg[32];
566 	uint32_t xmt4_dma_reg[32];
567 	uint32_t xmt_data_dma_reg[16];
568 	uint32_t rcvt0_data_dma_reg[32];
569 	uint32_t rcvt1_data_dma_reg[32];
570 	uint32_t risc_gp_reg[128];
571 	uint32_t shadow_reg[7];
572 	uint32_t lmc_reg[112];
573 	uint32_t fpm_hdw_reg[192];
574 	uint32_t fb_hdw_reg[176];
575 	uint32_t code_ram[0x2000];
576 	uint32_t ext_mem[1];
577 } ql_24xx_fw_dump_t;
578 
579 typedef struct ql_25xx_fw_dump {
580 	uint32_t r2h_status;
581 	uint32_t hostrisc_reg[32];
582 	uint32_t pcie_reg[4];
583 	uint32_t host_reg[32];
584 	uint16_t mailbox_reg[32];
585 	uint32_t xseq_gp_reg[128];
586 	uint32_t xseq_0_reg[48];
587 	uint32_t xseq_1_reg[16];
588 	uint32_t rseq_gp_reg[128];
589 	uint32_t rseq_0_reg[32];
590 	uint32_t rseq_1_reg[16];
591 	uint32_t rseq_2_reg[16];
592 	uint32_t aseq_gp_reg[128];
593 	uint32_t aseq_0_reg[32];
594 	uint32_t aseq_1_reg[16];
595 	uint32_t aseq_2_reg[16];
596 	uint32_t cmd_dma_reg[16];
597 	uint32_t req0_dma_reg[15];
598 	uint32_t resp0_dma_reg[15];
599 	uint32_t req1_dma_reg[15];
600 	uint32_t xmt0_dma_reg[32];
601 	uint32_t xmt1_dma_reg[32];
602 	uint32_t xmt2_dma_reg[32];
603 	uint32_t xmt3_dma_reg[32];
604 	uint32_t xmt4_dma_reg[32];
605 	uint32_t xmt_data_dma_reg[16];
606 	uint32_t rcvt0_data_dma_reg[32];
607 	uint32_t rcvt1_data_dma_reg[32];
608 	uint32_t risc_gp_reg[128];
609 	uint32_t shadow_reg[11];
610 	uint32_t risc_io;
611 	uint32_t lmc_reg[128];
612 	uint32_t fpm_hdw_reg[192];
613 	uint32_t fb_hdw_reg[192];
614 	uint32_t code_ram[0x2000];
615 	uint16_t req_rsp_q[(REQUEST_QUEUE_SIZE + RESPONSE_QUEUE_SIZE) / 2];
616 	uint32_t ext_mem[1];
617 } ql_25xx_fw_dump_t;
618 
619 #ifdef _KERNEL
620 
621 /*
622  * ql_lock_nvram() flags
623  */
624 #define	LNF_NVRAM_DATA	BIT_0		/* get nvram */
625 #define	LNF_VPD_DATA	BIT_1		/* get vpd data (24xx only) */
626 
627 /*
628  *  ISP product identification definitions in mailboxes after reset.
629  */
630 #define	PROD_ID_1	0x4953
631 #define	PROD_ID_2	0x0000
632 #define	PROD_ID_2a	0x5020
633 #define	PROD_ID_3	0x2020
634 
635 /*
636  * NVRAM Command values.
637  */
638 #define	NV_START_BIT	BIT_2
639 #define	NV_WRITE_OP	(BIT_26+BIT_24)
640 #define	NV_READ_OP	(BIT_26+BIT_25)
641 #define	NV_ERASE_OP	(BIT_26+BIT_25+BIT_24)
642 #define	NV_MASK_OP	(BIT_26+BIT_25+BIT_24)
643 #define	NV_DELAY_COUNT	10
644 
645 union ql_dev_id_list;
646 
647 /*
648  * Global Data in ql_init.c source file.
649  */
650 
651 /*
652  * Global Function Prototypes in ql_init.c source file.
653  */
654 int ql_initialize_adapter(ql_adapter_state_t *);
655 int ql_pci_sbus_config(ql_adapter_state_t *);
656 int ql_nvram_config(ql_adapter_state_t *);
657 uint16_t ql_get_nvram_word(ql_adapter_state_t *, uint32_t);
658 void ql_nv_write(ql_adapter_state_t *, uint16_t);
659 void ql_nv_delay(void);
660 int ql_lock_nvram(ql_adapter_state_t *, uint32_t *, uint32_t);
661 void ql_release_nvram(ql_adapter_state_t *);
662 void ql_common_properties(ql_adapter_state_t *);
663 uint32_t ql_get_prop(ql_adapter_state_t *, char *);
664 int ql_load_isp_firmware(ql_adapter_state_t *);
665 int ql_start_firmware(ql_adapter_state_t *);
666 int ql_set_cache_line(ql_adapter_state_t *);
667 int ql_init_rings(ql_adapter_state_t *);
668 int ql_fw_ready(ql_adapter_state_t *, uint8_t);
669 void ql_dev_list(ql_adapter_state_t *, union ql_dev_id_list *, uint32_t,
670     port_id_t *, uint16_t *);
671 void ql_reset_chip(ql_adapter_state_t *);
672 void ql_reset_24xx_chip(ql_adapter_state_t *);
673 int ql_abort_isp(ql_adapter_state_t *);
674 int ql_vport_control(ql_adapter_state_t *, uint8_t);
675 int ql_vport_modify(ql_adapter_state_t *, uint8_t, uint8_t);
676 int ql_vport_enable(ql_adapter_state_t *);
677 ql_adapter_state_t *ql_vport_create(ql_adapter_state_t *, uint8_t);
678 void ql_vport_destroy(ql_adapter_state_t *);
679 #endif	/* _KERNEL */
680 
681 #ifdef	__cplusplus
682 }
683 #endif
684 
685 #endif /* _QL_INIT_H */
686