193c20f26SSukumar Swaminathan /* 293c20f26SSukumar Swaminathan * CDDL HEADER START 393c20f26SSukumar Swaminathan * 493c20f26SSukumar Swaminathan * The contents of this file are subject to the terms of the 593c20f26SSukumar Swaminathan * Common Development and Distribution License (the "License"). 693c20f26SSukumar Swaminathan * You may not use this file except in compliance with the License. 793c20f26SSukumar Swaminathan * 893c20f26SSukumar Swaminathan * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 993c20f26SSukumar Swaminathan * or http://www.opensolaris.org/os/licensing. 1093c20f26SSukumar Swaminathan * See the License for the specific language governing permissions 1193c20f26SSukumar Swaminathan * and limitations under the License. 1293c20f26SSukumar Swaminathan * 1393c20f26SSukumar Swaminathan * When distributing Covered Code, include this CDDL HEADER in each 1493c20f26SSukumar Swaminathan * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 1593c20f26SSukumar Swaminathan * If applicable, add the following below this CDDL HEADER, with the 1693c20f26SSukumar Swaminathan * fields enclosed by brackets "[]" replaced with your own identifying 1793c20f26SSukumar Swaminathan * information: Portions Copyright [yyyy] [name of copyright owner] 1893c20f26SSukumar Swaminathan * 1993c20f26SSukumar Swaminathan * CDDL HEADER END 2093c20f26SSukumar Swaminathan */ 2193c20f26SSukumar Swaminathan 22*4c3888b8SHans Rosenfeld /* Copyright 2015 QLogic Corporation */ 2393c20f26SSukumar Swaminathan 2493c20f26SSukumar Swaminathan /* 25f885d00fSDaniel Beauregard * Copyright (c) 2008, 2010, Oracle and/or its affiliates. All rights reserved. 2693c20f26SSukumar Swaminathan */ 2793c20f26SSukumar Swaminathan 2893c20f26SSukumar Swaminathan #ifndef _QL_MBX_H 2993c20f26SSukumar Swaminathan #define _QL_MBX_H 3093c20f26SSukumar Swaminathan 3193c20f26SSukumar Swaminathan /* 3293c20f26SSukumar Swaminathan * ISP2xxx Solaris Fibre Channel Adapter (FCA) driver header file. 3393c20f26SSukumar Swaminathan * 3493c20f26SSukumar Swaminathan * *********************************************************************** 3593c20f26SSukumar Swaminathan * * ** 3693c20f26SSukumar Swaminathan * * NOTICE ** 37*4c3888b8SHans Rosenfeld * * COPYRIGHT (C) 1996-2015 QLOGIC CORPORATION ** 3893c20f26SSukumar Swaminathan * * ALL RIGHTS RESERVED ** 3993c20f26SSukumar Swaminathan * * ** 4093c20f26SSukumar Swaminathan * *********************************************************************** 4193c20f26SSukumar Swaminathan * 4293c20f26SSukumar Swaminathan */ 4393c20f26SSukumar Swaminathan 4493c20f26SSukumar Swaminathan #ifdef __cplusplus 4593c20f26SSukumar Swaminathan extern "C" { 4693c20f26SSukumar Swaminathan #endif 4793c20f26SSukumar Swaminathan 4893c20f26SSukumar Swaminathan /* 4993c20f26SSukumar Swaminathan * ISP mailbox Self-Test status codes 5093c20f26SSukumar Swaminathan */ 51*4c3888b8SHans Rosenfeld #define MBS_ROM_IDLE 0 /* Firmware Alive. */ 52*4c3888b8SHans Rosenfeld #define MBS_ROM_CHKSUM_ERR 1 /* Checksum Error. */ 53*4c3888b8SHans Rosenfeld #define MBS_ROM_BUSY 4 /* Busy. */ 54*4c3888b8SHans Rosenfeld #define MBS_ROM_CONFIG_ERR 0xF /* Board Config Error. */ 55*4c3888b8SHans Rosenfeld #define MBS_ROM_STATUS_MASK 0xF 56*4c3888b8SHans Rosenfeld 57*4c3888b8SHans Rosenfeld #define MBS_ROM_FW_RUNNING 0x8400 /* firmware running. */ 58*4c3888b8SHans Rosenfeld #define MBS_ROM_FW_CONFIG_ERR 0x8401 /* firmware config error */ 5993c20f26SSukumar Swaminathan 6093c20f26SSukumar Swaminathan /* 6193c20f26SSukumar Swaminathan * ISP mailbox command complete status codes 6293c20f26SSukumar Swaminathan */ 6393c20f26SSukumar Swaminathan #define MBS_COMMAND_COMPLETE 0x4000 6493c20f26SSukumar Swaminathan #define MBS_INVALID_COMMAND 0x4001 6593c20f26SSukumar Swaminathan #define MBS_HOST_INTERFACE_ERROR 0x4002 6693c20f26SSukumar Swaminathan #define MBS_TEST_FAILED 0x4003 6793c20f26SSukumar Swaminathan #define MBS_POST_ERROR 0x4004 6893c20f26SSukumar Swaminathan #define MBS_COMMAND_ERROR 0x4005 6993c20f26SSukumar Swaminathan #define MBS_COMMAND_PARAMETER_ERROR 0x4006 7093c20f26SSukumar Swaminathan #define MBS_PORT_ID_USED 0x4007 7193c20f26SSukumar Swaminathan #define MBS_LOOP_ID_USED 0x4008 7293c20f26SSukumar Swaminathan #define MBS_ALL_IDS_IN_USE 0x4009 7393c20f26SSukumar Swaminathan #define MBS_NOT_LOGGED_IN 0x400A 7493c20f26SSukumar Swaminathan #define MBS_LOOP_DOWN 0x400B 7593c20f26SSukumar Swaminathan #define MBS_LOOP_BACK_ERROR 0x400C 7693c20f26SSukumar Swaminathan #define MBS_CHECKSUM_ERROR 0x4010 7793c20f26SSukumar Swaminathan 7893c20f26SSukumar Swaminathan /* 7993c20f26SSukumar Swaminathan * Sub-error Codes for Mailbox Command Completion Status Code 4005h 8093c20f26SSukumar Swaminathan */ 8193c20f26SSukumar Swaminathan #define MBSS_NO_LINK 0x0001 8293c20f26SSukumar Swaminathan #define MBSS_IOCB_ALLOC_ERR 0x0002 8393c20f26SSukumar Swaminathan #define MBSS_ECB_ALLOC_ERR 0x0003 8493c20f26SSukumar Swaminathan #define MBSS_CMD_FAILURE 0x0004 8593c20f26SSukumar Swaminathan #define MBSS_NO_FABRIC 0x0005 8693c20f26SSukumar Swaminathan #define MBSS_FIRMWARE_NOT_RDY 0x0007 8793c20f26SSukumar Swaminathan #define MBSS_INITIATOR_DISABLED 0x0008 8893c20f26SSukumar Swaminathan #define MBSS_NOT_LOGGED_IN 0x0009 8993c20f26SSukumar Swaminathan #define MBSS_PARTIAL_DATA_XFER 0x000A 9093c20f26SSukumar Swaminathan #define MBSS_TOPOLOGY_ERR 0x0016 9193c20f26SSukumar Swaminathan #define MBSS_CHIP_RESET_NEEDED 0x0017 9293c20f26SSukumar Swaminathan #define MBSS_MULTIPLE_OPEN_EXCH 0x0018 9393c20f26SSukumar Swaminathan #define MBSS_IOCB_COUNT_ERR 0x0019 9493c20f26SSukumar Swaminathan #define MBSS_CMD_AFTER_FW_INIT_ERR 0x001A 954f8b8adcSDaniel Beauregard #define MBSS_NO_VIRTUAL_PORT_ID 0x001B 964f8b8adcSDaniel Beauregard #define MBSS_INVALID_FCF_INDEX 0x0022 974f8b8adcSDaniel Beauregard #define MBSS_MPI_PROCESSOR_ERR 0x0023 984f8b8adcSDaniel Beauregard #define MBSS_SEMAPHORE_ERR 0x0024 994f8b8adcSDaniel Beauregard #define MBSS_RANGE_ERR 0x0025 1004f8b8adcSDaniel Beauregard #define MBSS_TRANSFER_SIZE_TO_LARGE 0x0026 1014f8b8adcSDaniel Beauregard #define MBSS_CHECKSUM_ERR 0x0027 1024f8b8adcSDaniel Beauregard #define MBSS_CONFIGURATION_ERR 0x0028 10393c20f26SSukumar Swaminathan 10493c20f26SSukumar Swaminathan /* 10593c20f26SSukumar Swaminathan * ISP mailbox asynchronous event status codes 10693c20f26SSukumar Swaminathan */ 10793c20f26SSukumar Swaminathan #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ 10893c20f26SSukumar Swaminathan #define MBA_RESET 0x8001 /* Reset Detected. */ 10993c20f26SSukumar Swaminathan #define MBA_SYSTEM_ERR 0x8002 /* System Error. */ 11093c20f26SSukumar Swaminathan #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ 11193c20f26SSukumar Swaminathan #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ 11293c20f26SSukumar Swaminathan #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ 11393c20f26SSukumar Swaminathan #define MBA_MENLO_ALERT 0x800f /* Menlo Alert Notification. */ 11493c20f26SSukumar Swaminathan #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */ 11593c20f26SSukumar Swaminathan /* occurred. */ 11693c20f26SSukumar Swaminathan #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */ 11793c20f26SSukumar Swaminathan #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */ 11893c20f26SSukumar Swaminathan #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */ 11993c20f26SSukumar Swaminathan #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */ 12093c20f26SSukumar Swaminathan #define MBA_RSCN_UPDATE 0x8015 /* State Change Registration. */ 12193c20f26SSukumar Swaminathan #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */ 12293c20f26SSukumar Swaminathan #define MBA_LIP_ERROR 0x8017 /* Loop initialization errors. */ 123*4c3888b8SHans Rosenfeld #define MBA_LOGIN_REJECT 0x8018 /* Login Reject Reason. */ 12493c20f26SSukumar Swaminathan #define MBA_SECURITY_UPDATE 0x801B /* FC-SP security update. */ 12593c20f26SSukumar Swaminathan #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */ 12693c20f26SSukumar Swaminathan #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */ 12793c20f26SSukumar Swaminathan #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */ 12893c20f26SSukumar Swaminathan #define MBA_IP_RECEIVE 0x8023 /* IP Received. */ 12993c20f26SSukumar Swaminathan #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */ 13093c20f26SSukumar Swaminathan #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */ 13193c20f26SSukumar Swaminathan #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */ 13293c20f26SSukumar Swaminathan #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */ 13393c20f26SSukumar Swaminathan /* used. */ 1344f8b8adcSDaniel Beauregard #define MBA_ERROR_LOGGING_DISABLED 0x8029 /* Error Logging Disabled. */ 13593c20f26SSukumar Swaminathan #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */ 1365dfd244aSDaniel Beauregard #define MBA_DCBX_COMPLETED 0x8030 /* DCBX completed. */ 13793c20f26SSukumar Swaminathan #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */ 1385dfd244aSDaniel Beauregard #define MBA_FCF_CONFIG_ERROR 0x8031 /* FCF configuration error. */ 13993c20f26SSukumar Swaminathan #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */ 1404f8b8adcSDaniel Beauregard #define MBA_DCBX_PARAM_CHANGED 0x8032 /* DCBX parameters changed. */ 14193c20f26SSukumar Swaminathan #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */ 14293c20f26SSukumar Swaminathan #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */ 14393c20f26SSukumar Swaminathan #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */ 14493c20f26SSukumar Swaminathan #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */ 14593c20f26SSukumar Swaminathan #define MBA_ZIO_UPDATE 0x8040 /* ZIO response queue update. */ 14693c20f26SSukumar Swaminathan #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */ 14793c20f26SSukumar Swaminathan #define MBA_PORT_BYPASS_CHANGED 0x8043 /* Crystal+ port#0 bypass transition */ 14893c20f26SSukumar Swaminathan #define MBA_RECEIVE_ERROR 0x8048 /* Receive Error */ 14993c20f26SSukumar Swaminathan #define MBA_LS_RJT_SENT 0x8049 /* LS_RJT response sent */ 150*4c3888b8SHans Rosenfeld #define MBA_QUEUE_FULL 0x8049 /* Queue full */ 151*4c3888b8SHans Rosenfeld #define MBA_CLASS_2_RJT 0x804F /* Class 2 RJT sent */ 152*4c3888b8SHans Rosenfeld #define MBA_VDC_MESSAGE 0x805F /* VDC message event */ 15393c20f26SSukumar Swaminathan #define MBA_FW_RESTART_COMP 0x8060 /* Firmware Restart Complete. */ 154*4c3888b8SHans Rosenfeld #define MBA_TEMPERATURE_EVENT 0x8070 /* Temperature event. */ 155*4c3888b8SHans Rosenfeld #define MBA_D_PORT_DIAGS 0x8080 /* D_Port Diagnostics. */ 1565dfd244aSDaniel Beauregard #define MBA_IDC_COMPLETE 0x8100 /* Inter-driver communication */ 1575dfd244aSDaniel Beauregard /* complete. */ 1585dfd244aSDaniel Beauregard #define MBA_IDC_NOTIFICATION 0x8101 /* Inter-driver communication */ 1595dfd244aSDaniel Beauregard /* notification. */ 1605dfd244aSDaniel Beauregard #define MBA_IDC_TIME_EXTENDED 0x8102 /* Inter-driver communication */ 1615dfd244aSDaniel Beauregard /* time extended. */ 162*4c3888b8SHans Rosenfeld #define MBA_SFP_INSERTION 0x8130 /* Transceiver insertion */ 163*4c3888b8SHans Rosenfeld #define MBA_SFP_REMOVAL 0x8131 /* Transceiver removal */ 164*4c3888b8SHans Rosenfeld #define MBA_NIC_STATE_CHANGE 0x8200 /* NIC Firmware State Change */ 165*4c3888b8SHans Rosenfeld #define MBA_AUTO_FW_INIT_COMP 0x8400 /* Autoload fw init complete. */ 166*4c3888b8SHans Rosenfeld #define MBA_AUTO_FW_INIT_ERR 0x8401 /* Autoload fw init failure. */ 16793c20f26SSukumar Swaminathan 16893c20f26SSukumar Swaminathan /* Driver defined. */ 16993c20f26SSukumar Swaminathan #define MBA_CMPLT_1_32BIT 0x9000 /* Completion 1 32bit IOSB. */ 17093c20f26SSukumar Swaminathan /* 17193c20f26SSukumar Swaminathan * Mailbox 23 event codes 17293c20f26SSukumar Swaminathan */ 17393c20f26SSukumar Swaminathan #define MBX23_MBX_OR_ASYNC_EVENT 0x0 17493c20f26SSukumar Swaminathan #define MBX23_RESPONSE_QUEUE_UPDATE 0x1 17593c20f26SSukumar Swaminathan #define MBX23_SCSI_COMPLETION 0x2 17693c20f26SSukumar Swaminathan 17793c20f26SSukumar Swaminathan /* 1784f8b8adcSDaniel Beauregard * System Error event (0x8002) defines 1794f8b8adcSDaniel Beauregard */ 180*4c3888b8SHans Rosenfeld #define SE_NIC_HEARTHBEAT BIT_3 1814f8b8adcSDaniel Beauregard #define SE_MPI_RISC BIT_2 1824f8b8adcSDaniel Beauregard #define SE_NIC_1 BIT_1 1834f8b8adcSDaniel Beauregard #define SE_NIC_2 BIT_0 1844f8b8adcSDaniel Beauregard 1854f8b8adcSDaniel Beauregard /* 186*4c3888b8SHans Rosenfeld * Port Database Update event (0x8014) defines 187*4c3888b8SHans Rosenfeld */ 188*4c3888b8SHans Rosenfeld #define PDU_GLOBAL_EVENT 0xffff 189*4c3888b8SHans Rosenfeld /* 190*4c3888b8SHans Rosenfeld * Port Database Update event (0x8014) login states 191*4c3888b8SHans Rosenfeld */ 192*4c3888b8SHans Rosenfeld #define PDU_PLOGI_COMPLETE 0x4 193*4c3888b8SHans Rosenfeld #define PDU_PRLI_COMPLETE 0x6 194*4c3888b8SHans Rosenfeld #define PDU_PORT_LOGOUT 0x7 195*4c3888b8SHans Rosenfeld /* 196*4c3888b8SHans Rosenfeld * Port Database Update event (0x8014) reason codes 197*4c3888b8SHans Rosenfeld */ 198*4c3888b8SHans Rosenfeld #define PDU_LINK_INITIALIZED 0x0 199*4c3888b8SHans Rosenfeld #define PDU_ADISC_ACC_CONFLICT 0x1 200*4c3888b8SHans Rosenfeld #define PDU_ADISC_REJECT 0x2 201*4c3888b8SHans Rosenfeld #define PDU_ADISC_REQ_CONFLICT 0x3 202*4c3888b8SHans Rosenfeld #define PDU_PLOGI_RECEIVED 0x4 203*4c3888b8SHans Rosenfeld #define PDU_PLOGI_REJECT 0x5 204*4c3888b8SHans Rosenfeld #define PDU_PRLI_RECEIVED 0x6 205*4c3888b8SHans Rosenfeld #define PDU_PRLI_REJECT 0x7 206*4c3888b8SHans Rosenfeld #define PDU_GLOBAL_TPRLO 0x8 207*4c3888b8SHans Rosenfeld #define PDU_SELECTIVE_TPRLO 0x9 208*4c3888b8SHans Rosenfeld #define PDU_PRLO_RECEIVED 0xa 209*4c3888b8SHans Rosenfeld #define PDU_LOGO_RECEIVED 0xb 210*4c3888b8SHans Rosenfeld #define PDU_TOPOLOGY_CHANGE 0xc 211*4c3888b8SHans Rosenfeld #define PDU_N_PORT_ID_CHANGE 0xd 212*4c3888b8SHans Rosenfeld #define PDU_FLOGI_REJECT 0xe 213*4c3888b8SHans Rosenfeld #define PDU_BAD_FAN 0xf 214*4c3888b8SHans Rosenfeld #define PDU_FLOGI_TIMEOUT 0x10 215*4c3888b8SHans Rosenfeld #define PDU_ABTS_LOGO_FAILED 0x11 216*4c3888b8SHans Rosenfeld #define PDU_PLOGI_COMPLETED 0x12 217*4c3888b8SHans Rosenfeld #define PDU_PRLI_COMPLETED 0x13 218*4c3888b8SHans Rosenfeld #define PDU_OWN_OPN_FRAME_PATH 0x14 219*4c3888b8SHans Rosenfeld #define PDU_OWN_OPN_DATA_PATH 0x15 220*4c3888b8SHans Rosenfeld #define PDU_TRANSMIT_ERROR 0x16 221*4c3888b8SHans Rosenfeld #define PDU_EXPLICIT_LOGO_REQ 0x17 222*4c3888b8SHans Rosenfeld #define PDU_ADISC_REQ_TIMEOUT 0x18 223*4c3888b8SHans Rosenfeld #define PDU_EVFP_RECEIVED 0x19 224*4c3888b8SHans Rosenfeld #define PDU_SW_LOGO_RECEIVED 0x1a 225*4c3888b8SHans Rosenfeld #define PDU_FCF_LIST_CHANGED 0x1b 226*4c3888b8SHans Rosenfeld #define PDU_FCF_CONFIG_CHANGED 0x1c 227*4c3888b8SHans Rosenfeld #define PDU_FIP_RECEIVED 0x1d 228*4c3888b8SHans Rosenfeld #define PDU_FCF_TIMEOUT 0x1e 229*4c3888b8SHans Rosenfeld 230*4c3888b8SHans Rosenfeld /* 231*4c3888b8SHans Rosenfeld * Registered State Change Notification (0x8015) defines 232*4c3888b8SHans Rosenfeld */ 233*4c3888b8SHans Rosenfeld #define RSCN_AF_PORT 0x0 234*4c3888b8SHans Rosenfeld #define RSCN_AF_AREA 0x1 235*4c3888b8SHans Rosenfeld #define RSCN_AF_DOMAIN 0x2 236*4c3888b8SHans Rosenfeld #define RSCN_AF_FABRIC 0x3 237*4c3888b8SHans Rosenfeld #define RSCN_AF_MASK (BIT_1 | BIT_0) 238*4c3888b8SHans Rosenfeld 239*4c3888b8SHans Rosenfeld /* 240*4c3888b8SHans Rosenfeld * Temperature alert event (0x8070) defines 241*4c3888b8SHans Rosenfeld */ 242*4c3888b8SHans Rosenfeld #define TCA_INVALID_CONFIGURATION 0x10 243*4c3888b8SHans Rosenfeld #define TCA_INVALID_NUMBER_OF_SENSORS 0x11 244*4c3888b8SHans Rosenfeld #define TCA_SHUTDOWN_INITIATED 0x12 245*4c3888b8SHans Rosenfeld #define TCA_SENSOR_NOT_FUNCTIONAL 0x13 246*4c3888b8SHans Rosenfeld 247*4c3888b8SHans Rosenfeld /* 248*4c3888b8SHans Rosenfeld * Thermal temperature defines 249*4c3888b8SHans Rosenfeld */ 250*4c3888b8SHans Rosenfeld #define READ_ASIC_TEMP 0xC 251*4c3888b8SHans Rosenfeld #define TEMP_SUPPORT_I2C BIT_0 252*4c3888b8SHans Rosenfeld #define TEMP_SUPPORT_ISP BIT_1 253*4c3888b8SHans Rosenfeld 254*4c3888b8SHans Rosenfeld /* 255*4c3888b8SHans Rosenfeld * D_Port Diagnostic event (0x8080) defines 256*4c3888b8SHans Rosenfeld */ 257*4c3888b8SHans Rosenfeld #define DPA_START 0 258*4c3888b8SHans Rosenfeld #define DPA_DONE 1 259*4c3888b8SHans Rosenfeld #define DPA_ERROR 2 260*4c3888b8SHans Rosenfeld #define DPA_MASK 0xF 261*4c3888b8SHans Rosenfeld 262*4c3888b8SHans Rosenfeld /* 26393c20f26SSukumar Swaminathan * Menlo alert event defines 26493c20f26SSukumar Swaminathan */ 26593c20f26SSukumar Swaminathan #define MLA_PANIC_RECOVERY 0x1 26693c20f26SSukumar Swaminathan #define MLA_LOGIN_OPERATIONAL_FW 0x2 26793c20f26SSukumar Swaminathan #define MLA_LOGIN_DIAGNOSTIC_FW 0x3 26893c20f26SSukumar Swaminathan #define MLA_LOGIN_GOLDEN_FW 0x4 26993c20f26SSukumar Swaminathan #define MLA_REJECT_RESPONSE 0x5 27093c20f26SSukumar Swaminathan 27193c20f26SSukumar Swaminathan /* 27293c20f26SSukumar Swaminathan * ISP mailbox commands 27393c20f26SSukumar Swaminathan */ 27493c20f26SSukumar Swaminathan #define MBC_LOAD_RAM 1 /* Load RAM. */ 275*4c3888b8SHans Rosenfeld #define MBC_WRITE_REMOTE_REG 1 /* Write remote register. */ 27693c20f26SSukumar Swaminathan #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ 27793c20f26SSukumar Swaminathan #define MBC_DUMP_RAM 3 /* Dump RAM. */ 278*4c3888b8SHans Rosenfeld #define MBC_LOAD_FLASH_IMAGE 3 /* Load flash image. */ 279*4c3888b8SHans Rosenfeld #define MBC_WRITE_SERDES_REG 3 /* Write FC serdes register */ 280*4c3888b8SHans Rosenfeld #define MBC_READ_SERDES_REG 4 /* Read FC serdes registers */ 28193c20f26SSukumar Swaminathan #define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */ 28293c20f26SSukumar Swaminathan #define MBC_READ_RAM_WORD 5 /* Read RAM word. */ 283*4c3888b8SHans Rosenfeld #define MBC_MPI_RAM 5 /* Load/dump MPI RAM. */ 28493c20f26SSukumar Swaminathan #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ 28593c20f26SSukumar Swaminathan #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ 28693c20f26SSukumar Swaminathan #define MBC_ABOUT_FIRMWARE 8 /* About Firmware. */ 287*4c3888b8SHans Rosenfeld #define MBC_LOAD_RISC_RAM 9 /* Load RSIC RAM. */ 288*4c3888b8SHans Rosenfeld #define MBC_READ_REMOTE_REG 9 /* Read remote register. */ 28993c20f26SSukumar Swaminathan #define MBC_DUMP_RISC_RAM 0xa /* Dump RISC RAM command. */ 29093c20f26SSukumar Swaminathan #define MBC_LOAD_RAM_EXTENDED 0xb /* Load RAM extended. */ 29193c20f26SSukumar Swaminathan #define MBC_DUMP_RAM_EXTENDED 0xc /* Dump RAM extended. */ 292f33c1cdbSDaniel Beauregard #define MBC_WRITE_RAM_EXTENDED 0xd /* Write RAM word. */ 29393c20f26SSukumar Swaminathan #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */ 29493c20f26SSukumar Swaminathan #define MBC_SERDES_TRANSMIT_PARAMETERS 0x10 /* Serdes Xmit Parameters */ 295eb82ff87SDaniel Beauregard #define MBC_TOGGLE_INTERRUPT 0x10 /* 82XX enable/disable intr */ 29693c20f26SSukumar Swaminathan #define MBC_2300_EXECUTE_IOCB 0x12 /* ISP2300 Execute IOCB cmd */ 29793c20f26SSukumar Swaminathan #define MBC_GET_IO_STATUS 0x12 /* ISP2422 Get I/O Status */ 29893c20f26SSukumar Swaminathan #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware */ 29993c20f26SSukumar Swaminathan #define MBC_ABORT_COMMAND_IOCB 0x15 /* Abort IOCB command. */ 30093c20f26SSukumar Swaminathan #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ 30193c20f26SSukumar Swaminathan #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ 30293c20f26SSukumar Swaminathan #define MBC_RESET 0x18 /* Target reset. */ 30393c20f26SSukumar Swaminathan #define MBC_XMIT_PARM 0x19 /* Change default xmit parms */ 30493c20f26SSukumar Swaminathan #define MBC_PORT_PARAM 0x1a /* Get/set port speed parms */ 305*4c3888b8SHans Rosenfeld #define MBC_INIT_MULTIPLE_QUEUE 0x1f /* Initialize Multiple Queue */ 30693c20f26SSukumar Swaminathan #define MBC_GET_ID 0x20 /* Get loop id of ISP2200. */ 30793c20f26SSukumar Swaminathan #define MBC_GET_TIMEOUT_PARAMETERS 0x22 /* Get Timeout Parameters. */ 30893c20f26SSukumar Swaminathan #define MBC_TRACE_CONTROL 0x27 /* Trace control. */ 30993c20f26SSukumar Swaminathan #define MBC_GET_FIRMWARE_OPTIONS 0x28 /* Get firmware options */ 3105dfd244aSDaniel Beauregard #define MBC_READ_SFP 0x31 /* Read SFP. */ 31193c20f26SSukumar Swaminathan #define MBC_SET_FIRMWARE_OPTIONS 0x38 /* set firmware options */ 31293c20f26SSukumar Swaminathan #define MBC_RESET_MENLO 0x3a /* Reset Menlo. */ 313*4c3888b8SHans Rosenfeld #define MBC_FC_LED_CONFIG 0x3b /* Set/Get FC LED Config */ 3145dfd244aSDaniel Beauregard #define MBC_RESTART_MPI 0x3d /* Restart MPI. */ 3155dfd244aSDaniel Beauregard #define MBC_FLASH_ACCESS 0x3e /* Flash Access Control */ 31693c20f26SSukumar Swaminathan #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */ 31793c20f26SSukumar Swaminathan #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */ 31893c20f26SSukumar Swaminathan #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */ 31993c20f26SSukumar Swaminathan #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */ 32093c20f26SSukumar Swaminathan #define MBC_ECHO 0x44 /* ELS ECHO */ 32193c20f26SSukumar Swaminathan #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */ 32293c20f26SSukumar Swaminathan #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */ 32393c20f26SSukumar Swaminathan #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get Port Database + login */ 32493c20f26SSukumar Swaminathan #define MBC_INITIALIZE_MULTI_ID_FW 0x48 /* Initialize multi-id fw */ 325eb82ff87SDaniel Beauregard #define MBC_GET_FCF_LIST 0x50 /* Get FCF List */ 3264f8b8adcSDaniel Beauregard #define MBC_GET_DCBX_PARAMS 0x51 /* Get DCBX parameters */ 32793c20f26SSukumar Swaminathan #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */ 32893c20f26SSukumar Swaminathan #define MBC_EXECUTE_IOCB 0x54 /* 64 Bit Execute IOCB cmd. */ 32993c20f26SSukumar Swaminathan #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */ 33093c20f26SSukumar Swaminathan #define MBC_SET_PARAMETERS 0x59 /* Set RNID parameters */ 33193c20f26SSukumar Swaminathan #define MBC_GET_PARAMETERS 0x5a /* Get RNID parameters */ 33293c20f26SSukumar Swaminathan #define MBC_DATA_RATE 0x5d /* Data Rate */ 33393c20f26SSukumar Swaminathan #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ 33493c20f26SSukumar Swaminathan #define MBC_INITIATE_LIP 0x62 /* Initiate LIP */ 33593c20f26SSukumar Swaminathan #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */ 33693c20f26SSukumar Swaminathan #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */ 33793c20f26SSukumar Swaminathan #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */ 33893c20f26SSukumar Swaminathan #define MBC_TARGET_RESET 0x66 /* Target Reset. */ 33993c20f26SSukumar Swaminathan #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */ 34093c20f26SSukumar Swaminathan #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */ 34193c20f26SSukumar Swaminathan #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ 34293c20f26SSukumar Swaminathan #define MBC_GET_PORT_NAME 0x6a /* Get port name. */ 34393c20f26SSukumar Swaminathan #define MBC_GET_LINK_STATUS 0x6b /* Get Link Status. */ 34493c20f26SSukumar Swaminathan #define MBC_LIP_RESET 0x6c /* LIP reset. */ 34593c20f26SSukumar Swaminathan #define MBC_GET_STATUS_COUNTS 0x6d /* Get Link Statistics and */ 34693c20f26SSukumar Swaminathan /* Private Data Counts */ 34793c20f26SSukumar Swaminathan #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */ 34893c20f26SSukumar Swaminathan #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */ 34993c20f26SSukumar Swaminathan #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */ 35093c20f26SSukumar Swaminathan #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */ 35193c20f26SSukumar Swaminathan #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */ 35293c20f26SSukumar Swaminathan #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */ 35393c20f26SSukumar Swaminathan #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list */ 35493c20f26SSukumar Swaminathan #define MBC_INITIALIZE_IP 0x77 /* Initialize IP */ 35593c20f26SSukumar Swaminathan #define MBC_SEND_FARP_REQ_COMMAND 0x78 /* FARP request. */ 35693c20f26SSukumar Swaminathan #define MBC_UNLOAD_IP 0x79 /* Unload IP */ 3575dfd244aSDaniel Beauregard #define MBC_GET_XGMAC_STATS 0x7a /* Get XGMAC Statistics. */ 35893c20f26SSukumar Swaminathan #define MBC_GET_ID_LIST 0x7c /* Get port ID list. */ 35993c20f26SSukumar Swaminathan #define MBC_SEND_LFA_COMMAND 0x7d /* Send Loop Fabric Address */ 36093c20f26SSukumar Swaminathan #define MBC_LUN_RESET 0x7e /* Send Task mgmt LUN reset */ 3615dfd244aSDaniel Beauregard #define MBC_IDC_REQUEST 0x100 /* IDC request */ 3625dfd244aSDaniel Beauregard #define MBC_IDC_ACK 0x101 /* IDC acknowledge */ 3635dfd244aSDaniel Beauregard #define MBC_IDC_TIME_EXTEND 0x102 /* IDC extend time */ 3644f8b8adcSDaniel Beauregard #define MBC_PORT_RESET 0x120 /* Port Reset */ 3655dfd244aSDaniel Beauregard #define MBC_SET_PORT_CONFIG 0x122 /* Set port configuration */ 3665dfd244aSDaniel Beauregard #define MBC_GET_PORT_CONFIG 0x123 /* Get port configuration */ 367*4c3888b8SHans Rosenfeld #define MBC_SET_LED_CONFIG 0x125 /* Beaconing set led config */ 368*4c3888b8SHans Rosenfeld #define MBC_GET_LED_CONFIG 0x126 /* Get led config */ 369*4c3888b8SHans Rosenfeld #define MBC_GET_MD_TEMPLATE 0x129 /* Get mini dump template */ 3705dfd244aSDaniel Beauregard 3715dfd244aSDaniel Beauregard /* 3725dfd244aSDaniel Beauregard * Mbc 0x100 (IDC request) 3735dfd244aSDaniel Beauregard */ 3745dfd244aSDaniel Beauregard /* Timeout Value */ 3755dfd244aSDaniel Beauregard #define IDC_TIMEOUT_POS 8 3765dfd244aSDaniel Beauregard #define IDC_TIMEOUT_MASK (BIT_11 | BIT_10 | BIT_9 | BIT_8) 3775dfd244aSDaniel Beauregard 3785dfd244aSDaniel Beauregard /* Function Destination Selector */ 3795dfd244aSDaniel Beauregard #define IDC_FUNC_DST_MASK (BIT_5 | BIT_4) 3805dfd244aSDaniel Beauregard #define IDC_FUNC_DST_MBX3 0 3815dfd244aSDaniel Beauregard #define IDC_FUNC_DST_SP 0x10 3825dfd244aSDaniel Beauregard 3835dfd244aSDaniel Beauregard /* Function Source */ 3845dfd244aSDaniel Beauregard #define IDC_FUNC_SRC_MASK (BIT_3 | BIT_2 | BIT_1 | BIT_0) 3855dfd244aSDaniel Beauregard 3865dfd244aSDaniel Beauregard /* Information opcode */ 3875dfd244aSDaniel Beauregard #define IDC_OPC_DRV_START 0x100 3885dfd244aSDaniel Beauregard #define IDC_OPC_FLASH_ACC 0x101 3895dfd244aSDaniel Beauregard #define IDC_OPC_RESTART_MPI 0x102 390f885d00fSDaniel Beauregard #define IDC_OPC_PORT_RESET_MBC 0x120 391f885d00fSDaniel Beauregard #define IDC_OPC_SET_PORT_CONFIG_MBC 0x122 3925dfd244aSDaniel Beauregard 3935dfd244aSDaniel Beauregard /* Function Destination Mask */ 3945dfd244aSDaniel Beauregard #define IDC_FUNC_3 BIT_3 3955dfd244aSDaniel Beauregard #define IDC_FUNC_2 BIT_2 3965dfd244aSDaniel Beauregard #define IDC_FUNC_1 BIT_1 3975dfd244aSDaniel Beauregard #define IDC_FUNC_0 BIT_0 3985dfd244aSDaniel Beauregard #define IDC_FC_FUNC (BIT_3 | BIT_2) 3995dfd244aSDaniel Beauregard #define IDC_NIC_FUNC (BIT_1 | BIT_0) 4005dfd244aSDaniel Beauregard #define IDC_ALL_FUNC (IDC_FC_FUNC | IDC_NIC_FUNC) 4015dfd244aSDaniel Beauregard 4025dfd244aSDaniel Beauregard /* Requestor Id Function Type */ 4035dfd244aSDaniel Beauregard #define IDC_RIT_MASK (BIT_6 | BIT_5 | BIT_4) 4045dfd244aSDaniel Beauregard #define IDC_RIT_NIC 0 4055dfd244aSDaniel Beauregard #define IDC_RIT_FC 0x10 4065dfd244aSDaniel Beauregard 4075dfd244aSDaniel Beauregard /* Requestor Id Originator */ 4085dfd244aSDaniel Beauregard #define IDC_RIO_MASK (BIT_3 | BIT_2 | BIT_1 | BIT_0) 4095dfd244aSDaniel Beauregard #define IDC_RIO_DRV 0 4105dfd244aSDaniel Beauregard #define IDC_RIO_FW 1 4115dfd244aSDaniel Beauregard #define IDC_RIO_MPI 2 4125dfd244aSDaniel Beauregard #define IDC_RIO_DRV_APP 3 4135dfd244aSDaniel Beauregard #define IDC_RIO_QL_APP 4 4145dfd244aSDaniel Beauregard #define IDC_RIO_QL_MFG 5 4155dfd244aSDaniel Beauregard #define IDC_RIO_OTH_APP 6 4165dfd244aSDaniel Beauregard 4175dfd244aSDaniel Beauregard /* Region Code */ 4185dfd244aSDaniel Beauregard #define IDC_RC_POS 8 4195dfd244aSDaniel Beauregard #define IDC_RC_MASK 0xFF00 4205dfd244aSDaniel Beauregard 4215dfd244aSDaniel Beauregard /* Region Size in 64k blocks */ 4225dfd244aSDaniel Beauregard #define IDC_RS_POS 0 4235dfd244aSDaniel Beauregard #define IDC_RS_MASK 0xFF 4245dfd244aSDaniel Beauregard 4255dfd244aSDaniel Beauregard /* Message Source */ 4265dfd244aSDaniel Beauregard #define IDC_MSG_QLGC BIT_15 4275dfd244aSDaniel Beauregard 4285dfd244aSDaniel Beauregard /* Message Subcode */ 4295dfd244aSDaniel Beauregard #define IDC_MS_MASK (BIT_7 | BIT_6 | BIT_5 | BIT_4) 4305dfd244aSDaniel Beauregard #define IDC_MS_NONE 0x00 4315dfd244aSDaniel Beauregard #define IDC_MS_READ 0x10 4325dfd244aSDaniel Beauregard #define IDC_MS_WRITE 0x20 4335dfd244aSDaniel Beauregard #define IDC_MS_ERASE 0x30 4345dfd244aSDaniel Beauregard 4355dfd244aSDaniel Beauregard /* Marker */ 4365dfd244aSDaniel Beauregard #define IDC_MM_MASK (BIT_3 | BIT_2 | BIT_1 | BIT_0) 4375dfd244aSDaniel Beauregard #define IDC_MM_NONE 0x0 4385dfd244aSDaniel Beauregard #define IDC_MM_BEG 0x1 4395dfd244aSDaniel Beauregard #define IDC_MM_END 0x2 4405dfd244aSDaniel Beauregard #define IDC_MM_WIP 0x3 4415dfd244aSDaniel Beauregard #define IDC_MM_ABORT 0x4 4425dfd244aSDaniel Beauregard 4435dfd244aSDaniel Beauregard /* 4445dfd244aSDaniel Beauregard * Mbc 0x3e (Flash Access Control) 4455dfd244aSDaniel Beauregard */ 4465dfd244aSDaniel Beauregard #define FAC_FORCE_SEMA_LOCK BIT_15 4475dfd244aSDaniel Beauregard #define FAC_APPL_ID BIT_14 4485dfd244aSDaniel Beauregard #define FAC_WRT_PROTECT 0 4495dfd244aSDaniel Beauregard #define FAC_WRT_ENABLE 1 4505dfd244aSDaniel Beauregard #define FAC_ERASE_SECTOR 2 4515dfd244aSDaniel Beauregard #define FAC_SEMA_LOCK 3 4525dfd244aSDaniel Beauregard #define FAC_SEMA_UNLOCK 4 4535dfd244aSDaniel Beauregard #define FAC_GET_SECTOR_SIZE 5 4545dfd244aSDaniel Beauregard #define FAC_ADDR_MASK 0x3fff 45593c20f26SSukumar Swaminathan 45693c20f26SSukumar Swaminathan /* 457c1fad183SDaniel Beauregard * MBC_DIAGNOSTIC_LOOP_BACK 458c1fad183SDaniel Beauregard */ 459eb82ff87SDaniel Beauregard #define MBC_LOOPBACK_POINT_MASK 0x07 460eb82ff87SDaniel Beauregard #define MBC_LOOPBACK_POINT_10BIT 0x00 /* 2425xx */ 461eb82ff87SDaniel Beauregard #define MBC_LOOPBACK_POINT_1BIT 0x01 /* 2425xx */ 462eb82ff87SDaniel Beauregard #define MBC_LOOPBACK_POINT_INTERNAL 0x01 /* 81xx */ 463eb82ff87SDaniel Beauregard #define MBC_LOOPBACK_POINT_EXTERNAL 0x02 /* 242581xx */ 464*4c3888b8SHans Rosenfeld #define MBC_LOOPBACK_64BIT BIT_6 /* 2200 0r 2300 */ 465c1fad183SDaniel Beauregard 466c1fad183SDaniel Beauregard /* 467f885d00fSDaniel Beauregard * MBC_ECHO 468f885d00fSDaniel Beauregard */ 469f885d00fSDaniel Beauregard #define MBC_ECHO_ELS BIT_15 /* echo ELS */ 470f885d00fSDaniel Beauregard #define MBC_ECHO_64BIT BIT_6 /* 64bit DMA address used */ 471f885d00fSDaniel Beauregard 472f885d00fSDaniel Beauregard /* 473*4c3888b8SHans Rosenfeld * 81xx, 83xx 474f885d00fSDaniel Beauregard * MBC_SET_PORT_CONFIG 475f885d00fSDaniel Beauregard * MBC_GET_PORT_CONFIG 476f885d00fSDaniel Beauregard */ 477*4c3888b8SHans Rosenfeld #define LOOPBACK_MODE_FIELD_MASK 0xE 478f885d00fSDaniel Beauregard #define LOOPBACK_MODE_NONE 0x00 479*4c3888b8SHans Rosenfeld #define LOOPBACK_MODE_INTERNAL 0x04 480*4c3888b8SHans Rosenfeld #define LOOPBACK_MODE_EXTERNAL 0x08 /* 8031 */ 481f885d00fSDaniel Beauregard 482f885d00fSDaniel Beauregard /* 48393c20f26SSukumar Swaminathan * Mbc 20h (Get ID) returns the switch capabilities in mailbox7. 48493c20f26SSukumar Swaminathan * The extra bits were added with 4.00.28 MID firmware. 48593c20f26SSukumar Swaminathan */ 4865dfd244aSDaniel Beauregard #define GID_TOP_NL_PORT 0 4875dfd244aSDaniel Beauregard #define GID_TOP_FL_PORT 1 4885dfd244aSDaniel Beauregard #define GID_TOP_N_PORT 2 4895dfd244aSDaniel Beauregard #define GID_TOP_F_PORT 3 4905dfd244aSDaniel Beauregard #define GID_TOP_N_PORT_NO_TGT 4 4915dfd244aSDaniel Beauregard 4925dfd244aSDaniel Beauregard #define GID_FP_IN_ORDER BIT_8 4935dfd244aSDaniel Beauregard #define GID_FP_MAC_ADDR BIT_9 4945dfd244aSDaniel Beauregard #define GID_FP_NPIV_SUPPORT BIT_10 /* implies FDISC support */ 4955dfd244aSDaniel Beauregard #define GID_FP_VF_SUPPORT BIT_12 4965dfd244aSDaniel Beauregard #define GID_FP_SP_SUPPORT BIT_13 497*4c3888b8SHans Rosenfeld #define GID_FP_FA_WWPN BIT_14 498*4c3888b8SHans Rosenfeld 499*4c3888b8SHans Rosenfeld /* 500*4c3888b8SHans Rosenfeld * Mbc 20h (Get ID) returns the Buffer to Buffer Credits in mailbox15. 501*4c3888b8SHans Rosenfeld */ 502*4c3888b8SHans Rosenfeld #define BBCR_INITIAL_MASK 0xf 503*4c3888b8SHans Rosenfeld #define BBCR_RUNTIME_MASK 0xf 504*4c3888b8SHans Rosenfeld #define BBCR_RUNTIME_REJECT BIT_4 50593c20f26SSukumar Swaminathan 50693c20f26SSukumar Swaminathan /* 50793c20f26SSukumar Swaminathan * Driver Mailbox command definitions. 50893c20f26SSukumar Swaminathan */ 50993c20f26SSukumar Swaminathan #define MAILBOX_TOV 30 /* Default Timeout value. */ 51093c20f26SSukumar Swaminathan 51193c20f26SSukumar Swaminathan /* Mailbox command parameter structure definition. */ 51293c20f26SSukumar Swaminathan typedef struct mbx_cmd { 51393c20f26SSukumar Swaminathan uint32_t out_mb; /* Outgoing from driver */ 51493c20f26SSukumar Swaminathan uint32_t in_mb; /* Incomming from RISC */ 51593c20f26SSukumar Swaminathan uint16_t mb[MAX_MBOX_COUNT]; 51693c20f26SSukumar Swaminathan clock_t timeout; /* Timeout in seconds. */ 51793c20f26SSukumar Swaminathan } mbx_cmd_t; 51893c20f26SSukumar Swaminathan 51993c20f26SSukumar Swaminathan /* Mailbox bit definitions for out_mb and in_mb */ 52093c20f26SSukumar Swaminathan #define MBX_29 BIT_29 52193c20f26SSukumar Swaminathan #define MBX_28 BIT_28 52293c20f26SSukumar Swaminathan #define MBX_27 BIT_27 52393c20f26SSukumar Swaminathan #define MBX_26 BIT_26 52493c20f26SSukumar Swaminathan #define MBX_25 BIT_25 52593c20f26SSukumar Swaminathan #define MBX_24 BIT_24 52693c20f26SSukumar Swaminathan #define MBX_23 BIT_23 52793c20f26SSukumar Swaminathan #define MBX_22 BIT_22 52893c20f26SSukumar Swaminathan #define MBX_21 BIT_21 52993c20f26SSukumar Swaminathan #define MBX_20 BIT_20 53093c20f26SSukumar Swaminathan #define MBX_19 BIT_19 53193c20f26SSukumar Swaminathan #define MBX_18 BIT_18 53293c20f26SSukumar Swaminathan #define MBX_17 BIT_17 53393c20f26SSukumar Swaminathan #define MBX_16 BIT_16 53493c20f26SSukumar Swaminathan #define MBX_15 BIT_15 53593c20f26SSukumar Swaminathan #define MBX_14 BIT_14 53693c20f26SSukumar Swaminathan #define MBX_13 BIT_13 53793c20f26SSukumar Swaminathan #define MBX_12 BIT_12 53893c20f26SSukumar Swaminathan #define MBX_11 BIT_11 53993c20f26SSukumar Swaminathan #define MBX_10 BIT_10 54093c20f26SSukumar Swaminathan #define MBX_9 BIT_9 54193c20f26SSukumar Swaminathan #define MBX_8 BIT_8 54293c20f26SSukumar Swaminathan #define MBX_7 BIT_7 54393c20f26SSukumar Swaminathan #define MBX_6 BIT_6 54493c20f26SSukumar Swaminathan #define MBX_5 BIT_5 54593c20f26SSukumar Swaminathan #define MBX_4 BIT_4 54693c20f26SSukumar Swaminathan #define MBX_3 BIT_3 54793c20f26SSukumar Swaminathan #define MBX_2 BIT_2 54893c20f26SSukumar Swaminathan #define MBX_1 BIT_1 54993c20f26SSukumar Swaminathan #define MBX_0 BIT_0 55093c20f26SSukumar Swaminathan 55116dd44c2SDaniel Beauregard #define MBX_0_THRU_1 MBX_0|MBX_1 55216dd44c2SDaniel Beauregard #define MBX_0_THRU_2 MBX_0_THRU_1 | MBX_2 55316dd44c2SDaniel Beauregard #define MBX_0_THRU_3 MBX_0_THRU_2 | MBX_3 55416dd44c2SDaniel Beauregard #define MBX_0_THRU_4 MBX_0_THRU_3 | MBX_4 55516dd44c2SDaniel Beauregard #define MBX_0_THRU_5 MBX_0_THRU_4 | MBX_5 55616dd44c2SDaniel Beauregard #define MBX_0_THRU_6 MBX_0_THRU_5 | MBX_6 55716dd44c2SDaniel Beauregard #define MBX_0_THRU_7 MBX_0_THRU_6 | MBX_7 55816dd44c2SDaniel Beauregard #define MBX_0_THRU_8 MBX_0_THRU_7 | MBX_8 55916dd44c2SDaniel Beauregard #define MBX_0_THRU_9 MBX_0_THRU_8 | MBX_9 56016dd44c2SDaniel Beauregard #define MBX_0_THRU_10 MBX_0_THRU_9 | MBX_10 561*4c3888b8SHans Rosenfeld #define MBX_0_THRU_11 MBX_0_THRU_10 | MBX_11 562*4c3888b8SHans Rosenfeld #define MBX_0_THRU_12 MBX_0_THRU_11 | MBX_12 563*4c3888b8SHans Rosenfeld #define MBX_0_THRU_13 MBX_0_THRU_12 | MBX_13 564*4c3888b8SHans Rosenfeld #define MBX_0_THRU_14 MBX_0_THRU_13 | MBX_14 565*4c3888b8SHans Rosenfeld #define MBX_0_THRU_15 MBX_0_THRU_14 | MBX_15 566*4c3888b8SHans Rosenfeld #define MBX_0_THRU_16 MBX_0_THRU_15 | MBX_16 567*4c3888b8SHans Rosenfeld #define MBX_0_THRU_17 MBX_0_THRU_16 | MBX_17 568*4c3888b8SHans Rosenfeld #define MBX_0_THRU_18 MBX_0_THRU_17 | MBX_18 569*4c3888b8SHans Rosenfeld #define MBX_0_THRU_19 MBX_0_THRU_18 | MBX_19 570*4c3888b8SHans Rosenfeld #define MBX_0_THRU_20 MBX_0_THRU_19 | MBX_20 571*4c3888b8SHans Rosenfeld #define MBX_0_THRU_21 MBX_0_THRU_20 | MBX_21 572*4c3888b8SHans Rosenfeld #define MBX_0_THRU_22 MBX_0_THRU_21 | MBX_22 573*4c3888b8SHans Rosenfeld #define MBX_0_THRU_23 MBX_0_THRU_22 | MBX_23 574*4c3888b8SHans Rosenfeld #define MBX_0_THRU_24 MBX_0_THRU_23 | MBX_24 /* not supported by 2200 */ 575*4c3888b8SHans Rosenfeld #define MBX_0_THRU_25 MBX_0_THRU_24 | MBX_25 /* not supported by 2200 */ 57616dd44c2SDaniel Beauregard 57793c20f26SSukumar Swaminathan /* 57893c20f26SSukumar Swaminathan * Firmware state codes from get firmware state mailbox command 57993c20f26SSukumar Swaminathan */ 58093c20f26SSukumar Swaminathan #define FSTATE_CONFIG_WAIT 0 58193c20f26SSukumar Swaminathan #define FSTATE_WAIT_AL_PA 1 58293c20f26SSukumar Swaminathan #define FSTATE_WAIT_LOGIN 2 58393c20f26SSukumar Swaminathan #define FSTATE_READY 3 58493c20f26SSukumar Swaminathan #define FSTATE_LOSS_SYNC 4 58593c20f26SSukumar Swaminathan #define FSTATE_ERROR 5 58693c20f26SSukumar Swaminathan #define FSTATE_NON_PART 7 587*4c3888b8SHans Rosenfeld #define FSTATE_MPI_NIC_ERROR 0x10 58893c20f26SSukumar Swaminathan 58993c20f26SSukumar Swaminathan /* 59093c20f26SSukumar Swaminathan * Firmware options 1, 2, 3. 59193c20f26SSukumar Swaminathan */ 59293c20f26SSukumar Swaminathan #define FO1_AE_ON_LIPF8 BIT_0 59393c20f26SSukumar Swaminathan #define FO1_AE_ALL_LIP_RESET BIT_1 59493c20f26SSukumar Swaminathan #define FO1_CTIO_RETRY BIT_3 59593c20f26SSukumar Swaminathan #define FO1_DISABLE_LIP_F7_SW BIT_4 59693c20f26SSukumar Swaminathan #define FO1_DISABLE_100MS_LOS_WAIT BIT_5 59793c20f26SSukumar Swaminathan #define FO1_DISABLE_GPIO BIT_6 598*4c3888b8SHans Rosenfeld #define FO1_DISABLE_LEDS BIT_6 59993c20f26SSukumar Swaminathan #define FO1_AE_AUTO_BYPASS BIT_9 60093c20f26SSukumar Swaminathan #define FO1_ENABLE_PURE_IOCB BIT_10 60193c20f26SSukumar Swaminathan #define FO1_AE_PLOGI_RJT BIT_11 6024f8b8adcSDaniel Beauregard #define FO1_AE_IMMEDIATE_NOTIFY_IOCB BIT_11 60393c20f26SSukumar Swaminathan #define FO1_ENABLE_ABORT_SEQUENCE BIT_12 60493c20f26SSukumar Swaminathan #define FO1_AE_QUEUE_FULL BIT_13 6054f8b8adcSDaniel Beauregard #define FO1_POST_NOTIFY_ACK_IOCB_2_ATIO BIT_13 6064f8b8adcSDaniel Beauregard #define FO1_POST_NOTIFY_ACK_IOCB BIT_14 60793c20f26SSukumar Swaminathan 608*4c3888b8SHans Rosenfeld #define FO2_ENABLE_FIBRE_LITE BIT_13 609f885d00fSDaniel Beauregard #define FO2_FCOE_512_MAX_MEM_WR_BURST BIT_9 6104f8b8adcSDaniel Beauregard #define FO2_ENABLE_SELECTIVE_CLASS_2 BIT_5 61193c20f26SSukumar Swaminathan #define FO2_REV_LOOPBACK BIT_1 61293c20f26SSukumar Swaminathan #define FO2_ENABLE_ATIO_TYPE_3 BIT_0 61393c20f26SSukumar Swaminathan 6144f8b8adcSDaniel Beauregard #define FO3_NO_ABORT_IO_ON_LINK_DOWN BIT_14 6154f8b8adcSDaniel Beauregard #define FO3_HOLD_STS_FOR_ABTS_RSP BIT_12 61693c20f26SSukumar Swaminathan #define FO3_STARTUP_OPTS_VALID BIT_5 6174f8b8adcSDaniel Beauregard #define FO3_SEND_N2N_PRLI BIT_4 61893c20f26SSukumar Swaminathan #define FO3_AE_RND_ERROR BIT_1 61993c20f26SSukumar Swaminathan #define FO3_ENABLE_EMERG_IOCB BIT_0 62093c20f26SSukumar Swaminathan 62193c20f26SSukumar Swaminathan #define FO13_LESB_NO_RESET BIT_0 62293c20f26SSukumar Swaminathan 62393c20f26SSukumar Swaminathan /* 62416dd44c2SDaniel Beauregard * f/w trace opcodes - mailbox 1(bits 7-0) 62593c20f26SSukumar Swaminathan */ 62616dd44c2SDaniel Beauregard #define FTO_INSERT_TIME_STAMP 1 62716dd44c2SDaniel Beauregard #define FTO_RESERVED_2 2 62816dd44c2SDaniel Beauregard #define FTO_RESERVED_3 3 62916dd44c2SDaniel Beauregard #define FTO_EXT_TRACE_ENABLE 4 63016dd44c2SDaniel Beauregard #define FTO_EXT_TRACE_DISABLE 5 63116dd44c2SDaniel Beauregard #define FTO_FCE_TRACE_ENABLE 8 63216dd44c2SDaniel Beauregard #define FTO_FCE_TRACE_DISABLE 9 63393c20f26SSukumar Swaminathan #define FTO_FCEMAXTRACEBUF 0x840 /* max frame size */ 63493c20f26SSukumar Swaminathan 63593c20f26SSukumar Swaminathan /* 6365dfd244aSDaniel Beauregard * fw version 1 attributes defines from firmware version mailbox command 63793c20f26SSukumar Swaminathan */ 63893c20f26SSukumar Swaminathan #define FWATTRIB_EF 0x7 63993c20f26SSukumar Swaminathan #define FWATTRIB_TP 0x17 64093c20f26SSukumar Swaminathan #define FWATTRIB_IP 0x37 64193c20f26SSukumar Swaminathan #define FWATTRIB_TPX 0x117 64293c20f26SSukumar Swaminathan #define FWATTRIB_IPX 0x137 64393c20f26SSukumar Swaminathan #define FWATTRIB_FL 0x217 64493c20f26SSukumar Swaminathan #define FWATTRIB_FPX 0x317 64593c20f26SSukumar Swaminathan 64693c20f26SSukumar Swaminathan /* 6475dfd244aSDaniel Beauregard * fw version 2 attributes defines 6485dfd244aSDaniel Beauregard */ 6495dfd244aSDaniel Beauregard #define FWATTRIB2_CLASS2 BIT_0 6505dfd244aSDaniel Beauregard #define FWATTRIB2_IP BIT_1 6515dfd244aSDaniel Beauregard #define FWATTRIB2_MID BIT_2 6525dfd244aSDaniel Beauregard #define FWATTRIB2_SB2 BIT_3 6535dfd244aSDaniel Beauregard #define FWATTRIB2_T10_CRC BIT_4 6545dfd244aSDaniel Beauregard #define FWATTRIB2_VI BIT_5 6555dfd244aSDaniel Beauregard #define FWATTRIB2_MQUE BIT_6 6565dfd244aSDaniel Beauregard #define FWATTRIB2_FCOE BIT_11 6575dfd244aSDaniel Beauregard #define FWATTRIB2_EX_REL BIT_13 6585dfd244aSDaniel Beauregard 6595dfd244aSDaniel Beauregard /* 660*4c3888b8SHans Rosenfeld * Initialize Multiple Queue mailbox command options. 661*4c3888b8SHans Rosenfeld * qlc_init_req_q() options 662*4c3888b8SHans Rosenfeld */ 663*4c3888b8SHans Rosenfeld #define IMO_QUEUE_POINTER_SHADOWING BIT_13 664*4c3888b8SHans Rosenfeld #define IMO_ATIO_QUEUE_SERVICE BIT_12 665*4c3888b8SHans Rosenfeld #define IMO_MOVE_QUEUE_BASE_ADDRESS BIT_11 666*4c3888b8SHans Rosenfeld #define IMO_FORCE_DELETE BIT_9 667*4c3888b8SHans Rosenfeld #define IMO_QOS_BANDWIDTH_MODE BIT_8 668*4c3888b8SHans Rosenfeld #define IMO_QUEUE_NOT_ASSOCIATED BIT_7 669*4c3888b8SHans Rosenfeld #define IMO_INTERRUPT_HANDSHAKE BIT_6 670*4c3888b8SHans Rosenfeld #define IMO_DEVICE_FUNCTION_NUMBER BIT_5 671*4c3888b8SHans Rosenfeld #define IMO_BUS_NUMBER BIT_4 672*4c3888b8SHans Rosenfeld #define IMO_QOS_UPDATE BIT_3 673*4c3888b8SHans Rosenfeld #define IMO_REQ_RSP_Q_ADDR_TLA BIT_2 674*4c3888b8SHans Rosenfeld #define IMO_RESPONSE_Q_SERVICE BIT_1 675*4c3888b8SHans Rosenfeld #define IMO_DELETE_Q BIT_0 676*4c3888b8SHans Rosenfeld #define IMO_NONE 0 677*4c3888b8SHans Rosenfeld 678*4c3888b8SHans Rosenfeld /* 67993c20f26SSukumar Swaminathan * Diagnostic ELS ECHO parameter structure definition. 68093c20f26SSukumar Swaminathan */ 68193c20f26SSukumar Swaminathan typedef struct echo { 68293c20f26SSukumar Swaminathan uint16_t options; 68393c20f26SSukumar Swaminathan uint32_t transfer_count; 68493c20f26SSukumar Swaminathan ddi_dma_cookie_t transfer_data_address; 68593c20f26SSukumar Swaminathan ddi_dma_cookie_t receive_data_address; 68693c20f26SSukumar Swaminathan } echo_t; 68793c20f26SSukumar Swaminathan 68893c20f26SSukumar Swaminathan /* 68993c20f26SSukumar Swaminathan * LFA command structure. 69093c20f26SSukumar Swaminathan */ 69193c20f26SSukumar Swaminathan #define LFA_PAYLOAD_SIZE 38 69293c20f26SSukumar Swaminathan typedef struct lfa_cmd { 69393c20f26SSukumar Swaminathan uint8_t resp_buffer_length[2]; /* length in 16bit words. */ 69493c20f26SSukumar Swaminathan uint8_t reserved[2]; 69593c20f26SSukumar Swaminathan uint8_t resp_buffer_address[8]; 69693c20f26SSukumar Swaminathan uint8_t subcommand_length[2]; /* length in 16bit words. */ 69793c20f26SSukumar Swaminathan uint8_t reserved_1[2]; 69893c20f26SSukumar Swaminathan uint8_t addr[4]; 69993c20f26SSukumar Swaminathan uint8_t subcommand[2]; 70093c20f26SSukumar Swaminathan uint8_t payload[LFA_PAYLOAD_SIZE]; 70193c20f26SSukumar Swaminathan } lfa_cmd_t; 70293c20f26SSukumar Swaminathan 70393c20f26SSukumar Swaminathan /* Define size of Loop Position Map. */ 70493c20f26SSukumar Swaminathan #define LOOP_POSITION_MAP_SIZE 128 /* bytes */ 70593c20f26SSukumar Swaminathan 70693c20f26SSukumar Swaminathan /* 70793c20f26SSukumar Swaminathan * Port Database structure definition 70893c20f26SSukumar Swaminathan * Little endian except where noted. 70993c20f26SSukumar Swaminathan */ 71093c20f26SSukumar Swaminathan #define PORT_DATABASE_SIZE 128 /* bytes */ 71193c20f26SSukumar Swaminathan typedef struct port_database_23 { 71293c20f26SSukumar Swaminathan uint8_t options; 71393c20f26SSukumar Swaminathan uint8_t control; 71493c20f26SSukumar Swaminathan uint8_t master_state; 71593c20f26SSukumar Swaminathan uint8_t slave_state; 71693c20f26SSukumar Swaminathan uint8_t hard_address[3]; 71793c20f26SSukumar Swaminathan uint8_t rsvd; 71893c20f26SSukumar Swaminathan uint32_t port_id; 71993c20f26SSukumar Swaminathan uint8_t node_name[8]; /* Big endian. */ 72093c20f26SSukumar Swaminathan uint8_t port_name[8]; /* Big endian. */ 72193c20f26SSukumar Swaminathan uint16_t execution_throttle; 72293c20f26SSukumar Swaminathan uint16_t execution_count; 72393c20f26SSukumar Swaminathan uint8_t reset_count; 72493c20f26SSukumar Swaminathan uint8_t reserved_2; 72593c20f26SSukumar Swaminathan uint16_t resource_allocation; 72693c20f26SSukumar Swaminathan uint16_t current_allocation; 72793c20f26SSukumar Swaminathan uint16_t queue_head; 72893c20f26SSukumar Swaminathan uint16_t queue_tail; 72993c20f26SSukumar Swaminathan uint16_t transmit_execution_list_next; 73093c20f26SSukumar Swaminathan uint16_t transmit_execution_list_previous; 73193c20f26SSukumar Swaminathan uint16_t common_features; 73293c20f26SSukumar Swaminathan uint16_t total_concurrent_sequences; 73393c20f26SSukumar Swaminathan uint16_t RO_by_information_category; 73493c20f26SSukumar Swaminathan uint8_t recipient; 73593c20f26SSukumar Swaminathan uint8_t initiator; 73693c20f26SSukumar Swaminathan uint16_t receive_data_size; 73793c20f26SSukumar Swaminathan uint16_t concurrent_sequences; 73893c20f26SSukumar Swaminathan uint16_t open_sequences_per_exchange; 73993c20f26SSukumar Swaminathan uint16_t lun_abort_flags; 74093c20f26SSukumar Swaminathan uint16_t lun_stop_flags; 74193c20f26SSukumar Swaminathan uint16_t stop_queue_head; 74293c20f26SSukumar Swaminathan uint16_t stop_queue_tail; 74393c20f26SSukumar Swaminathan uint16_t port_retry_timer; 74493c20f26SSukumar Swaminathan uint16_t next_sequence_id; 74593c20f26SSukumar Swaminathan uint16_t frame_count; 74693c20f26SSukumar Swaminathan uint16_t PRLI_payload_length; 74793c20f26SSukumar Swaminathan uint16_t PRLI_service_parameter_word_0; /* Big endian */ 74893c20f26SSukumar Swaminathan /* Bits 15-0 of word 0 */ 74993c20f26SSukumar Swaminathan uint16_t PRLI_service_parameter_word_3; /* Big endian */ 75093c20f26SSukumar Swaminathan /* Bits 15-0 of word 3 */ 75193c20f26SSukumar Swaminathan uint16_t loop_id; 75293c20f26SSukumar Swaminathan uint16_t extended_lun_info_list_pointer; 75393c20f26SSukumar Swaminathan uint16_t extended_lun_stop_list_pointer; 75493c20f26SSukumar Swaminathan } port_database_23_t; 75593c20f26SSukumar Swaminathan 75693c20f26SSukumar Swaminathan typedef struct port_database_24 { 75793c20f26SSukumar Swaminathan uint16_t flags; 75893c20f26SSukumar Swaminathan uint8_t current_login_state; 75993c20f26SSukumar Swaminathan uint8_t last_stable_login_state; 76093c20f26SSukumar Swaminathan uint8_t hard_address[3]; 76193c20f26SSukumar Swaminathan uint8_t rsvd; 76293c20f26SSukumar Swaminathan uint8_t port_id[3]; 76393c20f26SSukumar Swaminathan uint8_t sequence_id; 76493c20f26SSukumar Swaminathan uint16_t port_retry_timer; 76593c20f26SSukumar Swaminathan uint16_t n_port_handle; 76693c20f26SSukumar Swaminathan uint16_t receive_data_size; 76793c20f26SSukumar Swaminathan uint8_t reserved_1[2]; 76893c20f26SSukumar Swaminathan uint16_t PRLI_service_parameter_word_0; /* Big endian */ 76993c20f26SSukumar Swaminathan /* Bits 15-0 of word 0 */ 77093c20f26SSukumar Swaminathan uint16_t PRLI_service_parameter_word_3; /* Big endian */ 77193c20f26SSukumar Swaminathan /* Bits 15-0 of word 3 */ 77293c20f26SSukumar Swaminathan uint8_t port_name[8]; /* Big endian. */ 77393c20f26SSukumar Swaminathan uint8_t node_name[8]; /* Big endian. */ 77493c20f26SSukumar Swaminathan uint8_t reserved_2[24]; 77593c20f26SSukumar Swaminathan } port_database_24_t; 77693c20f26SSukumar Swaminathan 77793c20f26SSukumar Swaminathan /* 77893c20f26SSukumar Swaminathan * Port database slave/master/current_login/ast_stable_login states 77993c20f26SSukumar Swaminathan */ 78093c20f26SSukumar Swaminathan #define PD_STATE_DISCOVERY 0 78193c20f26SSukumar Swaminathan #define PD_STATE_WAIT_DISCOVERY_ACK 1 78293c20f26SSukumar Swaminathan #define PD_STATE_PORT_LOGIN 2 78393c20f26SSukumar Swaminathan #define PD_STATE_WAIT_PORT_LOGIN_ACK 3 78416dd44c2SDaniel Beauregard #define PD_STATE_PLOGI_PENDING 3 78593c20f26SSukumar Swaminathan #define PD_STATE_PROCESS_LOGIN 4 78616dd44c2SDaniel Beauregard #define PD_STATE_PLOGI_COMPLETED 4 78793c20f26SSukumar Swaminathan #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5 78816dd44c2SDaniel Beauregard #define PD_STATE_PRLI_PENDING 5 78993c20f26SSukumar Swaminathan #define PD_STATE_PORT_LOGGED_IN 6 79016dd44c2SDaniel Beauregard #define PD_STATE_PLOGI_PRLI_COMPLETED 6 79193c20f26SSukumar Swaminathan #define PD_STATE_PORT_UNAVAILABLE 7 79293c20f26SSukumar Swaminathan #define PD_STATE_PROCESS_LOGOUT 8 79393c20f26SSukumar Swaminathan #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9 79493c20f26SSukumar Swaminathan #define PD_STATE_PORT_LOGOUT 10 79593c20f26SSukumar Swaminathan #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11 79693c20f26SSukumar Swaminathan 79793c20f26SSukumar Swaminathan #define PD_PORT_LOGIN(tq) \ 79893c20f26SSukumar Swaminathan (tq->master_state == PD_STATE_PROCESS_LOGIN || \ 79993c20f26SSukumar Swaminathan tq->master_state == PD_STATE_PORT_LOGGED_IN || \ 80093c20f26SSukumar Swaminathan tq->slave_state == PD_STATE_PROCESS_LOGIN || \ 80193c20f26SSukumar Swaminathan tq->slave_state == PD_STATE_PORT_LOGGED_IN) 80293c20f26SSukumar Swaminathan 80393c20f26SSukumar Swaminathan /* 80493c20f26SSukumar Swaminathan * ql_login_lport() options 80593c20f26SSukumar Swaminathan */ 80693c20f26SSukumar Swaminathan #define LLF_NONE 0 80793c20f26SSukumar Swaminathan #define LLF_PLOGI BIT_0 /* unconditional PLOGI */ 80893c20f26SSukumar Swaminathan 80993c20f26SSukumar Swaminathan /* 81093c20f26SSukumar Swaminathan * ql_login_fport() options 81193c20f26SSukumar Swaminathan */ 81293c20f26SSukumar Swaminathan #define LFF_NONE 0 81393c20f26SSukumar Swaminathan #define LFF_NO_PLOGI BIT_0 81493c20f26SSukumar Swaminathan #define LFF_NO_PRLI BIT_1 81593c20f26SSukumar Swaminathan 81693c20f26SSukumar Swaminathan /* 81793c20f26SSukumar Swaminathan * ql_get_port_database() options 81893c20f26SSukumar Swaminathan */ 81993c20f26SSukumar Swaminathan #define PDF_NONE 0 82093c20f26SSukumar Swaminathan #define PDF_PLOGI BIT_0 82193c20f26SSukumar Swaminathan #define PDF_ADISC BIT_1 82293c20f26SSukumar Swaminathan 82393c20f26SSukumar Swaminathan /* 824c1fad183SDaniel Beauregard * Set/Get Port Configuration MBC 825c1fad183SDaniel Beauregard */ 826c1fad183SDaniel Beauregard #define LINK_CONFIG_PAUSE_MASK (BIT_6 | BIT_5) 827c1fad183SDaniel Beauregard #define LINK_CONFIG_PAUSE_DISABLE 0x00 828c1fad183SDaniel Beauregard #define LINK_CONFIG_PAUSE_STD_ETH 0x01 829c1fad183SDaniel Beauregard #define LINK_CONFIG_PAUSE_PER_PRIO 0x02 830c1fad183SDaniel Beauregard 831c1fad183SDaniel Beauregard #define LINK_CONFIG_DCBX_ENA BIT_4 832c1fad183SDaniel Beauregard 833c1fad183SDaniel Beauregard #define LINK_CONFIG_LB_MODE_MASK (BIT_3 | BIT_2 | BIT_1) 834c1fad183SDaniel Beauregard #define LINK_CONFIG_LB_NONE 0x00 835c1fad183SDaniel Beauregard #define LINK_CONFIG_LB_INTERNAL 0x02 836c1fad183SDaniel Beauregard 837c1fad183SDaniel Beauregard #define LINK_CONFIG2_BP_TRAIN_ENA BIT_15 838c1fad183SDaniel Beauregard #define LINK_CONFIG2_BP_AUTO_NEGO_ENA BIT_14 839c1fad183SDaniel Beauregard #define LINK_CONFIG2_JUMBO_FRM_ENA BIT_0 840c1fad183SDaniel Beauregard 841c1fad183SDaniel Beauregard /* 842eb82ff87SDaniel Beauregard * 843eb82ff87SDaniel Beauregard */ 844eb82ff87SDaniel Beauregard #define FCF_LIST_RETURN_ALL BIT_0 845eb82ff87SDaniel Beauregard #define FCF_LIST_RETURN_ONE BIT_1 846eb82ff87SDaniel Beauregard 847eb82ff87SDaniel Beauregard typedef struct fcf_desc { 848eb82ff87SDaniel Beauregard uint16_t options; 849eb82ff87SDaniel Beauregard uint16_t fcf_index; 850eb82ff87SDaniel Beauregard uint32_t buffer_size; 851eb82ff87SDaniel Beauregard } ql_fcf_list_desc_t; 852eb82ff87SDaniel Beauregard 853eb82ff87SDaniel Beauregard /* 85493c20f26SSukumar Swaminathan * Global Data in ql_mbx.c source file. 85593c20f26SSukumar Swaminathan */ 85693c20f26SSukumar Swaminathan 85793c20f26SSukumar Swaminathan /* 85893c20f26SSukumar Swaminathan * Global Function Prototypes in ql_mbx.c source file. 85993c20f26SSukumar Swaminathan */ 86093c20f26SSukumar Swaminathan int ql_initialize_ip(ql_adapter_state_t *); 86193c20f26SSukumar Swaminathan int ql_shutdown_ip(ql_adapter_state_t *); 86293c20f26SSukumar Swaminathan int ql_online_selftest(ql_adapter_state_t *); 8634f8b8adcSDaniel Beauregard int ql_loop_back(ql_adapter_state_t *, uint16_t, lbp_t *, uint32_t, uint32_t); 8644f8b8adcSDaniel Beauregard int ql_echo(ql_adapter_state_t *, uint16_t, echo_t *); 86593c20f26SSukumar Swaminathan int ql_send_change_request(ql_adapter_state_t *, uint16_t); 86693c20f26SSukumar Swaminathan int ql_send_lfa(ql_adapter_state_t *, lfa_cmd_t *); 867*4c3888b8SHans Rosenfeld int ql_clear_aca(ql_adapter_state_t *, ql_tgt_t *, ql_lun_t *); 86893c20f26SSukumar Swaminathan int ql_target_reset(ql_adapter_state_t *, ql_tgt_t *, uint16_t); 86993c20f26SSukumar Swaminathan int ql_abort_target(ql_adapter_state_t *, ql_tgt_t *, uint16_t); 870*4c3888b8SHans Rosenfeld int ql_lun_reset(ql_adapter_state_t *, ql_tgt_t *, ql_lun_t *); 871*4c3888b8SHans Rosenfeld int ql_clear_task_set(ql_adapter_state_t *, ql_tgt_t *, ql_lun_t *); 872*4c3888b8SHans Rosenfeld int ql_abort_task_set(ql_adapter_state_t *, ql_tgt_t *, ql_lun_t *); 87393c20f26SSukumar Swaminathan int ql_loop_port_bypass(ql_adapter_state_t *, ql_tgt_t *); 87493c20f26SSukumar Swaminathan int ql_loop_port_enable(ql_adapter_state_t *, ql_tgt_t *); 87593c20f26SSukumar Swaminathan int ql_login_lport(ql_adapter_state_t *, ql_tgt_t *, uint16_t, uint16_t); 87693c20f26SSukumar Swaminathan int ql_login_fport(ql_adapter_state_t *, ql_tgt_t *, uint16_t, uint16_t, 87793c20f26SSukumar Swaminathan ql_mbx_data_t *); 87893c20f26SSukumar Swaminathan int ql_logout_fabric_port(ql_adapter_state_t *, ql_tgt_t *); 87993c20f26SSukumar Swaminathan int ql_log_iocb(ql_adapter_state_t *, ql_tgt_t *, uint16_t, uint16_t, 88093c20f26SSukumar Swaminathan ql_mbx_data_t *); 88193c20f26SSukumar Swaminathan int ql_get_port_database(ql_adapter_state_t *, ql_tgt_t *, uint8_t); 88293c20f26SSukumar Swaminathan int ql_get_loop_position_map(ql_adapter_state_t *, size_t, caddr_t); 88393c20f26SSukumar Swaminathan int ql_set_rnid_params(ql_adapter_state_t *, size_t, caddr_t); 88493c20f26SSukumar Swaminathan int ql_send_rnid_els(ql_adapter_state_t *, uint16_t, uint8_t, size_t, caddr_t); 88593c20f26SSukumar Swaminathan int ql_get_rnid_params(ql_adapter_state_t *, size_t, caddr_t); 88693c20f26SSukumar Swaminathan int ql_get_link_status(ql_adapter_state_t *, uint16_t, size_t, caddr_t, 88793c20f26SSukumar Swaminathan uint8_t); 88893c20f26SSukumar Swaminathan int ql_get_status_counts(ql_adapter_state_t *, uint16_t, size_t, caddr_t, 88993c20f26SSukumar Swaminathan uint8_t); 89093c20f26SSukumar Swaminathan int ql_reset_link_status(ql_adapter_state_t *); 89193c20f26SSukumar Swaminathan int ql_loop_reset(ql_adapter_state_t *); 89293c20f26SSukumar Swaminathan int ql_initiate_lip(ql_adapter_state_t *); 89393c20f26SSukumar Swaminathan int ql_full_login_lip(ql_adapter_state_t *); 89493c20f26SSukumar Swaminathan int ql_lip_reset(ql_adapter_state_t *, uint16_t); 89593c20f26SSukumar Swaminathan int ql_abort_command(ql_adapter_state_t *, ql_srb_t *); 89693c20f26SSukumar Swaminathan int ql_verify_checksum(ql_adapter_state_t *); 89793c20f26SSukumar Swaminathan int ql_get_id_list(ql_adapter_state_t *, caddr_t, uint32_t, ql_mbx_data_t *); 89893c20f26SSukumar Swaminathan int ql_wrt_risc_ram(ql_adapter_state_t *, uint32_t, uint64_t, uint32_t); 89993c20f26SSukumar Swaminathan int ql_rd_risc_ram(ql_adapter_state_t *, uint32_t, uint64_t, uint32_t); 900f33c1cdbSDaniel Beauregard int ql_wrt_risc_ram_word(ql_adapter_state_t *, uint32_t, uint32_t); 901f33c1cdbSDaniel Beauregard int ql_rd_risc_ram_word(ql_adapter_state_t *, uint32_t, uint32_t *); 90293c20f26SSukumar Swaminathan int ql_issue_mbx_iocb(ql_adapter_state_t *, caddr_t, uint32_t); 90393c20f26SSukumar Swaminathan int ql_mbx_wrap_test(ql_adapter_state_t *, ql_mbx_data_t *); 90493c20f26SSukumar Swaminathan int ql_execute_fw(ql_adapter_state_t *); 90593c20f26SSukumar Swaminathan int ql_get_firmware_option(ql_adapter_state_t *, ql_mbx_data_t *); 90693c20f26SSukumar Swaminathan int ql_set_firmware_option(ql_adapter_state_t *, ql_mbx_data_t *); 90793c20f26SSukumar Swaminathan int ql_init_firmware(ql_adapter_state_t *); 90893c20f26SSukumar Swaminathan int ql_get_firmware_state(ql_adapter_state_t *, ql_mbx_data_t *); 90993c20f26SSukumar Swaminathan int ql_get_adapter_id(ql_adapter_state_t *, ql_mbx_data_t *); 910eb82ff87SDaniel Beauregard int ql_get_fw_version(ql_adapter_state_t *, ql_mbx_data_t *, uint16_t); 91193c20f26SSukumar Swaminathan int ql_data_rate(ql_adapter_state_t *, ql_mbx_data_t *); 912*4c3888b8SHans Rosenfeld int ql_diag_loopback(ql_adapter_state_t *, caddr_t, uint32_t, uint16_t, 913*4c3888b8SHans Rosenfeld uint32_t, ql_mbx_data_t *); 914*4c3888b8SHans Rosenfeld int ql_diag_echo(ql_adapter_state_t *, caddr_t, uint32_t, uint16_t, 91593c20f26SSukumar Swaminathan ql_mbx_data_t *); 916*4c3888b8SHans Rosenfeld int ql_diag_beacon(ql_adapter_state_t *, int, ql_mbx_data_t *); 91793c20f26SSukumar Swaminathan int ql_serdes_param(ql_adapter_state_t *, ql_mbx_data_t *); 91893c20f26SSukumar Swaminathan int ql_get_timeout_parameters(ql_adapter_state_t *, uint16_t *); 91993c20f26SSukumar Swaminathan int ql_stop_firmware(ql_adapter_state_t *); 92093c20f26SSukumar Swaminathan int ql_read_sfp(ql_adapter_state_t *, dma_mem_t *, uint16_t, uint16_t); 92193c20f26SSukumar Swaminathan int ql_iidma_rate(ql_adapter_state_t *, uint16_t, uint32_t *, uint32_t); 922*4c3888b8SHans Rosenfeld int ql_fw_etrace(ql_adapter_state_t *, dma_mem_t *, uint16_t, ql_mbx_data_t *); 92393c20f26SSukumar Swaminathan int ql_reset_menlo(ql_adapter_state_t *, ql_mbx_data_t *, uint16_t); 9245dfd244aSDaniel Beauregard int ql_restart_mpi(ql_adapter_state_t *); 9255dfd244aSDaniel Beauregard int ql_idc_request(ql_adapter_state_t *, ql_mbx_data_t *); 9265dfd244aSDaniel Beauregard int ql_idc_ack(ql_adapter_state_t *); 927*4c3888b8SHans Rosenfeld int ql_idc_time_extend(ql_adapter_state_t *); 9284f8b8adcSDaniel Beauregard int ql_port_reset(ql_adapter_state_t *); 9295dfd244aSDaniel Beauregard int ql_set_port_config(ql_adapter_state_t *, ql_mbx_data_t *); 9305dfd244aSDaniel Beauregard int ql_get_port_config(ql_adapter_state_t *, ql_mbx_data_t *); 9315dfd244aSDaniel Beauregard int ql_flash_access(ql_adapter_state_t *, uint16_t, uint32_t, uint32_t, 9325dfd244aSDaniel Beauregard uint32_t *); 9335dfd244aSDaniel Beauregard int ql_get_xgmac_stats(ql_adapter_state_t *, size_t, caddr_t); 9344f8b8adcSDaniel Beauregard int ql_get_dcbx_params(ql_adapter_state_t *, uint32_t, caddr_t); 935eb82ff87SDaniel Beauregard int ql_get_fcf_list_mbx(ql_adapter_state_t *, ql_fcf_list_desc_t *, caddr_t); 936eb82ff87SDaniel Beauregard int ql_get_resource_cnts(ql_adapter_state_t *, ql_mbx_data_t *); 937eb82ff87SDaniel Beauregard int ql_toggle_interrupt(ql_adapter_state_t *, uint16_t); 938*4c3888b8SHans Rosenfeld int ql_get_md_template(ql_adapter_state_t *, dma_mem_t *, ql_mbx_data_t *, 939*4c3888b8SHans Rosenfeld uint32_t, uint16_t); 940*4c3888b8SHans Rosenfeld int ql_load_flash_image(ql_adapter_state_t *); 941*4c3888b8SHans Rosenfeld int ql_set_led_config(ql_adapter_state_t *, ql_mbx_data_t *); 942*4c3888b8SHans Rosenfeld int ql_get_led_config(ql_adapter_state_t *, ql_mbx_data_t *); 943*4c3888b8SHans Rosenfeld int ql_led_config(ql_adapter_state_t *, ql_mbx_data_t *); 944*4c3888b8SHans Rosenfeld int ql_write_remote_reg(ql_adapter_state_t *, uint32_t, uint32_t); 945*4c3888b8SHans Rosenfeld int ql_read_remote_reg(ql_adapter_state_t *, uint32_t, uint32_t *); 946*4c3888b8SHans Rosenfeld int ql_get_temp(ql_adapter_state_t *, ql_mbx_data_t *mr); 947*4c3888b8SHans Rosenfeld int ql_write_serdes(ql_adapter_state_t *, ql_mbx_data_t *); 948*4c3888b8SHans Rosenfeld int ql_read_serdes(ql_adapter_state_t *, ql_mbx_data_t *); 949*4c3888b8SHans Rosenfeld 95016dd44c2SDaniel Beauregard /* 95116dd44c2SDaniel Beauregard * Mailbox command table initializer 95216dd44c2SDaniel Beauregard */ 95316dd44c2SDaniel Beauregard #define MBOX_CMD_TABLE() \ 95416dd44c2SDaniel Beauregard { \ 955*4c3888b8SHans Rosenfeld {MBC_LOAD_RAM, "MBC_LOAD_RAM or MBC_WRITE_REMOTE_REG"}, \ 95616dd44c2SDaniel Beauregard {MBC_EXECUTE_FIRMWARE, "MBC_EXECUTE_FIRMWARE"}, \ 957*4c3888b8SHans Rosenfeld {MBC_DUMP_RAM, \ 958*4c3888b8SHans Rosenfeld "MBC_DUMP_RAM, MBC_LOAD_FLASH_IMAGE or MBC_WRITE_SERDES_REG"}, \ 959*4c3888b8SHans Rosenfeld {MBC_WRITE_RAM_WORD, "MBC_WRITE_RAM_WORD or MBC_READ_SERDES_REG"},\ 960*4c3888b8SHans Rosenfeld {MBC_READ_RAM_WORD, "MBC_READ_RAM_WORD or MBC_MPI_RAM"}, \ 96116dd44c2SDaniel Beauregard {MBC_MAILBOX_REGISTER_TEST, "MBC_MAILBOX_REGISTER_TEST"}, \ 96216dd44c2SDaniel Beauregard {MBC_VERIFY_CHECKSUM, "MBC_VERIFY_CHECKSUM"}, \ 96316dd44c2SDaniel Beauregard {MBC_ABOUT_FIRMWARE, "MBC_ABOUT_FIRMWARE"}, \ 964*4c3888b8SHans Rosenfeld {MBC_LOAD_RISC_RAM, "MBC_LOAD_RISC_RAM or MBC_READ_REMOTE_REG"},\ 96516dd44c2SDaniel Beauregard {MBC_DUMP_RISC_RAM, "MBC_DUMP_RISC_RAM"}, \ 96616dd44c2SDaniel Beauregard {MBC_LOAD_RAM_EXTENDED, "MBC_LOAD_RAM_EXTENDED"}, \ 96716dd44c2SDaniel Beauregard {MBC_DUMP_RAM_EXTENDED, "MBC_DUMP_RAM_EXTENDED"}, \ 968f33c1cdbSDaniel Beauregard {MBC_WRITE_RAM_EXTENDED, "MBC_WRITE_RAM_EXTENDED"}, \ 96916dd44c2SDaniel Beauregard {MBC_READ_RAM_EXTENDED, "MBC_READ_RAM_EXTENDED"}, \ 970eb82ff87SDaniel Beauregard {MBC_SERDES_TRANSMIT_PARAMETERS, \ 971eb82ff87SDaniel Beauregard "MBC_SERDES_TRANSMIT_PARAMETERS or MBC_TOGGLE_INTERRUPT"},\ 97216dd44c2SDaniel Beauregard {MBC_2300_EXECUTE_IOCB, "MBC_2300_EXECUTE_IOCB"}, \ 97316dd44c2SDaniel Beauregard {MBC_GET_IO_STATUS, "MBC_GET_IO_STATUS"}, \ 97416dd44c2SDaniel Beauregard {MBC_STOP_FIRMWARE, "MBC_STOP_FIRMWARE"}, \ 97516dd44c2SDaniel Beauregard {MBC_ABORT_COMMAND_IOCB, "MBC_ABORT_COMMAND_IOCB"}, \ 97616dd44c2SDaniel Beauregard {MBC_ABORT_DEVICE, "MBC_ABORT_DEVICE"}, \ 97716dd44c2SDaniel Beauregard {MBC_ABORT_TARGET, "MBC_ABORT_TARGET"}, \ 97816dd44c2SDaniel Beauregard {MBC_RESET, "MBC_RESET"}, \ 97916dd44c2SDaniel Beauregard {MBC_XMIT_PARM, "MBC_XMIT_PARM"}, \ 98016dd44c2SDaniel Beauregard {MBC_PORT_PARAM, "MBC_PORT_PARAM"}, \ 981*4c3888b8SHans Rosenfeld {MBC_INIT_MULTIPLE_QUEUE, "MBC_INIT_MULTIPLE_QUEUE"}, \ 98216dd44c2SDaniel Beauregard {MBC_GET_ID, "MBC_GET_ID"}, \ 98316dd44c2SDaniel Beauregard {MBC_GET_TIMEOUT_PARAMETERS, "MBC_GET_TIMEOUT_PARAMETERS"}, \ 98416dd44c2SDaniel Beauregard {MBC_TRACE_CONTROL, "MBC_TRACE_CONTROL"}, \ 98516dd44c2SDaniel Beauregard {MBC_GET_FIRMWARE_OPTIONS, "MBC_GET_FIRMWARE_OPTIONS"}, \ 9865dfd244aSDaniel Beauregard {MBC_READ_SFP, "MBC_READ_SFP"}, \ 98716dd44c2SDaniel Beauregard {MBC_SET_FIRMWARE_OPTIONS, "MBC_SET_FIRMWARE_OPTIONS"}, \ 9885dfd244aSDaniel Beauregard {MBC_RESET_MENLO, "MBC_RESET_MENLO"}, \ 989*4c3888b8SHans Rosenfeld {MBC_FC_LED_CONFIG, "MBC_FC_LED_CONFIG"}, \ 9905dfd244aSDaniel Beauregard {MBC_RESTART_MPI, "MBC_RESTART_MPI"}, \ 9915dfd244aSDaniel Beauregard {MBC_FLASH_ACCESS, "MBC_FLASH_ACCESS"}, \ 99216dd44c2SDaniel Beauregard {MBC_LOOP_PORT_BYPASS, "MBC_LOOP_PORT_BYPASS"}, \ 99316dd44c2SDaniel Beauregard {MBC_LOOP_PORT_ENABLE, "MBC_LOOP_PORT_ENABLE"}, \ 99416dd44c2SDaniel Beauregard {MBC_GET_RESOURCE_COUNTS, "MBC_GET_RESOURCE_COUNTS"}, \ 99516dd44c2SDaniel Beauregard {MBC_NON_PARTICIPATE, "MBC_NON_PARTICIPATE"}, \ 99616dd44c2SDaniel Beauregard {MBC_ECHO, "MBC_ECHO"}, \ 99716dd44c2SDaniel Beauregard {MBC_DIAGNOSTIC_LOOP_BACK, "MBC_DIAGNOSTIC_LOOP_BACK"}, \ 99816dd44c2SDaniel Beauregard {MBC_ONLINE_SELF_TEST, "MBC_ONLINE_SELF_TEST"}, \ 99916dd44c2SDaniel Beauregard {MBC_ENHANCED_GET_PORT_DATABASE, "MBC_ENHANCED_GET_PORT_DATABASE"},\ 100016dd44c2SDaniel Beauregard {MBC_INITIALIZE_MULTI_ID_FW, "MBC_INITIALIZE_MULTI_ID_FW"}, \ 1001eb82ff87SDaniel Beauregard {MBC_GET_FCF_LIST, "MBC_GET_FCF_LIST"}, \ 10024f8b8adcSDaniel Beauregard {MBC_GET_DCBX_PARAMS, "MBC_GET_DCBX_PARAMS"}, \ 100316dd44c2SDaniel Beauregard {MBC_RESET_LINK_STATUS, "MBC_RESET_LINK_STATUS"}, \ 100416dd44c2SDaniel Beauregard {MBC_EXECUTE_IOCB, "MBC_EXECUTE_IOCB"}, \ 100516dd44c2SDaniel Beauregard {MBC_SEND_RNID_ELS, "MBC_SEND_RNID_ELS"}, \ 100616dd44c2SDaniel Beauregard {MBC_SET_PARAMETERS, "MBC_SET_PARAMETERS"}, \ 100716dd44c2SDaniel Beauregard {MBC_GET_PARAMETERS, "MBC_GET_PARAMETERS"}, \ 100816dd44c2SDaniel Beauregard {MBC_DATA_RATE, "MBC_DATA_RATE"}, \ 100916dd44c2SDaniel Beauregard {MBC_INITIALIZE_FIRMWARE, "MBC_INITIALIZE_FIRMWARE"}, \ 101016dd44c2SDaniel Beauregard {MBC_INITIATE_LIP, "MBC_INITIATE_LIP"}, \ 101116dd44c2SDaniel Beauregard {MBC_GET_FC_AL_POSITION_MAP, "MBC_GET_FC_AL_POSITION_MAP"}, \ 101216dd44c2SDaniel Beauregard {MBC_GET_PORT_DATABASE, "MBC_GET_PORT_DATABASE"}, \ 101316dd44c2SDaniel Beauregard {MBC_CLEAR_ACA, "MBC_CLEAR_ACA"}, \ 101416dd44c2SDaniel Beauregard {MBC_TARGET_RESET, "MBC_TARGET_RESET"}, \ 101516dd44c2SDaniel Beauregard {MBC_CLEAR_TASK_SET, "MBC_CLEAR_TASK_SET"}, \ 101616dd44c2SDaniel Beauregard {MBC_ABORT_TASK_SET, "MBC_ABORT_TASK_SET"}, \ 101716dd44c2SDaniel Beauregard {MBC_GET_FIRMWARE_STATE, "MBC_GET_FIRMWARE_STATE"}, \ 101816dd44c2SDaniel Beauregard {MBC_GET_PORT_NAME, "MBC_GET_PORT_NAME"}, \ 101916dd44c2SDaniel Beauregard {MBC_GET_LINK_STATUS, "MBC_GET_LINK_STATUS"}, \ 102016dd44c2SDaniel Beauregard {MBC_LIP_RESET, "MBC_LIP_RESET"}, \ 102116dd44c2SDaniel Beauregard {MBC_GET_STATUS_COUNTS, "MBC_GET_STATUS_COUNTS"}, \ 102216dd44c2SDaniel Beauregard {MBC_SEND_SNS_COMMAND, "MBC_SEND_SNS_COMMAND"}, \ 102316dd44c2SDaniel Beauregard {MBC_LOGIN_FABRIC_PORT, "MBC_LOGIN_FABRIC_PORT"}, \ 102416dd44c2SDaniel Beauregard {MBC_SEND_CHANGE_REQUEST, "MBC_SEND_CHANGE_REQUEST"}, \ 102516dd44c2SDaniel Beauregard {MBC_LOGOUT_FABRIC_PORT, "MBC_LOGOUT_FABRIC_PORT"}, \ 102616dd44c2SDaniel Beauregard {MBC_LIP_FULL_LOGIN, "MBC_LIP_FULL_LOGIN"}, \ 102716dd44c2SDaniel Beauregard {MBC_LOGIN_LOOP_PORT, "MBC_LOGIN_LOOP_PORT"}, \ 102816dd44c2SDaniel Beauregard {MBC_PORT_NODE_NAME_LIST, "MBC_PORT_NODE_NAME_LIST"}, \ 102916dd44c2SDaniel Beauregard {MBC_INITIALIZE_IP, "MBC_INITIALIZE_IP"}, \ 103016dd44c2SDaniel Beauregard {MBC_SEND_FARP_REQ_COMMAND, "MBC_SEND_FARP_REQ_COMMAND"}, \ 103116dd44c2SDaniel Beauregard {MBC_UNLOAD_IP, "MBC_UNLOAD_IP"}, \ 10325dfd244aSDaniel Beauregard {MBC_GET_XGMAC_STATS, "MBC_GET_XGMAC_STATS"}, \ 103316dd44c2SDaniel Beauregard {MBC_GET_ID_LIST, "MBC_GET_ID_LIST"}, \ 103416dd44c2SDaniel Beauregard {MBC_SEND_LFA_COMMAND, "MBC_SEND_LFA_COMMAND"}, \ 103516dd44c2SDaniel Beauregard {MBC_LUN_RESET, "MBC_LUN_RESET"}, \ 10365dfd244aSDaniel Beauregard {MBC_IDC_REQUEST, "MBC_IDC_REQUEST"}, \ 10375dfd244aSDaniel Beauregard {MBC_IDC_ACK, "MBC_IDC_ACK"}, \ 10385dfd244aSDaniel Beauregard {MBC_IDC_TIME_EXTEND, "MBC_IDC_TIME_EXTEND"}, \ 10394f8b8adcSDaniel Beauregard {MBC_PORT_RESET, "MBC_PORT_RESET"}, \ 10405dfd244aSDaniel Beauregard {MBC_SET_PORT_CONFIG, "MBC_SET_PORT_CONFIG"}, \ 10415dfd244aSDaniel Beauregard {MBC_GET_PORT_CONFIG, "MBC_GET_PORT_CONFIG"}, \ 1042*4c3888b8SHans Rosenfeld {MBC_SET_LED_CONFIG, "MBC_SET_LED_CONFIG"}, \ 1043*4c3888b8SHans Rosenfeld {MBC_GET_LED_CONFIG, "MBC_GET_LED_CONFIG"}, \ 1044*4c3888b8SHans Rosenfeld {MBC_GET_MD_TEMPLATE, "MBC_GET_MD_TEMPLATE"}, \ 1045c92b35bbSToomas Soome {0, "Unsupported"} \ 104616dd44c2SDaniel Beauregard } 104793c20f26SSukumar Swaminathan 104893c20f26SSukumar Swaminathan #ifdef __cplusplus 104993c20f26SSukumar Swaminathan } 105093c20f26SSukumar Swaminathan #endif 105193c20f26SSukumar Swaminathan 105293c20f26SSukumar Swaminathan #endif /* _QL_MBX_H */ 1053