1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* Copyright 2008 QLogic Corporation */ 23 24 /* 25 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 26 * Use is subject to license terms. 27 */ 28 29 #ifndef _QL_MBX_H 30 #define _QL_MBX_H 31 32 33 /* 34 * ISP2xxx Solaris Fibre Channel Adapter (FCA) driver header file. 35 * 36 * *********************************************************************** 37 * * ** 38 * * NOTICE ** 39 * * COPYRIGHT (C) 1996-2008 QLOGIC CORPORATION ** 40 * * ALL RIGHTS RESERVED ** 41 * * ** 42 * *********************************************************************** 43 * 44 */ 45 46 #ifdef __cplusplus 47 extern "C" { 48 #endif 49 50 /* 51 * ISP mailbox Self-Test status codes 52 */ 53 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */ 54 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */ 55 #define MBS_BUSY 4 /* Busy. */ 56 57 /* 58 * ISP mailbox command complete status codes 59 */ 60 #define MBS_COMMAND_COMPLETE 0x4000 61 #define MBS_INVALID_COMMAND 0x4001 62 #define MBS_HOST_INTERFACE_ERROR 0x4002 63 #define MBS_TEST_FAILED 0x4003 64 #define MBS_POST_ERROR 0x4004 65 #define MBS_COMMAND_ERROR 0x4005 66 #define MBS_COMMAND_PARAMETER_ERROR 0x4006 67 #define MBS_PORT_ID_USED 0x4007 68 #define MBS_LOOP_ID_USED 0x4008 69 #define MBS_ALL_IDS_IN_USE 0x4009 70 #define MBS_NOT_LOGGED_IN 0x400A 71 #define MBS_LOOP_DOWN 0x400B 72 #define MBS_LOOP_BACK_ERROR 0x400C 73 #define MBS_CHECKSUM_ERROR 0x4010 74 75 /* 76 * Sub-error Codes for Mailbox Command Completion Status Code 4005h 77 */ 78 #define MBSS_NO_LINK 0x0001 79 #define MBSS_IOCB_ALLOC_ERR 0x0002 80 #define MBSS_ECB_ALLOC_ERR 0x0003 81 #define MBSS_CMD_FAILURE 0x0004 82 #define MBSS_NO_FABRIC 0x0005 83 #define MBSS_FIRMWARE_NOT_RDY 0x0007 84 #define MBSS_INITIATOR_DISABLED 0x0008 85 #define MBSS_NOT_LOGGED_IN 0x0009 86 #define MBSS_PARTIAL_DATA_XFER 0x000A 87 #define MBSS_TOPOLOGY_ERR 0x0016 88 #define MBSS_CHIP_RESET_NEEDED 0x0017 89 #define MBSS_MULTIPLE_OPEN_EXCH 0x0018 90 #define MBSS_IOCB_COUNT_ERR 0x0019 91 #define MBSS_CMD_AFTER_FW_INIT_ERR 0x001A 92 93 /* 94 * ISP mailbox asynchronous event status codes 95 */ 96 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */ 97 #define MBA_RESET 0x8001 /* Reset Detected. */ 98 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */ 99 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */ 100 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */ 101 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */ 102 #define MBA_MENLO_ALERT 0x800f /* Menlo Alert Notification. */ 103 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */ 104 /* occurred. */ 105 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */ 106 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */ 107 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */ 108 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */ 109 #define MBA_RSCN_UPDATE 0x8015 /* State Change Registration. */ 110 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */ 111 #define MBA_LIP_ERROR 0x8017 /* Loop initialization errors. */ 112 #define MBA_SECURITY_UPDATE 0x801B /* FC-SP security update. */ 113 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */ 114 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */ 115 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */ 116 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */ 117 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */ 118 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */ 119 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */ 120 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */ 121 /* used. */ 122 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */ 123 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */ 124 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */ 125 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */ 126 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */ 127 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */ 128 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */ 129 #define MBA_ZIO_UPDATE 0x8040 /* ZIO response queue update. */ 130 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */ 131 #define MBA_PORT_BYPASS_CHANGED 0x8043 /* Crystal+ port#0 bypass transition */ 132 #define MBA_RECEIVE_ERROR 0x8048 /* Receive Error */ 133 #define MBA_LS_RJT_SENT 0x8049 /* LS_RJT response sent */ 134 #define MBA_FW_RESTART_COMP 0x8060 /* Firmware Restart Complete. */ 135 136 /* Driver defined. */ 137 #define MBA_CMPLT_1_32BIT 0x9000 /* Completion 1 32bit IOSB. */ 138 139 /* 140 * Mailbox 23 event codes 141 */ 142 #define MBX23_MBX_OR_ASYNC_EVENT 0x0 143 #define MBX23_RESPONSE_QUEUE_UPDATE 0x1 144 #define MBX23_SCSI_COMPLETION 0x2 145 146 /* 147 * Menlo alert event defines 148 */ 149 #define MLA_PANIC_RECOVERY 0x1 150 #define MLA_LOGIN_OPERATIONAL_FW 0x2 151 #define MLA_LOGIN_DIAGNOSTIC_FW 0x3 152 #define MLA_LOGIN_GOLDEN_FW 0x4 153 #define MLA_REJECT_RESPONSE 0x5 154 155 /* 156 * ISP mailbox commands 157 */ 158 #define MBC_LOAD_RAM 1 /* Load RAM. */ 159 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */ 160 #define MBC_DUMP_RAM 3 /* Dump RAM. */ 161 #define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */ 162 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */ 163 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */ 164 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */ 165 #define MBC_ABOUT_FIRMWARE 8 /* About Firmware. */ 166 #define MBC_DUMP_RISC_RAM 0xa /* Dump RISC RAM command. */ 167 #define MBC_LOAD_RAM_EXTENDED 0xb /* Load RAM extended. */ 168 #define MBC_DUMP_RAM_EXTENDED 0xc /* Dump RAM extended. */ 169 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */ 170 #define MBC_SERDES_TRANSMIT_PARAMETERS 0x10 /* Serdes Xmit Parameters */ 171 #define MBC_2300_EXECUTE_IOCB 0x12 /* ISP2300 Execute IOCB cmd */ 172 #define MBC_GET_IO_STATUS 0x12 /* ISP2422 Get I/O Status */ 173 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware */ 174 #define MBC_ABORT_COMMAND_IOCB 0x15 /* Abort IOCB command. */ 175 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */ 176 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */ 177 #define MBC_RESET 0x18 /* Target reset. */ 178 #define MBC_XMIT_PARM 0x19 /* Change default xmit parms */ 179 #define MBC_PORT_PARAM 0x1a /* Get/set port speed parms */ 180 #define MBC_GET_ID 0x20 /* Get loop id of ISP2200. */ 181 #define MBC_GET_TIMEOUT_PARAMETERS 0x22 /* Get Timeout Parameters. */ 182 #define MBC_TRACE_CONTROL 0x27 /* Trace control. */ 183 #define MBC_READ_SFP 0x31 /* Read SFP. */ 184 #define MBC_GET_FIRMWARE_OPTIONS 0x28 /* Get firmware options */ 185 #define MBC_SET_FIRMWARE_OPTIONS 0x38 /* set firmware options */ 186 #define MBC_RESET_MENLO 0x3a /* Reset Menlo. */ 187 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */ 188 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */ 189 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */ 190 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */ 191 #define MBC_ECHO 0x44 /* ELS ECHO */ 192 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */ 193 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */ 194 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get Port Database + login */ 195 #define MBC_INITIALIZE_MULTI_ID_FW 0x48 /* Initialize multi-id fw */ 196 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */ 197 #define MBC_EXECUTE_IOCB 0x54 /* 64 Bit Execute IOCB cmd. */ 198 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */ 199 #define MBC_SET_PARAMETERS 0x59 /* Set RNID parameters */ 200 #define MBC_GET_PARAMETERS 0x5a /* Get RNID parameters */ 201 #define MBC_DATA_RATE 0x5d /* Data Rate */ 202 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */ 203 #define MBC_INITIATE_LIP 0x62 /* Initiate LIP */ 204 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */ 205 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */ 206 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */ 207 #define MBC_TARGET_RESET 0x66 /* Target Reset. */ 208 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */ 209 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */ 210 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */ 211 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */ 212 #define MBC_GET_LINK_STATUS 0x6b /* Get Link Status. */ 213 #define MBC_LIP_RESET 0x6c /* LIP reset. */ 214 #define MBC_GET_STATUS_COUNTS 0x6d /* Get Link Statistics and */ 215 /* Private Data Counts */ 216 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */ 217 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */ 218 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */ 219 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */ 220 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */ 221 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */ 222 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list */ 223 #define MBC_INITIALIZE_IP 0x77 /* Initialize IP */ 224 #define MBC_SEND_FARP_REQ_COMMAND 0x78 /* FARP request. */ 225 #define MBC_UNLOAD_IP 0x79 /* Unload IP */ 226 #define MBC_GET_ID_LIST 0x7c /* Get port ID list. */ 227 #define MBC_SEND_LFA_COMMAND 0x7d /* Send Loop Fabric Address */ 228 #define MBC_LUN_RESET 0x7e /* Send Task mgmt LUN reset */ 229 230 /* 231 * Mbc 20h (Get ID) returns the switch capabilities in mailbox7. 232 * The extra bits were added with 4.00.28 MID firmware. 233 */ 234 #define FLOGI_SEQ_DEL BIT_8 235 #define FLOGI_NPIV_SUPPORT BIT_10 /* implies FDISC support */ 236 #define FLOGI_VSAN_SUPPORT BIT_12 237 #define FLOGI_SP_SUPPORT BIT_13 238 239 /* 240 * Driver Mailbox command definitions. 241 */ 242 #define MAILBOX_TOV 30 /* Default Timeout value. */ 243 244 /* Mailbox command parameter structure definition. */ 245 typedef struct mbx_cmd { 246 uint32_t out_mb; /* Outgoing from driver */ 247 uint32_t in_mb; /* Incomming from RISC */ 248 uint16_t mb[MAX_MBOX_COUNT]; 249 clock_t timeout; /* Timeout in seconds. */ 250 } mbx_cmd_t; 251 252 /* Returned Mailbox registers. */ 253 typedef struct ql_mbx_data { 254 uint16_t mb[MAX_MBOX_COUNT]; 255 } ql_mbx_data_t; 256 257 /* Mailbox bit definitions for out_mb and in_mb */ 258 #define MBX_29 BIT_29 259 #define MBX_28 BIT_28 260 #define MBX_27 BIT_27 261 #define MBX_26 BIT_26 262 #define MBX_25 BIT_25 263 #define MBX_24 BIT_24 264 #define MBX_23 BIT_23 265 #define MBX_22 BIT_22 266 #define MBX_21 BIT_21 267 #define MBX_20 BIT_20 268 #define MBX_19 BIT_19 269 #define MBX_18 BIT_18 270 #define MBX_17 BIT_17 271 #define MBX_16 BIT_16 272 #define MBX_15 BIT_15 273 #define MBX_14 BIT_14 274 #define MBX_13 BIT_13 275 #define MBX_12 BIT_12 276 #define MBX_11 BIT_11 277 #define MBX_10 BIT_10 278 #define MBX_9 BIT_9 279 #define MBX_8 BIT_8 280 #define MBX_7 BIT_7 281 #define MBX_6 BIT_6 282 #define MBX_5 BIT_5 283 #define MBX_4 BIT_4 284 #define MBX_3 BIT_3 285 #define MBX_2 BIT_2 286 #define MBX_1 BIT_1 287 #define MBX_0 BIT_0 288 289 /* 290 * Firmware state codes from get firmware state mailbox command 291 */ 292 #define FSTATE_CONFIG_WAIT 0 293 #define FSTATE_WAIT_AL_PA 1 294 #define FSTATE_WAIT_LOGIN 2 295 #define FSTATE_READY 3 296 #define FSTATE_LOSS_SYNC 4 297 #define FSTATE_ERROR 5 298 #define FSTATE_NON_PART 7 299 300 /* 301 * Firmware options 1, 2, 3. 302 */ 303 #define FO1_AE_ON_LIPF8 BIT_0 304 #define FO1_AE_ALL_LIP_RESET BIT_1 305 #define FO1_CTIO_RETRY BIT_3 306 #define FO1_DISABLE_LIP_F7_SW BIT_4 307 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5 308 #define FO1_DISABLE_GPIO BIT_6 309 #define FO1_AE_AUTO_BYPASS BIT_9 310 #define FO1_ENABLE_PURE_IOCB BIT_10 311 #define FO1_AE_PLOGI_RJT BIT_11 312 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12 313 #define FO1_AE_QUEUE_FULL BIT_13 314 315 #define FO2_REV_LOOPBACK BIT_1 316 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0 317 318 #define FO3_STARTUP_OPTS_VALID BIT_5 319 #define FO3_AE_RND_ERROR BIT_1 320 #define FO3_ENABLE_EMERG_IOCB BIT_0 321 322 #define FO13_LESB_NO_RESET BIT_0 323 324 /* 325 * f/w trace options 326 */ 327 #define FTO_EXTENABLE 4 328 #define FTO_EXTDISABLE 5 329 #define FTO_FCEENABLE 8 330 #define FTO_FCEDISABLE 9 331 #define FTO_FCEMAXTRACEBUF 0x840 /* max frame size */ 332 333 /* 334 * fw_attributes defines from firmware version mailbox command 335 */ 336 #define FWATTRIB_EF 0x7 337 #define FWATTRIB_TP 0x17 338 #define FWATTRIB_IP 0x37 339 #define FWATTRIB_TPX 0x117 340 #define FWATTRIB_IPX 0x137 341 #define FWATTRIB_FL 0x217 342 #define FWATTRIB_FPX 0x317 343 344 /* 345 * Diagnostic ELS ECHO parameter structure definition. 346 */ 347 typedef struct echo { 348 uint16_t options; 349 uint32_t transfer_count; 350 ddi_dma_cookie_t transfer_data_address; 351 ddi_dma_cookie_t receive_data_address; 352 } echo_t; 353 354 /* 355 * LFA command structure. 356 */ 357 #define LFA_PAYLOAD_SIZE 38 358 typedef struct lfa_cmd { 359 uint8_t resp_buffer_length[2]; /* length in 16bit words. */ 360 uint8_t reserved[2]; 361 uint8_t resp_buffer_address[8]; 362 uint8_t subcommand_length[2]; /* length in 16bit words. */ 363 uint8_t reserved_1[2]; 364 uint8_t addr[4]; 365 uint8_t subcommand[2]; 366 uint8_t payload[LFA_PAYLOAD_SIZE]; 367 } lfa_cmd_t; 368 369 /* 370 * Deivce ID list definitions. 371 */ 372 struct ql_dev_id { 373 uint8_t al_pa; 374 uint8_t area; 375 uint8_t domain; 376 uint8_t loop_id; 377 }; 378 379 struct ql_ex_dev_id { 380 uint8_t al_pa; 381 uint8_t area; 382 uint8_t domain; 383 uint8_t reserved; 384 uint8_t loop_id_l; 385 uint8_t loop_id_h; 386 }; 387 388 struct ql_24_dev_id { 389 uint8_t al_pa; 390 uint8_t area; 391 uint8_t domain; 392 uint8_t reserved; 393 uint8_t n_port_hdl_l; 394 uint8_t n_port_hdl_h; 395 uint8_t reserved_1[2]; 396 }; 397 398 typedef union ql_dev_id_list { 399 struct ql_dev_id d; 400 struct ql_ex_dev_id d_ex; 401 struct ql_24_dev_id d_24; 402 } ql_dev_id_list_t; 403 404 /* Define maximum number of device list entries.. */ 405 #define DEVICE_LIST_ENTRIES MAX_24_FIBRE_DEVICES 406 407 /* Define size of Loop Position Map. */ 408 #define LOOP_POSITION_MAP_SIZE 128 /* bytes */ 409 410 /* 411 * Port Database structure definition 412 * Little endian except where noted. 413 */ 414 #define PORT_DATABASE_SIZE 128 /* bytes */ 415 typedef struct port_database_23 { 416 uint8_t options; 417 uint8_t control; 418 uint8_t master_state; 419 uint8_t slave_state; 420 uint8_t hard_address[3]; 421 uint8_t rsvd; 422 uint32_t port_id; 423 uint8_t node_name[8]; /* Big endian. */ 424 uint8_t port_name[8]; /* Big endian. */ 425 uint16_t execution_throttle; 426 uint16_t execution_count; 427 uint8_t reset_count; 428 uint8_t reserved_2; 429 uint16_t resource_allocation; 430 uint16_t current_allocation; 431 uint16_t queue_head; 432 uint16_t queue_tail; 433 uint16_t transmit_execution_list_next; 434 uint16_t transmit_execution_list_previous; 435 uint16_t common_features; 436 uint16_t total_concurrent_sequences; 437 uint16_t RO_by_information_category; 438 uint8_t recipient; 439 uint8_t initiator; 440 uint16_t receive_data_size; 441 uint16_t concurrent_sequences; 442 uint16_t open_sequences_per_exchange; 443 uint16_t lun_abort_flags; 444 uint16_t lun_stop_flags; 445 uint16_t stop_queue_head; 446 uint16_t stop_queue_tail; 447 uint16_t port_retry_timer; 448 uint16_t next_sequence_id; 449 uint16_t frame_count; 450 uint16_t PRLI_payload_length; 451 uint16_t PRLI_service_parameter_word_0; /* Big endian */ 452 /* Bits 15-0 of word 0 */ 453 uint16_t PRLI_service_parameter_word_3; /* Big endian */ 454 /* Bits 15-0 of word 3 */ 455 uint16_t loop_id; 456 uint16_t extended_lun_info_list_pointer; 457 uint16_t extended_lun_stop_list_pointer; 458 } port_database_23_t; 459 460 typedef struct port_database_24 { 461 uint16_t flags; 462 uint8_t current_login_state; 463 uint8_t last_stable_login_state; 464 uint8_t hard_address[3]; 465 uint8_t rsvd; 466 uint8_t port_id[3]; 467 uint8_t sequence_id; 468 uint16_t port_retry_timer; 469 uint16_t n_port_handle; 470 uint16_t receive_data_size; 471 uint8_t reserved_1[2]; 472 uint16_t PRLI_service_parameter_word_0; /* Big endian */ 473 /* Bits 15-0 of word 0 */ 474 uint16_t PRLI_service_parameter_word_3; /* Big endian */ 475 /* Bits 15-0 of word 3 */ 476 uint8_t port_name[8]; /* Big endian. */ 477 uint8_t node_name[8]; /* Big endian. */ 478 uint8_t reserved_2[24]; 479 } port_database_24_t; 480 481 /* 482 * Port database slave/master/current_login/ast_stable_login states 483 */ 484 #define PD_STATE_DISCOVERY 0 485 #define PD_STATE_WAIT_DISCOVERY_ACK 1 486 #define PD_STATE_PORT_LOGIN 2 487 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3 488 #define PD_STATE_PROCESS_LOGIN 4 489 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5 490 #define PD_STATE_PORT_LOGGED_IN 6 491 #define PD_STATE_PORT_UNAVAILABLE 7 492 #define PD_STATE_PROCESS_LOGOUT 8 493 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9 494 #define PD_STATE_PORT_LOGOUT 10 495 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11 496 497 #define PD_PORT_LOGIN(tq) \ 498 (tq->master_state == PD_STATE_PROCESS_LOGIN || \ 499 tq->master_state == PD_STATE_PORT_LOGGED_IN || \ 500 tq->slave_state == PD_STATE_PROCESS_LOGIN || \ 501 tq->slave_state == PD_STATE_PORT_LOGGED_IN) 502 503 /* 504 * ql_login_lport() options 505 */ 506 #define LLF_NONE 0 507 #define LLF_PLOGI BIT_0 /* unconditional PLOGI */ 508 509 /* 510 * ql_login_fport() options 511 */ 512 #define LFF_NONE 0 513 #define LFF_NO_PLOGI BIT_0 514 #define LFF_NO_PRLI BIT_1 515 516 /* 517 * ql_get_port_database() options 518 */ 519 #define PDF_NONE 0 520 #define PDF_PLOGI BIT_0 521 #define PDF_ADISC BIT_1 522 523 /* 524 * ql_get_adapter_id() returned connection types 525 */ 526 #define CNX_LOOP_NO_FABRIC 0 527 #define CNX_FLPORT_IN_LOOP 1 528 #define CNX_NPORT_2_NPORT_P2P 2 529 #define CNX_FLPORT_P2P 3 530 #define CNX_NPORT_2_NPORT_NO_TGT_RSP 4 531 532 /* 533 * Global Data in ql_mbx.c source file. 534 */ 535 536 /* 537 * Global Function Prototypes in ql_mbx.c source file. 538 */ 539 int ql_initialize_ip(ql_adapter_state_t *); 540 int ql_shutdown_ip(ql_adapter_state_t *); 541 int ql_online_selftest(ql_adapter_state_t *); 542 int ql_loop_back(ql_adapter_state_t *, lbp_t *, uint32_t, uint32_t); 543 int ql_echo(ql_adapter_state_t *, echo_t *); 544 int ql_send_change_request(ql_adapter_state_t *, uint16_t); 545 int ql_send_lfa(ql_adapter_state_t *, lfa_cmd_t *); 546 int ql_clear_aca(ql_adapter_state_t *, ql_tgt_t *, uint16_t); 547 int ql_target_reset(ql_adapter_state_t *, ql_tgt_t *, uint16_t); 548 int ql_abort_target(ql_adapter_state_t *, ql_tgt_t *, uint16_t); 549 int ql_lun_reset(ql_adapter_state_t *, ql_tgt_t *, uint16_t); 550 int ql_clear_task_set(ql_adapter_state_t *, ql_tgt_t *, uint16_t); 551 int ql_abort_task_set(ql_adapter_state_t *, ql_tgt_t *, uint16_t); 552 int ql_loop_port_bypass(ql_adapter_state_t *, ql_tgt_t *); 553 int ql_loop_port_enable(ql_adapter_state_t *, ql_tgt_t *); 554 int ql_login_lport(ql_adapter_state_t *, ql_tgt_t *, uint16_t, uint16_t); 555 int ql_login_fport(ql_adapter_state_t *, ql_tgt_t *, uint16_t, uint16_t, 556 ql_mbx_data_t *); 557 int ql_logout_fabric_port(ql_adapter_state_t *, ql_tgt_t *); 558 int ql_log_iocb(ql_adapter_state_t *, ql_tgt_t *, uint16_t, uint16_t, 559 ql_mbx_data_t *); 560 int ql_get_port_database(ql_adapter_state_t *, ql_tgt_t *, uint8_t); 561 int ql_get_loop_position_map(ql_adapter_state_t *, size_t, caddr_t); 562 int ql_set_rnid_params(ql_adapter_state_t *, size_t, caddr_t); 563 int ql_send_rnid_els(ql_adapter_state_t *, uint16_t, uint8_t, size_t, caddr_t); 564 int ql_get_rnid_params(ql_adapter_state_t *, size_t, caddr_t); 565 int ql_get_link_status(ql_adapter_state_t *, uint16_t, size_t, caddr_t, 566 uint8_t); 567 int ql_get_status_counts(ql_adapter_state_t *, uint16_t, size_t, caddr_t, 568 uint8_t); 569 int ql_reset_link_status(ql_adapter_state_t *); 570 int ql_loop_reset(ql_adapter_state_t *); 571 int ql_initiate_lip(ql_adapter_state_t *); 572 int ql_full_login_lip(ql_adapter_state_t *); 573 int ql_lip_reset(ql_adapter_state_t *, uint16_t); 574 int ql_abort_command(ql_adapter_state_t *, ql_srb_t *); 575 int ql_verify_checksum(ql_adapter_state_t *); 576 int ql_get_id_list(ql_adapter_state_t *, caddr_t, uint32_t, ql_mbx_data_t *); 577 int ql_wrt_risc_ram(ql_adapter_state_t *, uint32_t, uint64_t, uint32_t); 578 int ql_rd_risc_ram(ql_adapter_state_t *, uint32_t, uint64_t, uint32_t); 579 int ql_issue_mbx_iocb(ql_adapter_state_t *, caddr_t, uint32_t); 580 int ql_mbx_wrap_test(ql_adapter_state_t *, ql_mbx_data_t *); 581 int ql_execute_fw(ql_adapter_state_t *); 582 int ql_get_firmware_option(ql_adapter_state_t *, ql_mbx_data_t *); 583 int ql_set_firmware_option(ql_adapter_state_t *, ql_mbx_data_t *); 584 int ql_init_firmware(ql_adapter_state_t *); 585 int ql_get_firmware_state(ql_adapter_state_t *, ql_mbx_data_t *); 586 int ql_get_adapter_id(ql_adapter_state_t *, ql_mbx_data_t *); 587 int ql_get_fw_version(ql_adapter_state_t *, ql_mbx_data_t *); 588 int ql_data_rate(ql_adapter_state_t *, ql_mbx_data_t *); 589 int ql_diag_loopback(ql_adapter_state_t *, caddr_t, uint32_t, uint16_t, 590 uint32_t, ql_mbx_data_t *); 591 int ql_diag_echo(ql_adapter_state_t *, caddr_t, uint32_t, uint16_t, 592 ql_mbx_data_t *); 593 int ql_serdes_param(ql_adapter_state_t *, ql_mbx_data_t *); 594 int ql_get_timeout_parameters(ql_adapter_state_t *, uint16_t *); 595 int ql_stop_firmware(ql_adapter_state_t *); 596 int ql_read_sfp(ql_adapter_state_t *, dma_mem_t *, uint16_t, uint16_t); 597 int ql_iidma_rate(ql_adapter_state_t *, uint16_t, uint32_t *, uint32_t); 598 int ql_fw_etrace(ql_adapter_state_t *, dma_mem_t *, uint16_t); 599 int ql_reset_menlo(ql_adapter_state_t *, ql_mbx_data_t *, uint16_t); 600 601 #ifdef __cplusplus 602 } 603 #endif 604 605 #endif /* _QL_MBX_H */ 606