1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_IB_IBTL_IBTL_TYPES_H 28 #define _SYS_IB_IBTL_IBTL_TYPES_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 /* 33 * ibtl_types.h 34 * 35 * All common IBTL defined types. These are common data types 36 * that are shared by the IBTI and IBCI interfaces, it is only included 37 * by ibti.h and ibci.h 38 */ 39 #include <sys/ddi.h> 40 #include <sys/sunddi.h> 41 #include <sys/ib/ib_types.h> 42 #include <sys/ib/ibtl/ibtl_status.h> 43 44 #ifdef __cplusplus 45 extern "C" { 46 #endif 47 48 /* 49 * Define Internal IBTL handles 50 */ 51 typedef struct ibtl_clnt_s *ibt_clnt_hdl_t; /* ibt_attach() */ 52 typedef struct ibtl_hca_s *ibt_hca_hdl_t; /* ibt_open_hca() */ 53 typedef struct ibtl_channel_s *ibt_channel_hdl_t; /* alloc_rc|ud_channel() */ 54 typedef struct ibtl_srq_s *ibt_srq_hdl_t; /* ibt_alloc_srq() */ 55 typedef struct ibtl_cq_s *ibt_cq_hdl_t; /* ibt_alloc_cq() */ 56 typedef struct ibcm_svc_info_s *ibt_srv_hdl_t; /* ibt_register_service() */ 57 typedef struct ibcm_svc_bind_s *ibt_sbind_hdl_t; /* ibt_bind_service() */ 58 59 typedef struct ibc_ma_s *ibt_ma_hdl_t; /* ibt_map_mem_area() */ 60 typedef struct ibc_pd_s *ibt_pd_hdl_t; /* ibt_alloc_pd() */ 61 typedef struct ibc_sched_s *ibt_sched_hdl_t; /* ibt_alloc_cq_sched() */ 62 typedef struct ibc_mr_s *ibt_mr_hdl_t; /* ibt_register_mr() */ 63 typedef struct ibc_mw_s *ibt_mw_hdl_t; /* ibt_alloc_mw() */ 64 typedef struct ibt_ud_dest_s *ibt_ud_dest_hdl_t; /* UD dest handle */ 65 typedef struct ibc_ah_s *ibt_ah_hdl_t; /* ibt_alloc_ah() */ 66 typedef struct ibtl_eec_s *ibt_eec_hdl_t; 67 typedef struct ibt_rd_dest_s *ibt_rd_dest_hdl_t; /* Reserved for */ 68 /* Future use */ 69 70 /* 71 * Some General Types. 72 */ 73 typedef uint32_t ibt_lkey_t; /* L_Key */ 74 typedef uint32_t ibt_rkey_t; /* R_Key */ 75 typedef uint64_t ibt_wrid_t; /* Client assigned WR ID */ 76 typedef uint32_t ibt_immed_t; /* WR Immediate Data */ 77 typedef uint64_t ibt_atom_arg_t; /* WR Atomic Operation arg */ 78 typedef uint_t ibt_cq_handler_id_t; /* Event handler ID */ 79 80 /* 81 * IBT selector type, used when looking up/requesting either an 82 * MTU, Pkt lifetime, or Static rate. 83 * The interpretation of IBT_BEST depends on the attribute being selected. 84 */ 85 typedef enum ibt_selector_e { 86 IBT_GT = 0, /* Greater than */ 87 IBT_LT = 1, /* Less than */ 88 IBT_EQU = 2, /* Equal to */ 89 IBT_BEST = 3 /* Best */ 90 } ibt_selector_t; 91 92 93 /* 94 * Static rate definitions. 95 */ 96 typedef enum ibt_srate_e { 97 IBT_SRATE_NOT_SPECIFIED = 0, 98 IBT_SRATE_1X = 2, 99 IBT_SRATE_4X = 3, 100 IBT_SRATE_12X = 4 101 } ibt_srate_t; 102 103 /* 104 * Static rate request type. 105 */ 106 typedef struct ibt_srate_req_s { 107 ibt_srate_t r_srate; /* Requested srate */ 108 ibt_selector_t r_selector; /* Qualifier for r_srate */ 109 } ibt_srate_req_t; 110 111 /* 112 * Packet Life Time Request Type. 113 */ 114 typedef struct ibt_pkt_lt_req_s { 115 clock_t p_pkt_lt; /* Requested Packet Life Time */ 116 ibt_selector_t p_selector; /* Qualifier for p_pkt_lt */ 117 } ibt_pkt_lt_req_t; 118 119 /* 120 * Queue size struct. 121 */ 122 typedef struct ibt_queue_sizes_s { 123 uint_t qs_sq; /* SendQ size. */ 124 uint_t qs_rq; /* RecvQ size. */ 125 } ibt_queue_sizes_t; 126 127 /* 128 * Channel sizes struct, used by functions that allocate/query RC or UD 129 * channels. 130 */ 131 typedef struct ibt_chan_sizes_s { 132 uint_t cs_sq; /* SendQ size. */ 133 uint_t cs_rq; /* ReceiveQ size. */ 134 uint_t cs_sq_sgl; /* Max SGL elements in a SQ WR. */ 135 uint_t cs_rq_sgl; /* Max SGL elements in a RQ Wr. */ 136 } ibt_chan_sizes_t; 137 138 /* 139 * Shared Queue size struct. 140 */ 141 typedef struct ibt_srq_sizes_s { 142 uint_t srq_wr_sz; 143 uint_t srq_sgl_sz; 144 } ibt_srq_sizes_t; 145 146 /* 147 * SRQ Modify Flags 148 */ 149 typedef enum ibt_srq_modify_flags_e { 150 IBT_SRQ_SET_NOTHING = 0, 151 IBT_SRQ_SET_SIZE = (1 << 1), 152 IBT_SRQ_SET_LIMIT = (1 << 2) 153 } ibt_srq_modify_flags_t; 154 155 156 /* 157 * Execution flags, indicates if the function should block or not. 158 * Note: in some cases, e.g., a NULL rc_cm_handler, IBT_NONBLOCKING 159 * will not have an effect, and the thread will block. 160 * IBT_NOCALLBACKS is valid for ibt_close_rc_channel only. 161 */ 162 typedef enum ibt_execution_mode_e { 163 IBT_BLOCKING = 0, /* Block */ 164 IBT_NONBLOCKING = 1, /* Return as soon as possible */ 165 IBT_NOCALLBACKS = 2 /* cm_handler is not invoked after */ 166 /* ibt_close_rc_channel returns */ 167 } ibt_execution_mode_t; 168 169 /* 170 * Memory window alloc flags 171 */ 172 typedef enum ibt_mw_flags_e { 173 IBT_MW_SLEEP = 0, /* Can block */ 174 IBT_MW_NOSLEEP = (1 << 0), /* Can't block */ 175 IBT_MW_USER_MAP = (1 << 1), 176 IBT_MW_DEFER_ALLOC = (1 << 2), 177 IBT_MW_TYPE_1 = (1 << 3), 178 IBT_MW_TYPE_2 = (1 << 4) 179 } ibt_mw_flags_t; 180 181 /* 182 * PD alloc flags 183 */ 184 typedef enum ibt_pd_flags_e { 185 IBT_PD_NO_FLAGS = 0, 186 IBT_PD_USER_MAP = (1 << 0), 187 IBT_PD_DEFER_ALLOC = (1 << 1) 188 } ibt_pd_flags_t; 189 190 /* 191 * UD Dest alloc flags 192 */ 193 typedef enum ibt_ud_dest_flags_e { 194 IBT_UD_DEST_NO_FLAGS = 0, 195 IBT_UD_DEST_USER_MAP = (1 << 0), 196 IBT_UD_DEST_DEFER_ALLOC = (1 << 1) 197 } ibt_ud_dest_flags_t; 198 199 /* 200 * SRQ alloc flags 201 */ 202 typedef enum ibt_srq_flags_e { 203 IBT_SRQ_NO_FLAGS = 0, 204 IBT_SRQ_USER_MAP = (1 << 0), 205 IBT_SRQ_DEFER_ALLOC = (1 << 1) 206 } ibt_srq_flags_t; 207 208 /* 209 * ibt_alloc_lkey() alloc flags 210 */ 211 typedef enum ibt_lkey_flags_e { 212 IBT_KEY_NO_FLAGS = 0, 213 IBT_KEY_REMOTE = (1 << 0) 214 } ibt_lkey_flags_t; 215 216 /* 217 * RNR NAK retry counts. 218 */ 219 typedef enum ibt_rnr_retry_cnt_e { 220 IBT_RNR_NO_RETRY = 0x0, /* Don't retry, fail on first timeout */ 221 IBT_RNR_RETRY_1 = 0x1, /* Retry once */ 222 IBT_RNR_RETRY_2 = 0x2, /* Retry twice */ 223 IBT_RNR_RETRY_3 = 0x3, /* Retry three times */ 224 IBT_RNR_RETRY_4 = 0x4, /* Retry four times */ 225 IBT_RNR_RETRY_5 = 0x5, /* Retry five times */ 226 IBT_RNR_RETRY_6 = 0x6, /* Retry six times */ 227 IBT_RNR_INFINITE_RETRY = 0x7 /* Retry forever */ 228 } ibt_rnr_retry_cnt_t; 229 230 /* 231 * Valid values for RNR NAK timer fields, part of a channel's context. 232 */ 233 typedef enum ibt_rnr_nak_time_e { 234 IBT_RNR_NAK_655ms = 0x0, 235 IBT_RNR_NAK_10us = 0x1, 236 IBT_RNR_NAK_20us = 0x2, 237 IBT_RNR_NAK_30us = 0x3, 238 IBT_RNR_NAK_40us = 0x4, 239 IBT_RNR_NAK_60us = 0x5, 240 IBT_RNR_NAK_80us = 0x6, 241 IBT_RNR_NAK_120us = 0x7, 242 IBT_RNR_NAK_160us = 0x8, 243 IBT_RNR_NAK_240us = 0x9, 244 IBT_RNR_NAK_320us = 0xA, 245 IBT_RNR_NAK_480us = 0xB, 246 IBT_RNR_NAK_640us = 0xC, 247 IBT_RNR_NAK_960us = 0xD, 248 IBT_RNR_NAK_1280us = 0xE, 249 IBT_RNR_NAK_1920us = 0xF, 250 IBT_RNR_NAK_2560us = 0x10, 251 IBT_RNR_NAK_3840us = 0x11, 252 IBT_RNR_NAK_5120us = 0x12, 253 IBT_RNR_NAK_7680us = 0x13, 254 IBT_RNR_NAK_10ms = 0x14, 255 IBT_RNR_NAK_15ms = 0x15, 256 IBT_RNR_NAK_20ms = 0x16, 257 IBT_RNR_NAK_31ms = 0x17, 258 IBT_RNR_NAK_41ms = 0x18, 259 IBT_RNR_NAK_61ms = 0x19, 260 IBT_RNR_NAK_82ms = 0x1A, 261 IBT_RNR_NAK_123ms = 0x1B, 262 IBT_RNR_NAK_164ms = 0x1C, 263 IBT_RNR_NAK_246ms = 0x1D, 264 IBT_RNR_NAK_328ms = 0x1E, 265 IBT_RNR_NAK_492ms = 0x1F 266 } ibt_rnr_nak_time_t; 267 268 /* 269 * The definition of HCA capabilities etc as a bitfield. 270 */ 271 typedef enum ibt_hca_flags_e { 272 IBT_HCA_NO_FLAGS = 0, 273 274 IBT_HCA_RD = 1 << 0, 275 IBT_HCA_UD_MULTICAST = 1 << 1, 276 IBT_HCA_RAW_MULTICAST = 1 << 2, 277 278 IBT_HCA_ATOMICS_HCA = 1 << 3, 279 IBT_HCA_ATOMICS_GLOBAL = 1 << 4, 280 281 IBT_HCA_RESIZE_CHAN = 1 << 5, /* Is resize supported? */ 282 IBT_HCA_AUTO_PATH_MIG = 1 << 6, /* Is APM supported? */ 283 IBT_HCA_SQD_SQD_PORT = 1 << 7, /* Can change physical port */ 284 /* on transit from SQD to SQD */ 285 IBT_HCA_PKEY_CNTR = 1 << 8, 286 IBT_HCA_QKEY_CNTR = 1 << 9, 287 IBT_HCA_AH_PORT_CHECK = 1 << 10, /* HCA checks AH port match */ 288 /* in UD WRs */ 289 IBT_HCA_PORT_UP = 1 << 11, /* PortActive event supported */ 290 IBT_HCA_INIT_TYPE = 1 << 12, /* InitType supported */ 291 IBT_HCA_SI_GUID = 1 << 13, /* System Image GUID */ 292 /* supported */ 293 IBT_HCA_SHUTDOWN_PORT = 1 << 14, /* ShutdownPort supported */ 294 IBT_HCA_RNR_NAK = 1 << 15, /* RNR-NAK supported for RC */ 295 IBT_HCA_CURRENT_QP_STATE = 1 << 16, /* Does modify_qp support */ 296 /* checking of current state? */ 297 IBT_HCA_SRQ = 1 << 17, /* Shared Receive Queue */ 298 IBT_HCA_RESIZE_SRQ = 1 << 18, /* Is resize SRQ supported? */ 299 IBT_HCA_BASE_MEM_MGT = 1 << 19, /* Base memory mgt supported? */ 300 IBT_HCA_MULT_PAGE_SZ_MR = 1 << 20, /* Support of multiple page */ 301 /* sizes per memory region? */ 302 IBT_HCA_BLOCK_LIST = 1 << 21, /* Block list physical buffer */ 303 /* lists supported? */ 304 IBT_HCA_ZERO_BASED_VA = 1 << 22, /* Zero Based Virtual */ 305 /* Addresses supported? */ 306 IBT_HCA_LOCAL_INVAL_FENCE = 1 << 23, /* Local invalidate fencing? */ 307 IBT_HCA_BASE_QUEUE_MGT = 1 << 24, /* Base Queue Mgt supported? */ 308 IBT_HCA_CKSUM_FULL = 1 << 25, /* Checksum offload supported */ 309 IBT_HCA_MEM_WIN_TYPE_2B = 1 << 26, /* Type 2B memory windows */ 310 IBT_HCA_PHYS_BUF_BLOCK = 1 << 27 /* Block mode phys buf lists */ 311 } ibt_hca_flags_t; 312 313 /* 314 * The definition of HCA page size capabilities as a bitfield 315 */ 316 typedef enum ibt_page_sizes_e { 317 IBT_PAGE_4K = 0x1 << 2, 318 IBT_PAGE_8K = 0x1 << 3, 319 IBT_PAGE_16K = 0x1 << 4, 320 IBT_PAGE_32K = 0x1 << 5, 321 IBT_PAGE_64K = 0x1 << 6, 322 IBT_PAGE_128K = 0x1 << 7, 323 IBT_PAGE_256K = 0x1 << 8, 324 IBT_PAGE_512K = 0x1 << 9, 325 IBT_PAGE_1M = 0x1 << 10, 326 IBT_PAGE_2M = 0x1 << 11, 327 IBT_PAGE_4M = 0x1 << 12, 328 IBT_PAGE_8M = 0x1 << 13, 329 IBT_PAGE_16M = 0x1 << 14, 330 IBT_PAGE_32M = 0x1 << 15, 331 IBT_PAGE_64M = 0x1 << 16, 332 IBT_PAGE_128M = 0x1 << 17, 333 IBT_PAGE_256M = 0x1 << 18, 334 IBT_PAGE_512M = 0x1 << 19, 335 IBT_PAGE_1G = 0x1 << 20, 336 IBT_PAGE_2G = 0x1 << 21, 337 IBT_PAGE_4G = 0x1 << 22, 338 IBT_PAGE_8G = 0x1 << 23, 339 IBT_PAGE_16G = 0x1 << 24 340 } ibt_page_sizes_t; 341 342 /* 343 * Memory Window Type. 344 */ 345 typedef enum ibt_mem_win_type_e { 346 IBT_MEM_WIN_TYPE_NOT_DEFINED = 0, 347 IBT_MEM_WIN_TYPE_1 = (1 << 0), 348 IBT_MEM_WIN_TYPE_2 = (1 << 1) 349 } ibt_mem_win_type_t; 350 351 /* 352 * HCA attributes. 353 * Contains all HCA static attributes. 354 */ 355 typedef struct ibt_hca_attr_s { 356 ibt_hca_flags_t hca_flags; /* HCA capabilities etc */ 357 358 /* device/version inconsistency w/ NodeInfo and IOControllerProfile */ 359 uint32_t hca_vendor_id:24; /* 24 bit Vendor ID */ 360 uint16_t hca_device_id; 361 uint32_t hca_version_id; 362 363 uint_t hca_max_chans; /* Max Chans supported */ 364 uint_t hca_max_chan_sz; /* Max outstanding WRs on any */ 365 /* channel */ 366 367 uint_t hca_max_sgl; /* Max SGL entries per WR */ 368 369 uint_t hca_max_cq; /* Max num of CQs supported */ 370 uint_t hca_max_cq_sz; /* Max capacity of each CQ */ 371 372 ibt_page_sizes_t hca_page_sz; /* Bit mask of page sizes */ 373 374 uint_t hca_max_memr; /* Max num of HCA mem regions */ 375 ib_memlen_t hca_max_memr_len; /* Largest block, in bytes of */ 376 /* mem that can be registered */ 377 uint_t hca_max_mem_win; /* Max Memory windows in HCA */ 378 379 uint_t hca_max_rsc; /* Max Responder Resources of */ 380 /* this HCA for RDMAR/Atomics */ 381 /* with this HCA as target. */ 382 uint8_t hca_max_rdma_in_chan; /* Max RDMAR/Atomics in per */ 383 /* chan this HCA as target. */ 384 uint8_t hca_max_rdma_out_chan; /* Max RDMA Reads/Atomics out */ 385 /* per channel by this HCA */ 386 uint_t hca_max_ipv6_chan; /* Max IPV6 channels in HCA */ 387 uint_t hca_max_ether_chan; /* Max Ether channels in HCA */ 388 389 uint_t hca_max_mcg_chans; /* Max number of channels */ 390 /* that can join multicast */ 391 /* groups */ 392 uint_t hca_max_mcg; /* Max multicast groups */ 393 uint_t hca_max_chan_per_mcg; /* Max number of channels per */ 394 /* Multicast group in HCA */ 395 396 uint16_t hca_max_partitions; /* Max partitions in HCA */ 397 uint8_t hca_nports; /* Number of physical ports */ 398 ib_guid_t hca_node_guid; /* Node GUID */ 399 400 ib_time_t hca_local_ack_delay; 401 402 uint_t hca_max_port_sgid_tbl_sz; 403 uint16_t hca_max_port_pkey_tbl_sz; 404 uint_t hca_max_pd; /* Max# of Protection Domains */ 405 ib_guid_t hca_si_guid; /* Optional System Image GUID */ 406 uint_t hca_hca_max_ci_priv_sz; 407 uint_t hca_chan_max_ci_priv_sz; 408 uint_t hca_cq_max_ci_priv_sz; 409 uint_t hca_pd_max_ci_priv_sz; 410 uint_t hca_mr_max_ci_priv_sz; 411 uint_t hca_mw_max_ci_priv_sz; 412 uint_t hca_ud_dest_max_ci_priv_sz; 413 uint_t hca_cq_sched_max_ci_priv_sz; 414 uint_t hca_max_ud_dest; 415 uint_t hca_opaque2; 416 uint_t hca_opaque3; 417 uint_t hca_opaque4; 418 uint8_t hca_opaque5; 419 uint8_t hca_opaque6; 420 uint_t hca_opaque7; 421 uint_t hca_opaque8; 422 uint_t hca_max_srqs; /* Max SRQs supported */ 423 uint_t hca_max_srqs_sz; /* Max outstanding WRs on any */ 424 /* SRQ */ 425 uint_t hca_max_srq_sgl; /* Max SGL entries per SRQ WR */ 426 uint_t hca_max_phys_buf_list_sz; 427 size_t hca_block_sz_lo; /* Range of block sizes */ 428 size_t hca_block_sz_hi; /* supported by the HCA */ 429 uint_t hca_max_cq_handlers; 430 ibt_lkey_t hca_reserved_lkey; 431 } ibt_hca_attr_t; 432 433 /* 434 * HCA Port link states. 435 */ 436 typedef enum ibt_port_state_e { 437 IBT_PORT_DOWN = 1, 438 IBT_PORT_INIT, 439 IBT_PORT_ARM, 440 IBT_PORT_ACTIVE 441 } ibt_port_state_t; 442 443 /* 444 * HCA Port capabilities as a bitfield. 445 */ 446 typedef enum ibt_port_caps_e { 447 IBT_PORT_CAP_NO_FLAGS = 0, 448 IBT_PORT_CAP_SM = 1 << 0, /* SM port */ 449 IBT_PORT_CAP_SM_DISABLED = 1 << 1, 450 IBT_PORT_CAP_SNMP_TUNNEL = 1 << 2, /* SNMP Tunneling */ 451 IBT_PORT_CAP_DM = 1 << 3, /* DM supported */ 452 IBT_PORT_CAP_VENDOR = 1 << 4 /* Vendor Class */ 453 } ibt_port_caps_t; 454 455 456 /* 457 * HCA port attributes structure definition. The number of ports per HCA 458 * can be found from the "ibt_hca_attr_t" structure. 459 * 460 * p_pkey_tbl is a pointer to an array of ib_pkey_t, members are 461 * accessed as: 462 * hca_portinfo->p_pkey_tbl[i] 463 * 464 * Where 0 <= i < hca_portinfo.p_pkey_tbl_sz 465 * 466 * Similarly p_sgid_tbl is a pointer to an array of ib_gid_t. 467 * 468 * The Query Port function - ibt_query_hca_ports() allocates the memory 469 * required for the ibt_hca_portinfo_t struct as well as the memory 470 * required for the SGID and P_Key tables. The memory is freed by calling 471 * ibt_free_portinfo(). 472 */ 473 typedef struct ibt_hca_portinfo_s { 474 ib_lid_t p_opaque1; /* Base LID of port */ 475 ib_qkey_cntr_t p_qkey_violations; /* Bad Q_Key cnt */ 476 ib_pkey_cntr_t p_pkey_violations; /* Optional bad P_Key cnt */ 477 uint8_t p_sm_sl:4; /* SM Service level */ 478 ib_lid_t p_sm_lid; /* SM LID */ 479 ibt_port_state_t p_linkstate; /* Port state */ 480 uint8_t p_port_num; 481 ib_mtu_t p_mtu; /* Max transfer unit - pkt */ 482 uint8_t p_lmc:3; /* Local mask control */ 483 ib_gid_t *p_sgid_tbl; /* SGID Table */ 484 uint_t p_sgid_tbl_sz; /* Size of SGID table */ 485 uint16_t p_pkey_tbl_sz; /* Size of P_Key table */ 486 uint16_t p_def_pkey_ix; /* default pkey index for TI */ 487 ib_pkey_t *p_pkey_tbl; /* P_Key table */ 488 uint8_t p_max_vl; /* Max num of virtual lanes */ 489 uint8_t p_init_type_reply; /* Optional InitTypeReply */ 490 ib_time_t p_subnet_timeout; /* Max Subnet Timeout */ 491 ibt_port_caps_t p_capabilities; /* Port Capabilities */ 492 uint32_t p_msg_sz; /* Max message size */ 493 } ibt_hca_portinfo_t; 494 495 /* 496 * Modify HCA port attributes flags, specifies which HCA port 497 * attributes to modify. 498 */ 499 typedef enum ibt_port_modify_flags_e { 500 IBT_PORT_NO_FLAGS = 0, 501 502 IBT_PORT_RESET_QKEY = 1 << 0, /* Reset Q_Key violation */ 503 /* counter */ 504 IBT_PORT_RESET_SM = 1 << 1, /* SM */ 505 IBT_PORT_SET_SM = 1 << 2, 506 IBT_PORT_RESET_SNMP = 1 << 3, /* SNMP Tunneling */ 507 IBT_PORT_SET_SNMP = 1 << 4, 508 IBT_PORT_RESET_DEVMGT = 1 << 5, /* Device Management */ 509 IBT_PORT_SET_DEVMGT = 1 << 6, 510 IBT_PORT_RESET_VENDOR = 1 << 7, /* Vendor Class */ 511 IBT_PORT_SET_VENDOR = 1 << 8, 512 IBT_PORT_SHUTDOWN = 1 << 9, /* Shut down the port */ 513 IBT_PORT_SET_INIT_TYPE = 1 << 10 /* InitTypeReply value */ 514 } ibt_port_modify_flags_t; 515 516 /* 517 * Modify HCA port InitType bit definitions, applicable only if 518 * IBT_PORT_SET_INIT_TYPE modify flag (ibt_port_modify_flags_t) is set. 519 */ 520 #define IBT_PINIT_NO_LOAD 0x1 521 #define IBT_PINIT_PRESERVE_CONTENT 0x2 522 #define IBT_PINIT_PRESERVE_PRESENCE 0x4 523 #define IBT_PINIT_NO_RESUSCITATE 0x8 524 525 526 /* 527 * Address vector definition. 528 */ 529 typedef struct ibt_adds_vect_s { 530 ib_gid_t av_dgid; /* IPV6 dest GID in GRH */ 531 ib_gid_t av_sgid; /* SGID */ 532 ibt_srate_t av_srate; /* Max static rate */ 533 uint8_t av_srvl:4; /* Service level in LRH */ 534 uint_t av_flow:20; /* 20 bit Flow Label */ 535 uint8_t av_tclass; /* Traffic Class */ 536 uint8_t av_hop; /* Hop Limit */ 537 uint8_t av_port_num; /* Port number for UD */ 538 boolean_t av_opaque1; 539 ib_lid_t av_opaque2; 540 ib_path_bits_t av_opaque3; 541 uint32_t av_opaque4; 542 } ibt_adds_vect_t; 543 544 typedef struct ibt_cep_path_s { 545 ibt_adds_vect_t cep_adds_vect; /* Address Vector */ 546 uint16_t cep_pkey_ix; /* P_Key Index */ 547 uint8_t cep_hca_port_num; /* Port number for connected */ 548 /* channels. A value of 0 */ 549 /* indicates an invalid path */ 550 ib_time_t cep_cm_opaque1; 551 } ibt_cep_path_t; 552 553 /* 554 * Channel Migration State. 555 */ 556 typedef enum ibt_cep_cmstate_e { 557 IBT_STATE_NOT_SUPPORTED = 0, 558 IBT_STATE_MIGRATED = 1, 559 IBT_STATE_REARMED = 2, 560 IBT_STATE_ARMED = 3 561 } ibt_cep_cmstate_t; 562 563 /* 564 * Transport service type 565 * 566 * NOTE: this was converted from an enum to a uint8_t to save space. 567 */ 568 typedef uint8_t ibt_tran_srv_t; 569 570 #define IBT_RC_SRV 0 571 #define IBT_UC_SRV 1 572 #define IBT_RD_SRV 2 573 #define IBT_UD_SRV 3 574 #define IBT_RAWIP_SRV 4 575 #define IBT_RAWETHER_SRV 5 576 577 /* 578 * Channel (QP/EEC) state definitions. 579 */ 580 typedef enum ibt_cep_state_e { 581 IBT_STATE_RESET = 0, /* Reset */ 582 IBT_STATE_INIT, /* Initialized */ 583 IBT_STATE_RTR, /* Ready to Receive */ 584 IBT_STATE_RTS, /* Ready to Send */ 585 IBT_STATE_SQD, /* Send Queue Drained */ 586 IBT_STATE_SQE, /* Send Queue Error */ 587 IBT_STATE_ERROR, /* Error */ 588 IBT_STATE_SQDRAIN, /* Send Queue Draining */ 589 IBT_STATE_NUM /* Number of states */ 590 } ibt_cep_state_t; 591 592 593 /* 594 * Channel Attribute flags. 595 */ 596 typedef enum ibt_attr_flags_e { 597 IBT_ALL_SIGNALED = 0, /* All sends signaled */ 598 IBT_WR_SIGNALED = 1, /* Signaled on a WR basis */ 599 IBT_FAST_REG_RES_LKEY = (1 << 1) 600 } ibt_attr_flags_t; 601 602 /* 603 * Channel End Point (CEP) Control Flags. 604 */ 605 typedef enum ibt_cep_flags_e { 606 IBT_CEP_NO_FLAGS = 0, /* Enable Nothing */ 607 IBT_CEP_RDMA_RD = (1 << 0), /* Enable incoming RDMA RD's */ 608 /* RC & RD only */ 609 IBT_CEP_RDMA_WR = (1 << 1), /* Enable incoming RDMA WR's */ 610 /* RC & RD only */ 611 IBT_CEP_ATOMIC = (1 << 2) /* Enable incoming Atomics, */ 612 /* RC & RD only */ 613 } ibt_cep_flags_t; 614 615 /* 616 * Channel Modify Flags 617 */ 618 typedef enum ibt_cep_modify_flags_e { 619 IBT_CEP_SET_NOTHING = 0, 620 IBT_CEP_SET_SQ_SIZE = (1 << 1), 621 IBT_CEP_SET_RQ_SIZE = (1 << 2), 622 623 IBT_CEP_SET_RDMA_R = (1 << 3), 624 IBT_CEP_SET_RDMA_W = (1 << 4), 625 IBT_CEP_SET_ATOMIC = (1 << 5), 626 627 IBT_CEP_SET_ALT_PATH = (1 << 6), /* Alternate Path */ 628 629 IBT_CEP_SET_ADDS_VECT = (1 << 7), 630 IBT_CEP_SET_PORT = (1 << 8), 631 IBT_CEP_SET_OPAQUE5 = (1 << 9), 632 IBT_CEP_SET_RETRY = (1 << 10), 633 IBT_CEP_SET_RNR_NAK_RETRY = (1 << 11), 634 IBT_CEP_SET_MIN_RNR_NAK = (1 << 12), 635 636 IBT_CEP_SET_QKEY = (1 << 13), 637 IBT_CEP_SET_RDMARA_OUT = (1 << 14), 638 IBT_CEP_SET_RDMARA_IN = (1 << 15), 639 640 IBT_CEP_SET_OPAQUE1 = (1 << 16), 641 IBT_CEP_SET_OPAQUE2 = (1 << 17), 642 IBT_CEP_SET_OPAQUE3 = (1 << 18), 643 IBT_CEP_SET_OPAQUE4 = (1 << 19), 644 IBT_CEP_SET_SQD_EVENT = (1 << 20), 645 IBT_CEP_SET_OPAQUE6 = (1 << 21), 646 IBT_CEP_SET_OPAQUE7 = (1 << 22), 647 IBT_CEP_SET_OPAQUE8 = (1 << 23) 648 } ibt_cep_modify_flags_t; 649 650 /* 651 * CQ notify types. 652 */ 653 typedef enum ibt_cq_notify_flags_e { 654 IBT_NEXT_COMPLETION = 1, 655 IBT_NEXT_SOLICITED = 2 656 } ibt_cq_notify_flags_t; 657 658 /* 659 * CQ types shared across TI and CI. 660 */ 661 typedef enum ibt_cq_flags_e { 662 IBT_CQ_NO_FLAGS = 0, 663 IBT_CQ_HANDLER_IN_THREAD = 1 << 0, /* A thread calls the */ 664 /* CQ handler */ 665 IBT_CQ_USER_MAP = 1 << 1, 666 IBT_CQ_DEFER_ALLOC = 1 << 2 667 } ibt_cq_flags_t; 668 669 /* 670 * CQ types shared across TI and CI. 671 */ 672 typedef enum ibt_cq_sched_flags_e { 673 IBT_CQS_NO_FLAGS = 0, 674 IBT_CQS_WARM_CACHE = 1 << 0, /* run on same CPU */ 675 IBT_CQS_AFFINITY = 1 << 1, 676 IBT_CQS_SCHED_GROUP = 1 << 2, 677 IBT_CQS_USER_MAP = 1 << 3, 678 IBT_CQS_DEFER_ALLOC = 1 << 4 679 } ibt_cq_sched_flags_t; 680 681 /* 682 * Attributes when creating a Completion Queue. 683 * 684 * Note: 685 * The IBT_CQ_HANDLER_IN_THREAD cq_flags bit should be ignored by the CI. 686 */ 687 typedef struct ibt_cq_attr_s { 688 uint_t cq_size; 689 ibt_sched_hdl_t cq_sched; /* 0 = no hint, */ 690 /* other = cq_sched value */ 691 ibt_cq_flags_t cq_flags; 692 } ibt_cq_attr_t; 693 694 /* 695 * Memory Management 696 */ 697 698 /* Memory management flags */ 699 typedef enum ibt_mr_flags_e { 700 IBT_MR_SLEEP = 0, 701 IBT_MR_NOSLEEP = (1 << 1), 702 IBT_MR_NONCOHERENT = (1 << 2), 703 IBT_MR_PHYS_IOVA = (1 << 3), /* ibt_(re)register_buf */ 704 705 /* Access control flags */ 706 IBT_MR_ENABLE_WINDOW_BIND = (1 << 4), 707 IBT_MR_ENABLE_LOCAL_WRITE = (1 << 5), 708 IBT_MR_ENABLE_REMOTE_READ = (1 << 6), 709 IBT_MR_ENABLE_REMOTE_WRITE = (1 << 7), 710 IBT_MR_ENABLE_REMOTE_ATOMIC = (1 << 8), 711 712 /* Reregister flags */ 713 IBT_MR_CHANGE_TRANSLATION = (1 << 9), 714 IBT_MR_CHANGE_ACCESS = (1 << 10), 715 IBT_MR_CHANGE_PD = (1 << 11), 716 717 /* Additional registration flags */ 718 IBT_MR_ZBVA = (1 << 12), 719 720 /* Additional physical registration flags */ 721 IBT_MR_CONSUMER_KEY = (1 << 13) /* Consumer owns key */ 722 /* portion of keys */ 723 } ibt_mr_flags_t; 724 725 726 /* Memory Region attribute flags */ 727 typedef enum ibt_mr_attr_flags_e { 728 /* Access control flags */ 729 IBT_MR_WINDOW_BIND = (1 << 0), 730 IBT_MR_LOCAL_WRITE = (1 << 1), 731 IBT_MR_REMOTE_READ = (1 << 2), 732 IBT_MR_REMOTE_WRITE = (1 << 3), 733 IBT_MR_REMOTE_ATOMIC = (1 << 4), 734 IBT_MR_ZERO_BASED_VA = (1 << 5), 735 IBT_MR_CONSUMER_OWNED_KEY = (1 << 6), 736 IBT_MR_SHARED = (1 << 7) 737 } ibt_mr_attr_flags_t; 738 739 /* Memory region physical descriptor. */ 740 typedef struct ibt_phys_buf_s { 741 union { 742 uint64_t _p_ll; /* 64 bit DMA address */ 743 uint32_t _p_la[2]; /* 2 x 32 bit address */ 744 } _phys_buf; 745 size_t p_size; 746 } ibt_phys_buf_t; 747 748 #define p_laddr _phys_buf._p_ll 749 #ifdef _LONG_LONG_HTOL 750 #define p_notused _phys_buf._p_la[0] 751 #define p_addr _phys_buf._p_la[1] 752 #else 753 #define p_addr _phys_buf._p_la[0] 754 #define p_notused _phys_buf._p_la[1] 755 #endif 756 757 758 /* Memory region descriptor. */ 759 typedef struct ibt_mr_desc_s { 760 ib_vaddr_t md_vaddr; /* IB virtual adds of memory */ 761 ibt_lkey_t md_lkey; 762 ibt_rkey_t md_rkey; 763 boolean_t md_sync_required; 764 } ibt_mr_desc_t; 765 766 /* Physical Memory region descriptor. */ 767 typedef struct ibt_pmr_desc_s { 768 ib_vaddr_t pmd_iova; /* Returned I/O Virtual Address */ 769 ibt_lkey_t pmd_lkey; 770 ibt_rkey_t pmd_rkey; 771 uint_t pmd_phys_buf_list_sz; /* Allocated Phys buf sz */ 772 boolean_t pmd_sync_required; 773 } ibt_pmr_desc_t; 774 775 /* Memory region protection bounds. */ 776 typedef struct ibt_mr_prot_bounds_s { 777 ib_vaddr_t pb_addr; /* Beginning address */ 778 size_t pb_len; /* Length of protected region */ 779 } ibt_mr_prot_bounds_t; 780 781 /* Memory Region (Re)Register attributes */ 782 typedef struct ibt_mr_attr_s { 783 ib_vaddr_t mr_vaddr; /* Virtual address to register */ 784 ib_memlen_t mr_len; /* Length of region to register */ 785 struct as *mr_as; /* A pointer to an address space */ 786 /* structure. This parameter should */ 787 /* be set to NULL, which implies */ 788 /* kernel address space. */ 789 ibt_mr_flags_t mr_flags; 790 } ibt_mr_attr_t; 791 792 /* Physical Memory Region (Re)Register */ 793 typedef struct ibt_pmr_attr_s { 794 ib_vaddr_t pmr_iova; /* I/O virtual address requested by */ 795 /* client for the first byte of the */ 796 /* region */ 797 ib_memlen_t pmr_len; /* Length of region to register */ 798 ib_memlen_t pmr_offset; /* Offset of the regions starting */ 799 /* IOVA within the 1st physical */ 800 /* buffer */ 801 ibt_mr_flags_t pmr_flags; 802 ibt_lkey_t pmr_lkey; /* Reregister only */ 803 ibt_rkey_t pmr_rkey; /* Reregister only */ 804 uint8_t pmr_key; /* Key to use on new Lkey & Rkey */ 805 uint_t pmr_num_buf; /* Num of entries in the mr_buf_list */ 806 ibt_phys_buf_t *pmr_buf_list; /* List of physical buffers accessed */ 807 /* as an array */ 808 } ibt_pmr_attr_t; 809 810 811 /* 812 * Memory Region (Re)Register attributes - used by ibt_register_shared_mr(), 813 * ibt_register_buf() and ibt_reregister_buf(). 814 */ 815 typedef struct ibt_smr_attr_s { 816 ib_vaddr_t mr_vaddr; 817 ibt_mr_flags_t mr_flags; 818 uint8_t mr_key; /* Only for physical */ 819 /* ibt_(Re)register_buf() */ 820 ibt_lkey_t mr_lkey; /* Only for physical */ 821 ibt_rkey_t mr_rkey; /* ibt_Reregister_buf() */ 822 } ibt_smr_attr_t; 823 824 /* 825 * key states. 826 */ 827 typedef enum ibt_key_state_e { 828 IBT_KEY_INVALID = 0, 829 IBT_KEY_FREE, 830 IBT_KEY_VALID 831 } ibt_key_state_t; 832 833 /* Memory region query attributes */ 834 typedef struct ibt_mr_query_attr_s { 835 ibt_lkey_t mr_lkey; 836 ibt_rkey_t mr_rkey; 837 ibt_mr_prot_bounds_t mr_lbounds; /* Actual local CI protection */ 838 /* bounds */ 839 ibt_mr_prot_bounds_t mr_rbounds; /* Actual remote CI */ 840 /* protection bounds */ 841 ibt_mr_attr_flags_t mr_attr_flags; /* Access rights etc. */ 842 ibt_pd_hdl_t mr_pd; /* Protection domain */ 843 boolean_t mr_sync_required; 844 ibt_key_state_t mr_lkey_state; 845 uint_t mr_phys_buf_list_sz; 846 } ibt_mr_query_attr_t; 847 848 /* Memory window query attributes */ 849 typedef struct ibt_mw_query_attr_s { 850 ibt_pd_hdl_t mw_pd; 851 ibt_mem_win_type_t mw_type; 852 ibt_rkey_t mw_rkey; 853 ibt_key_state_t mw_state; 854 } ibt_mw_query_attr_t; 855 856 857 /* Memory Region Sync Flags. */ 858 #define IBT_SYNC_READ 0x1 /* Make memory changes visible to incoming */ 859 /* RDMA reads */ 860 861 #define IBT_SYNC_WRITE 0x2 /* Make the affects of an incoming RDMA write */ 862 /* visible to the consumer */ 863 864 /* Memory region sync args */ 865 typedef struct ibt_mr_sync_s { 866 ibt_mr_hdl_t ms_handle; 867 ib_vaddr_t ms_vaddr; 868 ib_memlen_t ms_len; 869 uint32_t ms_flags; /* IBT_SYNC_READ or IBT_SYNC_WRITE */ 870 } ibt_mr_sync_t; 871 872 /* 873 * Flags for Virtual Address to HCA Physical Address translation. 874 */ 875 typedef enum ibt_va_flags_e { 876 IBT_VA_NO_FLAGS = 0 877 } ibt_va_flags_t; 878 879 880 /* Address Translation parameters */ 881 typedef struct ibt_va_attr_s { 882 ib_vaddr_t va_vaddr; /* Virtual address to register */ 883 ib_memlen_t va_len; /* Length of region to register */ 884 struct as *va_as; /* A pointer to an address space */ 885 /* structure. */ 886 ibt_va_flags_t va_flags; 887 } ibt_va_attr_t; 888 889 /* 890 * WORK REQUEST AND WORK REQUEST COMPLETION DEFINITIONS. 891 */ 892 893 /* 894 * Work Request and Work Request Completion types - These types are used 895 * to indicate the type of work requests posted to a work queue 896 * or the type of completion received. Immediate Data is indicated via 897 * ibt_wr_flags_t or ibt_wc_flags_t. 898 * 899 * IBT_WRC_RECV and IBT_WRC_RECV_RDMAWI are only used as opcodes in the 900 * work completions. 901 * 902 * NOTE: this was converted from an enum to a uint8_t to save space. 903 */ 904 typedef uint8_t ibt_wrc_opcode_t; 905 906 #define IBT_WRC_SEND 1 /* Send */ 907 #define IBT_WRC_RDMAR 2 /* RDMA Read */ 908 #define IBT_WRC_RDMAW 3 /* RDMA Write */ 909 #define IBT_WRC_CSWAP 4 /* Compare & Swap Atomic */ 910 #define IBT_WRC_FADD 5 /* Fetch & Add Atomic */ 911 #define IBT_WRC_BIND 6 /* Bind Memory Window */ 912 #define IBT_WRC_RECV 7 /* Receive */ 913 #define IBT_WRC_RECV_RDMAWI 8 /* Received RDMA Write w/ Immediate */ 914 #define IBT_WRC_FAST_REG_PMR 9 /* Fast Register Physical mem region */ 915 #define IBT_WRC_LOCAL_INVALIDATE 10 916 917 918 /* 919 * Work Request Completion flags - These flags indicate what type 920 * of data is present in the Work Request Completion structure 921 */ 922 typedef uint8_t ibt_wc_flags_t; 923 924 #define IBT_WC_NO_FLAGS 0 925 #define IBT_WC_GRH_PRESENT (1 << 0) 926 #define IBT_WC_IMMED_DATA_PRESENT (1 << 1) 927 #define IBT_WC_RKEY_INVALIDATED (1 << 2) 928 #define IBT_WC_CKSUM_OK (1 << 3) 929 930 931 /* 932 * Work Request Completion - This structure encapsulates the information 933 * necessary to define a work request completion. 934 */ 935 typedef struct ibt_wc_s { 936 ibt_wrid_t wc_id; /* Work Request Id */ 937 uint64_t wc_fma_ena; /* fault management err data */ 938 ib_msglen_t wc_bytes_xfer; /* Number of Bytes */ 939 /* Transferred */ 940 ibt_wc_flags_t wc_flags; /* WR Completion Flags */ 941 ibt_wrc_opcode_t wc_type; /* Operation Type */ 942 uint16_t wc_cksum; /* payload checksum */ 943 ibt_immed_t wc_immed_data; /* Immediate Data */ 944 uint32_t wc_freed_rc; /* Freed Resource Count */ 945 ibt_wc_status_t wc_status; /* Completion Status */ 946 uint8_t wc_sl:4; /* Remote SL */ 947 uint16_t wc_ethertype; /* Ethertype Field - RE */ 948 ib_lid_t wc_opaque1; 949 uint16_t wc_opaque2; 950 ib_qpn_t wc_qpn; /* Source QPN Datagram only */ 951 ib_eecn_t wc_opaque3; 952 ib_qpn_t wc_local_qpn; 953 ibt_rkey_t wc_rkey; 954 ib_path_bits_t wc_opaque4; 955 } ibt_wc_t; 956 957 958 /* 959 * WR Flags. Common for both RC and UD 960 * 961 * NOTE: this was converted from an enum to a uint8_t to save space. 962 */ 963 typedef uint8_t ibt_wr_flags_t; 964 965 #define IBT_WR_NO_FLAGS 0 966 #define IBT_WR_SEND_IMMED (1 << 0) /* Immediate Data Indicator */ 967 #define IBT_WR_SEND_SIGNAL (1 << 1) /* Signaled, if set */ 968 #define IBT_WR_SEND_FENCE (1 << 2) /* Fence Indicator */ 969 #define IBT_WR_SEND_SOLICIT (1 << 3) /* Solicited Event Indicator */ 970 #define IBT_WR_SEND_REMOTE_INVAL (1 << 4) /* Remote Invalidate */ 971 #define IBT_WR_SEND_CKSUM (1 << 5) /* Checksum offload Indicator */ 972 973 /* 974 * Access control flags for Bind Memory Window operation, 975 * applicable for RC/UC/RD only. 976 * 977 * If IBT_WR_BIND_WRITE or IBT_WR_BIND_ATOMIC is desired then 978 * it is required that Memory Region should have Local Write Access. 979 */ 980 typedef enum ibt_bind_flags_e { 981 IBT_WR_BIND_READ = (1 << 0), /* enable remote read */ 982 IBT_WR_BIND_WRITE = (1 << 1), /* enable remote write */ 983 IBT_WR_BIND_ATOMIC = (1 << 2), /* enable remote atomics */ 984 IBT_WR_BIND_ZBVA = (1 << 3) /* Zero Based Virtual Address */ 985 } ibt_bind_flags_t; 986 987 /* 988 * Data Segment for scatter-gather list 989 * 990 * SGL consists of an array of data segments and the length of the SGL. 991 */ 992 typedef struct ibt_wr_ds_s { 993 ib_vaddr_t ds_va; /* Virtual Address */ 994 ibt_lkey_t ds_key; /* L_Key */ 995 ib_msglen_t ds_len; /* Length of DS */ 996 } ibt_wr_ds_t; 997 998 /* 999 * Bind Memory Window WR 1000 * 1001 * WR ID from ibt_send_wr_t applies here too, SWG_0038 errata. 1002 */ 1003 typedef struct ibt_wr_bind_s { 1004 ibt_bind_flags_t bind_flags; 1005 ibt_rkey_t bind_rkey; /* Mem Window's R_key */ 1006 ibt_lkey_t bind_lkey; /* Mem Region's L_Key */ 1007 ibt_rkey_t bind_rkey_out; /* OUT: new R_Key */ 1008 ibt_mr_hdl_t bind_ibt_mr_hdl; /* Mem Region handle */ 1009 ibt_mw_hdl_t bind_ibt_mw_hdl; /* Mem Window handle */ 1010 ib_vaddr_t bind_va; /* Virtual Address */ 1011 ib_memlen_t bind_len; /* Length of Window */ 1012 } ibt_wr_bind_t; 1013 1014 /* 1015 * Atomic WR 1016 * 1017 * Operation type (compare & swap or fetch & add) in ibt_wrc_opcode_t. 1018 * 1019 * A copy of the original contents of the remote memory will be stored 1020 * in the local data segment described by wr_sgl within ibt_send_wr_t, 1021 * and wr_nds should be set to 1. 1022 * 1023 * Atomic operation operands: 1024 * Compare & Swap Operation: 1025 * atom_arg1 - Compare Operand 1026 * atom_arg2 - Swap Operand 1027 * 1028 * Fetch & Add Operation: 1029 * atom_arg1 - Add Operand 1030 * atom_arg2 - ignored 1031 */ 1032 typedef struct ibt_wr_atomic_s { 1033 ib_vaddr_t atom_raddr; /* Remote address. */ 1034 ibt_atom_arg_t atom_arg1; /* operand #1 */ 1035 ibt_atom_arg_t atom_arg2; /* operand #2 */ 1036 ibt_rkey_t atom_rkey; /* R_Key. */ 1037 } ibt_wr_atomic_t; 1038 1039 /* 1040 * RDMA WR 1041 * Immediate Data indicator in ibt_wr_flags_t. 1042 */ 1043 typedef struct ibt_wr_rdma_s { 1044 ib_vaddr_t rdma_raddr; /* Remote address. */ 1045 ibt_rkey_t rdma_rkey; /* R_Key. */ 1046 ibt_immed_t rdma_immed; /* Immediate Data */ 1047 } ibt_wr_rdma_t; 1048 1049 /* 1050 * Fast Register Physical Memory Region Work Request. 1051 */ 1052 typedef struct ibt_wr_reg_pmr_s { 1053 ib_vaddr_t pmr_iova; /* I/O virtual address requested by */ 1054 /* client for the first byte of the */ 1055 /* region */ 1056 ib_memlen_t pmr_len; /* Length of region to register */ 1057 ib_memlen_t pmr_offset; /* Offset of the regions starting */ 1058 /* IOVA within the 1st physical */ 1059 /* buffer */ 1060 ibt_mr_hdl_t pmr_mr_hdl; 1061 ibt_phys_buf_t *pmr_buf_list; /* List of physical buffers accessed */ 1062 /* as an array */ 1063 uint_t pmr_num_buf; /* Num of entries in the pmr_buf_list */ 1064 ibt_lkey_t pmr_lkey; 1065 ibt_rkey_t pmr_rkey; 1066 ibt_mr_flags_t pmr_flags; 1067 uint8_t pmr_key; /* Key to use on new Lkey & Rkey */ 1068 } ibt_wr_reg_pmr_t; 1069 1070 /* 1071 * Local Invalidate. 1072 */ 1073 typedef struct ibt_wr_li_s { 1074 ibt_mr_hdl_t li_mr_hdl; /* Null for MW invalidates */ 1075 ibt_mw_hdl_t li_mw_hdl; /* Null for MR invalidates */ 1076 ibt_lkey_t li_lkey; /* Ignore for MW invalidates */ 1077 ibt_rkey_t li_rkey; 1078 } ibt_wr_li_t; 1079 1080 /* 1081 * Reserved For Future Use. 1082 * Raw IPv6 Send WR 1083 */ 1084 typedef struct ibt_wr_ripv6_s { 1085 ib_lid_t rip_dlid; /* DLID */ 1086 ib_path_bits_t rip_slid_bits; /* SLID path bits, SWG_0033 errata */ 1087 uint8_t rip_sl:4; /* SL */ 1088 ibt_srate_t rip_rate; /* Max Static Rate, SWG_0007 errata */ 1089 } ibt_wr_ripv6_t; 1090 1091 /* 1092 * Reserved For Future Use. 1093 * Raw Ethertype Send WR 1094 */ 1095 typedef struct ibt_wr_reth_s { 1096 ib_ethertype_t reth_type; /* Ethertype */ 1097 ib_lid_t reth_dlid; /* DLID */ 1098 ib_path_bits_t reth_slid_bits; /* SLID path bits, SWG_0033 errata */ 1099 uint8_t reth_sl:4; /* SL */ 1100 ibt_srate_t reth_rate; /* Max Static Rate, SWG_0007 errata */ 1101 } ibt_wr_reth_t; 1102 1103 /* 1104 * Reserved For future Use. 1105 * RD Send WR, Operation type in ibt_wrc_opcode_t. 1106 */ 1107 typedef struct ibt_wr_rd_s { 1108 ibt_rd_dest_hdl_t rdwr_dest_hdl; 1109 union { 1110 ibt_immed_t send_immed; /* IBT_WRC_SEND */ 1111 ibt_wr_rdma_t rdma; /* IBT_WRC_RDMAR */ 1112 /* IBT_WRC_RDMAW */ 1113 ibt_wr_li_t *li; /* IBT_WRC_LOCAL_INVALIDATE */ 1114 ibt_wr_atomic_t *atomic; /* IBT_WRC_FADD */ 1115 /* IBT_WRC_CSWAP */ 1116 ibt_wr_bind_t *bind; /* IBT_WRC_BIND */ 1117 ibt_wr_reg_pmr_t *reg_pmr; /* IBT_WRC_FAST_REG_PMR */ 1118 } rdwr; 1119 } ibt_wr_rd_t; 1120 1121 /* 1122 * Reserved For Future Use. 1123 * UC Send WR, Operation type in ibt_wrc_opcode_t, the only valid 1124 * ones are: 1125 * IBT_WRC_SEND 1126 * IBT_WRC_RDMAW 1127 * IBT_WRC_BIND 1128 */ 1129 typedef struct ibt_wr_uc_s { 1130 union { 1131 ibt_immed_t send_immed; /* IBT_WRC_SEND */ 1132 ibt_wr_rdma_t rdma; /* IBT_WRC_RDMAW */ 1133 ibt_wr_li_t *li; /* IBT_WRC_LOCAL_INVALIDATE */ 1134 ibt_wr_bind_t *bind; /* IBT_WRC_BIND */ 1135 ibt_wr_reg_pmr_t *reg_pmr; /* IBT_WRC_FAST_REG_PMR */ 1136 } ucwr; 1137 } ibt_wr_uc_t; 1138 1139 /* 1140 * RC Send WR, Operation type in ibt_wrc_opcode_t. 1141 */ 1142 typedef struct ibt_wr_rc_s { 1143 union { 1144 ibt_immed_t send_immed; /* IBT_WRC_SEND w/ immediate */ 1145 ibt_rkey_t send_inval; /* IBT_WRC_SEND w/ invalidate */ 1146 ibt_wr_rdma_t rdma; /* IBT_WRC_RDMAR */ 1147 /* IBT_WRC_RDMAW */ 1148 ibt_wr_li_t *li; /* IBT_WRC_LOCAL_INVALIDATE */ 1149 ibt_wr_atomic_t *atomic; /* IBT_WRC_CSWAP */ 1150 /* IBT_WRC_FADD */ 1151 ibt_wr_bind_t *bind; /* IBT_WRC_BIND */ 1152 ibt_wr_reg_pmr_t *reg_pmr; /* IBT_WRC_FAST_REG_PMR */ 1153 } rcwr; 1154 } ibt_wr_rc_t; 1155 1156 /* 1157 * UD Send WR, the only valid Operation is IBT_WRC_SEND. 1158 */ 1159 typedef struct ibt_wr_ud_s { 1160 ibt_immed_t udwr_immed; 1161 ibt_ud_dest_hdl_t udwr_dest; 1162 } ibt_wr_ud_t; 1163 1164 /* 1165 * Send Work Request (WR) attributes structure. 1166 * 1167 * Operation type in ibt_wrc_opcode_t. 1168 * Immediate Data indicator in ibt_wr_flags_t. 1169 */ 1170 typedef struct ibt_send_wr_s { 1171 ibt_wrid_t wr_id; /* WR ID */ 1172 ibt_wr_flags_t wr_flags; /* Work Request Flags. */ 1173 ibt_tran_srv_t wr_trans; /* Transport Type. */ 1174 ibt_wrc_opcode_t wr_opcode; /* Operation Type. */ 1175 uint8_t wr_rsvd; /* maybe later */ 1176 uint32_t wr_nds; /* Number of data segments */ 1177 /* pointed to by wr_sgl */ 1178 ibt_wr_ds_t *wr_sgl; /* SGL */ 1179 union { 1180 ibt_wr_ud_t ud; 1181 ibt_wr_rc_t rc; 1182 ibt_wr_rd_t rd; /* Reserved For Future Use */ 1183 ibt_wr_uc_t uc; /* Reserved For Future Use */ 1184 ibt_wr_reth_t reth; /* Reserved For Future Use */ 1185 ibt_wr_ripv6_t ripv6; /* Reserved For Future Use */ 1186 } wr; /* operation specific */ 1187 } ibt_send_wr_t; 1188 1189 /* 1190 * Receive Work Request (WR) attributes structure. 1191 */ 1192 typedef struct ibt_recv_wr_s { 1193 ibt_wrid_t wr_id; /* WR ID */ 1194 uint32_t wr_nds; /* number of data segments */ 1195 /* pointed to by wr_sgl */ 1196 ibt_wr_ds_t *wr_sgl; /* SGL */ 1197 } ibt_recv_wr_t; 1198 1199 1200 /* 1201 * Asynchronous Events and Errors. 1202 * 1203 * The following codes are not used in calls to ibc_async_handler, but 1204 * are used by IBTL to inform IBT clients of a significant event. 1205 * 1206 * IBT_HCA_ATTACH_EVENT - New HCA available. 1207 * IBT_HCA_DETACH_EVENT - HCA is requesting not to be used. 1208 * 1209 * ERRORs on a channel indicate that the channel has entered error state. 1210 * EVENTs on a channel indicate that the channel has not changed state. 1211 * 1212 */ 1213 typedef enum ibt_async_code_e { 1214 IBT_EVENT_PATH_MIGRATED = 0x000001, 1215 IBT_EVENT_SQD = 0x000002, 1216 IBT_EVENT_COM_EST = 0x000004, 1217 IBT_ERROR_CATASTROPHIC_CHAN = 0x000008, 1218 IBT_ERROR_INVALID_REQUEST_CHAN = 0x000010, 1219 IBT_ERROR_ACCESS_VIOLATION_CHAN = 0x000020, 1220 IBT_ERROR_PATH_MIGRATE_REQ = 0x000040, 1221 1222 IBT_ERROR_CQ = 0x000080, 1223 1224 IBT_EVENT_PORT_UP = 0x000100, 1225 IBT_ERROR_PORT_DOWN = 0x000200, 1226 IBT_ERROR_LOCAL_CATASTROPHIC = 0x000400, 1227 1228 IBT_HCA_ATTACH_EVENT = 0x000800, 1229 IBT_HCA_DETACH_EVENT = 0x001000, 1230 IBT_ASYNC_OPAQUE1 = 0x002000, 1231 IBT_ASYNC_OPAQUE2 = 0x004000, 1232 IBT_ASYNC_OPAQUE3 = 0x008000, 1233 IBT_ASYNC_OPAQUE4 = 0x010000, 1234 IBT_EVENT_LIMIT_REACHED_SRQ = 0x020000, 1235 IBT_EVENT_EMPTY_CHAN = 0x040000, 1236 IBT_ERROR_CATASTROPHIC_SRQ = 0x080000 1237 } ibt_async_code_t; 1238 1239 1240 /* 1241 * ibt_ci_data_in() and ibt_ci_data_out() flags. 1242 */ 1243 typedef enum ibt_ci_data_flags_e { 1244 IBT_CI_NO_FLAGS = 0, 1245 IBT_CI_COMPLETE_ALLOC = (1 << 0) 1246 } ibt_ci_data_flags_t; 1247 1248 /* 1249 * Used by ibt_ci_data_in() and ibt_ci_data_out() identifies the type of handle 1250 * mapping data is being obtained for. 1251 */ 1252 typedef enum ibt_object_type_e { 1253 IBT_HDL_HCA = 1, 1254 IBT_HDL_CHANNEL, 1255 IBT_HDL_CQ, 1256 IBT_HDL_PD, 1257 IBT_HDL_MR, 1258 IBT_HDL_MW, 1259 IBT_HDL_UD_DEST, 1260 IBT_HDL_SCHED, 1261 IBT_HDL_OPAQUE1, 1262 IBT_HDL_OPAQUE2, 1263 IBT_HDL_SRQ 1264 } ibt_object_type_t; 1265 1266 /* 1267 * Memory error handler data structures; code, and payload data. 1268 */ 1269 typedef enum ibt_mem_code_s { 1270 IBT_MEM_AREA = 0x1, 1271 IBT_MEM_REGION = 0x2 1272 } ibt_mem_code_t; 1273 1274 typedef struct ibt_mem_data_s { 1275 uint64_t ev_fma_ena; /* FMA Error data */ 1276 ibt_mr_hdl_t ev_mr_hdl; /* MR handle */ 1277 ibt_ma_hdl_t ev_ma_hdl; /* MA handle */ 1278 } ibt_mem_data_t; 1279 1280 /* 1281 * Special case failure type. 1282 */ 1283 typedef enum ibt_failure_type_e { 1284 IBT_FAILURE_STANDARD = 0, 1285 IBT_FAILURE_CI, 1286 IBT_FAILURE_IBMF, 1287 IBT_FAILURE_IBTL, 1288 IBT_FAILURE_IBCM, 1289 IBT_FAILURE_IBDM 1290 } ibt_failure_type_t; 1291 1292 #ifdef __cplusplus 1293 } 1294 #endif 1295 1296 #endif /* _SYS_IB_IBTL_IBTL_TYPES_H */ 1297