1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_IB_IBTL_IBTL_TYPES_H 27 #define _SYS_IB_IBTL_IBTL_TYPES_H 28 29 /* 30 * ibtl_types.h 31 * 32 * All common IBTL defined types. These are common data types 33 * that are shared by the IBTI and IBCI interfaces, it is only included 34 * by ibti.h and ibci.h 35 */ 36 #include <sys/ddi.h> 37 #include <sys/sunddi.h> 38 #include <sys/ib/ib_types.h> 39 #include <sys/ib/ibtl/ibtl_status.h> 40 #include <sys/socket.h> 41 #include <sys/byteorder.h> 42 43 44 #ifdef __cplusplus 45 extern "C" { 46 #endif 47 48 /* 49 * Endian Macros 50 * h2b - host endian to big endian protocol 51 * b2h - big endian protocol to host endian 52 * h2l - host endian to little endian protocol 53 * l2h - little endian protocol to host endian 54 */ 55 #if defined(_LITTLE_ENDIAN) 56 #define h2b16(x) (htons(x)) 57 #define h2b32(x) (htonl(x)) 58 #define h2b64(x) (htonll(x)) 59 #define b2h16(x) (ntohs(x)) 60 #define b2h32(x) (ntohl(x)) 61 #define b2h64(x) (htonll(x)) 62 63 #define h2l16(x) (x) 64 #define h2l32(x) (x) 65 #define h2l64(x) (x) 66 #define l2h16(x) (x) 67 #define l2h32(x) (x) 68 #define l2h64(x) (x) 69 70 #elif defined(_BIG_ENDIAN) 71 #define h2b16(x) (x) 72 #define h2b32(x) (x) 73 #define h2b64(x) (x) 74 #define b2h16(x) (x) 75 #define b2h32(x) (x) 76 #define b2h64(x) (x) 77 78 #define h2l16(x) (ddi_swap16(x)) 79 #define h2l32(x) (ddi_swap32(x)) 80 #define h2l64(x) (ddi_swap64(x)) 81 #define l2h16(x) (ddi_swap16(x)) 82 #define l2h32(x) (ddi_swap32(x)) 83 #define l2h64(x) (ddi_swap64(x)) 84 85 #else 86 #error "what endian is this machine?" 87 #endif 88 89 /* 90 * Define Internal IBTL handles 91 */ 92 typedef struct ibtl_clnt_s *ibt_clnt_hdl_t; /* ibt_attach() */ 93 typedef struct ibtl_hca_s *ibt_hca_hdl_t; /* ibt_open_hca() */ 94 typedef struct ibtl_channel_s *ibt_channel_hdl_t; /* alloc_rc|ud_channel() */ 95 typedef struct ibtl_srq_s *ibt_srq_hdl_t; /* ibt_alloc_srq() */ 96 typedef struct ibtl_cq_s *ibt_cq_hdl_t; /* ibt_alloc_cq() */ 97 typedef struct ibcm_svc_info_s *ibt_srv_hdl_t; /* ibt_register_service() */ 98 typedef struct ibcm_svc_bind_s *ibt_sbind_hdl_t; /* ibt_bind_service() */ 99 100 typedef struct ibc_fmr_pool_s *ibt_fmr_pool_hdl_t; /* ibt_create_fmr_pool() */ 101 typedef struct ibc_ma_s *ibt_ma_hdl_t; /* ibt_map_mem_area() */ 102 typedef struct ibc_pd_s *ibt_pd_hdl_t; /* ibt_alloc_pd() */ 103 typedef struct ibc_sched_s *ibt_sched_hdl_t; /* ibt_alloc_cq_sched() */ 104 typedef struct ibc_mr_s *ibt_mr_hdl_t; /* ibt_register_mr() */ 105 typedef struct ibc_mw_s *ibt_mw_hdl_t; /* ibt_alloc_mw() */ 106 typedef struct ibt_ud_dest_s *ibt_ud_dest_hdl_t; /* UD dest handle */ 107 typedef struct ibc_ah_s *ibt_ah_hdl_t; /* ibt_alloc_ah() */ 108 typedef struct ibtl_eec_s *ibt_eec_hdl_t; 109 typedef struct ibt_rd_dest_s *ibt_rd_dest_hdl_t; /* Reserved for */ 110 /* Future use */ 111 typedef struct ibc_mem_alloc_s *ibt_mem_alloc_hdl_t; /* ibt_alloc_io_mem() */ 112 typedef struct ibc_mi_s *ibt_mi_hdl_t; /* ibt_map_mem_iov() */ 113 114 /* 115 * Some General Types. 116 */ 117 typedef uint32_t ibt_lkey_t; /* L_Key */ 118 typedef uint32_t ibt_rkey_t; /* R_Key */ 119 typedef uint64_t ibt_wrid_t; /* Client assigned WR ID */ 120 typedef uint32_t ibt_immed_t; /* WR Immediate Data */ 121 typedef uint64_t ibt_atom_arg_t; /* WR Atomic Operation arg */ 122 typedef uint_t ibt_cq_handler_id_t; /* Event handler ID */ 123 124 /* 125 * IBT selector type, used when looking up/requesting either an 126 * MTU, Pkt lifetime, or Static rate. 127 * The interpretation of IBT_BEST depends on the attribute being selected. 128 */ 129 typedef enum ibt_selector_e { 130 IBT_GT = 0, /* Greater than */ 131 IBT_LT = 1, /* Less than */ 132 IBT_EQU = 2, /* Equal to */ 133 IBT_BEST = 3 /* Best */ 134 } ibt_selector_t; 135 136 137 /* 138 * Static rate definitions. 139 */ 140 typedef enum ibt_srate_e { 141 IBT_SRATE_NOT_SPECIFIED = 0, 142 IBT_SRATE_2 = 2, /* 1X SDR i.e 2.5 Gbps */ 143 IBT_SRATE_10 = 3, /* 4X SDR or 1X QDR i.e 10 Gbps */ 144 IBT_SRATE_30 = 4, /* 12X SDR i.e 30 Gbps */ 145 146 IBT_SRATE_5 = 5, /* 1X DDR i.e 5 Gbps */ 147 IBT_SRATE_20 = 6, /* 4X DDR or 8X SDR i.e 20 Gbps */ 148 IBT_SRATE_40 = 7, /* 8X DDR or 4X QDR i.e 40 Gbps */ 149 150 IBT_SRATE_60 = 8, /* 12X DDR i.e 60 Gbps */ 151 IBT_SRATE_80 = 9, /* 8X QDR i.e 80 Gbps */ 152 IBT_SRATE_120 = 10 /* 12X QDR i.e 120 Gbps */ 153 } ibt_srate_t; 154 155 /* retain old definition to be compatible with older bits. */ 156 #define IBT_SRATE_1X IBT_SRATE_2 157 #define IBT_SRATE_4X IBT_SRATE_10 158 #define IBT_SRATE_12X IBT_SRATE_30 159 160 /* 161 * Static rate request type. 162 */ 163 typedef struct ibt_srate_req_s { 164 ibt_srate_t r_srate; /* Requested srate */ 165 ibt_selector_t r_selector; /* Qualifier for r_srate */ 166 } ibt_srate_req_t; 167 168 /* 169 * Packet Life Time Request Type. 170 */ 171 typedef struct ibt_pkt_lt_req_s { 172 clock_t p_pkt_lt; /* Requested Packet Life Time */ 173 ibt_selector_t p_selector; /* Qualifier for p_pkt_lt */ 174 } ibt_pkt_lt_req_t; 175 176 /* 177 * Queue size struct. 178 */ 179 typedef struct ibt_queue_sizes_s { 180 uint_t qs_sq; /* SendQ size. */ 181 uint_t qs_rq; /* RecvQ size. */ 182 } ibt_queue_sizes_t; 183 184 /* 185 * Channel sizes struct, used by functions that allocate/query RC or UD 186 * channels. 187 */ 188 typedef struct ibt_chan_sizes_s { 189 uint_t cs_sq; /* SendQ size. */ 190 uint_t cs_rq; /* ReceiveQ size. */ 191 uint_t cs_sq_sgl; /* Max SGL elements in a SQ WR. */ 192 uint_t cs_rq_sgl; /* Max SGL elements in a RQ Wr. */ 193 uint_t cs_inline; /* max inline payload size */ 194 } ibt_chan_sizes_t; 195 196 /* 197 * Shared Queue size struct. 198 */ 199 typedef struct ibt_srq_sizes_s { 200 uint_t srq_wr_sz; 201 uint_t srq_sgl_sz; 202 } ibt_srq_sizes_t; 203 204 /* 205 * SRQ Modify Flags 206 */ 207 typedef enum ibt_srq_modify_flags_e { 208 IBT_SRQ_SET_NOTHING = 0, 209 IBT_SRQ_SET_SIZE = (1 << 1), 210 IBT_SRQ_SET_LIMIT = (1 << 2) 211 } ibt_srq_modify_flags_t; 212 213 214 /* 215 * Execution flags, indicates if the function should block or not. 216 * Note: in some cases, e.g., a NULL rc_cm_handler, IBT_NONBLOCKING 217 * will not have an effect, and the thread will block. 218 * IBT_NOCALLBACKS is valid for ibt_close_rc_channel only. 219 */ 220 typedef enum ibt_execution_mode_e { 221 IBT_BLOCKING = 0, /* Block */ 222 IBT_NONBLOCKING = 1, /* Return as soon as possible */ 223 IBT_NOCALLBACKS = 2 /* cm_handler is not invoked after */ 224 /* ibt_close_rc_channel returns */ 225 } ibt_execution_mode_t; 226 227 /* 228 * Memory window alloc flags 229 */ 230 typedef enum ibt_mw_flags_e { 231 IBT_MW_SLEEP = 0, /* Can block */ 232 IBT_MW_NOSLEEP = (1 << 0), /* Can't block */ 233 IBT_MW_USER_MAP = (1 << 1), 234 IBT_MW_DEFER_ALLOC = (1 << 2), 235 IBT_MW_TYPE_1 = (1 << 3), 236 IBT_MW_TYPE_2 = (1 << 4) 237 } ibt_mw_flags_t; 238 239 /* 240 * PD alloc flags 241 */ 242 typedef enum ibt_pd_flags_e { 243 IBT_PD_NO_FLAGS = 0, 244 IBT_PD_USER_MAP = (1 << 0), 245 IBT_PD_DEFER_ALLOC = (1 << 1) 246 } ibt_pd_flags_t; 247 248 /* 249 * UD Dest alloc flags 250 */ 251 typedef enum ibt_ud_dest_flags_e { 252 IBT_UD_DEST_NO_FLAGS = 0, 253 IBT_UD_DEST_USER_MAP = (1 << 0), 254 IBT_UD_DEST_DEFER_ALLOC = (1 << 1) 255 } ibt_ud_dest_flags_t; 256 257 /* 258 * SRQ alloc flags 259 */ 260 typedef enum ibt_srq_flags_e { 261 IBT_SRQ_NO_FLAGS = 0, 262 IBT_SRQ_USER_MAP = (1 << 0), 263 IBT_SRQ_DEFER_ALLOC = (1 << 1) 264 } ibt_srq_flags_t; 265 266 /* 267 * ibt_alloc_lkey() alloc flags 268 */ 269 typedef enum ibt_lkey_flags_e { 270 IBT_KEY_SLEEP = 0, 271 IBT_KEY_NOSLEEP = (1 << 0), 272 IBT_KEY_REMOTE = (1 << 1) 273 } ibt_lkey_flags_t; 274 275 /* 276 * RNR NAK retry counts. 277 */ 278 typedef enum ibt_rnr_retry_cnt_e { 279 IBT_RNR_NO_RETRY = 0x0, /* Don't retry, fail on first timeout */ 280 IBT_RNR_RETRY_1 = 0x1, /* Retry once */ 281 IBT_RNR_RETRY_2 = 0x2, /* Retry twice */ 282 IBT_RNR_RETRY_3 = 0x3, /* Retry three times */ 283 IBT_RNR_RETRY_4 = 0x4, /* Retry four times */ 284 IBT_RNR_RETRY_5 = 0x5, /* Retry five times */ 285 IBT_RNR_RETRY_6 = 0x6, /* Retry six times */ 286 IBT_RNR_INFINITE_RETRY = 0x7 /* Retry forever */ 287 } ibt_rnr_retry_cnt_t; 288 289 /* 290 * Valid values for RNR NAK timer fields, part of a channel's context. 291 */ 292 typedef enum ibt_rnr_nak_time_e { 293 IBT_RNR_NAK_655ms = 0x0, 294 IBT_RNR_NAK_10us = 0x1, 295 IBT_RNR_NAK_20us = 0x2, 296 IBT_RNR_NAK_30us = 0x3, 297 IBT_RNR_NAK_40us = 0x4, 298 IBT_RNR_NAK_60us = 0x5, 299 IBT_RNR_NAK_80us = 0x6, 300 IBT_RNR_NAK_120us = 0x7, 301 IBT_RNR_NAK_160us = 0x8, 302 IBT_RNR_NAK_240us = 0x9, 303 IBT_RNR_NAK_320us = 0xA, 304 IBT_RNR_NAK_480us = 0xB, 305 IBT_RNR_NAK_640us = 0xC, 306 IBT_RNR_NAK_960us = 0xD, 307 IBT_RNR_NAK_1280us = 0xE, 308 IBT_RNR_NAK_1920us = 0xF, 309 IBT_RNR_NAK_2560us = 0x10, 310 IBT_RNR_NAK_3840us = 0x11, 311 IBT_RNR_NAK_5120us = 0x12, 312 IBT_RNR_NAK_7680us = 0x13, 313 IBT_RNR_NAK_10ms = 0x14, 314 IBT_RNR_NAK_15ms = 0x15, 315 IBT_RNR_NAK_20ms = 0x16, 316 IBT_RNR_NAK_31ms = 0x17, 317 IBT_RNR_NAK_41ms = 0x18, 318 IBT_RNR_NAK_61ms = 0x19, 319 IBT_RNR_NAK_82ms = 0x1A, 320 IBT_RNR_NAK_123ms = 0x1B, 321 IBT_RNR_NAK_164ms = 0x1C, 322 IBT_RNR_NAK_246ms = 0x1D, 323 IBT_RNR_NAK_328ms = 0x1E, 324 IBT_RNR_NAK_492ms = 0x1F 325 } ibt_rnr_nak_time_t; 326 327 /* 328 * The definition of HCA capabilities etc as a bitfield. 329 */ 330 typedef enum ibt_hca_flags_e { 331 IBT_HCA_NO_FLAGS = 0, 332 333 IBT_HCA_RD = 1 << 0, 334 IBT_HCA_UD_MULTICAST = 1 << 1, 335 IBT_HCA_RAW_MULTICAST = 1 << 2, 336 337 IBT_HCA_ATOMICS_HCA = 1 << 3, 338 IBT_HCA_ATOMICS_GLOBAL = 1 << 4, 339 340 IBT_HCA_RESIZE_CHAN = 1 << 5, /* Is resize supported? */ 341 IBT_HCA_AUTO_PATH_MIG = 1 << 6, /* Is APM supported? */ 342 IBT_HCA_SQD_SQD_PORT = 1 << 7, /* Can change physical port */ 343 /* on transit from SQD to SQD */ 344 IBT_HCA_PKEY_CNTR = 1 << 8, 345 IBT_HCA_QKEY_CNTR = 1 << 9, 346 IBT_HCA_AH_PORT_CHECK = 1 << 10, /* HCA checks AH port match */ 347 /* in UD WRs */ 348 IBT_HCA_PORT_UP = 1 << 11, /* PortActive event supported */ 349 IBT_HCA_INIT_TYPE = 1 << 12, /* InitType supported */ 350 IBT_HCA_SI_GUID = 1 << 13, /* System Image GUID */ 351 /* supported */ 352 IBT_HCA_SHUTDOWN_PORT = 1 << 14, /* ShutdownPort supported */ 353 IBT_HCA_RNR_NAK = 1 << 15, /* RNR-NAK supported for RC */ 354 IBT_HCA_CURRENT_QP_STATE = 1 << 16, /* Does modify_qp support */ 355 /* checking of current state? */ 356 IBT_HCA_SRQ = 1 << 17, /* Shared Receive Queue (RC) */ 357 IBT_HCA_RC_SRQ = IBT_HCA_SRQ, 358 IBT_HCA_RESIZE_SRQ = 1 << 18, /* Is resize SRQ supported? */ 359 IBT_HCA_UD_SRQ = 1 << 19, /* UD with SRQ */ 360 361 IBT_HCA_MULT_PAGE_SZ_MR = 1 << 20, /* Support of multiple page */ 362 /* sizes per memory region? */ 363 IBT_HCA_BLOCK_LIST = 1 << 21, /* Block list physical buffer */ 364 /* lists supported? */ 365 IBT_HCA_ZERO_BASED_VA = 1 << 22, /* Zero Based Virtual */ 366 /* Addresses supported? */ 367 IBT_HCA_LOCAL_INVAL_FENCE = 1 << 23, /* Local invalidate fencing? */ 368 IBT_HCA_BASE_QUEUE_MGT = 1 << 24, /* Base Queue Mgt supported? */ 369 IBT_HCA_CKSUM_FULL = 1 << 25, /* Checksum offload supported */ 370 IBT_HCA_MEM_WIN_TYPE_2B = 1 << 26, /* Type 2B memory windows */ 371 IBT_HCA_PHYS_BUF_BLOCK = 1 << 27, /* Block mode phys buf lists */ 372 IBT_HCA_FMR = 1 << 28, /* FMR Support */ 373 IBT_HCA_WQE_SIZE_INFO = 1 << 29, /* detailed WQE size info */ 374 IBT_HCA_SQD_STATE = 1 << 30 /* SQD QP state */ 375 } ibt_hca_flags_t; 376 377 typedef enum ibt_hca_flags2_e { 378 IBT_HCA2_NO_FLAGS = 0, 379 380 IBT_HCA2_UC = 1 << 1, /* Unreliable Connected */ 381 IBT_HCA2_UC_SRQ = 1 << 2, /* UC with SRQ */ 382 IBT_HCA2_RES_LKEY = 1 << 3, /* Reserved L_Key */ 383 IBT_HCA2_PORT_CHANGE = 1 << 4, /* Port Change event */ 384 IBT_HCA2_IP_CLASS = 1 << 5, /* IP Classification flags */ 385 IBT_HCA2_RSS_TPL_ALG = 1 << 6, /* RSS: Toeplitz algorithm */ 386 IBT_HCA2_RSS_XOR_ALG = 1 << 7, /* RSS: XOR algorithm */ 387 IBT_HCA2_XRC = 1 << 8, /* Extended RC (XRC) */ 388 IBT_HCA2_XRC_SRQ_RESIZE = 1 << 9, /* resize XRC SRQ */ 389 IBT_HCA2_MEM_MGT_EXT = 1 << 10 /* FMR-WR, send-inv, local-inv */ 390 } ibt_hca_flags2_t; 391 392 /* 393 * The definition of HCA page size capabilities as a bitfield 394 */ 395 typedef enum ibt_page_sizes_e { 396 IBT_PAGE_4K = 0x1 << 2, 397 IBT_PAGE_8K = 0x1 << 3, 398 IBT_PAGE_16K = 0x1 << 4, 399 IBT_PAGE_32K = 0x1 << 5, 400 IBT_PAGE_64K = 0x1 << 6, 401 IBT_PAGE_128K = 0x1 << 7, 402 IBT_PAGE_256K = 0x1 << 8, 403 IBT_PAGE_512K = 0x1 << 9, 404 IBT_PAGE_1M = 0x1 << 10, 405 IBT_PAGE_2M = 0x1 << 11, 406 IBT_PAGE_4M = 0x1 << 12, 407 IBT_PAGE_8M = 0x1 << 13, 408 IBT_PAGE_16M = 0x1 << 14, 409 IBT_PAGE_32M = 0x1 << 15, 410 IBT_PAGE_64M = 0x1 << 16, 411 IBT_PAGE_128M = 0x1 << 17, 412 IBT_PAGE_256M = 0x1 << 18, 413 IBT_PAGE_512M = 0x1 << 19, 414 IBT_PAGE_1G = 0x1 << 20, 415 IBT_PAGE_2G = 0x1 << 21, 416 IBT_PAGE_4G = 0x1 << 22, 417 IBT_PAGE_8G = 0x1 << 23, 418 IBT_PAGE_16G = 0x1 << 24 419 } ibt_page_sizes_t; 420 421 /* 422 * Memory Window Type. 423 */ 424 typedef enum ibt_mem_win_type_e { 425 IBT_MEM_WIN_TYPE_NOT_DEFINED = 0, 426 IBT_MEM_WIN_TYPE_1 = (1 << 0), 427 IBT_MEM_WIN_TYPE_2 = (1 << 1) 428 } ibt_mem_win_type_t; 429 430 /* 431 * HCA attributes. 432 * Contains all HCA static attributes. 433 */ 434 typedef struct ibt_hca_attr_s { 435 ibt_hca_flags_t hca_flags; /* HCA capabilities etc */ 436 ibt_hca_flags2_t hca_flags2; 437 438 /* device/version inconsistency w/ NodeInfo and IOControllerProfile */ 439 uint32_t hca_vendor_id:24; /* 24 bit Vendor ID */ 440 uint16_t hca_device_id; 441 uint32_t hca_version_id; 442 443 uint_t hca_max_chans; /* Max Chans supported */ 444 uint_t hca_max_chan_sz; /* Max outstanding WRs on any */ 445 /* channel */ 446 447 uint_t hca_max_sgl; /* Max SGL entries per WR */ 448 449 uint_t hca_max_cq; /* Max num of CQs supported */ 450 uint_t hca_max_cq_sz; /* Max capacity of each CQ */ 451 452 ibt_page_sizes_t hca_page_sz; /* Bit mask of page sizes */ 453 454 uint_t hca_max_memr; /* Max num of HCA mem regions */ 455 ib_memlen_t hca_max_memr_len; /* Largest block, in bytes of */ 456 /* mem that can be registered */ 457 uint_t hca_max_mem_win; /* Max Memory windows in HCA */ 458 459 uint_t hca_max_rsc; /* Max Responder Resources of */ 460 /* this HCA for RDMAR/Atomics */ 461 /* with this HCA as target. */ 462 uint8_t hca_max_rdma_in_chan; /* Max RDMAR/Atomics in per */ 463 /* chan this HCA as target. */ 464 uint8_t hca_max_rdma_out_chan; /* Max RDMA Reads/Atomics out */ 465 /* per channel by this HCA */ 466 uint_t hca_max_ipv6_chan; /* Max IPV6 channels in HCA */ 467 uint_t hca_max_ether_chan; /* Max Ether channels in HCA */ 468 469 uint_t hca_max_mcg_chans; /* Max number of channels */ 470 /* that can join multicast */ 471 /* groups */ 472 uint_t hca_max_mcg; /* Max multicast groups */ 473 uint_t hca_max_chan_per_mcg; /* Max number of channels per */ 474 /* Multicast group in HCA */ 475 476 uint16_t hca_max_partitions; /* Max partitions in HCA */ 477 uint8_t hca_nports; /* Number of physical ports */ 478 ib_guid_t hca_node_guid; /* Node GUID */ 479 480 ib_time_t hca_local_ack_delay; 481 482 uint_t hca_max_port_sgid_tbl_sz; 483 uint16_t hca_max_port_pkey_tbl_sz; 484 uint_t hca_max_pd; /* Max# of Protection Domains */ 485 ib_guid_t hca_si_guid; /* Optional System Image GUID */ 486 uint_t hca_hca_max_ci_priv_sz; 487 uint_t hca_chan_max_ci_priv_sz; 488 uint_t hca_cq_max_ci_priv_sz; 489 uint_t hca_pd_max_ci_priv_sz; 490 uint_t hca_mr_max_ci_priv_sz; 491 uint_t hca_mw_max_ci_priv_sz; 492 uint_t hca_ud_dest_max_ci_priv_sz; 493 uint_t hca_cq_sched_max_ci_priv_sz; 494 uint_t hca_max_ud_dest; 495 uint_t hca_opaque2; 496 uint_t hca_opaque3; 497 uint_t hca_opaque4; 498 uint8_t hca_opaque5; 499 uint8_t hca_opaque6; 500 uint8_t hca_rss_max_log2_table; /* max RSS log2 table size */ 501 uint_t hca_opaque7; 502 uint_t hca_opaque8; 503 uint_t hca_max_srqs; /* Max SRQs supported */ 504 uint_t hca_max_srqs_sz; /* Max outstanding WRs on any */ 505 /* SRQ */ 506 uint_t hca_max_srq_sgl; /* Max SGL entries per SRQ WR */ 507 uint_t hca_max_phys_buf_list_sz; 508 size_t hca_block_sz_lo; /* Range of block sizes */ 509 size_t hca_block_sz_hi; /* supported by the HCA */ 510 uint_t hca_max_cq_handlers; 511 ibt_lkey_t hca_reserved_lkey; /* Reserved L_Key value */ 512 uint_t hca_max_fmrs; /* Max FMR Supported */ 513 uint_t hca_opaque9; 514 515 uint_t hca_max_lso_size; 516 uint_t hca_max_lso_hdr_size; 517 uint_t hca_max_inline_size; 518 519 uint_t hca_max_cq_mod_count; /* CQ notify moderation */ 520 uint_t hca_max_cq_mod_usec; 521 522 uint32_t hca_fw_major_version; /* firmware version */ 523 uint16_t hca_fw_minor_version; 524 uint16_t hca_fw_micro_version; 525 526 uint_t hca_max_xrc_domains; /* XRC items */ 527 uint_t hca_max_xrc_srqs; 528 uint_t hca_max_xrc_srq_size; 529 uint_t hca_max_xrc_srq_sgl; 530 531 /* detailed WQE size info */ 532 uint_t hca_ud_send_inline_sz; /* inline size in bytes */ 533 uint_t hca_conn_send_inline_sz; 534 uint_t hca_conn_rdmaw_inline_overhead; 535 uint_t hca_recv_sgl_sz; /* detailed SGL sizes */ 536 uint_t hca_ud_send_sgl_sz; 537 uint_t hca_conn_send_sgl_sz; 538 uint_t hca_conn_rdma_sgl_overhead; 539 } ibt_hca_attr_t; 540 541 /* 542 * HCA Port link states. 543 */ 544 typedef enum ibt_port_state_e { 545 IBT_PORT_DOWN = 1, 546 IBT_PORT_INIT, 547 IBT_PORT_ARM, 548 IBT_PORT_ACTIVE 549 } ibt_port_state_t; 550 551 /* 552 * HCA Port capabilities as a bitfield. 553 */ 554 typedef enum ibt_port_caps_e { 555 IBT_PORT_CAP_NO_FLAGS = 0, 556 IBT_PORT_CAP_SM = 1 << 0, /* SM port */ 557 IBT_PORT_CAP_SM_DISABLED = 1 << 1, 558 IBT_PORT_CAP_SNMP_TUNNEL = 1 << 2, /* SNMP Tunneling */ 559 IBT_PORT_CAP_DM = 1 << 3, /* DM supported */ 560 IBT_PORT_CAP_VENDOR = 1 << 4, /* Vendor Class */ 561 IBT_PORT_CAP_CLNT_REREG = 1 << 5 /* Client Rereg */ 562 } ibt_port_caps_t; 563 564 565 /* LinkWidth fields from PortInfo */ 566 typedef uint8_t ib_link_width_t; 567 568 /* 569 * When reading LinkWidthSupported and LinkWidthEnabled, these 570 * values will be OR-ed together. See IB spec 14.2.5.6 for allowed 571 * combinations. For LinkWidthActive, only one will be returned. 572 */ 573 #define IBT_LINK_WIDTH_1X (1) 574 #define IBT_LINK_WIDTH_4X (2) 575 #define IBT_LINK_WIDTH_8X (4) 576 #define IBT_LINK_WIDTH_12X (8) 577 578 /* LinkSpeed fields from PortInfo */ 579 typedef uint8_t ib_link_speed_t; 580 581 /* 582 * When reading LinkSpeedSupported and LinkSpeedEnabled, these 583 * values will be OR-ed together. See IB spec 14.2.5.6 for allowed 584 * combinations. For LinkSpeedActive, only one will be returned. 585 */ 586 #define IBT_LINK_SPEED_SDR (1) 587 #define IBT_LINK_SPEED_DDR (2) 588 #define IBT_LINK_SPEED_QDR (4) 589 590 /* PortPhysicalState field from PortInfo */ 591 typedef uint8_t ib_port_phys_state_t; 592 593 #define IBT_PORT_PHYS_STATE_SLEEP (1) 594 #define IBT_PORT_PHYS_STATE_POLLING (2) 595 #define IBT_PORT_PHYS_STATE_DISABLED (3) 596 #define IBT_PORT_PHYS_STATE_TRAINING (4) 597 #define IBT_PORT_PHYS_STATE_UP (5) 598 #define IBT_PORT_PHYS_STATE_RECOVERY (6) 599 #define IBT_PORT_PHYS_STATE_TEST (7) 600 601 /* 602 * HCA port attributes structure definition. The number of ports per HCA 603 * can be found from the "ibt_hca_attr_t" structure. 604 * 605 * p_pkey_tbl is a pointer to an array of ib_pkey_t, members are 606 * accessed as: 607 * hca_portinfo->p_pkey_tbl[i] 608 * 609 * Where 0 <= i < hca_portinfo.p_pkey_tbl_sz 610 * 611 * Similarly p_sgid_tbl is a pointer to an array of ib_gid_t. 612 * 613 * The Query Port function - ibt_query_hca_ports() allocates the memory 614 * required for the ibt_hca_portinfo_t struct as well as the memory 615 * required for the SGID and P_Key tables. The memory is freed by calling 616 * ibt_free_portinfo(). 617 */ 618 typedef struct ibt_hca_portinfo_s { 619 ib_lid_t p_opaque1; /* Base LID of port */ 620 ib_qkey_cntr_t p_qkey_violations; /* Bad Q_Key cnt */ 621 ib_pkey_cntr_t p_pkey_violations; /* Optional bad P_Key cnt */ 622 uint8_t p_sm_sl:4; /* SM Service level */ 623 ib_port_phys_state_t p_phys_state; 624 ib_lid_t p_sm_lid; /* SM LID */ 625 ibt_port_state_t p_linkstate; /* Port state */ 626 uint8_t p_port_num; 627 ib_link_width_t p_width_supported; 628 ib_link_width_t p_width_enabled; 629 ib_link_width_t p_width_active; 630 ib_mtu_t p_mtu; /* Max transfer unit - pkt */ 631 uint8_t p_lmc:3; /* Local mask control */ 632 ib_link_speed_t p_speed_supported; 633 ib_link_speed_t p_speed_enabled; 634 ib_link_speed_t p_speed_active; 635 ib_gid_t *p_sgid_tbl; /* SGID Table */ 636 uint_t p_sgid_tbl_sz; /* Size of SGID table */ 637 uint16_t p_pkey_tbl_sz; /* Size of P_Key table */ 638 uint16_t p_def_pkey_ix; /* default pkey index for TI */ 639 ib_pkey_t *p_pkey_tbl; /* P_Key table */ 640 uint8_t p_max_vl; /* Max num of virtual lanes */ 641 uint8_t p_init_type_reply; /* Optional InitTypeReply */ 642 ib_time_t p_subnet_timeout; /* Max Subnet Timeout */ 643 ibt_port_caps_t p_capabilities; /* Port Capabilities */ 644 uint32_t p_msg_sz; /* Max message size */ 645 } ibt_hca_portinfo_t; 646 647 /* 648 * Modify HCA port attributes flags, specifies which HCA port 649 * attributes to modify. 650 */ 651 typedef enum ibt_port_modify_flags_e { 652 IBT_PORT_NO_FLAGS = 0, 653 654 IBT_PORT_RESET_QKEY = 1 << 0, /* Reset Q_Key violation */ 655 /* counter */ 656 IBT_PORT_RESET_SM = 1 << 1, /* SM */ 657 IBT_PORT_SET_SM = 1 << 2, 658 IBT_PORT_RESET_SNMP = 1 << 3, /* SNMP Tunneling */ 659 IBT_PORT_SET_SNMP = 1 << 4, 660 IBT_PORT_RESET_DEVMGT = 1 << 5, /* Device Management */ 661 IBT_PORT_SET_DEVMGT = 1 << 6, 662 IBT_PORT_RESET_VENDOR = 1 << 7, /* Vendor Class */ 663 IBT_PORT_SET_VENDOR = 1 << 8, 664 IBT_PORT_SHUTDOWN = 1 << 9, /* Shut down the port */ 665 IBT_PORT_SET_INIT_TYPE = 1 << 10 /* InitTypeReply value */ 666 } ibt_port_modify_flags_t; 667 668 /* 669 * Modify HCA port InitType bit definitions, applicable only if 670 * IBT_PORT_SET_INIT_TYPE modify flag (ibt_port_modify_flags_t) is set. 671 */ 672 #define IBT_PINIT_NO_LOAD 0x1 673 #define IBT_PINIT_PRESERVE_CONTENT 0x2 674 #define IBT_PINIT_PRESERVE_PRESENCE 0x4 675 #define IBT_PINIT_NO_RESUSCITATE 0x8 676 677 678 /* 679 * Address vector definition. 680 */ 681 typedef struct ibt_adds_vect_s { 682 ib_gid_t av_dgid; /* IPV6 dest GID in GRH */ 683 ib_gid_t av_sgid; /* SGID */ 684 ibt_srate_t av_srate; /* Max static rate */ 685 uint8_t av_srvl:4; /* Service level in LRH */ 686 uint_t av_flow:20; /* 20 bit Flow Label */ 687 uint8_t av_tclass; /* Traffic Class */ 688 uint8_t av_hop; /* Hop Limit */ 689 uint8_t av_port_num; /* Port number for UD */ 690 boolean_t av_opaque1; 691 ib_lid_t av_opaque2; 692 ib_path_bits_t av_opaque3; 693 uint32_t av_opaque4; 694 } ibt_adds_vect_t; 695 696 typedef struct ibt_cep_path_s { 697 ibt_adds_vect_t cep_adds_vect; /* Address Vector */ 698 uint16_t cep_pkey_ix; /* P_Key Index */ 699 uint8_t cep_hca_port_num; /* Port number for connected */ 700 /* channels. A value of 0 */ 701 /* indicates an invalid path */ 702 ib_time_t cep_cm_opaque1; 703 } ibt_cep_path_t; 704 705 /* 706 * Define Receive Side Scaling types for IP over IB. 707 */ 708 typedef enum ibt_rss_flags_e { 709 IBT_RSS_ALG_TPL = (1 << 0), /* RSS: Toeplitz hash */ 710 IBT_RSS_ALG_XOR = (1 << 1), /* RSS: XOR hash */ 711 IBT_RSS_HASH_IPV4 = (1 << 2), /* RSS: hash IPv4 headers */ 712 IBT_RSS_HASH_IPV6 = (1 << 3), /* RSS: hash IPv6 headers */ 713 IBT_RSS_HASH_TCP_IPV4 = (1 << 4), /* RSS: hash TCP/IPv4 hdrs */ 714 IBT_RSS_HASH_TCP_IPV6 = (1 << 5) /* RSS: hash TCP/IPv6 hdrs */ 715 } ibt_rss_flags_t; 716 717 typedef struct ibt_rss_attr_s { 718 ibt_rss_flags_t rss_flags; /* RSS: flags */ 719 uint_t rss_log2_table; /* RSS: log2 table size */ 720 ib_qpn_t rss_base_qpn; /* RSS: base QPN */ 721 ib_qpn_t rss_def_qpn; /* RSS: default QPN */ 722 uint8_t rss_toe_key[40]; /* RSS: Toeplitz hash key */ 723 } ibt_rss_attr_t; 724 725 /* 726 * Channel Migration State. 727 */ 728 typedef enum ibt_cep_cmstate_e { 729 IBT_STATE_NOT_SUPPORTED = 0, 730 IBT_STATE_MIGRATED = 1, 731 IBT_STATE_REARMED = 2, 732 IBT_STATE_ARMED = 3 733 } ibt_cep_cmstate_t; 734 735 /* 736 * Transport service type 737 * 738 * NOTE: this was converted from an enum to a uint8_t to save space. 739 */ 740 typedef uint8_t ibt_tran_srv_t; 741 742 #define IBT_RC_SRV 0 743 #define IBT_UC_SRV 1 744 #define IBT_RD_SRV 2 745 #define IBT_UD_SRV 3 746 #define IBT_RAWIP_SRV 4 747 #define IBT_RAWETHER_SRV 5 748 749 /* 750 * Channel (QP/EEC) state definitions. 751 */ 752 typedef enum ibt_cep_state_e { 753 IBT_STATE_RESET = 0, /* Reset */ 754 IBT_STATE_INIT, /* Initialized */ 755 IBT_STATE_RTR, /* Ready to Receive */ 756 IBT_STATE_RTS, /* Ready to Send */ 757 IBT_STATE_SQD, /* Send Queue Drained */ 758 IBT_STATE_SQE, /* Send Queue Error */ 759 IBT_STATE_ERROR, /* Error */ 760 IBT_STATE_SQDRAIN, /* Send Queue Draining */ 761 IBT_STATE_NUM /* Number of states */ 762 } ibt_cep_state_t; 763 764 765 /* 766 * Channel Attribute flags. 767 */ 768 typedef enum ibt_attr_flags_e { 769 IBT_ALL_SIGNALED = 0, /* All sends signaled */ 770 IBT_WR_SIGNALED = 1, /* Signaled on a WR basis */ 771 IBT_FAST_REG_RES_LKEY = (1 << 1), 772 IBT_USES_LSO = (1 << 2) 773 } ibt_attr_flags_t; 774 775 /* 776 * Channel End Point (CEP) Control Flags. 777 */ 778 typedef enum ibt_cep_flags_e { 779 IBT_CEP_NO_FLAGS = 0, /* Enable Nothing */ 780 IBT_CEP_RDMA_RD = (1 << 0), /* Enable incoming RDMA RD's */ 781 /* RC & RD only */ 782 IBT_CEP_RDMA_WR = (1 << 1), /* Enable incoming RDMA WR's */ 783 /* RC & RD only */ 784 IBT_CEP_ATOMIC = (1 << 2) /* Enable incoming Atomics, */ 785 /* RC & RD only */ 786 } ibt_cep_flags_t; 787 788 /* 789 * Channel Modify Flags 790 */ 791 typedef enum ibt_cep_modify_flags_e { 792 IBT_CEP_SET_NOTHING = 0, 793 IBT_CEP_SET_SQ_SIZE = (1 << 1), 794 IBT_CEP_SET_RQ_SIZE = (1 << 2), 795 796 IBT_CEP_SET_RDMA_R = (1 << 3), 797 IBT_CEP_SET_RDMA_W = (1 << 4), 798 IBT_CEP_SET_ATOMIC = (1 << 5), 799 800 IBT_CEP_SET_ALT_PATH = (1 << 6), /* Alternate Path */ 801 802 IBT_CEP_SET_ADDS_VECT = (1 << 7), 803 IBT_CEP_SET_PORT = (1 << 8), 804 IBT_CEP_SET_OPAQUE5 = (1 << 9), 805 IBT_CEP_SET_RETRY = (1 << 10), 806 IBT_CEP_SET_RNR_NAK_RETRY = (1 << 11), 807 IBT_CEP_SET_MIN_RNR_NAK = (1 << 12), 808 809 IBT_CEP_SET_QKEY = (1 << 13), 810 IBT_CEP_SET_RDMARA_OUT = (1 << 14), 811 IBT_CEP_SET_RDMARA_IN = (1 << 15), 812 813 IBT_CEP_SET_OPAQUE1 = (1 << 16), 814 IBT_CEP_SET_OPAQUE2 = (1 << 17), 815 IBT_CEP_SET_OPAQUE3 = (1 << 18), 816 IBT_CEP_SET_OPAQUE4 = (1 << 19), 817 IBT_CEP_SET_SQD_EVENT = (1 << 20), 818 IBT_CEP_SET_OPAQUE6 = (1 << 21), 819 IBT_CEP_SET_OPAQUE7 = (1 << 22), 820 IBT_CEP_SET_OPAQUE8 = (1 << 23), 821 IBT_CEP_SET_RSS = (1 << 24) 822 } ibt_cep_modify_flags_t; 823 824 /* 825 * CQ notify types. 826 */ 827 typedef enum ibt_cq_notify_flags_e { 828 IBT_NEXT_COMPLETION = 1, 829 IBT_NEXT_SOLICITED = 2 830 } ibt_cq_notify_flags_t; 831 832 /* 833 * CQ types shared across TI and CI. 834 */ 835 typedef enum ibt_cq_flags_e { 836 IBT_CQ_NO_FLAGS = 0, 837 IBT_CQ_HANDLER_IN_THREAD = 1 << 0, /* A thread calls the */ 838 /* CQ handler */ 839 IBT_CQ_USER_MAP = 1 << 1, 840 IBT_CQ_DEFER_ALLOC = 1 << 2 841 } ibt_cq_flags_t; 842 843 /* 844 * CQ types shared across TI and CI. 845 */ 846 typedef enum ibt_cq_sched_flags_e { 847 IBT_CQS_NO_FLAGS = 0, 848 IBT_CQS_WARM_CACHE = 1 << 0, /* run on same CPU */ 849 IBT_CQS_AFFINITY = 1 << 1, 850 IBT_CQS_SCHED_GROUP = 1 << 2, 851 IBT_CQS_USER_MAP = 1 << 3, 852 IBT_CQS_DEFER_ALLOC = 1 << 4 853 } ibt_cq_sched_flags_t; 854 855 /* 856 * Attributes when creating a Completion Queue. 857 * 858 * Note: 859 * The IBT_CQ_HANDLER_IN_THREAD cq_flags bit should be ignored by the CI. 860 */ 861 typedef struct ibt_cq_attr_s { 862 uint_t cq_size; 863 ibt_sched_hdl_t cq_sched; /* 0 = no hint, */ 864 /* other = cq_sched value */ 865 ibt_cq_flags_t cq_flags; 866 } ibt_cq_attr_t; 867 868 /* 869 * Memory Management 870 */ 871 872 /* Memory management flags */ 873 typedef enum ibt_mr_flags_e { 874 IBT_MR_SLEEP = 0, 875 IBT_MR_NOSLEEP = (1 << 1), 876 IBT_MR_NONCOHERENT = (1 << 2), 877 IBT_MR_PHYS_IOVA = (1 << 3), /* ibt_(re)register_buf */ 878 879 /* Access control flags */ 880 IBT_MR_ENABLE_WINDOW_BIND = (1 << 4), 881 IBT_MR_ENABLE_LOCAL_WRITE = (1 << 5), 882 IBT_MR_ENABLE_REMOTE_READ = (1 << 6), 883 IBT_MR_ENABLE_REMOTE_WRITE = (1 << 7), 884 IBT_MR_ENABLE_REMOTE_ATOMIC = (1 << 8), 885 886 /* Reregister flags */ 887 IBT_MR_CHANGE_TRANSLATION = (1 << 9), 888 IBT_MR_CHANGE_ACCESS = (1 << 10), 889 IBT_MR_CHANGE_PD = (1 << 11), 890 891 /* Additional registration flags */ 892 IBT_MR_ZBVA = (1 << 12), 893 894 /* Additional physical registration flags */ 895 IBT_MR_CONSUMER_KEY = (1 << 13), /* Consumer owns key */ 896 /* portion of keys */ 897 IBT_MR_DISABLE_RO = (1 << 14) 898 } ibt_mr_flags_t; 899 900 901 /* Memory Region attribute flags */ 902 typedef enum ibt_mr_attr_flags_e { 903 /* Access control flags */ 904 IBT_MR_WINDOW_BIND = (1 << 0), 905 IBT_MR_LOCAL_WRITE = (1 << 1), 906 IBT_MR_REMOTE_READ = (1 << 2), 907 IBT_MR_REMOTE_WRITE = (1 << 3), 908 IBT_MR_REMOTE_ATOMIC = (1 << 4), 909 IBT_MR_ZERO_BASED_VA = (1 << 5), 910 IBT_MR_CONSUMER_OWNED_KEY = (1 << 6), 911 IBT_MR_SHARED = (1 << 7), 912 IBT_MR_FMR = (1 << 8), 913 IBT_MR_RO_DISABLED = (1 << 9) 914 } ibt_mr_attr_flags_t; 915 916 /* Memory region physical descriptor. */ 917 typedef struct ibt_phys_buf_s { 918 union { 919 uint64_t _p_ll; /* 64 bit DMA address */ 920 uint32_t _p_la[2]; /* 2 x 32 bit address */ 921 } _phys_buf; 922 size_t p_size; 923 } ibt_phys_buf_t; 924 925 /* version of above for uniform buffer size */ 926 typedef struct ib_phys_addr_t { 927 union { 928 uint64_t _p_ll; /* 64 bit DMA address */ 929 uint32_t _p_la[2]; /* 2 x 32 bit address */ 930 } _phys_buf; 931 } ibt_phys_addr_t; 932 933 #define p_laddr _phys_buf._p_ll 934 #ifdef _LONG_LONG_HTOL 935 #define p_notused _phys_buf._p_la[0] 936 #define p_addr _phys_buf._p_la[1] 937 #else 938 #define p_addr _phys_buf._p_la[0] 939 #define p_notused _phys_buf._p_la[1] 940 #endif 941 942 943 /* Memory region descriptor. */ 944 typedef struct ibt_mr_desc_s { 945 ib_vaddr_t md_vaddr; /* IB virtual adds of memory */ 946 ibt_lkey_t md_lkey; 947 ibt_rkey_t md_rkey; 948 boolean_t md_sync_required; 949 } ibt_mr_desc_t; 950 951 /* Physical Memory region descriptor. */ 952 typedef struct ibt_pmr_desc_s { 953 ib_vaddr_t pmd_iova; /* Returned I/O Virtual Address */ 954 ibt_lkey_t pmd_lkey; 955 ibt_rkey_t pmd_rkey; 956 uint_t pmd_phys_buf_list_sz; /* Allocated Phys buf sz */ 957 boolean_t pmd_sync_required; 958 } ibt_pmr_desc_t; 959 960 /* Memory region protection bounds. */ 961 typedef struct ibt_mr_prot_bounds_s { 962 ib_vaddr_t pb_addr; /* Beginning address */ 963 size_t pb_len; /* Length of protected region */ 964 } ibt_mr_prot_bounds_t; 965 966 /* Memory Region (Re)Register attributes */ 967 typedef struct ibt_mr_attr_s { 968 ib_vaddr_t mr_vaddr; /* Virtual address to register */ 969 ib_memlen_t mr_len; /* Length of region to register */ 970 struct as *mr_as; /* A pointer to an address space */ 971 /* structure. This parameter should */ 972 /* be set to NULL, which implies */ 973 /* kernel address space. */ 974 ibt_mr_flags_t mr_flags; 975 } ibt_mr_attr_t; 976 977 /* Physical Memory Region (Re)Register */ 978 typedef struct ibt_pmr_attr_s { 979 ib_vaddr_t pmr_iova; /* I/O virtual address requested by */ 980 /* client for the first byte of the */ 981 /* region */ 982 ib_memlen_t pmr_len; /* Length of region to register */ 983 ib_memlen_t pmr_offset; /* Offset of the regions starting */ 984 /* IOVA within the 1st physical */ 985 /* buffer */ 986 ibt_ma_hdl_t pmr_ma; /* Memory handle used to obtain the */ 987 /* pmr_buf_list */ 988 ibt_phys_addr_t *pmr_addr_list; /* List of physical buffers accessed */ 989 /* as an array */ 990 size_t pmr_buf_sz; 991 uint_t pmr_num_buf; /* Num of entries in the pmr_buf_list */ 992 ibt_lkey_t pmr_lkey; /* Reregister only */ 993 ibt_rkey_t pmr_rkey; /* Reregister only */ 994 ibt_mr_flags_t pmr_flags; 995 uint8_t pmr_key; /* Key to use on new Lkey & Rkey */ 996 } ibt_pmr_attr_t; 997 998 /* addr/length pair */ 999 typedef struct ibt_iov_s { 1000 caddr_t iov_addr; /* Beginning address */ 1001 size_t iov_len; /* Length */ 1002 } ibt_iov_t; 1003 1004 /* Map memory IOV */ 1005 typedef enum ibt_iov_flags_e { 1006 IBT_IOV_SLEEP = 0, 1007 IBT_IOV_NOSLEEP = (1 << 0), 1008 IBT_IOV_BUF = (1 << 1), 1009 IBT_IOV_RECV = (1 << 2) 1010 } ibt_iov_flags_t; 1011 1012 typedef struct ibt_iov_attr_s { 1013 struct as *iov_as; 1014 ibt_iov_t *iov; 1015 struct buf *iov_buf; 1016 uint32_t iov_list_len; 1017 uint32_t iov_wr_nds; 1018 ib_msglen_t iov_lso_hdr_sz; 1019 ibt_iov_flags_t iov_flags; 1020 } ibt_iov_attr_t; 1021 1022 /* 1023 * Memory Region (Re)Register attributes - used by ibt_register_shared_mr(), 1024 * ibt_register_buf() and ibt_reregister_buf(). 1025 */ 1026 typedef struct ibt_smr_attr_s { 1027 ib_vaddr_t mr_vaddr; 1028 ibt_mr_flags_t mr_flags; 1029 uint8_t mr_key; /* Only for physical */ 1030 /* ibt_(Re)register_buf() */ 1031 ibt_lkey_t mr_lkey; /* Only for physical */ 1032 ibt_rkey_t mr_rkey; /* ibt_Reregister_buf() */ 1033 } ibt_smr_attr_t; 1034 1035 /* 1036 * key states. 1037 */ 1038 typedef enum ibt_key_state_e { 1039 IBT_KEY_INVALID = 0, 1040 IBT_KEY_FREE, 1041 IBT_KEY_VALID 1042 } ibt_key_state_t; 1043 1044 /* Memory region query attributes */ 1045 typedef struct ibt_mr_query_attr_s { 1046 ibt_lkey_t mr_lkey; 1047 ibt_rkey_t mr_rkey; 1048 ibt_mr_prot_bounds_t mr_lbounds; /* Actual local CI protection */ 1049 /* bounds */ 1050 ibt_mr_prot_bounds_t mr_rbounds; /* Actual remote CI */ 1051 /* protection bounds */ 1052 ibt_mr_attr_flags_t mr_attr_flags; /* Access rights etc. */ 1053 ibt_pd_hdl_t mr_pd; /* Protection domain */ 1054 boolean_t mr_sync_required; 1055 ibt_key_state_t mr_lkey_state; 1056 uint_t mr_phys_buf_list_sz; 1057 } ibt_mr_query_attr_t; 1058 1059 /* Memory window query attributes */ 1060 typedef struct ibt_mw_query_attr_s { 1061 ibt_pd_hdl_t mw_pd; 1062 ibt_mem_win_type_t mw_type; 1063 ibt_rkey_t mw_rkey; 1064 ibt_key_state_t mw_state; 1065 } ibt_mw_query_attr_t; 1066 1067 1068 /* Memory Region Sync Flags. */ 1069 #define IBT_SYNC_READ 0x1 /* Make memory changes visible to incoming */ 1070 /* RDMA reads */ 1071 1072 #define IBT_SYNC_WRITE 0x2 /* Make the affects of an incoming RDMA write */ 1073 /* visible to the consumer */ 1074 1075 /* Memory region sync args */ 1076 typedef struct ibt_mr_sync_s { 1077 ibt_mr_hdl_t ms_handle; 1078 ib_vaddr_t ms_vaddr; 1079 ib_memlen_t ms_len; 1080 uint32_t ms_flags; /* IBT_SYNC_READ or IBT_SYNC_WRITE */ 1081 } ibt_mr_sync_t; 1082 1083 /* 1084 * Flags for Virtual Address to HCA Physical Address translation. 1085 */ 1086 typedef enum ibt_va_flags_e { 1087 IBT_VA_SLEEP = 0, 1088 IBT_VA_NOSLEEP = (1 << 0), 1089 IBT_VA_NONCOHERENT = (1 << 1), 1090 IBT_VA_FMR = (1 << 2), 1091 IBT_VA_BLOCK_MODE = (1 << 3), 1092 IBT_VA_BUF = (1 << 4), 1093 IBT_VA_REG_FN = (1 << 5) 1094 } ibt_va_flags_t; 1095 1096 1097 /* Address Translation parameters */ 1098 typedef struct ibt_va_attr_s { 1099 ib_vaddr_t va_vaddr; /* Virtual address to register */ 1100 ib_memlen_t va_len; /* Length of region to register */ 1101 struct as *va_as; /* A pointer to an address space */ 1102 /* structure. */ 1103 size_t va_phys_buf_min; /* block mode only */ 1104 size_t va_phys_buf_max; /* block mode only */ 1105 ibt_va_flags_t va_flags; 1106 struct buf *va_buf; 1107 } ibt_va_attr_t; 1108 1109 1110 /* 1111 * Fast Memory Registration (FMR) support. 1112 */ 1113 1114 /* FMR flush function handler. */ 1115 typedef void (*ibt_fmr_flush_handler_t)(ibt_fmr_pool_hdl_t fmr_pool, 1116 void *fmr_func_arg); 1117 1118 /* FMR Pool create attributes. */ 1119 typedef struct ibt_fmr_pool_attr_s { 1120 uint_t fmr_max_pages_per_fmr; 1121 uint_t fmr_pool_size; 1122 uint_t fmr_dirty_watermark; 1123 size_t fmr_page_sz; 1124 boolean_t fmr_cache; 1125 ibt_mr_flags_t fmr_flags; 1126 ibt_fmr_flush_handler_t fmr_func_hdlr; 1127 void *fmr_func_arg; 1128 } ibt_fmr_pool_attr_t; 1129 1130 1131 /* 1132 * WORK REQUEST AND WORK REQUEST COMPLETION DEFINITIONS. 1133 */ 1134 1135 /* 1136 * Work Request and Work Request Completion types - These types are used 1137 * to indicate the type of work requests posted to a work queue 1138 * or the type of completion received. Immediate Data is indicated via 1139 * ibt_wr_flags_t or ibt_wc_flags_t. 1140 * 1141 * IBT_WRC_RECV and IBT_WRC_RECV_RDMAWI are only used as opcodes in the 1142 * work completions. 1143 * 1144 * NOTE: this was converted from an enum to a uint8_t to save space. 1145 */ 1146 typedef uint8_t ibt_wrc_opcode_t; 1147 1148 #define IBT_WRC_SEND 1 /* Send */ 1149 #define IBT_WRC_RDMAR 2 /* RDMA Read */ 1150 #define IBT_WRC_RDMAW 3 /* RDMA Write */ 1151 #define IBT_WRC_CSWAP 4 /* Compare & Swap Atomic */ 1152 #define IBT_WRC_FADD 5 /* Fetch & Add Atomic */ 1153 #define IBT_WRC_BIND 6 /* Bind Memory Window */ 1154 #define IBT_WRC_RECV 7 /* Receive */ 1155 #define IBT_WRC_RECV_RDMAWI 8 /* Received RDMA Write w/ Immediate */ 1156 #define IBT_WRC_FAST_REG_PMR 9 /* Fast Register Physical mem region */ 1157 #define IBT_WRC_LOCAL_INVALIDATE 10 1158 #define IBT_WRC_SEND_LSO 11 1159 1160 1161 /* 1162 * Work Request Completion flags - These flags indicate what type 1163 * of data is present in the Work Request Completion structure 1164 */ 1165 typedef uint8_t ibt_wc_flags_t; 1166 1167 #define IBT_WC_NO_FLAGS 0 1168 #define IBT_WC_GRH_PRESENT (1 << 0) 1169 #define IBT_WC_IMMED_DATA_PRESENT (1 << 1) 1170 #define IBT_WC_RKEY_INVALIDATED (1 << 2) 1171 #define IBT_WC_CKSUM_OK (1 << 3) 1172 1173 /* IPoIB flags for wc_detail field */ 1174 #define IBT_WC_DETAIL_ALL_FLAGS_MASK (0x0FC00000) 1175 #define IBT_WC_DETAIL_IPV4 (1 << 22) 1176 #define IBT_WC_DETAIL_IPV4_FRAG (1 << 23) 1177 #define IBT_WC_DETAIL_IPV6 (1 << 24) 1178 #define IBT_WC_DETAIL_IPV4_OPT (1 << 25) 1179 #define IBT_WC_DETAIL_TCP (1 << 26) 1180 #define IBT_WC_DETAIL_UDP (1 << 27) 1181 1182 #define IBT_WC_DETAIL_RSS_MATCH_MASK (0x003F0000) 1183 #define IBT_WC_DETAIL_RSS_TCP_IPV6 (1 << 18) 1184 #define IBT_WC_DETAIL_RSS_IPV6 (1 << 19) 1185 #define IBT_WC_DETAIL_RSS_TCP_IPV4 (1 << 20) 1186 #define IBT_WC_DETAIL_RSS_IPV4 (1 << 21) 1187 1188 /* 1189 * Work Request Completion - This structure encapsulates the information 1190 * necessary to define a work request completion. 1191 */ 1192 typedef struct ibt_wc_s { 1193 ibt_wrid_t wc_id; /* Work Request Id */ 1194 uint64_t wc_fma_ena; /* fault management err data */ 1195 ib_msglen_t wc_bytes_xfer; /* Number of Bytes */ 1196 /* Transferred */ 1197 ibt_wc_flags_t wc_flags; /* WR Completion Flags */ 1198 ibt_wrc_opcode_t wc_type; /* Operation Type */ 1199 uint16_t wc_cksum; /* payload checksum */ 1200 ibt_immed_t wc_immed_data; /* Immediate Data */ 1201 uint32_t wc_res_hash; /* RD: Freed Res, RSS: hash */ 1202 ibt_wc_status_t wc_status; /* Completion Status */ 1203 uint8_t wc_sl:4; /* Remote SL */ 1204 uint16_t wc_ethertype; /* Ethertype Field - RE */ 1205 ib_lid_t wc_opaque1; 1206 uint16_t wc_opaque2; 1207 ib_qpn_t wc_qpn; /* Source QPN Datagram only */ 1208 uint32_t wc_detail; /* RD: EECN, UD: IPoIB flags */ 1209 ib_qpn_t wc_local_qpn; 1210 ibt_rkey_t wc_rkey; 1211 ib_path_bits_t wc_opaque4; 1212 } ibt_wc_t; 1213 1214 /* 1215 * WR Flags. Common for both RC and UD 1216 * 1217 * NOTE: this was converted from an enum to a uint8_t to save space. 1218 */ 1219 typedef uint8_t ibt_wr_flags_t; 1220 1221 #define IBT_WR_NO_FLAGS 0 1222 #define IBT_WR_SEND_IMMED (1 << 0) /* Immediate Data Indicator */ 1223 #define IBT_WR_SEND_SIGNAL (1 << 1) /* Signaled, if set */ 1224 #define IBT_WR_SEND_FENCE (1 << 2) /* Fence Indicator */ 1225 #define IBT_WR_SEND_SOLICIT (1 << 3) /* Solicited Event Indicator */ 1226 #define IBT_WR_SEND_REMOTE_INVAL (1 << 4) /* Remote Invalidate */ 1227 #define IBT_WR_SEND_CKSUM (1 << 5) /* Checksum offload Indicator */ 1228 #define IBT_WR_SEND_INLINE (1 << 6) /* INLINE required (no lkey) */ 1229 1230 /* 1231 * Access control flags for Bind Memory Window operation, 1232 * applicable for RC/UC/RD only. 1233 * 1234 * If IBT_WR_BIND_WRITE or IBT_WR_BIND_ATOMIC is desired then 1235 * it is required that Memory Region should have Local Write Access. 1236 */ 1237 typedef enum ibt_bind_flags_e { 1238 IBT_WR_BIND_READ = (1 << 0), /* enable remote read */ 1239 IBT_WR_BIND_WRITE = (1 << 1), /* enable remote write */ 1240 IBT_WR_BIND_ATOMIC = (1 << 2), /* enable remote atomics */ 1241 IBT_WR_BIND_ZBVA = (1 << 3) /* Zero Based Virtual Address */ 1242 } ibt_bind_flags_t; 1243 1244 /* 1245 * Data Segment for scatter-gather list 1246 * 1247 * SGL consists of an array of data segments and the length of the SGL. 1248 */ 1249 typedef struct ibt_wr_ds_s { 1250 ib_vaddr_t ds_va; /* Virtual Address */ 1251 ibt_lkey_t ds_key; /* L_Key */ 1252 ib_msglen_t ds_len; /* Length of DS */ 1253 } ibt_wr_ds_t; 1254 1255 /* 1256 * Bind Memory Window WR 1257 * 1258 * WR ID from ibt_send_wr_t applies here too, SWG_0038 errata. 1259 */ 1260 typedef struct ibt_wr_bind_s { 1261 ibt_bind_flags_t bind_flags; 1262 ibt_rkey_t bind_rkey; /* Mem Window's R_key */ 1263 ibt_lkey_t bind_lkey; /* Mem Region's L_Key */ 1264 ibt_rkey_t bind_rkey_out; /* OUT: new R_Key */ 1265 ibt_mr_hdl_t bind_ibt_mr_hdl; /* Mem Region handle */ 1266 ibt_mw_hdl_t bind_ibt_mw_hdl; /* Mem Window handle */ 1267 ib_vaddr_t bind_va; /* Virtual Address */ 1268 ib_memlen_t bind_len; /* Length of Window */ 1269 } ibt_wr_bind_t; 1270 1271 /* 1272 * Atomic WR 1273 * 1274 * Operation type (compare & swap or fetch & add) in ibt_wrc_opcode_t. 1275 * 1276 * A copy of the original contents of the remote memory will be stored 1277 * in the local data segment described by wr_sgl within ibt_send_wr_t, 1278 * and wr_nds should be set to 1. 1279 * 1280 * Atomic operation operands: 1281 * Compare & Swap Operation: 1282 * atom_arg1 - Compare Operand 1283 * atom_arg2 - Swap Operand 1284 * 1285 * Fetch & Add Operation: 1286 * atom_arg1 - Add Operand 1287 * atom_arg2 - ignored 1288 */ 1289 typedef struct ibt_wr_atomic_s { 1290 ib_vaddr_t atom_raddr; /* Remote address. */ 1291 ibt_atom_arg_t atom_arg1; /* operand #1 */ 1292 ibt_atom_arg_t atom_arg2; /* operand #2 */ 1293 ibt_rkey_t atom_rkey; /* R_Key. */ 1294 } ibt_wr_atomic_t; 1295 1296 /* 1297 * RDMA WR 1298 * Immediate Data indicator in ibt_wr_flags_t. 1299 */ 1300 typedef struct ibt_wr_rdma_s { 1301 ib_vaddr_t rdma_raddr; /* Remote address. */ 1302 ibt_rkey_t rdma_rkey; /* R_Key. */ 1303 ibt_immed_t rdma_immed; /* Immediate Data */ 1304 } ibt_wr_rdma_t; 1305 1306 /* 1307 * Fast Register Physical Memory Region Work Request. 1308 */ 1309 typedef struct ibt_wr_reg_pmr_s { 1310 ib_vaddr_t pmr_iova; /* I/O virtual address requested by */ 1311 /* client for the first byte of the */ 1312 /* region */ 1313 ib_memlen_t pmr_len; /* Length of region to register */ 1314 ib_memlen_t pmr_offset; /* Offset of the region's starting */ 1315 /* IOVA within the 1st physical */ 1316 /* buffer */ 1317 ibt_mr_hdl_t pmr_mr_hdl; 1318 ibt_phys_addr_t *pmr_addr_list; /* List of physical buffers accessed */ 1319 /* as an array */ 1320 size_t pmr_buf_sz; /* size of uniform size PBEs */ 1321 uint_t pmr_num_buf; /* #entries in the pmr_addr_list */ 1322 ibt_lkey_t pmr_lkey; /* new lkey upon return */ 1323 ibt_rkey_t pmr_rkey; /* new rkey upon return */ 1324 ibt_mr_flags_t pmr_flags; 1325 uint8_t pmr_key; /* Key to use on new Lkey & Rkey */ 1326 } ibt_wr_reg_pmr_t; 1327 1328 /* phys reg function or WR */ 1329 typedef union ibt_reg_req_u { 1330 ibt_pmr_attr_t fn_arg; 1331 ibt_wr_reg_pmr_t wr; 1332 } ibt_reg_req_t; 1333 1334 /* 1335 * Local Invalidate. 1336 */ 1337 typedef struct ibt_wr_li_s { 1338 ibt_mr_hdl_t li_mr_hdl; /* Null for MW invalidates */ 1339 ibt_mw_hdl_t li_mw_hdl; /* Null for MR invalidates */ 1340 ibt_lkey_t li_lkey; /* Ignore for MW invalidates */ 1341 ibt_rkey_t li_rkey; 1342 } ibt_wr_li_t; 1343 1344 /* 1345 * Reserved For Future Use. 1346 * Raw IPv6 Send WR 1347 */ 1348 typedef struct ibt_wr_ripv6_s { 1349 ib_lid_t rip_dlid; /* DLID */ 1350 ib_path_bits_t rip_slid_bits; /* SLID path bits, SWG_0033 errata */ 1351 uint8_t rip_sl:4; /* SL */ 1352 ibt_srate_t rip_rate; /* Max Static Rate, SWG_0007 errata */ 1353 } ibt_wr_ripv6_t; 1354 1355 /* 1356 * Reserved For Future Use. 1357 * Raw Ethertype Send WR 1358 */ 1359 typedef struct ibt_wr_reth_s { 1360 ib_ethertype_t reth_type; /* Ethertype */ 1361 ib_lid_t reth_dlid; /* DLID */ 1362 ib_path_bits_t reth_slid_bits; /* SLID path bits, SWG_0033 errata */ 1363 uint8_t reth_sl:4; /* SL */ 1364 ibt_srate_t reth_rate; /* Max Static Rate, SWG_0007 errata */ 1365 } ibt_wr_reth_t; 1366 1367 /* 1368 * Reserved For future Use. 1369 * RD Send WR, Operation type in ibt_wrc_opcode_t. 1370 */ 1371 typedef struct ibt_wr_rd_s { 1372 ibt_rd_dest_hdl_t rdwr_dest_hdl; 1373 union { 1374 ibt_immed_t send_immed; /* IBT_WRC_SEND */ 1375 ibt_wr_rdma_t rdma; /* IBT_WRC_RDMAR */ 1376 /* IBT_WRC_RDMAW */ 1377 ibt_wr_li_t *li; /* IBT_WRC_LOCAL_INVALIDATE */ 1378 ibt_wr_atomic_t *atomic; /* IBT_WRC_FADD */ 1379 /* IBT_WRC_CSWAP */ 1380 ibt_wr_bind_t *bind; /* IBT_WRC_BIND */ 1381 ibt_wr_reg_pmr_t *reg_pmr; /* IBT_WRC_FAST_REG_PMR */ 1382 } rdwr; 1383 } ibt_wr_rd_t; 1384 1385 /* 1386 * Reserved For Future Use. 1387 * UC Send WR, Operation type in ibt_wrc_opcode_t, the only valid 1388 * ones are: 1389 * IBT_WRC_SEND 1390 * IBT_WRC_RDMAW 1391 * IBT_WRC_BIND 1392 */ 1393 typedef struct ibt_wr_uc_s { 1394 union { 1395 ibt_immed_t send_immed; /* IBT_WRC_SEND */ 1396 ibt_wr_rdma_t rdma; /* IBT_WRC_RDMAW */ 1397 ibt_wr_li_t *li; /* IBT_WRC_LOCAL_INVALIDATE */ 1398 ibt_wr_bind_t *bind; /* IBT_WRC_BIND */ 1399 ibt_wr_reg_pmr_t *reg_pmr; /* IBT_WRC_FAST_REG_PMR */ 1400 } ucwr; 1401 } ibt_wr_uc_t; 1402 1403 /* 1404 * RC Send WR, Operation type in ibt_wrc_opcode_t. 1405 */ 1406 typedef struct ibt_wr_rc_s { 1407 union { 1408 ibt_immed_t send_immed; /* IBT_WRC_SEND w/ immediate */ 1409 ibt_rkey_t send_inval; /* IBT_WRC_SEND w/ invalidate */ 1410 ibt_wr_rdma_t rdma; /* IBT_WRC_RDMAR */ 1411 /* IBT_WRC_RDMAW */ 1412 ibt_wr_li_t *li; /* IBT_WRC_LOCAL_INVALIDATE */ 1413 ibt_wr_atomic_t *atomic; /* IBT_WRC_CSWAP */ 1414 /* IBT_WRC_FADD */ 1415 ibt_wr_bind_t *bind; /* IBT_WRC_BIND */ 1416 ibt_wr_reg_pmr_t *reg_pmr; /* IBT_WRC_FAST_REG_PMR */ 1417 } rcwr; 1418 } ibt_wr_rc_t; 1419 1420 /* 1421 * UD Send WR, the only valid Operation is IBT_WRC_SEND. 1422 */ 1423 typedef struct ibt_wr_ud_s { 1424 ibt_immed_t udwr_immed; 1425 ibt_ud_dest_hdl_t udwr_dest; 1426 } ibt_wr_ud_t; 1427 1428 /* LSO variant */ 1429 typedef struct ibt_wr_lso_s { 1430 ibt_ud_dest_hdl_t lso_ud_dest; 1431 uint8_t *lso_hdr; 1432 ib_msglen_t lso_hdr_sz; 1433 ib_msglen_t lso_mss; 1434 } ibt_wr_lso_t; 1435 1436 /* 1437 * Send Work Request (WR) attributes structure. 1438 * 1439 * Operation type in ibt_wrc_opcode_t. 1440 * Immediate Data indicator in ibt_wr_flags_t. 1441 */ 1442 typedef struct ibt_send_wr_s { 1443 ibt_wrid_t wr_id; /* WR ID */ 1444 ibt_wr_flags_t wr_flags; /* Work Request Flags. */ 1445 ibt_tran_srv_t wr_trans; /* Transport Type. */ 1446 ibt_wrc_opcode_t wr_opcode; /* Operation Type. */ 1447 uint8_t wr_rsvd; /* maybe later */ 1448 uint32_t wr_nds; /* Number of data segments */ 1449 /* pointed to by wr_sgl */ 1450 ibt_wr_ds_t *wr_sgl; /* SGL */ 1451 union { 1452 ibt_wr_ud_t ud; 1453 ibt_wr_rc_t rc; 1454 ibt_wr_rd_t rd; /* Reserved For Future Use */ 1455 ibt_wr_uc_t uc; /* Reserved For Future Use */ 1456 ibt_wr_reth_t reth; /* Reserved For Future Use */ 1457 ibt_wr_ripv6_t ripv6; /* Reserved For Future Use */ 1458 ibt_wr_lso_t ud_lso; 1459 } wr; /* operation specific */ 1460 } ibt_send_wr_t; 1461 1462 /* 1463 * Receive Work Request (WR) attributes structure. 1464 */ 1465 typedef struct ibt_recv_wr_s { 1466 ibt_wrid_t wr_id; /* WR ID */ 1467 uint32_t wr_nds; /* number of data segments */ 1468 /* pointed to by wr_sgl */ 1469 ibt_wr_ds_t *wr_sgl; /* SGL */ 1470 } ibt_recv_wr_t; 1471 1472 typedef union ibt_all_wr_u { 1473 ibt_send_wr_t send; 1474 ibt_recv_wr_t recv; 1475 } ibt_all_wr_t; 1476 1477 1478 /* 1479 * Asynchronous Events and Errors. 1480 * 1481 * The following codes are not used in calls to ibc_async_handler, but 1482 * are used by IBTL to inform IBT clients of a significant event. 1483 * 1484 * IBT_HCA_ATTACH_EVENT - New HCA available. 1485 * IBT_HCA_DETACH_EVENT - HCA is requesting not to be used. 1486 * 1487 * ERRORs on a channel indicate that the channel has entered error state. 1488 * EVENTs on a channel indicate that the channel has not changed state. 1489 * 1490 */ 1491 typedef enum ibt_async_code_e { 1492 IBT_EVENT_PATH_MIGRATED = 0x000001, 1493 IBT_EVENT_SQD = 0x000002, 1494 IBT_EVENT_COM_EST = 0x000004, 1495 IBT_ERROR_CATASTROPHIC_CHAN = 0x000008, 1496 IBT_ERROR_INVALID_REQUEST_CHAN = 0x000010, 1497 IBT_ERROR_ACCESS_VIOLATION_CHAN = 0x000020, 1498 IBT_ERROR_PATH_MIGRATE_REQ = 0x000040, 1499 1500 IBT_ERROR_CQ = 0x000080, 1501 1502 IBT_EVENT_PORT_UP = 0x000100, 1503 IBT_ERROR_PORT_DOWN = 0x000200, 1504 IBT_ERROR_LOCAL_CATASTROPHIC = 0x000400, 1505 1506 IBT_HCA_ATTACH_EVENT = 0x000800, 1507 IBT_HCA_DETACH_EVENT = 0x001000, 1508 IBT_ASYNC_OPAQUE1 = 0x002000, 1509 IBT_ASYNC_OPAQUE2 = 0x004000, 1510 IBT_ASYNC_OPAQUE3 = 0x008000, 1511 IBT_ASYNC_OPAQUE4 = 0x010000, 1512 IBT_EVENT_LIMIT_REACHED_SRQ = 0x020000, 1513 IBT_EVENT_EMPTY_CHAN = 0x040000, 1514 IBT_ERROR_CATASTROPHIC_SRQ = 0x080000, 1515 1516 IBT_PORT_CHANGE_EVENT = 0x100000, 1517 IBT_CLNT_REREG_EVENT = 0x200000 1518 } ibt_async_code_t; 1519 1520 #define IBT_PORT_EVENTS (IBT_EVENT_PORT_UP|IBT_PORT_CHANGE_EVENT|\ 1521 IBT_ERROR_PORT_DOWN|IBT_CLNT_REREG_EVENT) 1522 1523 typedef enum ibt_port_change_e { 1524 IBT_PORT_CHANGE_SGID = 0x000001, /* SGID table */ 1525 IBT_PORT_CHANGE_PKEY = 0x000002, /* P_Key table */ 1526 IBT_PORT_CHANGE_SM_LID = 0x000004, /* Master SM LID */ 1527 IBT_PORT_CHANGE_SM_SL = 0x000008, /* Master SM SL */ 1528 IBT_PORT_CHANGE_SUB_TIMEOUT = 0x000010, /* Subnet Timeout */ 1529 IBT_PORT_CHANGE_SM_FLAG = 0x000020, /* IsSMDisabled bit */ 1530 IBT_PORT_CHANGE_REREG = 0x000040 /* IsClientReregSupport */ 1531 } ibt_port_change_t; 1532 1533 /* 1534 * ibt_ci_data_in() and ibt_ci_data_out() flags. 1535 */ 1536 typedef enum ibt_ci_data_flags_e { 1537 IBT_CI_NO_FLAGS = 0, 1538 IBT_CI_COMPLETE_ALLOC = (1 << 0) 1539 } ibt_ci_data_flags_t; 1540 1541 /* 1542 * Used by ibt_ci_data_in() and ibt_ci_data_out() identifies the type of handle 1543 * mapping data is being obtained for. 1544 */ 1545 typedef enum ibt_object_type_e { 1546 IBT_HDL_HCA = 1, 1547 IBT_HDL_CHANNEL, 1548 IBT_HDL_CQ, 1549 IBT_HDL_PD, 1550 IBT_HDL_MR, 1551 IBT_HDL_MW, 1552 IBT_HDL_UD_DEST, 1553 IBT_HDL_SCHED, 1554 IBT_HDL_OPAQUE1, 1555 IBT_HDL_OPAQUE2, 1556 IBT_HDL_SRQ 1557 } ibt_object_type_t; 1558 1559 /* 1560 * Standard information for ibt_ci_data_in() for memory regions. 1561 * 1562 * IBT_MR_DATA_IN_IF_VERSION is the value used in the mr_rev member. 1563 * mr_func is the callback handler. mr_arg1 and mr_arg2 are its arguments. 1564 */ 1565 #define IBT_MR_DATA_IN_IF_VERSION 1 1566 typedef struct ibt_mr_data_in_s { 1567 uint_t mr_rev; 1568 void (*mr_func)(void *, void *); 1569 void *mr_arg1; 1570 void *mr_arg2; 1571 } ibt_mr_data_in_t; 1572 1573 /* 1574 * Memory error handler data structures; code, and payload data. 1575 */ 1576 typedef enum ibt_mem_code_s { 1577 IBT_MEM_AREA = 0x1, 1578 IBT_MEM_REGION = 0x2 1579 } ibt_mem_code_t; 1580 1581 typedef struct ibt_mem_data_s { 1582 uint64_t ev_fma_ena; /* FMA Error data */ 1583 ibt_mr_hdl_t ev_mr_hdl; /* MR handle */ 1584 ibt_ma_hdl_t ev_ma_hdl; /* MA handle */ 1585 } ibt_mem_data_t; 1586 1587 /* 1588 * Special case failure type. 1589 */ 1590 typedef enum ibt_failure_type_e { 1591 IBT_FAILURE_STANDARD = 0, 1592 IBT_FAILURE_CI, 1593 IBT_FAILURE_IBMF, 1594 IBT_FAILURE_IBTL, 1595 IBT_FAILURE_IBCM, 1596 IBT_FAILURE_IBDM, 1597 IBT_FAILURE_IBSM 1598 } ibt_failure_type_t; 1599 1600 /* 1601 * RDMA IP CM service Annex definitions 1602 */ 1603 typedef struct ibt_ip_addr_s { 1604 sa_family_t family; /* AF_INET or AF_INET6 */ 1605 union { 1606 in_addr_t ip4addr; 1607 in6_addr_t ip6addr; 1608 } un; 1609 uint32_t ip6_scope_id; /* Applicable only for AF_INET6 */ 1610 } ibt_ip_addr_t; 1611 1612 #ifdef __cplusplus 1613 } 1614 #endif 1615 1616 #endif /* _SYS_IB_IBTL_IBTL_TYPES_H */ 1617