1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_IB_IBTL_IBTL_TYPES_H 27 #define _SYS_IB_IBTL_IBTL_TYPES_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 /* 32 * ibtl_types.h 33 * 34 * All common IBTL defined types. These are common data types 35 * that are shared by the IBTI and IBCI interfaces, it is only included 36 * by ibti.h and ibci.h 37 */ 38 #include <sys/ddi.h> 39 #include <sys/sunddi.h> 40 #include <sys/ib/ib_types.h> 41 #include <sys/ib/ibtl/ibtl_status.h> 42 43 #ifdef __cplusplus 44 extern "C" { 45 #endif 46 47 /* 48 * Define Internal IBTL handles 49 */ 50 typedef struct ibtl_clnt_s *ibt_clnt_hdl_t; /* ibt_attach() */ 51 typedef struct ibtl_hca_s *ibt_hca_hdl_t; /* ibt_open_hca() */ 52 typedef struct ibtl_channel_s *ibt_channel_hdl_t; /* alloc_rc|ud_channel() */ 53 typedef struct ibtl_srq_s *ibt_srq_hdl_t; /* ibt_alloc_srq() */ 54 typedef struct ibtl_cq_s *ibt_cq_hdl_t; /* ibt_alloc_cq() */ 55 typedef struct ibcm_svc_info_s *ibt_srv_hdl_t; /* ibt_register_service() */ 56 typedef struct ibcm_svc_bind_s *ibt_sbind_hdl_t; /* ibt_bind_service() */ 57 58 typedef struct ibc_fmr_pool_s *ibt_fmr_pool_hdl_t; /* ibt_create_fmr_pool() */ 59 typedef struct ibc_ma_s *ibt_ma_hdl_t; /* ibt_map_mem_area() */ 60 typedef struct ibc_pd_s *ibt_pd_hdl_t; /* ibt_alloc_pd() */ 61 typedef struct ibc_sched_s *ibt_sched_hdl_t; /* ibt_alloc_cq_sched() */ 62 typedef struct ibc_mr_s *ibt_mr_hdl_t; /* ibt_register_mr() */ 63 typedef struct ibc_mw_s *ibt_mw_hdl_t; /* ibt_alloc_mw() */ 64 typedef struct ibt_ud_dest_s *ibt_ud_dest_hdl_t; /* UD dest handle */ 65 typedef struct ibc_ah_s *ibt_ah_hdl_t; /* ibt_alloc_ah() */ 66 typedef struct ibtl_eec_s *ibt_eec_hdl_t; 67 typedef struct ibt_rd_dest_s *ibt_rd_dest_hdl_t; /* Reserved for */ 68 /* Future use */ 69 70 /* 71 * Some General Types. 72 */ 73 typedef uint32_t ibt_lkey_t; /* L_Key */ 74 typedef uint32_t ibt_rkey_t; /* R_Key */ 75 typedef uint64_t ibt_wrid_t; /* Client assigned WR ID */ 76 typedef uint32_t ibt_immed_t; /* WR Immediate Data */ 77 typedef uint64_t ibt_atom_arg_t; /* WR Atomic Operation arg */ 78 typedef uint_t ibt_cq_handler_id_t; /* Event handler ID */ 79 80 /* 81 * IBT selector type, used when looking up/requesting either an 82 * MTU, Pkt lifetime, or Static rate. 83 * The interpretation of IBT_BEST depends on the attribute being selected. 84 */ 85 typedef enum ibt_selector_e { 86 IBT_GT = 0, /* Greater than */ 87 IBT_LT = 1, /* Less than */ 88 IBT_EQU = 2, /* Equal to */ 89 IBT_BEST = 3 /* Best */ 90 } ibt_selector_t; 91 92 93 /* 94 * Static rate definitions. 95 */ 96 typedef enum ibt_srate_e { 97 IBT_SRATE_NOT_SPECIFIED = 0, 98 IBT_SRATE_2 = 2, /* 1X SDR i.e 2.5 Gbps */ 99 IBT_SRATE_10 = 3, /* 4X SDR or 1X QDR i.e 10 Gbps */ 100 IBT_SRATE_30 = 4, /* 12X SDR i.e 30 Gbps */ 101 102 IBT_SRATE_5 = 5, /* 1X DDR i.e 5 Gbps */ 103 IBT_SRATE_20 = 6, /* 4X DDR or 8X SDR i.e 20 Gbps */ 104 IBT_SRATE_40 = 7, /* 8X DDR or 4X QDR i.e 40 Gbps */ 105 106 IBT_SRATE_60 = 8, /* 12X DDR i.e 60 Gbps */ 107 IBT_SRATE_80 = 9, /* 8X QDR i.e 80 Gbps */ 108 IBT_SRATE_120 = 10 /* 12X QDR i.e 120 Gbps */ 109 } ibt_srate_t; 110 111 /* retain old definition to be compatible with older bits. */ 112 #define IBT_SRATE_1X IBT_SRATE_2 113 #define IBT_SRATE_4X IBT_SRATE_10 114 #define IBT_SRATE_12X IBT_SRATE_30 115 116 /* 117 * Static rate request type. 118 */ 119 typedef struct ibt_srate_req_s { 120 ibt_srate_t r_srate; /* Requested srate */ 121 ibt_selector_t r_selector; /* Qualifier for r_srate */ 122 } ibt_srate_req_t; 123 124 /* 125 * Packet Life Time Request Type. 126 */ 127 typedef struct ibt_pkt_lt_req_s { 128 clock_t p_pkt_lt; /* Requested Packet Life Time */ 129 ibt_selector_t p_selector; /* Qualifier for p_pkt_lt */ 130 } ibt_pkt_lt_req_t; 131 132 /* 133 * Queue size struct. 134 */ 135 typedef struct ibt_queue_sizes_s { 136 uint_t qs_sq; /* SendQ size. */ 137 uint_t qs_rq; /* RecvQ size. */ 138 } ibt_queue_sizes_t; 139 140 /* 141 * Channel sizes struct, used by functions that allocate/query RC or UD 142 * channels. 143 */ 144 typedef struct ibt_chan_sizes_s { 145 uint_t cs_sq; /* SendQ size. */ 146 uint_t cs_rq; /* ReceiveQ size. */ 147 uint_t cs_sq_sgl; /* Max SGL elements in a SQ WR. */ 148 uint_t cs_rq_sgl; /* Max SGL elements in a RQ Wr. */ 149 } ibt_chan_sizes_t; 150 151 /* 152 * Shared Queue size struct. 153 */ 154 typedef struct ibt_srq_sizes_s { 155 uint_t srq_wr_sz; 156 uint_t srq_sgl_sz; 157 } ibt_srq_sizes_t; 158 159 /* 160 * SRQ Modify Flags 161 */ 162 typedef enum ibt_srq_modify_flags_e { 163 IBT_SRQ_SET_NOTHING = 0, 164 IBT_SRQ_SET_SIZE = (1 << 1), 165 IBT_SRQ_SET_LIMIT = (1 << 2) 166 } ibt_srq_modify_flags_t; 167 168 169 /* 170 * Execution flags, indicates if the function should block or not. 171 * Note: in some cases, e.g., a NULL rc_cm_handler, IBT_NONBLOCKING 172 * will not have an effect, and the thread will block. 173 * IBT_NOCALLBACKS is valid for ibt_close_rc_channel only. 174 */ 175 typedef enum ibt_execution_mode_e { 176 IBT_BLOCKING = 0, /* Block */ 177 IBT_NONBLOCKING = 1, /* Return as soon as possible */ 178 IBT_NOCALLBACKS = 2 /* cm_handler is not invoked after */ 179 /* ibt_close_rc_channel returns */ 180 } ibt_execution_mode_t; 181 182 /* 183 * Memory window alloc flags 184 */ 185 typedef enum ibt_mw_flags_e { 186 IBT_MW_SLEEP = 0, /* Can block */ 187 IBT_MW_NOSLEEP = (1 << 0), /* Can't block */ 188 IBT_MW_USER_MAP = (1 << 1), 189 IBT_MW_DEFER_ALLOC = (1 << 2), 190 IBT_MW_TYPE_1 = (1 << 3), 191 IBT_MW_TYPE_2 = (1 << 4) 192 } ibt_mw_flags_t; 193 194 /* 195 * PD alloc flags 196 */ 197 typedef enum ibt_pd_flags_e { 198 IBT_PD_NO_FLAGS = 0, 199 IBT_PD_USER_MAP = (1 << 0), 200 IBT_PD_DEFER_ALLOC = (1 << 1) 201 } ibt_pd_flags_t; 202 203 /* 204 * UD Dest alloc flags 205 */ 206 typedef enum ibt_ud_dest_flags_e { 207 IBT_UD_DEST_NO_FLAGS = 0, 208 IBT_UD_DEST_USER_MAP = (1 << 0), 209 IBT_UD_DEST_DEFER_ALLOC = (1 << 1) 210 } ibt_ud_dest_flags_t; 211 212 /* 213 * SRQ alloc flags 214 */ 215 typedef enum ibt_srq_flags_e { 216 IBT_SRQ_NO_FLAGS = 0, 217 IBT_SRQ_USER_MAP = (1 << 0), 218 IBT_SRQ_DEFER_ALLOC = (1 << 1) 219 } ibt_srq_flags_t; 220 221 /* 222 * ibt_alloc_lkey() alloc flags 223 */ 224 typedef enum ibt_lkey_flags_e { 225 IBT_KEY_NO_FLAGS = 0, 226 IBT_KEY_REMOTE = (1 << 0) 227 } ibt_lkey_flags_t; 228 229 /* 230 * RNR NAK retry counts. 231 */ 232 typedef enum ibt_rnr_retry_cnt_e { 233 IBT_RNR_NO_RETRY = 0x0, /* Don't retry, fail on first timeout */ 234 IBT_RNR_RETRY_1 = 0x1, /* Retry once */ 235 IBT_RNR_RETRY_2 = 0x2, /* Retry twice */ 236 IBT_RNR_RETRY_3 = 0x3, /* Retry three times */ 237 IBT_RNR_RETRY_4 = 0x4, /* Retry four times */ 238 IBT_RNR_RETRY_5 = 0x5, /* Retry five times */ 239 IBT_RNR_RETRY_6 = 0x6, /* Retry six times */ 240 IBT_RNR_INFINITE_RETRY = 0x7 /* Retry forever */ 241 } ibt_rnr_retry_cnt_t; 242 243 /* 244 * Valid values for RNR NAK timer fields, part of a channel's context. 245 */ 246 typedef enum ibt_rnr_nak_time_e { 247 IBT_RNR_NAK_655ms = 0x0, 248 IBT_RNR_NAK_10us = 0x1, 249 IBT_RNR_NAK_20us = 0x2, 250 IBT_RNR_NAK_30us = 0x3, 251 IBT_RNR_NAK_40us = 0x4, 252 IBT_RNR_NAK_60us = 0x5, 253 IBT_RNR_NAK_80us = 0x6, 254 IBT_RNR_NAK_120us = 0x7, 255 IBT_RNR_NAK_160us = 0x8, 256 IBT_RNR_NAK_240us = 0x9, 257 IBT_RNR_NAK_320us = 0xA, 258 IBT_RNR_NAK_480us = 0xB, 259 IBT_RNR_NAK_640us = 0xC, 260 IBT_RNR_NAK_960us = 0xD, 261 IBT_RNR_NAK_1280us = 0xE, 262 IBT_RNR_NAK_1920us = 0xF, 263 IBT_RNR_NAK_2560us = 0x10, 264 IBT_RNR_NAK_3840us = 0x11, 265 IBT_RNR_NAK_5120us = 0x12, 266 IBT_RNR_NAK_7680us = 0x13, 267 IBT_RNR_NAK_10ms = 0x14, 268 IBT_RNR_NAK_15ms = 0x15, 269 IBT_RNR_NAK_20ms = 0x16, 270 IBT_RNR_NAK_31ms = 0x17, 271 IBT_RNR_NAK_41ms = 0x18, 272 IBT_RNR_NAK_61ms = 0x19, 273 IBT_RNR_NAK_82ms = 0x1A, 274 IBT_RNR_NAK_123ms = 0x1B, 275 IBT_RNR_NAK_164ms = 0x1C, 276 IBT_RNR_NAK_246ms = 0x1D, 277 IBT_RNR_NAK_328ms = 0x1E, 278 IBT_RNR_NAK_492ms = 0x1F 279 } ibt_rnr_nak_time_t; 280 281 /* 282 * The definition of HCA capabilities etc as a bitfield. 283 */ 284 typedef enum ibt_hca_flags_e { 285 IBT_HCA_NO_FLAGS = 0, 286 287 IBT_HCA_RD = 1 << 0, 288 IBT_HCA_UD_MULTICAST = 1 << 1, 289 IBT_HCA_RAW_MULTICAST = 1 << 2, 290 291 IBT_HCA_ATOMICS_HCA = 1 << 3, 292 IBT_HCA_ATOMICS_GLOBAL = 1 << 4, 293 294 IBT_HCA_RESIZE_CHAN = 1 << 5, /* Is resize supported? */ 295 IBT_HCA_AUTO_PATH_MIG = 1 << 6, /* Is APM supported? */ 296 IBT_HCA_SQD_SQD_PORT = 1 << 7, /* Can change physical port */ 297 /* on transit from SQD to SQD */ 298 IBT_HCA_PKEY_CNTR = 1 << 8, 299 IBT_HCA_QKEY_CNTR = 1 << 9, 300 IBT_HCA_AH_PORT_CHECK = 1 << 10, /* HCA checks AH port match */ 301 /* in UD WRs */ 302 IBT_HCA_PORT_UP = 1 << 11, /* PortActive event supported */ 303 IBT_HCA_INIT_TYPE = 1 << 12, /* InitType supported */ 304 IBT_HCA_SI_GUID = 1 << 13, /* System Image GUID */ 305 /* supported */ 306 IBT_HCA_SHUTDOWN_PORT = 1 << 14, /* ShutdownPort supported */ 307 IBT_HCA_RNR_NAK = 1 << 15, /* RNR-NAK supported for RC */ 308 IBT_HCA_CURRENT_QP_STATE = 1 << 16, /* Does modify_qp support */ 309 /* checking of current state? */ 310 IBT_HCA_SRQ = 1 << 17, /* Shared Receive Queue */ 311 IBT_HCA_RESIZE_SRQ = 1 << 18, /* Is resize SRQ supported? */ 312 IBT_HCA_BASE_MEM_MGT = 1 << 19, /* Base memory mgt supported? */ 313 IBT_HCA_MULT_PAGE_SZ_MR = 1 << 20, /* Support of multiple page */ 314 /* sizes per memory region? */ 315 IBT_HCA_BLOCK_LIST = 1 << 21, /* Block list physical buffer */ 316 /* lists supported? */ 317 IBT_HCA_ZERO_BASED_VA = 1 << 22, /* Zero Based Virtual */ 318 /* Addresses supported? */ 319 IBT_HCA_LOCAL_INVAL_FENCE = 1 << 23, /* Local invalidate fencing? */ 320 IBT_HCA_BASE_QUEUE_MGT = 1 << 24, /* Base Queue Mgt supported? */ 321 IBT_HCA_CKSUM_FULL = 1 << 25, /* Checksum offload supported */ 322 IBT_HCA_MEM_WIN_TYPE_2B = 1 << 26, /* Type 2B memory windows */ 323 IBT_HCA_PHYS_BUF_BLOCK = 1 << 27, /* Block mode phys buf lists */ 324 IBT_HCA_FMR = 1 << 28 /* FMR Support */ 325 } ibt_hca_flags_t; 326 327 /* 328 * The definition of HCA page size capabilities as a bitfield 329 */ 330 typedef enum ibt_page_sizes_e { 331 IBT_PAGE_4K = 0x1 << 2, 332 IBT_PAGE_8K = 0x1 << 3, 333 IBT_PAGE_16K = 0x1 << 4, 334 IBT_PAGE_32K = 0x1 << 5, 335 IBT_PAGE_64K = 0x1 << 6, 336 IBT_PAGE_128K = 0x1 << 7, 337 IBT_PAGE_256K = 0x1 << 8, 338 IBT_PAGE_512K = 0x1 << 9, 339 IBT_PAGE_1M = 0x1 << 10, 340 IBT_PAGE_2M = 0x1 << 11, 341 IBT_PAGE_4M = 0x1 << 12, 342 IBT_PAGE_8M = 0x1 << 13, 343 IBT_PAGE_16M = 0x1 << 14, 344 IBT_PAGE_32M = 0x1 << 15, 345 IBT_PAGE_64M = 0x1 << 16, 346 IBT_PAGE_128M = 0x1 << 17, 347 IBT_PAGE_256M = 0x1 << 18, 348 IBT_PAGE_512M = 0x1 << 19, 349 IBT_PAGE_1G = 0x1 << 20, 350 IBT_PAGE_2G = 0x1 << 21, 351 IBT_PAGE_4G = 0x1 << 22, 352 IBT_PAGE_8G = 0x1 << 23, 353 IBT_PAGE_16G = 0x1 << 24 354 } ibt_page_sizes_t; 355 356 /* 357 * Memory Window Type. 358 */ 359 typedef enum ibt_mem_win_type_e { 360 IBT_MEM_WIN_TYPE_NOT_DEFINED = 0, 361 IBT_MEM_WIN_TYPE_1 = (1 << 0), 362 IBT_MEM_WIN_TYPE_2 = (1 << 1) 363 } ibt_mem_win_type_t; 364 365 /* 366 * HCA attributes. 367 * Contains all HCA static attributes. 368 */ 369 typedef struct ibt_hca_attr_s { 370 ibt_hca_flags_t hca_flags; /* HCA capabilities etc */ 371 372 /* device/version inconsistency w/ NodeInfo and IOControllerProfile */ 373 uint32_t hca_vendor_id:24; /* 24 bit Vendor ID */ 374 uint16_t hca_device_id; 375 uint32_t hca_version_id; 376 377 uint_t hca_max_chans; /* Max Chans supported */ 378 uint_t hca_max_chan_sz; /* Max outstanding WRs on any */ 379 /* channel */ 380 381 uint_t hca_max_sgl; /* Max SGL entries per WR */ 382 383 uint_t hca_max_cq; /* Max num of CQs supported */ 384 uint_t hca_max_cq_sz; /* Max capacity of each CQ */ 385 386 ibt_page_sizes_t hca_page_sz; /* Bit mask of page sizes */ 387 388 uint_t hca_max_memr; /* Max num of HCA mem regions */ 389 ib_memlen_t hca_max_memr_len; /* Largest block, in bytes of */ 390 /* mem that can be registered */ 391 uint_t hca_max_mem_win; /* Max Memory windows in HCA */ 392 393 uint_t hca_max_rsc; /* Max Responder Resources of */ 394 /* this HCA for RDMAR/Atomics */ 395 /* with this HCA as target. */ 396 uint8_t hca_max_rdma_in_chan; /* Max RDMAR/Atomics in per */ 397 /* chan this HCA as target. */ 398 uint8_t hca_max_rdma_out_chan; /* Max RDMA Reads/Atomics out */ 399 /* per channel by this HCA */ 400 uint_t hca_max_ipv6_chan; /* Max IPV6 channels in HCA */ 401 uint_t hca_max_ether_chan; /* Max Ether channels in HCA */ 402 403 uint_t hca_max_mcg_chans; /* Max number of channels */ 404 /* that can join multicast */ 405 /* groups */ 406 uint_t hca_max_mcg; /* Max multicast groups */ 407 uint_t hca_max_chan_per_mcg; /* Max number of channels per */ 408 /* Multicast group in HCA */ 409 410 uint16_t hca_max_partitions; /* Max partitions in HCA */ 411 uint8_t hca_nports; /* Number of physical ports */ 412 ib_guid_t hca_node_guid; /* Node GUID */ 413 414 ib_time_t hca_local_ack_delay; 415 416 uint_t hca_max_port_sgid_tbl_sz; 417 uint16_t hca_max_port_pkey_tbl_sz; 418 uint_t hca_max_pd; /* Max# of Protection Domains */ 419 ib_guid_t hca_si_guid; /* Optional System Image GUID */ 420 uint_t hca_hca_max_ci_priv_sz; 421 uint_t hca_chan_max_ci_priv_sz; 422 uint_t hca_cq_max_ci_priv_sz; 423 uint_t hca_pd_max_ci_priv_sz; 424 uint_t hca_mr_max_ci_priv_sz; 425 uint_t hca_mw_max_ci_priv_sz; 426 uint_t hca_ud_dest_max_ci_priv_sz; 427 uint_t hca_cq_sched_max_ci_priv_sz; 428 uint_t hca_max_ud_dest; 429 uint_t hca_opaque2; 430 uint_t hca_opaque3; 431 uint_t hca_opaque4; 432 uint8_t hca_opaque5; 433 uint8_t hca_opaque6; 434 uint_t hca_opaque7; 435 uint_t hca_opaque8; 436 uint_t hca_max_srqs; /* Max SRQs supported */ 437 uint_t hca_max_srqs_sz; /* Max outstanding WRs on any */ 438 /* SRQ */ 439 uint_t hca_max_srq_sgl; /* Max SGL entries per SRQ WR */ 440 uint_t hca_max_phys_buf_list_sz; 441 size_t hca_block_sz_lo; /* Range of block sizes */ 442 size_t hca_block_sz_hi; /* supported by the HCA */ 443 uint_t hca_max_cq_handlers; 444 ibt_lkey_t hca_reserved_lkey; 445 uint_t hca_max_fmrs; /* Max FMR Supported */ 446 uint_t hca_opaque9; 447 } ibt_hca_attr_t; 448 449 /* 450 * HCA Port link states. 451 */ 452 typedef enum ibt_port_state_e { 453 IBT_PORT_DOWN = 1, 454 IBT_PORT_INIT, 455 IBT_PORT_ARM, 456 IBT_PORT_ACTIVE 457 } ibt_port_state_t; 458 459 /* 460 * HCA Port capabilities as a bitfield. 461 */ 462 typedef enum ibt_port_caps_e { 463 IBT_PORT_CAP_NO_FLAGS = 0, 464 IBT_PORT_CAP_SM = 1 << 0, /* SM port */ 465 IBT_PORT_CAP_SM_DISABLED = 1 << 1, 466 IBT_PORT_CAP_SNMP_TUNNEL = 1 << 2, /* SNMP Tunneling */ 467 IBT_PORT_CAP_DM = 1 << 3, /* DM supported */ 468 IBT_PORT_CAP_VENDOR = 1 << 4 /* Vendor Class */ 469 } ibt_port_caps_t; 470 471 472 /* 473 * HCA port attributes structure definition. The number of ports per HCA 474 * can be found from the "ibt_hca_attr_t" structure. 475 * 476 * p_pkey_tbl is a pointer to an array of ib_pkey_t, members are 477 * accessed as: 478 * hca_portinfo->p_pkey_tbl[i] 479 * 480 * Where 0 <= i < hca_portinfo.p_pkey_tbl_sz 481 * 482 * Similarly p_sgid_tbl is a pointer to an array of ib_gid_t. 483 * 484 * The Query Port function - ibt_query_hca_ports() allocates the memory 485 * required for the ibt_hca_portinfo_t struct as well as the memory 486 * required for the SGID and P_Key tables. The memory is freed by calling 487 * ibt_free_portinfo(). 488 */ 489 typedef struct ibt_hca_portinfo_s { 490 ib_lid_t p_opaque1; /* Base LID of port */ 491 ib_qkey_cntr_t p_qkey_violations; /* Bad Q_Key cnt */ 492 ib_pkey_cntr_t p_pkey_violations; /* Optional bad P_Key cnt */ 493 uint8_t p_sm_sl:4; /* SM Service level */ 494 ib_lid_t p_sm_lid; /* SM LID */ 495 ibt_port_state_t p_linkstate; /* Port state */ 496 uint8_t p_port_num; 497 ib_mtu_t p_mtu; /* Max transfer unit - pkt */ 498 uint8_t p_lmc:3; /* Local mask control */ 499 ib_gid_t *p_sgid_tbl; /* SGID Table */ 500 uint_t p_sgid_tbl_sz; /* Size of SGID table */ 501 uint16_t p_pkey_tbl_sz; /* Size of P_Key table */ 502 uint16_t p_def_pkey_ix; /* default pkey index for TI */ 503 ib_pkey_t *p_pkey_tbl; /* P_Key table */ 504 uint8_t p_max_vl; /* Max num of virtual lanes */ 505 uint8_t p_init_type_reply; /* Optional InitTypeReply */ 506 ib_time_t p_subnet_timeout; /* Max Subnet Timeout */ 507 ibt_port_caps_t p_capabilities; /* Port Capabilities */ 508 uint32_t p_msg_sz; /* Max message size */ 509 } ibt_hca_portinfo_t; 510 511 /* 512 * Modify HCA port attributes flags, specifies which HCA port 513 * attributes to modify. 514 */ 515 typedef enum ibt_port_modify_flags_e { 516 IBT_PORT_NO_FLAGS = 0, 517 518 IBT_PORT_RESET_QKEY = 1 << 0, /* Reset Q_Key violation */ 519 /* counter */ 520 IBT_PORT_RESET_SM = 1 << 1, /* SM */ 521 IBT_PORT_SET_SM = 1 << 2, 522 IBT_PORT_RESET_SNMP = 1 << 3, /* SNMP Tunneling */ 523 IBT_PORT_SET_SNMP = 1 << 4, 524 IBT_PORT_RESET_DEVMGT = 1 << 5, /* Device Management */ 525 IBT_PORT_SET_DEVMGT = 1 << 6, 526 IBT_PORT_RESET_VENDOR = 1 << 7, /* Vendor Class */ 527 IBT_PORT_SET_VENDOR = 1 << 8, 528 IBT_PORT_SHUTDOWN = 1 << 9, /* Shut down the port */ 529 IBT_PORT_SET_INIT_TYPE = 1 << 10 /* InitTypeReply value */ 530 } ibt_port_modify_flags_t; 531 532 /* 533 * Modify HCA port InitType bit definitions, applicable only if 534 * IBT_PORT_SET_INIT_TYPE modify flag (ibt_port_modify_flags_t) is set. 535 */ 536 #define IBT_PINIT_NO_LOAD 0x1 537 #define IBT_PINIT_PRESERVE_CONTENT 0x2 538 #define IBT_PINIT_PRESERVE_PRESENCE 0x4 539 #define IBT_PINIT_NO_RESUSCITATE 0x8 540 541 542 /* 543 * Address vector definition. 544 */ 545 typedef struct ibt_adds_vect_s { 546 ib_gid_t av_dgid; /* IPV6 dest GID in GRH */ 547 ib_gid_t av_sgid; /* SGID */ 548 ibt_srate_t av_srate; /* Max static rate */ 549 uint8_t av_srvl:4; /* Service level in LRH */ 550 uint_t av_flow:20; /* 20 bit Flow Label */ 551 uint8_t av_tclass; /* Traffic Class */ 552 uint8_t av_hop; /* Hop Limit */ 553 uint8_t av_port_num; /* Port number for UD */ 554 boolean_t av_opaque1; 555 ib_lid_t av_opaque2; 556 ib_path_bits_t av_opaque3; 557 uint32_t av_opaque4; 558 } ibt_adds_vect_t; 559 560 typedef struct ibt_cep_path_s { 561 ibt_adds_vect_t cep_adds_vect; /* Address Vector */ 562 uint16_t cep_pkey_ix; /* P_Key Index */ 563 uint8_t cep_hca_port_num; /* Port number for connected */ 564 /* channels. A value of 0 */ 565 /* indicates an invalid path */ 566 ib_time_t cep_cm_opaque1; 567 } ibt_cep_path_t; 568 569 /* 570 * Channel Migration State. 571 */ 572 typedef enum ibt_cep_cmstate_e { 573 IBT_STATE_NOT_SUPPORTED = 0, 574 IBT_STATE_MIGRATED = 1, 575 IBT_STATE_REARMED = 2, 576 IBT_STATE_ARMED = 3 577 } ibt_cep_cmstate_t; 578 579 /* 580 * Transport service type 581 * 582 * NOTE: this was converted from an enum to a uint8_t to save space. 583 */ 584 typedef uint8_t ibt_tran_srv_t; 585 586 #define IBT_RC_SRV 0 587 #define IBT_UC_SRV 1 588 #define IBT_RD_SRV 2 589 #define IBT_UD_SRV 3 590 #define IBT_RAWIP_SRV 4 591 #define IBT_RAWETHER_SRV 5 592 593 /* 594 * Channel (QP/EEC) state definitions. 595 */ 596 typedef enum ibt_cep_state_e { 597 IBT_STATE_RESET = 0, /* Reset */ 598 IBT_STATE_INIT, /* Initialized */ 599 IBT_STATE_RTR, /* Ready to Receive */ 600 IBT_STATE_RTS, /* Ready to Send */ 601 IBT_STATE_SQD, /* Send Queue Drained */ 602 IBT_STATE_SQE, /* Send Queue Error */ 603 IBT_STATE_ERROR, /* Error */ 604 IBT_STATE_SQDRAIN, /* Send Queue Draining */ 605 IBT_STATE_NUM /* Number of states */ 606 } ibt_cep_state_t; 607 608 609 /* 610 * Channel Attribute flags. 611 */ 612 typedef enum ibt_attr_flags_e { 613 IBT_ALL_SIGNALED = 0, /* All sends signaled */ 614 IBT_WR_SIGNALED = 1, /* Signaled on a WR basis */ 615 IBT_FAST_REG_RES_LKEY = (1 << 1) 616 } ibt_attr_flags_t; 617 618 /* 619 * Channel End Point (CEP) Control Flags. 620 */ 621 typedef enum ibt_cep_flags_e { 622 IBT_CEP_NO_FLAGS = 0, /* Enable Nothing */ 623 IBT_CEP_RDMA_RD = (1 << 0), /* Enable incoming RDMA RD's */ 624 /* RC & RD only */ 625 IBT_CEP_RDMA_WR = (1 << 1), /* Enable incoming RDMA WR's */ 626 /* RC & RD only */ 627 IBT_CEP_ATOMIC = (1 << 2) /* Enable incoming Atomics, */ 628 /* RC & RD only */ 629 } ibt_cep_flags_t; 630 631 /* 632 * Channel Modify Flags 633 */ 634 typedef enum ibt_cep_modify_flags_e { 635 IBT_CEP_SET_NOTHING = 0, 636 IBT_CEP_SET_SQ_SIZE = (1 << 1), 637 IBT_CEP_SET_RQ_SIZE = (1 << 2), 638 639 IBT_CEP_SET_RDMA_R = (1 << 3), 640 IBT_CEP_SET_RDMA_W = (1 << 4), 641 IBT_CEP_SET_ATOMIC = (1 << 5), 642 643 IBT_CEP_SET_ALT_PATH = (1 << 6), /* Alternate Path */ 644 645 IBT_CEP_SET_ADDS_VECT = (1 << 7), 646 IBT_CEP_SET_PORT = (1 << 8), 647 IBT_CEP_SET_OPAQUE5 = (1 << 9), 648 IBT_CEP_SET_RETRY = (1 << 10), 649 IBT_CEP_SET_RNR_NAK_RETRY = (1 << 11), 650 IBT_CEP_SET_MIN_RNR_NAK = (1 << 12), 651 652 IBT_CEP_SET_QKEY = (1 << 13), 653 IBT_CEP_SET_RDMARA_OUT = (1 << 14), 654 IBT_CEP_SET_RDMARA_IN = (1 << 15), 655 656 IBT_CEP_SET_OPAQUE1 = (1 << 16), 657 IBT_CEP_SET_OPAQUE2 = (1 << 17), 658 IBT_CEP_SET_OPAQUE3 = (1 << 18), 659 IBT_CEP_SET_OPAQUE4 = (1 << 19), 660 IBT_CEP_SET_SQD_EVENT = (1 << 20), 661 IBT_CEP_SET_OPAQUE6 = (1 << 21), 662 IBT_CEP_SET_OPAQUE7 = (1 << 22), 663 IBT_CEP_SET_OPAQUE8 = (1 << 23) 664 } ibt_cep_modify_flags_t; 665 666 /* 667 * CQ notify types. 668 */ 669 typedef enum ibt_cq_notify_flags_e { 670 IBT_NEXT_COMPLETION = 1, 671 IBT_NEXT_SOLICITED = 2 672 } ibt_cq_notify_flags_t; 673 674 /* 675 * CQ types shared across TI and CI. 676 */ 677 typedef enum ibt_cq_flags_e { 678 IBT_CQ_NO_FLAGS = 0, 679 IBT_CQ_HANDLER_IN_THREAD = 1 << 0, /* A thread calls the */ 680 /* CQ handler */ 681 IBT_CQ_USER_MAP = 1 << 1, 682 IBT_CQ_DEFER_ALLOC = 1 << 2 683 } ibt_cq_flags_t; 684 685 /* 686 * CQ types shared across TI and CI. 687 */ 688 typedef enum ibt_cq_sched_flags_e { 689 IBT_CQS_NO_FLAGS = 0, 690 IBT_CQS_WARM_CACHE = 1 << 0, /* run on same CPU */ 691 IBT_CQS_AFFINITY = 1 << 1, 692 IBT_CQS_SCHED_GROUP = 1 << 2, 693 IBT_CQS_USER_MAP = 1 << 3, 694 IBT_CQS_DEFER_ALLOC = 1 << 4 695 } ibt_cq_sched_flags_t; 696 697 /* 698 * Attributes when creating a Completion Queue. 699 * 700 * Note: 701 * The IBT_CQ_HANDLER_IN_THREAD cq_flags bit should be ignored by the CI. 702 */ 703 typedef struct ibt_cq_attr_s { 704 uint_t cq_size; 705 ibt_sched_hdl_t cq_sched; /* 0 = no hint, */ 706 /* other = cq_sched value */ 707 ibt_cq_flags_t cq_flags; 708 } ibt_cq_attr_t; 709 710 /* 711 * Memory Management 712 */ 713 714 /* Memory management flags */ 715 typedef enum ibt_mr_flags_e { 716 IBT_MR_SLEEP = 0, 717 IBT_MR_NOSLEEP = (1 << 1), 718 IBT_MR_NONCOHERENT = (1 << 2), 719 IBT_MR_PHYS_IOVA = (1 << 3), /* ibt_(re)register_buf */ 720 721 /* Access control flags */ 722 IBT_MR_ENABLE_WINDOW_BIND = (1 << 4), 723 IBT_MR_ENABLE_LOCAL_WRITE = (1 << 5), 724 IBT_MR_ENABLE_REMOTE_READ = (1 << 6), 725 IBT_MR_ENABLE_REMOTE_WRITE = (1 << 7), 726 IBT_MR_ENABLE_REMOTE_ATOMIC = (1 << 8), 727 728 /* Reregister flags */ 729 IBT_MR_CHANGE_TRANSLATION = (1 << 9), 730 IBT_MR_CHANGE_ACCESS = (1 << 10), 731 IBT_MR_CHANGE_PD = (1 << 11), 732 733 /* Additional registration flags */ 734 IBT_MR_ZBVA = (1 << 12), 735 736 /* Additional physical registration flags */ 737 IBT_MR_CONSUMER_KEY = (1 << 13) /* Consumer owns key */ 738 /* portion of keys */ 739 } ibt_mr_flags_t; 740 741 742 /* Memory Region attribute flags */ 743 typedef enum ibt_mr_attr_flags_e { 744 /* Access control flags */ 745 IBT_MR_WINDOW_BIND = (1 << 0), 746 IBT_MR_LOCAL_WRITE = (1 << 1), 747 IBT_MR_REMOTE_READ = (1 << 2), 748 IBT_MR_REMOTE_WRITE = (1 << 3), 749 IBT_MR_REMOTE_ATOMIC = (1 << 4), 750 IBT_MR_ZERO_BASED_VA = (1 << 5), 751 IBT_MR_CONSUMER_OWNED_KEY = (1 << 6), 752 IBT_MR_SHARED = (1 << 7), 753 IBT_MR_FMR = (1 << 8) 754 } ibt_mr_attr_flags_t; 755 756 /* Memory region physical descriptor. */ 757 typedef struct ibt_phys_buf_s { 758 union { 759 uint64_t _p_ll; /* 64 bit DMA address */ 760 uint32_t _p_la[2]; /* 2 x 32 bit address */ 761 } _phys_buf; 762 size_t p_size; 763 } ibt_phys_buf_t; 764 765 #define p_laddr _phys_buf._p_ll 766 #ifdef _LONG_LONG_HTOL 767 #define p_notused _phys_buf._p_la[0] 768 #define p_addr _phys_buf._p_la[1] 769 #else 770 #define p_addr _phys_buf._p_la[0] 771 #define p_notused _phys_buf._p_la[1] 772 #endif 773 774 775 /* Memory region descriptor. */ 776 typedef struct ibt_mr_desc_s { 777 ib_vaddr_t md_vaddr; /* IB virtual adds of memory */ 778 ibt_lkey_t md_lkey; 779 ibt_rkey_t md_rkey; 780 boolean_t md_sync_required; 781 } ibt_mr_desc_t; 782 783 /* Physical Memory region descriptor. */ 784 typedef struct ibt_pmr_desc_s { 785 ib_vaddr_t pmd_iova; /* Returned I/O Virtual Address */ 786 ibt_lkey_t pmd_lkey; 787 ibt_rkey_t pmd_rkey; 788 uint_t pmd_phys_buf_list_sz; /* Allocated Phys buf sz */ 789 boolean_t pmd_sync_required; 790 } ibt_pmr_desc_t; 791 792 /* Memory region protection bounds. */ 793 typedef struct ibt_mr_prot_bounds_s { 794 ib_vaddr_t pb_addr; /* Beginning address */ 795 size_t pb_len; /* Length of protected region */ 796 } ibt_mr_prot_bounds_t; 797 798 /* Memory Region (Re)Register attributes */ 799 typedef struct ibt_mr_attr_s { 800 ib_vaddr_t mr_vaddr; /* Virtual address to register */ 801 ib_memlen_t mr_len; /* Length of region to register */ 802 struct as *mr_as; /* A pointer to an address space */ 803 /* structure. This parameter should */ 804 /* be set to NULL, which implies */ 805 /* kernel address space. */ 806 ibt_mr_flags_t mr_flags; 807 } ibt_mr_attr_t; 808 809 /* Physical Memory Region (Re)Register */ 810 typedef struct ibt_pmr_attr_s { 811 ib_vaddr_t pmr_iova; /* I/O virtual address requested by */ 812 /* client for the first byte of the */ 813 /* region */ 814 ib_memlen_t pmr_len; /* Length of region to register */ 815 ib_memlen_t pmr_offset; /* Offset of the regions starting */ 816 /* IOVA within the 1st physical */ 817 /* buffer */ 818 ibt_mr_flags_t pmr_flags; 819 ibt_lkey_t pmr_lkey; /* Reregister only */ 820 ibt_rkey_t pmr_rkey; /* Reregister only */ 821 uint8_t pmr_key; /* Key to use on new Lkey & Rkey */ 822 uint_t pmr_num_buf; /* Num of entries in the pmr_buf_list */ 823 size_t pmr_buf_sz; 824 ibt_phys_buf_t *pmr_buf_list; /* List of physical buffers accessed */ 825 /* as an array */ 826 ibt_ma_hdl_t pmr_ma; /* Memory handle used to obtain the */ 827 /* pmr_buf_list */ 828 } ibt_pmr_attr_t; 829 830 831 /* 832 * Memory Region (Re)Register attributes - used by ibt_register_shared_mr(), 833 * ibt_register_buf() and ibt_reregister_buf(). 834 */ 835 typedef struct ibt_smr_attr_s { 836 ib_vaddr_t mr_vaddr; 837 ibt_mr_flags_t mr_flags; 838 uint8_t mr_key; /* Only for physical */ 839 /* ibt_(Re)register_buf() */ 840 ibt_lkey_t mr_lkey; /* Only for physical */ 841 ibt_rkey_t mr_rkey; /* ibt_Reregister_buf() */ 842 } ibt_smr_attr_t; 843 844 /* 845 * key states. 846 */ 847 typedef enum ibt_key_state_e { 848 IBT_KEY_INVALID = 0, 849 IBT_KEY_FREE, 850 IBT_KEY_VALID 851 } ibt_key_state_t; 852 853 /* Memory region query attributes */ 854 typedef struct ibt_mr_query_attr_s { 855 ibt_lkey_t mr_lkey; 856 ibt_rkey_t mr_rkey; 857 ibt_mr_prot_bounds_t mr_lbounds; /* Actual local CI protection */ 858 /* bounds */ 859 ibt_mr_prot_bounds_t mr_rbounds; /* Actual remote CI */ 860 /* protection bounds */ 861 ibt_mr_attr_flags_t mr_attr_flags; /* Access rights etc. */ 862 ibt_pd_hdl_t mr_pd; /* Protection domain */ 863 boolean_t mr_sync_required; 864 ibt_key_state_t mr_lkey_state; 865 uint_t mr_phys_buf_list_sz; 866 } ibt_mr_query_attr_t; 867 868 /* Memory window query attributes */ 869 typedef struct ibt_mw_query_attr_s { 870 ibt_pd_hdl_t mw_pd; 871 ibt_mem_win_type_t mw_type; 872 ibt_rkey_t mw_rkey; 873 ibt_key_state_t mw_state; 874 } ibt_mw_query_attr_t; 875 876 877 /* Memory Region Sync Flags. */ 878 #define IBT_SYNC_READ 0x1 /* Make memory changes visible to incoming */ 879 /* RDMA reads */ 880 881 #define IBT_SYNC_WRITE 0x2 /* Make the affects of an incoming RDMA write */ 882 /* visible to the consumer */ 883 884 /* Memory region sync args */ 885 typedef struct ibt_mr_sync_s { 886 ibt_mr_hdl_t ms_handle; 887 ib_vaddr_t ms_vaddr; 888 ib_memlen_t ms_len; 889 uint32_t ms_flags; /* IBT_SYNC_READ or IBT_SYNC_WRITE */ 890 } ibt_mr_sync_t; 891 892 /* 893 * Flags for Virtual Address to HCA Physical Address translation. 894 */ 895 typedef enum ibt_va_flags_e { 896 IBT_VA_SLEEP = 0, 897 IBT_VA_NOSLEEP = (1 << 0), 898 IBT_VA_NONCOHERENT = (1 << 1), 899 IBT_VA_FMR = (1 << 2), 900 IBT_VA_BLOCK_MODE = (1 << 3), 901 IBT_VA_BUF = (1 << 4) 902 } ibt_va_flags_t; 903 904 905 /* Address Translation parameters */ 906 typedef struct ibt_va_attr_s { 907 ib_vaddr_t va_vaddr; /* Virtual address to register */ 908 ib_memlen_t va_len; /* Length of region to register */ 909 struct as *va_as; /* A pointer to an address space */ 910 /* structure. */ 911 size_t va_phys_buf_min; 912 size_t va_phys_buf_max; 913 ibt_va_flags_t va_flags; 914 struct buf *va_buf; 915 } ibt_va_attr_t; 916 917 918 /* 919 * Fast Memory Registration (FMR) support. 920 */ 921 922 /* FMR flush function handler. */ 923 typedef void (*ibt_fmr_flush_handler_t)(ibt_fmr_pool_hdl_t fmr_pool, 924 void *fmr_func_arg); 925 926 /* FMR Pool create attributes. */ 927 typedef struct ibt_fmr_pool_attr_s { 928 uint_t fmr_max_pages_per_fmr; 929 uint_t fmr_pool_size; 930 uint_t fmr_dirty_watermark; 931 size_t fmr_page_sz; 932 boolean_t fmr_cache; 933 ibt_mr_flags_t fmr_flags; 934 ibt_fmr_flush_handler_t fmr_func_hdlr; 935 void *fmr_func_arg; 936 } ibt_fmr_pool_attr_t; 937 938 939 /* 940 * WORK REQUEST AND WORK REQUEST COMPLETION DEFINITIONS. 941 */ 942 943 /* 944 * Work Request and Work Request Completion types - These types are used 945 * to indicate the type of work requests posted to a work queue 946 * or the type of completion received. Immediate Data is indicated via 947 * ibt_wr_flags_t or ibt_wc_flags_t. 948 * 949 * IBT_WRC_RECV and IBT_WRC_RECV_RDMAWI are only used as opcodes in the 950 * work completions. 951 * 952 * NOTE: this was converted from an enum to a uint8_t to save space. 953 */ 954 typedef uint8_t ibt_wrc_opcode_t; 955 956 #define IBT_WRC_SEND 1 /* Send */ 957 #define IBT_WRC_RDMAR 2 /* RDMA Read */ 958 #define IBT_WRC_RDMAW 3 /* RDMA Write */ 959 #define IBT_WRC_CSWAP 4 /* Compare & Swap Atomic */ 960 #define IBT_WRC_FADD 5 /* Fetch & Add Atomic */ 961 #define IBT_WRC_BIND 6 /* Bind Memory Window */ 962 #define IBT_WRC_RECV 7 /* Receive */ 963 #define IBT_WRC_RECV_RDMAWI 8 /* Received RDMA Write w/ Immediate */ 964 #define IBT_WRC_FAST_REG_PMR 9 /* Fast Register Physical mem region */ 965 #define IBT_WRC_LOCAL_INVALIDATE 10 966 967 968 /* 969 * Work Request Completion flags - These flags indicate what type 970 * of data is present in the Work Request Completion structure 971 */ 972 typedef uint8_t ibt_wc_flags_t; 973 974 #define IBT_WC_NO_FLAGS 0 975 #define IBT_WC_GRH_PRESENT (1 << 0) 976 #define IBT_WC_IMMED_DATA_PRESENT (1 << 1) 977 #define IBT_WC_RKEY_INVALIDATED (1 << 2) 978 #define IBT_WC_CKSUM_OK (1 << 3) 979 980 981 /* 982 * Work Request Completion - This structure encapsulates the information 983 * necessary to define a work request completion. 984 */ 985 typedef struct ibt_wc_s { 986 ibt_wrid_t wc_id; /* Work Request Id */ 987 uint64_t wc_fma_ena; /* fault management err data */ 988 ib_msglen_t wc_bytes_xfer; /* Number of Bytes */ 989 /* Transferred */ 990 ibt_wc_flags_t wc_flags; /* WR Completion Flags */ 991 ibt_wrc_opcode_t wc_type; /* Operation Type */ 992 uint16_t wc_cksum; /* payload checksum */ 993 ibt_immed_t wc_immed_data; /* Immediate Data */ 994 uint32_t wc_freed_rc; /* Freed Resource Count */ 995 ibt_wc_status_t wc_status; /* Completion Status */ 996 uint8_t wc_sl:4; /* Remote SL */ 997 uint16_t wc_ethertype; /* Ethertype Field - RE */ 998 ib_lid_t wc_opaque1; 999 uint16_t wc_opaque2; 1000 ib_qpn_t wc_qpn; /* Source QPN Datagram only */ 1001 ib_eecn_t wc_opaque3; 1002 ib_qpn_t wc_local_qpn; 1003 ibt_rkey_t wc_rkey; 1004 ib_path_bits_t wc_opaque4; 1005 } ibt_wc_t; 1006 1007 1008 /* 1009 * WR Flags. Common for both RC and UD 1010 * 1011 * NOTE: this was converted from an enum to a uint8_t to save space. 1012 */ 1013 typedef uint8_t ibt_wr_flags_t; 1014 1015 #define IBT_WR_NO_FLAGS 0 1016 #define IBT_WR_SEND_IMMED (1 << 0) /* Immediate Data Indicator */ 1017 #define IBT_WR_SEND_SIGNAL (1 << 1) /* Signaled, if set */ 1018 #define IBT_WR_SEND_FENCE (1 << 2) /* Fence Indicator */ 1019 #define IBT_WR_SEND_SOLICIT (1 << 3) /* Solicited Event Indicator */ 1020 #define IBT_WR_SEND_REMOTE_INVAL (1 << 4) /* Remote Invalidate */ 1021 #define IBT_WR_SEND_CKSUM (1 << 5) /* Checksum offload Indicator */ 1022 1023 /* 1024 * Access control flags for Bind Memory Window operation, 1025 * applicable for RC/UC/RD only. 1026 * 1027 * If IBT_WR_BIND_WRITE or IBT_WR_BIND_ATOMIC is desired then 1028 * it is required that Memory Region should have Local Write Access. 1029 */ 1030 typedef enum ibt_bind_flags_e { 1031 IBT_WR_BIND_READ = (1 << 0), /* enable remote read */ 1032 IBT_WR_BIND_WRITE = (1 << 1), /* enable remote write */ 1033 IBT_WR_BIND_ATOMIC = (1 << 2), /* enable remote atomics */ 1034 IBT_WR_BIND_ZBVA = (1 << 3) /* Zero Based Virtual Address */ 1035 } ibt_bind_flags_t; 1036 1037 /* 1038 * Data Segment for scatter-gather list 1039 * 1040 * SGL consists of an array of data segments and the length of the SGL. 1041 */ 1042 typedef struct ibt_wr_ds_s { 1043 ib_vaddr_t ds_va; /* Virtual Address */ 1044 ibt_lkey_t ds_key; /* L_Key */ 1045 ib_msglen_t ds_len; /* Length of DS */ 1046 } ibt_wr_ds_t; 1047 1048 /* 1049 * Bind Memory Window WR 1050 * 1051 * WR ID from ibt_send_wr_t applies here too, SWG_0038 errata. 1052 */ 1053 typedef struct ibt_wr_bind_s { 1054 ibt_bind_flags_t bind_flags; 1055 ibt_rkey_t bind_rkey; /* Mem Window's R_key */ 1056 ibt_lkey_t bind_lkey; /* Mem Region's L_Key */ 1057 ibt_rkey_t bind_rkey_out; /* OUT: new R_Key */ 1058 ibt_mr_hdl_t bind_ibt_mr_hdl; /* Mem Region handle */ 1059 ibt_mw_hdl_t bind_ibt_mw_hdl; /* Mem Window handle */ 1060 ib_vaddr_t bind_va; /* Virtual Address */ 1061 ib_memlen_t bind_len; /* Length of Window */ 1062 } ibt_wr_bind_t; 1063 1064 /* 1065 * Atomic WR 1066 * 1067 * Operation type (compare & swap or fetch & add) in ibt_wrc_opcode_t. 1068 * 1069 * A copy of the original contents of the remote memory will be stored 1070 * in the local data segment described by wr_sgl within ibt_send_wr_t, 1071 * and wr_nds should be set to 1. 1072 * 1073 * Atomic operation operands: 1074 * Compare & Swap Operation: 1075 * atom_arg1 - Compare Operand 1076 * atom_arg2 - Swap Operand 1077 * 1078 * Fetch & Add Operation: 1079 * atom_arg1 - Add Operand 1080 * atom_arg2 - ignored 1081 */ 1082 typedef struct ibt_wr_atomic_s { 1083 ib_vaddr_t atom_raddr; /* Remote address. */ 1084 ibt_atom_arg_t atom_arg1; /* operand #1 */ 1085 ibt_atom_arg_t atom_arg2; /* operand #2 */ 1086 ibt_rkey_t atom_rkey; /* R_Key. */ 1087 } ibt_wr_atomic_t; 1088 1089 /* 1090 * RDMA WR 1091 * Immediate Data indicator in ibt_wr_flags_t. 1092 */ 1093 typedef struct ibt_wr_rdma_s { 1094 ib_vaddr_t rdma_raddr; /* Remote address. */ 1095 ibt_rkey_t rdma_rkey; /* R_Key. */ 1096 ibt_immed_t rdma_immed; /* Immediate Data */ 1097 } ibt_wr_rdma_t; 1098 1099 /* 1100 * Fast Register Physical Memory Region Work Request. 1101 */ 1102 typedef struct ibt_wr_reg_pmr_s { 1103 ib_vaddr_t pmr_iova; /* I/O virtual address requested by */ 1104 /* client for the first byte of the */ 1105 /* region */ 1106 ib_memlen_t pmr_len; /* Length of region to register */ 1107 ib_memlen_t pmr_offset; /* Offset of the regions starting */ 1108 /* IOVA within the 1st physical */ 1109 /* buffer */ 1110 ibt_mr_hdl_t pmr_mr_hdl; 1111 ibt_phys_buf_t *pmr_buf_list; /* List of physical buffers accessed */ 1112 /* as an array */ 1113 uint_t pmr_num_buf; /* Num of entries in the pmr_buf_list */ 1114 ibt_lkey_t pmr_lkey; 1115 ibt_rkey_t pmr_rkey; 1116 ibt_mr_flags_t pmr_flags; 1117 uint8_t pmr_key; /* Key to use on new Lkey & Rkey */ 1118 } ibt_wr_reg_pmr_t; 1119 1120 /* 1121 * Local Invalidate. 1122 */ 1123 typedef struct ibt_wr_li_s { 1124 ibt_mr_hdl_t li_mr_hdl; /* Null for MW invalidates */ 1125 ibt_mw_hdl_t li_mw_hdl; /* Null for MR invalidates */ 1126 ibt_lkey_t li_lkey; /* Ignore for MW invalidates */ 1127 ibt_rkey_t li_rkey; 1128 } ibt_wr_li_t; 1129 1130 /* 1131 * Reserved For Future Use. 1132 * Raw IPv6 Send WR 1133 */ 1134 typedef struct ibt_wr_ripv6_s { 1135 ib_lid_t rip_dlid; /* DLID */ 1136 ib_path_bits_t rip_slid_bits; /* SLID path bits, SWG_0033 errata */ 1137 uint8_t rip_sl:4; /* SL */ 1138 ibt_srate_t rip_rate; /* Max Static Rate, SWG_0007 errata */ 1139 } ibt_wr_ripv6_t; 1140 1141 /* 1142 * Reserved For Future Use. 1143 * Raw Ethertype Send WR 1144 */ 1145 typedef struct ibt_wr_reth_s { 1146 ib_ethertype_t reth_type; /* Ethertype */ 1147 ib_lid_t reth_dlid; /* DLID */ 1148 ib_path_bits_t reth_slid_bits; /* SLID path bits, SWG_0033 errata */ 1149 uint8_t reth_sl:4; /* SL */ 1150 ibt_srate_t reth_rate; /* Max Static Rate, SWG_0007 errata */ 1151 } ibt_wr_reth_t; 1152 1153 /* 1154 * Reserved For future Use. 1155 * RD Send WR, Operation type in ibt_wrc_opcode_t. 1156 */ 1157 typedef struct ibt_wr_rd_s { 1158 ibt_rd_dest_hdl_t rdwr_dest_hdl; 1159 union { 1160 ibt_immed_t send_immed; /* IBT_WRC_SEND */ 1161 ibt_wr_rdma_t rdma; /* IBT_WRC_RDMAR */ 1162 /* IBT_WRC_RDMAW */ 1163 ibt_wr_li_t *li; /* IBT_WRC_LOCAL_INVALIDATE */ 1164 ibt_wr_atomic_t *atomic; /* IBT_WRC_FADD */ 1165 /* IBT_WRC_CSWAP */ 1166 ibt_wr_bind_t *bind; /* IBT_WRC_BIND */ 1167 ibt_wr_reg_pmr_t *reg_pmr; /* IBT_WRC_FAST_REG_PMR */ 1168 } rdwr; 1169 } ibt_wr_rd_t; 1170 1171 /* 1172 * Reserved For Future Use. 1173 * UC Send WR, Operation type in ibt_wrc_opcode_t, the only valid 1174 * ones are: 1175 * IBT_WRC_SEND 1176 * IBT_WRC_RDMAW 1177 * IBT_WRC_BIND 1178 */ 1179 typedef struct ibt_wr_uc_s { 1180 union { 1181 ibt_immed_t send_immed; /* IBT_WRC_SEND */ 1182 ibt_wr_rdma_t rdma; /* IBT_WRC_RDMAW */ 1183 ibt_wr_li_t *li; /* IBT_WRC_LOCAL_INVALIDATE */ 1184 ibt_wr_bind_t *bind; /* IBT_WRC_BIND */ 1185 ibt_wr_reg_pmr_t *reg_pmr; /* IBT_WRC_FAST_REG_PMR */ 1186 } ucwr; 1187 } ibt_wr_uc_t; 1188 1189 /* 1190 * RC Send WR, Operation type in ibt_wrc_opcode_t. 1191 */ 1192 typedef struct ibt_wr_rc_s { 1193 union { 1194 ibt_immed_t send_immed; /* IBT_WRC_SEND w/ immediate */ 1195 ibt_rkey_t send_inval; /* IBT_WRC_SEND w/ invalidate */ 1196 ibt_wr_rdma_t rdma; /* IBT_WRC_RDMAR */ 1197 /* IBT_WRC_RDMAW */ 1198 ibt_wr_li_t *li; /* IBT_WRC_LOCAL_INVALIDATE */ 1199 ibt_wr_atomic_t *atomic; /* IBT_WRC_CSWAP */ 1200 /* IBT_WRC_FADD */ 1201 ibt_wr_bind_t *bind; /* IBT_WRC_BIND */ 1202 ibt_wr_reg_pmr_t *reg_pmr; /* IBT_WRC_FAST_REG_PMR */ 1203 } rcwr; 1204 } ibt_wr_rc_t; 1205 1206 /* 1207 * UD Send WR, the only valid Operation is IBT_WRC_SEND. 1208 */ 1209 typedef struct ibt_wr_ud_s { 1210 ibt_immed_t udwr_immed; 1211 ibt_ud_dest_hdl_t udwr_dest; 1212 } ibt_wr_ud_t; 1213 1214 /* 1215 * Send Work Request (WR) attributes structure. 1216 * 1217 * Operation type in ibt_wrc_opcode_t. 1218 * Immediate Data indicator in ibt_wr_flags_t. 1219 */ 1220 typedef struct ibt_send_wr_s { 1221 ibt_wrid_t wr_id; /* WR ID */ 1222 ibt_wr_flags_t wr_flags; /* Work Request Flags. */ 1223 ibt_tran_srv_t wr_trans; /* Transport Type. */ 1224 ibt_wrc_opcode_t wr_opcode; /* Operation Type. */ 1225 uint8_t wr_rsvd; /* maybe later */ 1226 uint32_t wr_nds; /* Number of data segments */ 1227 /* pointed to by wr_sgl */ 1228 ibt_wr_ds_t *wr_sgl; /* SGL */ 1229 union { 1230 ibt_wr_ud_t ud; 1231 ibt_wr_rc_t rc; 1232 ibt_wr_rd_t rd; /* Reserved For Future Use */ 1233 ibt_wr_uc_t uc; /* Reserved For Future Use */ 1234 ibt_wr_reth_t reth; /* Reserved For Future Use */ 1235 ibt_wr_ripv6_t ripv6; /* Reserved For Future Use */ 1236 } wr; /* operation specific */ 1237 } ibt_send_wr_t; 1238 1239 /* 1240 * Receive Work Request (WR) attributes structure. 1241 */ 1242 typedef struct ibt_recv_wr_s { 1243 ibt_wrid_t wr_id; /* WR ID */ 1244 uint32_t wr_nds; /* number of data segments */ 1245 /* pointed to by wr_sgl */ 1246 ibt_wr_ds_t *wr_sgl; /* SGL */ 1247 } ibt_recv_wr_t; 1248 1249 1250 /* 1251 * Asynchronous Events and Errors. 1252 * 1253 * The following codes are not used in calls to ibc_async_handler, but 1254 * are used by IBTL to inform IBT clients of a significant event. 1255 * 1256 * IBT_HCA_ATTACH_EVENT - New HCA available. 1257 * IBT_HCA_DETACH_EVENT - HCA is requesting not to be used. 1258 * 1259 * ERRORs on a channel indicate that the channel has entered error state. 1260 * EVENTs on a channel indicate that the channel has not changed state. 1261 * 1262 */ 1263 typedef enum ibt_async_code_e { 1264 IBT_EVENT_PATH_MIGRATED = 0x000001, 1265 IBT_EVENT_SQD = 0x000002, 1266 IBT_EVENT_COM_EST = 0x000004, 1267 IBT_ERROR_CATASTROPHIC_CHAN = 0x000008, 1268 IBT_ERROR_INVALID_REQUEST_CHAN = 0x000010, 1269 IBT_ERROR_ACCESS_VIOLATION_CHAN = 0x000020, 1270 IBT_ERROR_PATH_MIGRATE_REQ = 0x000040, 1271 1272 IBT_ERROR_CQ = 0x000080, 1273 1274 IBT_EVENT_PORT_UP = 0x000100, 1275 IBT_ERROR_PORT_DOWN = 0x000200, 1276 IBT_ERROR_LOCAL_CATASTROPHIC = 0x000400, 1277 1278 IBT_HCA_ATTACH_EVENT = 0x000800, 1279 IBT_HCA_DETACH_EVENT = 0x001000, 1280 IBT_ASYNC_OPAQUE1 = 0x002000, 1281 IBT_ASYNC_OPAQUE2 = 0x004000, 1282 IBT_ASYNC_OPAQUE3 = 0x008000, 1283 IBT_ASYNC_OPAQUE4 = 0x010000, 1284 IBT_EVENT_LIMIT_REACHED_SRQ = 0x020000, 1285 IBT_EVENT_EMPTY_CHAN = 0x040000, 1286 IBT_ERROR_CATASTROPHIC_SRQ = 0x080000 1287 } ibt_async_code_t; 1288 1289 1290 /* 1291 * ibt_ci_data_in() and ibt_ci_data_out() flags. 1292 */ 1293 typedef enum ibt_ci_data_flags_e { 1294 IBT_CI_NO_FLAGS = 0, 1295 IBT_CI_COMPLETE_ALLOC = (1 << 0) 1296 } ibt_ci_data_flags_t; 1297 1298 /* 1299 * Used by ibt_ci_data_in() and ibt_ci_data_out() identifies the type of handle 1300 * mapping data is being obtained for. 1301 */ 1302 typedef enum ibt_object_type_e { 1303 IBT_HDL_HCA = 1, 1304 IBT_HDL_CHANNEL, 1305 IBT_HDL_CQ, 1306 IBT_HDL_PD, 1307 IBT_HDL_MR, 1308 IBT_HDL_MW, 1309 IBT_HDL_UD_DEST, 1310 IBT_HDL_SCHED, 1311 IBT_HDL_OPAQUE1, 1312 IBT_HDL_OPAQUE2, 1313 IBT_HDL_SRQ 1314 } ibt_object_type_t; 1315 1316 /* 1317 * Memory error handler data structures; code, and payload data. 1318 */ 1319 typedef enum ibt_mem_code_s { 1320 IBT_MEM_AREA = 0x1, 1321 IBT_MEM_REGION = 0x2 1322 } ibt_mem_code_t; 1323 1324 typedef struct ibt_mem_data_s { 1325 uint64_t ev_fma_ena; /* FMA Error data */ 1326 ibt_mr_hdl_t ev_mr_hdl; /* MR handle */ 1327 ibt_ma_hdl_t ev_ma_hdl; /* MA handle */ 1328 } ibt_mem_data_t; 1329 1330 /* 1331 * Special case failure type. 1332 */ 1333 typedef enum ibt_failure_type_e { 1334 IBT_FAILURE_STANDARD = 0, 1335 IBT_FAILURE_CI, 1336 IBT_FAILURE_IBMF, 1337 IBT_FAILURE_IBTL, 1338 IBT_FAILURE_IBCM, 1339 IBT_FAILURE_IBDM, 1340 IBT_FAILURE_IBSM 1341 } ibt_failure_type_t; 1342 1343 #ifdef __cplusplus 1344 } 1345 #endif 1346 1347 #endif /* _SYS_IB_IBTL_IBTL_TYPES_H */ 1348