1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_IB_IBTL_IBTL_TYPES_H 28 #define _SYS_IB_IBTL_IBTL_TYPES_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 /* 33 * ibtl_types.h 34 * 35 * All common IBTL defined types. These are common data types 36 * that are shared by the IBTI and IBCI interfaces, it is only included 37 * by ibti.h and ibci.h 38 */ 39 #include <sys/ddi.h> 40 #include <sys/sunddi.h> 41 #include <sys/ib/ib_types.h> 42 #include <sys/ib/ibtl/ibtl_status.h> 43 44 #ifdef __cplusplus 45 extern "C" { 46 #endif 47 48 /* 49 * Define Internal IBTL handles 50 */ 51 typedef struct ibtl_clnt_s *ibt_clnt_hdl_t; /* ibt_attach() */ 52 typedef struct ibtl_hca_s *ibt_hca_hdl_t; /* ibt_open_hca() */ 53 typedef struct ibtl_channel_s *ibt_channel_hdl_t; /* alloc_rc|ud_channel() */ 54 typedef struct ibtl_srq_s *ibt_srq_hdl_t; /* ibt_alloc_srq() */ 55 typedef struct ibtl_cq_s *ibt_cq_hdl_t; /* ibt_alloc_cq() */ 56 typedef struct ibcm_svc_info_s *ibt_srv_hdl_t; /* ibt_register_service() */ 57 typedef struct ibcm_svc_bind_s *ibt_sbind_hdl_t; /* ibt_bind_service() */ 58 59 typedef struct ibc_fmr_pool_s *ibt_fmr_pool_hdl_t; /* ibt_create_fmr_pool() */ 60 typedef struct ibc_ma_s *ibt_ma_hdl_t; /* ibt_map_mem_area() */ 61 typedef struct ibc_pd_s *ibt_pd_hdl_t; /* ibt_alloc_pd() */ 62 typedef struct ibc_sched_s *ibt_sched_hdl_t; /* ibt_alloc_cq_sched() */ 63 typedef struct ibc_mr_s *ibt_mr_hdl_t; /* ibt_register_mr() */ 64 typedef struct ibc_mw_s *ibt_mw_hdl_t; /* ibt_alloc_mw() */ 65 typedef struct ibt_ud_dest_s *ibt_ud_dest_hdl_t; /* UD dest handle */ 66 typedef struct ibc_ah_s *ibt_ah_hdl_t; /* ibt_alloc_ah() */ 67 typedef struct ibtl_eec_s *ibt_eec_hdl_t; 68 typedef struct ibt_rd_dest_s *ibt_rd_dest_hdl_t; /* Reserved for */ 69 /* Future use */ 70 71 /* 72 * Some General Types. 73 */ 74 typedef uint32_t ibt_lkey_t; /* L_Key */ 75 typedef uint32_t ibt_rkey_t; /* R_Key */ 76 typedef uint64_t ibt_wrid_t; /* Client assigned WR ID */ 77 typedef uint32_t ibt_immed_t; /* WR Immediate Data */ 78 typedef uint64_t ibt_atom_arg_t; /* WR Atomic Operation arg */ 79 typedef uint_t ibt_cq_handler_id_t; /* Event handler ID */ 80 81 /* 82 * IBT selector type, used when looking up/requesting either an 83 * MTU, Pkt lifetime, or Static rate. 84 * The interpretation of IBT_BEST depends on the attribute being selected. 85 */ 86 typedef enum ibt_selector_e { 87 IBT_GT = 0, /* Greater than */ 88 IBT_LT = 1, /* Less than */ 89 IBT_EQU = 2, /* Equal to */ 90 IBT_BEST = 3 /* Best */ 91 } ibt_selector_t; 92 93 94 /* 95 * Static rate definitions. 96 */ 97 typedef enum ibt_srate_e { 98 IBT_SRATE_NOT_SPECIFIED = 0, 99 IBT_SRATE_1X = 2, 100 IBT_SRATE_4X = 3, 101 IBT_SRATE_12X = 4 102 } ibt_srate_t; 103 104 /* 105 * Static rate request type. 106 */ 107 typedef struct ibt_srate_req_s { 108 ibt_srate_t r_srate; /* Requested srate */ 109 ibt_selector_t r_selector; /* Qualifier for r_srate */ 110 } ibt_srate_req_t; 111 112 /* 113 * Packet Life Time Request Type. 114 */ 115 typedef struct ibt_pkt_lt_req_s { 116 clock_t p_pkt_lt; /* Requested Packet Life Time */ 117 ibt_selector_t p_selector; /* Qualifier for p_pkt_lt */ 118 } ibt_pkt_lt_req_t; 119 120 /* 121 * Queue size struct. 122 */ 123 typedef struct ibt_queue_sizes_s { 124 uint_t qs_sq; /* SendQ size. */ 125 uint_t qs_rq; /* RecvQ size. */ 126 } ibt_queue_sizes_t; 127 128 /* 129 * Channel sizes struct, used by functions that allocate/query RC or UD 130 * channels. 131 */ 132 typedef struct ibt_chan_sizes_s { 133 uint_t cs_sq; /* SendQ size. */ 134 uint_t cs_rq; /* ReceiveQ size. */ 135 uint_t cs_sq_sgl; /* Max SGL elements in a SQ WR. */ 136 uint_t cs_rq_sgl; /* Max SGL elements in a RQ Wr. */ 137 } ibt_chan_sizes_t; 138 139 /* 140 * Shared Queue size struct. 141 */ 142 typedef struct ibt_srq_sizes_s { 143 uint_t srq_wr_sz; 144 uint_t srq_sgl_sz; 145 } ibt_srq_sizes_t; 146 147 /* 148 * SRQ Modify Flags 149 */ 150 typedef enum ibt_srq_modify_flags_e { 151 IBT_SRQ_SET_NOTHING = 0, 152 IBT_SRQ_SET_SIZE = (1 << 1), 153 IBT_SRQ_SET_LIMIT = (1 << 2) 154 } ibt_srq_modify_flags_t; 155 156 157 /* 158 * Execution flags, indicates if the function should block or not. 159 * Note: in some cases, e.g., a NULL rc_cm_handler, IBT_NONBLOCKING 160 * will not have an effect, and the thread will block. 161 * IBT_NOCALLBACKS is valid for ibt_close_rc_channel only. 162 */ 163 typedef enum ibt_execution_mode_e { 164 IBT_BLOCKING = 0, /* Block */ 165 IBT_NONBLOCKING = 1, /* Return as soon as possible */ 166 IBT_NOCALLBACKS = 2 /* cm_handler is not invoked after */ 167 /* ibt_close_rc_channel returns */ 168 } ibt_execution_mode_t; 169 170 /* 171 * Memory window alloc flags 172 */ 173 typedef enum ibt_mw_flags_e { 174 IBT_MW_SLEEP = 0, /* Can block */ 175 IBT_MW_NOSLEEP = (1 << 0), /* Can't block */ 176 IBT_MW_USER_MAP = (1 << 1), 177 IBT_MW_DEFER_ALLOC = (1 << 2), 178 IBT_MW_TYPE_1 = (1 << 3), 179 IBT_MW_TYPE_2 = (1 << 4) 180 } ibt_mw_flags_t; 181 182 /* 183 * PD alloc flags 184 */ 185 typedef enum ibt_pd_flags_e { 186 IBT_PD_NO_FLAGS = 0, 187 IBT_PD_USER_MAP = (1 << 0), 188 IBT_PD_DEFER_ALLOC = (1 << 1) 189 } ibt_pd_flags_t; 190 191 /* 192 * UD Dest alloc flags 193 */ 194 typedef enum ibt_ud_dest_flags_e { 195 IBT_UD_DEST_NO_FLAGS = 0, 196 IBT_UD_DEST_USER_MAP = (1 << 0), 197 IBT_UD_DEST_DEFER_ALLOC = (1 << 1) 198 } ibt_ud_dest_flags_t; 199 200 /* 201 * SRQ alloc flags 202 */ 203 typedef enum ibt_srq_flags_e { 204 IBT_SRQ_NO_FLAGS = 0, 205 IBT_SRQ_USER_MAP = (1 << 0), 206 IBT_SRQ_DEFER_ALLOC = (1 << 1) 207 } ibt_srq_flags_t; 208 209 /* 210 * ibt_alloc_lkey() alloc flags 211 */ 212 typedef enum ibt_lkey_flags_e { 213 IBT_KEY_NO_FLAGS = 0, 214 IBT_KEY_REMOTE = (1 << 0) 215 } ibt_lkey_flags_t; 216 217 /* 218 * RNR NAK retry counts. 219 */ 220 typedef enum ibt_rnr_retry_cnt_e { 221 IBT_RNR_NO_RETRY = 0x0, /* Don't retry, fail on first timeout */ 222 IBT_RNR_RETRY_1 = 0x1, /* Retry once */ 223 IBT_RNR_RETRY_2 = 0x2, /* Retry twice */ 224 IBT_RNR_RETRY_3 = 0x3, /* Retry three times */ 225 IBT_RNR_RETRY_4 = 0x4, /* Retry four times */ 226 IBT_RNR_RETRY_5 = 0x5, /* Retry five times */ 227 IBT_RNR_RETRY_6 = 0x6, /* Retry six times */ 228 IBT_RNR_INFINITE_RETRY = 0x7 /* Retry forever */ 229 } ibt_rnr_retry_cnt_t; 230 231 /* 232 * Valid values for RNR NAK timer fields, part of a channel's context. 233 */ 234 typedef enum ibt_rnr_nak_time_e { 235 IBT_RNR_NAK_655ms = 0x0, 236 IBT_RNR_NAK_10us = 0x1, 237 IBT_RNR_NAK_20us = 0x2, 238 IBT_RNR_NAK_30us = 0x3, 239 IBT_RNR_NAK_40us = 0x4, 240 IBT_RNR_NAK_60us = 0x5, 241 IBT_RNR_NAK_80us = 0x6, 242 IBT_RNR_NAK_120us = 0x7, 243 IBT_RNR_NAK_160us = 0x8, 244 IBT_RNR_NAK_240us = 0x9, 245 IBT_RNR_NAK_320us = 0xA, 246 IBT_RNR_NAK_480us = 0xB, 247 IBT_RNR_NAK_640us = 0xC, 248 IBT_RNR_NAK_960us = 0xD, 249 IBT_RNR_NAK_1280us = 0xE, 250 IBT_RNR_NAK_1920us = 0xF, 251 IBT_RNR_NAK_2560us = 0x10, 252 IBT_RNR_NAK_3840us = 0x11, 253 IBT_RNR_NAK_5120us = 0x12, 254 IBT_RNR_NAK_7680us = 0x13, 255 IBT_RNR_NAK_10ms = 0x14, 256 IBT_RNR_NAK_15ms = 0x15, 257 IBT_RNR_NAK_20ms = 0x16, 258 IBT_RNR_NAK_31ms = 0x17, 259 IBT_RNR_NAK_41ms = 0x18, 260 IBT_RNR_NAK_61ms = 0x19, 261 IBT_RNR_NAK_82ms = 0x1A, 262 IBT_RNR_NAK_123ms = 0x1B, 263 IBT_RNR_NAK_164ms = 0x1C, 264 IBT_RNR_NAK_246ms = 0x1D, 265 IBT_RNR_NAK_328ms = 0x1E, 266 IBT_RNR_NAK_492ms = 0x1F 267 } ibt_rnr_nak_time_t; 268 269 /* 270 * The definition of HCA capabilities etc as a bitfield. 271 */ 272 typedef enum ibt_hca_flags_e { 273 IBT_HCA_NO_FLAGS = 0, 274 275 IBT_HCA_RD = 1 << 0, 276 IBT_HCA_UD_MULTICAST = 1 << 1, 277 IBT_HCA_RAW_MULTICAST = 1 << 2, 278 279 IBT_HCA_ATOMICS_HCA = 1 << 3, 280 IBT_HCA_ATOMICS_GLOBAL = 1 << 4, 281 282 IBT_HCA_RESIZE_CHAN = 1 << 5, /* Is resize supported? */ 283 IBT_HCA_AUTO_PATH_MIG = 1 << 6, /* Is APM supported? */ 284 IBT_HCA_SQD_SQD_PORT = 1 << 7, /* Can change physical port */ 285 /* on transit from SQD to SQD */ 286 IBT_HCA_PKEY_CNTR = 1 << 8, 287 IBT_HCA_QKEY_CNTR = 1 << 9, 288 IBT_HCA_AH_PORT_CHECK = 1 << 10, /* HCA checks AH port match */ 289 /* in UD WRs */ 290 IBT_HCA_PORT_UP = 1 << 11, /* PortActive event supported */ 291 IBT_HCA_INIT_TYPE = 1 << 12, /* InitType supported */ 292 IBT_HCA_SI_GUID = 1 << 13, /* System Image GUID */ 293 /* supported */ 294 IBT_HCA_SHUTDOWN_PORT = 1 << 14, /* ShutdownPort supported */ 295 IBT_HCA_RNR_NAK = 1 << 15, /* RNR-NAK supported for RC */ 296 IBT_HCA_CURRENT_QP_STATE = 1 << 16, /* Does modify_qp support */ 297 /* checking of current state? */ 298 IBT_HCA_SRQ = 1 << 17, /* Shared Receive Queue */ 299 IBT_HCA_RESIZE_SRQ = 1 << 18, /* Is resize SRQ supported? */ 300 IBT_HCA_BASE_MEM_MGT = 1 << 19, /* Base memory mgt supported? */ 301 IBT_HCA_MULT_PAGE_SZ_MR = 1 << 20, /* Support of multiple page */ 302 /* sizes per memory region? */ 303 IBT_HCA_BLOCK_LIST = 1 << 21, /* Block list physical buffer */ 304 /* lists supported? */ 305 IBT_HCA_ZERO_BASED_VA = 1 << 22, /* Zero Based Virtual */ 306 /* Addresses supported? */ 307 IBT_HCA_LOCAL_INVAL_FENCE = 1 << 23, /* Local invalidate fencing? */ 308 IBT_HCA_BASE_QUEUE_MGT = 1 << 24, /* Base Queue Mgt supported? */ 309 IBT_HCA_CKSUM_FULL = 1 << 25, /* Checksum offload supported */ 310 IBT_HCA_MEM_WIN_TYPE_2B = 1 << 26, /* Type 2B memory windows */ 311 IBT_HCA_PHYS_BUF_BLOCK = 1 << 27, /* Block mode phys buf lists */ 312 IBT_HCA_FMR = 1 << 28 /* FMR Support */ 313 } ibt_hca_flags_t; 314 315 /* 316 * The definition of HCA page size capabilities as a bitfield 317 */ 318 typedef enum ibt_page_sizes_e { 319 IBT_PAGE_4K = 0x1 << 2, 320 IBT_PAGE_8K = 0x1 << 3, 321 IBT_PAGE_16K = 0x1 << 4, 322 IBT_PAGE_32K = 0x1 << 5, 323 IBT_PAGE_64K = 0x1 << 6, 324 IBT_PAGE_128K = 0x1 << 7, 325 IBT_PAGE_256K = 0x1 << 8, 326 IBT_PAGE_512K = 0x1 << 9, 327 IBT_PAGE_1M = 0x1 << 10, 328 IBT_PAGE_2M = 0x1 << 11, 329 IBT_PAGE_4M = 0x1 << 12, 330 IBT_PAGE_8M = 0x1 << 13, 331 IBT_PAGE_16M = 0x1 << 14, 332 IBT_PAGE_32M = 0x1 << 15, 333 IBT_PAGE_64M = 0x1 << 16, 334 IBT_PAGE_128M = 0x1 << 17, 335 IBT_PAGE_256M = 0x1 << 18, 336 IBT_PAGE_512M = 0x1 << 19, 337 IBT_PAGE_1G = 0x1 << 20, 338 IBT_PAGE_2G = 0x1 << 21, 339 IBT_PAGE_4G = 0x1 << 22, 340 IBT_PAGE_8G = 0x1 << 23, 341 IBT_PAGE_16G = 0x1 << 24 342 } ibt_page_sizes_t; 343 344 /* 345 * Memory Window Type. 346 */ 347 typedef enum ibt_mem_win_type_e { 348 IBT_MEM_WIN_TYPE_NOT_DEFINED = 0, 349 IBT_MEM_WIN_TYPE_1 = (1 << 0), 350 IBT_MEM_WIN_TYPE_2 = (1 << 1) 351 } ibt_mem_win_type_t; 352 353 /* 354 * HCA attributes. 355 * Contains all HCA static attributes. 356 */ 357 typedef struct ibt_hca_attr_s { 358 ibt_hca_flags_t hca_flags; /* HCA capabilities etc */ 359 360 /* device/version inconsistency w/ NodeInfo and IOControllerProfile */ 361 uint32_t hca_vendor_id:24; /* 24 bit Vendor ID */ 362 uint16_t hca_device_id; 363 uint32_t hca_version_id; 364 365 uint_t hca_max_chans; /* Max Chans supported */ 366 uint_t hca_max_chan_sz; /* Max outstanding WRs on any */ 367 /* channel */ 368 369 uint_t hca_max_sgl; /* Max SGL entries per WR */ 370 371 uint_t hca_max_cq; /* Max num of CQs supported */ 372 uint_t hca_max_cq_sz; /* Max capacity of each CQ */ 373 374 ibt_page_sizes_t hca_page_sz; /* Bit mask of page sizes */ 375 376 uint_t hca_max_memr; /* Max num of HCA mem regions */ 377 ib_memlen_t hca_max_memr_len; /* Largest block, in bytes of */ 378 /* mem that can be registered */ 379 uint_t hca_max_mem_win; /* Max Memory windows in HCA */ 380 381 uint_t hca_max_rsc; /* Max Responder Resources of */ 382 /* this HCA for RDMAR/Atomics */ 383 /* with this HCA as target. */ 384 uint8_t hca_max_rdma_in_chan; /* Max RDMAR/Atomics in per */ 385 /* chan this HCA as target. */ 386 uint8_t hca_max_rdma_out_chan; /* Max RDMA Reads/Atomics out */ 387 /* per channel by this HCA */ 388 uint_t hca_max_ipv6_chan; /* Max IPV6 channels in HCA */ 389 uint_t hca_max_ether_chan; /* Max Ether channels in HCA */ 390 391 uint_t hca_max_mcg_chans; /* Max number of channels */ 392 /* that can join multicast */ 393 /* groups */ 394 uint_t hca_max_mcg; /* Max multicast groups */ 395 uint_t hca_max_chan_per_mcg; /* Max number of channels per */ 396 /* Multicast group in HCA */ 397 398 uint16_t hca_max_partitions; /* Max partitions in HCA */ 399 uint8_t hca_nports; /* Number of physical ports */ 400 ib_guid_t hca_node_guid; /* Node GUID */ 401 402 ib_time_t hca_local_ack_delay; 403 404 uint_t hca_max_port_sgid_tbl_sz; 405 uint16_t hca_max_port_pkey_tbl_sz; 406 uint_t hca_max_pd; /* Max# of Protection Domains */ 407 ib_guid_t hca_si_guid; /* Optional System Image GUID */ 408 uint_t hca_hca_max_ci_priv_sz; 409 uint_t hca_chan_max_ci_priv_sz; 410 uint_t hca_cq_max_ci_priv_sz; 411 uint_t hca_pd_max_ci_priv_sz; 412 uint_t hca_mr_max_ci_priv_sz; 413 uint_t hca_mw_max_ci_priv_sz; 414 uint_t hca_ud_dest_max_ci_priv_sz; 415 uint_t hca_cq_sched_max_ci_priv_sz; 416 uint_t hca_max_ud_dest; 417 uint_t hca_opaque2; 418 uint_t hca_opaque3; 419 uint_t hca_opaque4; 420 uint8_t hca_opaque5; 421 uint8_t hca_opaque6; 422 uint_t hca_opaque7; 423 uint_t hca_opaque8; 424 uint_t hca_max_srqs; /* Max SRQs supported */ 425 uint_t hca_max_srqs_sz; /* Max outstanding WRs on any */ 426 /* SRQ */ 427 uint_t hca_max_srq_sgl; /* Max SGL entries per SRQ WR */ 428 uint_t hca_max_phys_buf_list_sz; 429 size_t hca_block_sz_lo; /* Range of block sizes */ 430 size_t hca_block_sz_hi; /* supported by the HCA */ 431 uint_t hca_max_cq_handlers; 432 ibt_lkey_t hca_reserved_lkey; 433 uint_t hca_max_fmrs; /* Max FMR Supported */ 434 uint_t hca_opaque9; 435 } ibt_hca_attr_t; 436 437 /* 438 * HCA Port link states. 439 */ 440 typedef enum ibt_port_state_e { 441 IBT_PORT_DOWN = 1, 442 IBT_PORT_INIT, 443 IBT_PORT_ARM, 444 IBT_PORT_ACTIVE 445 } ibt_port_state_t; 446 447 /* 448 * HCA Port capabilities as a bitfield. 449 */ 450 typedef enum ibt_port_caps_e { 451 IBT_PORT_CAP_NO_FLAGS = 0, 452 IBT_PORT_CAP_SM = 1 << 0, /* SM port */ 453 IBT_PORT_CAP_SM_DISABLED = 1 << 1, 454 IBT_PORT_CAP_SNMP_TUNNEL = 1 << 2, /* SNMP Tunneling */ 455 IBT_PORT_CAP_DM = 1 << 3, /* DM supported */ 456 IBT_PORT_CAP_VENDOR = 1 << 4 /* Vendor Class */ 457 } ibt_port_caps_t; 458 459 460 /* 461 * HCA port attributes structure definition. The number of ports per HCA 462 * can be found from the "ibt_hca_attr_t" structure. 463 * 464 * p_pkey_tbl is a pointer to an array of ib_pkey_t, members are 465 * accessed as: 466 * hca_portinfo->p_pkey_tbl[i] 467 * 468 * Where 0 <= i < hca_portinfo.p_pkey_tbl_sz 469 * 470 * Similarly p_sgid_tbl is a pointer to an array of ib_gid_t. 471 * 472 * The Query Port function - ibt_query_hca_ports() allocates the memory 473 * required for the ibt_hca_portinfo_t struct as well as the memory 474 * required for the SGID and P_Key tables. The memory is freed by calling 475 * ibt_free_portinfo(). 476 */ 477 typedef struct ibt_hca_portinfo_s { 478 ib_lid_t p_opaque1; /* Base LID of port */ 479 ib_qkey_cntr_t p_qkey_violations; /* Bad Q_Key cnt */ 480 ib_pkey_cntr_t p_pkey_violations; /* Optional bad P_Key cnt */ 481 uint8_t p_sm_sl:4; /* SM Service level */ 482 ib_lid_t p_sm_lid; /* SM LID */ 483 ibt_port_state_t p_linkstate; /* Port state */ 484 uint8_t p_port_num; 485 ib_mtu_t p_mtu; /* Max transfer unit - pkt */ 486 uint8_t p_lmc:3; /* Local mask control */ 487 ib_gid_t *p_sgid_tbl; /* SGID Table */ 488 uint_t p_sgid_tbl_sz; /* Size of SGID table */ 489 uint16_t p_pkey_tbl_sz; /* Size of P_Key table */ 490 uint16_t p_def_pkey_ix; /* default pkey index for TI */ 491 ib_pkey_t *p_pkey_tbl; /* P_Key table */ 492 uint8_t p_max_vl; /* Max num of virtual lanes */ 493 uint8_t p_init_type_reply; /* Optional InitTypeReply */ 494 ib_time_t p_subnet_timeout; /* Max Subnet Timeout */ 495 ibt_port_caps_t p_capabilities; /* Port Capabilities */ 496 uint32_t p_msg_sz; /* Max message size */ 497 } ibt_hca_portinfo_t; 498 499 /* 500 * Modify HCA port attributes flags, specifies which HCA port 501 * attributes to modify. 502 */ 503 typedef enum ibt_port_modify_flags_e { 504 IBT_PORT_NO_FLAGS = 0, 505 506 IBT_PORT_RESET_QKEY = 1 << 0, /* Reset Q_Key violation */ 507 /* counter */ 508 IBT_PORT_RESET_SM = 1 << 1, /* SM */ 509 IBT_PORT_SET_SM = 1 << 2, 510 IBT_PORT_RESET_SNMP = 1 << 3, /* SNMP Tunneling */ 511 IBT_PORT_SET_SNMP = 1 << 4, 512 IBT_PORT_RESET_DEVMGT = 1 << 5, /* Device Management */ 513 IBT_PORT_SET_DEVMGT = 1 << 6, 514 IBT_PORT_RESET_VENDOR = 1 << 7, /* Vendor Class */ 515 IBT_PORT_SET_VENDOR = 1 << 8, 516 IBT_PORT_SHUTDOWN = 1 << 9, /* Shut down the port */ 517 IBT_PORT_SET_INIT_TYPE = 1 << 10 /* InitTypeReply value */ 518 } ibt_port_modify_flags_t; 519 520 /* 521 * Modify HCA port InitType bit definitions, applicable only if 522 * IBT_PORT_SET_INIT_TYPE modify flag (ibt_port_modify_flags_t) is set. 523 */ 524 #define IBT_PINIT_NO_LOAD 0x1 525 #define IBT_PINIT_PRESERVE_CONTENT 0x2 526 #define IBT_PINIT_PRESERVE_PRESENCE 0x4 527 #define IBT_PINIT_NO_RESUSCITATE 0x8 528 529 530 /* 531 * Address vector definition. 532 */ 533 typedef struct ibt_adds_vect_s { 534 ib_gid_t av_dgid; /* IPV6 dest GID in GRH */ 535 ib_gid_t av_sgid; /* SGID */ 536 ibt_srate_t av_srate; /* Max static rate */ 537 uint8_t av_srvl:4; /* Service level in LRH */ 538 uint_t av_flow:20; /* 20 bit Flow Label */ 539 uint8_t av_tclass; /* Traffic Class */ 540 uint8_t av_hop; /* Hop Limit */ 541 uint8_t av_port_num; /* Port number for UD */ 542 boolean_t av_opaque1; 543 ib_lid_t av_opaque2; 544 ib_path_bits_t av_opaque3; 545 uint32_t av_opaque4; 546 } ibt_adds_vect_t; 547 548 typedef struct ibt_cep_path_s { 549 ibt_adds_vect_t cep_adds_vect; /* Address Vector */ 550 uint16_t cep_pkey_ix; /* P_Key Index */ 551 uint8_t cep_hca_port_num; /* Port number for connected */ 552 /* channels. A value of 0 */ 553 /* indicates an invalid path */ 554 ib_time_t cep_cm_opaque1; 555 } ibt_cep_path_t; 556 557 /* 558 * Channel Migration State. 559 */ 560 typedef enum ibt_cep_cmstate_e { 561 IBT_STATE_NOT_SUPPORTED = 0, 562 IBT_STATE_MIGRATED = 1, 563 IBT_STATE_REARMED = 2, 564 IBT_STATE_ARMED = 3 565 } ibt_cep_cmstate_t; 566 567 /* 568 * Transport service type 569 * 570 * NOTE: this was converted from an enum to a uint8_t to save space. 571 */ 572 typedef uint8_t ibt_tran_srv_t; 573 574 #define IBT_RC_SRV 0 575 #define IBT_UC_SRV 1 576 #define IBT_RD_SRV 2 577 #define IBT_UD_SRV 3 578 #define IBT_RAWIP_SRV 4 579 #define IBT_RAWETHER_SRV 5 580 581 /* 582 * Channel (QP/EEC) state definitions. 583 */ 584 typedef enum ibt_cep_state_e { 585 IBT_STATE_RESET = 0, /* Reset */ 586 IBT_STATE_INIT, /* Initialized */ 587 IBT_STATE_RTR, /* Ready to Receive */ 588 IBT_STATE_RTS, /* Ready to Send */ 589 IBT_STATE_SQD, /* Send Queue Drained */ 590 IBT_STATE_SQE, /* Send Queue Error */ 591 IBT_STATE_ERROR, /* Error */ 592 IBT_STATE_SQDRAIN, /* Send Queue Draining */ 593 IBT_STATE_NUM /* Number of states */ 594 } ibt_cep_state_t; 595 596 597 /* 598 * Channel Attribute flags. 599 */ 600 typedef enum ibt_attr_flags_e { 601 IBT_ALL_SIGNALED = 0, /* All sends signaled */ 602 IBT_WR_SIGNALED = 1, /* Signaled on a WR basis */ 603 IBT_FAST_REG_RES_LKEY = (1 << 1) 604 } ibt_attr_flags_t; 605 606 /* 607 * Channel End Point (CEP) Control Flags. 608 */ 609 typedef enum ibt_cep_flags_e { 610 IBT_CEP_NO_FLAGS = 0, /* Enable Nothing */ 611 IBT_CEP_RDMA_RD = (1 << 0), /* Enable incoming RDMA RD's */ 612 /* RC & RD only */ 613 IBT_CEP_RDMA_WR = (1 << 1), /* Enable incoming RDMA WR's */ 614 /* RC & RD only */ 615 IBT_CEP_ATOMIC = (1 << 2) /* Enable incoming Atomics, */ 616 /* RC & RD only */ 617 } ibt_cep_flags_t; 618 619 /* 620 * Channel Modify Flags 621 */ 622 typedef enum ibt_cep_modify_flags_e { 623 IBT_CEP_SET_NOTHING = 0, 624 IBT_CEP_SET_SQ_SIZE = (1 << 1), 625 IBT_CEP_SET_RQ_SIZE = (1 << 2), 626 627 IBT_CEP_SET_RDMA_R = (1 << 3), 628 IBT_CEP_SET_RDMA_W = (1 << 4), 629 IBT_CEP_SET_ATOMIC = (1 << 5), 630 631 IBT_CEP_SET_ALT_PATH = (1 << 6), /* Alternate Path */ 632 633 IBT_CEP_SET_ADDS_VECT = (1 << 7), 634 IBT_CEP_SET_PORT = (1 << 8), 635 IBT_CEP_SET_OPAQUE5 = (1 << 9), 636 IBT_CEP_SET_RETRY = (1 << 10), 637 IBT_CEP_SET_RNR_NAK_RETRY = (1 << 11), 638 IBT_CEP_SET_MIN_RNR_NAK = (1 << 12), 639 640 IBT_CEP_SET_QKEY = (1 << 13), 641 IBT_CEP_SET_RDMARA_OUT = (1 << 14), 642 IBT_CEP_SET_RDMARA_IN = (1 << 15), 643 644 IBT_CEP_SET_OPAQUE1 = (1 << 16), 645 IBT_CEP_SET_OPAQUE2 = (1 << 17), 646 IBT_CEP_SET_OPAQUE3 = (1 << 18), 647 IBT_CEP_SET_OPAQUE4 = (1 << 19), 648 IBT_CEP_SET_SQD_EVENT = (1 << 20), 649 IBT_CEP_SET_OPAQUE6 = (1 << 21), 650 IBT_CEP_SET_OPAQUE7 = (1 << 22), 651 IBT_CEP_SET_OPAQUE8 = (1 << 23) 652 } ibt_cep_modify_flags_t; 653 654 /* 655 * CQ notify types. 656 */ 657 typedef enum ibt_cq_notify_flags_e { 658 IBT_NEXT_COMPLETION = 1, 659 IBT_NEXT_SOLICITED = 2 660 } ibt_cq_notify_flags_t; 661 662 /* 663 * CQ types shared across TI and CI. 664 */ 665 typedef enum ibt_cq_flags_e { 666 IBT_CQ_NO_FLAGS = 0, 667 IBT_CQ_HANDLER_IN_THREAD = 1 << 0, /* A thread calls the */ 668 /* CQ handler */ 669 IBT_CQ_USER_MAP = 1 << 1, 670 IBT_CQ_DEFER_ALLOC = 1 << 2 671 } ibt_cq_flags_t; 672 673 /* 674 * CQ types shared across TI and CI. 675 */ 676 typedef enum ibt_cq_sched_flags_e { 677 IBT_CQS_NO_FLAGS = 0, 678 IBT_CQS_WARM_CACHE = 1 << 0, /* run on same CPU */ 679 IBT_CQS_AFFINITY = 1 << 1, 680 IBT_CQS_SCHED_GROUP = 1 << 2, 681 IBT_CQS_USER_MAP = 1 << 3, 682 IBT_CQS_DEFER_ALLOC = 1 << 4 683 } ibt_cq_sched_flags_t; 684 685 /* 686 * Attributes when creating a Completion Queue. 687 * 688 * Note: 689 * The IBT_CQ_HANDLER_IN_THREAD cq_flags bit should be ignored by the CI. 690 */ 691 typedef struct ibt_cq_attr_s { 692 uint_t cq_size; 693 ibt_sched_hdl_t cq_sched; /* 0 = no hint, */ 694 /* other = cq_sched value */ 695 ibt_cq_flags_t cq_flags; 696 } ibt_cq_attr_t; 697 698 /* 699 * Memory Management 700 */ 701 702 /* Memory management flags */ 703 typedef enum ibt_mr_flags_e { 704 IBT_MR_SLEEP = 0, 705 IBT_MR_NOSLEEP = (1 << 1), 706 IBT_MR_NONCOHERENT = (1 << 2), 707 IBT_MR_PHYS_IOVA = (1 << 3), /* ibt_(re)register_buf */ 708 709 /* Access control flags */ 710 IBT_MR_ENABLE_WINDOW_BIND = (1 << 4), 711 IBT_MR_ENABLE_LOCAL_WRITE = (1 << 5), 712 IBT_MR_ENABLE_REMOTE_READ = (1 << 6), 713 IBT_MR_ENABLE_REMOTE_WRITE = (1 << 7), 714 IBT_MR_ENABLE_REMOTE_ATOMIC = (1 << 8), 715 716 /* Reregister flags */ 717 IBT_MR_CHANGE_TRANSLATION = (1 << 9), 718 IBT_MR_CHANGE_ACCESS = (1 << 10), 719 IBT_MR_CHANGE_PD = (1 << 11), 720 721 /* Additional registration flags */ 722 IBT_MR_ZBVA = (1 << 12), 723 724 /* Additional physical registration flags */ 725 IBT_MR_CONSUMER_KEY = (1 << 13) /* Consumer owns key */ 726 /* portion of keys */ 727 } ibt_mr_flags_t; 728 729 730 /* Memory Region attribute flags */ 731 typedef enum ibt_mr_attr_flags_e { 732 /* Access control flags */ 733 IBT_MR_WINDOW_BIND = (1 << 0), 734 IBT_MR_LOCAL_WRITE = (1 << 1), 735 IBT_MR_REMOTE_READ = (1 << 2), 736 IBT_MR_REMOTE_WRITE = (1 << 3), 737 IBT_MR_REMOTE_ATOMIC = (1 << 4), 738 IBT_MR_ZERO_BASED_VA = (1 << 5), 739 IBT_MR_CONSUMER_OWNED_KEY = (1 << 6), 740 IBT_MR_SHARED = (1 << 7), 741 IBT_MR_FMR = (1 << 8) 742 } ibt_mr_attr_flags_t; 743 744 /* Memory region physical descriptor. */ 745 typedef struct ibt_phys_buf_s { 746 union { 747 uint64_t _p_ll; /* 64 bit DMA address */ 748 uint32_t _p_la[2]; /* 2 x 32 bit address */ 749 } _phys_buf; 750 size_t p_size; 751 } ibt_phys_buf_t; 752 753 #define p_laddr _phys_buf._p_ll 754 #ifdef _LONG_LONG_HTOL 755 #define p_notused _phys_buf._p_la[0] 756 #define p_addr _phys_buf._p_la[1] 757 #else 758 #define p_addr _phys_buf._p_la[0] 759 #define p_notused _phys_buf._p_la[1] 760 #endif 761 762 763 /* Memory region descriptor. */ 764 typedef struct ibt_mr_desc_s { 765 ib_vaddr_t md_vaddr; /* IB virtual adds of memory */ 766 ibt_lkey_t md_lkey; 767 ibt_rkey_t md_rkey; 768 boolean_t md_sync_required; 769 } ibt_mr_desc_t; 770 771 /* Physical Memory region descriptor. */ 772 typedef struct ibt_pmr_desc_s { 773 ib_vaddr_t pmd_iova; /* Returned I/O Virtual Address */ 774 ibt_lkey_t pmd_lkey; 775 ibt_rkey_t pmd_rkey; 776 uint_t pmd_phys_buf_list_sz; /* Allocated Phys buf sz */ 777 boolean_t pmd_sync_required; 778 } ibt_pmr_desc_t; 779 780 /* Memory region protection bounds. */ 781 typedef struct ibt_mr_prot_bounds_s { 782 ib_vaddr_t pb_addr; /* Beginning address */ 783 size_t pb_len; /* Length of protected region */ 784 } ibt_mr_prot_bounds_t; 785 786 /* Memory Region (Re)Register attributes */ 787 typedef struct ibt_mr_attr_s { 788 ib_vaddr_t mr_vaddr; /* Virtual address to register */ 789 ib_memlen_t mr_len; /* Length of region to register */ 790 struct as *mr_as; /* A pointer to an address space */ 791 /* structure. This parameter should */ 792 /* be set to NULL, which implies */ 793 /* kernel address space. */ 794 ibt_mr_flags_t mr_flags; 795 } ibt_mr_attr_t; 796 797 /* Physical Memory Region (Re)Register */ 798 typedef struct ibt_pmr_attr_s { 799 ib_vaddr_t pmr_iova; /* I/O virtual address requested by */ 800 /* client for the first byte of the */ 801 /* region */ 802 ib_memlen_t pmr_len; /* Length of region to register */ 803 ib_memlen_t pmr_offset; /* Offset of the regions starting */ 804 /* IOVA within the 1st physical */ 805 /* buffer */ 806 ibt_mr_flags_t pmr_flags; 807 ibt_lkey_t pmr_lkey; /* Reregister only */ 808 ibt_rkey_t pmr_rkey; /* Reregister only */ 809 uint8_t pmr_key; /* Key to use on new Lkey & Rkey */ 810 uint_t pmr_num_buf; /* Num of entries in the pmr_buf_list */ 811 size_t pmr_buf_sz; 812 ibt_phys_buf_t *pmr_buf_list; /* List of physical buffers accessed */ 813 /* as an array */ 814 ibt_ma_hdl_t pmr_ma; /* Memory handle used to obtain the */ 815 /* pmr_buf_list */ 816 } ibt_pmr_attr_t; 817 818 819 /* 820 * Memory Region (Re)Register attributes - used by ibt_register_shared_mr(), 821 * ibt_register_buf() and ibt_reregister_buf(). 822 */ 823 typedef struct ibt_smr_attr_s { 824 ib_vaddr_t mr_vaddr; 825 ibt_mr_flags_t mr_flags; 826 uint8_t mr_key; /* Only for physical */ 827 /* ibt_(Re)register_buf() */ 828 ibt_lkey_t mr_lkey; /* Only for physical */ 829 ibt_rkey_t mr_rkey; /* ibt_Reregister_buf() */ 830 } ibt_smr_attr_t; 831 832 /* 833 * key states. 834 */ 835 typedef enum ibt_key_state_e { 836 IBT_KEY_INVALID = 0, 837 IBT_KEY_FREE, 838 IBT_KEY_VALID 839 } ibt_key_state_t; 840 841 /* Memory region query attributes */ 842 typedef struct ibt_mr_query_attr_s { 843 ibt_lkey_t mr_lkey; 844 ibt_rkey_t mr_rkey; 845 ibt_mr_prot_bounds_t mr_lbounds; /* Actual local CI protection */ 846 /* bounds */ 847 ibt_mr_prot_bounds_t mr_rbounds; /* Actual remote CI */ 848 /* protection bounds */ 849 ibt_mr_attr_flags_t mr_attr_flags; /* Access rights etc. */ 850 ibt_pd_hdl_t mr_pd; /* Protection domain */ 851 boolean_t mr_sync_required; 852 ibt_key_state_t mr_lkey_state; 853 uint_t mr_phys_buf_list_sz; 854 } ibt_mr_query_attr_t; 855 856 /* Memory window query attributes */ 857 typedef struct ibt_mw_query_attr_s { 858 ibt_pd_hdl_t mw_pd; 859 ibt_mem_win_type_t mw_type; 860 ibt_rkey_t mw_rkey; 861 ibt_key_state_t mw_state; 862 } ibt_mw_query_attr_t; 863 864 865 /* Memory Region Sync Flags. */ 866 #define IBT_SYNC_READ 0x1 /* Make memory changes visible to incoming */ 867 /* RDMA reads */ 868 869 #define IBT_SYNC_WRITE 0x2 /* Make the affects of an incoming RDMA write */ 870 /* visible to the consumer */ 871 872 /* Memory region sync args */ 873 typedef struct ibt_mr_sync_s { 874 ibt_mr_hdl_t ms_handle; 875 ib_vaddr_t ms_vaddr; 876 ib_memlen_t ms_len; 877 uint32_t ms_flags; /* IBT_SYNC_READ or IBT_SYNC_WRITE */ 878 } ibt_mr_sync_t; 879 880 /* 881 * Flags for Virtual Address to HCA Physical Address translation. 882 */ 883 typedef enum ibt_va_flags_e { 884 IBT_VA_SLEEP = 0, 885 IBT_VA_NOSLEEP = (1 << 0), 886 IBT_VA_NONCOHERENT = (1 << 1), 887 IBT_VA_FMR = (1 << 2), 888 IBT_VA_BLOCK_MODE = (1 << 3), 889 IBT_VA_BUF = (1 << 4) 890 } ibt_va_flags_t; 891 892 893 /* Address Translation parameters */ 894 typedef struct ibt_va_attr_s { 895 ib_vaddr_t va_vaddr; /* Virtual address to register */ 896 ib_memlen_t va_len; /* Length of region to register */ 897 struct as *va_as; /* A pointer to an address space */ 898 /* structure. */ 899 size_t va_phys_buf_min; 900 size_t va_phys_buf_max; 901 ibt_va_flags_t va_flags; 902 struct buf *va_buf; 903 } ibt_va_attr_t; 904 905 906 /* 907 * Fast Memory Registration (FMR) support. 908 */ 909 910 /* FMR flush function handler. */ 911 typedef void (*ibt_fmr_flush_handler_t)(ibt_fmr_pool_hdl_t fmr_pool, 912 void *fmr_func_arg); 913 914 /* FMR Pool create attributes. */ 915 typedef struct ibt_fmr_pool_attr_s { 916 uint_t fmr_max_pages_per_fmr; 917 uint_t fmr_pool_size; 918 uint_t fmr_dirty_watermark; 919 size_t fmr_page_sz; 920 boolean_t fmr_cache; 921 ibt_mr_flags_t fmr_flags; 922 ibt_fmr_flush_handler_t fmr_func_hdlr; 923 void *fmr_func_arg; 924 } ibt_fmr_pool_attr_t; 925 926 927 /* 928 * WORK REQUEST AND WORK REQUEST COMPLETION DEFINITIONS. 929 */ 930 931 /* 932 * Work Request and Work Request Completion types - These types are used 933 * to indicate the type of work requests posted to a work queue 934 * or the type of completion received. Immediate Data is indicated via 935 * ibt_wr_flags_t or ibt_wc_flags_t. 936 * 937 * IBT_WRC_RECV and IBT_WRC_RECV_RDMAWI are only used as opcodes in the 938 * work completions. 939 * 940 * NOTE: this was converted from an enum to a uint8_t to save space. 941 */ 942 typedef uint8_t ibt_wrc_opcode_t; 943 944 #define IBT_WRC_SEND 1 /* Send */ 945 #define IBT_WRC_RDMAR 2 /* RDMA Read */ 946 #define IBT_WRC_RDMAW 3 /* RDMA Write */ 947 #define IBT_WRC_CSWAP 4 /* Compare & Swap Atomic */ 948 #define IBT_WRC_FADD 5 /* Fetch & Add Atomic */ 949 #define IBT_WRC_BIND 6 /* Bind Memory Window */ 950 #define IBT_WRC_RECV 7 /* Receive */ 951 #define IBT_WRC_RECV_RDMAWI 8 /* Received RDMA Write w/ Immediate */ 952 #define IBT_WRC_FAST_REG_PMR 9 /* Fast Register Physical mem region */ 953 #define IBT_WRC_LOCAL_INVALIDATE 10 954 955 956 /* 957 * Work Request Completion flags - These flags indicate what type 958 * of data is present in the Work Request Completion structure 959 */ 960 typedef uint8_t ibt_wc_flags_t; 961 962 #define IBT_WC_NO_FLAGS 0 963 #define IBT_WC_GRH_PRESENT (1 << 0) 964 #define IBT_WC_IMMED_DATA_PRESENT (1 << 1) 965 #define IBT_WC_RKEY_INVALIDATED (1 << 2) 966 #define IBT_WC_CKSUM_OK (1 << 3) 967 968 969 /* 970 * Work Request Completion - This structure encapsulates the information 971 * necessary to define a work request completion. 972 */ 973 typedef struct ibt_wc_s { 974 ibt_wrid_t wc_id; /* Work Request Id */ 975 uint64_t wc_fma_ena; /* fault management err data */ 976 ib_msglen_t wc_bytes_xfer; /* Number of Bytes */ 977 /* Transferred */ 978 ibt_wc_flags_t wc_flags; /* WR Completion Flags */ 979 ibt_wrc_opcode_t wc_type; /* Operation Type */ 980 uint16_t wc_cksum; /* payload checksum */ 981 ibt_immed_t wc_immed_data; /* Immediate Data */ 982 uint32_t wc_freed_rc; /* Freed Resource Count */ 983 ibt_wc_status_t wc_status; /* Completion Status */ 984 uint8_t wc_sl:4; /* Remote SL */ 985 uint16_t wc_ethertype; /* Ethertype Field - RE */ 986 ib_lid_t wc_opaque1; 987 uint16_t wc_opaque2; 988 ib_qpn_t wc_qpn; /* Source QPN Datagram only */ 989 ib_eecn_t wc_opaque3; 990 ib_qpn_t wc_local_qpn; 991 ibt_rkey_t wc_rkey; 992 ib_path_bits_t wc_opaque4; 993 } ibt_wc_t; 994 995 996 /* 997 * WR Flags. Common for both RC and UD 998 * 999 * NOTE: this was converted from an enum to a uint8_t to save space. 1000 */ 1001 typedef uint8_t ibt_wr_flags_t; 1002 1003 #define IBT_WR_NO_FLAGS 0 1004 #define IBT_WR_SEND_IMMED (1 << 0) /* Immediate Data Indicator */ 1005 #define IBT_WR_SEND_SIGNAL (1 << 1) /* Signaled, if set */ 1006 #define IBT_WR_SEND_FENCE (1 << 2) /* Fence Indicator */ 1007 #define IBT_WR_SEND_SOLICIT (1 << 3) /* Solicited Event Indicator */ 1008 #define IBT_WR_SEND_REMOTE_INVAL (1 << 4) /* Remote Invalidate */ 1009 #define IBT_WR_SEND_CKSUM (1 << 5) /* Checksum offload Indicator */ 1010 1011 /* 1012 * Access control flags for Bind Memory Window operation, 1013 * applicable for RC/UC/RD only. 1014 * 1015 * If IBT_WR_BIND_WRITE or IBT_WR_BIND_ATOMIC is desired then 1016 * it is required that Memory Region should have Local Write Access. 1017 */ 1018 typedef enum ibt_bind_flags_e { 1019 IBT_WR_BIND_READ = (1 << 0), /* enable remote read */ 1020 IBT_WR_BIND_WRITE = (1 << 1), /* enable remote write */ 1021 IBT_WR_BIND_ATOMIC = (1 << 2), /* enable remote atomics */ 1022 IBT_WR_BIND_ZBVA = (1 << 3) /* Zero Based Virtual Address */ 1023 } ibt_bind_flags_t; 1024 1025 /* 1026 * Data Segment for scatter-gather list 1027 * 1028 * SGL consists of an array of data segments and the length of the SGL. 1029 */ 1030 typedef struct ibt_wr_ds_s { 1031 ib_vaddr_t ds_va; /* Virtual Address */ 1032 ibt_lkey_t ds_key; /* L_Key */ 1033 ib_msglen_t ds_len; /* Length of DS */ 1034 } ibt_wr_ds_t; 1035 1036 /* 1037 * Bind Memory Window WR 1038 * 1039 * WR ID from ibt_send_wr_t applies here too, SWG_0038 errata. 1040 */ 1041 typedef struct ibt_wr_bind_s { 1042 ibt_bind_flags_t bind_flags; 1043 ibt_rkey_t bind_rkey; /* Mem Window's R_key */ 1044 ibt_lkey_t bind_lkey; /* Mem Region's L_Key */ 1045 ibt_rkey_t bind_rkey_out; /* OUT: new R_Key */ 1046 ibt_mr_hdl_t bind_ibt_mr_hdl; /* Mem Region handle */ 1047 ibt_mw_hdl_t bind_ibt_mw_hdl; /* Mem Window handle */ 1048 ib_vaddr_t bind_va; /* Virtual Address */ 1049 ib_memlen_t bind_len; /* Length of Window */ 1050 } ibt_wr_bind_t; 1051 1052 /* 1053 * Atomic WR 1054 * 1055 * Operation type (compare & swap or fetch & add) in ibt_wrc_opcode_t. 1056 * 1057 * A copy of the original contents of the remote memory will be stored 1058 * in the local data segment described by wr_sgl within ibt_send_wr_t, 1059 * and wr_nds should be set to 1. 1060 * 1061 * Atomic operation operands: 1062 * Compare & Swap Operation: 1063 * atom_arg1 - Compare Operand 1064 * atom_arg2 - Swap Operand 1065 * 1066 * Fetch & Add Operation: 1067 * atom_arg1 - Add Operand 1068 * atom_arg2 - ignored 1069 */ 1070 typedef struct ibt_wr_atomic_s { 1071 ib_vaddr_t atom_raddr; /* Remote address. */ 1072 ibt_atom_arg_t atom_arg1; /* operand #1 */ 1073 ibt_atom_arg_t atom_arg2; /* operand #2 */ 1074 ibt_rkey_t atom_rkey; /* R_Key. */ 1075 } ibt_wr_atomic_t; 1076 1077 /* 1078 * RDMA WR 1079 * Immediate Data indicator in ibt_wr_flags_t. 1080 */ 1081 typedef struct ibt_wr_rdma_s { 1082 ib_vaddr_t rdma_raddr; /* Remote address. */ 1083 ibt_rkey_t rdma_rkey; /* R_Key. */ 1084 ibt_immed_t rdma_immed; /* Immediate Data */ 1085 } ibt_wr_rdma_t; 1086 1087 /* 1088 * Fast Register Physical Memory Region Work Request. 1089 */ 1090 typedef struct ibt_wr_reg_pmr_s { 1091 ib_vaddr_t pmr_iova; /* I/O virtual address requested by */ 1092 /* client for the first byte of the */ 1093 /* region */ 1094 ib_memlen_t pmr_len; /* Length of region to register */ 1095 ib_memlen_t pmr_offset; /* Offset of the regions starting */ 1096 /* IOVA within the 1st physical */ 1097 /* buffer */ 1098 ibt_mr_hdl_t pmr_mr_hdl; 1099 ibt_phys_buf_t *pmr_buf_list; /* List of physical buffers accessed */ 1100 /* as an array */ 1101 uint_t pmr_num_buf; /* Num of entries in the pmr_buf_list */ 1102 ibt_lkey_t pmr_lkey; 1103 ibt_rkey_t pmr_rkey; 1104 ibt_mr_flags_t pmr_flags; 1105 uint8_t pmr_key; /* Key to use on new Lkey & Rkey */ 1106 } ibt_wr_reg_pmr_t; 1107 1108 /* 1109 * Local Invalidate. 1110 */ 1111 typedef struct ibt_wr_li_s { 1112 ibt_mr_hdl_t li_mr_hdl; /* Null for MW invalidates */ 1113 ibt_mw_hdl_t li_mw_hdl; /* Null for MR invalidates */ 1114 ibt_lkey_t li_lkey; /* Ignore for MW invalidates */ 1115 ibt_rkey_t li_rkey; 1116 } ibt_wr_li_t; 1117 1118 /* 1119 * Reserved For Future Use. 1120 * Raw IPv6 Send WR 1121 */ 1122 typedef struct ibt_wr_ripv6_s { 1123 ib_lid_t rip_dlid; /* DLID */ 1124 ib_path_bits_t rip_slid_bits; /* SLID path bits, SWG_0033 errata */ 1125 uint8_t rip_sl:4; /* SL */ 1126 ibt_srate_t rip_rate; /* Max Static Rate, SWG_0007 errata */ 1127 } ibt_wr_ripv6_t; 1128 1129 /* 1130 * Reserved For Future Use. 1131 * Raw Ethertype Send WR 1132 */ 1133 typedef struct ibt_wr_reth_s { 1134 ib_ethertype_t reth_type; /* Ethertype */ 1135 ib_lid_t reth_dlid; /* DLID */ 1136 ib_path_bits_t reth_slid_bits; /* SLID path bits, SWG_0033 errata */ 1137 uint8_t reth_sl:4; /* SL */ 1138 ibt_srate_t reth_rate; /* Max Static Rate, SWG_0007 errata */ 1139 } ibt_wr_reth_t; 1140 1141 /* 1142 * Reserved For future Use. 1143 * RD Send WR, Operation type in ibt_wrc_opcode_t. 1144 */ 1145 typedef struct ibt_wr_rd_s { 1146 ibt_rd_dest_hdl_t rdwr_dest_hdl; 1147 union { 1148 ibt_immed_t send_immed; /* IBT_WRC_SEND */ 1149 ibt_wr_rdma_t rdma; /* IBT_WRC_RDMAR */ 1150 /* IBT_WRC_RDMAW */ 1151 ibt_wr_li_t *li; /* IBT_WRC_LOCAL_INVALIDATE */ 1152 ibt_wr_atomic_t *atomic; /* IBT_WRC_FADD */ 1153 /* IBT_WRC_CSWAP */ 1154 ibt_wr_bind_t *bind; /* IBT_WRC_BIND */ 1155 ibt_wr_reg_pmr_t *reg_pmr; /* IBT_WRC_FAST_REG_PMR */ 1156 } rdwr; 1157 } ibt_wr_rd_t; 1158 1159 /* 1160 * Reserved For Future Use. 1161 * UC Send WR, Operation type in ibt_wrc_opcode_t, the only valid 1162 * ones are: 1163 * IBT_WRC_SEND 1164 * IBT_WRC_RDMAW 1165 * IBT_WRC_BIND 1166 */ 1167 typedef struct ibt_wr_uc_s { 1168 union { 1169 ibt_immed_t send_immed; /* IBT_WRC_SEND */ 1170 ibt_wr_rdma_t rdma; /* IBT_WRC_RDMAW */ 1171 ibt_wr_li_t *li; /* IBT_WRC_LOCAL_INVALIDATE */ 1172 ibt_wr_bind_t *bind; /* IBT_WRC_BIND */ 1173 ibt_wr_reg_pmr_t *reg_pmr; /* IBT_WRC_FAST_REG_PMR */ 1174 } ucwr; 1175 } ibt_wr_uc_t; 1176 1177 /* 1178 * RC Send WR, Operation type in ibt_wrc_opcode_t. 1179 */ 1180 typedef struct ibt_wr_rc_s { 1181 union { 1182 ibt_immed_t send_immed; /* IBT_WRC_SEND w/ immediate */ 1183 ibt_rkey_t send_inval; /* IBT_WRC_SEND w/ invalidate */ 1184 ibt_wr_rdma_t rdma; /* IBT_WRC_RDMAR */ 1185 /* IBT_WRC_RDMAW */ 1186 ibt_wr_li_t *li; /* IBT_WRC_LOCAL_INVALIDATE */ 1187 ibt_wr_atomic_t *atomic; /* IBT_WRC_CSWAP */ 1188 /* IBT_WRC_FADD */ 1189 ibt_wr_bind_t *bind; /* IBT_WRC_BIND */ 1190 ibt_wr_reg_pmr_t *reg_pmr; /* IBT_WRC_FAST_REG_PMR */ 1191 } rcwr; 1192 } ibt_wr_rc_t; 1193 1194 /* 1195 * UD Send WR, the only valid Operation is IBT_WRC_SEND. 1196 */ 1197 typedef struct ibt_wr_ud_s { 1198 ibt_immed_t udwr_immed; 1199 ibt_ud_dest_hdl_t udwr_dest; 1200 } ibt_wr_ud_t; 1201 1202 /* 1203 * Send Work Request (WR) attributes structure. 1204 * 1205 * Operation type in ibt_wrc_opcode_t. 1206 * Immediate Data indicator in ibt_wr_flags_t. 1207 */ 1208 typedef struct ibt_send_wr_s { 1209 ibt_wrid_t wr_id; /* WR ID */ 1210 ibt_wr_flags_t wr_flags; /* Work Request Flags. */ 1211 ibt_tran_srv_t wr_trans; /* Transport Type. */ 1212 ibt_wrc_opcode_t wr_opcode; /* Operation Type. */ 1213 uint8_t wr_rsvd; /* maybe later */ 1214 uint32_t wr_nds; /* Number of data segments */ 1215 /* pointed to by wr_sgl */ 1216 ibt_wr_ds_t *wr_sgl; /* SGL */ 1217 union { 1218 ibt_wr_ud_t ud; 1219 ibt_wr_rc_t rc; 1220 ibt_wr_rd_t rd; /* Reserved For Future Use */ 1221 ibt_wr_uc_t uc; /* Reserved For Future Use */ 1222 ibt_wr_reth_t reth; /* Reserved For Future Use */ 1223 ibt_wr_ripv6_t ripv6; /* Reserved For Future Use */ 1224 } wr; /* operation specific */ 1225 } ibt_send_wr_t; 1226 1227 /* 1228 * Receive Work Request (WR) attributes structure. 1229 */ 1230 typedef struct ibt_recv_wr_s { 1231 ibt_wrid_t wr_id; /* WR ID */ 1232 uint32_t wr_nds; /* number of data segments */ 1233 /* pointed to by wr_sgl */ 1234 ibt_wr_ds_t *wr_sgl; /* SGL */ 1235 } ibt_recv_wr_t; 1236 1237 1238 /* 1239 * Asynchronous Events and Errors. 1240 * 1241 * The following codes are not used in calls to ibc_async_handler, but 1242 * are used by IBTL to inform IBT clients of a significant event. 1243 * 1244 * IBT_HCA_ATTACH_EVENT - New HCA available. 1245 * IBT_HCA_DETACH_EVENT - HCA is requesting not to be used. 1246 * 1247 * ERRORs on a channel indicate that the channel has entered error state. 1248 * EVENTs on a channel indicate that the channel has not changed state. 1249 * 1250 */ 1251 typedef enum ibt_async_code_e { 1252 IBT_EVENT_PATH_MIGRATED = 0x000001, 1253 IBT_EVENT_SQD = 0x000002, 1254 IBT_EVENT_COM_EST = 0x000004, 1255 IBT_ERROR_CATASTROPHIC_CHAN = 0x000008, 1256 IBT_ERROR_INVALID_REQUEST_CHAN = 0x000010, 1257 IBT_ERROR_ACCESS_VIOLATION_CHAN = 0x000020, 1258 IBT_ERROR_PATH_MIGRATE_REQ = 0x000040, 1259 1260 IBT_ERROR_CQ = 0x000080, 1261 1262 IBT_EVENT_PORT_UP = 0x000100, 1263 IBT_ERROR_PORT_DOWN = 0x000200, 1264 IBT_ERROR_LOCAL_CATASTROPHIC = 0x000400, 1265 1266 IBT_HCA_ATTACH_EVENT = 0x000800, 1267 IBT_HCA_DETACH_EVENT = 0x001000, 1268 IBT_ASYNC_OPAQUE1 = 0x002000, 1269 IBT_ASYNC_OPAQUE2 = 0x004000, 1270 IBT_ASYNC_OPAQUE3 = 0x008000, 1271 IBT_ASYNC_OPAQUE4 = 0x010000, 1272 IBT_EVENT_LIMIT_REACHED_SRQ = 0x020000, 1273 IBT_EVENT_EMPTY_CHAN = 0x040000, 1274 IBT_ERROR_CATASTROPHIC_SRQ = 0x080000 1275 } ibt_async_code_t; 1276 1277 1278 /* 1279 * ibt_ci_data_in() and ibt_ci_data_out() flags. 1280 */ 1281 typedef enum ibt_ci_data_flags_e { 1282 IBT_CI_NO_FLAGS = 0, 1283 IBT_CI_COMPLETE_ALLOC = (1 << 0) 1284 } ibt_ci_data_flags_t; 1285 1286 /* 1287 * Used by ibt_ci_data_in() and ibt_ci_data_out() identifies the type of handle 1288 * mapping data is being obtained for. 1289 */ 1290 typedef enum ibt_object_type_e { 1291 IBT_HDL_HCA = 1, 1292 IBT_HDL_CHANNEL, 1293 IBT_HDL_CQ, 1294 IBT_HDL_PD, 1295 IBT_HDL_MR, 1296 IBT_HDL_MW, 1297 IBT_HDL_UD_DEST, 1298 IBT_HDL_SCHED, 1299 IBT_HDL_OPAQUE1, 1300 IBT_HDL_OPAQUE2, 1301 IBT_HDL_SRQ 1302 } ibt_object_type_t; 1303 1304 /* 1305 * Memory error handler data structures; code, and payload data. 1306 */ 1307 typedef enum ibt_mem_code_s { 1308 IBT_MEM_AREA = 0x1, 1309 IBT_MEM_REGION = 0x2 1310 } ibt_mem_code_t; 1311 1312 typedef struct ibt_mem_data_s { 1313 uint64_t ev_fma_ena; /* FMA Error data */ 1314 ibt_mr_hdl_t ev_mr_hdl; /* MR handle */ 1315 ibt_ma_hdl_t ev_ma_hdl; /* MA handle */ 1316 } ibt_mem_data_t; 1317 1318 /* 1319 * Special case failure type. 1320 */ 1321 typedef enum ibt_failure_type_e { 1322 IBT_FAILURE_STANDARD = 0, 1323 IBT_FAILURE_CI, 1324 IBT_FAILURE_IBMF, 1325 IBT_FAILURE_IBTL, 1326 IBT_FAILURE_IBCM, 1327 IBT_FAILURE_IBDM, 1328 IBT_FAILURE_IBSM 1329 } ibt_failure_type_t; 1330 1331 #ifdef __cplusplus 1332 } 1333 #endif 1334 1335 #endif /* _SYS_IB_IBTL_IBTL_TYPES_H */ 1336