1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_IB_IBTL_IBTL_TYPES_H 27 #define _SYS_IB_IBTL_IBTL_TYPES_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 /* 32 * ibtl_types.h 33 * 34 * All common IBTL defined types. These are common data types 35 * that are shared by the IBTI and IBCI interfaces, it is only included 36 * by ibti.h and ibci.h 37 */ 38 #include <sys/ddi.h> 39 #include <sys/sunddi.h> 40 #include <sys/ib/ib_types.h> 41 #include <sys/ib/ibtl/ibtl_status.h> 42 #include <sys/socket.h> 43 44 45 #ifdef __cplusplus 46 extern "C" { 47 #endif 48 49 /* 50 * Define Internal IBTL handles 51 */ 52 typedef struct ibtl_clnt_s *ibt_clnt_hdl_t; /* ibt_attach() */ 53 typedef struct ibtl_hca_s *ibt_hca_hdl_t; /* ibt_open_hca() */ 54 typedef struct ibtl_channel_s *ibt_channel_hdl_t; /* alloc_rc|ud_channel() */ 55 typedef struct ibtl_srq_s *ibt_srq_hdl_t; /* ibt_alloc_srq() */ 56 typedef struct ibtl_cq_s *ibt_cq_hdl_t; /* ibt_alloc_cq() */ 57 typedef struct ibcm_svc_info_s *ibt_srv_hdl_t; /* ibt_register_service() */ 58 typedef struct ibcm_svc_bind_s *ibt_sbind_hdl_t; /* ibt_bind_service() */ 59 60 typedef struct ibc_fmr_pool_s *ibt_fmr_pool_hdl_t; /* ibt_create_fmr_pool() */ 61 typedef struct ibc_ma_s *ibt_ma_hdl_t; /* ibt_map_mem_area() */ 62 typedef struct ibc_pd_s *ibt_pd_hdl_t; /* ibt_alloc_pd() */ 63 typedef struct ibc_sched_s *ibt_sched_hdl_t; /* ibt_alloc_cq_sched() */ 64 typedef struct ibc_mr_s *ibt_mr_hdl_t; /* ibt_register_mr() */ 65 typedef struct ibc_mw_s *ibt_mw_hdl_t; /* ibt_alloc_mw() */ 66 typedef struct ibt_ud_dest_s *ibt_ud_dest_hdl_t; /* UD dest handle */ 67 typedef struct ibc_ah_s *ibt_ah_hdl_t; /* ibt_alloc_ah() */ 68 typedef struct ibtl_eec_s *ibt_eec_hdl_t; 69 typedef struct ibt_rd_dest_s *ibt_rd_dest_hdl_t; /* Reserved for */ 70 /* Future use */ 71 72 /* 73 * Some General Types. 74 */ 75 typedef uint32_t ibt_lkey_t; /* L_Key */ 76 typedef uint32_t ibt_rkey_t; /* R_Key */ 77 typedef uint64_t ibt_wrid_t; /* Client assigned WR ID */ 78 typedef uint32_t ibt_immed_t; /* WR Immediate Data */ 79 typedef uint64_t ibt_atom_arg_t; /* WR Atomic Operation arg */ 80 typedef uint_t ibt_cq_handler_id_t; /* Event handler ID */ 81 82 /* 83 * IBT selector type, used when looking up/requesting either an 84 * MTU, Pkt lifetime, or Static rate. 85 * The interpretation of IBT_BEST depends on the attribute being selected. 86 */ 87 typedef enum ibt_selector_e { 88 IBT_GT = 0, /* Greater than */ 89 IBT_LT = 1, /* Less than */ 90 IBT_EQU = 2, /* Equal to */ 91 IBT_BEST = 3 /* Best */ 92 } ibt_selector_t; 93 94 95 /* 96 * Static rate definitions. 97 */ 98 typedef enum ibt_srate_e { 99 IBT_SRATE_NOT_SPECIFIED = 0, 100 IBT_SRATE_2 = 2, /* 1X SDR i.e 2.5 Gbps */ 101 IBT_SRATE_10 = 3, /* 4X SDR or 1X QDR i.e 10 Gbps */ 102 IBT_SRATE_30 = 4, /* 12X SDR i.e 30 Gbps */ 103 104 IBT_SRATE_5 = 5, /* 1X DDR i.e 5 Gbps */ 105 IBT_SRATE_20 = 6, /* 4X DDR or 8X SDR i.e 20 Gbps */ 106 IBT_SRATE_40 = 7, /* 8X DDR or 4X QDR i.e 40 Gbps */ 107 108 IBT_SRATE_60 = 8, /* 12X DDR i.e 60 Gbps */ 109 IBT_SRATE_80 = 9, /* 8X QDR i.e 80 Gbps */ 110 IBT_SRATE_120 = 10 /* 12X QDR i.e 120 Gbps */ 111 } ibt_srate_t; 112 113 /* retain old definition to be compatible with older bits. */ 114 #define IBT_SRATE_1X IBT_SRATE_2 115 #define IBT_SRATE_4X IBT_SRATE_10 116 #define IBT_SRATE_12X IBT_SRATE_30 117 118 /* 119 * Static rate request type. 120 */ 121 typedef struct ibt_srate_req_s { 122 ibt_srate_t r_srate; /* Requested srate */ 123 ibt_selector_t r_selector; /* Qualifier for r_srate */ 124 } ibt_srate_req_t; 125 126 /* 127 * Packet Life Time Request Type. 128 */ 129 typedef struct ibt_pkt_lt_req_s { 130 clock_t p_pkt_lt; /* Requested Packet Life Time */ 131 ibt_selector_t p_selector; /* Qualifier for p_pkt_lt */ 132 } ibt_pkt_lt_req_t; 133 134 /* 135 * Queue size struct. 136 */ 137 typedef struct ibt_queue_sizes_s { 138 uint_t qs_sq; /* SendQ size. */ 139 uint_t qs_rq; /* RecvQ size. */ 140 } ibt_queue_sizes_t; 141 142 /* 143 * Channel sizes struct, used by functions that allocate/query RC or UD 144 * channels. 145 */ 146 typedef struct ibt_chan_sizes_s { 147 uint_t cs_sq; /* SendQ size. */ 148 uint_t cs_rq; /* ReceiveQ size. */ 149 uint_t cs_sq_sgl; /* Max SGL elements in a SQ WR. */ 150 uint_t cs_rq_sgl; /* Max SGL elements in a RQ Wr. */ 151 } ibt_chan_sizes_t; 152 153 /* 154 * Shared Queue size struct. 155 */ 156 typedef struct ibt_srq_sizes_s { 157 uint_t srq_wr_sz; 158 uint_t srq_sgl_sz; 159 } ibt_srq_sizes_t; 160 161 /* 162 * SRQ Modify Flags 163 */ 164 typedef enum ibt_srq_modify_flags_e { 165 IBT_SRQ_SET_NOTHING = 0, 166 IBT_SRQ_SET_SIZE = (1 << 1), 167 IBT_SRQ_SET_LIMIT = (1 << 2) 168 } ibt_srq_modify_flags_t; 169 170 171 /* 172 * Execution flags, indicates if the function should block or not. 173 * Note: in some cases, e.g., a NULL rc_cm_handler, IBT_NONBLOCKING 174 * will not have an effect, and the thread will block. 175 * IBT_NOCALLBACKS is valid for ibt_close_rc_channel only. 176 */ 177 typedef enum ibt_execution_mode_e { 178 IBT_BLOCKING = 0, /* Block */ 179 IBT_NONBLOCKING = 1, /* Return as soon as possible */ 180 IBT_NOCALLBACKS = 2 /* cm_handler is not invoked after */ 181 /* ibt_close_rc_channel returns */ 182 } ibt_execution_mode_t; 183 184 /* 185 * Memory window alloc flags 186 */ 187 typedef enum ibt_mw_flags_e { 188 IBT_MW_SLEEP = 0, /* Can block */ 189 IBT_MW_NOSLEEP = (1 << 0), /* Can't block */ 190 IBT_MW_USER_MAP = (1 << 1), 191 IBT_MW_DEFER_ALLOC = (1 << 2), 192 IBT_MW_TYPE_1 = (1 << 3), 193 IBT_MW_TYPE_2 = (1 << 4) 194 } ibt_mw_flags_t; 195 196 /* 197 * PD alloc flags 198 */ 199 typedef enum ibt_pd_flags_e { 200 IBT_PD_NO_FLAGS = 0, 201 IBT_PD_USER_MAP = (1 << 0), 202 IBT_PD_DEFER_ALLOC = (1 << 1) 203 } ibt_pd_flags_t; 204 205 /* 206 * UD Dest alloc flags 207 */ 208 typedef enum ibt_ud_dest_flags_e { 209 IBT_UD_DEST_NO_FLAGS = 0, 210 IBT_UD_DEST_USER_MAP = (1 << 0), 211 IBT_UD_DEST_DEFER_ALLOC = (1 << 1) 212 } ibt_ud_dest_flags_t; 213 214 /* 215 * SRQ alloc flags 216 */ 217 typedef enum ibt_srq_flags_e { 218 IBT_SRQ_NO_FLAGS = 0, 219 IBT_SRQ_USER_MAP = (1 << 0), 220 IBT_SRQ_DEFER_ALLOC = (1 << 1) 221 } ibt_srq_flags_t; 222 223 /* 224 * ibt_alloc_lkey() alloc flags 225 */ 226 typedef enum ibt_lkey_flags_e { 227 IBT_KEY_NO_FLAGS = 0, 228 IBT_KEY_REMOTE = (1 << 0) 229 } ibt_lkey_flags_t; 230 231 /* 232 * RNR NAK retry counts. 233 */ 234 typedef enum ibt_rnr_retry_cnt_e { 235 IBT_RNR_NO_RETRY = 0x0, /* Don't retry, fail on first timeout */ 236 IBT_RNR_RETRY_1 = 0x1, /* Retry once */ 237 IBT_RNR_RETRY_2 = 0x2, /* Retry twice */ 238 IBT_RNR_RETRY_3 = 0x3, /* Retry three times */ 239 IBT_RNR_RETRY_4 = 0x4, /* Retry four times */ 240 IBT_RNR_RETRY_5 = 0x5, /* Retry five times */ 241 IBT_RNR_RETRY_6 = 0x6, /* Retry six times */ 242 IBT_RNR_INFINITE_RETRY = 0x7 /* Retry forever */ 243 } ibt_rnr_retry_cnt_t; 244 245 /* 246 * Valid values for RNR NAK timer fields, part of a channel's context. 247 */ 248 typedef enum ibt_rnr_nak_time_e { 249 IBT_RNR_NAK_655ms = 0x0, 250 IBT_RNR_NAK_10us = 0x1, 251 IBT_RNR_NAK_20us = 0x2, 252 IBT_RNR_NAK_30us = 0x3, 253 IBT_RNR_NAK_40us = 0x4, 254 IBT_RNR_NAK_60us = 0x5, 255 IBT_RNR_NAK_80us = 0x6, 256 IBT_RNR_NAK_120us = 0x7, 257 IBT_RNR_NAK_160us = 0x8, 258 IBT_RNR_NAK_240us = 0x9, 259 IBT_RNR_NAK_320us = 0xA, 260 IBT_RNR_NAK_480us = 0xB, 261 IBT_RNR_NAK_640us = 0xC, 262 IBT_RNR_NAK_960us = 0xD, 263 IBT_RNR_NAK_1280us = 0xE, 264 IBT_RNR_NAK_1920us = 0xF, 265 IBT_RNR_NAK_2560us = 0x10, 266 IBT_RNR_NAK_3840us = 0x11, 267 IBT_RNR_NAK_5120us = 0x12, 268 IBT_RNR_NAK_7680us = 0x13, 269 IBT_RNR_NAK_10ms = 0x14, 270 IBT_RNR_NAK_15ms = 0x15, 271 IBT_RNR_NAK_20ms = 0x16, 272 IBT_RNR_NAK_31ms = 0x17, 273 IBT_RNR_NAK_41ms = 0x18, 274 IBT_RNR_NAK_61ms = 0x19, 275 IBT_RNR_NAK_82ms = 0x1A, 276 IBT_RNR_NAK_123ms = 0x1B, 277 IBT_RNR_NAK_164ms = 0x1C, 278 IBT_RNR_NAK_246ms = 0x1D, 279 IBT_RNR_NAK_328ms = 0x1E, 280 IBT_RNR_NAK_492ms = 0x1F 281 } ibt_rnr_nak_time_t; 282 283 /* 284 * The definition of HCA capabilities etc as a bitfield. 285 */ 286 typedef enum ibt_hca_flags_e { 287 IBT_HCA_NO_FLAGS = 0, 288 289 IBT_HCA_RD = 1 << 0, 290 IBT_HCA_UD_MULTICAST = 1 << 1, 291 IBT_HCA_RAW_MULTICAST = 1 << 2, 292 293 IBT_HCA_ATOMICS_HCA = 1 << 3, 294 IBT_HCA_ATOMICS_GLOBAL = 1 << 4, 295 296 IBT_HCA_RESIZE_CHAN = 1 << 5, /* Is resize supported? */ 297 IBT_HCA_AUTO_PATH_MIG = 1 << 6, /* Is APM supported? */ 298 IBT_HCA_SQD_SQD_PORT = 1 << 7, /* Can change physical port */ 299 /* on transit from SQD to SQD */ 300 IBT_HCA_PKEY_CNTR = 1 << 8, 301 IBT_HCA_QKEY_CNTR = 1 << 9, 302 IBT_HCA_AH_PORT_CHECK = 1 << 10, /* HCA checks AH port match */ 303 /* in UD WRs */ 304 IBT_HCA_PORT_UP = 1 << 11, /* PortActive event supported */ 305 IBT_HCA_INIT_TYPE = 1 << 12, /* InitType supported */ 306 IBT_HCA_SI_GUID = 1 << 13, /* System Image GUID */ 307 /* supported */ 308 IBT_HCA_SHUTDOWN_PORT = 1 << 14, /* ShutdownPort supported */ 309 IBT_HCA_RNR_NAK = 1 << 15, /* RNR-NAK supported for RC */ 310 IBT_HCA_CURRENT_QP_STATE = 1 << 16, /* Does modify_qp support */ 311 /* checking of current state? */ 312 IBT_HCA_SRQ = 1 << 17, /* Shared Receive Queue */ 313 IBT_HCA_RESIZE_SRQ = 1 << 18, /* Is resize SRQ supported? */ 314 IBT_HCA_BASE_MEM_MGT = 1 << 19, /* Base memory mgt supported? */ 315 IBT_HCA_MULT_PAGE_SZ_MR = 1 << 20, /* Support of multiple page */ 316 /* sizes per memory region? */ 317 IBT_HCA_BLOCK_LIST = 1 << 21, /* Block list physical buffer */ 318 /* lists supported? */ 319 IBT_HCA_ZERO_BASED_VA = 1 << 22, /* Zero Based Virtual */ 320 /* Addresses supported? */ 321 IBT_HCA_LOCAL_INVAL_FENCE = 1 << 23, /* Local invalidate fencing? */ 322 IBT_HCA_BASE_QUEUE_MGT = 1 << 24, /* Base Queue Mgt supported? */ 323 IBT_HCA_CKSUM_FULL = 1 << 25, /* Checksum offload supported */ 324 IBT_HCA_MEM_WIN_TYPE_2B = 1 << 26, /* Type 2B memory windows */ 325 IBT_HCA_PHYS_BUF_BLOCK = 1 << 27, /* Block mode phys buf lists */ 326 IBT_HCA_FMR = 1 << 28 /* FMR Support */ 327 } ibt_hca_flags_t; 328 329 /* 330 * The definition of HCA page size capabilities as a bitfield 331 */ 332 typedef enum ibt_page_sizes_e { 333 IBT_PAGE_4K = 0x1 << 2, 334 IBT_PAGE_8K = 0x1 << 3, 335 IBT_PAGE_16K = 0x1 << 4, 336 IBT_PAGE_32K = 0x1 << 5, 337 IBT_PAGE_64K = 0x1 << 6, 338 IBT_PAGE_128K = 0x1 << 7, 339 IBT_PAGE_256K = 0x1 << 8, 340 IBT_PAGE_512K = 0x1 << 9, 341 IBT_PAGE_1M = 0x1 << 10, 342 IBT_PAGE_2M = 0x1 << 11, 343 IBT_PAGE_4M = 0x1 << 12, 344 IBT_PAGE_8M = 0x1 << 13, 345 IBT_PAGE_16M = 0x1 << 14, 346 IBT_PAGE_32M = 0x1 << 15, 347 IBT_PAGE_64M = 0x1 << 16, 348 IBT_PAGE_128M = 0x1 << 17, 349 IBT_PAGE_256M = 0x1 << 18, 350 IBT_PAGE_512M = 0x1 << 19, 351 IBT_PAGE_1G = 0x1 << 20, 352 IBT_PAGE_2G = 0x1 << 21, 353 IBT_PAGE_4G = 0x1 << 22, 354 IBT_PAGE_8G = 0x1 << 23, 355 IBT_PAGE_16G = 0x1 << 24 356 } ibt_page_sizes_t; 357 358 /* 359 * Memory Window Type. 360 */ 361 typedef enum ibt_mem_win_type_e { 362 IBT_MEM_WIN_TYPE_NOT_DEFINED = 0, 363 IBT_MEM_WIN_TYPE_1 = (1 << 0), 364 IBT_MEM_WIN_TYPE_2 = (1 << 1) 365 } ibt_mem_win_type_t; 366 367 /* 368 * HCA attributes. 369 * Contains all HCA static attributes. 370 */ 371 typedef struct ibt_hca_attr_s { 372 ibt_hca_flags_t hca_flags; /* HCA capabilities etc */ 373 374 /* device/version inconsistency w/ NodeInfo and IOControllerProfile */ 375 uint32_t hca_vendor_id:24; /* 24 bit Vendor ID */ 376 uint16_t hca_device_id; 377 uint32_t hca_version_id; 378 379 uint_t hca_max_chans; /* Max Chans supported */ 380 uint_t hca_max_chan_sz; /* Max outstanding WRs on any */ 381 /* channel */ 382 383 uint_t hca_max_sgl; /* Max SGL entries per WR */ 384 385 uint_t hca_max_cq; /* Max num of CQs supported */ 386 uint_t hca_max_cq_sz; /* Max capacity of each CQ */ 387 388 ibt_page_sizes_t hca_page_sz; /* Bit mask of page sizes */ 389 390 uint_t hca_max_memr; /* Max num of HCA mem regions */ 391 ib_memlen_t hca_max_memr_len; /* Largest block, in bytes of */ 392 /* mem that can be registered */ 393 uint_t hca_max_mem_win; /* Max Memory windows in HCA */ 394 395 uint_t hca_max_rsc; /* Max Responder Resources of */ 396 /* this HCA for RDMAR/Atomics */ 397 /* with this HCA as target. */ 398 uint8_t hca_max_rdma_in_chan; /* Max RDMAR/Atomics in per */ 399 /* chan this HCA as target. */ 400 uint8_t hca_max_rdma_out_chan; /* Max RDMA Reads/Atomics out */ 401 /* per channel by this HCA */ 402 uint_t hca_max_ipv6_chan; /* Max IPV6 channels in HCA */ 403 uint_t hca_max_ether_chan; /* Max Ether channels in HCA */ 404 405 uint_t hca_max_mcg_chans; /* Max number of channels */ 406 /* that can join multicast */ 407 /* groups */ 408 uint_t hca_max_mcg; /* Max multicast groups */ 409 uint_t hca_max_chan_per_mcg; /* Max number of channels per */ 410 /* Multicast group in HCA */ 411 412 uint16_t hca_max_partitions; /* Max partitions in HCA */ 413 uint8_t hca_nports; /* Number of physical ports */ 414 ib_guid_t hca_node_guid; /* Node GUID */ 415 416 ib_time_t hca_local_ack_delay; 417 418 uint_t hca_max_port_sgid_tbl_sz; 419 uint16_t hca_max_port_pkey_tbl_sz; 420 uint_t hca_max_pd; /* Max# of Protection Domains */ 421 ib_guid_t hca_si_guid; /* Optional System Image GUID */ 422 uint_t hca_hca_max_ci_priv_sz; 423 uint_t hca_chan_max_ci_priv_sz; 424 uint_t hca_cq_max_ci_priv_sz; 425 uint_t hca_pd_max_ci_priv_sz; 426 uint_t hca_mr_max_ci_priv_sz; 427 uint_t hca_mw_max_ci_priv_sz; 428 uint_t hca_ud_dest_max_ci_priv_sz; 429 uint_t hca_cq_sched_max_ci_priv_sz; 430 uint_t hca_max_ud_dest; 431 uint_t hca_opaque2; 432 uint_t hca_opaque3; 433 uint_t hca_opaque4; 434 uint8_t hca_opaque5; 435 uint8_t hca_opaque6; 436 uint_t hca_opaque7; 437 uint_t hca_opaque8; 438 uint_t hca_max_srqs; /* Max SRQs supported */ 439 uint_t hca_max_srqs_sz; /* Max outstanding WRs on any */ 440 /* SRQ */ 441 uint_t hca_max_srq_sgl; /* Max SGL entries per SRQ WR */ 442 uint_t hca_max_phys_buf_list_sz; 443 size_t hca_block_sz_lo; /* Range of block sizes */ 444 size_t hca_block_sz_hi; /* supported by the HCA */ 445 uint_t hca_max_cq_handlers; 446 ibt_lkey_t hca_reserved_lkey; 447 uint_t hca_max_fmrs; /* Max FMR Supported */ 448 uint_t hca_opaque9; 449 } ibt_hca_attr_t; 450 451 /* 452 * HCA Port link states. 453 */ 454 typedef enum ibt_port_state_e { 455 IBT_PORT_DOWN = 1, 456 IBT_PORT_INIT, 457 IBT_PORT_ARM, 458 IBT_PORT_ACTIVE 459 } ibt_port_state_t; 460 461 /* 462 * HCA Port capabilities as a bitfield. 463 */ 464 typedef enum ibt_port_caps_e { 465 IBT_PORT_CAP_NO_FLAGS = 0, 466 IBT_PORT_CAP_SM = 1 << 0, /* SM port */ 467 IBT_PORT_CAP_SM_DISABLED = 1 << 1, 468 IBT_PORT_CAP_SNMP_TUNNEL = 1 << 2, /* SNMP Tunneling */ 469 IBT_PORT_CAP_DM = 1 << 3, /* DM supported */ 470 IBT_PORT_CAP_VENDOR = 1 << 4 /* Vendor Class */ 471 } ibt_port_caps_t; 472 473 474 /* 475 * HCA port attributes structure definition. The number of ports per HCA 476 * can be found from the "ibt_hca_attr_t" structure. 477 * 478 * p_pkey_tbl is a pointer to an array of ib_pkey_t, members are 479 * accessed as: 480 * hca_portinfo->p_pkey_tbl[i] 481 * 482 * Where 0 <= i < hca_portinfo.p_pkey_tbl_sz 483 * 484 * Similarly p_sgid_tbl is a pointer to an array of ib_gid_t. 485 * 486 * The Query Port function - ibt_query_hca_ports() allocates the memory 487 * required for the ibt_hca_portinfo_t struct as well as the memory 488 * required for the SGID and P_Key tables. The memory is freed by calling 489 * ibt_free_portinfo(). 490 */ 491 typedef struct ibt_hca_portinfo_s { 492 ib_lid_t p_opaque1; /* Base LID of port */ 493 ib_qkey_cntr_t p_qkey_violations; /* Bad Q_Key cnt */ 494 ib_pkey_cntr_t p_pkey_violations; /* Optional bad P_Key cnt */ 495 uint8_t p_sm_sl:4; /* SM Service level */ 496 ib_lid_t p_sm_lid; /* SM LID */ 497 ibt_port_state_t p_linkstate; /* Port state */ 498 uint8_t p_port_num; 499 ib_mtu_t p_mtu; /* Max transfer unit - pkt */ 500 uint8_t p_lmc:3; /* Local mask control */ 501 ib_gid_t *p_sgid_tbl; /* SGID Table */ 502 uint_t p_sgid_tbl_sz; /* Size of SGID table */ 503 uint16_t p_pkey_tbl_sz; /* Size of P_Key table */ 504 uint16_t p_def_pkey_ix; /* default pkey index for TI */ 505 ib_pkey_t *p_pkey_tbl; /* P_Key table */ 506 uint8_t p_max_vl; /* Max num of virtual lanes */ 507 uint8_t p_init_type_reply; /* Optional InitTypeReply */ 508 ib_time_t p_subnet_timeout; /* Max Subnet Timeout */ 509 ibt_port_caps_t p_capabilities; /* Port Capabilities */ 510 uint32_t p_msg_sz; /* Max message size */ 511 } ibt_hca_portinfo_t; 512 513 /* 514 * Modify HCA port attributes flags, specifies which HCA port 515 * attributes to modify. 516 */ 517 typedef enum ibt_port_modify_flags_e { 518 IBT_PORT_NO_FLAGS = 0, 519 520 IBT_PORT_RESET_QKEY = 1 << 0, /* Reset Q_Key violation */ 521 /* counter */ 522 IBT_PORT_RESET_SM = 1 << 1, /* SM */ 523 IBT_PORT_SET_SM = 1 << 2, 524 IBT_PORT_RESET_SNMP = 1 << 3, /* SNMP Tunneling */ 525 IBT_PORT_SET_SNMP = 1 << 4, 526 IBT_PORT_RESET_DEVMGT = 1 << 5, /* Device Management */ 527 IBT_PORT_SET_DEVMGT = 1 << 6, 528 IBT_PORT_RESET_VENDOR = 1 << 7, /* Vendor Class */ 529 IBT_PORT_SET_VENDOR = 1 << 8, 530 IBT_PORT_SHUTDOWN = 1 << 9, /* Shut down the port */ 531 IBT_PORT_SET_INIT_TYPE = 1 << 10 /* InitTypeReply value */ 532 } ibt_port_modify_flags_t; 533 534 /* 535 * Modify HCA port InitType bit definitions, applicable only if 536 * IBT_PORT_SET_INIT_TYPE modify flag (ibt_port_modify_flags_t) is set. 537 */ 538 #define IBT_PINIT_NO_LOAD 0x1 539 #define IBT_PINIT_PRESERVE_CONTENT 0x2 540 #define IBT_PINIT_PRESERVE_PRESENCE 0x4 541 #define IBT_PINIT_NO_RESUSCITATE 0x8 542 543 544 /* 545 * Address vector definition. 546 */ 547 typedef struct ibt_adds_vect_s { 548 ib_gid_t av_dgid; /* IPV6 dest GID in GRH */ 549 ib_gid_t av_sgid; /* SGID */ 550 ibt_srate_t av_srate; /* Max static rate */ 551 uint8_t av_srvl:4; /* Service level in LRH */ 552 uint_t av_flow:20; /* 20 bit Flow Label */ 553 uint8_t av_tclass; /* Traffic Class */ 554 uint8_t av_hop; /* Hop Limit */ 555 uint8_t av_port_num; /* Port number for UD */ 556 boolean_t av_opaque1; 557 ib_lid_t av_opaque2; 558 ib_path_bits_t av_opaque3; 559 uint32_t av_opaque4; 560 } ibt_adds_vect_t; 561 562 typedef struct ibt_cep_path_s { 563 ibt_adds_vect_t cep_adds_vect; /* Address Vector */ 564 uint16_t cep_pkey_ix; /* P_Key Index */ 565 uint8_t cep_hca_port_num; /* Port number for connected */ 566 /* channels. A value of 0 */ 567 /* indicates an invalid path */ 568 ib_time_t cep_cm_opaque1; 569 } ibt_cep_path_t; 570 571 /* 572 * Channel Migration State. 573 */ 574 typedef enum ibt_cep_cmstate_e { 575 IBT_STATE_NOT_SUPPORTED = 0, 576 IBT_STATE_MIGRATED = 1, 577 IBT_STATE_REARMED = 2, 578 IBT_STATE_ARMED = 3 579 } ibt_cep_cmstate_t; 580 581 /* 582 * Transport service type 583 * 584 * NOTE: this was converted from an enum to a uint8_t to save space. 585 */ 586 typedef uint8_t ibt_tran_srv_t; 587 588 #define IBT_RC_SRV 0 589 #define IBT_UC_SRV 1 590 #define IBT_RD_SRV 2 591 #define IBT_UD_SRV 3 592 #define IBT_RAWIP_SRV 4 593 #define IBT_RAWETHER_SRV 5 594 595 /* 596 * Channel (QP/EEC) state definitions. 597 */ 598 typedef enum ibt_cep_state_e { 599 IBT_STATE_RESET = 0, /* Reset */ 600 IBT_STATE_INIT, /* Initialized */ 601 IBT_STATE_RTR, /* Ready to Receive */ 602 IBT_STATE_RTS, /* Ready to Send */ 603 IBT_STATE_SQD, /* Send Queue Drained */ 604 IBT_STATE_SQE, /* Send Queue Error */ 605 IBT_STATE_ERROR, /* Error */ 606 IBT_STATE_SQDRAIN, /* Send Queue Draining */ 607 IBT_STATE_NUM /* Number of states */ 608 } ibt_cep_state_t; 609 610 611 /* 612 * Channel Attribute flags. 613 */ 614 typedef enum ibt_attr_flags_e { 615 IBT_ALL_SIGNALED = 0, /* All sends signaled */ 616 IBT_WR_SIGNALED = 1, /* Signaled on a WR basis */ 617 IBT_FAST_REG_RES_LKEY = (1 << 1) 618 } ibt_attr_flags_t; 619 620 /* 621 * Channel End Point (CEP) Control Flags. 622 */ 623 typedef enum ibt_cep_flags_e { 624 IBT_CEP_NO_FLAGS = 0, /* Enable Nothing */ 625 IBT_CEP_RDMA_RD = (1 << 0), /* Enable incoming RDMA RD's */ 626 /* RC & RD only */ 627 IBT_CEP_RDMA_WR = (1 << 1), /* Enable incoming RDMA WR's */ 628 /* RC & RD only */ 629 IBT_CEP_ATOMIC = (1 << 2) /* Enable incoming Atomics, */ 630 /* RC & RD only */ 631 } ibt_cep_flags_t; 632 633 /* 634 * Channel Modify Flags 635 */ 636 typedef enum ibt_cep_modify_flags_e { 637 IBT_CEP_SET_NOTHING = 0, 638 IBT_CEP_SET_SQ_SIZE = (1 << 1), 639 IBT_CEP_SET_RQ_SIZE = (1 << 2), 640 641 IBT_CEP_SET_RDMA_R = (1 << 3), 642 IBT_CEP_SET_RDMA_W = (1 << 4), 643 IBT_CEP_SET_ATOMIC = (1 << 5), 644 645 IBT_CEP_SET_ALT_PATH = (1 << 6), /* Alternate Path */ 646 647 IBT_CEP_SET_ADDS_VECT = (1 << 7), 648 IBT_CEP_SET_PORT = (1 << 8), 649 IBT_CEP_SET_OPAQUE5 = (1 << 9), 650 IBT_CEP_SET_RETRY = (1 << 10), 651 IBT_CEP_SET_RNR_NAK_RETRY = (1 << 11), 652 IBT_CEP_SET_MIN_RNR_NAK = (1 << 12), 653 654 IBT_CEP_SET_QKEY = (1 << 13), 655 IBT_CEP_SET_RDMARA_OUT = (1 << 14), 656 IBT_CEP_SET_RDMARA_IN = (1 << 15), 657 658 IBT_CEP_SET_OPAQUE1 = (1 << 16), 659 IBT_CEP_SET_OPAQUE2 = (1 << 17), 660 IBT_CEP_SET_OPAQUE3 = (1 << 18), 661 IBT_CEP_SET_OPAQUE4 = (1 << 19), 662 IBT_CEP_SET_SQD_EVENT = (1 << 20), 663 IBT_CEP_SET_OPAQUE6 = (1 << 21), 664 IBT_CEP_SET_OPAQUE7 = (1 << 22), 665 IBT_CEP_SET_OPAQUE8 = (1 << 23) 666 } ibt_cep_modify_flags_t; 667 668 /* 669 * CQ notify types. 670 */ 671 typedef enum ibt_cq_notify_flags_e { 672 IBT_NEXT_COMPLETION = 1, 673 IBT_NEXT_SOLICITED = 2 674 } ibt_cq_notify_flags_t; 675 676 /* 677 * CQ types shared across TI and CI. 678 */ 679 typedef enum ibt_cq_flags_e { 680 IBT_CQ_NO_FLAGS = 0, 681 IBT_CQ_HANDLER_IN_THREAD = 1 << 0, /* A thread calls the */ 682 /* CQ handler */ 683 IBT_CQ_USER_MAP = 1 << 1, 684 IBT_CQ_DEFER_ALLOC = 1 << 2 685 } ibt_cq_flags_t; 686 687 /* 688 * CQ types shared across TI and CI. 689 */ 690 typedef enum ibt_cq_sched_flags_e { 691 IBT_CQS_NO_FLAGS = 0, 692 IBT_CQS_WARM_CACHE = 1 << 0, /* run on same CPU */ 693 IBT_CQS_AFFINITY = 1 << 1, 694 IBT_CQS_SCHED_GROUP = 1 << 2, 695 IBT_CQS_USER_MAP = 1 << 3, 696 IBT_CQS_DEFER_ALLOC = 1 << 4 697 } ibt_cq_sched_flags_t; 698 699 /* 700 * Attributes when creating a Completion Queue. 701 * 702 * Note: 703 * The IBT_CQ_HANDLER_IN_THREAD cq_flags bit should be ignored by the CI. 704 */ 705 typedef struct ibt_cq_attr_s { 706 uint_t cq_size; 707 ibt_sched_hdl_t cq_sched; /* 0 = no hint, */ 708 /* other = cq_sched value */ 709 ibt_cq_flags_t cq_flags; 710 } ibt_cq_attr_t; 711 712 /* 713 * Memory Management 714 */ 715 716 /* Memory management flags */ 717 typedef enum ibt_mr_flags_e { 718 IBT_MR_SLEEP = 0, 719 IBT_MR_NOSLEEP = (1 << 1), 720 IBT_MR_NONCOHERENT = (1 << 2), 721 IBT_MR_PHYS_IOVA = (1 << 3), /* ibt_(re)register_buf */ 722 723 /* Access control flags */ 724 IBT_MR_ENABLE_WINDOW_BIND = (1 << 4), 725 IBT_MR_ENABLE_LOCAL_WRITE = (1 << 5), 726 IBT_MR_ENABLE_REMOTE_READ = (1 << 6), 727 IBT_MR_ENABLE_REMOTE_WRITE = (1 << 7), 728 IBT_MR_ENABLE_REMOTE_ATOMIC = (1 << 8), 729 730 /* Reregister flags */ 731 IBT_MR_CHANGE_TRANSLATION = (1 << 9), 732 IBT_MR_CHANGE_ACCESS = (1 << 10), 733 IBT_MR_CHANGE_PD = (1 << 11), 734 735 /* Additional registration flags */ 736 IBT_MR_ZBVA = (1 << 12), 737 738 /* Additional physical registration flags */ 739 IBT_MR_CONSUMER_KEY = (1 << 13) /* Consumer owns key */ 740 /* portion of keys */ 741 } ibt_mr_flags_t; 742 743 744 /* Memory Region attribute flags */ 745 typedef enum ibt_mr_attr_flags_e { 746 /* Access control flags */ 747 IBT_MR_WINDOW_BIND = (1 << 0), 748 IBT_MR_LOCAL_WRITE = (1 << 1), 749 IBT_MR_REMOTE_READ = (1 << 2), 750 IBT_MR_REMOTE_WRITE = (1 << 3), 751 IBT_MR_REMOTE_ATOMIC = (1 << 4), 752 IBT_MR_ZERO_BASED_VA = (1 << 5), 753 IBT_MR_CONSUMER_OWNED_KEY = (1 << 6), 754 IBT_MR_SHARED = (1 << 7), 755 IBT_MR_FMR = (1 << 8) 756 } ibt_mr_attr_flags_t; 757 758 /* Memory region physical descriptor. */ 759 typedef struct ibt_phys_buf_s { 760 union { 761 uint64_t _p_ll; /* 64 bit DMA address */ 762 uint32_t _p_la[2]; /* 2 x 32 bit address */ 763 } _phys_buf; 764 size_t p_size; 765 } ibt_phys_buf_t; 766 767 #define p_laddr _phys_buf._p_ll 768 #ifdef _LONG_LONG_HTOL 769 #define p_notused _phys_buf._p_la[0] 770 #define p_addr _phys_buf._p_la[1] 771 #else 772 #define p_addr _phys_buf._p_la[0] 773 #define p_notused _phys_buf._p_la[1] 774 #endif 775 776 777 /* Memory region descriptor. */ 778 typedef struct ibt_mr_desc_s { 779 ib_vaddr_t md_vaddr; /* IB virtual adds of memory */ 780 ibt_lkey_t md_lkey; 781 ibt_rkey_t md_rkey; 782 boolean_t md_sync_required; 783 } ibt_mr_desc_t; 784 785 /* Physical Memory region descriptor. */ 786 typedef struct ibt_pmr_desc_s { 787 ib_vaddr_t pmd_iova; /* Returned I/O Virtual Address */ 788 ibt_lkey_t pmd_lkey; 789 ibt_rkey_t pmd_rkey; 790 uint_t pmd_phys_buf_list_sz; /* Allocated Phys buf sz */ 791 boolean_t pmd_sync_required; 792 } ibt_pmr_desc_t; 793 794 /* Memory region protection bounds. */ 795 typedef struct ibt_mr_prot_bounds_s { 796 ib_vaddr_t pb_addr; /* Beginning address */ 797 size_t pb_len; /* Length of protected region */ 798 } ibt_mr_prot_bounds_t; 799 800 /* Memory Region (Re)Register attributes */ 801 typedef struct ibt_mr_attr_s { 802 ib_vaddr_t mr_vaddr; /* Virtual address to register */ 803 ib_memlen_t mr_len; /* Length of region to register */ 804 struct as *mr_as; /* A pointer to an address space */ 805 /* structure. This parameter should */ 806 /* be set to NULL, which implies */ 807 /* kernel address space. */ 808 ibt_mr_flags_t mr_flags; 809 } ibt_mr_attr_t; 810 811 /* Physical Memory Region (Re)Register */ 812 typedef struct ibt_pmr_attr_s { 813 ib_vaddr_t pmr_iova; /* I/O virtual address requested by */ 814 /* client for the first byte of the */ 815 /* region */ 816 ib_memlen_t pmr_len; /* Length of region to register */ 817 ib_memlen_t pmr_offset; /* Offset of the regions starting */ 818 /* IOVA within the 1st physical */ 819 /* buffer */ 820 ibt_mr_flags_t pmr_flags; 821 ibt_lkey_t pmr_lkey; /* Reregister only */ 822 ibt_rkey_t pmr_rkey; /* Reregister only */ 823 uint8_t pmr_key; /* Key to use on new Lkey & Rkey */ 824 uint_t pmr_num_buf; /* Num of entries in the pmr_buf_list */ 825 size_t pmr_buf_sz; 826 ibt_phys_buf_t *pmr_buf_list; /* List of physical buffers accessed */ 827 /* as an array */ 828 ibt_ma_hdl_t pmr_ma; /* Memory handle used to obtain the */ 829 /* pmr_buf_list */ 830 } ibt_pmr_attr_t; 831 832 833 /* 834 * Memory Region (Re)Register attributes - used by ibt_register_shared_mr(), 835 * ibt_register_buf() and ibt_reregister_buf(). 836 */ 837 typedef struct ibt_smr_attr_s { 838 ib_vaddr_t mr_vaddr; 839 ibt_mr_flags_t mr_flags; 840 uint8_t mr_key; /* Only for physical */ 841 /* ibt_(Re)register_buf() */ 842 ibt_lkey_t mr_lkey; /* Only for physical */ 843 ibt_rkey_t mr_rkey; /* ibt_Reregister_buf() */ 844 } ibt_smr_attr_t; 845 846 /* 847 * key states. 848 */ 849 typedef enum ibt_key_state_e { 850 IBT_KEY_INVALID = 0, 851 IBT_KEY_FREE, 852 IBT_KEY_VALID 853 } ibt_key_state_t; 854 855 /* Memory region query attributes */ 856 typedef struct ibt_mr_query_attr_s { 857 ibt_lkey_t mr_lkey; 858 ibt_rkey_t mr_rkey; 859 ibt_mr_prot_bounds_t mr_lbounds; /* Actual local CI protection */ 860 /* bounds */ 861 ibt_mr_prot_bounds_t mr_rbounds; /* Actual remote CI */ 862 /* protection bounds */ 863 ibt_mr_attr_flags_t mr_attr_flags; /* Access rights etc. */ 864 ibt_pd_hdl_t mr_pd; /* Protection domain */ 865 boolean_t mr_sync_required; 866 ibt_key_state_t mr_lkey_state; 867 uint_t mr_phys_buf_list_sz; 868 } ibt_mr_query_attr_t; 869 870 /* Memory window query attributes */ 871 typedef struct ibt_mw_query_attr_s { 872 ibt_pd_hdl_t mw_pd; 873 ibt_mem_win_type_t mw_type; 874 ibt_rkey_t mw_rkey; 875 ibt_key_state_t mw_state; 876 } ibt_mw_query_attr_t; 877 878 879 /* Memory Region Sync Flags. */ 880 #define IBT_SYNC_READ 0x1 /* Make memory changes visible to incoming */ 881 /* RDMA reads */ 882 883 #define IBT_SYNC_WRITE 0x2 /* Make the affects of an incoming RDMA write */ 884 /* visible to the consumer */ 885 886 /* Memory region sync args */ 887 typedef struct ibt_mr_sync_s { 888 ibt_mr_hdl_t ms_handle; 889 ib_vaddr_t ms_vaddr; 890 ib_memlen_t ms_len; 891 uint32_t ms_flags; /* IBT_SYNC_READ or IBT_SYNC_WRITE */ 892 } ibt_mr_sync_t; 893 894 /* 895 * Flags for Virtual Address to HCA Physical Address translation. 896 */ 897 typedef enum ibt_va_flags_e { 898 IBT_VA_SLEEP = 0, 899 IBT_VA_NOSLEEP = (1 << 0), 900 IBT_VA_NONCOHERENT = (1 << 1), 901 IBT_VA_FMR = (1 << 2), 902 IBT_VA_BLOCK_MODE = (1 << 3), 903 IBT_VA_BUF = (1 << 4) 904 } ibt_va_flags_t; 905 906 907 /* Address Translation parameters */ 908 typedef struct ibt_va_attr_s { 909 ib_vaddr_t va_vaddr; /* Virtual address to register */ 910 ib_memlen_t va_len; /* Length of region to register */ 911 struct as *va_as; /* A pointer to an address space */ 912 /* structure. */ 913 size_t va_phys_buf_min; 914 size_t va_phys_buf_max; 915 ibt_va_flags_t va_flags; 916 struct buf *va_buf; 917 } ibt_va_attr_t; 918 919 920 /* 921 * Fast Memory Registration (FMR) support. 922 */ 923 924 /* FMR flush function handler. */ 925 typedef void (*ibt_fmr_flush_handler_t)(ibt_fmr_pool_hdl_t fmr_pool, 926 void *fmr_func_arg); 927 928 /* FMR Pool create attributes. */ 929 typedef struct ibt_fmr_pool_attr_s { 930 uint_t fmr_max_pages_per_fmr; 931 uint_t fmr_pool_size; 932 uint_t fmr_dirty_watermark; 933 size_t fmr_page_sz; 934 boolean_t fmr_cache; 935 ibt_mr_flags_t fmr_flags; 936 ibt_fmr_flush_handler_t fmr_func_hdlr; 937 void *fmr_func_arg; 938 } ibt_fmr_pool_attr_t; 939 940 941 /* 942 * WORK REQUEST AND WORK REQUEST COMPLETION DEFINITIONS. 943 */ 944 945 /* 946 * Work Request and Work Request Completion types - These types are used 947 * to indicate the type of work requests posted to a work queue 948 * or the type of completion received. Immediate Data is indicated via 949 * ibt_wr_flags_t or ibt_wc_flags_t. 950 * 951 * IBT_WRC_RECV and IBT_WRC_RECV_RDMAWI are only used as opcodes in the 952 * work completions. 953 * 954 * NOTE: this was converted from an enum to a uint8_t to save space. 955 */ 956 typedef uint8_t ibt_wrc_opcode_t; 957 958 #define IBT_WRC_SEND 1 /* Send */ 959 #define IBT_WRC_RDMAR 2 /* RDMA Read */ 960 #define IBT_WRC_RDMAW 3 /* RDMA Write */ 961 #define IBT_WRC_CSWAP 4 /* Compare & Swap Atomic */ 962 #define IBT_WRC_FADD 5 /* Fetch & Add Atomic */ 963 #define IBT_WRC_BIND 6 /* Bind Memory Window */ 964 #define IBT_WRC_RECV 7 /* Receive */ 965 #define IBT_WRC_RECV_RDMAWI 8 /* Received RDMA Write w/ Immediate */ 966 #define IBT_WRC_FAST_REG_PMR 9 /* Fast Register Physical mem region */ 967 #define IBT_WRC_LOCAL_INVALIDATE 10 968 969 970 /* 971 * Work Request Completion flags - These flags indicate what type 972 * of data is present in the Work Request Completion structure 973 */ 974 typedef uint8_t ibt_wc_flags_t; 975 976 #define IBT_WC_NO_FLAGS 0 977 #define IBT_WC_GRH_PRESENT (1 << 0) 978 #define IBT_WC_IMMED_DATA_PRESENT (1 << 1) 979 #define IBT_WC_RKEY_INVALIDATED (1 << 2) 980 #define IBT_WC_CKSUM_OK (1 << 3) 981 982 983 /* 984 * Work Request Completion - This structure encapsulates the information 985 * necessary to define a work request completion. 986 */ 987 typedef struct ibt_wc_s { 988 ibt_wrid_t wc_id; /* Work Request Id */ 989 uint64_t wc_fma_ena; /* fault management err data */ 990 ib_msglen_t wc_bytes_xfer; /* Number of Bytes */ 991 /* Transferred */ 992 ibt_wc_flags_t wc_flags; /* WR Completion Flags */ 993 ibt_wrc_opcode_t wc_type; /* Operation Type */ 994 uint16_t wc_cksum; /* payload checksum */ 995 ibt_immed_t wc_immed_data; /* Immediate Data */ 996 uint32_t wc_freed_rc; /* Freed Resource Count */ 997 ibt_wc_status_t wc_status; /* Completion Status */ 998 uint8_t wc_sl:4; /* Remote SL */ 999 uint16_t wc_ethertype; /* Ethertype Field - RE */ 1000 ib_lid_t wc_opaque1; 1001 uint16_t wc_opaque2; 1002 ib_qpn_t wc_qpn; /* Source QPN Datagram only */ 1003 ib_eecn_t wc_opaque3; 1004 ib_qpn_t wc_local_qpn; 1005 ibt_rkey_t wc_rkey; 1006 ib_path_bits_t wc_opaque4; 1007 } ibt_wc_t; 1008 1009 1010 /* 1011 * WR Flags. Common for both RC and UD 1012 * 1013 * NOTE: this was converted from an enum to a uint8_t to save space. 1014 */ 1015 typedef uint8_t ibt_wr_flags_t; 1016 1017 #define IBT_WR_NO_FLAGS 0 1018 #define IBT_WR_SEND_IMMED (1 << 0) /* Immediate Data Indicator */ 1019 #define IBT_WR_SEND_SIGNAL (1 << 1) /* Signaled, if set */ 1020 #define IBT_WR_SEND_FENCE (1 << 2) /* Fence Indicator */ 1021 #define IBT_WR_SEND_SOLICIT (1 << 3) /* Solicited Event Indicator */ 1022 #define IBT_WR_SEND_REMOTE_INVAL (1 << 4) /* Remote Invalidate */ 1023 #define IBT_WR_SEND_CKSUM (1 << 5) /* Checksum offload Indicator */ 1024 1025 /* 1026 * Access control flags for Bind Memory Window operation, 1027 * applicable for RC/UC/RD only. 1028 * 1029 * If IBT_WR_BIND_WRITE or IBT_WR_BIND_ATOMIC is desired then 1030 * it is required that Memory Region should have Local Write Access. 1031 */ 1032 typedef enum ibt_bind_flags_e { 1033 IBT_WR_BIND_READ = (1 << 0), /* enable remote read */ 1034 IBT_WR_BIND_WRITE = (1 << 1), /* enable remote write */ 1035 IBT_WR_BIND_ATOMIC = (1 << 2), /* enable remote atomics */ 1036 IBT_WR_BIND_ZBVA = (1 << 3) /* Zero Based Virtual Address */ 1037 } ibt_bind_flags_t; 1038 1039 /* 1040 * Data Segment for scatter-gather list 1041 * 1042 * SGL consists of an array of data segments and the length of the SGL. 1043 */ 1044 typedef struct ibt_wr_ds_s { 1045 ib_vaddr_t ds_va; /* Virtual Address */ 1046 ibt_lkey_t ds_key; /* L_Key */ 1047 ib_msglen_t ds_len; /* Length of DS */ 1048 } ibt_wr_ds_t; 1049 1050 /* 1051 * Bind Memory Window WR 1052 * 1053 * WR ID from ibt_send_wr_t applies here too, SWG_0038 errata. 1054 */ 1055 typedef struct ibt_wr_bind_s { 1056 ibt_bind_flags_t bind_flags; 1057 ibt_rkey_t bind_rkey; /* Mem Window's R_key */ 1058 ibt_lkey_t bind_lkey; /* Mem Region's L_Key */ 1059 ibt_rkey_t bind_rkey_out; /* OUT: new R_Key */ 1060 ibt_mr_hdl_t bind_ibt_mr_hdl; /* Mem Region handle */ 1061 ibt_mw_hdl_t bind_ibt_mw_hdl; /* Mem Window handle */ 1062 ib_vaddr_t bind_va; /* Virtual Address */ 1063 ib_memlen_t bind_len; /* Length of Window */ 1064 } ibt_wr_bind_t; 1065 1066 /* 1067 * Atomic WR 1068 * 1069 * Operation type (compare & swap or fetch & add) in ibt_wrc_opcode_t. 1070 * 1071 * A copy of the original contents of the remote memory will be stored 1072 * in the local data segment described by wr_sgl within ibt_send_wr_t, 1073 * and wr_nds should be set to 1. 1074 * 1075 * Atomic operation operands: 1076 * Compare & Swap Operation: 1077 * atom_arg1 - Compare Operand 1078 * atom_arg2 - Swap Operand 1079 * 1080 * Fetch & Add Operation: 1081 * atom_arg1 - Add Operand 1082 * atom_arg2 - ignored 1083 */ 1084 typedef struct ibt_wr_atomic_s { 1085 ib_vaddr_t atom_raddr; /* Remote address. */ 1086 ibt_atom_arg_t atom_arg1; /* operand #1 */ 1087 ibt_atom_arg_t atom_arg2; /* operand #2 */ 1088 ibt_rkey_t atom_rkey; /* R_Key. */ 1089 } ibt_wr_atomic_t; 1090 1091 /* 1092 * RDMA WR 1093 * Immediate Data indicator in ibt_wr_flags_t. 1094 */ 1095 typedef struct ibt_wr_rdma_s { 1096 ib_vaddr_t rdma_raddr; /* Remote address. */ 1097 ibt_rkey_t rdma_rkey; /* R_Key. */ 1098 ibt_immed_t rdma_immed; /* Immediate Data */ 1099 } ibt_wr_rdma_t; 1100 1101 /* 1102 * Fast Register Physical Memory Region Work Request. 1103 */ 1104 typedef struct ibt_wr_reg_pmr_s { 1105 ib_vaddr_t pmr_iova; /* I/O virtual address requested by */ 1106 /* client for the first byte of the */ 1107 /* region */ 1108 ib_memlen_t pmr_len; /* Length of region to register */ 1109 ib_memlen_t pmr_offset; /* Offset of the regions starting */ 1110 /* IOVA within the 1st physical */ 1111 /* buffer */ 1112 ibt_mr_hdl_t pmr_mr_hdl; 1113 ibt_phys_buf_t *pmr_buf_list; /* List of physical buffers accessed */ 1114 /* as an array */ 1115 uint_t pmr_num_buf; /* Num of entries in the pmr_buf_list */ 1116 ibt_lkey_t pmr_lkey; 1117 ibt_rkey_t pmr_rkey; 1118 ibt_mr_flags_t pmr_flags; 1119 uint8_t pmr_key; /* Key to use on new Lkey & Rkey */ 1120 } ibt_wr_reg_pmr_t; 1121 1122 /* 1123 * Local Invalidate. 1124 */ 1125 typedef struct ibt_wr_li_s { 1126 ibt_mr_hdl_t li_mr_hdl; /* Null for MW invalidates */ 1127 ibt_mw_hdl_t li_mw_hdl; /* Null for MR invalidates */ 1128 ibt_lkey_t li_lkey; /* Ignore for MW invalidates */ 1129 ibt_rkey_t li_rkey; 1130 } ibt_wr_li_t; 1131 1132 /* 1133 * Reserved For Future Use. 1134 * Raw IPv6 Send WR 1135 */ 1136 typedef struct ibt_wr_ripv6_s { 1137 ib_lid_t rip_dlid; /* DLID */ 1138 ib_path_bits_t rip_slid_bits; /* SLID path bits, SWG_0033 errata */ 1139 uint8_t rip_sl:4; /* SL */ 1140 ibt_srate_t rip_rate; /* Max Static Rate, SWG_0007 errata */ 1141 } ibt_wr_ripv6_t; 1142 1143 /* 1144 * Reserved For Future Use. 1145 * Raw Ethertype Send WR 1146 */ 1147 typedef struct ibt_wr_reth_s { 1148 ib_ethertype_t reth_type; /* Ethertype */ 1149 ib_lid_t reth_dlid; /* DLID */ 1150 ib_path_bits_t reth_slid_bits; /* SLID path bits, SWG_0033 errata */ 1151 uint8_t reth_sl:4; /* SL */ 1152 ibt_srate_t reth_rate; /* Max Static Rate, SWG_0007 errata */ 1153 } ibt_wr_reth_t; 1154 1155 /* 1156 * Reserved For future Use. 1157 * RD Send WR, Operation type in ibt_wrc_opcode_t. 1158 */ 1159 typedef struct ibt_wr_rd_s { 1160 ibt_rd_dest_hdl_t rdwr_dest_hdl; 1161 union { 1162 ibt_immed_t send_immed; /* IBT_WRC_SEND */ 1163 ibt_wr_rdma_t rdma; /* IBT_WRC_RDMAR */ 1164 /* IBT_WRC_RDMAW */ 1165 ibt_wr_li_t *li; /* IBT_WRC_LOCAL_INVALIDATE */ 1166 ibt_wr_atomic_t *atomic; /* IBT_WRC_FADD */ 1167 /* IBT_WRC_CSWAP */ 1168 ibt_wr_bind_t *bind; /* IBT_WRC_BIND */ 1169 ibt_wr_reg_pmr_t *reg_pmr; /* IBT_WRC_FAST_REG_PMR */ 1170 } rdwr; 1171 } ibt_wr_rd_t; 1172 1173 /* 1174 * Reserved For Future Use. 1175 * UC Send WR, Operation type in ibt_wrc_opcode_t, the only valid 1176 * ones are: 1177 * IBT_WRC_SEND 1178 * IBT_WRC_RDMAW 1179 * IBT_WRC_BIND 1180 */ 1181 typedef struct ibt_wr_uc_s { 1182 union { 1183 ibt_immed_t send_immed; /* IBT_WRC_SEND */ 1184 ibt_wr_rdma_t rdma; /* IBT_WRC_RDMAW */ 1185 ibt_wr_li_t *li; /* IBT_WRC_LOCAL_INVALIDATE */ 1186 ibt_wr_bind_t *bind; /* IBT_WRC_BIND */ 1187 ibt_wr_reg_pmr_t *reg_pmr; /* IBT_WRC_FAST_REG_PMR */ 1188 } ucwr; 1189 } ibt_wr_uc_t; 1190 1191 /* 1192 * RC Send WR, Operation type in ibt_wrc_opcode_t. 1193 */ 1194 typedef struct ibt_wr_rc_s { 1195 union { 1196 ibt_immed_t send_immed; /* IBT_WRC_SEND w/ immediate */ 1197 ibt_rkey_t send_inval; /* IBT_WRC_SEND w/ invalidate */ 1198 ibt_wr_rdma_t rdma; /* IBT_WRC_RDMAR */ 1199 /* IBT_WRC_RDMAW */ 1200 ibt_wr_li_t *li; /* IBT_WRC_LOCAL_INVALIDATE */ 1201 ibt_wr_atomic_t *atomic; /* IBT_WRC_CSWAP */ 1202 /* IBT_WRC_FADD */ 1203 ibt_wr_bind_t *bind; /* IBT_WRC_BIND */ 1204 ibt_wr_reg_pmr_t *reg_pmr; /* IBT_WRC_FAST_REG_PMR */ 1205 } rcwr; 1206 } ibt_wr_rc_t; 1207 1208 /* 1209 * UD Send WR, the only valid Operation is IBT_WRC_SEND. 1210 */ 1211 typedef struct ibt_wr_ud_s { 1212 ibt_immed_t udwr_immed; 1213 ibt_ud_dest_hdl_t udwr_dest; 1214 } ibt_wr_ud_t; 1215 1216 /* 1217 * Send Work Request (WR) attributes structure. 1218 * 1219 * Operation type in ibt_wrc_opcode_t. 1220 * Immediate Data indicator in ibt_wr_flags_t. 1221 */ 1222 typedef struct ibt_send_wr_s { 1223 ibt_wrid_t wr_id; /* WR ID */ 1224 ibt_wr_flags_t wr_flags; /* Work Request Flags. */ 1225 ibt_tran_srv_t wr_trans; /* Transport Type. */ 1226 ibt_wrc_opcode_t wr_opcode; /* Operation Type. */ 1227 uint8_t wr_rsvd; /* maybe later */ 1228 uint32_t wr_nds; /* Number of data segments */ 1229 /* pointed to by wr_sgl */ 1230 ibt_wr_ds_t *wr_sgl; /* SGL */ 1231 union { 1232 ibt_wr_ud_t ud; 1233 ibt_wr_rc_t rc; 1234 ibt_wr_rd_t rd; /* Reserved For Future Use */ 1235 ibt_wr_uc_t uc; /* Reserved For Future Use */ 1236 ibt_wr_reth_t reth; /* Reserved For Future Use */ 1237 ibt_wr_ripv6_t ripv6; /* Reserved For Future Use */ 1238 } wr; /* operation specific */ 1239 } ibt_send_wr_t; 1240 1241 /* 1242 * Receive Work Request (WR) attributes structure. 1243 */ 1244 typedef struct ibt_recv_wr_s { 1245 ibt_wrid_t wr_id; /* WR ID */ 1246 uint32_t wr_nds; /* number of data segments */ 1247 /* pointed to by wr_sgl */ 1248 ibt_wr_ds_t *wr_sgl; /* SGL */ 1249 } ibt_recv_wr_t; 1250 1251 1252 /* 1253 * Asynchronous Events and Errors. 1254 * 1255 * The following codes are not used in calls to ibc_async_handler, but 1256 * are used by IBTL to inform IBT clients of a significant event. 1257 * 1258 * IBT_HCA_ATTACH_EVENT - New HCA available. 1259 * IBT_HCA_DETACH_EVENT - HCA is requesting not to be used. 1260 * 1261 * ERRORs on a channel indicate that the channel has entered error state. 1262 * EVENTs on a channel indicate that the channel has not changed state. 1263 * 1264 */ 1265 typedef enum ibt_async_code_e { 1266 IBT_EVENT_PATH_MIGRATED = 0x000001, 1267 IBT_EVENT_SQD = 0x000002, 1268 IBT_EVENT_COM_EST = 0x000004, 1269 IBT_ERROR_CATASTROPHIC_CHAN = 0x000008, 1270 IBT_ERROR_INVALID_REQUEST_CHAN = 0x000010, 1271 IBT_ERROR_ACCESS_VIOLATION_CHAN = 0x000020, 1272 IBT_ERROR_PATH_MIGRATE_REQ = 0x000040, 1273 1274 IBT_ERROR_CQ = 0x000080, 1275 1276 IBT_EVENT_PORT_UP = 0x000100, 1277 IBT_ERROR_PORT_DOWN = 0x000200, 1278 IBT_ERROR_LOCAL_CATASTROPHIC = 0x000400, 1279 1280 IBT_HCA_ATTACH_EVENT = 0x000800, 1281 IBT_HCA_DETACH_EVENT = 0x001000, 1282 IBT_ASYNC_OPAQUE1 = 0x002000, 1283 IBT_ASYNC_OPAQUE2 = 0x004000, 1284 IBT_ASYNC_OPAQUE3 = 0x008000, 1285 IBT_ASYNC_OPAQUE4 = 0x010000, 1286 IBT_EVENT_LIMIT_REACHED_SRQ = 0x020000, 1287 IBT_EVENT_EMPTY_CHAN = 0x040000, 1288 IBT_ERROR_CATASTROPHIC_SRQ = 0x080000 1289 } ibt_async_code_t; 1290 1291 1292 /* 1293 * ibt_ci_data_in() and ibt_ci_data_out() flags. 1294 */ 1295 typedef enum ibt_ci_data_flags_e { 1296 IBT_CI_NO_FLAGS = 0, 1297 IBT_CI_COMPLETE_ALLOC = (1 << 0) 1298 } ibt_ci_data_flags_t; 1299 1300 /* 1301 * Used by ibt_ci_data_in() and ibt_ci_data_out() identifies the type of handle 1302 * mapping data is being obtained for. 1303 */ 1304 typedef enum ibt_object_type_e { 1305 IBT_HDL_HCA = 1, 1306 IBT_HDL_CHANNEL, 1307 IBT_HDL_CQ, 1308 IBT_HDL_PD, 1309 IBT_HDL_MR, 1310 IBT_HDL_MW, 1311 IBT_HDL_UD_DEST, 1312 IBT_HDL_SCHED, 1313 IBT_HDL_OPAQUE1, 1314 IBT_HDL_OPAQUE2, 1315 IBT_HDL_SRQ 1316 } ibt_object_type_t; 1317 1318 /* 1319 * Memory error handler data structures; code, and payload data. 1320 */ 1321 typedef enum ibt_mem_code_s { 1322 IBT_MEM_AREA = 0x1, 1323 IBT_MEM_REGION = 0x2 1324 } ibt_mem_code_t; 1325 1326 typedef struct ibt_mem_data_s { 1327 uint64_t ev_fma_ena; /* FMA Error data */ 1328 ibt_mr_hdl_t ev_mr_hdl; /* MR handle */ 1329 ibt_ma_hdl_t ev_ma_hdl; /* MA handle */ 1330 } ibt_mem_data_t; 1331 1332 /* 1333 * Special case failure type. 1334 */ 1335 typedef enum ibt_failure_type_e { 1336 IBT_FAILURE_STANDARD = 0, 1337 IBT_FAILURE_CI, 1338 IBT_FAILURE_IBMF, 1339 IBT_FAILURE_IBTL, 1340 IBT_FAILURE_IBCM, 1341 IBT_FAILURE_IBDM, 1342 IBT_FAILURE_IBSM 1343 } ibt_failure_type_t; 1344 1345 /* 1346 * RDMA IP CM service Annex definitions 1347 */ 1348 typedef struct ibt_ip_addr_s { 1349 sa_family_t family; /* AF_INET or AF_INET6 */ 1350 union { 1351 in_addr_t ip4addr; 1352 in6_addr_t ip6addr; 1353 } un; 1354 } ibt_ip_addr_t; 1355 1356 #ifdef __cplusplus 1357 } 1358 #endif 1359 1360 #endif /* _SYS_IB_IBTL_IBTL_TYPES_H */ 1361