1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_NXGE_NXGE_N2_ESR_HW_H 27 #define _SYS_NXGE_NXGE_N2_ESR_HW_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 #define ESR_N2_DEV_ADDR 0x1E 34 #define ESR_N2_BASE 0x8000 35 36 /* 37 * Definitions for TI WIZ6C2xxN2x0 Macro Family. 38 */ 39 40 /* Register Blocks base address */ 41 42 #define ESR_N2_PLL_REG_OFFSET 0 43 #define ESR_N2_TEST_REG_OFFSET 0x004 44 #define ESR_N2_TX_REG_OFFSET 0x100 45 #define ESR_N2_TX_0_REG_OFFSET 0x100 46 #define ESR_N2_TX_1_REG_OFFSET 0x104 47 #define ESR_N2_TX_2_REG_OFFSET 0x108 48 #define ESR_N2_TX_3_REG_OFFSET 0x10c 49 #define ESR_N2_TX_4_REG_OFFSET 0x110 50 #define ESR_N2_TX_5_REG_OFFSET 0x114 51 #define ESR_N2_TX_6_REG_OFFSET 0x118 52 #define ESR_N2_TX_7_REG_OFFSET 0x11c 53 #define ESR_N2_RX_REG_OFFSET 0x120 54 #define ESR_N2_RX_0_REG_OFFSET 0x120 55 #define ESR_N2_RX_1_REG_OFFSET 0x124 56 #define ESR_N2_RX_2_REG_OFFSET 0x128 57 #define ESR_N2_RX_3_REG_OFFSET 0x12c 58 #define ESR_N2_RX_4_REG_OFFSET 0x130 59 #define ESR_N2_RX_5_REG_OFFSET 0x134 60 #define ESR_N2_RX_6_REG_OFFSET 0x138 61 #define ESR_N2_RX_7_REG_OFFSET 0x13c 62 #define ESR_N2_P1_REG_OFFSET 0x400 63 64 /* Register address */ 65 66 #define ESR_N2_PLL_CFG_REG ESR_N2_BASE + ESR_N2_PLL_REG_OFFSET 67 #define ESR_N2_PLL_CFG_L_REG ESR_N2_BASE + ESR_N2_PLL_REG_OFFSET 68 #define ESR_N2_PLL_CFG_H_REG ESR_N2_BASE + ESR_N2_PLL_REG_OFFSET + 1 69 #define ESR_N2_PLL_STS_REG ESR_N2_BASE + ESR_N2_PLL_REG_OFFSET + 2 70 #define ESR_N2_PLL_STS_L_REG ESR_N2_BASE + ESR_N2_PLL_REG_OFFSET + 2 71 #define ESR_N2_PLL_STS_H_REG ESR_N2_BASE + ESR_N2_PLL_REG_OFFSET + 3 72 #define ESR_N2_TEST_CFG_REG ESR_N2_BASE + ESR_N2_TEST_REG_OFFSET 73 #define ESR_N2_TEST_CFG_L_REG ESR_N2_BASE + ESR_N2_TEST_REG_OFFSET 74 #define ESR_N2_TEST_CFG_H_REG ESR_N2_BASE + ESR_N2_TEST_REG_OFFSET + 1 75 76 #define ESR_N2_TX_CFG_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_TX_REG_OFFSET +\ 77 (chan * 4)) 78 #define ESR_N2_TX_CFG_L_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_TX_REG_OFFSET +\ 79 (chan * 4)) 80 #define ESR_N2_TX_CFG_H_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_TX_REG_OFFSET +\ 81 (chan * 4) + 1) 82 #define ESR_N2_TX_STS_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_TX_REG_OFFSET +\ 83 (chan * 4) + 2) 84 #define ESR_N2_TX_STS_L_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_TX_REG_OFFSET +\ 85 (chan * 4) + 2) 86 #define ESR_N2_TX_STS_H_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_TX_REG_OFFSET +\ 87 (chan * 4) + 3) 88 #define ESR_N2_RX_CFG_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_RX_REG_OFFSET +\ 89 (chan * 4)) 90 #define ESR_N2_RX_CFG_L_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_RX_REG_OFFSET +\ 91 (chan * 4)) 92 #define ESR_N2_RX_CFG_H_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_RX_REG_OFFSET +\ 93 (chan * 4) + 1) 94 #define ESR_N2_RX_STS_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_RX_REG_OFFSET +\ 95 (chan * 4) + 2) 96 #define ESR_N2_RX_STS_L_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_RX_REG_OFFSET +\ 97 (chan * 4) + 2) 98 #define ESR_N2_RX_STS_H_REG_ADDR(chan) (ESR_N2_BASE + ESR_N2_RX_REG_OFFSET +\ 99 (chan * 4) + 3) 100 101 /* PLL Configuration Low 16-bit word */ 102 typedef union _esr_ti_cfgpll_l { 103 uint16_t value; 104 105 struct { 106 #if defined(_BIT_FIELDS_HTOL) 107 uint16_t res2 : 6; 108 uint16_t lb : 2; 109 uint16_t res1 : 3; 110 uint16_t mpy : 4; 111 uint16_t enpll : 1; 112 #elif defined(_BIT_FIELDS_LTOH) 113 uint16_t enpll : 1; 114 uint16_t mpy : 4; 115 uint16_t res1 : 3; 116 uint16_t lb : 2; 117 uint16_t res2 : 6; 118 #endif 119 } bits; 120 } esr_ti_cfgpll_l_t; 121 122 /* PLL Configurations */ 123 #define CFGPLL_LB_FREQ_DEP_BANDWIDTH 0 124 #define CFGPLL_LB_LOW_BANDWIDTH 0x2 125 #define CFGPLL_LB_HIGH_BANDWIDTH 0x3 126 #define CFGPLL_MPY_4X 0 127 #define CFGPLL_MPY_5X 0x1 128 #define CFGPLL_MPY_6X 0x2 129 #define CFGPLL_MPY_8X 0x4 130 #define CFGPLL_MPY_10X 0x5 131 #define CFGPLL_MPY_12X 0x6 132 #define CFGPLL_MPY_12P5X 0x7 133 134 /* Rx Configuration Low 16-bit word */ 135 136 typedef union _esr_ti_cfgrx_l { 137 uint16_t value; 138 139 struct { 140 #if defined(_BIT_FIELDS_HTOL) 141 uint16_t los : 2; 142 uint16_t align : 2; 143 uint16_t res : 1; 144 uint16_t term : 3; 145 uint16_t invpair : 1; 146 uint16_t rate : 2; 147 uint16_t buswidth : 3; 148 uint16_t entest : 1; 149 uint16_t enrx : 1; 150 #elif defined(_BIT_FIELDS_LTOH) 151 uint16_t enrx : 1; 152 uint16_t entest : 1; 153 uint16_t buswidth : 3; 154 uint16_t rate : 2; 155 uint16_t invpair : 1; 156 uint16_t term : 3; 157 uint16_t res : 1; 158 uint16_t align : 2; 159 uint16_t los : 2; 160 #endif 161 } bits; 162 } esr_ti_cfgrx_l_t; 163 164 /* Rx Configuration High 16-bit word */ 165 166 typedef union _esr_ti_cfgrx_h { 167 uint16_t value; 168 169 struct { 170 #if defined(_BIT_FIELDS_HTOL) 171 uint16_t res2 : 6; 172 uint16_t bsinrxn : 1; 173 uint16_t bsinrxp : 1; 174 uint16_t res1 : 1; 175 uint16_t eq : 4; 176 uint16_t cdr : 3; 177 #elif defined(_BIT_FIELDS_LTOH) 178 uint16_t cdr : 3; 179 uint16_t eq : 4; 180 uint16_t res1 : 1; 181 uint16_t bsinrxp : 1; 182 uint16_t bsinrxn : 1; 183 uint16_t res2 : 6; 184 #endif 185 } bits; 186 } esr_ti_cfgrx_h_t; 187 188 /* Receive Configurations */ 189 #define CFGRX_BUSWIDTH_10BIT 0 190 #define CFGRX_BUSWIDTH_8BIT 1 191 #define CFGRX_RATE_FULL 0 192 #define CFGRX_RATE_HALF 1 193 #define CFGRX_RATE_QUAD 2 194 #define CFGRX_TERM_VDDT 0 195 #define CFGRX_TERM_0P8VDDT 1 196 #define CFGRX_TERM_FLOAT 3 197 #define CFGRX_ALIGN_DIS 0 198 #define CFGRX_ALIGN_EN 1 199 #define CFGRX_ALIGN_JOG 2 200 #define CFGRX_LOS_DIS 0 201 #define CFGRX_LOS_HITHRES 1 202 #define CFGRX_LOS_LOTHRES 2 203 #define CFGRX_CDR_1ST_ORDER 0 204 #define CFGRX_CDR_2ND_ORDER_HP 1 205 #define CFGRX_CDR_2ND_ORDER_MP 2 206 #define CFGRX_CDR_2ND_ORDER_LP 3 207 #define CFGRX_CDR_1ST_ORDER_FAST_LOCK 4 208 #define CFGRX_CDR_2ND_ORDER_HP_FAST_LOCK 5 209 #define CFGRX_CDR_2ND_ORDER_MP_FAST_LOCK 6 210 #define CFGRX_CDR_2ND_ORDER_LP_FAST_LOCK 7 211 #define CFGRX_EQ_MAX_LF 0 212 #define CFGRX_EQ_ADAPTIVE_LP_ADAPTIVE_ZF 0x1 213 #define CFGRX_EQ_ADAPTIVE_LF_1084MHZ_ZF 0x8 214 #define CFGRX_EQ_ADAPTIVE_LF_805MHZ_ZF 0x9 215 #define CFGRX_EQ_ADAPTIVE_LP_573MHZ_ZF 0xA 216 #define CFGRX_EQ_ADAPTIVE_LP_402MHZ_ZF 0xB 217 #define CFGRX_EQ_ADAPTIVE_LP_304MHZ_ZF 0xC 218 #define CFGRX_EQ_ADAPTIVE_LP_216MHZ_ZF 0xD 219 #define CFGRX_EQ_ADAPTIVE_LP_156MHZ_ZF 0xE 220 #define CFGRX_EQ_ADAPTIVE_LP_135HZ_ZF 0xF 221 222 /* Rx Status Low 16-bit word */ 223 224 typedef union _esr_ti_stsrx_l { 225 uint16_t value; 226 227 struct { 228 #if defined(_BIT_FIELDS_HTOL) 229 uint16_t res : 10; 230 uint16_t bsrxn : 1; 231 uint16_t bsrxp : 1; 232 uint16_t losdtct : 1; 233 uint16_t oddcg : 1; 234 uint16_t sync : 1; 235 uint16_t testfail : 1; 236 #elif defined(_BIT_FIELDS_LTOH) 237 uint16_t testfail : 1; 238 uint16_t sync : 1; 239 uint16_t oddcg : 1; 240 uint16_t losdtct : 1; 241 uint16_t bsrxp : 1; 242 uint16_t bsrxn : 1; 243 uint16_t res : 10; 244 #endif 245 } bits; 246 } esr_ti_stsrx_l_t; 247 248 /* Tx Configuration Low 16-bit word */ 249 250 typedef union _esr_ti_cfgtx_l { 251 uint16_t value; 252 253 struct { 254 #if defined(_BIT_FIELDS_HTOL) 255 uint16_t de : 4; 256 uint16_t swing : 3; 257 uint16_t cm : 1; 258 uint16_t invpair : 1; 259 uint16_t rate : 2; 260 uint16_t buswwidth : 3; 261 uint16_t entest : 1; 262 uint16_t entx : 1; 263 #elif defined(_BIT_FIELDS_LTOH) 264 uint16_t entx : 1; 265 uint16_t entest : 1; 266 uint16_t buswwidth : 3; 267 uint16_t rate : 2; 268 uint16_t invpair : 1; 269 uint16_t cm : 1; 270 uint16_t swing : 3; 271 uint16_t de : 4; 272 #endif 273 } bits; 274 } esr_ti_cfgtx_l_t; 275 276 /* Tx Configuration High 16-bit word */ 277 278 typedef union _esr_ti_cfgtx_h { 279 uint16_t value; 280 281 struct { 282 #if defined(_BIT_FIELDS_HTOL) 283 uint16_t res : 14; 284 uint16_t bstx : 1; 285 uint16_t enftp : 1; 286 #elif defined(_BIT_FIELDS_LTOH) 287 uint16_t enftp : 1; 288 uint16_t bstx : 1; 289 uint16_t res : 14; 290 #endif 291 } bits; 292 } esr_ti_cfgtx_h_t; 293 294 /* Transmit Configurations */ 295 #define CFGTX_BUSWIDTH_10BIT 0 296 #define CFGTX_BUSWIDTH_8BIT 1 297 #define CFGTX_RATE_FULL 0 298 #define CFGTX_RATE_HALF 1 299 #define CFGTX_RATE_QUAD 2 300 #define CFGTX_SWING_125MV 0 301 #define CFGTX_SWING_250MV 1 302 #define CFGTX_SWING_500MV 2 303 #define CFGTX_SWING_625MV 3 304 #define CFGTX_SWING_750MV 4 305 #define CFGTX_SWING_1000MV 5 306 #define CFGTX_SWING_1250MV 6 307 #define CFGTX_SWING_1375MV 7 308 #define CFGTX_DE_0 0 309 #define CFGTX_DE_4P76 1 310 #define CFGTX_DE_9P52 2 311 #define CFGTX_DE_14P28 3 312 #define CFGTX_DE_19P04 4 313 #define CFGTX_DE_23P8 5 314 #define CFGTX_DE_28P56 6 315 #define CFGTX_DE_33P32 7 316 317 /* Test Configuration */ 318 319 typedef union _esr_ti_testcfg { 320 uint16_t value; 321 322 struct { 323 #if defined(_BIT_FIELDS_HTOL) 324 uint16_t res1 : 1; 325 uint16_t invpat : 1; 326 uint16_t rate : 2; 327 uint16_t res : 1; 328 uint16_t enbspls : 1; 329 uint16_t enbsrx : 1; 330 uint16_t enbstx : 1; 331 uint16_t loopback : 2; 332 uint16_t clkbyp : 2; 333 uint16_t enrxpatt : 1; 334 uint16_t entxpatt : 1; 335 uint16_t testpatt : 2; 336 #elif defined(_BIT_FIELDS_LTOH) 337 uint16_t testpatt : 2; 338 uint16_t entxpatt : 1; 339 uint16_t enrxpatt : 1; 340 uint16_t clkbyp : 2; 341 uint16_t loopback : 2; 342 uint16_t enbstx : 1; 343 uint16_t enbsrx : 1; 344 uint16_t enbspls : 1; 345 uint16_t res : 1; 346 uint16_t rate : 2; 347 uint16_t invpat : 1; 348 uint16_t res1 : 1; 349 #endif 350 } bits; 351 } esr_ti_testcfg_t; 352 353 #define TESTCFG_PAD_LOOPBACK 0x1 354 #define TESTCFG_INNER_CML_DIS_LOOPBACK 0x2 355 #define TESTCFG_INNER_CML_EN_LOOOPBACK 0x3 356 357 /* 358 * Definitions for TI WIZ7c2xxn5x1 Macro Family (KT/NIU). 359 */ 360 361 /* PLL_CFG: PLL Configuration Low 16-bit word */ 362 typedef union _k_esr_ti_cfgpll_l { 363 uint16_t value; 364 365 struct { 366 #if defined(_BIT_FIELDS_HTOL) 367 uint16_t res2 : 1; 368 uint16_t clkbyp : 2; 369 uint16_t lb : 2; 370 uint16_t res1 : 1; 371 uint16_t vrange : 1; 372 uint16_t divclken : 1; 373 uint16_t mpy : 7; 374 uint16_t enpll : 1; 375 #elif defined(_BIT_FIELDS_LTOH) 376 uint16_t enpll : 1; 377 uint16_t mpy : 7; 378 uint16_t divclken : 1; 379 uint16_t vrange : 1; 380 uint16_t res1 : 1; 381 uint16_t lb : 2; 382 uint16_t clkbyp : 2; 383 uint16_t res2 : 1; 384 #endif 385 } bits; 386 } k_esr_ti_cfgpll_l_t; 387 388 /* PLL Configurations */ 389 #define K_CFGPLL_ENABLE_PLL 1 390 #define K_CFGPLL_MPY_4X 0x10 391 #define K_CFGPLL_MPY_5X 0x14 392 #define K_CFGPLL_MPY_6X 0x18 393 #define K_CFGPLL_MPY_8X 0x20 394 #define K_CFGPLL_MPY_8P25X 0x21 395 #define K_CFGPLL_MPY_10X 0x28 396 #define K_CFGPLL_MPY_12X 0x30 397 #define K_CFGPLL_MPY_12P5X 0x32 398 #define K_CFGPLL_MPY_15X 0x3c 399 #define K_CFGPLL_MPY_16X 0x40 400 #define K_CFGPLL_MPY_16P5X 0x42 401 #define K_CFGPLL_MPY_20X 0x50 402 #define K_CFGPLL_MPY_22X 0x58 403 #define K_CFGPLL_MPY_25X 0x64 404 #define K_CFGPLL_ENABLE_DIVCLKEN 0x100 405 406 /* PLL_STS */ 407 typedef union _k_esr_ti_pll_sts { 408 uint16_t value; 409 410 struct { 411 #if defined(_BIT_FIELDS_HTOL) 412 uint16_t res2 : 12; 413 uint16_t res1 : 2; 414 uint16_t divclk : 1; 415 uint16_t lock : 1; 416 #elif defined(_BIT_FIELDS_LTOH) 417 uint16_t lock : 1; 418 uint16_t divclk : 1; 419 uint16_t res1 : 2; 420 uint16_t res2 : 12; 421 #endif 422 } bits; 423 } k_esr_ti_pll_sts_t; 424 425 /* TEST_CFT */ 426 typedef union _kt_esr_ti_testcfg { 427 uint16_t value; 428 429 struct { 430 #if defined(_BIT_FIELDS_HTOL) 431 uint16_t res : 7; 432 uint16_t testpatt2 : 3; 433 uint16_t testpatt1 : 3; 434 uint16_t enbspt : 1; 435 uint16_t enbsrx : 1; 436 uint16_t enbstx : 1; 437 #elif defined(_BIT_FIELDS_LTOH) 438 uint16_t enbstx : 1; 439 uint16_t enbsrx : 1; 440 uint16_t enbspt : 1; 441 uint16_t testpatt1 : 3; 442 uint16_t testpatt2 : 3; 443 uint16_t res : 7; 444 #endif 445 } bits; 446 } k_esr_ti_testcfg_t; 447 448 #define K_TESTCFG_ENBSTX 0x1 449 #define K_TESTCFG_ENBSRX 0x2 450 #define K_TESTCFG_ENBSPT 0x4 451 452 /* TX_CFG: Tx Configuration Low 16-bit word */ 453 454 typedef union _k_esr_ti_cfgtx_l { 455 uint16_t value; 456 457 struct { 458 #if defined(_BIT_FIELDS_HTOL) 459 uint16_t de : 3; 460 uint16_t swing : 4; 461 uint16_t cm : 1; 462 uint16_t invpair : 1; 463 uint16_t rate : 2; 464 uint16_t buswwidth : 4; 465 uint16_t entx : 1; 466 #elif defined(_BIT_FIELDS_LTOH) 467 uint16_t entx : 1; 468 uint16_t buswwidth : 4; 469 uint16_t rate : 2; 470 uint16_t invpair : 1; 471 uint16_t cm : 1; 472 uint16_t swing : 4; 473 uint16_t de : 3; 474 #endif 475 } bits; 476 } k_esr_ti_cfgtx_l_t; 477 478 /* Tx Configuration High 16-bit word */ 479 480 typedef union _k_esr_ti_cfgtx_h { 481 uint16_t value; 482 483 struct { 484 #if defined(_BIT_FIELDS_HTOL) 485 uint16_t res3 : 1; 486 uint16_t bstx : 1; 487 uint16_t res2 : 1; 488 uint16_t loopback : 2; 489 uint16_t rdtct : 2; 490 uint16_t enidl : 1; 491 uint16_t rsync : 1; 492 uint16_t msync : 1; 493 uint16_t res1 : 4; 494 uint16_t de : 2; 495 #elif defined(_BIT_FIELDS_LTOH) 496 uint16_t de : 2; 497 uint16_t res1 : 4; 498 uint16_t msync : 1; 499 uint16_t rsync : 1; 500 uint16_t enidl : 1; 501 uint16_t rdtct : 2; 502 uint16_t loopback : 2; 503 uint16_t res2 : 1; 504 uint16_t bstx : 1; 505 uint16_t res3 : 1; 506 #endif 507 } bits; 508 } k_esr_ti_cfgtx_h_t; 509 510 /* Transmit Configurations (TBD) */ 511 #define K_CFGTX_ENABLE_TX 0x1 512 #define K_CFGTX_ENABLE_MSYNC 0x1 513 514 #define K_CFGTX_BUSWIDTH_10BIT 0 515 #define K_CFGTX_BUSWIDTH_8BIT 1 516 #define K_CFGTX_RATE_FULL 0 517 #define K_CFGTX_RATE_HALF 0x1 518 #define K_CFGTX_RATE_QUAD 2 519 #define K_CFGTX_SWING_125MV 0 520 #define K_CFGTX_SWING_250MV 1 521 #define K_CFGTX_SWING_500MV 2 522 #define K_CFGTX_SWING_625MV 3 523 #define K_CFGTX_SWING_750MV 4 524 #define K_CFGTX_SWING_1000MV 5 525 #define K_CFGTX_SWING_1250MV 6 526 #define K_CFGTX_SWING_1375MV 7 527 #define K_CFGTX_SWING_2000MV 0xf 528 #define K_CFGTX_DE_0 0 529 #define K_CFGTX_DE_4P76 1 530 #define K_CFGTX_DE_9P52 2 531 #define K_CFGTX_DE_14P28 3 532 #define K_CFGTX_DE_19P04 4 533 #define K_CFGTX_DE_23P8 5 534 #define K_CFGTX_DE_28P56 6 535 #define K_CFGTX_DE_33P32 7 536 #define K_CFGTX_DIS_LOOPBACK 0x0 537 #define K_CFGTX_BUMP_PAD_LOOPBACK 0x1 538 #define K_CFGTX_INNER_CML_DIS_LOOPBACK 0x2 539 #define K_CFGTX_INNER_CML_ENA_LOOPBACK 0x3 540 541 /* TX_STS */ 542 typedef union _k_esr_ti_tx_sts { 543 uint16_t value; 544 545 struct { 546 #if defined(_BIT_FIELDS_HTOL) 547 uint16_t res1 : 14; 548 uint16_t rdtctip : 1; 549 uint16_t testfail : 1; 550 #elif defined(_BIT_FIELDS_LTOH) 551 uint16_t testfail : 1; 552 uint16_t rdtctip : 1; 553 uint16_t res1 : 14; 554 #endif 555 } bits; 556 } k_esr_ti_tx_sts_t; 557 558 /* Rx Configuration Low 16-bit word */ 559 560 typedef union _k_esr_ti_cfgrx_l { 561 uint16_t value; 562 563 struct { 564 #if defined(_BIT_FIELDS_HTOL) 565 uint16_t los : 3; 566 uint16_t align : 2; 567 uint16_t term : 3; 568 uint16_t invpair : 1; 569 uint16_t rate : 2; 570 uint16_t buswidth : 4; 571 uint16_t enrx : 1; 572 #elif defined(_BIT_FIELDS_LTOH) 573 uint16_t enrx : 1; 574 uint16_t buswidth : 4; 575 uint16_t rate : 2; 576 uint16_t invpair : 1; 577 uint16_t term : 3; 578 uint16_t align : 2; 579 uint16_t los : 3; 580 #endif 581 } bits; 582 } k_esr_ti_cfgrx_l_t; 583 584 /* Rx Configuration High 16-bit word */ 585 586 typedef union _k_esr_ti_cfgrx_h { 587 uint16_t value; 588 589 struct { 590 #if defined(_BIT_FIELDS_HTOL) 591 uint16_t res2 : 1; 592 uint16_t bsinrxn : 1; 593 uint16_t bsinrxp : 1; 594 uint16_t loopback : 2; 595 uint16_t res1 : 3; 596 uint16_t enoc : 1; 597 uint16_t eq : 4; 598 uint16_t cdr : 3; 599 #elif defined(_BIT_FIELDS_LTOH) 600 uint16_t cdr : 3; 601 uint16_t eq : 4; 602 uint16_t enoc : 1; 603 uint16_t res1 : 3; 604 uint16_t loopback : 2; 605 uint16_t bsinrxp : 1; 606 uint16_t bsinrxn : 1; 607 uint16_t res2 : 1; 608 #endif 609 } bits; 610 } k_esr_ti_cfgrx_h_t; 611 612 /* Receive Configurations (TBD) */ 613 #define K_CFGRX_ENABLE_RX 0x1 614 615 #define K_CFGRX_BUSWIDTH_10BIT 0 616 #define K_CFGRX_BUSWIDTH_8BIT 1 617 #define K_CFGRX_RATE_FULL 0 618 #define K_CFGRX_RATE_HALF 1 619 #define K_CFGRX_RATE_QUAD 2 620 #define K_CFGRX_TERM_VDDT 0 621 #define K_CFGRX_TERM_0P8VDDT 1 622 #define K_CFGRX_TERM_FLOAT 3 623 #define K_CFGRX_ALIGN_DIS 0x0 624 #define K_CFGRX_ALIGN_EN 0x1 625 #define K_CFGRX_ALIGN_JOG 0x2 626 #define K_CFGRX_LOS_DIS 0x0 627 #define K_CFGRX_LOS_ENABLE 0x2 628 #define K_CFGRX_CDR_1ST_ORDER 0 629 #define K_CFGRX_CDR_2ND_ORDER_HP 1 630 #define K_CFGRX_CDR_2ND_ORDER_MP 2 631 #define K_CFGRX_CDR_2ND_ORDER_LP 3 632 #define K_CFGRX_CDR_1ST_ORDER_FAST_LOCK 4 633 #define K_CFGRX_CDR_2ND_ORDER_HP_FAST_LOCK 5 634 #define K_CFGRX_CDR_2ND_ORDER_MP_FAST_LOCK 6 635 #define K_CFGRX_CDR_2ND_ORDER_LP_FAST_LOCK 7 636 #define K_CFGRX_EQ_MAX_LF_ZF 0 637 #define K_CFGRX_EQ_ADAPTIVE 0x1 638 #define K_CFGRX_EQ_ADAPTIVE_LF_365MHZ_ZF 0x8 639 #define K_CFGRX_EQ_ADAPTIVE_LF_275MHZ_ZF 0x9 640 #define K_CFGRX_EQ_ADAPTIVE_LP_195MHZ_ZF 0xa 641 #define K_CFGRX_EQ_ADAPTIVE_LP_140MHZ_ZF 0xb 642 #define K_CFGRX_EQ_ADAPTIVE_LP_105MHZ_ZF 0xc 643 #define K_CFGRX_EQ_ADAPTIVE_LP_75MHZ_ZF 0xd 644 #define K_CFGRX_EQ_ADAPTIVE_LP_55MHZ_ZF 0xe 645 #define K_CFGRX_EQ_ADAPTIVE_LP_50HZ_ZF 0xf 646 647 /* Rx Status Low 16-bit word */ 648 649 typedef union _k_esr_ti_stsrx_l { 650 uint16_t value; 651 652 struct { 653 #if defined(_BIT_FIELDS_HTOL) 654 uint16_t res2 : 10; 655 uint16_t bsrxn : 1; 656 uint16_t bsrxp : 1; 657 uint16_t losdtct : 1; 658 uint16_t res1 : 1; 659 uint16_t sync : 1; 660 uint16_t testfail : 1; 661 #elif defined(_BIT_FIELDS_LTOH) 662 uint16_t testfail : 1; 663 uint16_t sync : 1; 664 uint16_t res1 : 1; 665 uint16_t losdtct : 1; 666 uint16_t bsrxp : 1; 667 uint16_t bsrxn : 1; 668 uint16_t res : 10; 669 #endif 670 } bits; 671 } k_esr_ti_stsrx_l_t; 672 673 #define K_TESTCFG_INNER_CML_EN_LOOOPBACK 0x3 674 675 #ifdef __cplusplus 676 } 677 #endif 678 679 #endif /* _SYS_NXGE_NXGE_N2_ESR_HW_H */ 680