16f45ec7bSml29623 /* 26f45ec7bSml29623 * CDDL HEADER START 36f45ec7bSml29623 * 46f45ec7bSml29623 * The contents of this file are subject to the terms of the 56f45ec7bSml29623 * Common Development and Distribution License (the "License"). 66f45ec7bSml29623 * You may not use this file except in compliance with the License. 76f45ec7bSml29623 * 86f45ec7bSml29623 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 96f45ec7bSml29623 * or http://www.opensolaris.org/os/licensing. 106f45ec7bSml29623 * See the License for the specific language governing permissions 116f45ec7bSml29623 * and limitations under the License. 126f45ec7bSml29623 * 136f45ec7bSml29623 * When distributing Covered Code, include this CDDL HEADER in each 146f45ec7bSml29623 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 156f45ec7bSml29623 * If applicable, add the following below this CDDL HEADER, with the 166f45ec7bSml29623 * fields enclosed by brackets "[]" replaced with your own identifying 176f45ec7bSml29623 * information: Portions Copyright [yyyy] [name of copyright owner] 186f45ec7bSml29623 * 196f45ec7bSml29623 * CDDL HEADER END 206f45ec7bSml29623 */ 216f45ec7bSml29623 /* 22678453a8Sspeer * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 236f45ec7bSml29623 * Use is subject to license terms. 246f45ec7bSml29623 */ 256f45ec7bSml29623 266f45ec7bSml29623 #ifndef _SYS_NXGE_NXGE_TXDMA_HW_H 276f45ec7bSml29623 #define _SYS_NXGE_NXGE_TXDMA_HW_H 286f45ec7bSml29623 296f45ec7bSml29623 #ifdef __cplusplus 306f45ec7bSml29623 extern "C" { 316f45ec7bSml29623 #endif 326f45ec7bSml29623 336f45ec7bSml29623 #include <nxge_defs.h> 346f45ec7bSml29623 #include <nxge_hw.h> 356f45ec7bSml29623 366f45ec7bSml29623 #if !defined(_BIG_ENDIAN) 376f45ec7bSml29623 #define SWAP(X) (X) 386f45ec7bSml29623 #else 396f45ec7bSml29623 #define SWAP(X) \ 406f45ec7bSml29623 (((X >> 32) & 0x00000000ffffffff) | \ 416f45ec7bSml29623 ((X << 32) & 0xffffffff00000000)) 426f45ec7bSml29623 #endif 436f45ec7bSml29623 446f45ec7bSml29623 /* 456f45ec7bSml29623 * Partitioning Suport: same as those defined for the RX 466f45ec7bSml29623 */ 47678453a8Sspeer 486f45ec7bSml29623 /* 496f45ec7bSml29623 * TDC: Partitioning Support 506f45ec7bSml29623 * (Each of the following registers is for each TDC) 516f45ec7bSml29623 */ 526f45ec7bSml29623 #define TX_LOG_REG_SIZE 512 536f45ec7bSml29623 #define TX_LOG_DMA_OFFSET(channel) (channel * TX_LOG_REG_SIZE) 546f45ec7bSml29623 556f45ec7bSml29623 #define TX_LOG_PAGE_VLD_REG (FZC_DMC + 0x40000) 566f45ec7bSml29623 #define TX_LOG_PAGE_MASK1_REG (FZC_DMC + 0x40008) 576f45ec7bSml29623 #define TX_LOG_PAGE_VAL1_REG (FZC_DMC + 0x40010) 586f45ec7bSml29623 #define TX_LOG_PAGE_MASK2_REG (FZC_DMC + 0x40018) 596f45ec7bSml29623 #define TX_LOG_PAGE_VAL2_REG (FZC_DMC + 0x40020) 606f45ec7bSml29623 #define TX_LOG_PAGE_RELO1_REG (FZC_DMC + 0x40028) 616f45ec7bSml29623 #define TX_LOG_PAGE_RELO2_REG (FZC_DMC + 0x40030) 626f45ec7bSml29623 #define TX_LOG_PAGE_HDL_REG (FZC_DMC + 0x40038) 636f45ec7bSml29623 646f45ec7bSml29623 /* Transmit Addressing Mode: Set to 1 to select 32-bit addressing mode */ 656f45ec7bSml29623 #define TX_ADDR_MD_REG (FZC_DMC + 0x45000) 666f45ec7bSml29623 676f45ec7bSml29623 #define TX_ADDR_MD_SHIFT 0 /* bits 0:0 */ 686f45ec7bSml29623 #define TX_ADDR_MD_SET_32 0x0000000000000001ULL /* 1 to select 32 bit */ 696f45ec7bSml29623 #define TX_ADDR_MD_MASK 0x0000000000000001ULL 706f45ec7bSml29623 716f45ec7bSml29623 typedef union _tx_addr_md_t { 726f45ec7bSml29623 uint64_t value; 736f45ec7bSml29623 struct { 746f45ec7bSml29623 #if defined(_BIG_ENDIAN) 756f45ec7bSml29623 uint32_t hdw; 766f45ec7bSml29623 #endif 776f45ec7bSml29623 struct { 786f45ec7bSml29623 #if defined(_BIT_FIELDS_HTOL) 796f45ec7bSml29623 uint32_t res1_1:31; 806f45ec7bSml29623 uint32_t mode32:1; 816f45ec7bSml29623 #elif defined(_BIT_FIELDS_LTOH) 826f45ec7bSml29623 uint32_t mode32:1; 836f45ec7bSml29623 uint32_t res1_1:31; 846f45ec7bSml29623 #endif 856f45ec7bSml29623 } ldw; 866f45ec7bSml29623 #if !defined(_BIG_ENDIAN) 876f45ec7bSml29623 uint32_t hdw; 886f45ec7bSml29623 #endif 896f45ec7bSml29623 } bits; 906f45ec7bSml29623 } tx_addr_md_t, *p_tx_addr_md_t; 916f45ec7bSml29623 926f45ec7bSml29623 /* Transmit Packet Descriptor Structure */ 936f45ec7bSml29623 #define TX_PKT_DESC_SAD_SHIFT 0 /* bits 43:0 */ 946f45ec7bSml29623 #define TX_PKT_DESC_SAD_MASK 0x00000FFFFFFFFFFFULL 956f45ec7bSml29623 #define TX_PKT_DESC_TR_LEN_SHIFT 44 /* bits 56:44 */ 966f45ec7bSml29623 #define TX_PKT_DESC_TR_LEN_MASK 0x01FFF00000000000ULL 976f45ec7bSml29623 #define TX_PKT_DESC_NUM_PTR_SHIFT 58 /* bits 61:58 */ 986f45ec7bSml29623 #define TX_PKT_DESC_NUM_PTR_MASK 0x3C00000000000000ULL 996f45ec7bSml29623 #define TX_PKT_DESC_MARK_SHIFT 62 /* bit 62 */ 1006f45ec7bSml29623 #define TX_PKT_DESC_MARK 0x4000000000000000ULL 1016f45ec7bSml29623 #define TX_PKT_DESC_MARK_MASK 0x4000000000000000ULL 1026f45ec7bSml29623 #define TX_PKT_DESC_SOP_SHIFT 63 /* bit 63 */ 1036f45ec7bSml29623 #define TX_PKT_DESC_SOP 0x8000000000000000ULL 1046f45ec7bSml29623 #define TX_PKT_DESC_SOP_MASK 0x8000000000000000ULL 1056f45ec7bSml29623 1066f45ec7bSml29623 typedef union _tx_desc_t { 1076f45ec7bSml29623 uint64_t value; 1086f45ec7bSml29623 struct { 1096f45ec7bSml29623 #if defined(_BIG_ENDIAN) 1106f45ec7bSml29623 struct { 1116f45ec7bSml29623 #if defined(_BIT_FIELDS_HTOL) 1126f45ec7bSml29623 uint32_t sop:1; 1136f45ec7bSml29623 uint32_t mark:1; 1146f45ec7bSml29623 uint32_t num_ptr:4; 1156f45ec7bSml29623 uint32_t res1:1; 1166f45ec7bSml29623 uint32_t tr_len:13; 1176f45ec7bSml29623 uint32_t sad:12; 1186f45ec7bSml29623 1196f45ec7bSml29623 #elif defined(_BIT_FIELDS_LTOH) 1206f45ec7bSml29623 uint32_t sad:12; 1216f45ec7bSml29623 uint32_t tr_len:13; 1226f45ec7bSml29623 uint32_t res1:1; 1236f45ec7bSml29623 uint32_t num_ptr:4; 1246f45ec7bSml29623 uint32_t mark:1; 1256f45ec7bSml29623 uint32_t sop:1; 1266f45ec7bSml29623 1276f45ec7bSml29623 #endif 1286f45ec7bSml29623 } hdw; 1296f45ec7bSml29623 #endif 1306f45ec7bSml29623 struct { 1316f45ec7bSml29623 #if defined(_BIT_FIELDS_HTOL) 1326f45ec7bSml29623 uint32_t sad:32; 1336f45ec7bSml29623 #elif defined(_BIT_FIELDS_LTOH) 1346f45ec7bSml29623 uint32_t sad:32; 1356f45ec7bSml29623 #endif 1366f45ec7bSml29623 } ldw; 1376f45ec7bSml29623 #if !defined(_BIG_ENDIAN) 1386f45ec7bSml29623 struct { 1396f45ec7bSml29623 1406f45ec7bSml29623 #if defined(_BIT_FIELDS_HTOL) 1416f45ec7bSml29623 uint32_t sop:1; 1426f45ec7bSml29623 uint32_t mark:1; 1436f45ec7bSml29623 uint32_t num_ptr:4; 1446f45ec7bSml29623 uint32_t res1:1; 1456f45ec7bSml29623 uint32_t tr_len:13; 1466f45ec7bSml29623 uint32_t sad:12; 1476f45ec7bSml29623 #elif defined(_BIT_FIELDS_LTOH) 1486f45ec7bSml29623 uint32_t sad:12; 1496f45ec7bSml29623 uint32_t tr_len:13; 1506f45ec7bSml29623 uint32_t res1:1; 1516f45ec7bSml29623 uint32_t num_ptr:4; 1526f45ec7bSml29623 uint32_t mark:1; 1536f45ec7bSml29623 uint32_t sop:1; 1546f45ec7bSml29623 #endif 1556f45ec7bSml29623 } hdw; 1566f45ec7bSml29623 #endif 1576f45ec7bSml29623 } bits; 1586f45ec7bSml29623 } tx_desc_t, *p_tx_desc_t; 1596f45ec7bSml29623 1606f45ec7bSml29623 1616f45ec7bSml29623 /* Transmit Ring Configuration (24 Channels) */ 1626f45ec7bSml29623 #define TX_RNG_CFIG_REG (DMC + 0x40000) 1636f45ec7bSml29623 #if OLD 1646f45ec7bSml29623 #define TX_RING_HDH_REG (DMC + 0x40008) 1656f45ec7bSml29623 #endif 1666f45ec7bSml29623 #define TX_RING_HDL_REG (DMC + 0x40010) 1676f45ec7bSml29623 #define TX_RING_KICK_REG (DMC + 0x40018) 1686f45ec7bSml29623 #define TX_ENT_MSK_REG (DMC + 0x40020) 1696f45ec7bSml29623 #define TX_CS_REG (DMC + 0x40028) 1706f45ec7bSml29623 #define TXDMA_MBH_REG (DMC + 0x40030) 1716f45ec7bSml29623 #define TXDMA_MBL_REG (DMC + 0x40038) 1726f45ec7bSml29623 #define TX_DMA_PRE_ST_REG (DMC + 0x40040) 1736f45ec7bSml29623 #define TX_RNG_ERR_LOGH_REG (DMC + 0x40048) 1746f45ec7bSml29623 #define TX_RNG_ERR_LOGL_REG (DMC + 0x40050) 1756f45ec7bSml29623 #define TDMC_INTR_DBG_REG (DMC + 0x40060) 1766f45ec7bSml29623 #define TX_CS_DBG_REG (DMC + 0x40068) 1776f45ec7bSml29623 1786f45ec7bSml29623 /* Transmit Ring Configuration */ 1796f45ec7bSml29623 #define TX_RNG_CFIG_STADDR_SHIFT 6 /* bits 18:6 */ 1806f45ec7bSml29623 #define TX_RNG_CFIG_STADDR_MASK 0x000000000007FFC0ULL 1816f45ec7bSml29623 #define TX_RNG_CFIG_ADDR_MASK 0x00000FFFFFFFFFC0ULL 1826f45ec7bSml29623 #define TX_RNG_CFIG_STADDR_BASE_SHIFT 19 /* bits 43:19 */ 1836f45ec7bSml29623 #define TX_RNG_CFIG_STADDR_BASE_MASK 0x00000FFFFFF80000ULL 1846f45ec7bSml29623 #define TX_RNG_CFIG_LEN_SHIFT 48 /* bits 60:48 */ 1856f45ec7bSml29623 #define TX_RNG_CFIG_LEN_MASK 0xFFF8000000000000ULL 1866f45ec7bSml29623 1876f45ec7bSml29623 #define TX_RNG_HEAD_TAIL_SHIFT 3 1886f45ec7bSml29623 #define TX_RNG_HEAD_TAIL_WRAP_SHIFT 19 1896f45ec7bSml29623 1906f45ec7bSml29623 typedef union _tx_rng_cfig_t { 1916f45ec7bSml29623 uint64_t value; 1926f45ec7bSml29623 struct { 1936f45ec7bSml29623 #if defined(_BIG_ENDIAN) 1946f45ec7bSml29623 struct { 1956f45ec7bSml29623 #if defined(_BIT_FIELDS_HTOL) 1966f45ec7bSml29623 uint32_t res2:3; 1976f45ec7bSml29623 uint32_t len:13; 1986f45ec7bSml29623 uint32_t res1:4; 1996f45ec7bSml29623 uint32_t staddr_base:12; 2006f45ec7bSml29623 #elif defined(_BIT_FIELDS_LTOH) 2016f45ec7bSml29623 uint32_t staddr_base:12; 2026f45ec7bSml29623 uint32_t res1:4; 2036f45ec7bSml29623 uint32_t len:13; 2046f45ec7bSml29623 uint32_t res2:3; 2056f45ec7bSml29623 #endif 2066f45ec7bSml29623 } hdw; 2076f45ec7bSml29623 #endif 2086f45ec7bSml29623 struct { 2096f45ec7bSml29623 #if defined(_BIT_FIELDS_HTOL) 2106f45ec7bSml29623 uint32_t staddr_base:13; 2116f45ec7bSml29623 uint32_t staddr:13; 2126f45ec7bSml29623 uint32_t res2:6; 2136f45ec7bSml29623 #elif defined(_BIT_FIELDS_LTOH) 2146f45ec7bSml29623 uint32_t res2:6; 2156f45ec7bSml29623 uint32_t staddr:13; 2166f45ec7bSml29623 uint32_t staddr_base:13; 2176f45ec7bSml29623 #endif 2186f45ec7bSml29623 } ldw; 2196f45ec7bSml29623 #ifndef _BIG_ENDIAN 2206f45ec7bSml29623 struct { 2216f45ec7bSml29623 #if defined(_BIT_FIELDS_HTOL) 2226f45ec7bSml29623 uint32_t res2:3; 2236f45ec7bSml29623 uint32_t len:13; 2246f45ec7bSml29623 uint32_t res1:4; 2256f45ec7bSml29623 uint32_t staddr_base:12; 2266f45ec7bSml29623 #elif defined(_BIT_FIELDS_LTOH) 2276f45ec7bSml29623 uint32_t staddr_base:12; 2286f45ec7bSml29623 uint32_t res1:4; 2296f45ec7bSml29623 uint32_t len:13; 2306f45ec7bSml29623 uint32_t res2:3; 2316f45ec7bSml29623 #endif 2326f45ec7bSml29623 } hdw; 2336f45ec7bSml29623 #endif 2346f45ec7bSml29623 } bits; 2356f45ec7bSml29623 } tx_rng_cfig_t, *p_tx_rng_cfig_t; 2366f45ec7bSml29623 2376f45ec7bSml29623 /* Transmit Ring Head Low */ 2386f45ec7bSml29623 #define TX_RING_HDL_SHIFT 3 /* bit 31:3 */ 2396f45ec7bSml29623 #define TX_RING_HDL_MASK 0x00000000FFFFFFF8ULL 2406f45ec7bSml29623 2416f45ec7bSml29623 typedef union _tx_ring_hdl_t { 2426f45ec7bSml29623 uint64_t value; 2436f45ec7bSml29623 struct { 2446f45ec7bSml29623 #if defined(_BIG_ENDIAN) 2456f45ec7bSml29623 uint32_t hdw; 2466f45ec7bSml29623 #endif 2476f45ec7bSml29623 struct { 2486f45ec7bSml29623 #if defined(_BIT_FIELDS_HTOL) 2496f45ec7bSml29623 uint32_t res0:12; 2506f45ec7bSml29623 uint32_t wrap:1; 2516f45ec7bSml29623 uint32_t head:16; 2526f45ec7bSml29623 uint32_t res2:3; 2536f45ec7bSml29623 #elif defined(_BIT_FIELDS_LTOH) 2546f45ec7bSml29623 uint32_t res2:3; 2556f45ec7bSml29623 uint32_t head:16; 2566f45ec7bSml29623 uint32_t wrap:1; 2576f45ec7bSml29623 uint32_t res0:12; 2586f45ec7bSml29623 #endif 2596f45ec7bSml29623 } ldw; 2606f45ec7bSml29623 #ifndef _BIG_ENDIAN 2616f45ec7bSml29623 uint32_t hdw; 2626f45ec7bSml29623 #endif 2636f45ec7bSml29623 } bits; 2646f45ec7bSml29623 } tx_ring_hdl_t, *p_tx_ring_hdl_t; 2656f45ec7bSml29623 2666f45ec7bSml29623 /* Transmit Ring Kick */ 2676f45ec7bSml29623 #define TX_RING_KICK_TAIL_SHIFT 3 /* bit 43:3 */ 2686f45ec7bSml29623 #define TX_RING_KICK_TAIL_MASK 0x000000FFFFFFFFFF8ULL 2696f45ec7bSml29623 2706f45ec7bSml29623 typedef union _tx_ring_kick_t { 2716f45ec7bSml29623 uint64_t value; 2726f45ec7bSml29623 struct { 2736f45ec7bSml29623 #ifdef _BIG_ENDIAN 2746f45ec7bSml29623 uint32_t hdw; 2756f45ec7bSml29623 #endif 2766f45ec7bSml29623 struct { 2776f45ec7bSml29623 #if defined(_BIT_FIELDS_HTOL) 2786f45ec7bSml29623 uint32_t res0:12; 2796f45ec7bSml29623 uint32_t wrap:1; 2806f45ec7bSml29623 uint32_t tail:16; 2816f45ec7bSml29623 uint32_t res2:3; 2826f45ec7bSml29623 #elif defined(_BIT_FIELDS_LTOH) 2836f45ec7bSml29623 uint32_t res2:3; 2846f45ec7bSml29623 uint32_t tail:16; 2856f45ec7bSml29623 uint32_t wrap:1; 2866f45ec7bSml29623 uint32_t res0:12; 2876f45ec7bSml29623 #endif 2886f45ec7bSml29623 } ldw; 2896f45ec7bSml29623 #ifndef _BIG_ENDIAN 2906f45ec7bSml29623 uint32_t hdw; 2916f45ec7bSml29623 #endif 2926f45ec7bSml29623 } bits; 2936f45ec7bSml29623 } tx_ring_kick_t, *p_tx_ring_kick_t; 2946f45ec7bSml29623 2956f45ec7bSml29623 /* Transmit Event Mask (DMC + 0x40020) */ 2966f45ec7bSml29623 #define TX_ENT_MSK_PKT_PRT_ERR_SHIFT 0 /* bit 0: 0 to flag */ 2976f45ec7bSml29623 #define TX_ENT_MSK_PKT_PRT_ERR_MASK 0x0000000000000001ULL 2986f45ec7bSml29623 #define TX_ENT_MSK_CONF_PART_ERR_SHIFT 1 /* bit 1: 0 to flag */ 2996f45ec7bSml29623 #define TX_ENT_MSK_CONF_PART_ERR_MASK 0x0000000000000002ULL 3006f45ec7bSml29623 #define TX_ENT_MSK_NACK_PKT_RD_SHIFT 2 /* bit 2: 0 to flag */ 3016f45ec7bSml29623 #define TX_ENT_MSK_NACK_PKT_RD_MASK 0x0000000000000004ULL 3026f45ec7bSml29623 #define TX_ENT_MSK_NACK_PREF_SHIFT 3 /* bit 3: 0 to flag */ 3036f45ec7bSml29623 #define TX_ENT_MSK_NACK_PREF_MASK 0x0000000000000008ULL 3046f45ec7bSml29623 #define TX_ENT_MSK_PREF_BUF_ECC_ERR_SHIFT 4 /* bit 4: 0 to flag */ 3056f45ec7bSml29623 #define TX_ENT_MSK_PREF_BUF_ECC_ERR_MASK 0x0000000000000010ULL 3066f45ec7bSml29623 #define TX_ENT_MSK_TX_RING_OFLOW_SHIFT 5 /* bit 5: 0 to flag */ 3076f45ec7bSml29623 #define TX_ENT_MSK_TX_RING_OFLOW_MASK 0x0000000000000020ULL 3086f45ec7bSml29623 #define TX_ENT_MSK_PKT_SIZE_ERR_SHIFT 6 /* bit 6: 0 to flag */ 3096f45ec7bSml29623 #define TX_ENT_MSK_PKT_SIZE_ERR_MASK 0x0000000000000040ULL 3106f45ec7bSml29623 #define TX_ENT_MSK_MBOX_ERR_SHIFT 7 /* bit 7: 0 to flag */ 3116f45ec7bSml29623 #define TX_ENT_MSK_MBOX_ERR_MASK 0x0000000000000080ULL 3126f45ec7bSml29623 #define TX_ENT_MSK_MK_SHIFT 15 /* bit 15: 0 to flag */ 3136f45ec7bSml29623 #define TX_ENT_MSK_MK_MASK 0x0000000000008000ULL 3146f45ec7bSml29623 #define TX_ENT_MSK_MK_ALL (TX_ENT_MSK_PKT_PRT_ERR_MASK | \ 3156f45ec7bSml29623 TX_ENT_MSK_CONF_PART_ERR_MASK | \ 3166f45ec7bSml29623 TX_ENT_MSK_NACK_PKT_RD_MASK | \ 3176f45ec7bSml29623 TX_ENT_MSK_NACK_PREF_MASK | \ 3186f45ec7bSml29623 TX_ENT_MSK_PREF_BUF_ECC_ERR_MASK | \ 3196f45ec7bSml29623 TX_ENT_MSK_TX_RING_OFLOW_MASK | \ 3206f45ec7bSml29623 TX_ENT_MSK_PKT_SIZE_ERR_MASK | \ 3216f45ec7bSml29623 TX_ENT_MSK_MBOX_ERR_MASK | \ 3226f45ec7bSml29623 TX_ENT_MSK_MK_MASK) 3236f45ec7bSml29623 3246f45ec7bSml29623 3256f45ec7bSml29623 typedef union _tx_dma_ent_msk_t { 3266f45ec7bSml29623 uint64_t value; 3276f45ec7bSml29623 struct { 3286f45ec7bSml29623 #ifdef _BIG_ENDIAN 3296f45ec7bSml29623 uint32_t hdw; 3306f45ec7bSml29623 #endif 3316f45ec7bSml29623 struct { 3326f45ec7bSml29623 #if defined(_BIT_FIELDS_HTOL) 3336f45ec7bSml29623 uint32_t res1_1:16; 3346f45ec7bSml29623 uint32_t mk:1; 3356f45ec7bSml29623 uint32_t res2:7; 3366f45ec7bSml29623 uint32_t mbox_err:1; 3376f45ec7bSml29623 uint32_t pkt_size_err:1; 3386f45ec7bSml29623 uint32_t tx_ring_oflow:1; 3396f45ec7bSml29623 uint32_t pref_buf_ecc_err:1; 3406f45ec7bSml29623 uint32_t nack_pref:1; 3416f45ec7bSml29623 uint32_t nack_pkt_rd:1; 3426f45ec7bSml29623 uint32_t conf_part_err:1; 3436f45ec7bSml29623 uint32_t pkt_prt_err:1; 3446f45ec7bSml29623 #elif defined(_BIT_FIELDS_LTOH) 3456f45ec7bSml29623 uint32_t pkt_prt_err:1; 3466f45ec7bSml29623 uint32_t conf_part_err:1; 3476f45ec7bSml29623 uint32_t nack_pkt_rd:1; 3486f45ec7bSml29623 uint32_t nack_pref:1; 3496f45ec7bSml29623 uint32_t pref_buf_ecc_err:1; 3506f45ec7bSml29623 uint32_t tx_ring_oflow:1; 3516f45ec7bSml29623 uint32_t pkt_size_err:1; 3526f45ec7bSml29623 uint32_t mbox_err:1; 3536f45ec7bSml29623 uint32_t res2:7; 3546f45ec7bSml29623 uint32_t mk:1; 3556f45ec7bSml29623 uint32_t res1_1:16; 3566f45ec7bSml29623 #endif 3576f45ec7bSml29623 } ldw; 3586f45ec7bSml29623 #ifndef _BIG_ENDIAN 3596f45ec7bSml29623 uint32_t hdw; 3606f45ec7bSml29623 #endif 3616f45ec7bSml29623 } bits; 3626f45ec7bSml29623 } tx_dma_ent_msk_t, *p_tx_dma_ent_msk_t; 3636f45ec7bSml29623 3646f45ec7bSml29623 3656f45ec7bSml29623 /* Transmit Control and Status (DMC + 0x40028) */ 3666f45ec7bSml29623 #define TX_CS_PKT_PRT_ERR_SHIFT 0 /* RO, bit 0 */ 3676f45ec7bSml29623 #define TX_CS_PKT_PRT_ERR_MASK 0x0000000000000001ULL 3686f45ec7bSml29623 #define TX_CS_CONF_PART_ERR_SHIF 1 /* RO, bit 1 */ 3696f45ec7bSml29623 #define TX_CS_CONF_PART_ERR_MASK 0x0000000000000002ULL 3706f45ec7bSml29623 #define TX_CS_NACK_PKT_RD_SHIFT 2 /* RO, bit 2 */ 3716f45ec7bSml29623 #define TX_CS_NACK_PKT_RD_MASK 0x0000000000000004ULL 3726f45ec7bSml29623 #define TX_CS_PREF_SHIFT 3 /* RO, bit 3 */ 3736f45ec7bSml29623 #define TX_CS_PREF_MASK 0x0000000000000008ULL 3746f45ec7bSml29623 #define TX_CS_PREF_BUF_PAR_ERR_SHIFT 4 /* RO, bit 4 */ 3756f45ec7bSml29623 #define TX_CS_PREF_BUF_PAR_ERR_MASK 0x0000000000000010ULL 3766f45ec7bSml29623 #define TX_CS_RING_OFLOW_SHIFT 5 /* RO, bit 5 */ 3776f45ec7bSml29623 #define TX_CS_RING_OFLOW_MASK 0x0000000000000020ULL 3786f45ec7bSml29623 #define TX_CS_PKT_SIZE_ERR_SHIFT 6 /* RW, bit 6 */ 3796f45ec7bSml29623 #define TX_CS_PKT_SIZE_ERR_MASK 0x0000000000000040ULL 3806f45ec7bSml29623 #define TX_CS_MMK_SHIFT 14 /* RC, bit 14 */ 3816f45ec7bSml29623 #define TX_CS_MMK_MASK 0x0000000000004000ULL 3826f45ec7bSml29623 #define TX_CS_MK_SHIFT 15 /* RCW1C, bit 15 */ 3836f45ec7bSml29623 #define TX_CS_MK_MASK 0x0000000000008000ULL 3846f45ec7bSml29623 #define TX_CS_SNG_SHIFT 27 /* RO, bit 27 */ 3856f45ec7bSml29623 #define TX_CS_SNG_MASK 0x0000000008000000ULL 3866f45ec7bSml29623 #define TX_CS_STOP_N_GO_SHIFT 28 /* RW, bit 28 */ 3876f45ec7bSml29623 #define TX_CS_STOP_N_GO_MASK 0x0000000010000000ULL 3886f45ec7bSml29623 #define TX_CS_MB_SHIFT 29 /* RO, bit 29 */ 3896f45ec7bSml29623 #define TX_CS_MB_MASK 0x0000000020000000ULL 3906f45ec7bSml29623 #define TX_CS_RST_STATE_SHIFT 30 /* Rw, bit 30 */ 3916f45ec7bSml29623 #define TX_CS_RST_STATE_MASK 0x0000000040000000ULL 3926f45ec7bSml29623 #define TX_CS_RST_SHIFT 31 /* Rw, bit 31 */ 3936f45ec7bSml29623 #define TX_CS_RST_MASK 0x0000000080000000ULL 3946f45ec7bSml29623 #define TX_CS_LASTMASK_SHIFT 32 /* RW, bit 43:32 */ 3956f45ec7bSml29623 #define TX_CS_LASTMARK_MASK 0x00000FFF00000000ULL 3966f45ec7bSml29623 #define TX_CS_PKT_CNT_SHIFT 48 /* RW, bit 59:48 */ 3976f45ec7bSml29623 #define TX_CS_PKT_CNT_MASK 0x0FFF000000000000ULL 3986f45ec7bSml29623 3996f45ec7bSml29623 /* Trasnmit Control and Status */ 4006f45ec7bSml29623 typedef union _tx_cs_t { 4016f45ec7bSml29623 uint64_t value; 4026f45ec7bSml29623 struct { 4036f45ec7bSml29623 #ifdef _BIG_ENDIAN 4046f45ec7bSml29623 struct { 4056f45ec7bSml29623 #if defined(_BIT_FIELDS_HTOL) 4066f45ec7bSml29623 uint32_t res1:4; 4076f45ec7bSml29623 uint32_t pkt_cnt:12; 4086f45ec7bSml29623 uint32_t res2:4; 4096f45ec7bSml29623 uint32_t lastmark:12; 4106f45ec7bSml29623 #elif defined(_BIT_FIELDS_LTOH) 4116f45ec7bSml29623 uint32_t lastmark:12; 4126f45ec7bSml29623 uint32_t res2:4; 4136f45ec7bSml29623 uint32_t pkt_cnt:12; 4146f45ec7bSml29623 uint32_t res1:4; 4156f45ec7bSml29623 #endif 4166f45ec7bSml29623 } hdw; 4176f45ec7bSml29623 4186f45ec7bSml29623 #endif 4196f45ec7bSml29623 struct { 4206f45ec7bSml29623 #if defined(_BIT_FIELDS_HTOL) 4216f45ec7bSml29623 uint32_t rst:1; 4226f45ec7bSml29623 uint32_t rst_state:1; 4236f45ec7bSml29623 uint32_t mb:1; 4246f45ec7bSml29623 uint32_t stop_n_go:1; 4256f45ec7bSml29623 uint32_t sng_state:1; 4266f45ec7bSml29623 uint32_t res1:11; 4276f45ec7bSml29623 uint32_t mk:1; 4286f45ec7bSml29623 uint32_t mmk:1; 4296f45ec7bSml29623 uint32_t res2:6; 4306f45ec7bSml29623 uint32_t mbox_err:1; 4316f45ec7bSml29623 uint32_t pkt_size_err:1; 4326f45ec7bSml29623 uint32_t tx_ring_oflow:1; 4336f45ec7bSml29623 uint32_t pref_buf_par_err:1; 4346f45ec7bSml29623 uint32_t nack_pref:1; 4356f45ec7bSml29623 uint32_t nack_pkt_rd:1; 4366f45ec7bSml29623 uint32_t conf_part_err:1; 4376f45ec7bSml29623 uint32_t pkt_prt_err:1; 4386f45ec7bSml29623 #elif defined(_BIT_FIELDS_LTOH) 4396f45ec7bSml29623 uint32_t pkt_prt_err:1; 4406f45ec7bSml29623 uint32_t conf_part_err:1; 4416f45ec7bSml29623 uint32_t nack_pkt_rd:1; 4426f45ec7bSml29623 uint32_t nack_pref:1; 4436f45ec7bSml29623 uint32_t pref_buf_par_err:1; 4446f45ec7bSml29623 uint32_t tx_ring_oflow:1; 4456f45ec7bSml29623 uint32_t pkt_size_err:1; 4466f45ec7bSml29623 uint32_t mbox_err:1; 4476f45ec7bSml29623 uint32_t res2:6; 4486f45ec7bSml29623 uint32_t mmk:1; 4496f45ec7bSml29623 uint32_t mk:1; 4506f45ec7bSml29623 uint32_t res1:11; 4516f45ec7bSml29623 uint32_t sng_state:1; 4526f45ec7bSml29623 uint32_t stop_n_go:1; 4536f45ec7bSml29623 uint32_t mb:1; 4546f45ec7bSml29623 uint32_t rst_state:1; 4556f45ec7bSml29623 uint32_t rst:1; 4566f45ec7bSml29623 #endif 4576f45ec7bSml29623 } ldw; 4586f45ec7bSml29623 #ifndef _BIG_ENDIAN 4596f45ec7bSml29623 struct { 4606f45ec7bSml29623 #if defined(_BIT_FIELDS_HTOL) 4616f45ec7bSml29623 uint32_t res1:4; 4626f45ec7bSml29623 uint32_t pkt_cnt:12; 4636f45ec7bSml29623 uint32_t res2:4; 4646f45ec7bSml29623 uint32_t lastmark:12; 4656f45ec7bSml29623 #elif defined(_BIT_FIELDS_LTOH) 4666f45ec7bSml29623 uint32_t lastmark:12; 4676f45ec7bSml29623 uint32_t res2:4; 4686f45ec7bSml29623 uint32_t pkt_cnt:12; 4696f45ec7bSml29623 uint32_t res1:4; 4706f45ec7bSml29623 #endif 4716f45ec7bSml29623 } hdw; 4726f45ec7bSml29623 4736f45ec7bSml29623 #endif 4746f45ec7bSml29623 } bits; 4756f45ec7bSml29623 } tx_cs_t, *p_tx_cs_t; 4766f45ec7bSml29623 4776f45ec7bSml29623 /* Trasnmit Mailbox High (DMC + 0x40030) */ 4786f45ec7bSml29623 #define TXDMA_MBH_SHIFT 0 /* bit 11:0 */ 4796f45ec7bSml29623 #define TXDMA_MBH_ADDR_SHIFT 32 /* bit 43:32 */ 4806f45ec7bSml29623 #define TXDMA_MBH_MASK 0x0000000000000FFFULL 4816f45ec7bSml29623 4826f45ec7bSml29623 typedef union _txdma_mbh_t { 4836f45ec7bSml29623 uint64_t value; 4846f45ec7bSml29623 struct { 4856f45ec7bSml29623 #ifdef _BIG_ENDIAN 4866f45ec7bSml29623 uint32_t hdw; 4876f45ec7bSml29623 #endif 4886f45ec7bSml29623 struct { 4896f45ec7bSml29623 #if defined(_BIT_FIELDS_HTOL) 4906f45ec7bSml29623 uint32_t res1_1:20; 4916f45ec7bSml29623 uint32_t mbaddr:12; 4926f45ec7bSml29623 4936f45ec7bSml29623 #elif defined(_BIT_FIELDS_LTOH) 4946f45ec7bSml29623 uint32_t mbaddr:12; 4956f45ec7bSml29623 uint32_t res1_1:20; 4966f45ec7bSml29623 #endif 4976f45ec7bSml29623 } ldw; 4986f45ec7bSml29623 #ifndef _BIG_ENDIAN 4996f45ec7bSml29623 uint32_t hdw; 5006f45ec7bSml29623 #endif 5016f45ec7bSml29623 } bits; 5026f45ec7bSml29623 } txdma_mbh_t, *p_txdma_mbh_t; 5036f45ec7bSml29623 5046f45ec7bSml29623 5056f45ec7bSml29623 /* Trasnmit Mailbox Low (DMC + 0x40038) */ 5066f45ec7bSml29623 #define TXDMA_MBL_SHIFT 6 /* bit 31:6 */ 5076f45ec7bSml29623 #define TXDMA_MBL_MASK 0x00000000FFFFFFC0ULL 5086f45ec7bSml29623 5096f45ec7bSml29623 typedef union _txdma_mbl_t { 5106f45ec7bSml29623 uint64_t value; 5116f45ec7bSml29623 struct { 5126f45ec7bSml29623 #ifdef _BIG_ENDIAN 5136f45ec7bSml29623 uint32_t hdw; 5146f45ec7bSml29623 #endif 5156f45ec7bSml29623 struct { 5166f45ec7bSml29623 #if defined(_BIT_FIELDS_HTOL) 5176f45ec7bSml29623 uint32_t mbaddr:26; 5186f45ec7bSml29623 uint32_t res2:6; 5196f45ec7bSml29623 5206f45ec7bSml29623 #elif defined(_BIT_FIELDS_LTOH) 5216f45ec7bSml29623 uint32_t res2:6; 5226f45ec7bSml29623 uint32_t mbaddr:26; 5236f45ec7bSml29623 #endif 5246f45ec7bSml29623 } ldw; 5256f45ec7bSml29623 #ifndef _BIG_ENDIAN 5266f45ec7bSml29623 uint32_t hdw; 5276f45ec7bSml29623 #endif 5286f45ec7bSml29623 } bits; 5296f45ec7bSml29623 } txdma_mbl_t, *p_txdma_mbl_t; 5306f45ec7bSml29623 5316f45ec7bSml29623 /* Trasnmit Prefetch State High (DMC + 0x40040) */ 5326f45ec7bSml29623 #define TX_DMA_PREF_ST_SHIFT 0 /* bit 5:0 */ 5336f45ec7bSml29623 #define TX_DMA_PREF_ST_MASK 0x000000000000003FULL 5346f45ec7bSml29623 5356f45ec7bSml29623 typedef union _tx_dma_pre_st_t { 5366f45ec7bSml29623 uint64_t value; 5376f45ec7bSml29623 struct { 5386f45ec7bSml29623 #ifdef _BIG_ENDIAN 5396f45ec7bSml29623 uint32_t hdw; 5406f45ec7bSml29623 #endif 5416f45ec7bSml29623 struct { 5426f45ec7bSml29623 #if defined(_BIT_FIELDS_HTOL) 5436f45ec7bSml29623 uint32_t res1_1:13; 5446f45ec7bSml29623 uint32_t shadow_hd:19; 5456f45ec7bSml29623 #elif defined(_BIT_FIELDS_LTOH) 5466f45ec7bSml29623 uint32_t shadow_hd:19; 5476f45ec7bSml29623 uint32_t res1_1:13; 5486f45ec7bSml29623 #endif 5496f45ec7bSml29623 } ldw; 5506f45ec7bSml29623 #ifndef _BIG_ENDIAN 5516f45ec7bSml29623 uint32_t hdw; 5526f45ec7bSml29623 #endif 5536f45ec7bSml29623 } bits; 5546f45ec7bSml29623 } tx_dma_pre_st_t, *p_tx_dma_pre_st_t; 5556f45ec7bSml29623 5566f45ec7bSml29623 /* Trasnmit Ring Error Log High (DMC + 0x40048) */ 5576f45ec7bSml29623 #define TX_RNG_ERR_LOGH_ERR_ADDR_SHIFT 0 /* RO bit 11:0 */ 5586f45ec7bSml29623 #define TX_RNG_ERR_LOGH_ERR_ADDR_MASK 0x0000000000000FFFULL 5596f45ec7bSml29623 #define TX_RNG_ERR_LOGH_ADDR_SHIFT 32 5606f45ec7bSml29623 #define TX_RNG_ERR_LOGH_ERRCODE_SHIFT 26 /* RO bit 29:26 */ 5616f45ec7bSml29623 #define TX_RNG_ERR_LOGH_ERRCODE_MASK 0x000000003C000000ULL 5626f45ec7bSml29623 #define TX_RNG_ERR_LOGH_MERR_SHIFT 30 /* RO bit 30 */ 5636f45ec7bSml29623 #define TX_RNG_ERR_LOGH_MERR_MASK 0x0000000040000000ULL 5646f45ec7bSml29623 #define TX_RNG_ERR_LOGH_ERR_SHIFT 31 /* RO bit 31 */ 5656f45ec7bSml29623 #define TX_RNG_ERR_LOGH_ERR_MASK 0x0000000080000000ULL 5666f45ec7bSml29623 5676f45ec7bSml29623 /* Transmit Ring Error codes */ 5686f45ec7bSml29623 #define TXDMA_RING_PKT_PRT_ERR 0 5696f45ec7bSml29623 #define TXDMA_RING_CONF_PART_ERR 0x01 5706f45ec7bSml29623 #define TXDMA_RING_NACK_PKT_ERR 0x02 5716f45ec7bSml29623 #define TXDMA_RING_NACK_PREF_ERR 0x03 5726f45ec7bSml29623 #define TXDMA_RING_PREF_BUF_PAR_ERR 0x04 5736f45ec7bSml29623 #define TXDMA_RING_TX_RING_OFLOW_ERR 0x05 5746f45ec7bSml29623 #define TXDMA_RING_PKT_SIZE_ERR 0x06 5756f45ec7bSml29623 5766f45ec7bSml29623 typedef union _tx_rng_err_logh_t { 5776f45ec7bSml29623 uint64_t value; 5786f45ec7bSml29623 struct { 5796f45ec7bSml29623 #ifdef _BIG_ENDIAN 5806f45ec7bSml29623 uint32_t hdw; 5816f45ec7bSml29623 #endif 5826f45ec7bSml29623 struct { 5836f45ec7bSml29623 #if defined(_BIT_FIELDS_HTOL) 5846f45ec7bSml29623 uint32_t err:1; 5856f45ec7bSml29623 uint32_t merr:1; 5866f45ec7bSml29623 uint32_t errcode:4; 5876f45ec7bSml29623 uint32_t res2:14; 5886f45ec7bSml29623 uint32_t err_addr:12; 5896f45ec7bSml29623 #elif defined(_BIT_FIELDS_LTOH) 5906f45ec7bSml29623 uint32_t err_addr:12; 5916f45ec7bSml29623 uint32_t res2:14; 5926f45ec7bSml29623 uint32_t errcode:4; 5936f45ec7bSml29623 uint32_t merr:1; 5946f45ec7bSml29623 uint32_t err:1; 5956f45ec7bSml29623 5966f45ec7bSml29623 #endif 5976f45ec7bSml29623 } ldw; 5986f45ec7bSml29623 #ifndef _BIG_ENDIAN 5996f45ec7bSml29623 uint32_t hdw; 6006f45ec7bSml29623 #endif 6016f45ec7bSml29623 } bits; 6026f45ec7bSml29623 } tx_rng_err_logh_t, *p_tx_rng_err_logh_t; 6036f45ec7bSml29623 6046f45ec7bSml29623 6056f45ec7bSml29623 /* Trasnmit Ring Error Log Log (DMC + 0x40050) */ 6066f45ec7bSml29623 #define TX_RNG_ERR_LOGL_ERR_ADDR_SHIFT 0 /* RO bit 31:0 */ 6076f45ec7bSml29623 #define TX_RNG_ERR_LOGL_ERR_ADDR_MASK 0x00000000FFFFFFFFULL 6086f45ec7bSml29623 6096f45ec7bSml29623 typedef union _tx_rng_err_logl_t { 6106f45ec7bSml29623 uint64_t value; 6116f45ec7bSml29623 struct { 6126f45ec7bSml29623 #ifdef _BIG_ENDIAN 6136f45ec7bSml29623 uint32_t hdw; 6146f45ec7bSml29623 #endif 6156f45ec7bSml29623 struct { 6166f45ec7bSml29623 #if defined(_BIT_FIELDS_HTOL) 6176f45ec7bSml29623 uint32_t err_addr:32; 6186f45ec7bSml29623 #elif defined(_BIT_FIELDS_LTOH) 6196f45ec7bSml29623 uint32_t err_addr:32; 6206f45ec7bSml29623 6216f45ec7bSml29623 #endif 6226f45ec7bSml29623 } ldw; 6236f45ec7bSml29623 #ifndef _BIG_ENDIAN 6246f45ec7bSml29623 uint32_t hdw; 6256f45ec7bSml29623 #endif 6266f45ec7bSml29623 } bits; 6276f45ec7bSml29623 } tx_rng_err_logl_t, *p_tx_rng_err_logl_t; 6286f45ec7bSml29623 6296f45ec7bSml29623 /* 6306f45ec7bSml29623 * TDMC_INTR_RBG_REG (DMC + 0x40060) 6316f45ec7bSml29623 */ 6326f45ec7bSml29623 typedef union _tdmc_intr_dbg_t { 6336f45ec7bSml29623 uint64_t value; 6346f45ec7bSml29623 struct { 6356f45ec7bSml29623 #ifdef _BIG_ENDIAN 6366f45ec7bSml29623 uint32_t hdw; 6376f45ec7bSml29623 #endif 6386f45ec7bSml29623 struct { 6396f45ec7bSml29623 #if defined(_BIT_FIELDS_HTOL) 6406f45ec7bSml29623 uint32_t res:16; 6416f45ec7bSml29623 uint32_t mk:1; 6426f45ec7bSml29623 uint32_t rsvd:7; 6436f45ec7bSml29623 uint32_t mbox_err:1; 6446f45ec7bSml29623 uint32_t pkt_size_err:1; 6456f45ec7bSml29623 uint32_t tx_ring_oflow:1; 6466f45ec7bSml29623 uint32_t pref_buf_par_err:1; 6476f45ec7bSml29623 uint32_t nack_pref:1; 6486f45ec7bSml29623 uint32_t nack_pkt_rd:1; 6496f45ec7bSml29623 uint32_t conf_part_err:1; 6506f45ec7bSml29623 uint32_t pkt_part_err:1; 6516f45ec7bSml29623 #elif defined(_BIT_FIELDS_LTOH) 6526f45ec7bSml29623 uint32_t pkt_part_err:1; 6536f45ec7bSml29623 uint32_t conf_part_err:1; 6546f45ec7bSml29623 uint32_t nack_pkt_rd:1; 6556f45ec7bSml29623 uint32_t nack_pref:1; 6566f45ec7bSml29623 uint32_t pref_buf_par_err:1; 6576f45ec7bSml29623 uint32_t tx_ring_oflow:1; 6586f45ec7bSml29623 uint32_t pkt_size_err:1; 6596f45ec7bSml29623 uint32_t mbox_err:1; 6606f45ec7bSml29623 uint32_t rsvd:7; 6616f45ec7bSml29623 uint32_t mk:1; 6626f45ec7bSml29623 uint32_t res:16; 6636f45ec7bSml29623 #endif 6646f45ec7bSml29623 } ldw; 6656f45ec7bSml29623 #ifndef _BIG_ENDIAN 6666f45ec7bSml29623 uint32_t hdw; 6676f45ec7bSml29623 #endif 6686f45ec7bSml29623 } bits; 6696f45ec7bSml29623 } tdmc_intr_dbg_t, *p_tdmc_intr_dbg_t; 6706f45ec7bSml29623 6716f45ec7bSml29623 6726f45ec7bSml29623 /* 6736f45ec7bSml29623 * TX_CS_DBG (DMC + 0x40068) 6746f45ec7bSml29623 */ 6756f45ec7bSml29623 typedef union _tx_cs_dbg_t { 6766f45ec7bSml29623 uint64_t value; 6776f45ec7bSml29623 struct { 6786f45ec7bSml29623 #ifdef _BIG_ENDIAN 6796f45ec7bSml29623 struct { 6806f45ec7bSml29623 #if defined(_BIT_FIELDS_HTOL) 6816f45ec7bSml29623 uint32_t res1:4; 6826f45ec7bSml29623 uint32_t pkt_cnt:12; 6836f45ec7bSml29623 uint32_t res2:16; 6846f45ec7bSml29623 #elif defined(_BIT_FIELDS_LTOH) 6856f45ec7bSml29623 uint32_t res2:16; 6866f45ec7bSml29623 uint32_t pkt_cnt:12; 6876f45ec7bSml29623 uint32_t res1:4; 6886f45ec7bSml29623 #endif 6896f45ec7bSml29623 } hdw; 6906f45ec7bSml29623 6916f45ec7bSml29623 #endif 6926f45ec7bSml29623 struct { 6936f45ec7bSml29623 #if defined(_BIT_FIELDS_HTOL) 6946f45ec7bSml29623 uint32_t rsvd:32; 6956f45ec7bSml29623 #elif defined(_BIT_FIELDS_LTOH) 6966f45ec7bSml29623 uint32_t rsvd:32; 6976f45ec7bSml29623 6986f45ec7bSml29623 #endif 6996f45ec7bSml29623 } ldw; 7006f45ec7bSml29623 7016f45ec7bSml29623 #ifndef _BIG_ENDIAN 7026f45ec7bSml29623 struct { 7036f45ec7bSml29623 #if defined(_BIT_FIELDS_HTOL) 7046f45ec7bSml29623 uint32_t res1:4; 7056f45ec7bSml29623 uint32_t pkt_cnt:12; 7066f45ec7bSml29623 uint32_t res2:16; 7076f45ec7bSml29623 #elif defined(_BIT_FIELDS_LTOH) 7086f45ec7bSml29623 uint32_t res2:16; 7096f45ec7bSml29623 uint32_t pkt_cnt:12; 7106f45ec7bSml29623 uint32_t res1:4; 7116f45ec7bSml29623 #endif 7126f45ec7bSml29623 } hdw; 7136f45ec7bSml29623 7146f45ec7bSml29623 #endif 7156f45ec7bSml29623 } bits; 7166f45ec7bSml29623 } tx_cs_dbg_t, *p_tx_cs_dbg_t; 7176f45ec7bSml29623 7186f45ec7bSml29623 #define TXDMA_MAILBOX_BYTE_LENGTH 64 7196f45ec7bSml29623 #define TXDMA_MAILBOX_UNUSED 24 7206f45ec7bSml29623 7216f45ec7bSml29623 typedef struct _txdma_mailbox_t { 7226f45ec7bSml29623 tx_cs_t tx_cs; /* 8 bytes */ 7236f45ec7bSml29623 tx_dma_pre_st_t tx_dma_pre_st; /* 8 bytes */ 7246f45ec7bSml29623 tx_ring_hdl_t tx_ring_hdl; /* 8 bytes */ 7256f45ec7bSml29623 tx_ring_kick_t tx_ring_kick; /* 8 bytes */ 7266f45ec7bSml29623 uint32_t tx_rng_err_logh; /* 4 bytes */ 7276f45ec7bSml29623 uint32_t tx_rng_err_logl; /* 4 bytes */ 7286f45ec7bSml29623 uint32_t resv[TXDMA_MAILBOX_UNUSED]; 7296f45ec7bSml29623 } txdma_mailbox_t, *p_txdma_mailbox_t; 7306f45ec7bSml29623 7316f45ec7bSml29623 #if OLD 7326f45ec7bSml29623 /* Transmit Ring Scheduler (per port) */ 7336f45ec7bSml29623 #define TX_DMA_MAP_OFFSET(port) (port * 8 + TX_DMA_MAP_REG) 7346f45ec7bSml29623 #define TX_DMA_MAP_PORT_OFFSET(port) (port * 8) 7356f45ec7bSml29623 #define TX_DMA_MAP_REG (FZC_DMC + 0x50000) 7366f45ec7bSml29623 #define TX_DMA_MAP0_REG (FZC_DMC + 0x50000) 7376f45ec7bSml29623 #define TX_DMA_MAP1_REG (FZC_DMC + 0x50008) 7386f45ec7bSml29623 #define TX_DMA_MAP2_REG (FZC_DMC + 0x50010) 7396f45ec7bSml29623 #define TX_DMA_MAP3_REG (FZC_DMC + 0x50018) 7406f45ec7bSml29623 7416f45ec7bSml29623 #define TX_DMA_MAP_SHIFT 0 /* RO bit 31:0 */ 7426f45ec7bSml29623 #define TX_DMA_MAPMASK 0x00000000FFFFFFFFULL 7436f45ec7bSml29623 7446f45ec7bSml29623 typedef union _tx_dma_map_t { 7456f45ec7bSml29623 uint64_t value; 7466f45ec7bSml29623 struct { 7476f45ec7bSml29623 #ifdef _BIG_ENDIAN 7486f45ec7bSml29623 uint32_t hdw; 7496f45ec7bSml29623 #endif 7506f45ec7bSml29623 struct { 7516f45ec7bSml29623 #if defined(_BIT_FIELDS_HTOL) 7526f45ec7bSml29623 uint32_t bind:32; 7536f45ec7bSml29623 #elif defined(_BIT_FIELDS_LTOH) 7546f45ec7bSml29623 uint32_t bind:32; 7556f45ec7bSml29623 7566f45ec7bSml29623 #endif 7576f45ec7bSml29623 } ldw; 7586f45ec7bSml29623 #ifndef _BIG_ENDIAN 7596f45ec7bSml29623 uint32_t hdw; 7606f45ec7bSml29623 #endif 7616f45ec7bSml29623 } bits; 7626f45ec7bSml29623 } tx_dma_map_t, *p_tx_dma_map_t; 7636f45ec7bSml29623 #endif 7646f45ec7bSml29623 7656f45ec7bSml29623 #if OLD 7666f45ec7bSml29623 /* Transmit Ring Scheduler: DRR Weight (32 Channels) */ 7676f45ec7bSml29623 #define DRR_WT_REG (FZC_DMC + 0x51000) 7686f45ec7bSml29623 #define DRR_WT_SHIFT 0 /* RO bit 19:0 */ 7696f45ec7bSml29623 #define DRR_WT_MASK 0x00000000000FFFFFULL 7706f45ec7bSml29623 7716f45ec7bSml29623 #define TXDMA_DRR_RNG_USE_OFFSET(channel) (channel * 16) 7726f45ec7bSml29623 7736f45ec7bSml29623 typedef union _drr_wt_t { 7746f45ec7bSml29623 uint64_t value; 7756f45ec7bSml29623 struct { 7766f45ec7bSml29623 #ifdef _BIG_ENDIAN 7776f45ec7bSml29623 uint32_t hdw; 7786f45ec7bSml29623 #endif 7796f45ec7bSml29623 struct { 7806f45ec7bSml29623 #if defined(_BIT_FIELDS_HTOL) 7816f45ec7bSml29623 uint32_t res1_1:12; 7826f45ec7bSml29623 uint32_t wt:20; 7836f45ec7bSml29623 #elif defined(_BIT_FIELDS_LTOH) 7846f45ec7bSml29623 uint32_t wt:20; 7856f45ec7bSml29623 uint32_t res1_1:12; 7866f45ec7bSml29623 #endif 7876f45ec7bSml29623 } ldw; 7886f45ec7bSml29623 #ifndef _BIG_ENDIAN 7896f45ec7bSml29623 uint32_t hdw; 7906f45ec7bSml29623 #endif 7916f45ec7bSml29623 } bits; 7926f45ec7bSml29623 } drr_wt_t, *p_drr_wt_t; 7936f45ec7bSml29623 #endif 7946f45ec7bSml29623 7956f45ec7bSml29623 #if OLD 7966f45ec7bSml29623 7976f45ec7bSml29623 /* Performance Monitoring (32 Channels) */ 7986f45ec7bSml29623 #define TXRNG_USE_REG (FZC_DMC + 0x51008) 7996f45ec7bSml29623 #define TXRNG_USE_CNT_SHIFT 0 /* RO bit 26:0 */ 8006f45ec7bSml29623 #define TXRNG_USE_CNT_MASK 0x0000000007FFFFFFULL 8016f45ec7bSml29623 #define TXRNG_USE_OFLOW_SHIFT 0 /* RO bit 27 */ 8026f45ec7bSml29623 #define TXRNG_USE_OFLOW_MASK 0x0000000008000000ULL 8036f45ec7bSml29623 8046f45ec7bSml29623 typedef union _txrng_use_t { 8056f45ec7bSml29623 uint64_t value; 8066f45ec7bSml29623 struct { 8076f45ec7bSml29623 #ifdef _BIG_ENDIAN 8086f45ec7bSml29623 uint32_t hdw; 8096f45ec7bSml29623 #endif 8106f45ec7bSml29623 struct { 8116f45ec7bSml29623 #if defined(_BIT_FIELDS_HTOL) 8126f45ec7bSml29623 uint32_t res1_1:4; 8136f45ec7bSml29623 uint32_t oflow:1; 8146f45ec7bSml29623 uint32_t cnt:27; 8156f45ec7bSml29623 #elif defined(_BIT_FIELDS_LTOH) 8166f45ec7bSml29623 uint32_t cnt:27; 8176f45ec7bSml29623 uint32_t oflow:1; 8186f45ec7bSml29623 uint32_t res1_1:4; 8196f45ec7bSml29623 8206f45ec7bSml29623 #endif 8216f45ec7bSml29623 } ldw; 8226f45ec7bSml29623 #ifndef _BIG_ENDIAN 8236f45ec7bSml29623 uint32_t hdw; 8246f45ec7bSml29623 #endif 8256f45ec7bSml29623 } bits; 8266f45ec7bSml29623 } txrng_use_t, *p_txrng_use_t; 8276f45ec7bSml29623 8286f45ec7bSml29623 #endif 8296f45ec7bSml29623 8306f45ec7bSml29623 /* 8316f45ec7bSml29623 * Internal Transmit Packet Format (16 bytes) 8326f45ec7bSml29623 */ 8336f45ec7bSml29623 #define TX_PKT_HEADER_SIZE 16 8346f45ec7bSml29623 #define TX_MAX_GATHER_POINTERS 15 8356f45ec7bSml29623 #define TX_GATHER_POINTERS_THRESHOLD 8 8366f45ec7bSml29623 /* 8376f45ec7bSml29623 * There is bugs in the hardware 8386f45ec7bSml29623 * and max sfter len is changed from 4096 to 4076. 8396f45ec7bSml29623 * 8406f45ec7bSml29623 * Jumbo from 9500 to 9216 8416f45ec7bSml29623 */ 8426f45ec7bSml29623 #define TX_MAX_TRANSFER_LENGTH 4076 8436f45ec7bSml29623 #define TX_JUMBO_MTU 9216 8446f45ec7bSml29623 8456f45ec7bSml29623 #define TX_PKT_HEADER_PAD_SHIFT 0 /* bit 2:0 */ 8466f45ec7bSml29623 #define TX_PKT_HEADER_PAD_MASK 0x0000000000000007ULL 8476f45ec7bSml29623 #define TX_PKT_HEADER_TOT_XFER_LEN_SHIFT 16 /* bit 16:29 */ 8486f45ec7bSml29623 #define TX_PKT_HEADER_TOT_XFER_LEN_MASK 0x000000000000FFF8ULL 8496f45ec7bSml29623 #define TX_PKT_HEADER_L4STUFF_SHIFT 32 /* bit 37:32 */ 8506f45ec7bSml29623 #define TX_PKT_HEADER_L4STUFF_MASK 0x0000003F00000000ULL 8516f45ec7bSml29623 #define TX_PKT_HEADER_L4START_SHIFT 40 /* bit 45:40 */ 8526f45ec7bSml29623 #define TX_PKT_HEADER_L4START_MASK 0x00003F0000000000ULL 8536f45ec7bSml29623 #define TX_PKT_HEADER_L3START_SHIFT 48 /* bit 45:40 */ 8546f45ec7bSml29623 #define TX_PKT_HEADER_IHL_SHIFT 52 /* bit 52 */ 8556f45ec7bSml29623 #define TX_PKT_HEADER_VLAN__SHIFT 56 /* bit 56 */ 8566f45ec7bSml29623 #define TX_PKT_HEADER_TCP_UDP_CRC32C_SHIFT 57 /* bit 57 */ 8576f45ec7bSml29623 #define TX_PKT_HEADER_LLC_SHIFT 57 /* bit 57 */ 8586f45ec7bSml29623 #define TX_PKT_HEADER_TCP_UDP_CRC32C_SET 0x0200000000000000ULL 8596f45ec7bSml29623 #define TX_PKT_HEADER_TCP_UDP_CRC32C_MASK 0x0200000000000000ULL 8606f45ec7bSml29623 #define TX_PKT_HEADER_L4_PROTO_OP_SHIFT 2 /* bit 59:58 */ 8616f45ec7bSml29623 #define TX_PKT_HEADER_L4_PROTO_OP_MASK 0x0C00000000000000ULL 8626f45ec7bSml29623 #define TX_PKT_HEADER_V4_HDR_CS_SHIFT 60 /* bit 60 */ 8636f45ec7bSml29623 #define TX_PKT_HEADER_V4_HDR_CS_SET 0x1000000000000000ULL 8646f45ec7bSml29623 #define TX_PKT_HEADER_V4_HDR_CS_MASK 0x1000000000000000ULL 8656f45ec7bSml29623 #define TX_PKT_HEADER_IP_VER_SHIFT 61 /* bit 61 */ 8666f45ec7bSml29623 #define TX_PKT_HEADER_IP_VER_MASK 0x2000000000000000ULL 8676f45ec7bSml29623 #define TX_PKT_HEADER_PKT_TYPE_SHIFT 62 /* bit 62 */ 8686f45ec7bSml29623 #define TX_PKT_HEADER_PKT_TYPE_MASK 0x4000000000000000ULL 8696f45ec7bSml29623 8706f45ec7bSml29623 /* L4 Prototol Operations */ 8716f45ec7bSml29623 #define TX_PKT_L4_PROTO_OP_NOP 0x00 8726f45ec7bSml29623 #define TX_PKT_L4_PROTO_OP_FULL_L4_CSUM 0x01 8736f45ec7bSml29623 #define TX_PKT_L4_PROTO_OP_L4_PAYLOAD_CSUM 0x02 8746f45ec7bSml29623 #define TX_PKT_L4_PROTO_OP_SCTP_CRC32 0x04 8756f45ec7bSml29623 8766f45ec7bSml29623 /* Transmit Packet Types */ 8776f45ec7bSml29623 #define TX_PKT_PKT_TYPE_NOP 0x00 8786f45ec7bSml29623 #define TX_PKT_PKT_TYPE_TCP 0x01 8796f45ec7bSml29623 #define TX_PKT_PKT_TYPE_UDP 0x02 8806f45ec7bSml29623 #define TX_PKT_PKT_TYPE_SCTP 0x03 8816f45ec7bSml29623 882*b4d05839Sml29623 #define TX_CKSUM_EN_PKT_TYPE_TCP (1ull << TX_PKT_HEADER_PKT_TYPE_SHIFT) 883*b4d05839Sml29623 #define TX_CKSUM_EN_PKT_TYPE_UDP (2ull << TX_PKT_HEADER_PKT_TYPE_SHIFT) 884*b4d05839Sml29623 #define TX_CKSUM_EN_PKT_TYPE_NOOP (0ull << TX_PKT_HEADER_PKT_TYPE_SHIFT) 885*b4d05839Sml29623 8866f45ec7bSml29623 typedef union _tx_pkt_header_t { 8876f45ec7bSml29623 uint64_t value; 8886f45ec7bSml29623 struct { 8896f45ec7bSml29623 struct { 8906f45ec7bSml29623 #if defined(_BIT_FIELDS_HTOL) 8916f45ec7bSml29623 uint32_t pad:3; 8926f45ec7bSml29623 uint32_t resv2:13; 8936f45ec7bSml29623 uint32_t tot_xfer_len:14; 8946f45ec7bSml29623 uint32_t resv1:2; 8956f45ec7bSml29623 #elif defined(_BIT_FIELDS_LTOH) 8966f45ec7bSml29623 uint32_t pad:3; 8976f45ec7bSml29623 uint32_t resv2:13; 8986f45ec7bSml29623 uint32_t tot_xfer_len:14; 8996f45ec7bSml29623 uint32_t resv1:2; 9006f45ec7bSml29623 #endif 9016f45ec7bSml29623 } ldw; 9026f45ec7bSml29623 struct { 9036f45ec7bSml29623 #if defined(_BIT_FIELDS_HTOL) 9046f45ec7bSml29623 uint32_t l4stuff:6; 9056f45ec7bSml29623 uint32_t resv3:2; 9066f45ec7bSml29623 uint32_t l4start:6; 9076f45ec7bSml29623 uint32_t resv2:2; 9086f45ec7bSml29623 uint32_t l3start:4; 9096f45ec7bSml29623 uint32_t ihl:4; 9106f45ec7bSml29623 uint32_t vlan:1; 9116f45ec7bSml29623 uint32_t llc:1; 9126f45ec7bSml29623 uint32_t res1:3; 9136f45ec7bSml29623 uint32_t ip_ver:1; 9146f45ec7bSml29623 uint32_t cksum_en_pkt_type:2; 9156f45ec7bSml29623 #elif defined(_BIT_FIELDS_LTOH) 9166f45ec7bSml29623 uint32_t l4stuff:6; 9176f45ec7bSml29623 uint32_t resv3:2; 9186f45ec7bSml29623 uint32_t l4start:6; 9196f45ec7bSml29623 uint32_t resv2:2; 9206f45ec7bSml29623 uint32_t l3start:4; 9216f45ec7bSml29623 uint32_t ihl:4; 9226f45ec7bSml29623 uint32_t vlan:1; 9236f45ec7bSml29623 uint32_t llc:1; 9246f45ec7bSml29623 uint32_t res1:3; 9256f45ec7bSml29623 uint32_t ip_ver:1; 9266f45ec7bSml29623 uint32_t cksum_en_pkt_type:2; 9276f45ec7bSml29623 #endif 9286f45ec7bSml29623 } hdw; 9296f45ec7bSml29623 } bits; 9306f45ec7bSml29623 } tx_pkt_header_t, *p_tx_pkt_header_t; 9316f45ec7bSml29623 9326f45ec7bSml29623 typedef struct _tx_pkt_hdr_all_t { 9336f45ec7bSml29623 tx_pkt_header_t pkthdr; 9346f45ec7bSml29623 uint64_t reserved; 9356f45ec7bSml29623 } tx_pkt_hdr_all_t, *p_tx_pkt_hdr_all_t; 9366f45ec7bSml29623 9376f45ec7bSml29623 /* Debug only registers */ 9386f45ec7bSml29623 #define TDMC_INJ_PAR_ERR_REG (FZC_DMC + 0x45040) 9396f45ec7bSml29623 #define TDMC_INJ_PAR_ERR_MASK 0x0000000000FFFFFFULL 9406f45ec7bSml29623 #define TDMC_INJ_PAR_ERR_MASK_N2 0x000000000000FFFFULL 9416f45ec7bSml29623 9426f45ec7bSml29623 typedef union _tdmc_inj_par_err_t { 9436f45ec7bSml29623 uint64_t value; 9446f45ec7bSml29623 struct { 9456f45ec7bSml29623 #ifdef _BIG_ENDIAN 9466f45ec7bSml29623 uint32_t hdw; 9476f45ec7bSml29623 #endif 9486f45ec7bSml29623 struct { 9496f45ec7bSml29623 #if defined(_BIT_FIELDS_HTOL) 9506f45ec7bSml29623 uint32_t rsvc:8; 9516f45ec7bSml29623 uint32_t inject_parity_error:24; 9526f45ec7bSml29623 #elif defined(_BIT_FIELDS_LTOH) 9536f45ec7bSml29623 uint32_t inject_parity_error:24; 9546f45ec7bSml29623 uint32_t rsvc:8; 9556f45ec7bSml29623 #endif 9566f45ec7bSml29623 } ldw; 9576f45ec7bSml29623 #ifndef _BIG_ENDIAN 9586f45ec7bSml29623 uint32_t hdw; 9596f45ec7bSml29623 #endif 9606f45ec7bSml29623 } bits; 9616f45ec7bSml29623 } tdmc_inj_par_err_t, *p_tdmc_inj_par_err_t; 9626f45ec7bSml29623 9636f45ec7bSml29623 typedef union _tdmc_inj_par_err_n2_t { 9646f45ec7bSml29623 uint64_t value; 9656f45ec7bSml29623 struct { 9666f45ec7bSml29623 #ifdef _BIG_ENDIAN 9676f45ec7bSml29623 uint32_t hdw; 9686f45ec7bSml29623 #endif 9696f45ec7bSml29623 struct { 9706f45ec7bSml29623 #if defined(_BIT_FIELDS_HTOL) 9716f45ec7bSml29623 uint32_t rsvc:16; 9726f45ec7bSml29623 uint32_t inject_parity_error:16; 9736f45ec7bSml29623 #elif defined(_BIT_FIELDS_LTOH) 9746f45ec7bSml29623 uint32_t inject_parity_error:16; 9756f45ec7bSml29623 uint32_t rsvc:16; 9766f45ec7bSml29623 #endif 9776f45ec7bSml29623 } ldw; 9786f45ec7bSml29623 #ifndef _BIG_ENDIAN 9796f45ec7bSml29623 uint32_t hdw; 9806f45ec7bSml29623 #endif 9816f45ec7bSml29623 } bits; 9826f45ec7bSml29623 } tdmc_inj_par_err_n2_t, *p_tdmc_inj_par_err_n2_t; 9836f45ec7bSml29623 9846f45ec7bSml29623 #define TDMC_DBG_SEL_REG (FZC_DMC + 0x45080) 9856f45ec7bSml29623 #define TDMC_DBG_SEL_MASK 0x000000000000003FULL 9866f45ec7bSml29623 9876f45ec7bSml29623 typedef union _tdmc_dbg_sel_t { 9886f45ec7bSml29623 uint64_t value; 9896f45ec7bSml29623 struct { 9906f45ec7bSml29623 #ifdef _BIG_ENDIAN 9916f45ec7bSml29623 uint32_t hdw; 9926f45ec7bSml29623 #endif 9936f45ec7bSml29623 struct { 9946f45ec7bSml29623 #if defined(_BIT_FIELDS_HTOL) 9956f45ec7bSml29623 uint32_t rsvc:26; 9966f45ec7bSml29623 uint32_t dbg_sel:6; 9976f45ec7bSml29623 #elif defined(_BIT_FIELDS_LTOH) 9986f45ec7bSml29623 uint32_t dbg_sel:6; 9996f45ec7bSml29623 uint32_t rsvc:26; 10006f45ec7bSml29623 #endif 10016f45ec7bSml29623 } ldw; 10026f45ec7bSml29623 #ifndef _BIG_ENDIAN 10036f45ec7bSml29623 uint32_t hdw; 10046f45ec7bSml29623 #endif 10056f45ec7bSml29623 } bits; 10066f45ec7bSml29623 } tdmc_dbg_sel_t, *p_tdmc_dbg_sel_t; 10076f45ec7bSml29623 10086f45ec7bSml29623 #define TDMC_TRAINING_REG (FZC_DMC + 0x45088) 10096f45ec7bSml29623 #define TDMC_TRAINING_MASK 0x00000000FFFFFFFFULL 10106f45ec7bSml29623 10116f45ec7bSml29623 typedef union _tdmc_training_t { 10126f45ec7bSml29623 uint64_t value; 10136f45ec7bSml29623 struct { 10146f45ec7bSml29623 #ifdef _BIG_ENDIAN 10156f45ec7bSml29623 uint32_t hdw; 10166f45ec7bSml29623 #endif 10176f45ec7bSml29623 struct { 10186f45ec7bSml29623 #if defined(_BIT_FIELDS_HTOL) 10196f45ec7bSml29623 uint32_t vec:32; 10206f45ec7bSml29623 #elif defined(_BIT_FIELDS_LTOH) 10216f45ec7bSml29623 uint32_t vec:6; 10226f45ec7bSml29623 #endif 10236f45ec7bSml29623 } ldw; 10246f45ec7bSml29623 #ifndef _BIG_ENDIAN 10256f45ec7bSml29623 uint32_t hdw; 10266f45ec7bSml29623 #endif 10276f45ec7bSml29623 } bits; 10286f45ec7bSml29623 } tdmc_training_t, *p_tdmc_training_t; 10296f45ec7bSml29623 10306f45ec7bSml29623 #ifdef __cplusplus 10316f45ec7bSml29623 } 10326f45ec7bSml29623 #endif 10336f45ec7bSml29623 10346f45ec7bSml29623 #endif /* _SYS_NXGE_NXGE_TXDMA_HW_H */ 1035