1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _NV_SATA_H 28 #define _NV_SATA_H 29 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 36 /* 37 * SGPIO Support 38 * Enable SGPIO support only on x86/x64, because it is implemented using 39 * functions that are only available on x86/x64. 40 */ 41 42 #define NV_MAX_PORTS(nvc) nvc->nvc_sata_hba_tran.sata_tran_hba_num_cports 43 44 typedef struct nv_port nv_port_t; 45 46 #ifdef SGPIO_SUPPORT 47 typedef struct nv_sgp_cmn nv_sgp_cmn_t; 48 #endif 49 50 typedef struct nv_ctl { 51 /* 52 * Each of these are specific to the chipset in use. 53 */ 54 uint_t (*nvc_interrupt)(caddr_t arg1, caddr_t arg2); 55 void (*nvc_reg_init)(struct nv_ctl *nvc, 56 ddi_acc_handle_t pci_conf_handle); 57 58 dev_info_t *nvc_dip; /* devinfo pointer of controller */ 59 60 struct nv_port *nvc_port; /* array of pointers to port struct */ 61 62 /* 63 * handle and base address to register space. 64 * 65 * 0: port 0 task file 66 * 1: port 0 status 67 * 2: port 1 task file 68 * 3: port 1 status 69 * 4: bus master for both ports 70 * 5: extended registers for SATA features 71 */ 72 ddi_acc_handle_t nvc_bar_hdl[6]; 73 uchar_t *nvc_bar_addr[6]; 74 75 /* 76 * sata registers in bar 5 which are shared on all devices 77 * on the channel. 78 */ 79 uint32_t *nvc_mcp5x_ctl; 80 uint32_t *nvc_mcp5x_ncq; /* NCQ status control bits */ 81 82 kmutex_t nvc_mutex; /* ctrl level lock */ 83 84 ddi_intr_handle_t *nvc_htable; /* For array of interrupts */ 85 int nvc_intr_type; /* What type of interrupt */ 86 int nvc_intr_cnt; /* # of intrs count returned */ 87 size_t nvc_intr_size; /* Size of intr array to */ 88 uint_t nvc_intr_pri; /* Interrupt priority */ 89 int nvc_intr_cap; /* Interrupt capabilities */ 90 uint8_t *nvc_ck804_int_status; /* interrupt status ck804 */ 91 92 sata_hba_tran_t nvc_sata_hba_tran; /* sata_hba_tran for ctrl */ 93 94 /* 95 * enable/disable interrupts, controller specific 96 */ 97 void (*nvc_set_intr)(nv_port_t *nvp, int flag); 98 int nvc_state; /* state flags of ctrl see below */ 99 uint8_t nvc_revid; /* PCI revid of device */ 100 boolean_t dma_40bit; /* 40bit DMA support */ 101 102 #ifdef SGPIO_SUPPORT 103 int nvc_mcp5x_flag; /* is the controller MCP51/MCP55 */ 104 uint8_t nvc_ctlr_num; /* controller number within the part */ 105 uint32_t nvc_sgp_csr; /* SGPIO CSR i/o address */ 106 volatile nv_sgp_cb_t *nvc_sgp_cbp; /* SGPIO Control Block */ 107 nv_sgp_cmn_t *nvc_sgp_cmn; /* SGPIO shared data */ 108 #endif 109 } nv_ctl_t; 110 111 112 struct nv_port { 113 114 struct nv_ctl *nvp_ctlp; /* back pointer to controller */ 115 116 uint8_t nvp_port_num; /* port number, ie 1 or 2 */ 117 118 uint8_t nvp_type; /* SATA_DTYPE_{NONE,ATADISK,UNKNOWN} */ 119 uint32_t nvp_signature; /* sig acquired from task file regs */ 120 uchar_t *nvp_cmd_addr; /* base addr for cmd regs for port */ 121 uchar_t *nvp_bm_addr; /* base addr for bus master for port */ 122 uchar_t *nvp_ctl_addr; /* base addr for ctrl regs for port */ 123 124 ddi_acc_handle_t nvp_cmd_hdl; 125 uchar_t *nvp_data; /* data register */ 126 uchar_t *nvp_error; /* error register (read) */ 127 uchar_t *nvp_feature; /* features (write) */ 128 uchar_t *nvp_count; /* sector count */ 129 uchar_t *nvp_sect; /* sector number */ 130 uchar_t *nvp_lcyl; /* cylinder low byte */ 131 uchar_t *nvp_hcyl; /* cylinder high byte */ 132 uchar_t *nvp_drvhd; /* drive/head register */ 133 uchar_t *nvp_status; /* status/command register */ 134 uchar_t *nvp_cmd; /* status/command register */ 135 136 ddi_acc_handle_t nvp_ctl_hdl; 137 uchar_t *nvp_altstatus; /* alternate status (read) */ 138 uchar_t *nvp_devctl; /* device control (write) */ 139 140 ddi_acc_handle_t nvp_bm_hdl; 141 uchar_t *nvp_bmisx; 142 uint32_t *nvp_bmidtpx; 143 uchar_t *nvp_bmicx; 144 145 ddi_dma_handle_t *nvp_sg_dma_hdl; /* dma handle to prd table */ 146 caddr_t *nvp_sg_addr; /* virtual addr of prd table */ 147 uint32_t *nvp_sg_paddr; /* physical address of prd table */ 148 ddi_acc_handle_t *nvp_sg_acc_hdl; /* mem acc handle to the prd table */ 149 150 uint32_t *nvp_sstatus; 151 uint32_t *nvp_serror; 152 uint32_t *nvp_sctrl; 153 uint32_t *nvp_sactive; 154 155 kmutex_t nvp_mutex; /* main per port mutex */ 156 kcondvar_t nvp_poll_cv; /* handshake cv between poll & isr */ 157 158 /* 159 * nvp_slot is a pointer to an array of nv_slot 160 */ 161 struct nv_slot *nvp_slot; 162 uint32_t nvp_sactive_cache; /* cache of SACTIVE */ 163 uint8_t nvp_queue_depth; 164 165 /* 166 * NCQ flow control. During NCQ operation, no other commands 167 * allowed. The following are used to enforce this. 168 */ 169 int nvp_ncq_run; 170 int nvp_non_ncq_run; 171 172 timeout_id_t nvp_timeout_id; 173 174 clock_t nvp_reset_time; /* time of last reset */ 175 176 int nvp_state; /* state of port. flags defined below */ 177 178 uint16_t *nvp_mcp5x_int_status; 179 uint16_t *nvp_mcp5x_int_ctl; 180 181 #ifdef SGPIO_SUPPORT 182 uint8_t nvp_sgp_ioctl_mod; /* LEDs modified by ioctl */ 183 #endif 184 int nvp_timeout_duration; 185 186 uint8_t nvp_last_cmd; 187 uint8_t nvp_previous_cmd; 188 int nvp_reset_count; 189 clock_t intr_duration; /* max length of port intr (ticks) */ 190 clock_t intr_start_time; 191 int intr_loop_cnt; 192 }; 193 194 195 typedef struct nv_device_table { 196 ushort_t vendor_id; /* vendor id */ 197 ushort_t device_id; /* device id */ 198 ushort_t type; /* chipset type, ck804 or mcp51/mcp55 */ 199 } nv_device_table_t; 200 201 202 typedef struct nv_slot { 203 caddr_t nvslot_v_addr; /* I/O buffer address */ 204 size_t nvslot_byte_count; /* # bytes left to read/write */ 205 sata_pkt_t *nvslot_spkt; 206 uint8_t nvslot_rqsense_buff[SATA_ATAPI_RQSENSE_LEN]; 207 clock_t nvslot_stime; 208 int (*nvslot_start)(nv_port_t *nvp, int queue); 209 void (*nvslot_intr)(nv_port_t *nvp, 210 struct nv_slot *nv_slotp); 211 uint32_t nvslot_flags; 212 } nv_slot_t; 213 214 215 #ifdef SGPIO_SUPPORT 216 struct nv_sgp_cmn { 217 uint8_t nvs_in_use; /* bit-field of active ctlrs */ 218 uint8_t nvs_connected; /* port connected bit-field flag */ 219 uint8_t nvs_activity; /* port usage bit-field flag */ 220 int nvs_cbp; /* SGPIO Control Block Pointer */ 221 int nvs_taskq_delay; /* rest time for activity LED taskq */ 222 kmutex_t nvs_slock; /* lock for shared data */ 223 kmutex_t nvs_tlock; /* lock for taskq */ 224 kcondvar_t nvs_cv; /* condition variable for taskq wait */ 225 ddi_taskq_t *nvs_taskq; /* activity LED taskq */ 226 }; 227 228 struct nv_sgp_cbp2cmn { 229 uint32_t c2cm_cbp; /* ctlr block ptr from pci cfg space */ 230 nv_sgp_cmn_t *c2cm_cmn; /* point to common space */ 231 }; 232 #endif 233 234 235 /* 236 * nvslot_flags 237 */ 238 #define NVSLOT_COMPLETE 0x01 239 #define NVSLOT_NCQ 0x02 /* NCQ is active */ 240 #define NVSLOT_RQSENSE 0x04 /* processing request sense */ 241 242 /* 243 * state values for nv_attach 244 */ 245 #define ATTACH_PROGRESS_NONE (1 << 0) 246 #define ATTACH_PROGRESS_STATEP_ALLOC (1 << 1) 247 #define ATTACH_PROGRESS_PCI_HANDLE (1 << 2) 248 #define ATTACH_PROGRESS_BARS (1 << 3) 249 #define ATTACH_PROGRESS_INTR_ADDED (1 << 4) 250 #define ATTACH_PROGRESS_MUTEX_INIT (1 << 5) 251 #define ATTACH_PROGRESS_CTL_SETUP (1 << 6) 252 #define ATTACH_PROGRESS_TRAN_SETUP (1 << 7) 253 #define ATTACH_PROGRESS_COUNT (1 << 8) 254 #define ATTACH_PROGRESS_CONF_HANDLE (1 << 9) 255 #define ATTACH_PROGRESS_SATA_MODULE (1 << 10) 256 257 #ifdef DEBUG 258 259 #define NV_DEBUG 1 260 261 #endif /* DEBUG */ 262 263 264 /* 265 * nv_debug_flags 266 */ 267 #define NVDBG_ALWAYS 0x0001 268 #define NVDBG_INIT 0x0002 269 #define NVDBG_ENTRY 0x0004 270 #define NVDBG_DELIVER 0x0008 271 #define NVDBG_EVENT 0x0010 272 #define NVDBG_SYNC 0x0020 273 #define NVDBG_PKTCOMP 0x0040 274 #define NVDBG_TIMEOUT 0x0080 275 #define NVDBG_INFO 0x0100 276 #define NVDBG_VERBOSE 0x0200 277 #define NVDBG_INTR 0x0400 278 #define NVDBG_ERRS 0x0800 279 #define NVDBG_COOKIES 0x1000 280 #define NVDBG_HOT 0x2000 281 #define NVDBG_RESET 0x4000 282 #define NVDBG_ATAPI 0x8000 283 284 #ifdef DEBUG 285 #define NVLOG(a) nv_log a 286 #else 287 #define NVLOG(a) 288 #endif 289 290 #define NV_SUCCESS 0 291 #define NV_FAILURE -1 292 293 /* 294 * indicates whether nv_wait functions can sleep or not. 295 */ 296 #define NV_SLEEP 1 297 #define NV_NOSLEEP 2 298 299 /* 300 * port offsets from base address ioaddr1 301 */ 302 #define NV_DATA 0x00 /* data register */ 303 #define NV_ERROR 0x01 /* error register (read) */ 304 #define NV_FEATURE 0x01 /* features (write) */ 305 #define NV_COUNT 0x02 /* sector count */ 306 #define NV_SECT 0x03 /* sector number */ 307 #define NV_LCYL 0x04 /* cylinder low byte */ 308 #define NV_HCYL 0x05 /* cylinder high byte */ 309 #define NV_DRVHD 0x06 /* drive/head register */ 310 #define NV_STATUS 0x07 /* status/command register */ 311 #define NV_CMD 0x07 /* status/command register */ 312 313 /* 314 * port offsets from base address ioaddr2 315 */ 316 #define NV_ALTSTATUS 0x02 /* alternate status (read) */ 317 #define NV_DEVCTL 0x02 /* device control (write) */ 318 319 /* 320 * device control register 321 */ 322 #define ATDC_NIEN 0x02 /* disable interrupts */ 323 #define ATDC_SRST 0x04 /* controller reset */ 324 #define ATDC_D3 0x08 /* mysterious bit */ 325 #define ATDC_HOB 0x80 /* high order byte to read 48-bit values */ 326 327 /* 328 * MCP5x NCQ and INTR control registers 329 */ 330 #define MCP5X_CTL 0x400 /* queuing control */ 331 #define MCP5X_INT_STATUS 0x440 /* status bits for interrupt */ 332 #define MCP5X_INT_CTL 0x444 /* enable bits for interrupt */ 333 #define MCP5X_NCQ 0x448 /* NCQ status and ctrl bits */ 334 335 /* 336 * if either of these bits are set, when using NCQ, if no other commands are 337 * active while a new command is started, DMA engine can be programmed ahead 338 * of time to save extra interrupt. Presumably pre-programming is discarded 339 * if a subsequent command ends up finishing first. 340 */ 341 #define MCP_SATA_AE_NCQ_PDEV_FIRST_CMD (1 << 7) 342 #define MCP_SATA_AE_NCQ_SDEV_FIRST_CMD (1 << 23) 343 344 /* 345 * bit definitions to indicate which NCQ command requires 346 * DMA setup. 347 */ 348 #define MCP_SATA_AE_NCQ_PDEV_DMA_SETUP_TAG_SHIFT 2 349 #define MCP_SATA_AE_NCQ_SDEV_DMA_SETUP_TAG_SHIFT 18 350 #define MCP_SATA_AE_NCQ_DMA_SETUP_TAG_MASK 0x1f 351 352 353 /* 354 * Bits for NV_MCP5X_INT_CTL and NV_MCP5X_INT_STATUS 355 */ 356 #define MCP5X_INT_SNOTIFY 0x200 /* snotification set */ 357 #define MCP5X_INT_SERROR 0x100 /* serror set */ 358 #define MCP5X_INT_DMA_SETUP 0x80 /* DMA to be programmed */ 359 #define MCP5X_INT_DH_REGFIS 0x40 /* REGFIS received */ 360 #define MCP5X_INT_SDB_FIS 0x20 /* SDB FIS */ 361 #define MCP5X_INT_TX_BACKOUT 0x10 /* TX backout */ 362 #define MCP5X_INT_REM 0x08 /* device removed */ 363 #define MCP5X_INT_ADD 0x04 /* device added */ 364 #define MCP5X_INT_PM 0x02 /* power changed */ 365 #define MCP5X_INT_COMPLETE 0x01 /* device interrupt */ 366 367 /* 368 * Bits above that are not used for now. 369 */ 370 #define MCP5X_INT_IGNORE (MCP5X_INT_DMA_SETUP|MCP5X_INT_DH_REGFIS|\ 371 MCP5X_INT_SDB_FIS|MCP5X_INT_TX_BACKOUT|MCP5X_INT_PM|\ 372 MCP5X_INT_SNOTIFY|MCP5X_INT_SERROR) 373 374 /* 375 * Bits for MCP_SATA_AE_CTL 376 */ 377 #define MCP_SATA_AE_CTL_PRI_SWNCQ (1 << 1) /* software NCQ chan 0 */ 378 #define MCP_SATA_AE_CTL_SEC_SWNCQ (1 << 2) /* software NCQ chan 1 */ 379 380 #define NV_DELAY_NSEC(wait_ns) \ 381 { \ 382 hrtime_t start, end; \ 383 start = end = gethrtime(); \ 384 while ((end - start) < wait_ns) \ 385 end = gethrtime(); \ 386 } 387 388 /* 389 * signatures in task file registers after device reset 390 */ 391 #define NV_SIG_DISK 0x00000101 392 #define NV_SIG_ATAPI 0xeb140101 393 #define NV_SIG_PM 0x96690101 394 #define NV_SIG_NOTREADY 0x00000000 395 396 /* 397 * These bar5 offsets are common to mcp51/mcp55/ck804 and thus 398 * prefixed with NV. 399 */ 400 #define NV_SSTATUS 0x00 401 #define NV_SERROR 0x04 402 #define NV_SCTRL 0x08 403 #define NV_SACTIVE 0x0c 404 #define NV_SNOTIFICATION 0x10 405 406 #define CH0_SREG_OFFSET 0x0 407 #define CH1_SREG_OFFSET 0x40 408 409 410 /* 411 * The following config space offsets are needed to enable 412 * bar 5 register access in ck804/mcp51/mcp55 413 */ 414 #define NV_SATA_CFG_20 0x50 415 #define NV_BAR5_SPACE_EN 0x04 416 #define NV_40BIT_PRD 0x20 417 418 #define NV_SATA_CFG_23 0x60 419 420 /* 421 * ck804 interrupt status register 422 */ 423 424 /* 425 * offsets to bar 5 registers 426 */ 427 #define CK804_SATA_INT_STATUS 0x440 428 #define CK804_SATA_INT_EN 0x441 429 430 431 /* 432 * bit fields for int status and int enable 433 * registers 434 */ 435 #define CK804_INT_PDEV_INT 0x01 /* completion interrupt */ 436 #define CK804_INT_PDEV_PM 0x02 /* power change */ 437 #define CK804_INT_PDEV_ADD 0x04 /* hot plug */ 438 #define CK804_INT_PDEV_REM 0x08 /* hot remove */ 439 #define CK804_INT_PDEV_HOT CK804_INT_PDEV_ADD|CK804_INT_PDEV_REM 440 441 #define CK804_INT_SDEV_INT 0x10 /* completion interrupt */ 442 #define CK804_INT_SDEV_PM 0x20 /* power change */ 443 #define CK804_INT_SDEV_ADD 0x40 /* hot plug */ 444 #define CK804_INT_SDEV_REM 0x80 /* hot remove */ 445 #define CK804_INT_SDEV_HOT CK804_INT_SDEV_ADD|CK804_INT_SDEV_REM 446 447 #define CK804_INT_PDEV_ALL CK804_INT_PDEV_INT|CK804_INT_PDEV_HOT|\ 448 CK804_INT_PDEV_PM 449 #define CK804_INT_SDEV_ALL CK804_INT_SDEV_INT|CK804_INT_SDEV_HOT|\ 450 CK804_INT_SDEV_PM 451 452 /* 453 * config space offset 42 454 */ 455 #define NV_SATA_CFG_42 0xac 456 457 /* 458 * bit in CFG_42 which delays hotplug interrupt until 459 * PHY ready 460 */ 461 #define CK804_CFG_DELAY_HOTPLUG_INTR (0x1 << 12) 462 463 464 /* 465 * bar 5 offsets for SATA registers in ck804 466 */ 467 #define CK804_CH1_SSTATUS 0x00 468 #define CK804_CH1_SERROR 0x04 469 #define CK804_CH1_SCTRL 0x08 470 #define CK804_CH1_SACTIVE 0x0c 471 #define CK804_CH1_SNOTIFICATION 0x10 472 473 #define CK804_CH2_SSTATUS 0x40 474 #define CK804_CH2_SERROR 0x44 475 #define CK804_CH2_SCTRL 0x48 476 #define CK804_CH2_SACTIVE 0x4c 477 #define CK804_CH2_SNOTIFICATION 0x50 478 479 480 /* 481 * bar 5 offsets for ADMACTL settings for both ck804/mcp51/mcp/55 482 */ 483 #define NV_ADMACTL_X 0x4C0 484 #define NV_ADMACTL_Y 0x5C0 485 486 /* 487 * Bits for NV_ADMACTL_X and NV_ADMACTL_Y 488 */ 489 #define NV_HIRQ_EN 0x01 /* hot plug/unplug interrupt enable */ 490 #define NV_CH_RST 0x04 /* reset channel */ 491 492 493 /* 494 * bar 5 offset for ADMASTAT regs for ck804 495 */ 496 #define CK804_ADMASTAT_X 0x4C4 497 #define CK804_ADMASTAT_Y 0x5C4 498 499 /* 500 * Bits for CK804_ADMASTAT_X and CK804_ADMASTAT_Y 501 */ 502 #define CK804_HPIRQ 0x4 503 #define MCP05_HUIRQ 0x2 504 505 506 /* 507 * bar 4 offset to bus master command registers 508 */ 509 #define BMICX_REG 0 510 511 /* 512 * bit definitions for BMICX_REG 513 */ 514 #define BMICX_SSBM 0x01 /* Start/Stop Bus Master */ 515 /* 1=Start (Enable) */ 516 /* 0=Start (Disable) */ 517 518 /* 519 * NOTE: "read" and "write" are the actions of the DMA engine 520 * on the PCI bus, not the SATA bus. Therefore for a ATA READ 521 * command, program the DMA engine to "write to memory" mode 522 * (and vice versa). 523 */ 524 #define BMICX_RWCON 0x08 /* Read/Write Control */ 525 #define BMICX_RWCON_WRITE_TO_MEMORY 0x08 /* 1=Write (dev to host) */ 526 #define BMICX_RWCON_READ_FROM_MEMORY 0x00 /* 0=Read (host to dev) */ 527 528 /* 529 * BMICX bits to preserve during updates 530 */ 531 #define BMICX_MASK (~(BMICX_SSBM | BMICX_RWCON)) 532 533 /* 534 * bar 4 offset to bus master status register 535 */ 536 #define BMISX_REG 2 537 538 /* 539 * bit fields for bus master status register 540 */ 541 #define BMISX_BMIDEA 0x01 /* Bus Master IDE Active */ 542 #define BMISX_IDERR 0x02 /* IDE DMA Error */ 543 #define BMISX_IDEINTS 0x04 /* IDE Interrupt Status */ 544 545 /* 546 * bus master status register bits to preserve 547 */ 548 #define BMISX_MASK 0xf8 549 550 /* 551 * bar4 offset to bus master PRD descriptor table 552 */ 553 #define BMIDTPX_REG 4 554 555 556 /* 557 * structure for a single entry in the PRD table 558 * (physical region descriptor table) 559 */ 560 typedef struct prde { 561 uint32_t p_address; /* physical address */ 562 uint32_t p_count; /* byte count, EOT in high order bit */ 563 } prde_t; 564 565 566 #define PRDE_EOT ((uint_t)0x80000000) 567 568 #define NV_DMA_NSEGS 256 /* XXX DEBUG TEST change back to 257 */ 569 570 /* 571 * ck804 and mcp55 both have 2 ports per controller 572 */ 573 #define NV_NUM_CPORTS 2 574 575 /* 576 * Number of slots to allocate in data nv_sata structures to handle 577 * multiple commands at once. This does not reflect the capability of 578 * the drive or the hardware, and in many cases will not match. 579 * 1 or 32 slots are allocated, so in cases where the driver has NCQ 580 * enabled but the drive doesn't support it, or supports fewer than 581 * 32 slots, here may be an over allocation of memory. 582 */ 583 #ifdef NCQ 584 #define NV_QUEUE_SLOTS 32 585 #else 586 #define NV_QUEUE_SLOTS 1 587 #endif 588 589 #define NV_BM_64K_BOUNDARY 0x10000ull 590 591 #define NV_MAX_INTR_PER_DEV 20 /* Empirical value */ 592 593 /* 594 * 1 second (in microseconds) 595 */ 596 #define NV_ONE_SEC 1000000 597 598 /* 599 * 1 millisecond (in microseconds) 600 */ 601 #define NV_ONE_MSEC 1000 602 603 /* 604 * Length of port reset (microseconds) - SControl bit 0 set to 1 605 */ 606 #define NV_RESET_LENGTH 1000 607 608 #define NV_RESET_ATTEMPTS 3 609 610 /* 611 * The maximum amount of time (milliseconds) a link can be down during 612 * reset without assuming that there is no device attached. 613 */ 614 #define NV_LINK_DOWN_TIMEOUT 10 615 616 /* 617 * The maximum amount of time (milliseconds) the signature acquisition can 618 * drag on before it is terminated. 619 * Some disks have very long acquisition times after hotplug, related to 620 * to spinning-up and reading some data from a media. 621 * The value below is empirical (20s) 622 * 623 */ 624 #define NV_SIG_ACQUISITION_TIME 20000 625 626 /* 627 * Minimum amount of time (milliseconds) to delay reporting hotplug 628 * (device added) event. 629 * It is the time allowed for a drive to initialize and to send a D2H FIS with 630 * a device signature. 631 * It varies between drives from a few milliseconds up to 20s. 632 */ 633 #define NV_HOTPLUG_DELAY 20000 634 635 /* 636 * nvp_state flags 637 */ 638 #define NV_PORT_INACTIVE 0x001 639 #define NV_PORT_ABORTING 0x002 640 #define NV_PORT_HOTREMOVED 0x004 641 #define NV_PORT_INIT 0x008 642 #define NV_PORT_FAILED 0x010 643 #define NV_PORT_RESET 0x020 644 #define NV_PORT_RESET_RETRY 0x040 645 #define NV_PORT_RESTORE 0x080 646 #define NV_PORT_PROBE 0x100 647 #define NV_PORT_HOTPLUG_DELAY 0x200 648 649 /* 650 * nvc_state flags 651 */ 652 #define NV_CTRL_SUSPEND 0x1 653 654 655 /* 656 * flags for ck804_set_intr/mcp5x_set_intr 657 */ 658 #define NV_INTR_DISABLE 0x1 659 #define NV_INTR_ENABLE 0x2 660 #define NV_INTR_CLEAR_ALL 0x4 661 #define NV_INTR_DISABLE_NON_BLOCKING 0x8 662 663 /* 664 * sizes of strings to allocate 665 */ 666 #define NV_STRING_10 10 667 #define NV_STRING_512 512 668 669 #define NV_BYTES_PER_SEC 512 670 671 #define NV_WAIT_REG_CHECK 10 /* 10 microseconds */ 672 #define NV_ATA_NUM_CMDS 256 /* max num ATA cmds possible, 8 bits */ 673 #define NV_PRINT_INTERVAL 40 /* throttle debug msg from flooding */ 674 #define MCP5X_INT_CLEAR 0xffff /* clear all interrupts */ 675 676 /* 677 * definition labels for the BAR registers 678 */ 679 #define NV_BAR_0 0 /* chan 0 task file regs */ 680 #define NV_BAR_1 1 /* chan 0 status reg */ 681 #define NV_BAR_2 2 /* chan 1 task file regs */ 682 #define NV_BAR_3 3 /* chan 1 status reg */ 683 #define NV_BAR_4 4 /* bus master regs */ 684 #define NV_BAR_5 5 /* extra regs mostly SATA related */ 685 686 /* 687 * transform seconds to microseconds 688 */ 689 #define NV_SEC2USEC(x) x * MICROSEC 690 691 692 /* 693 * ck804 maps in task file regs into bar 5. These are 694 * only used to identify ck804, therefore only this reg is 695 * listed here. 696 */ 697 #define NV_BAR5_TRAN_LEN_CH_X 0x518 698 699 /* 700 * if after this many iterations through the interrupt 701 * processing loop, declare the interrupt wedged and 702 * disable. 703 */ 704 #define NV_MAX_INTR_LOOP 10 705 706 /* 707 * flag values for nv_copy_regs_out 708 */ 709 #define NV_COPY_COMPLETE 0x01 /* normal command completion */ 710 #define NV_COPY_ERROR 0x02 /* error, did not complete ok */ 711 #define NV_COPY_SSREGS 0x04 /* SS port registers */ 712 713 #ifdef SGPIO_SUPPORT 714 #define NV_MAX_CBPS 16 /* Maximum # of Control Block */ 715 /* Pointers. Corresponds to */ 716 /* each MCP55 and IO55 */ 717 #define SGPIO_LOOP_WAIT_USECS 62500 /* 1/16 second (in usecs) */ 718 #define SGPIO_TQ_NAME_LEN 32 719 720 /* 721 * The drive number format is ccp (binary). 722 * cc is the controller number (0-based number) 723 * p is the port number (0 or 1) 724 */ 725 #define SGP_DRV_TO_PORT(d) ((d) & 1) 726 #define SGP_DRV_TO_CTLR(d) ((d) >> 1) 727 #define SGP_CTLR_PORT_TO_DRV(c, p) (((c) << 1) | ((p) & 1)) 728 #endif 729 730 #ifdef __cplusplus 731 } 732 #endif 733 734 #endif /* _NV_SATA_H */ 735