1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2007, 2010, Oracle and/or its affiliates. All rights reserved. 24 */ 25 26 #ifndef _NV_SATA_H 27 #define _NV_SATA_H 28 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 35 /* 36 * SGPIO Support 37 * Enable SGPIO support only on x86/x64, because it is implemented using 38 * functions that are only available on x86/x64. 39 */ 40 41 #define NV_MAX_PORTS(nvc) nvc->nvc_sata_hba_tran.sata_tran_hba_num_cports 42 43 typedef struct nv_port nv_port_t; 44 45 #ifdef SGPIO_SUPPORT 46 typedef struct nv_sgp_cmn nv_sgp_cmn_t; 47 #endif 48 49 /* 50 * sizes of strings to allocate 51 */ 52 #define NV_STR_LEN 10 53 #define NV_LOGBUF_LEN 512 54 #define NV_REASON_LEN 30 55 56 typedef struct nv_ctl { 57 /* 58 * Each of these are specific to the chipset in use. 59 */ 60 uint_t (*nvc_interrupt)(caddr_t arg1, caddr_t arg2); 61 void (*nvc_reg_init)(struct nv_ctl *nvc, 62 ddi_acc_handle_t pci_conf_handle); 63 64 dev_info_t *nvc_dip; /* devinfo pointer of controller */ 65 66 struct nv_port *nvc_port; /* array of pointers to port struct */ 67 68 /* 69 * handle and base address to register space. 70 * 71 * 0: port 0 task file 72 * 1: port 0 status 73 * 2: port 1 task file 74 * 3: port 1 status 75 * 4: bus master for both ports 76 * 5: extended registers for SATA features 77 */ 78 ddi_acc_handle_t nvc_bar_hdl[6]; 79 uchar_t *nvc_bar_addr[6]; 80 81 /* 82 * sata registers in bar 5 which are shared on all devices 83 * on the channel. 84 */ 85 uint32_t *nvc_mcp5x_ctl; 86 uint32_t *nvc_mcp5x_ncq; /* NCQ status control bits */ 87 88 kmutex_t nvc_mutex; /* ctrl level lock */ 89 90 ddi_intr_handle_t *nvc_htable; /* For array of interrupts */ 91 int nvc_intr_type; /* What type of interrupt */ 92 int nvc_intr_cnt; /* # of intrs count returned */ 93 size_t nvc_intr_size; /* Size of intr array to */ 94 uint_t nvc_intr_pri; /* Interrupt priority */ 95 int nvc_intr_cap; /* Interrupt capabilities */ 96 uint8_t *nvc_ck804_int_status; /* interrupt status ck804 */ 97 98 sata_hba_tran_t nvc_sata_hba_tran; /* sata_hba_tran for ctrl */ 99 100 /* 101 * enable/disable interrupts, controller specific 102 */ 103 void (*nvc_set_intr)(nv_port_t *nvp, int flag); 104 int nvc_state; /* state flags of ctrl see below */ 105 uint8_t nvc_revid; /* PCI revid of device */ 106 boolean_t dma_40bit; /* 40bit DMA support */ 107 108 #ifdef SGPIO_SUPPORT 109 int nvc_mcp5x_flag; /* is the controller MCP51/MCP55 */ 110 uint8_t nvc_ctlr_num; /* controller number within the part */ 111 uint32_t nvc_sgp_csr; /* SGPIO CSR i/o address */ 112 volatile nv_sgp_cb_t *nvc_sgp_cbp; /* SGPIO Control Block */ 113 nv_sgp_cmn_t *nvc_sgp_cmn; /* SGPIO shared data */ 114 #endif 115 } nv_ctl_t; 116 117 118 struct nv_port { 119 120 struct nv_ctl *nvp_ctlp; /* back pointer to controller */ 121 122 uint8_t nvp_port_num; /* port number, ie 0 or 1 */ 123 124 uint8_t nvp_type; /* SATA_DTYPE_{NONE,ATADISK,UNKNOWN} */ 125 uint32_t nvp_signature; /* sig acquired from task file regs */ 126 uchar_t *nvp_cmd_addr; /* base addr for cmd regs for port */ 127 uchar_t *nvp_bm_addr; /* base addr for bus master for port */ 128 uchar_t *nvp_ctl_addr; /* base addr for ctrl regs for port */ 129 130 ddi_acc_handle_t nvp_cmd_hdl; 131 uchar_t *nvp_data; /* data register */ 132 uchar_t *nvp_error; /* error register (read) */ 133 uchar_t *nvp_feature; /* features (write) */ 134 uchar_t *nvp_count; /* sector count */ 135 uchar_t *nvp_sect; /* sector number */ 136 uchar_t *nvp_lcyl; /* cylinder low byte */ 137 uchar_t *nvp_hcyl; /* cylinder high byte */ 138 uchar_t *nvp_drvhd; /* drive/head register */ 139 uchar_t *nvp_status; /* status/command register */ 140 uchar_t *nvp_cmd; /* status/command register */ 141 142 ddi_acc_handle_t nvp_ctl_hdl; 143 uchar_t *nvp_altstatus; /* alternate status (read) */ 144 uchar_t *nvp_devctl; /* device control (write) */ 145 146 ddi_acc_handle_t nvp_bm_hdl; 147 uchar_t *nvp_bmisx; 148 uint32_t *nvp_bmidtpx; 149 uchar_t *nvp_bmicx; 150 151 ddi_dma_handle_t *nvp_sg_dma_hdl; /* dma handle to prd table */ 152 caddr_t *nvp_sg_addr; /* virtual addr of prd table */ 153 uint32_t *nvp_sg_paddr; /* physical address of prd table */ 154 ddi_acc_handle_t *nvp_sg_acc_hdl; /* mem acc handle to the prd table */ 155 156 uint32_t *nvp_sstatus; 157 uint32_t *nvp_serror; 158 uint32_t *nvp_sctrl; 159 uint32_t *nvp_sactive; 160 161 kmutex_t nvp_mutex; /* main per port mutex */ 162 kcondvar_t nvp_poll_cv; /* handshake cv between poll & isr */ 163 164 /* 165 * nvp_slot is a pointer to an array of nv_slot 166 */ 167 struct nv_slot *nvp_slot; 168 uint32_t nvp_sactive_cache; /* cache of SACTIVE */ 169 uint8_t nvp_queue_depth; 170 171 /* 172 * NCQ flow control. During NCQ operation, no other commands 173 * allowed. The following are used to enforce this. 174 */ 175 int nvp_ncq_run; 176 int nvp_non_ncq_run; 177 int nvp_seq; 178 179 timeout_id_t nvp_timeout_id; 180 181 clock_t nvp_reset_time; /* time of last reset */ 182 183 int nvp_state; /* state of port. flags defined below */ 184 185 uint16_t *nvp_mcp5x_int_status; 186 uint16_t *nvp_mcp5x_int_ctl; 187 188 #ifdef SGPIO_SUPPORT 189 uint8_t nvp_sgp_ioctl_mod; /* LEDs modified by ioctl */ 190 #endif 191 int nvp_timeout_duration; 192 193 uint8_t nvp_last_cmd; 194 uint8_t nvp_previous_cmd; 195 int nvp_reset_count; 196 char nvp_first_reset_reason[NV_REASON_LEN]; 197 char nvp_reset_reason[NV_REASON_LEN]; 198 clock_t intr_duration; /* max length of port intr (ticks) */ 199 clock_t intr_start_time; 200 int intr_loop_cnt; 201 }; 202 203 204 typedef struct nv_device_table { 205 ushort_t vendor_id; /* vendor id */ 206 ushort_t device_id; /* device id */ 207 ushort_t type; /* chipset type, ck804 or mcp51/mcp55 */ 208 } nv_device_table_t; 209 210 211 typedef struct nv_slot { 212 caddr_t nvslot_v_addr; /* I/O buffer address */ 213 size_t nvslot_byte_count; /* # bytes left to read/write */ 214 sata_pkt_t *nvslot_spkt; 215 uint8_t nvslot_rqsense_buff[SATA_ATAPI_RQSENSE_LEN]; 216 clock_t nvslot_stime; 217 int (*nvslot_start)(nv_port_t *nvp, int queue); 218 void (*nvslot_intr)(nv_port_t *nvp, 219 struct nv_slot *nv_slotp); 220 uint32_t nvslot_flags; 221 } nv_slot_t; 222 223 224 #ifdef SGPIO_SUPPORT 225 struct nv_sgp_cmn { 226 uint8_t nvs_in_use; /* bit-field of active ctlrs */ 227 uint8_t nvs_connected; /* port connected bit-field flag */ 228 uint8_t nvs_activity; /* port usage bit-field flag */ 229 int nvs_cbp; /* SGPIO Control Block Pointer */ 230 int nvs_taskq_delay; /* rest time for activity LED taskq */ 231 kmutex_t nvs_slock; /* lock for shared data */ 232 kmutex_t nvs_tlock; /* lock for taskq */ 233 kcondvar_t nvs_cv; /* condition variable for taskq wait */ 234 ddi_taskq_t *nvs_taskq; /* activity LED taskq */ 235 }; 236 237 struct nv_sgp_cbp2cmn { 238 uint32_t c2cm_cbp; /* ctlr block ptr from pci cfg space */ 239 nv_sgp_cmn_t *c2cm_cmn; /* point to common space */ 240 }; 241 #endif 242 243 244 /* 245 * nvslot_flags 246 */ 247 #define NVSLOT_COMPLETE 0x01 248 #define NVSLOT_NCQ 0x02 /* NCQ is active */ 249 #define NVSLOT_RQSENSE 0x04 /* processing request sense */ 250 251 /* 252 * state values for nv_attach 253 */ 254 #define ATTACH_PROGRESS_NONE (1 << 0) 255 #define ATTACH_PROGRESS_STATEP_ALLOC (1 << 1) 256 #define ATTACH_PROGRESS_PCI_HANDLE (1 << 2) 257 #define ATTACH_PROGRESS_BARS (1 << 3) 258 #define ATTACH_PROGRESS_INTR_ADDED (1 << 4) 259 #define ATTACH_PROGRESS_MUTEX_INIT (1 << 5) 260 #define ATTACH_PROGRESS_CTL_SETUP (1 << 6) 261 #define ATTACH_PROGRESS_TRAN_SETUP (1 << 7) 262 #define ATTACH_PROGRESS_COUNT (1 << 8) 263 #define ATTACH_PROGRESS_CONF_HANDLE (1 << 9) 264 #define ATTACH_PROGRESS_SATA_MODULE (1 << 10) 265 266 #ifdef DEBUG 267 268 #define NV_DEBUG 1 269 270 #endif /* DEBUG */ 271 272 273 /* 274 * nv_debug_flags 275 */ 276 #define NVDBG_ALWAYS 0x00001 277 #define NVDBG_INIT 0x00002 278 #define NVDBG_ENTRY 0x00004 279 #define NVDBG_DELIVER 0x00008 280 #define NVDBG_EVENT 0x00010 281 #define NVDBG_SYNC 0x00020 282 #define NVDBG_PKTCOMP 0x00040 283 #define NVDBG_TIMEOUT 0x00080 284 #define NVDBG_INFO 0x00100 285 #define NVDBG_VERBOSE 0x00200 286 #define NVDBG_INTR 0x00400 287 #define NVDBG_ERRS 0x00800 288 #define NVDBG_COOKIES 0x01000 289 #define NVDBG_HOT 0x02000 290 #define NVDBG_RESET 0x04000 291 #define NVDBG_ATAPI 0x08000 292 293 #define NVLOG(flag, nvc, nvp, fmt, args ...) \ 294 if (nv_debug_flags & (flag)) { \ 295 nv_log(nvc, nvp, fmt, ## args); \ 296 } 297 298 299 #define NV_SUCCESS 0 300 #define NV_FAILURE -1 301 302 /* 303 * indicates whether nv_wait functions can sleep or not. 304 */ 305 #define NV_SLEEP 1 306 #define NV_NOSLEEP 2 307 308 /* 309 * port offsets from base address ioaddr1 310 */ 311 #define NV_DATA 0x00 /* data register */ 312 #define NV_ERROR 0x01 /* error register (read) */ 313 #define NV_FEATURE 0x01 /* features (write) */ 314 #define NV_COUNT 0x02 /* sector count */ 315 #define NV_SECT 0x03 /* sector number */ 316 #define NV_LCYL 0x04 /* cylinder low byte */ 317 #define NV_HCYL 0x05 /* cylinder high byte */ 318 #define NV_DRVHD 0x06 /* drive/head register */ 319 #define NV_STATUS 0x07 /* status/command register */ 320 #define NV_CMD 0x07 /* status/command register */ 321 322 /* 323 * port offsets from base address ioaddr2 324 */ 325 #define NV_ALTSTATUS 0x02 /* alternate status (read) */ 326 #define NV_DEVCTL 0x02 /* device control (write) */ 327 328 /* 329 * device control register 330 */ 331 #define ATDC_NIEN 0x02 /* disable interrupts */ 332 #define ATDC_SRST 0x04 /* controller reset */ 333 #define ATDC_D3 0x08 /* mysterious bit */ 334 #define ATDC_HOB 0x80 /* high order byte to read 48-bit values */ 335 336 /* 337 * MCP5x NCQ and INTR control registers 338 */ 339 #define MCP5X_CTL 0x400 /* queuing control */ 340 #define MCP5X_INT_STATUS 0x440 /* status bits for interrupt */ 341 #define MCP5X_INT_CTL 0x444 /* enable bits for interrupt */ 342 #define MCP5X_NCQ 0x448 /* NCQ status and ctrl bits */ 343 344 /* 345 * if either of these bits are set, when using NCQ, if no other commands are 346 * active while a new command is started, DMA engine can be programmed ahead 347 * of time to save extra interrupt. Presumably pre-programming is discarded 348 * if a subsequent command ends up finishing first. 349 */ 350 #define MCP_SATA_AE_NCQ_PDEV_FIRST_CMD (1 << 7) 351 #define MCP_SATA_AE_NCQ_SDEV_FIRST_CMD (1 << 23) 352 353 /* 354 * bit definitions to indicate which NCQ command requires 355 * DMA setup. 356 */ 357 #define MCP_SATA_AE_NCQ_PDEV_DMA_SETUP_TAG_SHIFT 2 358 #define MCP_SATA_AE_NCQ_SDEV_DMA_SETUP_TAG_SHIFT 18 359 #define MCP_SATA_AE_NCQ_DMA_SETUP_TAG_MASK 0x1f 360 361 362 /* 363 * Bits for NV_MCP5X_INT_CTL and NV_MCP5X_INT_STATUS 364 */ 365 #define MCP5X_INT_SNOTIFY 0x200 /* snotification set */ 366 #define MCP5X_INT_SERROR 0x100 /* serror set */ 367 #define MCP5X_INT_DMA_SETUP 0x80 /* DMA to be programmed */ 368 #define MCP5X_INT_DH_REGFIS 0x40 /* REGFIS received */ 369 #define MCP5X_INT_SDB_FIS 0x20 /* SDB FIS */ 370 #define MCP5X_INT_TX_BACKOUT 0x10 /* TX backout */ 371 #define MCP5X_INT_REM 0x08 /* device removed */ 372 #define MCP5X_INT_ADD 0x04 /* device added */ 373 #define MCP5X_INT_PM 0x02 /* power changed */ 374 #define MCP5X_INT_COMPLETE 0x01 /* device interrupt */ 375 376 /* 377 * Bits above that are not used for now. 378 */ 379 #define MCP5X_INT_IGNORE (MCP5X_INT_DMA_SETUP|MCP5X_INT_DH_REGFIS|\ 380 MCP5X_INT_SDB_FIS|MCP5X_INT_TX_BACKOUT|MCP5X_INT_PM|\ 381 MCP5X_INT_SNOTIFY|MCP5X_INT_SERROR) 382 383 /* 384 * Bits for MCP_SATA_AE_CTL 385 */ 386 #define MCP_SATA_AE_CTL_PRI_SWNCQ (1 << 1) /* software NCQ chan 0 */ 387 #define MCP_SATA_AE_CTL_SEC_SWNCQ (1 << 2) /* software NCQ chan 1 */ 388 389 #define NV_DELAY_NSEC(wait_ns) \ 390 { \ 391 hrtime_t start, end; \ 392 start = end = gethrtime(); \ 393 while ((end - start) < wait_ns) \ 394 end = gethrtime(); \ 395 } 396 397 /* 398 * signatures in task file registers after device reset 399 */ 400 #define NV_SIG_DISK 0x00000101 401 #define NV_SIG_ATAPI 0xeb140101 402 #define NV_SIG_PM 0x96690101 403 #define NV_SIG_NOTREADY 0x00000000 404 405 /* 406 * These bar5 offsets are common to mcp51/mcp55/ck804 and thus 407 * prefixed with NV. 408 */ 409 #define NV_SSTATUS 0x00 410 #define NV_SERROR 0x04 411 #define NV_SCTRL 0x08 412 #define NV_SACTIVE 0x0c 413 #define NV_SNOTIFICATION 0x10 414 415 #define CH0_SREG_OFFSET 0x0 416 #define CH1_SREG_OFFSET 0x40 417 418 419 /* 420 * The following config space offsets are needed to enable 421 * bar 5 register access in ck804/mcp51/mcp55 422 */ 423 #define NV_SATA_CFG_20 0x50 424 #define NV_BAR5_SPACE_EN 0x04 425 #define NV_40BIT_PRD 0x20 426 427 #define NV_SATA_CFG_23 0x60 428 429 /* 430 * ck804 interrupt status register 431 */ 432 433 /* 434 * offsets to bar 5 registers 435 */ 436 #define CK804_SATA_INT_STATUS 0x440 437 #define CK804_SATA_INT_EN 0x441 438 439 440 /* 441 * bit fields for int status and int enable 442 * registers 443 */ 444 #define CK804_INT_PDEV_INT 0x01 /* completion interrupt */ 445 #define CK804_INT_PDEV_PM 0x02 /* power change */ 446 #define CK804_INT_PDEV_ADD 0x04 /* hot plug */ 447 #define CK804_INT_PDEV_REM 0x08 /* hot remove */ 448 #define CK804_INT_PDEV_HOT CK804_INT_PDEV_ADD|CK804_INT_PDEV_REM 449 450 #define CK804_INT_SDEV_INT 0x10 /* completion interrupt */ 451 #define CK804_INT_SDEV_PM 0x20 /* power change */ 452 #define CK804_INT_SDEV_ADD 0x40 /* hot plug */ 453 #define CK804_INT_SDEV_REM 0x80 /* hot remove */ 454 #define CK804_INT_SDEV_HOT CK804_INT_SDEV_ADD|CK804_INT_SDEV_REM 455 456 #define CK804_INT_PDEV_ALL CK804_INT_PDEV_INT|CK804_INT_PDEV_HOT|\ 457 CK804_INT_PDEV_PM 458 #define CK804_INT_SDEV_ALL CK804_INT_SDEV_INT|CK804_INT_SDEV_HOT|\ 459 CK804_INT_SDEV_PM 460 461 /* 462 * config space offset 42 463 */ 464 #define NV_SATA_CFG_42 0xac 465 466 /* 467 * bit in CFG_42 which delays hotplug interrupt until 468 * PHY ready 469 */ 470 #define CK804_CFG_DELAY_HOTPLUG_INTR (0x1 << 12) 471 472 473 /* 474 * bar 5 offsets for SATA registers in ck804 475 */ 476 #define CK804_CH1_SSTATUS 0x00 477 #define CK804_CH1_SERROR 0x04 478 #define CK804_CH1_SCTRL 0x08 479 #define CK804_CH1_SACTIVE 0x0c 480 #define CK804_CH1_SNOTIFICATION 0x10 481 482 #define CK804_CH2_SSTATUS 0x40 483 #define CK804_CH2_SERROR 0x44 484 #define CK804_CH2_SCTRL 0x48 485 #define CK804_CH2_SACTIVE 0x4c 486 #define CK804_CH2_SNOTIFICATION 0x50 487 488 489 /* 490 * bar 5 offsets for ADMACTL settings for both ck804/mcp51/mcp/55 491 */ 492 #define NV_ADMACTL_X 0x4C0 493 #define NV_ADMACTL_Y 0x5C0 494 495 /* 496 * Bits for NV_ADMACTL_X and NV_ADMACTL_Y 497 */ 498 #define NV_HIRQ_EN 0x01 /* hot plug/unplug interrupt enable */ 499 #define NV_CH_RST 0x04 /* reset channel */ 500 501 502 /* 503 * bar 5 offset for ADMASTAT regs for ck804 504 */ 505 #define CK804_ADMASTAT_X 0x4C4 506 #define CK804_ADMASTAT_Y 0x5C4 507 508 /* 509 * Bits for CK804_ADMASTAT_X and CK804_ADMASTAT_Y 510 */ 511 #define CK804_HPIRQ 0x4 512 #define MCP05_HUIRQ 0x2 513 514 515 /* 516 * bar 4 offset to bus master command registers 517 */ 518 #define BMICX_REG 0 519 520 /* 521 * bit definitions for BMICX_REG 522 */ 523 #define BMICX_SSBM 0x01 /* Start/Stop Bus Master */ 524 /* 1=Start (Enable) */ 525 /* 0=Start (Disable) */ 526 527 /* 528 * NOTE: "read" and "write" are the actions of the DMA engine 529 * on the PCI bus, not the SATA bus. Therefore for a ATA READ 530 * command, program the DMA engine to "write to memory" mode 531 * (and vice versa). 532 */ 533 #define BMICX_RWCON 0x08 /* Read/Write Control */ 534 #define BMICX_RWCON_WRITE_TO_MEMORY 0x08 /* 1=Write (dev to host) */ 535 #define BMICX_RWCON_READ_FROM_MEMORY 0x00 /* 0=Read (host to dev) */ 536 537 /* 538 * BMICX bits to preserve during updates 539 */ 540 #define BMICX_MASK (~(BMICX_SSBM | BMICX_RWCON)) 541 542 /* 543 * bar 4 offset to bus master status register 544 */ 545 #define BMISX_REG 2 546 547 /* 548 * bit fields for bus master status register 549 */ 550 #define BMISX_BMIDEA 0x01 /* Bus Master IDE Active */ 551 #define BMISX_IDERR 0x02 /* IDE DMA Error */ 552 #define BMISX_IDEINTS 0x04 /* IDE Interrupt Status */ 553 554 /* 555 * bus master status register bits to preserve 556 */ 557 #define BMISX_MASK 0xf8 558 559 /* 560 * bar4 offset to bus master PRD descriptor table 561 */ 562 #define BMIDTPX_REG 4 563 564 565 /* 566 * structure for a single entry in the PRD table 567 * (physical region descriptor table) 568 */ 569 typedef struct prde { 570 uint32_t p_address; /* physical address */ 571 uint32_t p_count; /* byte count, EOT in high order bit */ 572 } prde_t; 573 574 575 #define PRDE_EOT ((uint_t)0x80000000) 576 577 #define NV_DMA_NSEGS 256 /* XXX DEBUG TEST change back to 257 */ 578 579 /* 580 * ck804 and mcp55 both have 2 ports per controller 581 */ 582 #define NV_NUM_CPORTS 2 583 584 /* 585 * Number of slots to allocate in data nv_sata structures to handle 586 * multiple commands at once. This does not reflect the capability of 587 * the drive or the hardware, and in many cases will not match. 588 * 1 or 32 slots are allocated, so in cases where the driver has NCQ 589 * enabled but the drive doesn't support it, or supports fewer than 590 * 32 slots, here may be an over allocation of memory. 591 */ 592 #ifdef NCQ 593 #define NV_QUEUE_SLOTS 32 594 #else 595 #define NV_QUEUE_SLOTS 1 596 #endif 597 598 #define NV_BM_64K_BOUNDARY 0x10000ull 599 600 #define NV_MAX_INTR_PER_DEV 20 /* Empirical value */ 601 602 /* 603 * 1 second (in microseconds) 604 */ 605 #define NV_ONE_SEC 1000000 606 607 /* 608 * 1 millisecond (in microseconds) 609 */ 610 #define NV_ONE_MSEC 1000 611 612 /* 613 * Length of port reset (microseconds) - SControl bit 0 set to 1 614 */ 615 #define NV_RESET_LENGTH 1000 616 617 #define NV_RESET_ATTEMPTS 3 618 619 /* 620 * The maximum amount of time (milliseconds) a link can be down during 621 * reset without assuming that there is no device attached. 622 */ 623 #define NV_LINK_DOWN_TIMEOUT 10 624 625 /* 626 * The maximum amount of time (milliseconds) the signature acquisition can 627 * drag on before it is terminated. 628 * Some disks have very long acquisition times after hotplug, related to 629 * to spinning-up and reading some data from a media. 630 * The value below is empirical (20s) 631 * 632 */ 633 #define NV_SIG_ACQUISITION_TIME 20000 634 635 /* 636 * Minimum amount of time (milliseconds) to delay reporting hotplug 637 * (device added) event. 638 * It is the time allowed for a drive to initialize and to send a D2H FIS with 639 * a device signature. 640 * It varies between drives from a few milliseconds up to 20s. 641 */ 642 #define NV_HOTPLUG_DELAY 20000 643 644 /* 645 * nvp_state flags 646 */ 647 #define NV_PORT_INACTIVE 0x001 648 #define NV_PORT_ABORTING 0x002 649 #define NV_PORT_HOTREMOVED 0x004 650 #define NV_PORT_INIT 0x008 651 #define NV_PORT_FAILED 0x010 652 #define NV_PORT_RESET 0x020 653 #define NV_PORT_RESET_RETRY 0x040 654 #define NV_PORT_RESTORE 0x080 655 #define NV_PORT_PROBE 0x100 656 #define NV_PORT_HOTPLUG_DELAY 0x200 657 658 /* 659 * nvc_state flags 660 */ 661 #define NV_CTRL_SUSPEND 0x1 662 663 664 /* 665 * flags for ck804_set_intr/mcp5x_set_intr 666 */ 667 #define NV_INTR_DISABLE 0x1 668 #define NV_INTR_ENABLE 0x2 669 #define NV_INTR_CLEAR_ALL 0x4 670 #define NV_INTR_DISABLE_NON_BLOCKING 0x8 671 672 673 #define NV_BYTES_PER_SEC 512 674 675 #define NV_WAIT_REG_CHECK 10 /* 10 microseconds */ 676 #define NV_ATA_NUM_CMDS 256 /* max num ATA cmds possible, 8 bits */ 677 #define NV_PRINT_INTERVAL 40 /* throttle debug msg from flooding */ 678 #define MCP5X_INT_CLEAR 0xffff /* clear all interrupts */ 679 680 /* 681 * definition labels for the BAR registers 682 */ 683 #define NV_BAR_0 0 /* chan 0 task file regs */ 684 #define NV_BAR_1 1 /* chan 0 status reg */ 685 #define NV_BAR_2 2 /* chan 1 task file regs */ 686 #define NV_BAR_3 3 /* chan 1 status reg */ 687 #define NV_BAR_4 4 /* bus master regs */ 688 #define NV_BAR_5 5 /* extra regs mostly SATA related */ 689 690 /* 691 * transform seconds to microseconds 692 */ 693 #define NV_SEC2USEC(x) x * MICROSEC 694 695 696 /* 697 * ck804 maps in task file regs into bar 5. These are 698 * only used to identify ck804, therefore only this reg is 699 * listed here. 700 */ 701 #define NV_BAR5_TRAN_LEN_CH_X 0x518 702 703 /* 704 * if after this many iterations through the interrupt 705 * processing loop, declare the interrupt wedged and 706 * disable. 707 */ 708 #define NV_MAX_INTR_LOOP 10 709 710 /* 711 * flag values for nv_copy_regs_out 712 */ 713 #define NV_COPY_COMPLETE 0x01 /* normal command completion */ 714 #define NV_COPY_ERROR 0x02 /* error, did not complete ok */ 715 #define NV_COPY_SSREGS 0x04 /* SS port registers */ 716 717 #ifdef SGPIO_SUPPORT 718 #define NV_MAX_CBPS 16 /* Maximum # of Control Block */ 719 /* Pointers. Corresponds to */ 720 /* each MCP55 and IO55 */ 721 #define SGPIO_LOOP_WAIT_USECS 62500 /* 1/16 second (in usecs) */ 722 #define SGPIO_TQ_NAME_LEN 32 723 724 /* 725 * The drive number format is ccp (binary). 726 * cc is the controller number (0-based number) 727 * p is the port number (0 or 1) 728 */ 729 #define SGP_DRV_TO_PORT(d) ((d) & 1) 730 #define SGP_DRV_TO_CTLR(d) ((d) >> 1) 731 #define SGP_CTLR_PORT_TO_DRV(c, p) (((c) << 1) | ((p) & 1)) 732 #endif 733 734 #ifdef __cplusplus 735 } 736 #endif 737 738 #endif /* _NV_SATA_H */ 739