1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _NV_SATA_H 28 #define _NV_SATA_H 29 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 36 /* 37 * SGPIO Support 38 * Enable SGPIO support only on x86/x64, because it is implemented using 39 * functions that are only available on x86/x64. 40 */ 41 42 #define NV_MAX_PORTS(nvc) nvc->nvc_sata_hba_tran.sata_tran_hba_num_cports 43 44 typedef struct nv_port nv_port_t; 45 46 #ifdef SGPIO_SUPPORT 47 typedef struct nv_sgp_cmn nv_sgp_cmn_t; 48 #endif 49 50 typedef struct nv_ctl { 51 /* 52 * Each of these are specific to the chipset in use. 53 */ 54 uint_t (*nvc_interrupt)(caddr_t arg1, caddr_t arg2); 55 void (*nvc_reg_init)(struct nv_ctl *nvc, 56 ddi_acc_handle_t pci_conf_handle); 57 58 dev_info_t *nvc_dip; /* devinfo pointer of controller */ 59 60 struct nv_port *nvc_port; /* array of pointers to port struct */ 61 62 /* 63 * handle and base address to register space. 64 * 65 * 0: port 0 task file 66 * 1: port 0 status 67 * 2: port 1 task file 68 * 3: port 1 status 69 * 4: bus master for both ports 70 * 5: extended registers for SATA features 71 */ 72 ddi_acc_handle_t nvc_bar_hdl[6]; 73 uchar_t *nvc_bar_addr[6]; 74 75 /* 76 * sata registers in bar 5 which are shared on all devices 77 * on the channel. 78 */ 79 uint32_t *nvc_mcp55_ctl; 80 uint32_t *nvc_mcp55_ncq; /* NCQ status control bits */ 81 82 kmutex_t nvc_mutex; /* ctrl level lock */ 83 84 ddi_intr_handle_t *nvc_htable; /* For array of interrupts */ 85 int nvc_intr_type; /* What type of interrupt */ 86 int nvc_intr_cnt; /* # of intrs count returned */ 87 size_t nvc_intr_size; /* Size of intr array to */ 88 uint_t nvc_intr_pri; /* Interrupt priority */ 89 int nvc_intr_cap; /* Interrupt capabilities */ 90 uint8_t *nvc_mcp04_int_status; /* interrupt status mcp04 */ 91 92 sata_hba_tran_t nvc_sata_hba_tran; /* sata_hba_tran for ctrl */ 93 94 /* 95 * enable/disable interrupts, controller specific 96 */ 97 void (*nvc_set_intr)(nv_port_t *nvp, int flag); 98 int nvc_state; /* state flags of ctrl see below */ 99 uint8_t nvc_revid; /* PCI revid of device */ 100 101 #ifdef SGPIO_SUPPORT 102 int nvc_mcp55_flag; /* is the controller MCP55 or CK804 */ 103 uint8_t nvc_ctlr_num; /* controller number within the part */ 104 uint32_t nvc_sgp_csr; /* SGPIO CSR i/o address */ 105 volatile nv_sgp_cb_t *nvc_sgp_cbp; /* SGPIO Command Block */ 106 nv_sgp_cmn_t *nvc_sgp_cmn; /* SGPIO shared data */ 107 #endif 108 } nv_ctl_t; 109 110 111 struct nv_port { 112 113 struct nv_ctl *nvp_ctlp; /* back pointer to controller */ 114 115 uint8_t nvp_port_num; /* port number, ie 1 or 2 */ 116 117 uint8_t nvp_type; /* SATA_DTYPE_{NONE,ATADISK,UNKNOWN} */ 118 uint32_t nvp_signature; /* sig acquired from task file regs */ 119 uchar_t *nvp_cmd_addr; /* base addr for cmd regs for port */ 120 uchar_t *nvp_bm_addr; /* base addr for bus master for port */ 121 uchar_t *nvp_ctl_addr; /* base addr for ctrl regs for port */ 122 123 ddi_acc_handle_t nvp_cmd_hdl; 124 uchar_t *nvp_data; /* data register */ 125 uchar_t *nvp_error; /* error register (read) */ 126 uchar_t *nvp_feature; /* features (write) */ 127 uchar_t *nvp_count; /* sector count */ 128 uchar_t *nvp_sect; /* sector number */ 129 uchar_t *nvp_lcyl; /* cylinder low byte */ 130 uchar_t *nvp_hcyl; /* cylinder high byte */ 131 uchar_t *nvp_drvhd; /* drive/head register */ 132 uchar_t *nvp_status; /* status/command register */ 133 uchar_t *nvp_cmd; /* status/command register */ 134 135 ddi_acc_handle_t nvp_ctl_hdl; 136 uchar_t *nvp_altstatus; /* alternate status (read) */ 137 uchar_t *nvp_devctl; /* device control (write) */ 138 139 ddi_acc_handle_t nvp_bm_hdl; 140 uchar_t *nvp_bmisx; 141 uint32_t *nvp_bmidtpx; 142 uchar_t *nvp_bmicx; 143 144 ddi_dma_handle_t *nvp_sg_dma_hdl; /* dma handle to prd table */ 145 caddr_t *nvp_sg_addr; /* virtual addr of prd table */ 146 uint32_t *nvp_sg_paddr; /* physical address of prd table */ 147 ddi_acc_handle_t *nvp_sg_acc_hdl; /* mem acc handle to the prd table */ 148 149 uint32_t *nvp_sstatus; 150 uint32_t *nvp_serror; 151 uint32_t *nvp_sctrl; 152 uint32_t *nvp_sactive; 153 154 kmutex_t nvp_mutex; /* main per port mutex */ 155 kcondvar_t nvp_poll_cv; /* handshake cv between poll & isr */ 156 157 /* 158 * nvp_slot is a pointer to an array of nv_slot 159 */ 160 struct nv_slot *nvp_slot; 161 uint32_t nvp_sactive_cache; /* cache of SACTIVE */ 162 uint8_t nvp_queue_depth; 163 164 /* 165 * NCQ flow control. During NCQ operation, no other commands 166 * allowed. The following are used to enforce this. 167 */ 168 int nvp_ncq_run; 169 int nvp_non_ncq_run; 170 171 timeout_id_t nvp_timeout_id; 172 173 clock_t nvp_reset_time; /* time of last reset */ 174 clock_t nvp_probe_time; /* time when probe began */ 175 clock_t nvp_link_lost_time; /* time link lost was noticed */ 176 177 int nvp_state; /* state of port. flags defined below */ 178 179 uint16_t *nvp_mcp55_int_status; 180 uint16_t *nvp_mcp55_int_ctl; 181 182 #ifdef SGPIO_SUPPORT 183 uint8_t nvp_sgp_ioctl_mod; /* LEDs modified by ioctl */ 184 #endif 185 }; 186 187 188 typedef struct nv_device_table { 189 ushort_t vendor_id; /* vendor id */ 190 ushort_t device_id; /* device id */ 191 ushort_t type; /* chipset type, mcp04 or mcp55 */ 192 } nv_device_table_t; 193 194 195 typedef struct nv_slot { 196 caddr_t nvslot_v_addr; /* I/O buffer address */ 197 size_t nvslot_byte_count; /* # bytes left to read/write */ 198 sata_pkt_t *nvslot_spkt; 199 uint8_t nvslot_rqsense_buff[SATA_ATAPI_RQSENSE_LEN]; 200 clock_t nvslot_stime; 201 int (*nvslot_start)(nv_port_t *nvp, int queue); 202 void (*nvslot_intr)(nv_port_t *nvp, 203 struct nv_slot *nv_slotp); 204 uint32_t nvslot_flags; 205 } nv_slot_t; 206 207 208 #ifdef SGPIO_SUPPORT 209 struct nv_sgp_cmn { 210 uint16_t nvs_magic; /* verification of valid structure */ 211 uint8_t nvs_in_use; /* bit-field of active ctlrs */ 212 uint8_t nvs_connected; /* port connected bit-field flag */ 213 uint8_t nvs_activity; /* port usage bit-field flag */ 214 int nvs_taskq_delay; /* rest time for activity LED taskq */ 215 kmutex_t nvs_slock; /* lock for shared data */ 216 kmutex_t nvs_tlock; /* lock for taskq */ 217 kcondvar_t nvs_cv; /* condition variable for taskq wait */ 218 ddi_taskq_t *nvs_taskq; /* activity LED taskq */ 219 }; 220 #endif 221 222 223 /* 224 * nvslot_flags 225 */ 226 #define NVSLOT_COMPLETE 0x01 227 #define NVSLOT_NCQ 0x02 /* NCQ is active */ 228 #define NVSLOT_RQSENSE 0x04 /* processing request sense */ 229 230 /* 231 * state values for nv_attach 232 */ 233 #define ATTACH_PROGRESS_NONE (1 << 0) 234 #define ATTACH_PROGRESS_STATEP_ALLOC (1 << 1) 235 #define ATTACH_PROGRESS_PCI_HANDLE (1 << 2) 236 #define ATTACH_PROGRESS_BARS (1 << 3) 237 #define ATTACH_PROGRESS_INTR_ADDED (1 << 4) 238 #define ATTACH_PROGRESS_MUTEX_INIT (1 << 5) 239 #define ATTACH_PROGRESS_CTL_SETUP (1 << 6) 240 #define ATTACH_PROGRESS_TRAN_SETUP (1 << 7) 241 #define ATTACH_PROGRESS_COUNT (1 << 8) 242 #define ATTACH_PROGRESS_CONF_HANDLE (1 << 9) 243 #define ATTACH_PROGRESS_SATA_MODULE (1 << 10) 244 245 #ifdef DEBUG 246 247 #define NV_DEBUG 1 248 249 #endif /* DEBUG */ 250 251 252 /* 253 * nv_debug_flags 254 */ 255 #define NVDBG_ALWAYS 0x0001 256 #define NVDBG_INIT 0x0002 257 #define NVDBG_ENTRY 0x0004 258 #define NVDBG_DELIVER 0x0008 259 #define NVDBG_EVENT 0x0010 260 #define NVDBG_SYNC 0x0020 261 #define NVDBG_PKTCOMP 0x0040 262 #define NVDBG_TIMEOUT 0x0080 263 #define NVDBG_INFO 0x0100 264 #define NVDBG_VERBOSE 0x0200 265 #define NVDBG_INTR 0x0400 266 #define NVDBG_ERRS 0x0800 267 #define NVDBG_COOKIES 0x1000 268 #define NVDBG_HOT 0x2000 269 #define NVDBG_PROBE 0x4000 270 #define NVDBG_ATAPI 0x8000 271 272 #ifdef DEBUG 273 #define NVLOG(a) nv_log a 274 #else 275 #define NVLOG(a) 276 #endif 277 278 #define NV_SUCCESS 0 279 #define NV_FAILURE -1 280 281 /* 282 * indicates whether nv_wait functions can sleep or not. 283 */ 284 #define NV_SLEEP 1 285 #define NV_NOSLEEP 2 286 287 /* 288 * port offsets from base address ioaddr1 289 */ 290 #define NV_DATA 0x00 /* data register */ 291 #define NV_ERROR 0x01 /* error register (read) */ 292 #define NV_FEATURE 0x01 /* features (write) */ 293 #define NV_COUNT 0x02 /* sector count */ 294 #define NV_SECT 0x03 /* sector number */ 295 #define NV_LCYL 0x04 /* cylinder low byte */ 296 #define NV_HCYL 0x05 /* cylinder high byte */ 297 #define NV_DRVHD 0x06 /* drive/head register */ 298 #define NV_STATUS 0x07 /* status/command register */ 299 #define NV_CMD 0x07 /* status/command register */ 300 301 /* 302 * port offsets from base address ioaddr2 303 */ 304 #define NV_ALTSTATUS 0x02 /* alternate status (read) */ 305 #define NV_DEVCTL 0x02 /* device control (write) */ 306 307 /* 308 * device control register 309 */ 310 #define ATDC_NIEN 0x02 /* disable interrupts */ 311 #define ATDC_SRST 0x04 /* controller reset */ 312 #define ATDC_D3 0x08 /* mysterious bit */ 313 #define ATDC_HOB 0x80 /* high order byte to read 48-bit values */ 314 315 316 #define MCP55_CTL 0x400 /* queuing control */ 317 #define MCP55_INT_STATUS 0x440 /* status bits for interrupt */ 318 #define MCP55_INT_CTL 0x444 /* enable bits for interrupt */ 319 #define MCP55_NCQ 0x448 /* NCQ status and ctrl bits */ 320 321 /* 322 * if either of these bits are set, when using NCQ, if no other commands are 323 * active while a new command is started, DMA engine can be programmed ahead 324 * of time to save extra interrupt. Presumably pre-programming is discarded 325 * if a subsequent command ends up finishing first. 326 */ 327 #define MCP_SATA_AE_NCQ_PDEV_FIRST_CMD (1 << 7) 328 #define MCP_SATA_AE_NCQ_SDEV_FIRST_CMD (1 << 23) 329 330 /* 331 * bit definitions to indicate which NCQ command requires 332 * DMA setup. 333 */ 334 #define MCP_SATA_AE_NCQ_PDEV_DMA_SETUP_TAG_SHIFT 2 335 #define MCP_SATA_AE_NCQ_SDEV_DMA_SETUP_TAG_SHIFT 18 336 #define MCP_SATA_AE_NCQ_DMA_SETUP_TAG_MASK 0x1f 337 338 339 /* 340 * Bits for NV_MCP55_INT_CTL and NV_MCP55_INT_STATUS 341 */ 342 #define MCP55_INT_SNOTIFY 0x200 /* snotification set */ 343 #define MCP55_INT_SERROR 0x100 /* serror set */ 344 #define MCP55_INT_DMA_SETUP 0x80 /* DMA to be programmed */ 345 #define MCP55_INT_DH_REGFIS 0x40 /* REGFIS received */ 346 #define MCP55_INT_SDB_FIS 0x20 /* SDB FIS */ 347 #define MCP55_INT_TX_BACKOUT 0x10 /* TX backout */ 348 #define MCP55_INT_REM 0x08 /* device removed */ 349 #define MCP55_INT_ADD 0x04 /* device added */ 350 #define MCP55_INT_PM 0x02 /* power changed */ 351 #define MCP55_INT_COMPLETE 0x01 /* device interrupt */ 352 353 /* 354 * Bits above that are not used for now. 355 */ 356 #define MCP55_INT_IGNORE (MCP55_INT_DMA_SETUP|MCP55_INT_DH_REGFIS|\ 357 MCP55_INT_SDB_FIS|MCP55_INT_TX_BACKOUT|MCP55_INT_PM|\ 358 MCP55_INT_SNOTIFY|MCP55_INT_SERROR) 359 360 /* 361 * Bits for MCP_SATA_AE_CTL 362 */ 363 #define MCP_SATA_AE_CTL_PRI_SWNCQ (1 << 1) /* software NCQ chan 0 */ 364 #define MCP_SATA_AE_CTL_SEC_SWNCQ (1 << 2) /* software NCQ chan 1 */ 365 366 #define NV_DELAY_NSEC(wait_ns) \ 367 { \ 368 hrtime_t start, end; \ 369 start = end = gethrtime(); \ 370 while ((end - start) < wait_ns) \ 371 end = gethrtime(); \ 372 } 373 374 /* 375 * signatures in task file registers after device reset 376 */ 377 #define NV_SIG_DISK 0x00000101 378 #define NV_SIG_ATAPI 0xeb140101 379 #define NV_SIG_PM 0x96690101 380 #define NV_SIG_NOTREADY 0x00000000 381 382 /* 383 * These bar5 offsets are common to mcp55/mcp04 and thus 384 * prefixed with NV. 385 */ 386 #define NV_SSTATUS 0x00 387 #define NV_SERROR 0x04 388 #define NV_SCTRL 0x08 389 #define NV_SACTIVE 0x0c 390 #define NV_SNOTIFICATION 0x10 391 392 #define CH0_SREG_OFFSET 0x0 393 #define CH1_SREG_OFFSET 0x40 394 395 396 /* 397 * The following config space offsets are needed to enable 398 * bar 5 register access in mcp04/mcp55 399 */ 400 #define NV_SATA_CFG_20 0x50 401 #define NV_BAR5_SPACE_EN 0x04 402 #define NV_40BIT_PRD 0x20 403 404 /* 405 * mcp04 interrupt status register 406 */ 407 408 /* 409 * offsets to bar 5 registers 410 */ 411 #define MCP04_SATA_INT_STATUS 0x440 412 #define MCP04_SATA_INT_EN 0x441 413 414 415 /* 416 * bit fields for int status and int enable 417 * registers 418 */ 419 #define MCP04_INT_PDEV_INT 0x01 /* completion interrupt */ 420 #define MCP04_INT_PDEV_PM 0x02 /* power change */ 421 #define MCP04_INT_PDEV_ADD 0x04 /* hot plug */ 422 #define MCP04_INT_PDEV_REM 0x08 /* hot remove */ 423 #define MCP04_INT_PDEV_HOT MCP04_INT_PDEV_ADD|MCP04_INT_PDEV_REM 424 425 #define MCP04_INT_SDEV_INT 0x10 /* completion interrupt */ 426 #define MCP04_INT_SDEV_PM 0x20 /* power change */ 427 #define MCP04_INT_SDEV_ADD 0x40 /* hot plug */ 428 #define MCP04_INT_SDEV_REM 0x80 /* hot remove */ 429 #define MCP04_INT_SDEV_HOT MCP04_INT_SDEV_ADD|MCP04_INT_SDEV_REM 430 431 #define MCP04_INT_PDEV_ALL MCP04_INT_PDEV_INT|MCP04_INT_PDEV_HOT|\ 432 MCP04_INT_PDEV_PM 433 #define MCP04_INT_SDEV_ALL MCP04_INT_SDEV_INT|MCP04_INT_SDEV_HOT|\ 434 MCP04_INT_SDEV_PM 435 436 /* 437 * config space offset 42 438 */ 439 #define NV_SATA_CFG_42 0xac 440 441 /* 442 * bit in CFG_42 which delays hotplug interrupt until 443 * PHY ready 444 */ 445 #define MCP04_CFG_DELAY_HOTPLUG_INTR (0x1 << 12) 446 447 448 /* 449 * bar 5 offsets for SATA registers in ck804 450 */ 451 #define MCP04_CH1_SSTATUS 0x00 452 #define MCP04_CH1_SERROR 0x04 453 #define MCP04_CH1_SCTRL 0x08 454 #define MCP04_CH1_SACTIVE 0x0c 455 #define MCP04_CH1_SNOTIFICATION 0x10 456 457 #define MCP04_CH2_SSTATUS 0x40 458 #define MCP04_CH2_SERROR 0x44 459 #define MCP04_CH2_SCTRL 0x48 460 #define MCP04_CH2_SACTIVE 0x4c 461 #define MCP04_CH2_SNOTIFICATION 0x50 462 463 464 /* 465 * bar 5 offsets for ADMACTL settings for both mcp04/mcp55 466 */ 467 #define NV_ADMACTL_X 0x4C0 468 #define NV_ADMACTL_Y 0x5C0 469 470 /* 471 * Bits for NV_ADMACTL_X and NV_ADMACTL_Y 472 */ 473 #define NV_HIRQ_EN 0x01 /* hot plug/unplug interrupt enable */ 474 #define NV_CH_RST 0x04 /* reset channel */ 475 476 477 /* 478 * bar 5 offset for ADMASTAT regs for mcp04 479 */ 480 #define MCP04_ADMASTAT_X 0x4C4 481 #define MCP04_ADMASTAT_Y 0x5C4 482 483 /* 484 * Bits for MCP04_ADMASTAT_X and MCP04_ADMASTAT_Y 485 */ 486 #define MCP04_HPIRQ 0x4 487 #define MCP05_HUIRQ 0x2 488 489 490 /* 491 * bar 4 offset to bus master command registers 492 */ 493 #define BMICX_REG 0 494 495 /* 496 * bit definitions for BMICX_REG 497 */ 498 #define BMICX_SSBM 0x01 /* Start/Stop Bus Master */ 499 /* 1=Start (Enable) */ 500 /* 0=Start (Disable) */ 501 502 /* 503 * NOTE: "read" and "write" are the actions of the DMA engine 504 * on the PCI bus, not the SATA bus. Therefore for a ATA READ 505 * command, program the DMA engine to "write to memory" mode 506 * (and vice versa). 507 */ 508 #define BMICX_RWCON 0x08 /* Read/Write Control */ 509 #define BMICX_RWCON_WRITE_TO_MEMORY 0x08 /* 1=Write (dev to host) */ 510 #define BMICX_RWCON_READ_FROM_MEMORY 0x00 /* 0=Read (host to dev) */ 511 512 /* 513 * BMICX bits to preserve during updates 514 */ 515 #define BMICX_MASK (~(BMICX_SSBM | BMICX_RWCON)) 516 517 /* 518 * bar 4 offset to bus master status register 519 */ 520 #define BMISX_REG 2 521 522 /* 523 * bit fields for bus master status register 524 */ 525 #define BMISX_BMIDEA 0x01 /* Bus Master IDE Active */ 526 #define BMISX_IDERR 0x02 /* IDE DMA Error */ 527 #define BMISX_IDEINTS 0x04 /* IDE Interrupt Status */ 528 529 /* 530 * bus master status register bits to preserve 531 */ 532 #define BMISX_MASK 0xf8 533 534 /* 535 * bar4 offset to bus master PRD descriptor table 536 */ 537 #define BMIDTPX_REG 4 538 539 540 /* 541 * structure for a single entry in the PRD table 542 * (physical region descriptor table) 543 */ 544 typedef struct prde { 545 uint32_t p_address; /* physical address */ 546 uint32_t p_count; /* byte count, EOT in high order bit */ 547 } prde_t; 548 549 550 #define PRDE_EOT ((uint_t)0x80000000) 551 552 #define NV_DMA_NSEGS 256 /* XXX DEBUG TEST change back to 257 */ 553 554 /* 555 * ck804 and mcp55 both have 2 ports per controller 556 */ 557 #define NV_NUM_CPORTS 2 558 559 /* 560 * Number of slots to allocate in data nv_sata structures to handle 561 * multiple commands at once. This does not reflect the capability of 562 * the drive or the hardware, and in many cases will not match. 563 * 1 or 32 slots are allocated, so in cases where the driver has NCQ 564 * enabled but the drive doesn't support it, or supports fewer than 565 * 32 slots, here may be an over allocation of memory. 566 */ 567 #ifdef NCQ 568 #define NV_QUEUE_SLOTS 32 569 #else 570 #define NV_QUEUE_SLOTS 1 571 #endif 572 573 /* 574 * wait 30 seconds for signature 575 */ 576 #define NV_SIG_TIMEOUT 45 577 578 #define NV_BM_64K_BOUNDARY 0x10000ull 579 580 /* 581 * every 1 second 582 */ 583 #define NV_ONE_SEC 1000000 584 585 586 /* 587 * the amount of time link can be down during 588 * reset without taking action. 589 */ 590 #define NV_LINK_LOST_OK 2 591 592 /* 593 * nv_reset() flags 594 */ 595 #define NV_RESET_SEND_EVENT 0x1 /* send reset event to sata module */ 596 #define NV_RESET_WAIT 0x2 /* OK to block waiting for reset */ 597 598 599 600 #define NV_RESET_ATTEMPTS 3 601 602 /* 603 * nvp_state flags 604 */ 605 #define NV_PORT_INACTIVE 0x001 606 #define NV_PORT_ABORTING 0x002 607 #define NV_PORT_HOTREMOVED 0x004 608 #define NV_PORT_INIT 0x008 609 #define NV_PORT_FAILED 0x010 610 #define NV_PORT_RESET 0x020 611 #define NV_PORT_RESET_PROBE 0x040 612 #define NV_PORT_RESTORE 0x080 613 614 /* 615 * nvc_state flags 616 */ 617 #define NV_CTRL_SUSPEND 0x1 618 619 620 /* 621 * flags for mcp04_set_intr/mcp55_set_intr 622 */ 623 #define NV_INTR_DISABLE 0x1 624 #define NV_INTR_ENABLE 0x2 625 #define NV_INTR_CLEAR_ALL 0x4 626 #define NV_INTR_DISABLE_NON_BLOCKING 0x8 627 628 /* 629 * sizes of strings to allocate 630 */ 631 #define NV_STRING_10 10 632 #define NV_STRING_512 512 633 634 #define NV_BYTES_PER_SEC 512 635 636 #define NV_WAIT_REG_CHECK 10 /* 10 microseconds */ 637 #define NV_ATA_NUM_CMDS 256 /* max num ATA cmds possible, 8 bits */ 638 #define NV_PRINT_INTERVAL 40 /* throttle debug msg from flooding */ 639 #define MCP55_INT_CLEAR 0xffff /* clear all interrupts */ 640 641 /* 642 * definition labels for the BAR registers 643 */ 644 #define NV_BAR_0 0 /* chan 0 task file regs */ 645 #define NV_BAR_1 1 /* chan 0 status reg */ 646 #define NV_BAR_2 2 /* chan 1 task file regs */ 647 #define NV_BAR_3 3 /* chan 1 status reg */ 648 #define NV_BAR_4 4 /* bus master regs */ 649 #define NV_BAR_5 5 /* extra regs mostly SATA related */ 650 651 /* 652 * transform seconds to microseconds 653 */ 654 #define NV_SEC2USEC(x) x * MICROSEC 655 656 657 /* 658 * ck804 maps in task file regs into bar 5. These are 659 * only used to identify ck804, therefore only this reg is 660 * listed here. 661 */ 662 #define NV_BAR5_TRAN_LEN_CH_X 0x518 663 664 /* 665 * if after this many iterations through the interrupt 666 * processing loop, declare the interrupt wedged and 667 * disable. 668 */ 669 #define NV_MAX_INTR_LOOP 10 670 671 /* 672 * flag values for nv_copy_regs_out 673 */ 674 #define NV_COPY_COMPLETE 0x01 /* normal command completion */ 675 #define NV_COPY_ERROR 0x02 /* error, did not complete ok */ 676 #define NV_COPY_SSREGS 0x04 /* SS port registers */ 677 678 #ifdef SGPIO_SUPPORT 679 #define SGPIO_MAGIC 0x39da /* verifies good sgpio struct */ 680 #define SGPIO_LOOP_WAIT_USECS 62500 /* 1/16 second (in usecs) */ 681 #define SGPIO_TQ_NAME_LEN 32 682 683 /* 684 * The drive number format is ccp (binary). 685 * cc is the controller number (0-based number) 686 * p is the port number (0 or 1) 687 */ 688 #define SGP_DRV_TO_PORT(d) ((d) & 1) 689 #define SGP_DRV_TO_CTLR(d) ((d) >> 1) 690 #define SGP_CTLR_PORT_TO_DRV(c, p) (((c) << 1) | ((p) & 1)) 691 #endif 692 693 #ifdef __cplusplus 694 } 695 #endif 696 697 #endif /* _NV_SATA_H */ 698