1*98f0a994SHans Rosenfeld /* 2*98f0a994SHans Rosenfeld * This file and its contents are supplied under the terms of the 3*98f0a994SHans Rosenfeld * Common Development and Distribution License ("CDDL"), version 1.0. 4*98f0a994SHans Rosenfeld * You may only use this file in accordance with the terms of version 5*98f0a994SHans Rosenfeld * 1.0 of the CDDL. 6*98f0a994SHans Rosenfeld * 7*98f0a994SHans Rosenfeld * A full copy of the text of the CDDL should have accompanied this 8*98f0a994SHans Rosenfeld * source. A copy of the CDDL is also available via the Internet at 9*98f0a994SHans Rosenfeld * http://www.illumos.org/license/CDDL. 10*98f0a994SHans Rosenfeld */ 11*98f0a994SHans Rosenfeld 12*98f0a994SHans Rosenfeld /* 13*98f0a994SHans Rosenfeld * Copyright 2024 Racktop Systems, Inc. 14*98f0a994SHans Rosenfeld */ 15*98f0a994SHans Rosenfeld 16*98f0a994SHans Rosenfeld #ifndef _MFI_H 17*98f0a994SHans Rosenfeld #define _MFI_H 18*98f0a994SHans Rosenfeld 19*98f0a994SHans Rosenfeld #include <sys/bitext.h> 20*98f0a994SHans Rosenfeld #include <sys/debug.h> 21*98f0a994SHans Rosenfeld #include <sys/stddef.h> 22*98f0a994SHans Rosenfeld 23*98f0a994SHans Rosenfeld #ifdef __cplusplus 24*98f0a994SHans Rosenfeld extern "C" { 25*98f0a994SHans Rosenfeld #endif 26*98f0a994SHans Rosenfeld 27*98f0a994SHans Rosenfeld /* 28*98f0a994SHans Rosenfeld * Forward declaration of various types defined by the MFI headers. 29*98f0a994SHans Rosenfeld */ 30*98f0a994SHans Rosenfeld typedef struct mfi_drv_ver mfi_drv_ver_t; 31*98f0a994SHans Rosenfeld typedef struct mfi_pci_info mfi_pci_info_t; 32*98f0a994SHans Rosenfeld typedef struct mfi_ioctl mfi_ioctl_t; 33*98f0a994SHans Rosenfeld 34*98f0a994SHans Rosenfeld typedef union mfi_cap mfi_cap_t; 35*98f0a994SHans Rosenfeld typedef union mfi_sgl mfi_sgl_t; 36*98f0a994SHans Rosenfeld typedef struct mfi_header mfi_header_t; 37*98f0a994SHans Rosenfeld typedef struct mfi_init_payload mfi_init_payload_t; 38*98f0a994SHans Rosenfeld typedef struct mfi_io_payload mfi_io_payload_t; 39*98f0a994SHans Rosenfeld typedef struct mfi_pthru_payload mfi_pthru_payload_t; 40*98f0a994SHans Rosenfeld typedef struct mfi_dcmd_payload mfi_dcmd_payload_t; 41*98f0a994SHans Rosenfeld typedef struct mfi_abort_payload mfi_abort_payload_t; 42*98f0a994SHans Rosenfeld typedef struct mfi_frame mfi_frame_t; 43*98f0a994SHans Rosenfeld 44*98f0a994SHans Rosenfeld typedef struct mfi_array mfi_array_t; 45*98f0a994SHans Rosenfeld typedef struct mfi_spare mfi_spare_t; 46*98f0a994SHans Rosenfeld 47*98f0a994SHans Rosenfeld typedef struct mfi_ld_config mfi_ld_config_t; 48*98f0a994SHans Rosenfeld typedef struct mfi_ld_info mfi_ld_info_t; 49*98f0a994SHans Rosenfeld typedef struct mfi_ld_list mfi_ld_list_t; 50*98f0a994SHans Rosenfeld typedef struct mfi_ld_parameters mfi_ld_parameters_t; 51*98f0a994SHans Rosenfeld typedef struct mfi_ld_progress mfi_ld_progress_t; 52*98f0a994SHans Rosenfeld typedef struct mfi_ld_properties mfi_ld_properties_t; 53*98f0a994SHans Rosenfeld typedef struct mfi_ld_ref mfi_ld_ref_t; 54*98f0a994SHans Rosenfeld typedef struct mfi_ld_tgtid_list mfi_ld_tgtid_list_t; 55*98f0a994SHans Rosenfeld typedef struct mfi_span mfi_span_t; 56*98f0a994SHans Rosenfeld 57*98f0a994SHans Rosenfeld typedef struct mfi_config_data mfi_config_data_t; 58*98f0a994SHans Rosenfeld 59*98f0a994SHans Rosenfeld typedef struct mfi_pd_ref mfi_pd_ref_t; 60*98f0a994SHans Rosenfeld typedef struct mfi_pd_info mfi_pd_info_t; 61*98f0a994SHans Rosenfeld typedef struct mfi_pd_cfg mfi_pd_cfg_t; 62*98f0a994SHans Rosenfeld typedef struct mfi_pd_map mfi_pd_map_t; 63*98f0a994SHans Rosenfeld typedef struct mfi_pd_addr mfi_pd_addr_t; 64*98f0a994SHans Rosenfeld typedef struct mfi_pd_list mfi_pd_list_t; 65*98f0a994SHans Rosenfeld 66*98f0a994SHans Rosenfeld typedef struct mfi_ctrl_props mfi_ctrl_props_t; 67*98f0a994SHans Rosenfeld typedef struct mfi_image_comp mfi_image_comp_t; 68*98f0a994SHans Rosenfeld typedef struct mfi_ctrl_info mfi_ctrl_info_t; 69*98f0a994SHans Rosenfeld 70*98f0a994SHans Rosenfeld typedef struct mfi_bbu_capacity mfi_bbu_capacity_t; 71*98f0a994SHans Rosenfeld typedef struct mfi_bbu_design_info mfi_bbu_design_info_t; 72*98f0a994SHans Rosenfeld typedef struct mfi_bbu_properties mfi_bbu_properties_t; 73*98f0a994SHans Rosenfeld typedef struct mfi_ibbu_state mfi_ibbu_state_t; 74*98f0a994SHans Rosenfeld typedef struct mfi_bbu_state mfi_bbu_state_t; 75*98f0a994SHans Rosenfeld typedef struct mfi_bbu_status mfi_bbu_status_t; 76*98f0a994SHans Rosenfeld 77*98f0a994SHans Rosenfeld typedef struct mfi_pr_properties mfi_pr_properties_t; 78*98f0a994SHans Rosenfeld typedef struct mfi_pr_status mfi_pr_status_t; 79*98f0a994SHans Rosenfeld 80*98f0a994SHans Rosenfeld typedef struct mfi_progress mfi_progress_t; 81*98f0a994SHans Rosenfeld 82*98f0a994SHans Rosenfeld /* 83*98f0a994SHans Rosenfeld * MegaRAID Firmware Interface 84*98f0a994SHans Rosenfeld * 85*98f0a994SHans Rosenfeld * MFI stands for MegaRAID Firmware Interface. This is just a moniker 86*98f0a994SHans Rosenfeld * for the protocol between the software and the firmware. Commands are 87*98f0a994SHans Rosenfeld * issued using "message frames". 88*98f0a994SHans Rosenfeld */ 89*98f0a994SHans Rosenfeld 90*98f0a994SHans Rosenfeld #define MFI_MAX_LOGICAL_DRIVES 64 91*98f0a994SHans Rosenfeld #define MFI_MAX_PHYSICAL_DRIVES 256 92*98f0a994SHans Rosenfeld 93*98f0a994SHans Rosenfeld /* 94*98f0a994SHans Rosenfeld * During FW init, clear pending cmds & reset state using the doorbell register 95*98f0a994SHans Rosenfeld * 96*98f0a994SHans Rosenfeld * ABORT: Abort all pending cmds 97*98f0a994SHans Rosenfeld * READY: Move from OPERATIONAL to READY state; discard queue info 98*98f0a994SHans Rosenfeld * MFIMODE: Discard (possible) low MFA posted in 64-bit mode (??) 99*98f0a994SHans Rosenfeld * CLEAR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver 100*98f0a994SHans Rosenfeld * HOTPLUG: Resume from Hotplug 101*98f0a994SHans Rosenfeld * MFI_STOP_ADP: Send signal to FW to stop processing 102*98f0a994SHans Rosenfeld */ 103*98f0a994SHans Rosenfeld #define MFI_INIT_ABORT 0x00000001 104*98f0a994SHans Rosenfeld #define MFI_INIT_READY 0x00000002 105*98f0a994SHans Rosenfeld #define MFI_INIT_MFIMODE 0x00000004 106*98f0a994SHans Rosenfeld #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 107*98f0a994SHans Rosenfeld #define MFI_INIT_HOTPLUG 0x00000010 108*98f0a994SHans Rosenfeld #define MFI_STOP_ADP 0x00000020 109*98f0a994SHans Rosenfeld #define MFI_RESET_FLAGS (MFI_INIT_READY | MFI_INIT_MFIMODE | MFI_INIT_ABORT) 110*98f0a994SHans Rosenfeld 111*98f0a994SHans Rosenfeld /* 112*98f0a994SHans Rosenfeld * MFI frame flags 113*98f0a994SHans Rosenfeld */ 114*98f0a994SHans Rosenfeld #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 115*98f0a994SHans Rosenfeld #define MFI_FRAME_SGL64 0x0002 116*98f0a994SHans Rosenfeld #define MFI_FRAME_SENSE64 0x0004 117*98f0a994SHans Rosenfeld #define MFI_FRAME_DIR_NONE 0 118*98f0a994SHans Rosenfeld #define MFI_FRAME_DIR_WRITE 0x0008 119*98f0a994SHans Rosenfeld #define MFI_FRAME_DIR_READ 0x0010 120*98f0a994SHans Rosenfeld #define MFI_FRAME_DIR_BOTH 0x0018 121*98f0a994SHans Rosenfeld #define MFI_FRAME_IEEE 0x0020 122*98f0a994SHans Rosenfeld 123*98f0a994SHans Rosenfeld /* 124*98f0a994SHans Rosenfeld * MFI command opcodes 125*98f0a994SHans Rosenfeld */ 126*98f0a994SHans Rosenfeld #define MFI_CMD_INIT 0x00 127*98f0a994SHans Rosenfeld #define MFI_CMD_LD_READ 0x01 128*98f0a994SHans Rosenfeld #define MFI_CMD_LD_WRITE 0x02 129*98f0a994SHans Rosenfeld #define MFI_CMD_LD_SCSI_IO 0x03 130*98f0a994SHans Rosenfeld #define MFI_CMD_PD_SCSI_IO 0x04 131*98f0a994SHans Rosenfeld #define MFI_CMD_DCMD 0x05 132*98f0a994SHans Rosenfeld #define MFI_CMD_ABORT 0x06 133*98f0a994SHans Rosenfeld #define MFI_CMD_SMP 0x07 134*98f0a994SHans Rosenfeld #define MFI_CMD_STP 0x08 135*98f0a994SHans Rosenfeld #define MFI_CMD_INVALID 0xff 136*98f0a994SHans Rosenfeld 137*98f0a994SHans Rosenfeld /* 138*98f0a994SHans Rosenfeld * MFI command status completion codes 139*98f0a994SHans Rosenfeld */ 140*98f0a994SHans Rosenfeld #define MFI_STAT_OK 0x00 141*98f0a994SHans Rosenfeld #define MFI_STAT_INVALID_CMD 0x01 142*98f0a994SHans Rosenfeld #define MFI_STAT_INVALID_DCMD 0x02 143*98f0a994SHans Rosenfeld #define MFI_STAT_INVALID_PARAMETER 0x03 144*98f0a994SHans Rosenfeld #define MFI_STAT_INVALID_SEQUENCE_NUMBER 0x04 145*98f0a994SHans Rosenfeld #define MFI_STAT_ABORT_NOT_POSSIBLE 0x05 146*98f0a994SHans Rosenfeld #define MFI_STAT_APP_HOST_CODE_NOT_FOUND 0x06 147*98f0a994SHans Rosenfeld #define MFI_STAT_APP_IN_USE 0x07 148*98f0a994SHans Rosenfeld #define MFI_STAT_APP_NOT_INITIALIZED 0x08 149*98f0a994SHans Rosenfeld #define MFI_STAT_ARRAY_INDEX_INVALID 0x09 150*98f0a994SHans Rosenfeld #define MFI_STAT_ARRAY_ROW_NOT_EMPTY 0x0a 151*98f0a994SHans Rosenfeld #define MFI_STAT_CONFIG_RESOURCE_CONFLICT 0x0b 152*98f0a994SHans Rosenfeld #define MFI_STAT_DEVICE_NOT_FOUND 0x0c 153*98f0a994SHans Rosenfeld #define MFI_STAT_DRIVE_TOO_SMALL 0x0d 154*98f0a994SHans Rosenfeld #define MFI_STAT_FLASH_ALLOC_FAIL 0x0e 155*98f0a994SHans Rosenfeld #define MFI_STAT_FLASH_BUSY 0x0f 156*98f0a994SHans Rosenfeld #define MFI_STAT_FLASH_ERROR 0x10 157*98f0a994SHans Rosenfeld #define MFI_STAT_FLASH_IMAGE_BAD 0x11 158*98f0a994SHans Rosenfeld #define MFI_STAT_FLASH_IMAGE_INCOMPLETE 0x12 159*98f0a994SHans Rosenfeld #define MFI_STAT_FLASH_NOT_OPEN 0x13 160*98f0a994SHans Rosenfeld #define MFI_STAT_FLASH_NOT_STARTED 0x14 161*98f0a994SHans Rosenfeld #define MFI_STAT_FLUSH_FAILED 0x15 162*98f0a994SHans Rosenfeld #define MFI_STAT_HOST_CODE_NOT_FOUNT 0x16 163*98f0a994SHans Rosenfeld #define MFI_STAT_LD_CC_IN_PROGRESS 0x17 164*98f0a994SHans Rosenfeld #define MFI_STAT_LD_INIT_IN_PROGRESS 0x18 165*98f0a994SHans Rosenfeld #define MFI_STAT_LD_LBA_OUT_OF_RANGE 0x19 166*98f0a994SHans Rosenfeld #define MFI_STAT_LD_MAX_CONFIGURED 0x1a 167*98f0a994SHans Rosenfeld #define MFI_STAT_LD_NOT_OPTIMAL 0x1b 168*98f0a994SHans Rosenfeld #define MFI_STAT_LD_RBLD_IN_PROGRESS 0x1c 169*98f0a994SHans Rosenfeld #define MFI_STAT_LD_RECON_IN_PROGRESS 0x1d 170*98f0a994SHans Rosenfeld #define MFI_STAT_LD_WRONG_RAID_LEVEL 0x1e 171*98f0a994SHans Rosenfeld #define MFI_STAT_MAX_SPARES_EXCEEDED 0x1f 172*98f0a994SHans Rosenfeld #define MFI_STAT_MEMORY_NOT_AVAILABLE 0x20 173*98f0a994SHans Rosenfeld #define MFI_STAT_MFC_HW_ERROR 0x21 174*98f0a994SHans Rosenfeld #define MFI_STAT_NO_HW_PRESENT 0x22 175*98f0a994SHans Rosenfeld #define MFI_STAT_NOT_FOUND 0x23 176*98f0a994SHans Rosenfeld #define MFI_STAT_NOT_IN_ENCL 0x24 177*98f0a994SHans Rosenfeld #define MFI_STAT_PD_CLEAR_IN_PROGRESS 0x25 178*98f0a994SHans Rosenfeld #define MFI_STAT_PD_TYPE_WRONG 0x26 179*98f0a994SHans Rosenfeld #define MFI_STAT_PR_DISABLED 0x27 180*98f0a994SHans Rosenfeld #define MFI_STAT_ROW_INDEX_INVALID 0x28 181*98f0a994SHans Rosenfeld #define MFI_STAT_SAS_CONFIG_INVALID_ACTION 0x29 182*98f0a994SHans Rosenfeld #define MFI_STAT_SAS_CONFIG_INVALID_DATA 0x2a 183*98f0a994SHans Rosenfeld #define MFI_STAT_SAS_CONFIG_INVALID_PAGE 0x2b 184*98f0a994SHans Rosenfeld #define MFI_STAT_SAS_CONFIG_INVALID_TYPE 0x2c 185*98f0a994SHans Rosenfeld #define MFI_STAT_SCSI_DONE_WITH_ERROR 0x2d 186*98f0a994SHans Rosenfeld #define MFI_STAT_SCSI_IO_FAILED 0x2e 187*98f0a994SHans Rosenfeld #define MFI_STAT_SCSI_RESERVATION_CONFLICT 0x2f 188*98f0a994SHans Rosenfeld #define MFI_STAT_SHUTDOWN_FAILED 0x30 189*98f0a994SHans Rosenfeld #define MFI_STAT_TIME_NOT_SET 0x31 190*98f0a994SHans Rosenfeld #define MFI_STAT_WRONG_STATE 0x32 191*98f0a994SHans Rosenfeld #define MFI_STAT_LD_OFFLINE 0x33 192*98f0a994SHans Rosenfeld #define MFI_STAT_PEER_NOTIFICATION_REJECTED 0x34 193*98f0a994SHans Rosenfeld #define MFI_STAT_PEER_NOTIFICATION_FAILED 0x35 194*98f0a994SHans Rosenfeld #define MFI_STAT_RESERVATION_IN_PROGRESS 0x36 195*98f0a994SHans Rosenfeld #define MFI_STAT_I2C_ERRORS_DETECTED 0x37 196*98f0a994SHans Rosenfeld #define MFI_STAT_PCI_ERRORS_DETECTED 0x38 197*98f0a994SHans Rosenfeld #define MFI_STAT_CONFIG_SEQ_MISMATCH 0x67 198*98f0a994SHans Rosenfeld 199*98f0a994SHans Rosenfeld #define MFI_STAT_INVALID_STATUS 0xFF 200*98f0a994SHans Rosenfeld 201*98f0a994SHans Rosenfeld /* 202*98f0a994SHans Rosenfeld * MFI DCMDs 203*98f0a994SHans Rosenfeld */ 204*98f0a994SHans Rosenfeld #define MFI_DCMD_CTRL_GET_INFO 0x01010000 205*98f0a994SHans Rosenfeld #define MFI_DCMD_CTRL_GET_PROPS 0x01020100 206*98f0a994SHans Rosenfeld #define MFI_DCMD_CTRL_SET_PROPS 0x01020200 207*98f0a994SHans Rosenfeld #define MFI_DCMD_CTRL_EVENT_GET_INFO 0x01040100 208*98f0a994SHans Rosenfeld #define MFI_DCMD_CTRL_EVENT_GET 0x01040300 209*98f0a994SHans Rosenfeld #define MFI_DCMD_CTRL_EVENT_WAIT 0x01040500 210*98f0a994SHans Rosenfeld #define MFI_DCMD_CTRL_SHUTDOWN 0x01050000 211*98f0a994SHans Rosenfeld #define MFI_DCMD_PR_GET_STATUS 0x01070100 212*98f0a994SHans Rosenfeld #define MFI_DCMD_PR_GET_PROPERTIES 0x01070200 213*98f0a994SHans Rosenfeld #define MFI_DCMD_PR_SET_PROPERTIES 0x01070300 214*98f0a994SHans Rosenfeld #define MFI_DCMD_PR_START 0x01070400 215*98f0a994SHans Rosenfeld #define MFI_DCMD_PR_STOP 0x01070500 216*98f0a994SHans Rosenfeld #define MFI_DCMD_TIME_SECS_GET 0x01080201 217*98f0a994SHans Rosenfeld #define MFI_DCMD_FLASH_FW_OPEN 0x010f0100 218*98f0a994SHans Rosenfeld #define MFI_DCMD_FLASH_FW_DOWNLOAD 0x010f0200 219*98f0a994SHans Rosenfeld #define MFI_DCMD_FLASH_FW_FLASH 0x010f0300 220*98f0a994SHans Rosenfeld #define MFI_DCMD_FLASH_FW_CLOSE 0x010f0400 221*98f0a994SHans Rosenfeld #define MFI_DCMD_SYSTEM_PD_MAP_GET_INFO 0x0200e102 222*98f0a994SHans Rosenfeld #define MFI_DCMD_PD_GET_LIST 0x02010000 223*98f0a994SHans Rosenfeld #define MFI_DCMD_PD_LIST_QUERY 0x02010100 224*98f0a994SHans Rosenfeld #define MFI_DCMD_PD_GET_INFO 0x02020000 225*98f0a994SHans Rosenfeld #define MFI_DCMD_PD_STATE_SET 0x02030100 226*98f0a994SHans Rosenfeld #define MFI_DCMD_PD_REBUILD_START 0x02040100 227*98f0a994SHans Rosenfeld #define MFI_DCMD_PD_REBUILD_ABORT 0x02040200 228*98f0a994SHans Rosenfeld #define MFI_DCMD_PD_CLEAR_START 0x02050100 229*98f0a994SHans Rosenfeld #define MFI_DCMD_PD_CLEAR_ABORT 0x02050200 230*98f0a994SHans Rosenfeld #define MFI_DCMD_PD_LOCATE_START 0x02070100 231*98f0a994SHans Rosenfeld #define MFI_DCMD_PD_LOCATE_STOP 0x02070200 232*98f0a994SHans Rosenfeld #define MFI_DCMD_LD_MAP_GET_INFO 0x0300e101 233*98f0a994SHans Rosenfeld #define MFI_DCMD_LD_GET_LIST 0x03010000 234*98f0a994SHans Rosenfeld #define MFI_DCMD_LD_GET_INFO 0x03020000 235*98f0a994SHans Rosenfeld #define MFI_DCMD_LD_GET_PROP 0x03030000 236*98f0a994SHans Rosenfeld #define MFI_DCMD_LD_SET_PROP 0x03040000 237*98f0a994SHans Rosenfeld #define MFI_DCMD_LD_LIST_QUERY 0x03010100 238*98f0a994SHans Rosenfeld #define MFI_DCMD_LD_DELETE 0x03090000 239*98f0a994SHans Rosenfeld #define MFI_DCMD_CFG_READ 0x04010000 240*98f0a994SHans Rosenfeld #define MFI_DCMD_CFG_ADD 0x04020000 241*98f0a994SHans Rosenfeld #define MFI_DCMD_CFG_CLEAR 0x04030000 242*98f0a994SHans Rosenfeld #define MFI_DCMD_CFG_MAKE_SPARE 0x04040000 243*98f0a994SHans Rosenfeld #define MFI_DCMD_CFG_REMOVE_SPARE 0x04050000 244*98f0a994SHans Rosenfeld #define MFI_DCMD_CFG_FOREIGN_SCAN 0x04060100 245*98f0a994SHans Rosenfeld #define MFI_DCMD_CFG_FOREIGN_DISPLAY 0x04060200 246*98f0a994SHans Rosenfeld #define MFI_DCMD_CFG_FOREIGN_PREVIEW 0x04060300 247*98f0a994SHans Rosenfeld #define MFI_DCMD_CFG_FOREIGN_IMPORT 0x04060400 248*98f0a994SHans Rosenfeld #define MFI_DCMD_CFG_FOREIGN_CLEAR 0x04060500 249*98f0a994SHans Rosenfeld #define MFI_DCMD_BBU_GET_STATUS 0x05010000 250*98f0a994SHans Rosenfeld #define MFI_DCMD_BBU_GET_CAPACITY_INFO 0x05020000 251*98f0a994SHans Rosenfeld #define MFI_DCMD_BBU_GET_DESIGN_INFO 0x05030000 252*98f0a994SHans Rosenfeld #define MFI_DCMD_BBU_START_LEARN 0x05040000 253*98f0a994SHans Rosenfeld #define MFI_DCMD_BBU_GET_PROP 0x05050100 254*98f0a994SHans Rosenfeld #define MFI_DCMD_BBU_SET_PROP 0x05050200 255*98f0a994SHans Rosenfeld 256*98f0a994SHans Rosenfeld #define MFI_BBU_TYPE_NONE 0 257*98f0a994SHans Rosenfeld #define MFI_BBU_TYPE_IBBU 1 258*98f0a994SHans Rosenfeld #define MFI_BBU_TYPE_BBU 2 259*98f0a994SHans Rosenfeld 260*98f0a994SHans Rosenfeld #define MFI_PR_STATE_STOPPED 0 261*98f0a994SHans Rosenfeld #define MFI_PR_STATE_READY 1 262*98f0a994SHans Rosenfeld #define MFI_PR_STATE_ACTIVE 2 263*98f0a994SHans Rosenfeld #define MFI_PR_STATE_ABORTED 3 264*98f0a994SHans Rosenfeld 265*98f0a994SHans Rosenfeld #define MFI_PR_OPMODE_AUTO 0 266*98f0a994SHans Rosenfeld #define MFI_PR_OPMODE_MANUAL 1 267*98f0a994SHans Rosenfeld #define MFI_PR_OPMODE_DISABLED 2 268*98f0a994SHans Rosenfeld 269*98f0a994SHans Rosenfeld #define MFI_PD_QUERY_TYPE_ALL 0 270*98f0a994SHans Rosenfeld #define MFI_PD_QUERY_TYPE_STATE 1 271*98f0a994SHans Rosenfeld #define MFI_PD_QUERY_TYPE_POWER_STATE 2 272*98f0a994SHans Rosenfeld #define MFI_PD_QUERY_TYPE_MEDIA_TYPE 3 273*98f0a994SHans Rosenfeld #define MFI_PD_QUERY_TYPE_SPEED 4 274*98f0a994SHans Rosenfeld #define MFI_PD_QUERY_TYPE_EXPOSED_TO_HOST 5 275*98f0a994SHans Rosenfeld 276*98f0a994SHans Rosenfeld #define MFI_LD_QUERY_TYPE_ALL 0 277*98f0a994SHans Rosenfeld #define MFI_LD_QUERY_TYPE_EXPOSED_TO_HOST 1 278*98f0a994SHans Rosenfeld #define MFI_LD_QUERY_TYPE_USED_TGT_IDS 2 279*98f0a994SHans Rosenfeld #define MFI_LD_QUERY_TYPE_CLUSTER_ACCESS 3 280*98f0a994SHans Rosenfeld #define MFI_LD_QUERY_TYPE_CLUSTER_LOCALE 4 281*98f0a994SHans Rosenfeld 282*98f0a994SHans Rosenfeld #define MFI_DCMD_MBOX_PEND_FLAG 0x01 283*98f0a994SHans Rosenfeld 284*98f0a994SHans Rosenfeld #pragma pack(1) 285*98f0a994SHans Rosenfeld 286*98f0a994SHans Rosenfeld union mfi_cap { 287*98f0a994SHans Rosenfeld struct { 288*98f0a994SHans Rosenfeld uint32_t mc_support_fp_remote_lun:1; 289*98f0a994SHans Rosenfeld uint32_t mc_support_additional_msix:1; 290*98f0a994SHans Rosenfeld uint32_t mc_support_fastpath_wb:1; 291*98f0a994SHans Rosenfeld uint32_t mc_support_max_255lds:1; 292*98f0a994SHans Rosenfeld uint32_t mc_support_ndrive_r1_lb:1; 293*98f0a994SHans Rosenfeld uint32_t mc_support_core_affinity:1; 294*98f0a994SHans Rosenfeld uint32_t mc_support_security_protocol_cmds_fw:1; 295*98f0a994SHans Rosenfeld uint32_t mc_support_ext_queue_depth:1; 296*98f0a994SHans Rosenfeld uint32_t mc_support_ext_io_size:1; 297*98f0a994SHans Rosenfeld uint32_t mc_reserved:23; 298*98f0a994SHans Rosenfeld }; 299*98f0a994SHans Rosenfeld uint32_t mc_reg; 300*98f0a994SHans Rosenfeld }; 301*98f0a994SHans Rosenfeld CTASSERT(sizeof (mfi_cap_t) == 4); 302*98f0a994SHans Rosenfeld 303*98f0a994SHans Rosenfeld union mfi_sgl { 304*98f0a994SHans Rosenfeld struct { 305*98f0a994SHans Rosenfeld uint32_t ms32_phys_addr; 306*98f0a994SHans Rosenfeld uint32_t ms32_length; 307*98f0a994SHans Rosenfeld }; 308*98f0a994SHans Rosenfeld struct { 309*98f0a994SHans Rosenfeld uint64_t ms64_phys_addr; 310*98f0a994SHans Rosenfeld uint32_t ms64_length; 311*98f0a994SHans Rosenfeld }; 312*98f0a994SHans Rosenfeld }; 313*98f0a994SHans Rosenfeld 314*98f0a994SHans Rosenfeld struct mfi_header { 315*98f0a994SHans Rosenfeld uint8_t mh_cmd; /* 0x00 */ 316*98f0a994SHans Rosenfeld uint8_t mh_sense_len; /* 0x01 */ 317*98f0a994SHans Rosenfeld uint8_t mh_cmd_status; /* 0x02 */ 318*98f0a994SHans Rosenfeld uint8_t mh_scsi_status; /* 0x03 */ 319*98f0a994SHans Rosenfeld 320*98f0a994SHans Rosenfeld union { 321*98f0a994SHans Rosenfeld mfi_cap_t mh_drv_opts; /* 0x04 */ 322*98f0a994SHans Rosenfeld struct { 323*98f0a994SHans Rosenfeld uint8_t mh_target_id; /* 0x04 */ 324*98f0a994SHans Rosenfeld union { 325*98f0a994SHans Rosenfeld uint8_t mh_lun; /* 0x05 */ 326*98f0a994SHans Rosenfeld uint8_t mh_access_byte; /* 0x05 */ 327*98f0a994SHans Rosenfeld }; 328*98f0a994SHans Rosenfeld uint8_t mh_cdb_len; /* 0x06 */ 329*98f0a994SHans Rosenfeld uint8_t mh_sge_count; /* 0x07 */ 330*98f0a994SHans Rosenfeld }; 331*98f0a994SHans Rosenfeld }; 332*98f0a994SHans Rosenfeld 333*98f0a994SHans Rosenfeld uint32_t mh_context; /* 0x08 */ 334*98f0a994SHans Rosenfeld uint32_t mh_pad_0; /* 0x0c */ 335*98f0a994SHans Rosenfeld 336*98f0a994SHans Rosenfeld uint16_t mh_flags; /* 0x10 */ 337*98f0a994SHans Rosenfeld uint16_t mh_timeout; /* 0x12 */ 338*98f0a994SHans Rosenfeld union { 339*98f0a994SHans Rosenfeld uint32_t mh_data_xfer_len; /* 0x14 */ 340*98f0a994SHans Rosenfeld uint32_t mh_lba_count; /* 0x14 */ 341*98f0a994SHans Rosenfeld }; 342*98f0a994SHans Rosenfeld }; 343*98f0a994SHans Rosenfeld 344*98f0a994SHans Rosenfeld struct mfi_init_payload { 345*98f0a994SHans Rosenfeld uint64_t mi_queue_info_new_phys_addr; /* 0x18 */ 346*98f0a994SHans Rosenfeld uint64_t mi_queue_info_old_phys_addr; /* 0x20 */ 347*98f0a994SHans Rosenfeld uint64_t mi_driver_ver_phys_addr; /* 0x28 */ 348*98f0a994SHans Rosenfeld }; 349*98f0a994SHans Rosenfeld 350*98f0a994SHans Rosenfeld struct mfi_io_payload { 351*98f0a994SHans Rosenfeld uint64_t mio_sense_buf_phys_addr; /* 0x18 */ 352*98f0a994SHans Rosenfeld uint64_t mio_start_lba; /* 0x20 */ 353*98f0a994SHans Rosenfeld mfi_sgl_t mio_sgl; /* 0x28 */ 354*98f0a994SHans Rosenfeld }; 355*98f0a994SHans Rosenfeld 356*98f0a994SHans Rosenfeld struct mfi_pthru_payload { 357*98f0a994SHans Rosenfeld uint64_t mp_sense_buf_phys_addr; /* 0x18 */ 358*98f0a994SHans Rosenfeld uint8_t mp_cdb[16]; /* 0x20 */ 359*98f0a994SHans Rosenfeld mfi_sgl_t mp_sgl; /* 0x30 */ 360*98f0a994SHans Rosenfeld }; 361*98f0a994SHans Rosenfeld 362*98f0a994SHans Rosenfeld struct mfi_dcmd_payload { 363*98f0a994SHans Rosenfeld uint32_t md_opcode; /* 0x18 */ 364*98f0a994SHans Rosenfeld 365*98f0a994SHans Rosenfeld union { /* 0x1c */ 366*98f0a994SHans Rosenfeld uint8_t md_mbox_8[12]; 367*98f0a994SHans Rosenfeld uint16_t md_mbox_16[6]; 368*98f0a994SHans Rosenfeld uint32_t md_mbox_32[3]; 369*98f0a994SHans Rosenfeld }; 370*98f0a994SHans Rosenfeld 371*98f0a994SHans Rosenfeld mfi_sgl_t md_sgl; /* 0x28 */ 372*98f0a994SHans Rosenfeld }; 373*98f0a994SHans Rosenfeld 374*98f0a994SHans Rosenfeld struct mfi_abort_payload { 375*98f0a994SHans Rosenfeld uint32_t ma_abort_context; /* 0x18 */ 376*98f0a994SHans Rosenfeld uint32_t ma_pad_1; /* 0x1c */ 377*98f0a994SHans Rosenfeld uint64_t ma_abort_mfi_phys_addr; /* 0x20 */ 378*98f0a994SHans Rosenfeld }; 379*98f0a994SHans Rosenfeld 380*98f0a994SHans Rosenfeld struct mfi_frame { 381*98f0a994SHans Rosenfeld mfi_header_t mf_hdr; 382*98f0a994SHans Rosenfeld union { 383*98f0a994SHans Rosenfeld mfi_init_payload_t mf_init; 384*98f0a994SHans Rosenfeld mfi_io_payload_t mf_io; 385*98f0a994SHans Rosenfeld mfi_pthru_payload_t mf_pthru; 386*98f0a994SHans Rosenfeld mfi_dcmd_payload_t mf_dcmd; 387*98f0a994SHans Rosenfeld mfi_abort_payload_t mf_abort; 388*98f0a994SHans Rosenfeld uint8_t mf_raw[64 - sizeof (mfi_header_t)]; 389*98f0a994SHans Rosenfeld }; 390*98f0a994SHans Rosenfeld }; 391*98f0a994SHans Rosenfeld CTASSERT(offsetof(mfi_frame_t, mf_init) == 0x18); 392*98f0a994SHans Rosenfeld CTASSERT(sizeof (mfi_frame_t) == 64); 393*98f0a994SHans Rosenfeld 394*98f0a994SHans Rosenfeld 395*98f0a994SHans Rosenfeld /* 396*98f0a994SHans Rosenfeld * MFI controller properties 397*98f0a994SHans Rosenfeld */ 398*98f0a994SHans Rosenfeld struct mfi_ctrl_props { 399*98f0a994SHans Rosenfeld uint16_t cp_seq_num; 400*98f0a994SHans Rosenfeld uint16_t cp_pred_fail_poll_interval; 401*98f0a994SHans Rosenfeld uint16_t cp_intr_throttle_count; 402*98f0a994SHans Rosenfeld uint16_t cp_intr_throttle_timeouts; 403*98f0a994SHans Rosenfeld uint8_t cp_rebuild_rate; 404*98f0a994SHans Rosenfeld uint8_t cp_patrol_read_rate; 405*98f0a994SHans Rosenfeld uint8_t cp_bgi_rate; 406*98f0a994SHans Rosenfeld uint8_t cp_cc_rate; 407*98f0a994SHans Rosenfeld uint8_t cp_recon_rate; 408*98f0a994SHans Rosenfeld uint8_t cp_cache_flush_interval; 409*98f0a994SHans Rosenfeld uint8_t cp_spinup_drv_count; 410*98f0a994SHans Rosenfeld uint8_t cp_spinup_delay; 411*98f0a994SHans Rosenfeld uint8_t cp_cluster_enable; 412*98f0a994SHans Rosenfeld uint8_t cp_coercion_mode; 413*98f0a994SHans Rosenfeld uint8_t cp_alarm_enable; 414*98f0a994SHans Rosenfeld uint8_t cp_disable_auto_rebuild; 415*98f0a994SHans Rosenfeld uint8_t cp_disable_battery_warn; 416*98f0a994SHans Rosenfeld uint8_t cp_ecc_bucket_size; 417*98f0a994SHans Rosenfeld uint16_t cp_ecc_bucket_leak_rate; 418*98f0a994SHans Rosenfeld uint8_t cp_restore_hotspare_on_insertion; 419*98f0a994SHans Rosenfeld uint8_t cp_expose_encl_devices; 420*98f0a994SHans Rosenfeld uint8_t cp_maintain_pd_fail_history; 421*98f0a994SHans Rosenfeld uint8_t cp_disallow_host_request_reordering; 422*98f0a994SHans Rosenfeld uint8_t cp_abort_cc_on_error; 423*98f0a994SHans Rosenfeld uint8_t cp_load_balance_mode; 424*98f0a994SHans Rosenfeld uint8_t cp_disable_auto_detect_backplane; 425*98f0a994SHans Rosenfeld uint8_t cp_snap_vd_space; 426*98f0a994SHans Rosenfeld 427*98f0a994SHans Rosenfeld struct { 428*98f0a994SHans Rosenfeld uint32_t cp_copy_back_disabled:1; 429*98f0a994SHans Rosenfeld uint32_t cp_smarter_enabled:1; 430*98f0a994SHans Rosenfeld uint32_t cp_pr_correct_unconfigured_areas:1; 431*98f0a994SHans Rosenfeld uint32_t cp_use_FDE_only:1; 432*98f0a994SHans Rosenfeld uint32_t cp_disable_NCQ:1; 433*98f0a994SHans Rosenfeld uint32_t cp_SSD_smarter_enabled:1; 434*98f0a994SHans Rosenfeld uint32_t cp_SSD_patrol_read_enabled:1; 435*98f0a994SHans Rosenfeld uint32_t cp_enable_spin_down_unconfigured:1; 436*98f0a994SHans Rosenfeld uint32_t cp_auto_enhanced_import:1; 437*98f0a994SHans Rosenfeld uint32_t cp_enable_secret_key_control:1; 438*98f0a994SHans Rosenfeld uint32_t cp_disable_online_ctrl_reset:1; 439*98f0a994SHans Rosenfeld uint32_t cp_allow_boot_with_pinned_cache:1; 440*98f0a994SHans Rosenfeld uint32_t cp_disable_spin_down_HS:1; 441*98f0a994SHans Rosenfeld uint32_t cp_enable_JBOD:1; 442*98f0a994SHans Rosenfeld uint32_t cp_disable_cache_bypass:1; 443*98f0a994SHans Rosenfeld uint32_t cp_use_disk_activity_for_locate:1; 444*98f0a994SHans Rosenfeld uint32_t cp_enable_PI:1; 445*98f0a994SHans Rosenfeld uint32_t cp_prevent_PI_import:1; 446*98f0a994SHans Rosenfeld uint32_t cp_use_global_spares_for_emergency:1; 447*98f0a994SHans Rosenfeld uint32_t cp_use_unconf_good_for_emergency:1; 448*98f0a994SHans Rosenfeld uint32_t cp_use_emergency_spares_for_smarter:1; 449*98f0a994SHans Rosenfeld uint32_t cp_force_sgpio_for_quad_only:1; 450*98f0a994SHans Rosenfeld uint32_t cp_enable_config_auto_balance:1; 451*98f0a994SHans Rosenfeld uint32_t cp_enable_virtual_cache:1; 452*98f0a994SHans Rosenfeld uint32_t cp_enable_auto_lock_recovery:1; 453*98f0a994SHans Rosenfeld uint32_t cp_disable_immediate_io:1; 454*98f0a994SHans Rosenfeld uint32_t cp_disable_T10_rebuild_assist:1; 455*98f0a994SHans Rosenfeld uint32_t cp_ignore64_ld_restriction:1; 456*98f0a994SHans Rosenfeld uint32_t cp_enable_sw_zone:1; 457*98f0a994SHans Rosenfeld uint32_t cp_limit_max_rate_SATA_3G:1; 458*98f0a994SHans Rosenfeld uint32_t cp_reserved:2; 459*98f0a994SHans Rosenfeld }; 460*98f0a994SHans Rosenfeld uint8_t cp_auto_snap_vd_space; 461*98f0a994SHans Rosenfeld uint8_t cp_view_space; 462*98f0a994SHans Rosenfeld uint16_t cp_spin_down_time; 463*98f0a994SHans Rosenfeld uint8_t cp_reserved2[24]; 464*98f0a994SHans Rosenfeld }; 465*98f0a994SHans Rosenfeld CTASSERT(sizeof (mfi_ctrl_props_t) == 64); 466*98f0a994SHans Rosenfeld 467*98f0a994SHans Rosenfeld /* 468*98f0a994SHans Rosenfeld * MFI firmware image component 469*98f0a994SHans Rosenfeld */ 470*98f0a994SHans Rosenfeld struct mfi_image_comp { 471*98f0a994SHans Rosenfeld char ic_name[8]; 472*98f0a994SHans Rosenfeld char ic_version[32]; 473*98f0a994SHans Rosenfeld char ic_build_date[16]; 474*98f0a994SHans Rosenfeld char ic_build_time[16]; 475*98f0a994SHans Rosenfeld }; 476*98f0a994SHans Rosenfeld CTASSERT(sizeof (mfi_image_comp_t) == 72); 477*98f0a994SHans Rosenfeld 478*98f0a994SHans Rosenfeld /* 479*98f0a994SHans Rosenfeld * MFI controller information 480*98f0a994SHans Rosenfeld */ 481*98f0a994SHans Rosenfeld struct mfi_ctrl_info { 482*98f0a994SHans Rosenfeld /* PCI device information */ 483*98f0a994SHans Rosenfeld struct { 484*98f0a994SHans Rosenfeld uint16_t pci_vendor_id; 485*98f0a994SHans Rosenfeld uint16_t pci_device_id; 486*98f0a994SHans Rosenfeld uint16_t pci_sub_vendor_id; 487*98f0a994SHans Rosenfeld uint16_t pci_sub_device_id; 488*98f0a994SHans Rosenfeld uint8_t pci_reserved[24]; 489*98f0a994SHans Rosenfeld } ci_pci; 490*98f0a994SHans Rosenfeld 491*98f0a994SHans Rosenfeld /* Host interface information */ 492*98f0a994SHans Rosenfeld struct { 493*98f0a994SHans Rosenfeld uint8_t hi_PCIX:1; 494*98f0a994SHans Rosenfeld uint8_t hi_PCIE:1; 495*98f0a994SHans Rosenfeld uint8_t hi_iSCSI:1; 496*98f0a994SHans Rosenfeld uint8_t hi_SAS_3G:1; 497*98f0a994SHans Rosenfeld uint8_t hi_reserved_0:4; 498*98f0a994SHans Rosenfeld uint8_t hi_reserved_1[6]; 499*98f0a994SHans Rosenfeld uint8_t hi_port_count; 500*98f0a994SHans Rosenfeld uint64_t hi_port_addr[8]; 501*98f0a994SHans Rosenfeld } ci_host_interface; 502*98f0a994SHans Rosenfeld 503*98f0a994SHans Rosenfeld /* Target interface information */ 504*98f0a994SHans Rosenfeld struct { 505*98f0a994SHans Rosenfeld uint8_t di_SPI:1; 506*98f0a994SHans Rosenfeld uint8_t di_SAS_3G:1; 507*98f0a994SHans Rosenfeld uint8_t di_SATA_1_5G:1; 508*98f0a994SHans Rosenfeld uint8_t di_SATA_3G:1; 509*98f0a994SHans Rosenfeld uint8_t di_reserved_0:4; 510*98f0a994SHans Rosenfeld uint8_t di_reserved_1[6]; 511*98f0a994SHans Rosenfeld uint8_t di_port_count; 512*98f0a994SHans Rosenfeld uint64_t di_port_addr[8]; 513*98f0a994SHans Rosenfeld } ci_device_interface; 514*98f0a994SHans Rosenfeld 515*98f0a994SHans Rosenfeld uint32_t ci_image_check_word; 516*98f0a994SHans Rosenfeld 517*98f0a994SHans Rosenfeld uint32_t ci_image_component_count; 518*98f0a994SHans Rosenfeld mfi_image_comp_t ci_image_component[8]; 519*98f0a994SHans Rosenfeld 520*98f0a994SHans Rosenfeld uint32_t ci_pending_image_component_count; 521*98f0a994SHans Rosenfeld mfi_image_comp_t ci_pending_image_component[8]; 522*98f0a994SHans Rosenfeld 523*98f0a994SHans Rosenfeld uint8_t ci_max_arms; 524*98f0a994SHans Rosenfeld uint8_t ci_max_spans; 525*98f0a994SHans Rosenfeld uint8_t ci_max_arrays; 526*98f0a994SHans Rosenfeld uint8_t ci_max_lds; 527*98f0a994SHans Rosenfeld char ci_product_name[80]; 528*98f0a994SHans Rosenfeld char ci_serial_no[32]; 529*98f0a994SHans Rosenfeld 530*98f0a994SHans Rosenfeld /* 531*98f0a994SHans Rosenfeld * Hardware features 532*98f0a994SHans Rosenfeld */ 533*98f0a994SHans Rosenfeld struct { 534*98f0a994SHans Rosenfeld uint32_t hw_bbu:1; 535*98f0a994SHans Rosenfeld uint32_t hw_alarm:1; 536*98f0a994SHans Rosenfeld uint32_t hw_nvram:1; 537*98f0a994SHans Rosenfeld uint32_t hw_uart:1; 538*98f0a994SHans Rosenfeld uint32_t hw_reserved:28; 539*98f0a994SHans Rosenfeld } ci_hw_present; 540*98f0a994SHans Rosenfeld 541*98f0a994SHans Rosenfeld uint32_t ci_current_fw_time; 542*98f0a994SHans Rosenfeld 543*98f0a994SHans Rosenfeld /* Maximum data transfer sizes */ 544*98f0a994SHans Rosenfeld uint16_t ci_max_concurrent_cmds; 545*98f0a994SHans Rosenfeld uint16_t ci_max_sge_count; 546*98f0a994SHans Rosenfeld uint32_t ci_max_request_size; 547*98f0a994SHans Rosenfeld 548*98f0a994SHans Rosenfeld /* Logical and physical device counts */ 549*98f0a994SHans Rosenfeld uint16_t ci_ld_present_count; 550*98f0a994SHans Rosenfeld uint16_t ci_ld_degraded_count; 551*98f0a994SHans Rosenfeld uint16_t ci_ld_offline_count; 552*98f0a994SHans Rosenfeld 553*98f0a994SHans Rosenfeld uint16_t ci_pd_present_count; 554*98f0a994SHans Rosenfeld uint16_t ci_pd_disk_present_count; 555*98f0a994SHans Rosenfeld uint16_t ci_pd_disk_pred_failure_count; 556*98f0a994SHans Rosenfeld uint16_t ci_pd_disk_failed_count; 557*98f0a994SHans Rosenfeld 558*98f0a994SHans Rosenfeld /* Memory size information */ 559*98f0a994SHans Rosenfeld uint16_t ci_nvram_size; 560*98f0a994SHans Rosenfeld uint16_t ci_memory_size; 561*98f0a994SHans Rosenfeld uint16_t ci_flash_size; 562*98f0a994SHans Rosenfeld 563*98f0a994SHans Rosenfeld /* Error counters */ 564*98f0a994SHans Rosenfeld uint16_t ci_mem_correctable_error_count; 565*98f0a994SHans Rosenfeld uint16_t ci_mem_uncorrectable_error_count; 566*98f0a994SHans Rosenfeld 567*98f0a994SHans Rosenfeld /* Cluster information */ 568*98f0a994SHans Rosenfeld uint8_t ci_cluster_permitted; 569*98f0a994SHans Rosenfeld uint8_t ci_cluster_active; 570*98f0a994SHans Rosenfeld 571*98f0a994SHans Rosenfeld /* Additional max data transfer sizes */ 572*98f0a994SHans Rosenfeld uint16_t ci_max_stripes_per_io; 573*98f0a994SHans Rosenfeld 574*98f0a994SHans Rosenfeld /* Controller capabilities structures */ 575*98f0a994SHans Rosenfeld struct { 576*98f0a994SHans Rosenfeld uint32_t rl_raid_level_0:1; 577*98f0a994SHans Rosenfeld uint32_t rl_raid_level_1:1; 578*98f0a994SHans Rosenfeld uint32_t rl_raid_level_5:1; 579*98f0a994SHans Rosenfeld uint32_t rl_raid_level_1E:1; 580*98f0a994SHans Rosenfeld uint32_t rl_raid_level_6:1; 581*98f0a994SHans Rosenfeld uint32_t rl_reserved:27; 582*98f0a994SHans Rosenfeld } ci_raid_levels; 583*98f0a994SHans Rosenfeld 584*98f0a994SHans Rosenfeld struct { 585*98f0a994SHans Rosenfeld uint32_t ao_rbld_rate:1; 586*98f0a994SHans Rosenfeld uint32_t ao_cc_rate:1; 587*98f0a994SHans Rosenfeld uint32_t ao_bgi_rate:1; 588*98f0a994SHans Rosenfeld uint32_t ao_recon_rate:1; 589*98f0a994SHans Rosenfeld uint32_t ao_patrol_rate:1; 590*98f0a994SHans Rosenfeld uint32_t ao_alarm_control:1; 591*98f0a994SHans Rosenfeld uint32_t ao_cluster_supported:1; 592*98f0a994SHans Rosenfeld uint32_t ao_bbu:1; 593*98f0a994SHans Rosenfeld uint32_t ao_spanning_allowed:1; 594*98f0a994SHans Rosenfeld uint32_t ao_dedicated_hotspares:1; 595*98f0a994SHans Rosenfeld uint32_t ao_revertible_hotspares:1; 596*98f0a994SHans Rosenfeld uint32_t ao_foreign_config_import:1; 597*98f0a994SHans Rosenfeld uint32_t ao_self_diagnostic:1; 598*98f0a994SHans Rosenfeld uint32_t ao_mixed_redundancy_arr:1; 599*98f0a994SHans Rosenfeld uint32_t ao_global_hot_spares:1; 600*98f0a994SHans Rosenfeld uint32_t ao_reserved:17; 601*98f0a994SHans Rosenfeld } ci_adapter_opts; 602*98f0a994SHans Rosenfeld 603*98f0a994SHans Rosenfeld struct { 604*98f0a994SHans Rosenfeld uint32_t ld_read_policy:1; 605*98f0a994SHans Rosenfeld uint32_t ld_write_policy:1; 606*98f0a994SHans Rosenfeld uint32_t ld_io_policy:1; 607*98f0a994SHans Rosenfeld uint32_t ld_access_policy:1; 608*98f0a994SHans Rosenfeld uint32_t ld_disk_cache_policy:1; 609*98f0a994SHans Rosenfeld uint32_t ld_reserved:27; 610*98f0a994SHans Rosenfeld } ci_ld_opts; 611*98f0a994SHans Rosenfeld 612*98f0a994SHans Rosenfeld struct { 613*98f0a994SHans Rosenfeld uint8_t raid_stripe_sz_min; 614*98f0a994SHans Rosenfeld uint8_t raid_stripe_sz_max; 615*98f0a994SHans Rosenfeld uint8_t raid_reserved[2]; 616*98f0a994SHans Rosenfeld } ci_raid_opts; 617*98f0a994SHans Rosenfeld 618*98f0a994SHans Rosenfeld struct { 619*98f0a994SHans Rosenfeld uint32_t pd_force_online:1; 620*98f0a994SHans Rosenfeld uint32_t pd_force_offline:1; 621*98f0a994SHans Rosenfeld uint32_t pd_force_rebuild:1; 622*98f0a994SHans Rosenfeld uint32_t pd_reserved:29; 623*98f0a994SHans Rosenfeld } ci_pd_opts; 624*98f0a994SHans Rosenfeld 625*98f0a994SHans Rosenfeld struct { 626*98f0a994SHans Rosenfeld uint32_t pd_ctrl_supports_sas:1; 627*98f0a994SHans Rosenfeld uint32_t pd_ctrl_supports_sata:1; 628*98f0a994SHans Rosenfeld uint32_t pd_allow_mix_in_encl:1; 629*98f0a994SHans Rosenfeld uint32_t pd_allow_mix_in_ld:1; 630*98f0a994SHans Rosenfeld uint32_t pd_allow_sata_in_cluster:1; 631*98f0a994SHans Rosenfeld uint32_t pd_reserved:27; 632*98f0a994SHans Rosenfeld } ci_pd_mix_support; 633*98f0a994SHans Rosenfeld 634*98f0a994SHans Rosenfeld /* ECC single-bit error bucket information */ 635*98f0a994SHans Rosenfeld uint8_t ci_ecc_bucket_count; 636*98f0a994SHans Rosenfeld uint8_t ci_reserved_2[11]; 637*98f0a994SHans Rosenfeld 638*98f0a994SHans Rosenfeld /* Controller properties */ 639*98f0a994SHans Rosenfeld mfi_ctrl_props_t ci_prop; 640*98f0a994SHans Rosenfeld 641*98f0a994SHans Rosenfeld char ci_package_version[0x60]; 642*98f0a994SHans Rosenfeld 643*98f0a994SHans Rosenfeld uint64_t ci_device_interface_port_addr2[8]; 644*98f0a994SHans Rosenfeld uint8_t ci_reserved3[128]; 645*98f0a994SHans Rosenfeld 646*98f0a994SHans Rosenfeld struct { 647*98f0a994SHans Rosenfeld uint16_t pd_min_pd_raid_level_0:4; 648*98f0a994SHans Rosenfeld uint16_t pd_max_pd_raid_level_0:12; 649*98f0a994SHans Rosenfeld 650*98f0a994SHans Rosenfeld uint16_t pd_min_pd_raid_level_1:4; 651*98f0a994SHans Rosenfeld uint16_t pd_max_pd_raid_level_1:12; 652*98f0a994SHans Rosenfeld 653*98f0a994SHans Rosenfeld uint16_t pd_min_pd_raid_level_5:4; 654*98f0a994SHans Rosenfeld uint16_t pd_max_pd_raid_level_5:12; 655*98f0a994SHans Rosenfeld 656*98f0a994SHans Rosenfeld uint16_t pd_min_pd_raid_level_1E:4; 657*98f0a994SHans Rosenfeld uint16_t pd_max_pd_raid_level_1E:12; 658*98f0a994SHans Rosenfeld 659*98f0a994SHans Rosenfeld uint16_t pd_min_pd_raid_level_6:4; 660*98f0a994SHans Rosenfeld uint16_t pd_max_pd_raid_level_6:12; 661*98f0a994SHans Rosenfeld 662*98f0a994SHans Rosenfeld uint16_t pd_min_pd_raid_level_10:4; 663*98f0a994SHans Rosenfeld uint16_t pd_max_pd_raid_level_10:12; 664*98f0a994SHans Rosenfeld 665*98f0a994SHans Rosenfeld uint16_t pd_min_pd_raid_level_50:4; 666*98f0a994SHans Rosenfeld uint16_t pd_max_pd_raid_level_50:12; 667*98f0a994SHans Rosenfeld 668*98f0a994SHans Rosenfeld uint16_t pd_min_pd_raid_level_60:4; 669*98f0a994SHans Rosenfeld uint16_t pd_max_pd_raid_level_60:12; 670*98f0a994SHans Rosenfeld 671*98f0a994SHans Rosenfeld uint16_t pd_min_pd_raid_level_1E_RLQ0:4; 672*98f0a994SHans Rosenfeld uint16_t pd_max_pd_raid_level_1E_RLQ0:12; 673*98f0a994SHans Rosenfeld 674*98f0a994SHans Rosenfeld uint16_t pd_min_pd_raid_level_1E0_RLQ0:4; 675*98f0a994SHans Rosenfeld uint16_t pd_max_pd_raid_level_1E0_RLQ0:12; 676*98f0a994SHans Rosenfeld 677*98f0a994SHans Rosenfeld uint16_t pd_reserved[6]; 678*98f0a994SHans Rosenfeld } ci_pds_for_raid_levels; 679*98f0a994SHans Rosenfeld 680*98f0a994SHans Rosenfeld uint16_t ci_max_pds; /* 0x780 */ 681*98f0a994SHans Rosenfeld uint16_t ci_max_ded_HSPs; /* 0x782 */ 682*98f0a994SHans Rosenfeld uint16_t ci_max_global_HSPs; /* 0x784 */ 683*98f0a994SHans Rosenfeld uint16_t ci_ddf_size; /* 0x786 */ 684*98f0a994SHans Rosenfeld uint8_t ci_max_lds_per_array; /* 0x788 */ 685*98f0a994SHans Rosenfeld uint8_t ci_partitions_in_DDF; /* 0x789 */ 686*98f0a994SHans Rosenfeld uint8_t ci_lock_key_binding; /* 0x78a */ 687*98f0a994SHans Rosenfeld uint8_t ci_max_PITs_per_ld; /* 0x78b */ 688*98f0a994SHans Rosenfeld uint8_t ci_max_views_per_ld; /* 0x78c */ 689*98f0a994SHans Rosenfeld uint8_t ci_max_target_id; /* 0x78d */ 690*98f0a994SHans Rosenfeld uint16_t ci_max_bvl_vd_size; /* 0x78e */ 691*98f0a994SHans Rosenfeld 692*98f0a994SHans Rosenfeld uint16_t ci_max_configurable_SSC_size; /* 0x790 */ 693*98f0a994SHans Rosenfeld uint16_t ci_current_SSC_size; /* 0x792 */ 694*98f0a994SHans Rosenfeld 695*98f0a994SHans Rosenfeld char ci_expander_fw_version[12]; /* 0x794 */ 696*98f0a994SHans Rosenfeld 697*98f0a994SHans Rosenfeld uint16_t ci_PFK_trial_time_remaining; /* 0x7A0 */ 698*98f0a994SHans Rosenfeld 699*98f0a994SHans Rosenfeld uint16_t ci_cache_memory_size; /* 0x7A2 */ 700*98f0a994SHans Rosenfeld 701*98f0a994SHans Rosenfeld struct { /* 0x7A4 */ 702*98f0a994SHans Rosenfeld uint32_t ao2_support_PI_controller:1; 703*98f0a994SHans Rosenfeld uint32_t ao2_support_ld_PI_type1:1; 704*98f0a994SHans Rosenfeld uint32_t ao2_support_ld_PI_type2:1; 705*98f0a994SHans Rosenfeld uint32_t ao2_support_ld_PI_type3:1; 706*98f0a994SHans Rosenfeld uint32_t ao2_support_ld_BBM_info:1; 707*98f0a994SHans Rosenfeld uint32_t ao2_support_shield_state:1; 708*98f0a994SHans Rosenfeld uint32_t ao2_block_SSD_write_cache_change:1; 709*98f0a994SHans Rosenfeld uint32_t ao2_support_suspend_resume_b_Gops:1; 710*98f0a994SHans Rosenfeld uint32_t ao2_support_emergency_spares:1; 711*98f0a994SHans Rosenfeld uint32_t ao2_support_set_link_speed:1; 712*98f0a994SHans Rosenfeld uint32_t ao2_support_boot_time_PFK_change:1; 713*98f0a994SHans Rosenfeld uint32_t ao2_support_JBOD:1; 714*98f0a994SHans Rosenfeld uint32_t ao2_disable_online_PFK_change:1; 715*98f0a994SHans Rosenfeld uint32_t ao2_support_perf_tuning:1; 716*98f0a994SHans Rosenfeld uint32_t ao2_support_SSD_patrol_read:1; 717*98f0a994SHans Rosenfeld uint32_t ao2_real_time_scheduler:1; 718*98f0a994SHans Rosenfeld 719*98f0a994SHans Rosenfeld uint32_t ao2_support_reset_now:1; 720*98f0a994SHans Rosenfeld uint32_t ao2_support_emulated_drives:1; 721*98f0a994SHans Rosenfeld uint32_t ao2_headless_mode:1; 722*98f0a994SHans Rosenfeld uint32_t ao2_dedicated_hot_spares_limited:1; 723*98f0a994SHans Rosenfeld 724*98f0a994SHans Rosenfeld uint32_t ao2_support_uneven_spans:1; 725*98f0a994SHans Rosenfeld uint32_t ao2_reserved:11; 726*98f0a994SHans Rosenfeld } ci_adapter_opts2; 727*98f0a994SHans Rosenfeld 728*98f0a994SHans Rosenfeld uint8_t ci_driver_version[32]; /* 0x7A8 */ 729*98f0a994SHans Rosenfeld uint8_t ci_max_DAP_d_count_spinup60; /* 0x7C8 */ 730*98f0a994SHans Rosenfeld uint8_t ci_temperature_ROC; /* 0x7C9 */ 731*98f0a994SHans Rosenfeld uint8_t ci_temperature_ctrl; /* 0x7CA */ 732*98f0a994SHans Rosenfeld uint8_t ci_reserved4; /* 0x7CB */ 733*98f0a994SHans Rosenfeld uint16_t ci_max_configurable_pds; /* 0x7CC */ 734*98f0a994SHans Rosenfeld 735*98f0a994SHans Rosenfeld uint8_t ci_reserved5[2]; /* 0x7CD reserved */ 736*98f0a994SHans Rosenfeld 737*98f0a994SHans Rosenfeld struct { 738*98f0a994SHans Rosenfeld uint32_t cl_peer_is_present:1; 739*98f0a994SHans Rosenfeld uint32_t cl_peer_is_incompatible:1; 740*98f0a994SHans Rosenfeld 741*98f0a994SHans Rosenfeld uint32_t cl_hw_incompatible:1; 742*98f0a994SHans Rosenfeld uint32_t cl_fw_version_mismatch:1; 743*98f0a994SHans Rosenfeld uint32_t cl_ctrl_prop_incompatible:1; 744*98f0a994SHans Rosenfeld uint32_t cl_premium_feature_mismatch:1; 745*98f0a994SHans Rosenfeld uint32_t cl_reserved:26; 746*98f0a994SHans Rosenfeld } ci_cluster; 747*98f0a994SHans Rosenfeld 748*98f0a994SHans Rosenfeld char ci_cluster_id[16]; /* 0x7D4 */ 749*98f0a994SHans Rosenfeld 750*98f0a994SHans Rosenfeld char ci_reserved6[4]; /* 0x7E4 RESERVED FOR IOV */ 751*98f0a994SHans Rosenfeld 752*98f0a994SHans Rosenfeld struct { /* 0x7E8 */ 753*98f0a994SHans Rosenfeld uint32_t ao3_support_personality_change:2; 754*98f0a994SHans Rosenfeld uint32_t ao3_support_thermal_poll_interval:1; 755*98f0a994SHans Rosenfeld uint32_t ao3_support_disable_immediate_IO:1; 756*98f0a994SHans Rosenfeld uint32_t ao3_support_T10_rebuild_assist:1; 757*98f0a994SHans Rosenfeld uint32_t ao3_support_max_ext_lds:1; 758*98f0a994SHans Rosenfeld uint32_t ao3_support_crash_dump:1; 759*98f0a994SHans Rosenfeld uint32_t ao3_support_sw_zone:1; 760*98f0a994SHans Rosenfeld uint32_t ao3_support_debug_queue:1; 761*98f0a994SHans Rosenfeld uint32_t ao3_support_NV_cache_erase:1; 762*98f0a994SHans Rosenfeld uint32_t ao3_support_force_to_512e:1; 763*98f0a994SHans Rosenfeld uint32_t ao3_support_HOQ_rebuild:1; 764*98f0a994SHans Rosenfeld uint32_t ao3_support_allowed_opsfor_drv_removal:1; 765*98f0a994SHans Rosenfeld uint32_t ao3_support_drv_activity_LED_setting:1; 766*98f0a994SHans Rosenfeld uint32_t ao3_support_NVDRAM:1; 767*98f0a994SHans Rosenfeld uint32_t ao3_support_force_flash:1; 768*98f0a994SHans Rosenfeld uint32_t ao3_support_disable_SES_monitoring:1; 769*98f0a994SHans Rosenfeld uint32_t ao3_support_cache_bypass_modes:1; 770*98f0a994SHans Rosenfeld uint32_t ao3_support_securityon_JBOD:1; 771*98f0a994SHans Rosenfeld uint32_t ao3_discard_cache_during_ld_delete:1; 772*98f0a994SHans Rosenfeld uint32_t ao3_support_TTY_log_compression:1; 773*98f0a994SHans Rosenfeld uint32_t ao3_support_CPLD_update:1; 774*98f0a994SHans Rosenfeld uint32_t ao3_support_disk_cache_setting_for_sys_pds:1; 775*98f0a994SHans Rosenfeld uint32_t ao3_support_extended_SSC_size:1; 776*98f0a994SHans Rosenfeld uint32_t ao3_use_seq_num_jbod_FP:1; 777*98f0a994SHans Rosenfeld uint32_t ao3_reserved:7; 778*98f0a994SHans Rosenfeld } ci_adapter_opts3; 779*98f0a994SHans Rosenfeld 780*98f0a994SHans Rosenfeld uint8_t ci_pad_cpld[16]; 781*98f0a994SHans Rosenfeld 782*98f0a994SHans Rosenfeld struct { 783*98f0a994SHans Rosenfeld uint16_t ao4_ctrl_info_ext_supported:1; 784*98f0a994SHans Rosenfeld uint16_t ao4_support_ibutton_less:1; 785*98f0a994SHans Rosenfeld uint16_t ao4_supported_enc_algo:1; 786*98f0a994SHans Rosenfeld uint16_t ao4_support_encrypted_mfc:1; 787*98f0a994SHans Rosenfeld uint16_t ao4_image_upload_supported:1; 788*98f0a994SHans Rosenfeld uint16_t ao4_support_SES_ctrl_in_multipath_cfg:1; 789*98f0a994SHans Rosenfeld uint16_t ao4_support_pd_map_target_id:1; 790*98f0a994SHans Rosenfeld uint16_t ao4_fw_swaps_bbu_vpd_info:1; 791*98f0a994SHans Rosenfeld uint16_t ao4_reserved:8; 792*98f0a994SHans Rosenfeld } ci_adapter_opts4; 793*98f0a994SHans Rosenfeld 794*98f0a994SHans Rosenfeld uint8_t ci_pad[0x800 - 0x7FE]; /* 0x7FE */ 795*98f0a994SHans Rosenfeld }; 796*98f0a994SHans Rosenfeld CTASSERT(sizeof (mfi_ctrl_info_t) == 0x800); 797*98f0a994SHans Rosenfeld 798*98f0a994SHans Rosenfeld /* 799*98f0a994SHans Rosenfeld * PR (patrol read) properties & status 800*98f0a994SHans Rosenfeld */ 801*98f0a994SHans Rosenfeld struct mfi_pr_properties { 802*98f0a994SHans Rosenfeld uint8_t pp_op_mode; 803*98f0a994SHans Rosenfeld uint8_t pp_max_pd; 804*98f0a994SHans Rosenfeld uint8_t pp_rsvd; 805*98f0a994SHans Rosenfeld uint8_t pp_exclude_ld_cnt; 806*98f0a994SHans Rosenfeld uint16_t pp_excluded_ld[MFI_MAX_LOGICAL_DRIVES]; 807*98f0a994SHans Rosenfeld uint8_t pp_cur_pd_map[MFI_MAX_PHYSICAL_DRIVES / 8]; 808*98f0a994SHans Rosenfeld uint8_t pp_last_pd_map[MFI_MAX_PHYSICAL_DRIVES / 8]; 809*98f0a994SHans Rosenfeld uint32_t pp_next_exec; 810*98f0a994SHans Rosenfeld uint32_t pp_exec_freq; 811*98f0a994SHans Rosenfeld uint32_t pp_clear_freq; 812*98f0a994SHans Rosenfeld }; 813*98f0a994SHans Rosenfeld 814*98f0a994SHans Rosenfeld struct mfi_pr_status { 815*98f0a994SHans Rosenfeld uint32_t ps_num_iteration; 816*98f0a994SHans Rosenfeld uint8_t ps_state; 817*98f0a994SHans Rosenfeld uint8_t ps_num_pd_done; 818*98f0a994SHans Rosenfeld uint8_t ps_rsvd[10]; 819*98f0a994SHans Rosenfeld }; 820*98f0a994SHans Rosenfeld 821*98f0a994SHans Rosenfeld struct mfi_progress { 822*98f0a994SHans Rosenfeld uint16_t mp_progress; 823*98f0a994SHans Rosenfeld uint16_t mp_elapsed; 824*98f0a994SHans Rosenfeld }; 825*98f0a994SHans Rosenfeld CTASSERT(sizeof (mfi_progress_t) == 4); 826*98f0a994SHans Rosenfeld 827*98f0a994SHans Rosenfeld #pragma pack(0) 828*98f0a994SHans Rosenfeld 829*98f0a994SHans Rosenfeld #ifdef __cplusplus 830*98f0a994SHans Rosenfeld } 831*98f0a994SHans Rosenfeld #endif 832*98f0a994SHans Rosenfeld 833*98f0a994SHans Rosenfeld #endif /* _MFI_H */ 834