1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved. 24 */ 25 26 /* 27 * Copyright (c) 2000 to 2010, LSI Corporation. 28 * All rights reserved. 29 * 30 * Redistribution and use in source and binary forms of all code within 31 * this file that is exclusively owned by LSI, with or without 32 * modification, is permitted provided that, in addition to the CDDL 1.0 33 * License requirements, the following conditions are met: 34 * 35 * Neither the name of the author nor the names of its contributors may be 36 * used to endorse or promote products derived from this software without 37 * specific prior written permission. 38 * 39 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 40 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 41 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 42 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 43 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 44 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 45 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 46 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 47 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 48 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 49 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 50 * DAMAGE. 51 */ 52 53 #ifndef _SYS_SCSI_ADAPTERS_MPTVAR_H 54 #define _SYS_SCSI_ADAPTERS_MPTVAR_H 55 56 #include <sys/byteorder.h> 57 #include <sys/isa_defs.h> 58 #include <sys/sunmdi.h> 59 #include <sys/mdi_impldefs.h> 60 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h> 61 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h> 62 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h> 63 64 #ifdef __cplusplus 65 extern "C" { 66 #endif 67 68 /* 69 * Compile options 70 */ 71 #ifdef DEBUG 72 #define MPTSAS_DEBUG /* turn on debugging code */ 73 #endif /* DEBUG */ 74 75 #define MPTSAS_INITIAL_SOFT_SPACE 4 76 77 #define MAX_MPI_PORTS 16 78 79 /* 80 * Note below macro definition and data type definition 81 * are used for phy mask handling, it should be changed 82 * simultaneously. 83 */ 84 #define MPTSAS_MAX_PHYS 16 85 typedef uint16_t mptsas_phymask_t; 86 87 #define MPTSAS_INVALID_DEVHDL 0xffff 88 #define MPTSAS_SATA_GUID "sata-guid" 89 90 /* 91 * MPT HW defines 92 */ 93 #define MPTSAS_MAX_DISKS_IN_CONFIG 14 94 #define MPTSAS_MAX_DISKS_IN_VOL 10 95 #define MPTSAS_MAX_HOTSPARES 2 96 #define MPTSAS_MAX_RAIDVOLS 2 97 #define MPTSAS_MAX_RAIDCONFIGS 5 98 99 /* 100 * 64-bit SAS WWN is displayed as 16 characters as HEX characters, 101 * plus two means the prefix 'w' and end of the string '\0'. 102 */ 103 #define MPTSAS_WWN_STRLEN (16 + 2) 104 #define MPTSAS_MAX_GUID_LEN 64 105 106 /* 107 * DMA routine flags 108 */ 109 #define MPTSAS_DMA_HANDLE_ALLOCD 0x2 110 #define MPTSAS_DMA_MEMORY_ALLOCD 0x4 111 #define MPTSAS_DMA_HANDLE_BOUND 0x8 112 113 /* 114 * If the HBA supports DMA or bus-mastering, you may have your own 115 * scatter-gather list for physically non-contiguous memory in one 116 * I/O operation; if so, there's probably a size for that list. 117 * It must be placed in the ddi_dma_lim_t structure, so that the system 118 * DMA-support routines can use it to break up the I/O request, so we 119 * define it here. 120 */ 121 #if defined(__sparc) 122 #define MPTSAS_MAX_DMA_SEGS 1 123 #define MPTSAS_MAX_CMD_SEGS 1 124 #else 125 #define MPTSAS_MAX_DMA_SEGS 256 126 #define MPTSAS_MAX_CMD_SEGS 257 127 #endif 128 #define MPTSAS_MAX_FRAME_SGES(mpt) \ 129 (((mpt->m_req_frame_size - (sizeof (MPI2_SCSI_IO_REQUEST))) / 8) + 1) 130 131 /* 132 * Caculating how many 64-bit DMA simple elements can be stored in the first 133 * frame. Note that msg_scsi_io_request contains 2 double-words (8 bytes) for 134 * element storage. And 64-bit dma element is 3 double-words (12 bytes) in 135 * size. 136 */ 137 #define MPTSAS_MAX_FRAME_SGES64(mpt) \ 138 ((mpt->m_req_frame_size - \ 139 (sizeof (MPI2_SCSI_IO_REQUEST)) + sizeof (MPI2_SGE_IO_UNION)) / 12) 140 141 /* 142 * Scatter-gather list structure defined by HBA hardware 143 */ 144 typedef struct NcrTableIndirect { /* Table Indirect entries */ 145 uint32_t count; /* 24 bit count */ 146 union { 147 uint32_t address32; /* 32 bit address */ 148 struct { 149 uint32_t Low; 150 uint32_t High; 151 } address64; /* 64 bit address */ 152 } addr; 153 } mptti_t; 154 155 /* 156 * preferred pkt_private length in 64-bit quantities 157 */ 158 #ifdef _LP64 159 #define PKT_PRIV_SIZE 2 160 #define PKT_PRIV_LEN 16 /* in bytes */ 161 #else /* _ILP32 */ 162 #define PKT_PRIV_SIZE 1 163 #define PKT_PRIV_LEN 8 /* in bytes */ 164 #endif 165 166 #define PKT2CMD(pkt) ((struct mptsas_cmd *)((pkt)->pkt_ha_private)) 167 #define CMD2PKT(cmdp) ((struct scsi_pkt *)((cmdp)->cmd_pkt)) 168 #define EXTCMDS_STATUS_SIZE (sizeof (struct scsi_arq_status)) 169 170 /* 171 * get offset of item in structure 172 */ 173 #define MPTSAS_GET_ITEM_OFF(type, member) ((size_t)(&((type *)0)->member)) 174 175 /* 176 * WWID provided by LSI firmware is generated by firmware but the WWID is not 177 * IEEE NAA standard format, OBP has no chance to distinguish format of unit 178 * address. According LSI's confirmation, the top nibble of RAID WWID is 179 * meanless, so the consensus between Solaris and OBP is to replace top nibble 180 * of WWID provided by LSI to "3" always to hint OBP that this is a RAID WWID 181 * format unit address. 182 */ 183 #define MPTSAS_RAID_WWID(wwid) \ 184 ((wwid & 0x0FFFFFFFFFFFFFFF) | 0x3000000000000000) 185 186 typedef struct mptsas_target { 187 uint64_t m_sas_wwn; /* hash key1 */ 188 mptsas_phymask_t m_phymask; /* hash key2 */ 189 /* 190 * m_dr_flag is a flag for DR, make sure the member 191 * take the place of dr_flag of mptsas_hash_data. 192 */ 193 uint8_t m_dr_flag; /* dr_flag */ 194 uint16_t m_devhdl; 195 uint32_t m_deviceinfo; 196 uint8_t m_phynum; 197 uint32_t m_dups; 198 int32_t m_timeout; 199 int32_t m_timebase; 200 int32_t m_t_throttle; 201 int32_t m_t_ncmds; 202 int32_t m_reset_delay; 203 int32_t m_t_nwait; 204 205 uint16_t m_qfull_retry_interval; 206 uint8_t m_qfull_retries; 207 uint16_t m_enclosure; 208 uint16_t m_slot_num; 209 uint32_t m_tgt_unconfigured; 210 211 /* 212 * For the common case, the elements in this structure are 213 * protected by the per hba instance mutex. In order to make 214 * the key code path in ISR lockless, a separate mutex is 215 * introdeced to protect those shown in ISR. 216 */ 217 kmutex_t m_tgt_intr_mutex; 218 219 } mptsas_target_t; 220 221 typedef struct mptsas_smp { 222 uint64_t m_sasaddr; /* hash key1 */ 223 mptsas_phymask_t m_phymask; /* hash key2 */ 224 uint8_t reserved1; 225 uint16_t m_devhdl; 226 uint32_t m_deviceinfo; 227 uint16_t m_pdevhdl; 228 uint32_t m_pdevinfo; 229 } mptsas_smp_t; 230 231 typedef struct mptsas_hash_data { 232 uint64_t key1; 233 mptsas_phymask_t key2; 234 uint8_t dr_flag; 235 uint16_t devhdl; 236 uint32_t device_info; 237 } mptsas_hash_data_t; 238 239 typedef struct mptsas_cache_frames { 240 ddi_dma_handle_t m_dma_hdl; 241 ddi_acc_handle_t m_acc_hdl; 242 caddr_t m_frames_addr; 243 uint32_t m_phys_addr; 244 } mptsas_cache_frames_t; 245 246 typedef struct mptsas_cmd { 247 uint_t cmd_flags; /* flags from scsi_init_pkt */ 248 ddi_dma_handle_t cmd_dmahandle; /* dma handle */ 249 ddi_dma_cookie_t cmd_cookie; 250 uint_t cmd_cookiec; 251 uint_t cmd_winindex; 252 uint_t cmd_nwin; 253 uint_t cmd_cur_cookie; 254 off_t cmd_dma_offset; 255 size_t cmd_dma_len; 256 uint32_t cmd_totaldmacount; 257 258 ddi_dma_handle_t cmd_arqhandle; /* dma arq handle */ 259 ddi_dma_cookie_t cmd_arqcookie; 260 struct buf *cmd_arq_buf; 261 ddi_dma_handle_t cmd_ext_arqhandle; /* dma extern arq handle */ 262 ddi_dma_cookie_t cmd_ext_arqcookie; 263 struct buf *cmd_ext_arq_buf; 264 265 int cmd_pkt_flags; 266 267 /* timer for command in active slot */ 268 int cmd_active_timeout; 269 270 struct scsi_pkt *cmd_pkt; 271 struct scsi_arq_status cmd_scb; 272 uchar_t cmd_cdblen; /* length of cdb */ 273 uchar_t cmd_rqslen; /* len of requested rqsense */ 274 uchar_t cmd_privlen; 275 uint_t cmd_scblen; 276 uint32_t cmd_dmacount; 277 uint64_t cmd_dma_addr; 278 uchar_t cmd_age; 279 ushort_t cmd_qfull_retries; 280 uchar_t cmd_queued; /* true if queued */ 281 struct mptsas_cmd *cmd_linkp; 282 mptti_t *cmd_sg; /* Scatter/Gather structure */ 283 uchar_t cmd_cdb[SCSI_CDB_SIZE]; 284 uint64_t cmd_pkt_private[PKT_PRIV_LEN]; 285 uint32_t cmd_slot; 286 uint32_t ioc_cmd_slot; 287 288 mptsas_cache_frames_t *cmd_extra_frames; 289 290 uint32_t cmd_rfm; 291 mptsas_target_t *cmd_tgt_addr; 292 } mptsas_cmd_t; 293 294 /* 295 * These are the defined cmd_flags for this structure. 296 */ 297 #define CFLAG_CMDDISC 0x000001 /* cmd currently disconnected */ 298 #define CFLAG_WATCH 0x000002 /* watchdog time for this command */ 299 #define CFLAG_FINISHED 0x000004 /* command completed */ 300 #define CFLAG_CHKSEG 0x000008 /* check cmd_data within seg */ 301 #define CFLAG_COMPLETED 0x000010 /* completion routine called */ 302 #define CFLAG_PREPARED 0x000020 /* pkt has been init'ed */ 303 #define CFLAG_IN_TRANSPORT 0x000040 /* in use by host adapter driver */ 304 #define CFLAG_RESTORE_PTRS 0x000080 /* implicit restore ptr on reconnect */ 305 #define CFLAG_ARQ_IN_PROGRESS 0x000100 /* auto request sense in progress */ 306 #define CFLAG_TRANFLAG 0x0001ff /* covers transport part of flags */ 307 #define CFLAG_TM_CMD 0x000200 /* cmd is a task management command */ 308 #define CFLAG_CMDARQ 0x000400 /* cmd is a 'rqsense' command */ 309 #define CFLAG_DMAVALID 0x000800 /* dma mapping valid */ 310 #define CFLAG_DMASEND 0x001000 /* data is going 'out' */ 311 #define CFLAG_CMDIOPB 0x002000 /* this is an 'iopb' packet */ 312 #define CFLAG_CDBEXTERN 0x004000 /* cdb kmem_alloc'd */ 313 #define CFLAG_SCBEXTERN 0x008000 /* scb kmem_alloc'd */ 314 #define CFLAG_FREE 0x010000 /* packet is on free list */ 315 #define CFLAG_PRIVEXTERN 0x020000 /* target private kmem_alloc'd */ 316 #define CFLAG_DMA_PARTIAL 0x040000 /* partial xfer OK */ 317 #define CFLAG_QFULL_STATUS 0x080000 /* pkt got qfull status */ 318 #define CFLAG_TIMEOUT 0x100000 /* passthru/config command timeout */ 319 #define CFLAG_PMM_RECEIVED 0x200000 /* use cmd_pmm* for saving pointers */ 320 #define CFLAG_RETRY 0x400000 /* cmd has been retried */ 321 #define CFLAG_CMDIOC 0x800000 /* cmd is just for for ioc, no io */ 322 #define CFLAG_EXTARQBUFVALID 0x1000000 /* extern arq buf handle is valid */ 323 #define CFLAG_PASSTHRU 0x2000000 /* cmd is a passthrough command */ 324 #define CFLAG_XARQ 0x4000000 /* cmd requests for extra sense */ 325 #define CFLAG_CMDACK 0x8000000 /* cmd for event ack */ 326 #define CFLAG_TXQ 0x10000000 /* cmd queued in the tx_waitq */ 327 #define CFLAG_FW_CMD 0x20000000 /* cmd is a fw up/down command */ 328 #define CFLAG_CONFIG 0x40000000 /* cmd is for config header/page */ 329 #define CFLAG_FW_DIAG 0x80000000 /* cmd is for FW diag buffers */ 330 331 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE 8 332 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK 0xC0 333 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL 0x00 334 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE 0x40 335 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT 0x80 336 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_EXTENDED_UNIT 0xC0 337 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_2B 0x00 338 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_4B 0x01 339 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_6B 0x10 340 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_8B 0x20 341 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_SIZE 0x30 342 343 #define MPTSAS_HASH_ARRAY_SIZE 16 344 /* 345 * hash table definition 346 */ 347 348 #define MPTSAS_HASH_FIRST 0xffff 349 #define MPTSAS_HASH_NEXT 0x0000 350 351 typedef struct mptsas_dma_alloc_state 352 { 353 ddi_dma_handle_t handle; 354 caddr_t memp; 355 size_t size; 356 ddi_acc_handle_t accessp; 357 ddi_dma_cookie_t cookie; 358 } mptsas_dma_alloc_state_t; 359 360 /* 361 * passthrough request structure 362 */ 363 typedef struct mptsas_pt_request { 364 uint8_t *request; 365 uint32_t request_size; 366 uint32_t data_size; 367 uint32_t dataout_size; 368 uint32_t direction; 369 ddi_dma_cookie_t data_cookie; 370 ddi_dma_cookie_t dataout_cookie; 371 } mptsas_pt_request_t; 372 373 /* 374 * config page request structure 375 */ 376 typedef struct mptsas_config_request { 377 uint32_t page_address; 378 uint8_t action; 379 uint8_t page_type; 380 uint8_t page_number; 381 uint8_t page_length; 382 uint8_t page_version; 383 uint8_t ext_page_type; 384 uint16_t ext_page_length; 385 } mptsas_config_request_t; 386 387 typedef struct mptsas_fw_diagnostic_buffer { 388 mptsas_dma_alloc_state_t buffer_data; 389 uint8_t extended_type; 390 uint8_t buffer_type; 391 uint8_t force_release; 392 uint32_t product_specific[23]; 393 uint8_t immediate; 394 uint8_t enabled; 395 uint8_t valid_data; 396 uint8_t owned_by_firmware; 397 uint32_t unique_id; 398 } mptsas_fw_diagnostic_buffer_t; 399 400 /* 401 * FW diag request structure 402 */ 403 typedef struct mptsas_diag_request { 404 mptsas_fw_diagnostic_buffer_t *pBuffer; 405 uint8_t function; 406 } mptsas_diag_request_t; 407 408 typedef struct mptsas_hash_node { 409 void *data; 410 struct mptsas_hash_node *next; 411 } mptsas_hash_node_t; 412 413 typedef struct mptsas_hash_table { 414 struct mptsas_hash_node *head[MPTSAS_HASH_ARRAY_SIZE]; 415 /* 416 * last position in traverse 417 */ 418 struct mptsas_hash_node *cur; 419 uint16_t line; 420 421 } mptsas_hash_table_t; 422 423 /* 424 * RAID volume information 425 */ 426 typedef struct mptsas_raidvol { 427 ushort_t m_israid; 428 uint16_t m_raidhandle; 429 uint64_t m_raidwwid; 430 uint8_t m_state; 431 uint32_t m_statusflags; 432 uint32_t m_settings; 433 uint16_t m_devhdl[MPTSAS_MAX_DISKS_IN_VOL]; 434 uint8_t m_disknum[MPTSAS_MAX_DISKS_IN_VOL]; 435 ushort_t m_diskstatus[MPTSAS_MAX_DISKS_IN_VOL]; 436 uint64_t m_raidsize; 437 int m_raidlevel; 438 int m_ndisks; 439 mptsas_target_t *m_raidtgt; 440 } mptsas_raidvol_t; 441 442 /* 443 * RAID configurations 444 */ 445 typedef struct mptsas_raidconfig { 446 mptsas_raidvol_t m_raidvol[MPTSAS_MAX_RAIDVOLS]; 447 uint16_t m_physdisk_devhdl[ 448 MPTSAS_MAX_DISKS_IN_CONFIG]; 449 uint8_t m_native; 450 } m_raidconfig_t; 451 452 /* 453 * Structure to hold active outstanding cmds. Also, keep 454 * timeout on a per target basis. 455 */ 456 typedef struct mptsas_slots { 457 mptsas_hash_table_t m_tgttbl; 458 mptsas_hash_table_t m_smptbl; 459 m_raidconfig_t m_raidconfig[MPTSAS_MAX_RAIDCONFIGS]; 460 uint8_t m_num_raid_configs; 461 uint16_t m_tags; 462 size_t m_size; 463 uint16_t m_n_slots; 464 mptsas_cmd_t *m_slot[1]; 465 } mptsas_slots_t; 466 467 /* 468 * Structure to hold command and packets for event ack 469 * and task management commands. 470 */ 471 typedef struct m_event_struct { 472 struct mptsas_cmd m_event_cmd; 473 struct m_event_struct *m_event_linkp; 474 /* 475 * event member record the failure event and eventcntx 476 * event member would be used in send ack pending process 477 */ 478 uint32_t m_event; 479 uint32_t m_eventcntx; 480 uint_t in_use; 481 struct scsi_pkt m_event_pkt; /* must be last */ 482 /* ... scsi_pkt_size() */ 483 } m_event_struct_t; 484 #define M_EVENT_STRUCT_SIZE (sizeof (m_event_struct_t) - \ 485 sizeof (struct scsi_pkt) + scsi_pkt_size()) 486 487 #define MAX_IOC_COMMANDS 8 488 489 /* 490 * A pool of MAX_IOC_COMMANDS is maintained for event ack commands. 491 * A new event ack command requests mptsas_cmd and scsi_pkt structures 492 * from this pool, and returns it back when done. 493 */ 494 495 typedef struct m_replyh_arg { 496 void *mpt; 497 uint32_t rfm; 498 } m_replyh_arg_t; 499 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::mpt)) 500 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::rfm)) 501 502 /* 503 * Flags for DR handler topology change 504 */ 505 #define MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE 0x0 506 #define MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED 0x1 507 #define MPTSAS_TOPO_FLAG_LUN_ASSOCIATED 0x2 508 #define MPTSAS_TOPO_FLAG_RAID_ASSOCIATED 0x4 509 #define MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED 0x8 510 #define MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE 0x10 511 512 typedef struct mptsas_topo_change_list { 513 void *mpt; 514 uint_t event; 515 union { 516 uint8_t physport; 517 mptsas_phymask_t phymask; 518 } un; 519 uint16_t devhdl; 520 void *object; 521 uint8_t flags; 522 struct mptsas_topo_change_list *next; 523 } mptsas_topo_change_list_t; 524 525 526 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::mpt)) 527 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::event)) 528 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::physport)) 529 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::devhdl)) 530 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::object)) 531 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::flags)) 532 533 /* 534 * Status types when calling mptsas_get_target_device_info 535 */ 536 #define DEV_INFO_SUCCESS 0x0 537 #define DEV_INFO_FAIL_PAGE0 0x1 538 #define DEV_INFO_WRONG_DEVICE_TYPE 0x2 539 #define DEV_INFO_PHYS_DISK 0x3 540 #define DEV_INFO_FAIL_ALLOC 0x4 541 542 /* 543 * mpt hotplug event defines 544 */ 545 #define MPTSAS_DR_EVENT_RECONFIG_TARGET 0x01 546 #define MPTSAS_DR_EVENT_OFFLINE_TARGET 0x02 547 #define MPTSAS_TOPO_FLAG_REMOVE_HANDLE 0x04 548 549 /* 550 * SMP target hotplug events 551 */ 552 #define MPTSAS_DR_EVENT_RECONFIG_SMP 0x10 553 #define MPTSAS_DR_EVENT_OFFLINE_SMP 0x20 554 #define MPTSAS_DR_EVENT_MASK 0x3F 555 556 /* 557 * mpt hotplug status definition for m_dr_flag 558 */ 559 560 /* 561 * MPTSAS_DR_INACTIVE 562 * 563 * The target is in a normal operating state. 564 * No dynamic reconfiguration operation is in progress. 565 */ 566 #define MPTSAS_DR_INACTIVE 0x0 567 /* 568 * MPTSAS_DR_INTRANSITION 569 * 570 * The target is in a transition mode since 571 * hotplug event happens and offline procedure has not 572 * been finished 573 */ 574 #define MPTSAS_DR_INTRANSITION 0x1 575 576 typedef struct mptsas_tgt_private { 577 int t_lun; 578 struct mptsas_target *t_private; 579 } mptsas_tgt_private_t; 580 581 /* 582 * The following defines are used in mptsas_set_init_mode to track the current 583 * state as we progress through reprogramming the HBA from target mode into 584 * initiator mode. 585 */ 586 587 #define IOUC_READ_PAGE0 0x00000100 588 #define IOUC_READ_PAGE1 0x00000200 589 #define IOUC_WRITE_PAGE1 0x00000400 590 #define IOUC_DONE 0x00000800 591 #define DISCOVERY_IN_PROGRESS MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS 592 #define AUTO_PORT_CONFIGURATION MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG 593 594 /* 595 * Last allocated slot is used for TM requests. Since only m_max_requests 596 * frames are allocated, the last SMID will be m_max_requests - 1. 597 */ 598 #define MPTSAS_SLOTS_SIZE(mpt) \ 599 (sizeof (struct mptsas_slots) + (sizeof (struct mptsas_cmd *) * \ 600 mpt->m_max_requests)) 601 #define MPTSAS_TM_SLOT(mpt) (mpt->m_max_requests - 1) 602 603 typedef struct mptsas_slot_free_e { 604 processorid_t cpuid; 605 int slot; 606 list_node_t node; 607 } mptsas_slot_free_e_t; 608 609 /* 610 * each of the allocq and releaseq in all CPU groups resides in separate 611 * cacheline(64 bytes). Multiple mutex in the same cacheline is not good 612 * for performance. 613 */ 614 typedef union mptsas_slot_freeq { 615 struct { 616 kmutex_t m_fq_mutex; 617 list_t m_fq_list; 618 int m_fq_n; 619 int m_fq_n_init; 620 } s; 621 char pad[64]; 622 } mptsas_slot_freeq_t; 623 624 typedef struct mptsas_slot_freeq_pair { 625 mptsas_slot_freeq_t m_slot_allocq; 626 mptsas_slot_freeq_t m_slot_releq; 627 } mptsas_slot_freeq_pair_t; 628 629 /* 630 * Macro for phy_flags 631 */ 632 633 typedef struct smhba_info { 634 kmutex_t phy_mutex; 635 uint8_t phy_id; 636 uint64_t sas_addr; 637 char path[8]; 638 uint16_t owner_devhdl; 639 uint16_t attached_devhdl; 640 uint8_t attached_phy_identify; 641 uint32_t attached_phy_info; 642 uint8_t programmed_link_rate; 643 uint8_t hw_link_rate; 644 uint8_t change_count; 645 uint32_t phy_info; 646 uint8_t negotiated_link_rate; 647 uint8_t port_num; 648 kstat_t *phy_stats; 649 uint32_t invalid_dword_count; 650 uint32_t running_disparity_error_count; 651 uint32_t loss_of_dword_sync_count; 652 uint32_t phy_reset_problem_count; 653 void *mpt; 654 } smhba_info_t; 655 656 typedef struct mptsas_phy_info { 657 uint8_t port_num; 658 uint8_t port_flags; 659 uint16_t ctrl_devhdl; 660 uint32_t phy_device_type; 661 uint16_t attached_devhdl; 662 mptsas_phymask_t phy_mask; 663 smhba_info_t smhba_info; 664 } mptsas_phy_info_t; 665 666 667 typedef struct mptsas_doneq_thread_arg { 668 void *mpt; 669 uint64_t t; 670 } mptsas_doneq_thread_arg_t; 671 672 #define MPTSAS_DONEQ_THREAD_ACTIVE 0x1 673 typedef struct mptsas_doneq_thread_list { 674 mptsas_cmd_t *doneq; 675 mptsas_cmd_t **donetail; 676 kthread_t *threadp; 677 kcondvar_t cv; 678 ushort_t reserv1; 679 uint32_t reserv2; 680 kmutex_t mutex; 681 uint32_t flag; 682 uint32_t len; 683 mptsas_doneq_thread_arg_t arg; 684 } mptsas_doneq_thread_list_t; 685 686 typedef struct mptsas { 687 int m_instance; 688 689 struct mptsas *m_next; 690 691 scsi_hba_tran_t *m_tran; 692 smp_hba_tran_t *m_smptran; 693 kmutex_t m_mutex; 694 kcondvar_t m_cv; 695 kcondvar_t m_fw_cv; 696 kcondvar_t m_config_cv; 697 kcondvar_t m_fw_diag_cv; 698 dev_info_t *m_dip; 699 700 /* 701 * soft state flags 702 */ 703 uint_t m_softstate; 704 705 struct mptsas_slots *m_active; /* outstanding cmds */ 706 707 mptsas_cmd_t *m_waitq; /* cmd queue for active request */ 708 mptsas_cmd_t **m_waitqtail; /* wait queue tail ptr */ 709 710 mptsas_cmd_t *m_doneq; /* queue of completed commands */ 711 mptsas_cmd_t **m_donetail; /* queue tail ptr */ 712 713 kmutex_t m_passthru_mutex; 714 kcondvar_t m_passthru_cv; 715 /* 716 * variables for helper threads (fan-out interrupts) 717 */ 718 mptsas_doneq_thread_list_t *m_doneq_thread_id; 719 uint32_t m_doneq_thread_n; 720 uint32_t m_doneq_thread_threshold; 721 uint32_t m_doneq_length_threshold; 722 uint32_t m_doneq_len; 723 kcondvar_t m_doneq_thread_cv; 724 kmutex_t m_doneq_mutex; 725 726 int m_ncmds; /* number of outstanding commands */ 727 m_event_struct_t *m_ioc_event_cmdq; /* cmd queue for ioc event */ 728 m_event_struct_t **m_ioc_event_cmdtail; /* ioc cmd queue tail */ 729 730 ddi_acc_handle_t m_datap; /* operating regs data access handle */ 731 732 struct _MPI2_SYSTEM_INTERFACE_REGS *m_reg; 733 734 ushort_t m_devid; /* device id of chip. */ 735 uchar_t m_revid; /* revision of chip. */ 736 uint16_t m_svid; /* subsystem Vendor ID of chip */ 737 uint16_t m_ssid; /* subsystem Device ID of chip */ 738 739 uchar_t m_sync_offset; /* default offset for this chip. */ 740 741 timeout_id_t m_quiesce_timeid; 742 743 ddi_dma_handle_t m_dma_req_frame_hdl; 744 ddi_acc_handle_t m_acc_req_frame_hdl; 745 ddi_dma_handle_t m_dma_reply_frame_hdl; 746 ddi_acc_handle_t m_acc_reply_frame_hdl; 747 ddi_dma_handle_t m_dma_free_queue_hdl; 748 ddi_acc_handle_t m_acc_free_queue_hdl; 749 ddi_dma_handle_t m_dma_post_queue_hdl; 750 ddi_acc_handle_t m_acc_post_queue_hdl; 751 752 /* 753 * Try the best to make the key code path in the ISR lockless. 754 * so avoid to use the per instance mutex m_mutex in the ISR. Introduce 755 * a separate mutex to protect the elements shown in ISR. 756 */ 757 kmutex_t m_intr_mutex; 758 759 /* 760 * list of reset notification requests 761 */ 762 struct scsi_reset_notify_entry *m_reset_notify_listf; 763 764 /* 765 * qfull handling 766 */ 767 timeout_id_t m_restart_cmd_timeid; 768 769 /* 770 * scsi reset delay per bus 771 */ 772 uint_t m_scsi_reset_delay; 773 774 int m_pm_idle_delay; 775 776 uchar_t m_polled_intr; /* intr was polled. */ 777 uchar_t m_suspended; /* true if driver is suspended */ 778 779 struct kmem_cache *m_kmem_cache; 780 struct kmem_cache *m_cache_frames; 781 782 /* 783 * hba options. 784 */ 785 uint_t m_options; 786 787 int m_in_callback; 788 789 int m_power_level; /* current power level */ 790 791 int m_busy; /* power management busy state */ 792 793 off_t m_pmcsr_offset; /* PMCSR offset */ 794 795 ddi_acc_handle_t m_config_handle; 796 797 ddi_dma_attr_t m_io_dma_attr; /* Used for data I/O */ 798 ddi_dma_attr_t m_msg_dma_attr; /* Used for message frames */ 799 ddi_device_acc_attr_t m_dev_acc_attr; 800 ddi_device_acc_attr_t m_reg_acc_attr; 801 802 /* 803 * request/reply variables 804 */ 805 caddr_t m_req_frame; 806 uint64_t m_req_frame_dma_addr; 807 caddr_t m_reply_frame; 808 uint64_t m_reply_frame_dma_addr; 809 caddr_t m_free_queue; 810 uint64_t m_free_queue_dma_addr; 811 caddr_t m_post_queue; 812 uint64_t m_post_queue_dma_addr; 813 814 m_replyh_arg_t *m_replyh_args; 815 816 uint16_t m_max_requests; 817 uint16_t m_req_frame_size; 818 819 /* 820 * Max frames per request reprted in IOC Facts 821 */ 822 uint8_t m_max_chain_depth; 823 /* 824 * Max frames per request which is used in reality. It's adjusted 825 * according DMA SG length attribute, and shall not exceed the 826 * m_max_chain_depth. 827 */ 828 uint8_t m_max_request_frames; 829 830 uint16_t m_free_queue_depth; 831 uint16_t m_post_queue_depth; 832 uint16_t m_max_replies; 833 uint32_t m_free_index; 834 uint32_t m_post_index; 835 uint8_t m_reply_frame_size; 836 uint32_t m_ioc_capabilities; 837 838 /* 839 * indicates if the firmware was upload by the driver 840 * at boot time 841 */ 842 ushort_t m_fwupload; 843 844 uint16_t m_productid; 845 846 /* 847 * per instance data structures for dma memory resources for 848 * MPI handshake protocol. only one handshake cmd can run at a time. 849 */ 850 ddi_dma_handle_t m_hshk_dma_hdl; 851 852 ddi_acc_handle_t m_hshk_acc_hdl; 853 854 caddr_t m_hshk_memp; 855 856 size_t m_hshk_dma_size; 857 858 /* Firmware version on the card at boot time */ 859 uint32_t m_fwversion; 860 861 /* MSI specific fields */ 862 ddi_intr_handle_t *m_htable; /* For array of interrupts */ 863 int m_intr_type; /* What type of interrupt */ 864 int m_intr_cnt; /* # of intrs count returned */ 865 size_t m_intr_size; /* Size of intr array */ 866 uint_t m_intr_pri; /* Interrupt priority */ 867 int m_intr_cap; /* Interrupt capabilities */ 868 ddi_taskq_t *m_event_taskq; 869 870 /* SAS specific information */ 871 872 union { 873 uint64_t m_base_wwid; /* Base WWID */ 874 struct { 875 #ifdef _BIG_ENDIAN 876 uint32_t m_base_wwid_hi; 877 uint32_t m_base_wwid_lo; 878 #else 879 uint32_t m_base_wwid_lo; 880 uint32_t m_base_wwid_hi; 881 #endif 882 } sasaddr; 883 } un; 884 885 uint8_t m_num_phys; /* # of PHYs */ 886 mptsas_phy_info_t m_phy_info[MPTSAS_MAX_PHYS]; 887 uint8_t m_port_chng; /* initiator port changes */ 888 MPI2_CONFIG_PAGE_MAN_0 m_MANU_page0; /* Manufactor page 0 info */ 889 MPI2_CONFIG_PAGE_MAN_1 m_MANU_page1; /* Manufactor page 1 info */ 890 891 /* FMA Capabilities */ 892 int m_fm_capabilities; 893 ddi_taskq_t *m_dr_taskq; 894 int m_mpxio_enable; 895 uint8_t m_done_traverse_dev; 896 uint8_t m_done_traverse_smp; 897 int m_diag_action_in_progress; 898 uint16_t m_dev_handle; 899 uint16_t m_smp_devhdl; 900 901 /* 902 * Event recording 903 */ 904 uint8_t m_event_index; 905 uint32_t m_event_number; 906 uint32_t m_event_mask[4]; 907 mptsas_event_entry_t m_events[MPTSAS_EVENT_QUEUE_SIZE]; 908 909 /* 910 * FW diag Buffer List 911 */ 912 mptsas_fw_diagnostic_buffer_t 913 m_fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_COUNT]; 914 915 /* 916 * Event Replay flag (MUR support) 917 */ 918 uint8_t m_event_replay; 919 920 /* 921 * IR Capable flag 922 */ 923 uint8_t m_ir_capable; 924 925 /* 926 * release and alloc queue for slot 927 */ 928 int m_slot_freeq_pair_n; 929 mptsas_slot_freeq_pair_t *m_slot_freeq_pairp; 930 mptsas_slot_free_e_t *m_slot_free_ae; 931 #define MPI_ADDRESS_COALSCE_MAX 128 932 pMpi2ReplyDescriptorsUnion_t m_reply; 933 934 /* 935 * Is HBA processing a diag reset? 936 */ 937 uint8_t m_in_reset; 938 939 /* 940 * per instance cmd data structures for task management cmds 941 */ 942 m_event_struct_t m_event_task_mgmt; /* must be last */ 943 /* ... scsi_pkt_size */ 944 } mptsas_t; 945 #define MPTSAS_SIZE (sizeof (struct mptsas) - \ 946 sizeof (struct scsi_pkt) + scsi_pkt_size()) 947 /* 948 * Only one of below two conditions is satisfied, we 949 * think the target is associated to the iport and 950 * allow call into mptsas_probe_lun(). 951 * 1. physicalsport == physport 952 * 2. (phymask & (1 << physport)) == 0 953 * The condition #2 is because LSI uses lowest PHY 954 * number as the value of physical port when auto port 955 * configuration. 956 */ 957 #define IS_SAME_PORT(physicalport, physport, phymask, dynamicport) \ 958 ((physicalport == physport) || (dynamicport && (phymask & \ 959 (1 << physport)))) 960 961 _NOTE(MUTEX_PROTECTS_DATA(mptsas::m_mutex, mptsas)) 962 _NOTE(SCHEME_PROTECTS_DATA("safe sharing", mptsas::m_next)) 963 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_dip mptsas::m_tran)) 964 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_kmem_cache)) 965 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_io_dma_attr.dma_attr_sgllen)) 966 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_devid)) 967 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_productid)) 968 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_port_type)) 969 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_mpxio_enable)) 970 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_ntargets)) 971 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_instance)) 972 973 /* 974 * These should eventually migrate into the mpt header files 975 * that may become the /kernel/misc/mpt module... 976 */ 977 #define mptsas_init_std_hdr(hdl, mp, DevHandle, Lun, ChainOffset, Function) \ 978 mptsas_put_msg_DevHandle(hdl, mp, DevHandle); \ 979 mptsas_put_msg_ChainOffset(hdl, mp, ChainOffset); \ 980 mptsas_put_msg_Function(hdl, mp, Function); \ 981 mptsas_put_msg_Lun(hdl, mp, Lun) 982 983 #define mptsas_put_msg_DevHandle(hdl, mp, val) \ 984 ddi_put16(hdl, &(mp)->DevHandle, (val)) 985 #define mptsas_put_msg_ChainOffset(hdl, mp, val) \ 986 ddi_put8(hdl, &(mp)->ChainOffset, (val)) 987 #define mptsas_put_msg_Function(hdl, mp, val) \ 988 ddi_put8(hdl, &(mp)->Function, (val)) 989 #define mptsas_put_msg_Lun(hdl, mp, val) \ 990 ddi_put8(hdl, &(mp)->LUN[1], (val)) 991 992 #define mptsas_get_msg_Function(hdl, mp) \ 993 ddi_get8(hdl, &(mp)->Function) 994 995 #define mptsas_get_msg_MsgFlags(hdl, mp) \ 996 ddi_get8(hdl, &(mp)->MsgFlags) 997 998 #define MPTSAS_ENABLE_DRWE(hdl) \ 999 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1000 MPI2_WRSEQ_FLUSH_KEY_VALUE); \ 1001 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1002 MPI2_WRSEQ_1ST_KEY_VALUE); \ 1003 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1004 MPI2_WRSEQ_2ND_KEY_VALUE); \ 1005 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1006 MPI2_WRSEQ_3RD_KEY_VALUE); \ 1007 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1008 MPI2_WRSEQ_4TH_KEY_VALUE); \ 1009 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1010 MPI2_WRSEQ_5TH_KEY_VALUE); \ 1011 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1012 MPI2_WRSEQ_6TH_KEY_VALUE); 1013 1014 /* 1015 * m_options flags 1016 */ 1017 #define MPTSAS_OPT_PM 0x01 /* Power Management */ 1018 1019 /* 1020 * m_softstate flags 1021 */ 1022 #define MPTSAS_SS_DRAINING 0x02 1023 #define MPTSAS_SS_QUIESCED 0x04 1024 #define MPTSAS_SS_MSG_UNIT_RESET 0x08 1025 #define MPTSAS_DID_MSG_UNIT_RESET 0x10 1026 1027 /* 1028 * regspec defines. 1029 */ 1030 #define CONFIG_SPACE 0 /* regset[0] - configuration space */ 1031 #define IO_SPACE 1 /* regset[1] - used for i/o mapped device */ 1032 #define MEM_SPACE 2 /* regset[2] - used for memory mapped device */ 1033 #define BASE_REG2 3 /* regset[3] - used for 875 scripts ram */ 1034 1035 /* 1036 * Handy constants 1037 */ 1038 #define FALSE 0 1039 #define TRUE 1 1040 #define UNDEFINED -1 1041 #define FAILED -2 1042 1043 /* 1044 * power management. 1045 */ 1046 #define MPTSAS_POWER_ON(mpt) { \ 1047 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \ 1048 PCI_PMCSR_D0); \ 1049 delay(drv_usectohz(10000)); \ 1050 (void) pci_restore_config_regs(mpt->m_dip); \ 1051 mptsas_setup_cmd_reg(mpt); \ 1052 } 1053 1054 #define MPTSAS_POWER_OFF(mpt) { \ 1055 (void) pci_save_config_regs(mpt->m_dip); \ 1056 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \ 1057 PCI_PMCSR_D3HOT); \ 1058 mpt->m_power_level = PM_LEVEL_D3; \ 1059 } 1060 1061 /* 1062 * inq_dtype: 1063 * Bits 5 through 7 are the Peripheral Device Qualifier 1064 * 001b: device not connected to the LUN 1065 * Bits 0 through 4 are the Peripheral Device Type 1066 * 1fh: Unknown or no device type 1067 * 1068 * Although the inquiry may return success, the following value 1069 * means no valid LUN connected. 1070 */ 1071 #define MPTSAS_VALID_LUN(sd_inq) \ 1072 (((sd_inq->inq_dtype & 0xe0) != 0x20) && \ 1073 ((sd_inq->inq_dtype & 0x1f) != 0x1f)) 1074 1075 /* 1076 * Default is to have 10 retries on receiving QFULL status and 1077 * each retry to be after 100 ms. 1078 */ 1079 #define QFULL_RETRIES 10 1080 #define QFULL_RETRY_INTERVAL 100 1081 1082 /* 1083 * Handy macros 1084 */ 1085 #define Tgt(sp) ((sp)->cmd_pkt->pkt_address.a_target) 1086 #define Lun(sp) ((sp)->cmd_pkt->pkt_address.a_lun) 1087 1088 #define IS_HEX_DIGIT(n) (((n) >= '0' && (n) <= '9') || \ 1089 ((n) >= 'a' && (n) <= 'f') || ((n) >= 'A' && (n) <= 'F')) 1090 1091 /* 1092 * poll time for mptsas_pollret() and mptsas_wait_intr() 1093 */ 1094 #define MPTSAS_POLL_TIME 30000 /* 30 seconds */ 1095 1096 /* 1097 * default time for mptsas_do_passthru 1098 */ 1099 #define MPTSAS_PASS_THRU_TIME_DEFAULT 60 /* 60 seconds */ 1100 1101 /* 1102 * macro to return the effective address of a given per-target field 1103 */ 1104 #define EFF_ADDR(start, offset) ((start) + (offset)) 1105 1106 #define SDEV2ADDR(devp) (&((devp)->sd_address)) 1107 #define SDEV2TRAN(devp) ((devp)->sd_address.a_hba_tran) 1108 #define PKT2TRAN(pkt) ((pkt)->pkt_address.a_hba_tran) 1109 #define ADDR2TRAN(ap) ((ap)->a_hba_tran) 1110 #define DIP2TRAN(dip) (ddi_get_driver_private(dip)) 1111 1112 1113 #define TRAN2MPT(hba) ((mptsas_t *)(hba)->tran_hba_private) 1114 #define DIP2MPT(dip) (TRAN2MPT((scsi_hba_tran_t *)DIP2TRAN(dip))) 1115 #define SDEV2MPT(sd) (TRAN2MPT(SDEV2TRAN(sd))) 1116 #define PKT2MPT(pkt) (TRAN2MPT(PKT2TRAN(pkt))) 1117 1118 #define ADDR2MPT(ap) (TRAN2MPT(ADDR2TRAN(ap))) 1119 1120 #define POLL_TIMEOUT (2 * SCSI_POLL_TIMEOUT * 1000000) 1121 #define SHORT_POLL_TIMEOUT (1000000) /* in usec, about 1 secs */ 1122 #define MPTSAS_QUIESCE_TIMEOUT 1 /* 1 sec */ 1123 #define MPTSAS_PM_IDLE_TIMEOUT 60 /* 60 seconds */ 1124 1125 #define MPTSAS_GET_ISTAT(mpt) (ddi_get32((mpt)->m_datap, \ 1126 &(mpt)->m_reg->HostInterruptStatus)) 1127 1128 #define MPTSAS_SET_SIGP(P) \ 1129 ClrSetBits(mpt->m_devaddr + NREG_ISTAT, 0, NB_ISTAT_SIGP) 1130 1131 #define MPTSAS_RESET_SIGP(P) (void) ddi_get8(mpt->m_datap, \ 1132 (uint8_t *)(mpt->m_devaddr + NREG_CTEST2)) 1133 1134 #define MPTSAS_GET_INTCODE(P) (ddi_get32(mpt->m_datap, \ 1135 (uint32_t *)(mpt->m_devaddr + NREG_DSPS))) 1136 1137 1138 #define MPTSAS_START_CMD(mpt, req_desc_lo, req_desc_hi) \ 1139 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostLow,\ 1140 req_desc_lo);\ 1141 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostHigh,\ 1142 req_desc_hi); 1143 1144 #define INTPENDING(mpt) \ 1145 (MPTSAS_GET_ISTAT(mpt) & MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT) 1146 1147 /* 1148 * Mask all interrupts to disable 1149 */ 1150 #define MPTSAS_DISABLE_INTR(mpt) \ 1151 ddi_put32((mpt)->m_datap, &(mpt)->m_reg->HostInterruptMask, \ 1152 (MPI2_HIM_RIM | MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK)) 1153 1154 /* 1155 * Mask Doorbell and Reset interrupts to enable reply desc int. 1156 */ 1157 #define MPTSAS_ENABLE_INTR(mpt) \ 1158 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, \ 1159 (MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK)) 1160 1161 #define MPTSAS_GET_NEXT_REPLY(mpt, index) \ 1162 &((uint64_t *)(void *)mpt->m_post_queue)[index] 1163 1164 #define MPTSAS_GET_NEXT_FRAME(mpt, SMID) \ 1165 (mpt->m_req_frame + (mpt->m_req_frame_size * SMID)) 1166 1167 #define ClrSetBits32(hdl, reg, clr, set) \ 1168 ddi_put32(hdl, (reg), \ 1169 ((ddi_get32(mpt->m_datap, (reg)) & ~(clr)) | (set))) 1170 1171 #define ClrSetBits(reg, clr, set) \ 1172 ddi_put8(mpt->m_datap, (uint8_t *)(reg), \ 1173 ((ddi_get8(mpt->m_datap, (uint8_t *)(reg)) & ~(clr)) | (set))) 1174 1175 #define MPTSAS_WAITQ_RM(mpt, cmdp) \ 1176 if ((cmdp = mpt->m_waitq) != NULL) { \ 1177 /* If the queue is now empty fix the tail pointer */ \ 1178 if ((mpt->m_waitq = cmdp->cmd_linkp) == NULL) \ 1179 mpt->m_waitqtail = &mpt->m_waitq; \ 1180 cmdp->cmd_linkp = NULL; \ 1181 cmdp->cmd_queued = FALSE; \ 1182 } 1183 1184 #define MPTSAS_TX_WAITQ_RM(mpt, cmdp) \ 1185 if ((cmdp = mpt->m_tx_waitq) != NULL) { \ 1186 /* If the queue is now empty fix the tail pointer */ \ 1187 if ((mpt->m_tx_waitq = cmdp->cmd_linkp) == NULL) \ 1188 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; \ 1189 cmdp->cmd_linkp = NULL; \ 1190 cmdp->cmd_queued = FALSE; \ 1191 } 1192 1193 /* 1194 * defaults for the global properties 1195 */ 1196 #define DEFAULT_SCSI_OPTIONS SCSI_OPTIONS_DR 1197 #define DEFAULT_TAG_AGE_LIMIT 2 1198 #define DEFAULT_WD_TICK 10 1199 1200 /* 1201 * invalid hostid. 1202 */ 1203 #define MPTSAS_INVALID_HOSTID -1 1204 1205 /* 1206 * Get/Set hostid from SCSI port configuration page 1207 */ 1208 #define MPTSAS_GET_HOST_ID(configuration) (configuration & 0xFF) 1209 #define MPTSAS_SET_HOST_ID(hostid) (hostid | ((1 << hostid) << 16)) 1210 1211 /* 1212 * Config space. 1213 */ 1214 #define MPTSAS_LATENCY_TIMER 0x40 1215 1216 /* 1217 * Offset to firmware version 1218 */ 1219 #define MPTSAS_FW_VERSION_OFFSET 9 1220 1221 /* 1222 * Offset and masks to get at the ProductId field 1223 */ 1224 #define MPTSAS_FW_PRODUCTID_OFFSET 8 1225 #define MPTSAS_FW_PRODUCTID_MASK 0xFFFF0000 1226 #define MPTSAS_FW_PRODUCTID_SHIFT 16 1227 1228 /* 1229 * Subsystem ID for HBAs. 1230 */ 1231 #define MPTSAS_HBA_SUBSYSTEM_ID 0x10C0 1232 #define MPTSAS_RHEA_SUBSYSTEM_ID 0x10B0 1233 1234 /* 1235 * reset delay tick 1236 */ 1237 #define MPTSAS_WATCH_RESET_DELAY_TICK 50 /* specified in milli seconds */ 1238 1239 /* 1240 * Ioc reset return values 1241 */ 1242 #define MPTSAS_RESET_FAIL -1 1243 #define MPTSAS_NO_RESET 0 1244 #define MPTSAS_SUCCESS_HARDRESET 1 1245 #define MPTSAS_SUCCESS_MUR 2 1246 1247 /* 1248 * throttle support. 1249 */ 1250 #define MAX_THROTTLE 32 1251 #define HOLD_THROTTLE 0 1252 #define DRAIN_THROTTLE -1 1253 #define QFULL_THROTTLE -2 1254 1255 /* 1256 * Passthrough/config request flags 1257 */ 1258 #define MPTSAS_DATA_ALLOCATED 0x0001 1259 #define MPTSAS_DATAOUT_ALLOCATED 0x0002 1260 #define MPTSAS_REQUEST_POOL_CMD 0x0004 1261 #define MPTSAS_ADDRESS_REPLY 0x0008 1262 #define MPTSAS_CMD_TIMEOUT 0x0010 1263 1264 /* 1265 * response code tlr flag 1266 */ 1267 #define MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF 0x02 1268 1269 /* 1270 * System Events 1271 */ 1272 #ifndef DDI_VENDOR_LSI 1273 #define DDI_VENDOR_LSI "LSI" 1274 #endif /* DDI_VENDOR_LSI */ 1275 1276 /* 1277 * Shared functions 1278 */ 1279 int mptsas_save_cmd(struct mptsas *mpt, struct mptsas_cmd *cmd); 1280 void mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd); 1281 void mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd); 1282 void mptsas_log(struct mptsas *mpt, int level, char *fmt, ...); 1283 int mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime); 1284 int mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)()); 1285 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action, 1286 uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber, 1287 uint8_t pageversion, uint8_t pagelength, uint32_t 1288 SGEflagslength, uint32_t SGEaddress32); 1289 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action, 1290 uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber, 1291 uint8_t pageversion, uint16_t extpagelength, 1292 uint32_t SGEflagslength, uint32_t SGEaddress32); 1293 int mptsas_update_flash(mptsas_t *mpt, caddr_t ptrbuffer, uint32_t size, 1294 uint8_t type, int mode); 1295 int mptsas_check_flash(mptsas_t *mpt, caddr_t origfile, uint32_t size, 1296 uint8_t type, int mode); 1297 int mptsas_download_firmware(); 1298 int mptsas_can_download_firmware(); 1299 int mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep); 1300 void mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep); 1301 mptsas_phymask_t mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport); 1302 void mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd); 1303 int mptsas_check_acc_handle(ddi_acc_handle_t handle); 1304 int mptsas_check_dma_handle(ddi_dma_handle_t handle); 1305 void mptsas_fm_ereport(mptsas_t *mpt, char *detail); 1306 int mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr, 1307 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp, 1308 uint32_t alloc_size, ddi_dma_cookie_t *cookiep); 1309 void mptsas_dma_addr_destroy(ddi_dma_handle_t *, ddi_acc_handle_t *); 1310 1311 /* 1312 * impl functions 1313 */ 1314 int mptsas_ioc_wait_for_response(mptsas_t *mpt); 1315 int mptsas_ioc_wait_for_doorbell(mptsas_t *mpt); 1316 int mptsas_ioc_reset(mptsas_t *mpt); 1317 int mptsas_send_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes, 1318 ddi_acc_handle_t accessp); 1319 int mptsas_get_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes, 1320 ddi_acc_handle_t accessp); 1321 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action, 1322 uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber, 1323 uint8_t pageversion, uint8_t pagelength, uint32_t SGEflagslength, 1324 uint32_t SGEaddress32); 1325 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action, 1326 uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber, 1327 uint8_t pageversion, uint16_t extpagelength, 1328 uint32_t SGEflagslength, uint32_t SGEaddress32); 1329 1330 int mptsas_request_from_pool(mptsas_t *mpt, mptsas_cmd_t **cmd, 1331 struct scsi_pkt **pkt); 1332 void mptsas_return_to_pool(mptsas_t *mpt, mptsas_cmd_t *cmd); 1333 void mptsas_destroy_ioc_event_cmd(mptsas_t *mpt); 1334 void mptsas_start_config_page_access(mptsas_t *mpt, mptsas_cmd_t *cmd); 1335 int mptsas_access_config_page(mptsas_t *mpt, uint8_t action, uint8_t page_type, 1336 uint8_t page_number, uint32_t page_address, int (*callback) (mptsas_t *, 1337 caddr_t, ddi_acc_handle_t, uint16_t, uint32_t, va_list), ...); 1338 1339 int mptsas_ioc_task_management(mptsas_t *mpt, int task_type, 1340 uint16_t dev_handle, int lun, uint8_t *reply, uint32_t reply_size, 1341 int mode); 1342 int mptsas_send_event_ack(mptsas_t *mpt, uint32_t event, uint32_t eventcntx); 1343 void mptsas_send_pending_event_ack(mptsas_t *mpt); 1344 void mptsas_set_throttle(struct mptsas *mpt, mptsas_target_t *ptgt, int what); 1345 int mptsas_restart_ioc(mptsas_t *mpt); 1346 void mptsas_update_driver_data(struct mptsas *mpt); 1347 uint64_t mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun); 1348 1349 /* 1350 * init functions 1351 */ 1352 int mptsas_ioc_get_facts(mptsas_t *mpt); 1353 int mptsas_ioc_get_port_facts(mptsas_t *mpt, int port); 1354 int mptsas_ioc_enable_port(mptsas_t *mpt); 1355 int mptsas_ioc_enable_event_notification(mptsas_t *mpt); 1356 int mptsas_ioc_init(mptsas_t *mpt); 1357 1358 /* 1359 * configuration pages operation 1360 */ 1361 int mptsas_get_sas_device_page0(mptsas_t *mpt, uint32_t page_address, 1362 uint16_t *dev_handle, uint64_t *sas_wwn, uint32_t *dev_info, 1363 uint8_t *physport, uint8_t *phynum, uint16_t *pdevhandle, 1364 uint16_t *slot_num, uint16_t *enclosure); 1365 int mptsas_get_sas_io_unit_page(mptsas_t *mpt); 1366 int mptsas_get_sas_io_unit_page_hndshk(mptsas_t *mpt); 1367 int mptsas_get_sas_expander_page0(mptsas_t *mpt, uint32_t page_address, 1368 mptsas_smp_t *info); 1369 int mptsas_set_ioc_params(mptsas_t *mpt); 1370 int mptsas_get_manufacture_page5(mptsas_t *mpt); 1371 int mptsas_get_sas_port_page0(mptsas_t *mpt, uint32_t page_address, 1372 uint64_t *sas_wwn, uint8_t *portwidth); 1373 int mptsas_get_bios_page3(mptsas_t *mpt, uint32_t *bios_version); 1374 int 1375 mptsas_get_sas_phy_page0(mptsas_t *mpt, uint32_t page_address, 1376 smhba_info_t *info); 1377 int 1378 mptsas_get_sas_phy_page1(mptsas_t *mpt, uint32_t page_address, 1379 smhba_info_t *info); 1380 int 1381 mptsas_get_manufacture_page0(mptsas_t *mpt); 1382 void 1383 mptsas_create_phy_stats(mptsas_t *mpt, char *iport, dev_info_t *dip); 1384 void mptsas_destroy_phy_stats(mptsas_t *mpt); 1385 int mptsas_smhba_phy_init(mptsas_t *mpt); 1386 /* 1387 * RAID functions 1388 */ 1389 int mptsas_get_raid_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol); 1390 int mptsas_get_raid_info(mptsas_t *mpt); 1391 int mptsas_get_physdisk_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol, 1392 uint8_t physdisknum); 1393 int mptsas_delete_volume(mptsas_t *mpt, uint16_t volid); 1394 void mptsas_raid_action_system_shutdown(mptsas_t *mpt); 1395 1396 #define MPTSAS_IOCSTATUS(status) (status & MPI2_IOCSTATUS_MASK) 1397 /* 1398 * debugging. 1399 */ 1400 #if defined(MPTSAS_DEBUG) 1401 1402 void mptsas_printf(char *fmt, ...); 1403 1404 #define MPTSAS_DBGPR(m, args) \ 1405 if (mptsas_debug_flags & (m)) \ 1406 mptsas_printf args 1407 #else /* ! defined(MPTSAS_DEBUG) */ 1408 #define MPTSAS_DBGPR(m, args) 1409 #endif /* defined(MPTSAS_DEBUG) */ 1410 1411 #define NDBG0(args) MPTSAS_DBGPR(0x01, args) /* init */ 1412 #define NDBG1(args) MPTSAS_DBGPR(0x02, args) /* normal running */ 1413 #define NDBG2(args) MPTSAS_DBGPR(0x04, args) /* property handling */ 1414 #define NDBG3(args) MPTSAS_DBGPR(0x08, args) /* pkt handling */ 1415 1416 #define NDBG4(args) MPTSAS_DBGPR(0x10, args) /* kmem alloc/free */ 1417 #define NDBG5(args) MPTSAS_DBGPR(0x20, args) /* polled cmds */ 1418 #define NDBG6(args) MPTSAS_DBGPR(0x40, args) /* interrupts */ 1419 #define NDBG7(args) MPTSAS_DBGPR(0x80, args) /* queue handling */ 1420 1421 #define NDBG8(args) MPTSAS_DBGPR(0x0100, args) /* arq */ 1422 #define NDBG9(args) MPTSAS_DBGPR(0x0200, args) /* Tagged Q'ing */ 1423 #define NDBG10(args) MPTSAS_DBGPR(0x0400, args) /* halting chip */ 1424 #define NDBG11(args) MPTSAS_DBGPR(0x0800, args) /* power management */ 1425 1426 #define NDBG12(args) MPTSAS_DBGPR(0x1000, args) /* enumeration */ 1427 #define NDBG13(args) MPTSAS_DBGPR(0x2000, args) /* configuration page */ 1428 #define NDBG14(args) MPTSAS_DBGPR(0x4000, args) /* LED control */ 1429 #define NDBG15(args) MPTSAS_DBGPR(0x8000, args) 1430 1431 #define NDBG16(args) MPTSAS_DBGPR(0x010000, args) 1432 #define NDBG17(args) MPTSAS_DBGPR(0x020000, args) /* scatter/gather */ 1433 #define NDBG18(args) MPTSAS_DBGPR(0x040000, args) 1434 #define NDBG19(args) MPTSAS_DBGPR(0x080000, args) /* handshaking */ 1435 1436 #define NDBG20(args) MPTSAS_DBGPR(0x100000, args) /* events */ 1437 #define NDBG21(args) MPTSAS_DBGPR(0x200000, args) /* dma */ 1438 #define NDBG22(args) MPTSAS_DBGPR(0x400000, args) /* reset */ 1439 #define NDBG23(args) MPTSAS_DBGPR(0x800000, args) /* abort */ 1440 1441 #define NDBG24(args) MPTSAS_DBGPR(0x1000000, args) /* capabilities */ 1442 #define NDBG25(args) MPTSAS_DBGPR(0x2000000, args) /* flushing */ 1443 #define NDBG26(args) MPTSAS_DBGPR(0x4000000, args) 1444 #define NDBG27(args) MPTSAS_DBGPR(0x8000000, args) 1445 1446 #define NDBG28(args) MPTSAS_DBGPR(0x10000000, args) /* hotplug */ 1447 #define NDBG29(args) MPTSAS_DBGPR(0x20000000, args) /* timeouts */ 1448 #define NDBG30(args) MPTSAS_DBGPR(0x40000000, args) /* mptsas_watch */ 1449 #define NDBG31(args) MPTSAS_DBGPR(0x80000000, args) /* negotations */ 1450 1451 /* 1452 * auto request sense 1453 */ 1454 #define RQ_MAKECOM_COMMON(pkt, flag, cmd) \ 1455 (pkt)->pkt_flags = (flag), \ 1456 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_cmd = (cmd), \ 1457 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_lun = \ 1458 (pkt)->pkt_address.a_lun 1459 1460 #define RQ_MAKECOM_G0(pkt, flag, cmd, addr, cnt) \ 1461 RQ_MAKECOM_COMMON((pkt), (flag), (cmd)), \ 1462 FORMG0ADDR(((union scsi_cdb *)(pkt)->pkt_cdbp), (addr)), \ 1463 FORMG0COUNT(((union scsi_cdb *)(pkt)->pkt_cdbp), (cnt)) 1464 1465 1466 #ifdef __cplusplus 1467 } 1468 #endif 1469 1470 #endif /* _SYS_SCSI_ADAPTERS_MPTVAR_H */ 1471