1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved. 24 * Copyright 2012 Nexenta Systems, Inc. All rights reserved. 25 */ 26 27 /* 28 * Copyright (c) 2000 to 2010, LSI Corporation. 29 * All rights reserved. 30 * 31 * Redistribution and use in source and binary forms of all code within 32 * this file that is exclusively owned by LSI, with or without 33 * modification, is permitted provided that, in addition to the CDDL 1.0 34 * License requirements, the following conditions are met: 35 * 36 * Neither the name of the author nor the names of its contributors may be 37 * used to endorse or promote products derived from this software without 38 * specific prior written permission. 39 * 40 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 41 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 42 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 43 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 44 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 46 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 47 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 48 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 49 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 50 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH 51 * DAMAGE. 52 */ 53 54 #ifndef _SYS_SCSI_ADAPTERS_MPTVAR_H 55 #define _SYS_SCSI_ADAPTERS_MPTVAR_H 56 57 #include <sys/byteorder.h> 58 #include <sys/isa_defs.h> 59 #include <sys/sunmdi.h> 60 #include <sys/mdi_impldefs.h> 61 #include <sys/scsi/adapters/mpt_sas/mptsas_ioctl.h> 62 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_tool.h> 63 #include <sys/scsi/adapters/mpt_sas/mpi/mpi2_cnfg.h> 64 65 #ifdef __cplusplus 66 extern "C" { 67 #endif 68 69 /* 70 * Compile options 71 */ 72 #ifdef DEBUG 73 #define MPTSAS_DEBUG /* turn on debugging code */ 74 #endif /* DEBUG */ 75 76 #define MPTSAS_INITIAL_SOFT_SPACE 4 77 78 #define MAX_MPI_PORTS 16 79 80 /* 81 * Note below macro definition and data type definition 82 * are used for phy mask handling, it should be changed 83 * simultaneously. 84 */ 85 #define MPTSAS_MAX_PHYS 16 86 typedef uint16_t mptsas_phymask_t; 87 88 #define MPTSAS_INVALID_DEVHDL 0xffff 89 #define MPTSAS_SATA_GUID "sata-guid" 90 91 /* 92 * MPT HW defines 93 */ 94 #define MPTSAS_MAX_DISKS_IN_CONFIG 14 95 #define MPTSAS_MAX_DISKS_IN_VOL 10 96 #define MPTSAS_MAX_HOTSPARES 2 97 #define MPTSAS_MAX_RAIDVOLS 2 98 #define MPTSAS_MAX_RAIDCONFIGS 5 99 100 /* 101 * 64-bit SAS WWN is displayed as 16 characters as HEX characters, 102 * plus two means the prefix 'w' and end of the string '\0'. 103 */ 104 #define MPTSAS_WWN_STRLEN (16 + 2) 105 #define MPTSAS_MAX_GUID_LEN 64 106 107 /* 108 * DMA routine flags 109 */ 110 #define MPTSAS_DMA_HANDLE_ALLOCD 0x2 111 #define MPTSAS_DMA_MEMORY_ALLOCD 0x4 112 #define MPTSAS_DMA_HANDLE_BOUND 0x8 113 114 /* 115 * If the HBA supports DMA or bus-mastering, you may have your own 116 * scatter-gather list for physically non-contiguous memory in one 117 * I/O operation; if so, there's probably a size for that list. 118 * It must be placed in the ddi_dma_lim_t structure, so that the system 119 * DMA-support routines can use it to break up the I/O request, so we 120 * define it here. 121 */ 122 #if defined(__sparc) 123 #define MPTSAS_MAX_DMA_SEGS 1 124 #define MPTSAS_MAX_CMD_SEGS 1 125 #else 126 #define MPTSAS_MAX_DMA_SEGS 256 127 #define MPTSAS_MAX_CMD_SEGS 257 128 #endif 129 #define MPTSAS_MAX_FRAME_SGES(mpt) \ 130 (((mpt->m_req_frame_size - (sizeof (MPI2_SCSI_IO_REQUEST))) / 8) + 1) 131 132 /* 133 * Caculating how many 64-bit DMA simple elements can be stored in the first 134 * frame. Note that msg_scsi_io_request contains 2 double-words (8 bytes) for 135 * element storage. And 64-bit dma element is 3 double-words (12 bytes) in 136 * size. 137 */ 138 #define MPTSAS_MAX_FRAME_SGES64(mpt) \ 139 ((mpt->m_req_frame_size - \ 140 (sizeof (MPI2_SCSI_IO_REQUEST)) + sizeof (MPI2_SGE_IO_UNION)) / 12) 141 142 /* 143 * Scatter-gather list structure defined by HBA hardware 144 */ 145 typedef struct NcrTableIndirect { /* Table Indirect entries */ 146 uint32_t count; /* 24 bit count */ 147 union { 148 uint32_t address32; /* 32 bit address */ 149 struct { 150 uint32_t Low; 151 uint32_t High; 152 } address64; /* 64 bit address */ 153 } addr; 154 } mptti_t; 155 156 /* 157 * preferred pkt_private length in 64-bit quantities 158 */ 159 #ifdef _LP64 160 #define PKT_PRIV_SIZE 2 161 #define PKT_PRIV_LEN 16 /* in bytes */ 162 #else /* _ILP32 */ 163 #define PKT_PRIV_SIZE 1 164 #define PKT_PRIV_LEN 8 /* in bytes */ 165 #endif 166 167 #define PKT2CMD(pkt) ((struct mptsas_cmd *)((pkt)->pkt_ha_private)) 168 #define CMD2PKT(cmdp) ((struct scsi_pkt *)((cmdp)->cmd_pkt)) 169 #define EXTCMDS_STATUS_SIZE (sizeof (struct scsi_arq_status)) 170 171 /* 172 * get offset of item in structure 173 */ 174 #define MPTSAS_GET_ITEM_OFF(type, member) ((size_t)(&((type *)0)->member)) 175 176 /* 177 * WWID provided by LSI firmware is generated by firmware but the WWID is not 178 * IEEE NAA standard format, OBP has no chance to distinguish format of unit 179 * address. According LSI's confirmation, the top nibble of RAID WWID is 180 * meanless, so the consensus between Solaris and OBP is to replace top nibble 181 * of WWID provided by LSI to "3" always to hint OBP that this is a RAID WWID 182 * format unit address. 183 */ 184 #define MPTSAS_RAID_WWID(wwid) \ 185 ((wwid & 0x0FFFFFFFFFFFFFFF) | 0x3000000000000000) 186 187 typedef struct mptsas_target { 188 uint64_t m_sas_wwn; /* hash key1 */ 189 mptsas_phymask_t m_phymask; /* hash key2 */ 190 /* 191 * m_dr_flag is a flag for DR, make sure the member 192 * take the place of dr_flag of mptsas_hash_data. 193 */ 194 uint8_t m_dr_flag; /* dr_flag */ 195 uint16_t m_devhdl; 196 uint32_t m_deviceinfo; 197 uint8_t m_phynum; 198 uint32_t m_dups; 199 int32_t m_timeout; 200 int32_t m_timebase; 201 int32_t m_t_throttle; 202 int32_t m_t_ncmds; 203 int32_t m_reset_delay; 204 int32_t m_t_nwait; 205 206 uint16_t m_qfull_retry_interval; 207 uint8_t m_qfull_retries; 208 uint16_t m_enclosure; 209 uint16_t m_slot_num; 210 uint32_t m_tgt_unconfigured; 211 212 /* 213 * For the common case, the elements in this structure are 214 * protected by the per hba instance mutex. In order to make 215 * the key code path in ISR lockless, a separate mutex is 216 * introdeced to protect those shown in ISR. 217 */ 218 kmutex_t m_tgt_intr_mutex; 219 220 } mptsas_target_t; 221 222 typedef struct mptsas_smp { 223 uint64_t m_sasaddr; /* hash key1 */ 224 mptsas_phymask_t m_phymask; /* hash key2 */ 225 uint8_t reserved1; 226 uint16_t m_devhdl; 227 uint32_t m_deviceinfo; 228 uint16_t m_pdevhdl; 229 uint32_t m_pdevinfo; 230 } mptsas_smp_t; 231 232 typedef struct mptsas_hash_data { 233 uint64_t key1; 234 mptsas_phymask_t key2; 235 uint8_t dr_flag; 236 uint16_t devhdl; 237 uint32_t device_info; 238 } mptsas_hash_data_t; 239 240 typedef struct mptsas_cache_frames { 241 ddi_dma_handle_t m_dma_hdl; 242 ddi_acc_handle_t m_acc_hdl; 243 caddr_t m_frames_addr; 244 uint32_t m_phys_addr; 245 } mptsas_cache_frames_t; 246 247 typedef struct mptsas_cmd { 248 uint_t cmd_flags; /* flags from scsi_init_pkt */ 249 ddi_dma_handle_t cmd_dmahandle; /* dma handle */ 250 ddi_dma_cookie_t cmd_cookie; 251 uint_t cmd_cookiec; 252 uint_t cmd_winindex; 253 uint_t cmd_nwin; 254 uint_t cmd_cur_cookie; 255 off_t cmd_dma_offset; 256 size_t cmd_dma_len; 257 uint32_t cmd_totaldmacount; 258 259 ddi_dma_handle_t cmd_arqhandle; /* dma arq handle */ 260 ddi_dma_cookie_t cmd_arqcookie; 261 struct buf *cmd_arq_buf; 262 ddi_dma_handle_t cmd_ext_arqhandle; /* dma extern arq handle */ 263 ddi_dma_cookie_t cmd_ext_arqcookie; 264 struct buf *cmd_ext_arq_buf; 265 266 int cmd_pkt_flags; 267 268 /* timer for command in active slot */ 269 int cmd_active_timeout; 270 271 struct scsi_pkt *cmd_pkt; 272 struct scsi_arq_status cmd_scb; 273 uchar_t cmd_cdblen; /* length of cdb */ 274 uchar_t cmd_rqslen; /* len of requested rqsense */ 275 uchar_t cmd_privlen; 276 uint_t cmd_scblen; 277 uint32_t cmd_dmacount; 278 uint64_t cmd_dma_addr; 279 uchar_t cmd_age; 280 ushort_t cmd_qfull_retries; 281 uchar_t cmd_queued; /* true if queued */ 282 struct mptsas_cmd *cmd_linkp; 283 mptti_t *cmd_sg; /* Scatter/Gather structure */ 284 uchar_t cmd_cdb[SCSI_CDB_SIZE]; 285 uint64_t cmd_pkt_private[PKT_PRIV_LEN]; 286 uint32_t cmd_slot; 287 uint32_t ioc_cmd_slot; 288 289 mptsas_cache_frames_t *cmd_extra_frames; 290 291 uint32_t cmd_rfm; 292 mptsas_target_t *cmd_tgt_addr; 293 } mptsas_cmd_t; 294 295 /* 296 * These are the defined cmd_flags for this structure. 297 */ 298 #define CFLAG_CMDDISC 0x000001 /* cmd currently disconnected */ 299 #define CFLAG_WATCH 0x000002 /* watchdog time for this command */ 300 #define CFLAG_FINISHED 0x000004 /* command completed */ 301 #define CFLAG_CHKSEG 0x000008 /* check cmd_data within seg */ 302 #define CFLAG_COMPLETED 0x000010 /* completion routine called */ 303 #define CFLAG_PREPARED 0x000020 /* pkt has been init'ed */ 304 #define CFLAG_IN_TRANSPORT 0x000040 /* in use by host adapter driver */ 305 #define CFLAG_RESTORE_PTRS 0x000080 /* implicit restore ptr on reconnect */ 306 #define CFLAG_ARQ_IN_PROGRESS 0x000100 /* auto request sense in progress */ 307 #define CFLAG_TRANFLAG 0x0001ff /* covers transport part of flags */ 308 #define CFLAG_TM_CMD 0x000200 /* cmd is a task management command */ 309 #define CFLAG_CMDARQ 0x000400 /* cmd is a 'rqsense' command */ 310 #define CFLAG_DMAVALID 0x000800 /* dma mapping valid */ 311 #define CFLAG_DMASEND 0x001000 /* data is going 'out' */ 312 #define CFLAG_CMDIOPB 0x002000 /* this is an 'iopb' packet */ 313 #define CFLAG_CDBEXTERN 0x004000 /* cdb kmem_alloc'd */ 314 #define CFLAG_SCBEXTERN 0x008000 /* scb kmem_alloc'd */ 315 #define CFLAG_FREE 0x010000 /* packet is on free list */ 316 #define CFLAG_PRIVEXTERN 0x020000 /* target private kmem_alloc'd */ 317 #define CFLAG_DMA_PARTIAL 0x040000 /* partial xfer OK */ 318 #define CFLAG_QFULL_STATUS 0x080000 /* pkt got qfull status */ 319 #define CFLAG_TIMEOUT 0x100000 /* passthru/config command timeout */ 320 #define CFLAG_PMM_RECEIVED 0x200000 /* use cmd_pmm* for saving pointers */ 321 #define CFLAG_RETRY 0x400000 /* cmd has been retried */ 322 #define CFLAG_CMDIOC 0x800000 /* cmd is just for for ioc, no io */ 323 #define CFLAG_EXTARQBUFVALID 0x1000000 /* extern arq buf handle is valid */ 324 #define CFLAG_PASSTHRU 0x2000000 /* cmd is a passthrough command */ 325 #define CFLAG_XARQ 0x4000000 /* cmd requests for extra sense */ 326 #define CFLAG_CMDACK 0x8000000 /* cmd for event ack */ 327 #define CFLAG_TXQ 0x10000000 /* cmd queued in the tx_waitq */ 328 #define CFLAG_FW_CMD 0x20000000 /* cmd is a fw up/down command */ 329 #define CFLAG_CONFIG 0x40000000 /* cmd is for config header/page */ 330 #define CFLAG_FW_DIAG 0x80000000 /* cmd is for FW diag buffers */ 331 332 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_SIZE 8 333 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_MASK 0xC0 334 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_PERIPHERAL 0x00 335 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_FLAT_SPACE 0x40 336 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT 0x80 337 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_EXTENDED_UNIT 0xC0 338 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_2B 0x00 339 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_4B 0x01 340 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_6B 0x10 341 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_8B 0x20 342 #define MPTSAS_SCSI_REPORTLUNS_ADDRESS_LOGICAL_UNIT_SIZE 0x30 343 344 #define MPTSAS_HASH_ARRAY_SIZE 16 345 /* 346 * hash table definition 347 */ 348 349 #define MPTSAS_HASH_FIRST 0xffff 350 #define MPTSAS_HASH_NEXT 0x0000 351 352 typedef struct mptsas_dma_alloc_state 353 { 354 ddi_dma_handle_t handle; 355 caddr_t memp; 356 size_t size; 357 ddi_acc_handle_t accessp; 358 ddi_dma_cookie_t cookie; 359 } mptsas_dma_alloc_state_t; 360 361 /* 362 * passthrough request structure 363 */ 364 typedef struct mptsas_pt_request { 365 uint8_t *request; 366 uint32_t request_size; 367 uint32_t data_size; 368 uint32_t dataout_size; 369 uint32_t direction; 370 ddi_dma_cookie_t data_cookie; 371 ddi_dma_cookie_t dataout_cookie; 372 } mptsas_pt_request_t; 373 374 /* 375 * config page request structure 376 */ 377 typedef struct mptsas_config_request { 378 uint32_t page_address; 379 uint8_t action; 380 uint8_t page_type; 381 uint8_t page_number; 382 uint8_t page_length; 383 uint8_t page_version; 384 uint8_t ext_page_type; 385 uint16_t ext_page_length; 386 } mptsas_config_request_t; 387 388 typedef struct mptsas_fw_diagnostic_buffer { 389 mptsas_dma_alloc_state_t buffer_data; 390 uint8_t extended_type; 391 uint8_t buffer_type; 392 uint8_t force_release; 393 uint32_t product_specific[23]; 394 uint8_t immediate; 395 uint8_t enabled; 396 uint8_t valid_data; 397 uint8_t owned_by_firmware; 398 uint32_t unique_id; 399 } mptsas_fw_diagnostic_buffer_t; 400 401 /* 402 * FW diag request structure 403 */ 404 typedef struct mptsas_diag_request { 405 mptsas_fw_diagnostic_buffer_t *pBuffer; 406 uint8_t function; 407 } mptsas_diag_request_t; 408 409 typedef struct mptsas_hash_node { 410 void *data; 411 struct mptsas_hash_node *next; 412 } mptsas_hash_node_t; 413 414 typedef struct mptsas_hash_table { 415 struct mptsas_hash_node *head[MPTSAS_HASH_ARRAY_SIZE]; 416 /* 417 * last position in traverse 418 */ 419 struct mptsas_hash_node *cur; 420 uint16_t line; 421 422 } mptsas_hash_table_t; 423 424 /* 425 * RAID volume information 426 */ 427 typedef struct mptsas_raidvol { 428 ushort_t m_israid; 429 uint16_t m_raidhandle; 430 uint64_t m_raidwwid; 431 uint8_t m_state; 432 uint32_t m_statusflags; 433 uint32_t m_settings; 434 uint16_t m_devhdl[MPTSAS_MAX_DISKS_IN_VOL]; 435 uint8_t m_disknum[MPTSAS_MAX_DISKS_IN_VOL]; 436 ushort_t m_diskstatus[MPTSAS_MAX_DISKS_IN_VOL]; 437 uint64_t m_raidsize; 438 int m_raidlevel; 439 int m_ndisks; 440 mptsas_target_t *m_raidtgt; 441 } mptsas_raidvol_t; 442 443 /* 444 * RAID configurations 445 */ 446 typedef struct mptsas_raidconfig { 447 mptsas_raidvol_t m_raidvol[MPTSAS_MAX_RAIDVOLS]; 448 uint16_t m_physdisk_devhdl[ 449 MPTSAS_MAX_DISKS_IN_CONFIG]; 450 uint8_t m_native; 451 } m_raidconfig_t; 452 453 /* 454 * Structure to hold active outstanding cmds. Also, keep 455 * timeout on a per target basis. 456 */ 457 typedef struct mptsas_slots { 458 mptsas_hash_table_t m_tgttbl; 459 mptsas_hash_table_t m_smptbl; 460 m_raidconfig_t m_raidconfig[MPTSAS_MAX_RAIDCONFIGS]; 461 uint8_t m_num_raid_configs; 462 uint16_t m_tags; 463 size_t m_size; 464 uint16_t m_n_slots; 465 mptsas_cmd_t *m_slot[1]; 466 } mptsas_slots_t; 467 468 /* 469 * Structure to hold command and packets for event ack 470 * and task management commands. 471 */ 472 typedef struct m_event_struct { 473 struct mptsas_cmd m_event_cmd; 474 struct m_event_struct *m_event_linkp; 475 /* 476 * event member record the failure event and eventcntx 477 * event member would be used in send ack pending process 478 */ 479 uint32_t m_event; 480 uint32_t m_eventcntx; 481 uint_t in_use; 482 struct scsi_pkt m_event_pkt; /* must be last */ 483 /* ... scsi_pkt_size() */ 484 } m_event_struct_t; 485 #define M_EVENT_STRUCT_SIZE (sizeof (m_event_struct_t) - \ 486 sizeof (struct scsi_pkt) + scsi_pkt_size()) 487 488 #define MAX_IOC_COMMANDS 8 489 490 /* 491 * A pool of MAX_IOC_COMMANDS is maintained for event ack commands. 492 * A new event ack command requests mptsas_cmd and scsi_pkt structures 493 * from this pool, and returns it back when done. 494 */ 495 496 typedef struct m_replyh_arg { 497 void *mpt; 498 uint32_t rfm; 499 } m_replyh_arg_t; 500 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::mpt)) 501 _NOTE(DATA_READABLE_WITHOUT_LOCK(m_replyh_arg_t::rfm)) 502 503 /* 504 * Flags for DR handler topology change 505 */ 506 #define MPTSAS_TOPO_FLAG_DIRECT_ATTACHED_DEVICE 0x0 507 #define MPTSAS_TOPO_FLAG_EXPANDER_ASSOCIATED 0x1 508 #define MPTSAS_TOPO_FLAG_LUN_ASSOCIATED 0x2 509 #define MPTSAS_TOPO_FLAG_RAID_ASSOCIATED 0x4 510 #define MPTSAS_TOPO_FLAG_RAID_PHYSDRV_ASSOCIATED 0x8 511 #define MPTSAS_TOPO_FLAG_EXPANDER_ATTACHED_DEVICE 0x10 512 513 typedef struct mptsas_topo_change_list { 514 void *mpt; 515 uint_t event; 516 union { 517 uint8_t physport; 518 mptsas_phymask_t phymask; 519 } un; 520 uint16_t devhdl; 521 void *object; 522 uint8_t flags; 523 struct mptsas_topo_change_list *next; 524 } mptsas_topo_change_list_t; 525 526 527 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::mpt)) 528 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::event)) 529 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::physport)) 530 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::devhdl)) 531 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::object)) 532 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas_topo_change_list_t::flags)) 533 534 /* 535 * Status types when calling mptsas_get_target_device_info 536 */ 537 #define DEV_INFO_SUCCESS 0x0 538 #define DEV_INFO_FAIL_PAGE0 0x1 539 #define DEV_INFO_WRONG_DEVICE_TYPE 0x2 540 #define DEV_INFO_PHYS_DISK 0x3 541 #define DEV_INFO_FAIL_ALLOC 0x4 542 543 /* 544 * mpt hotplug event defines 545 */ 546 #define MPTSAS_DR_EVENT_RECONFIG_TARGET 0x01 547 #define MPTSAS_DR_EVENT_OFFLINE_TARGET 0x02 548 #define MPTSAS_TOPO_FLAG_REMOVE_HANDLE 0x04 549 550 /* 551 * SMP target hotplug events 552 */ 553 #define MPTSAS_DR_EVENT_RECONFIG_SMP 0x10 554 #define MPTSAS_DR_EVENT_OFFLINE_SMP 0x20 555 #define MPTSAS_DR_EVENT_MASK 0x3F 556 557 /* 558 * mpt hotplug status definition for m_dr_flag 559 */ 560 561 /* 562 * MPTSAS_DR_INACTIVE 563 * 564 * The target is in a normal operating state. 565 * No dynamic reconfiguration operation is in progress. 566 */ 567 #define MPTSAS_DR_INACTIVE 0x0 568 /* 569 * MPTSAS_DR_INTRANSITION 570 * 571 * The target is in a transition mode since 572 * hotplug event happens and offline procedure has not 573 * been finished 574 */ 575 #define MPTSAS_DR_INTRANSITION 0x1 576 577 typedef struct mptsas_tgt_private { 578 int t_lun; 579 struct mptsas_target *t_private; 580 } mptsas_tgt_private_t; 581 582 /* 583 * The following defines are used in mptsas_set_init_mode to track the current 584 * state as we progress through reprogramming the HBA from target mode into 585 * initiator mode. 586 */ 587 588 #define IOUC_READ_PAGE0 0x00000100 589 #define IOUC_READ_PAGE1 0x00000200 590 #define IOUC_WRITE_PAGE1 0x00000400 591 #define IOUC_DONE 0x00000800 592 #define DISCOVERY_IN_PROGRESS MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS 593 #define AUTO_PORT_CONFIGURATION MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG 594 595 /* 596 * Last allocated slot is used for TM requests. Since only m_max_requests 597 * frames are allocated, the last SMID will be m_max_requests - 1. 598 */ 599 #define MPTSAS_SLOTS_SIZE(mpt) \ 600 (sizeof (struct mptsas_slots) + (sizeof (struct mptsas_cmd *) * \ 601 mpt->m_max_requests)) 602 #define MPTSAS_TM_SLOT(mpt) (mpt->m_max_requests - 1) 603 604 typedef struct mptsas_slot_free_e { 605 processorid_t cpuid; 606 int slot; 607 list_node_t node; 608 } mptsas_slot_free_e_t; 609 610 /* 611 * each of the allocq and releaseq in all CPU groups resides in separate 612 * cacheline(64 bytes). Multiple mutex in the same cacheline is not good 613 * for performance. 614 */ 615 typedef union mptsas_slot_freeq { 616 struct { 617 kmutex_t m_fq_mutex; 618 list_t m_fq_list; 619 int m_fq_n; 620 int m_fq_n_init; 621 } s; 622 char pad[64]; 623 } mptsas_slot_freeq_t; 624 625 typedef struct mptsas_slot_freeq_pair { 626 mptsas_slot_freeq_t m_slot_allocq; 627 mptsas_slot_freeq_t m_slot_releq; 628 } mptsas_slot_freeq_pair_t; 629 630 /* 631 * Macro for phy_flags 632 */ 633 634 typedef struct smhba_info { 635 kmutex_t phy_mutex; 636 uint8_t phy_id; 637 uint64_t sas_addr; 638 char path[8]; 639 uint16_t owner_devhdl; 640 uint16_t attached_devhdl; 641 uint8_t attached_phy_identify; 642 uint32_t attached_phy_info; 643 uint8_t programmed_link_rate; 644 uint8_t hw_link_rate; 645 uint8_t change_count; 646 uint32_t phy_info; 647 uint8_t negotiated_link_rate; 648 uint8_t port_num; 649 kstat_t *phy_stats; 650 uint32_t invalid_dword_count; 651 uint32_t running_disparity_error_count; 652 uint32_t loss_of_dword_sync_count; 653 uint32_t phy_reset_problem_count; 654 void *mpt; 655 } smhba_info_t; 656 657 typedef struct mptsas_phy_info { 658 uint8_t port_num; 659 uint8_t port_flags; 660 uint16_t ctrl_devhdl; 661 uint32_t phy_device_type; 662 uint16_t attached_devhdl; 663 mptsas_phymask_t phy_mask; 664 smhba_info_t smhba_info; 665 } mptsas_phy_info_t; 666 667 668 typedef struct mptsas_doneq_thread_arg { 669 void *mpt; 670 uint64_t t; 671 } mptsas_doneq_thread_arg_t; 672 673 #define MPTSAS_DONEQ_THREAD_ACTIVE 0x1 674 typedef struct mptsas_doneq_thread_list { 675 mptsas_cmd_t *doneq; 676 mptsas_cmd_t **donetail; 677 kthread_t *threadp; 678 kcondvar_t cv; 679 ushort_t reserv1; 680 uint32_t reserv2; 681 kmutex_t mutex; 682 uint32_t flag; 683 uint32_t len; 684 mptsas_doneq_thread_arg_t arg; 685 } mptsas_doneq_thread_list_t; 686 687 typedef struct mptsas { 688 int m_instance; 689 690 struct mptsas *m_next; 691 692 scsi_hba_tran_t *m_tran; 693 smp_hba_tran_t *m_smptran; 694 kmutex_t m_mutex; 695 kcondvar_t m_cv; 696 kcondvar_t m_fw_cv; 697 kcondvar_t m_config_cv; 698 kcondvar_t m_fw_diag_cv; 699 dev_info_t *m_dip; 700 701 /* 702 * soft state flags 703 */ 704 uint_t m_softstate; 705 706 struct mptsas_slots *m_active; /* outstanding cmds */ 707 708 mptsas_cmd_t *m_waitq; /* cmd queue for active request */ 709 mptsas_cmd_t **m_waitqtail; /* wait queue tail ptr */ 710 711 mptsas_cmd_t *m_doneq; /* queue of completed commands */ 712 mptsas_cmd_t **m_donetail; /* queue tail ptr */ 713 714 kmutex_t m_passthru_mutex; 715 kcondvar_t m_passthru_cv; 716 /* 717 * variables for helper threads (fan-out interrupts) 718 */ 719 mptsas_doneq_thread_list_t *m_doneq_thread_id; 720 uint32_t m_doneq_thread_n; 721 uint32_t m_doneq_thread_threshold; 722 uint32_t m_doneq_length_threshold; 723 uint32_t m_doneq_len; 724 kcondvar_t m_doneq_thread_cv; 725 kmutex_t m_doneq_mutex; 726 727 int m_ncmds; /* number of outstanding commands */ 728 m_event_struct_t *m_ioc_event_cmdq; /* cmd queue for ioc event */ 729 m_event_struct_t **m_ioc_event_cmdtail; /* ioc cmd queue tail */ 730 731 ddi_acc_handle_t m_datap; /* operating regs data access handle */ 732 733 struct _MPI2_SYSTEM_INTERFACE_REGS *m_reg; 734 735 ushort_t m_devid; /* device id of chip. */ 736 uchar_t m_revid; /* revision of chip. */ 737 uint16_t m_svid; /* subsystem Vendor ID of chip */ 738 uint16_t m_ssid; /* subsystem Device ID of chip */ 739 740 uchar_t m_sync_offset; /* default offset for this chip. */ 741 742 timeout_id_t m_quiesce_timeid; 743 744 ddi_dma_handle_t m_dma_req_frame_hdl; 745 ddi_acc_handle_t m_acc_req_frame_hdl; 746 ddi_dma_handle_t m_dma_reply_frame_hdl; 747 ddi_acc_handle_t m_acc_reply_frame_hdl; 748 ddi_dma_handle_t m_dma_free_queue_hdl; 749 ddi_acc_handle_t m_acc_free_queue_hdl; 750 ddi_dma_handle_t m_dma_post_queue_hdl; 751 ddi_acc_handle_t m_acc_post_queue_hdl; 752 753 /* 754 * Try the best to make the key code path in the ISR lockless. 755 * so avoid to use the per instance mutex m_mutex in the ISR. Introduce 756 * a separate mutex to protect the elements shown in ISR. 757 */ 758 kmutex_t m_intr_mutex; 759 760 /* 761 * list of reset notification requests 762 */ 763 struct scsi_reset_notify_entry *m_reset_notify_listf; 764 765 /* 766 * qfull handling 767 */ 768 timeout_id_t m_restart_cmd_timeid; 769 770 /* 771 * scsi reset delay per bus 772 */ 773 uint_t m_scsi_reset_delay; 774 775 int m_pm_idle_delay; 776 777 uchar_t m_polled_intr; /* intr was polled. */ 778 uchar_t m_suspended; /* true if driver is suspended */ 779 780 struct kmem_cache *m_kmem_cache; 781 struct kmem_cache *m_cache_frames; 782 783 /* 784 * hba options. 785 */ 786 uint_t m_options; 787 788 int m_in_callback; 789 790 int m_power_level; /* current power level */ 791 792 int m_busy; /* power management busy state */ 793 794 off_t m_pmcsr_offset; /* PMCSR offset */ 795 796 ddi_acc_handle_t m_config_handle; 797 798 ddi_dma_attr_t m_io_dma_attr; /* Used for data I/O */ 799 ddi_dma_attr_t m_msg_dma_attr; /* Used for message frames */ 800 ddi_device_acc_attr_t m_dev_acc_attr; 801 ddi_device_acc_attr_t m_reg_acc_attr; 802 803 /* 804 * request/reply variables 805 */ 806 caddr_t m_req_frame; 807 uint64_t m_req_frame_dma_addr; 808 caddr_t m_reply_frame; 809 uint64_t m_reply_frame_dma_addr; 810 caddr_t m_free_queue; 811 uint64_t m_free_queue_dma_addr; 812 caddr_t m_post_queue; 813 uint64_t m_post_queue_dma_addr; 814 815 m_replyh_arg_t *m_replyh_args; 816 817 uint16_t m_max_requests; 818 uint16_t m_req_frame_size; 819 820 /* 821 * Max frames per request reprted in IOC Facts 822 */ 823 uint8_t m_max_chain_depth; 824 /* 825 * Max frames per request which is used in reality. It's adjusted 826 * according DMA SG length attribute, and shall not exceed the 827 * m_max_chain_depth. 828 */ 829 uint8_t m_max_request_frames; 830 831 uint16_t m_free_queue_depth; 832 uint16_t m_post_queue_depth; 833 uint16_t m_max_replies; 834 uint32_t m_free_index; 835 uint32_t m_post_index; 836 uint8_t m_reply_frame_size; 837 uint32_t m_ioc_capabilities; 838 839 /* 840 * indicates if the firmware was upload by the driver 841 * at boot time 842 */ 843 ushort_t m_fwupload; 844 845 uint16_t m_productid; 846 847 /* 848 * per instance data structures for dma memory resources for 849 * MPI handshake protocol. only one handshake cmd can run at a time. 850 */ 851 ddi_dma_handle_t m_hshk_dma_hdl; 852 853 ddi_acc_handle_t m_hshk_acc_hdl; 854 855 caddr_t m_hshk_memp; 856 857 size_t m_hshk_dma_size; 858 859 /* Firmware version on the card at boot time */ 860 uint32_t m_fwversion; 861 862 /* MSI specific fields */ 863 ddi_intr_handle_t *m_htable; /* For array of interrupts */ 864 int m_intr_type; /* What type of interrupt */ 865 int m_intr_cnt; /* # of intrs count returned */ 866 size_t m_intr_size; /* Size of intr array */ 867 uint_t m_intr_pri; /* Interrupt priority */ 868 int m_intr_cap; /* Interrupt capabilities */ 869 ddi_taskq_t *m_event_taskq; 870 871 /* SAS specific information */ 872 873 union { 874 uint64_t m_base_wwid; /* Base WWID */ 875 struct { 876 #ifdef _BIG_ENDIAN 877 uint32_t m_base_wwid_hi; 878 uint32_t m_base_wwid_lo; 879 #else 880 uint32_t m_base_wwid_lo; 881 uint32_t m_base_wwid_hi; 882 #endif 883 } sasaddr; 884 } un; 885 886 uint8_t m_num_phys; /* # of PHYs */ 887 mptsas_phy_info_t m_phy_info[MPTSAS_MAX_PHYS]; 888 uint8_t m_port_chng; /* initiator port changes */ 889 MPI2_CONFIG_PAGE_MAN_0 m_MANU_page0; /* Manufactor page 0 info */ 890 MPI2_CONFIG_PAGE_MAN_1 m_MANU_page1; /* Manufactor page 1 info */ 891 892 /* FMA Capabilities */ 893 int m_fm_capabilities; 894 ddi_taskq_t *m_dr_taskq; 895 int m_mpxio_enable; 896 uint8_t m_done_traverse_dev; 897 uint8_t m_done_traverse_smp; 898 int m_diag_action_in_progress; 899 uint16_t m_dev_handle; 900 uint16_t m_smp_devhdl; 901 902 /* 903 * Event recording 904 */ 905 uint8_t m_event_index; 906 uint32_t m_event_number; 907 uint32_t m_event_mask[4]; 908 mptsas_event_entry_t m_events[MPTSAS_EVENT_QUEUE_SIZE]; 909 910 /* 911 * FW diag Buffer List 912 */ 913 mptsas_fw_diagnostic_buffer_t 914 m_fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_COUNT]; 915 916 /* 917 * Event Replay flag (MUR support) 918 */ 919 uint8_t m_event_replay; 920 921 /* 922 * IR Capable flag 923 */ 924 uint8_t m_ir_capable; 925 926 /* 927 * release and alloc queue for slot 928 */ 929 int m_slot_freeq_pair_n; 930 mptsas_slot_freeq_pair_t *m_slot_freeq_pairp; 931 mptsas_slot_free_e_t *m_slot_free_ae; 932 #define MPI_ADDRESS_COALSCE_MAX 128 933 pMpi2ReplyDescriptorsUnion_t m_reply; 934 935 /* 936 * Is HBA processing a diag reset? 937 */ 938 uint8_t m_in_reset; 939 940 /* 941 * per instance cmd data structures for task management cmds 942 */ 943 m_event_struct_t m_event_task_mgmt; /* must be last */ 944 /* ... scsi_pkt_size */ 945 } mptsas_t; 946 #define MPTSAS_SIZE (sizeof (struct mptsas) - \ 947 sizeof (struct scsi_pkt) + scsi_pkt_size()) 948 /* 949 * Only one of below two conditions is satisfied, we 950 * think the target is associated to the iport and 951 * allow call into mptsas_probe_lun(). 952 * 1. physicalsport == physport 953 * 2. (phymask & (1 << physport)) == 0 954 * The condition #2 is because LSI uses lowest PHY 955 * number as the value of physical port when auto port 956 * configuration. 957 */ 958 #define IS_SAME_PORT(physicalport, physport, phymask, dynamicport) \ 959 ((physicalport == physport) || (dynamicport && (phymask & \ 960 (1 << physport)))) 961 962 _NOTE(MUTEX_PROTECTS_DATA(mptsas::m_mutex, mptsas)) 963 _NOTE(SCHEME_PROTECTS_DATA("safe sharing", mptsas::m_next)) 964 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_dip mptsas::m_tran)) 965 _NOTE(SCHEME_PROTECTS_DATA("stable data", mptsas::m_kmem_cache)) 966 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_io_dma_attr.dma_attr_sgllen)) 967 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_devid)) 968 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_productid)) 969 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_port_type)) 970 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_mpxio_enable)) 971 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_ntargets)) 972 _NOTE(DATA_READABLE_WITHOUT_LOCK(mptsas::m_instance)) 973 974 /* 975 * These should eventually migrate into the mpt header files 976 * that may become the /kernel/misc/mpt module... 977 */ 978 #define mptsas_init_std_hdr(hdl, mp, DevHandle, Lun, ChainOffset, Function) \ 979 mptsas_put_msg_DevHandle(hdl, mp, DevHandle); \ 980 mptsas_put_msg_ChainOffset(hdl, mp, ChainOffset); \ 981 mptsas_put_msg_Function(hdl, mp, Function); \ 982 mptsas_put_msg_Lun(hdl, mp, Lun) 983 984 #define mptsas_put_msg_DevHandle(hdl, mp, val) \ 985 ddi_put16(hdl, &(mp)->DevHandle, (val)) 986 #define mptsas_put_msg_ChainOffset(hdl, mp, val) \ 987 ddi_put8(hdl, &(mp)->ChainOffset, (val)) 988 #define mptsas_put_msg_Function(hdl, mp, val) \ 989 ddi_put8(hdl, &(mp)->Function, (val)) 990 #define mptsas_put_msg_Lun(hdl, mp, val) \ 991 ddi_put8(hdl, &(mp)->LUN[1], (val)) 992 993 #define mptsas_get_msg_Function(hdl, mp) \ 994 ddi_get8(hdl, &(mp)->Function) 995 996 #define mptsas_get_msg_MsgFlags(hdl, mp) \ 997 ddi_get8(hdl, &(mp)->MsgFlags) 998 999 #define MPTSAS_ENABLE_DRWE(hdl) \ 1000 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1001 MPI2_WRSEQ_FLUSH_KEY_VALUE); \ 1002 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1003 MPI2_WRSEQ_1ST_KEY_VALUE); \ 1004 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1005 MPI2_WRSEQ_2ND_KEY_VALUE); \ 1006 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1007 MPI2_WRSEQ_3RD_KEY_VALUE); \ 1008 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1009 MPI2_WRSEQ_4TH_KEY_VALUE); \ 1010 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1011 MPI2_WRSEQ_5TH_KEY_VALUE); \ 1012 ddi_put32(hdl->m_datap, &hdl->m_reg->WriteSequence, \ 1013 MPI2_WRSEQ_6TH_KEY_VALUE); 1014 1015 /* 1016 * m_options flags 1017 */ 1018 #define MPTSAS_OPT_PM 0x01 /* Power Management */ 1019 1020 /* 1021 * m_softstate flags 1022 */ 1023 #define MPTSAS_SS_DRAINING 0x02 1024 #define MPTSAS_SS_QUIESCED 0x04 1025 #define MPTSAS_SS_MSG_UNIT_RESET 0x08 1026 #define MPTSAS_DID_MSG_UNIT_RESET 0x10 1027 1028 /* 1029 * regspec defines. 1030 */ 1031 #define CONFIG_SPACE 0 /* regset[0] - configuration space */ 1032 #define IO_SPACE 1 /* regset[1] - used for i/o mapped device */ 1033 #define MEM_SPACE 2 /* regset[2] - used for memory mapped device */ 1034 #define BASE_REG2 3 /* regset[3] - used for 875 scripts ram */ 1035 1036 /* 1037 * Handy constants 1038 */ 1039 #define FALSE 0 1040 #define TRUE 1 1041 #define UNDEFINED -1 1042 #define FAILED -2 1043 1044 /* 1045 * power management. 1046 */ 1047 #define MPTSAS_POWER_ON(mpt) { \ 1048 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \ 1049 PCI_PMCSR_D0); \ 1050 delay(drv_usectohz(10000)); \ 1051 (void) pci_restore_config_regs(mpt->m_dip); \ 1052 mptsas_setup_cmd_reg(mpt); \ 1053 } 1054 1055 #define MPTSAS_POWER_OFF(mpt) { \ 1056 (void) pci_save_config_regs(mpt->m_dip); \ 1057 pci_config_put16(mpt->m_config_handle, mpt->m_pmcsr_offset, \ 1058 PCI_PMCSR_D3HOT); \ 1059 mpt->m_power_level = PM_LEVEL_D3; \ 1060 } 1061 1062 /* 1063 * inq_dtype: 1064 * Bits 5 through 7 are the Peripheral Device Qualifier 1065 * 001b: device not connected to the LUN 1066 * Bits 0 through 4 are the Peripheral Device Type 1067 * 1fh: Unknown or no device type 1068 * 1069 * Although the inquiry may return success, the following value 1070 * means no valid LUN connected. 1071 */ 1072 #define MPTSAS_VALID_LUN(sd_inq) \ 1073 (((sd_inq->inq_dtype & 0xe0) != 0x20) && \ 1074 ((sd_inq->inq_dtype & 0x1f) != 0x1f)) 1075 1076 /* 1077 * Default is to have 10 retries on receiving QFULL status and 1078 * each retry to be after 100 ms. 1079 */ 1080 #define QFULL_RETRIES 10 1081 #define QFULL_RETRY_INTERVAL 100 1082 1083 /* 1084 * Handy macros 1085 */ 1086 #define Tgt(sp) ((sp)->cmd_pkt->pkt_address.a_target) 1087 #define Lun(sp) ((sp)->cmd_pkt->pkt_address.a_lun) 1088 1089 #define IS_HEX_DIGIT(n) (((n) >= '0' && (n) <= '9') || \ 1090 ((n) >= 'a' && (n) <= 'f') || ((n) >= 'A' && (n) <= 'F')) 1091 1092 /* 1093 * poll time for mptsas_pollret() and mptsas_wait_intr() 1094 */ 1095 #define MPTSAS_POLL_TIME 30000 /* 30 seconds */ 1096 1097 /* 1098 * default time for mptsas_do_passthru 1099 */ 1100 #define MPTSAS_PASS_THRU_TIME_DEFAULT 60 /* 60 seconds */ 1101 1102 /* 1103 * macro to return the effective address of a given per-target field 1104 */ 1105 #define EFF_ADDR(start, offset) ((start) + (offset)) 1106 1107 #define SDEV2ADDR(devp) (&((devp)->sd_address)) 1108 #define SDEV2TRAN(devp) ((devp)->sd_address.a_hba_tran) 1109 #define PKT2TRAN(pkt) ((pkt)->pkt_address.a_hba_tran) 1110 #define ADDR2TRAN(ap) ((ap)->a_hba_tran) 1111 #define DIP2TRAN(dip) (ddi_get_driver_private(dip)) 1112 1113 1114 #define TRAN2MPT(hba) ((mptsas_t *)(hba)->tran_hba_private) 1115 #define DIP2MPT(dip) (TRAN2MPT((scsi_hba_tran_t *)DIP2TRAN(dip))) 1116 #define SDEV2MPT(sd) (TRAN2MPT(SDEV2TRAN(sd))) 1117 #define PKT2MPT(pkt) (TRAN2MPT(PKT2TRAN(pkt))) 1118 1119 #define ADDR2MPT(ap) (TRAN2MPT(ADDR2TRAN(ap))) 1120 1121 #define POLL_TIMEOUT (2 * SCSI_POLL_TIMEOUT * 1000000) 1122 #define SHORT_POLL_TIMEOUT (1000000) /* in usec, about 1 secs */ 1123 #define MPTSAS_QUIESCE_TIMEOUT 1 /* 1 sec */ 1124 #define MPTSAS_PM_IDLE_TIMEOUT 60 /* 60 seconds */ 1125 1126 #define MPTSAS_GET_ISTAT(mpt) (ddi_get32((mpt)->m_datap, \ 1127 &(mpt)->m_reg->HostInterruptStatus)) 1128 1129 #define MPTSAS_SET_SIGP(P) \ 1130 ClrSetBits(mpt->m_devaddr + NREG_ISTAT, 0, NB_ISTAT_SIGP) 1131 1132 #define MPTSAS_RESET_SIGP(P) (void) ddi_get8(mpt->m_datap, \ 1133 (uint8_t *)(mpt->m_devaddr + NREG_CTEST2)) 1134 1135 #define MPTSAS_GET_INTCODE(P) (ddi_get32(mpt->m_datap, \ 1136 (uint32_t *)(mpt->m_devaddr + NREG_DSPS))) 1137 1138 1139 #define MPTSAS_START_CMD(mpt, req_desc_lo, req_desc_hi) \ 1140 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostLow,\ 1141 req_desc_lo);\ 1142 ddi_put32(mpt->m_datap, &mpt->m_reg->RequestDescriptorPostHigh,\ 1143 req_desc_hi); 1144 1145 #define INTPENDING(mpt) \ 1146 (MPTSAS_GET_ISTAT(mpt) & MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT) 1147 1148 /* 1149 * Mask all interrupts to disable 1150 */ 1151 #define MPTSAS_DISABLE_INTR(mpt) \ 1152 ddi_put32((mpt)->m_datap, &(mpt)->m_reg->HostInterruptMask, \ 1153 (MPI2_HIM_RIM | MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK)) 1154 1155 /* 1156 * Mask Doorbell and Reset interrupts to enable reply desc int. 1157 */ 1158 #define MPTSAS_ENABLE_INTR(mpt) \ 1159 ddi_put32(mpt->m_datap, &mpt->m_reg->HostInterruptMask, \ 1160 (MPI2_HIM_DIM | MPI2_HIM_RESET_IRQ_MASK)) 1161 1162 #define MPTSAS_GET_NEXT_REPLY(mpt, index) \ 1163 &((uint64_t *)(void *)mpt->m_post_queue)[index] 1164 1165 #define MPTSAS_GET_NEXT_FRAME(mpt, SMID) \ 1166 (mpt->m_req_frame + (mpt->m_req_frame_size * SMID)) 1167 1168 #define ClrSetBits32(hdl, reg, clr, set) \ 1169 ddi_put32(hdl, (reg), \ 1170 ((ddi_get32(mpt->m_datap, (reg)) & ~(clr)) | (set))) 1171 1172 #define ClrSetBits(reg, clr, set) \ 1173 ddi_put8(mpt->m_datap, (uint8_t *)(reg), \ 1174 ((ddi_get8(mpt->m_datap, (uint8_t *)(reg)) & ~(clr)) | (set))) 1175 1176 #define MPTSAS_WAITQ_RM(mpt, cmdp) \ 1177 if ((cmdp = mpt->m_waitq) != NULL) { \ 1178 /* If the queue is now empty fix the tail pointer */ \ 1179 if ((mpt->m_waitq = cmdp->cmd_linkp) == NULL) \ 1180 mpt->m_waitqtail = &mpt->m_waitq; \ 1181 cmdp->cmd_linkp = NULL; \ 1182 cmdp->cmd_queued = FALSE; \ 1183 } 1184 1185 #define MPTSAS_TX_WAITQ_RM(mpt, cmdp) \ 1186 if ((cmdp = mpt->m_tx_waitq) != NULL) { \ 1187 /* If the queue is now empty fix the tail pointer */ \ 1188 if ((mpt->m_tx_waitq = cmdp->cmd_linkp) == NULL) \ 1189 mpt->m_tx_waitqtail = &mpt->m_tx_waitq; \ 1190 cmdp->cmd_linkp = NULL; \ 1191 cmdp->cmd_queued = FALSE; \ 1192 } 1193 1194 /* 1195 * defaults for the global properties 1196 */ 1197 #define DEFAULT_SCSI_OPTIONS SCSI_OPTIONS_DR 1198 #define DEFAULT_TAG_AGE_LIMIT 2 1199 #define DEFAULT_WD_TICK 10 1200 1201 /* 1202 * invalid hostid. 1203 */ 1204 #define MPTSAS_INVALID_HOSTID -1 1205 1206 /* 1207 * Get/Set hostid from SCSI port configuration page 1208 */ 1209 #define MPTSAS_GET_HOST_ID(configuration) (configuration & 0xFF) 1210 #define MPTSAS_SET_HOST_ID(hostid) (hostid | ((1 << hostid) << 16)) 1211 1212 /* 1213 * Config space. 1214 */ 1215 #define MPTSAS_LATENCY_TIMER 0x40 1216 1217 /* 1218 * Offset to firmware version 1219 */ 1220 #define MPTSAS_FW_VERSION_OFFSET 9 1221 1222 /* 1223 * Offset and masks to get at the ProductId field 1224 */ 1225 #define MPTSAS_FW_PRODUCTID_OFFSET 8 1226 #define MPTSAS_FW_PRODUCTID_MASK 0xFFFF0000 1227 #define MPTSAS_FW_PRODUCTID_SHIFT 16 1228 1229 /* 1230 * Subsystem ID for HBAs. 1231 */ 1232 #define MPTSAS_HBA_SUBSYSTEM_ID 0x10C0 1233 #define MPTSAS_RHEA_SUBSYSTEM_ID 0x10B0 1234 1235 /* 1236 * reset delay tick 1237 */ 1238 #define MPTSAS_WATCH_RESET_DELAY_TICK 50 /* specified in milli seconds */ 1239 1240 /* 1241 * Ioc reset return values 1242 */ 1243 #define MPTSAS_RESET_FAIL -1 1244 #define MPTSAS_NO_RESET 0 1245 #define MPTSAS_SUCCESS_HARDRESET 1 1246 #define MPTSAS_SUCCESS_MUR 2 1247 1248 /* 1249 * throttle support. 1250 */ 1251 #define MAX_THROTTLE 32 1252 #define HOLD_THROTTLE 0 1253 #define DRAIN_THROTTLE -1 1254 #define QFULL_THROTTLE -2 1255 1256 /* 1257 * Passthrough/config request flags 1258 */ 1259 #define MPTSAS_DATA_ALLOCATED 0x0001 1260 #define MPTSAS_DATAOUT_ALLOCATED 0x0002 1261 #define MPTSAS_REQUEST_POOL_CMD 0x0004 1262 #define MPTSAS_ADDRESS_REPLY 0x0008 1263 #define MPTSAS_CMD_TIMEOUT 0x0010 1264 1265 /* 1266 * response code tlr flag 1267 */ 1268 #define MPTSAS_SCSI_RESPONSE_CODE_TLR_OFF 0x02 1269 1270 /* 1271 * System Events 1272 */ 1273 #ifndef DDI_VENDOR_LSI 1274 #define DDI_VENDOR_LSI "LSI" 1275 #endif /* DDI_VENDOR_LSI */ 1276 1277 /* 1278 * Shared functions 1279 */ 1280 int mptsas_save_cmd(struct mptsas *mpt, struct mptsas_cmd *cmd); 1281 void mptsas_remove_cmd(mptsas_t *mpt, mptsas_cmd_t *cmd); 1282 void mptsas_waitq_add(mptsas_t *mpt, mptsas_cmd_t *cmd); 1283 void mptsas_log(struct mptsas *mpt, int level, char *fmt, ...); 1284 int mptsas_poll(mptsas_t *mpt, mptsas_cmd_t *poll_cmd, int polltime); 1285 int mptsas_do_dma(mptsas_t *mpt, uint32_t size, int var, int (*callback)()); 1286 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action, 1287 uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber, 1288 uint8_t pageversion, uint8_t pagelength, uint32_t 1289 SGEflagslength, uint32_t SGEaddress32); 1290 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action, 1291 uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber, 1292 uint8_t pageversion, uint16_t extpagelength, 1293 uint32_t SGEflagslength, uint32_t SGEaddress32); 1294 int mptsas_update_flash(mptsas_t *mpt, caddr_t ptrbuffer, uint32_t size, 1295 uint8_t type, int mode); 1296 int mptsas_check_flash(mptsas_t *mpt, caddr_t origfile, uint32_t size, 1297 uint8_t type, int mode); 1298 int mptsas_download_firmware(); 1299 int mptsas_can_download_firmware(); 1300 int mptsas_dma_alloc(mptsas_t *mpt, mptsas_dma_alloc_state_t *dma_statep); 1301 void mptsas_dma_free(mptsas_dma_alloc_state_t *dma_statep); 1302 mptsas_phymask_t mptsas_physport_to_phymask(mptsas_t *mpt, uint8_t physport); 1303 void mptsas_fma_check(mptsas_t *mpt, mptsas_cmd_t *cmd); 1304 int mptsas_check_acc_handle(ddi_acc_handle_t handle); 1305 int mptsas_check_dma_handle(ddi_dma_handle_t handle); 1306 void mptsas_fm_ereport(mptsas_t *mpt, char *detail); 1307 int mptsas_dma_addr_create(mptsas_t *mpt, ddi_dma_attr_t dma_attr, 1308 ddi_dma_handle_t *dma_hdp, ddi_acc_handle_t *acc_hdp, caddr_t *dma_memp, 1309 uint32_t alloc_size, ddi_dma_cookie_t *cookiep); 1310 void mptsas_dma_addr_destroy(ddi_dma_handle_t *, ddi_acc_handle_t *); 1311 1312 /* 1313 * impl functions 1314 */ 1315 int mptsas_ioc_wait_for_response(mptsas_t *mpt); 1316 int mptsas_ioc_wait_for_doorbell(mptsas_t *mpt); 1317 int mptsas_ioc_reset(mptsas_t *mpt, int); 1318 int mptsas_send_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes, 1319 ddi_acc_handle_t accessp); 1320 int mptsas_get_handshake_msg(mptsas_t *mpt, caddr_t memp, int numbytes, 1321 ddi_acc_handle_t accessp); 1322 int mptsas_send_config_request_msg(mptsas_t *mpt, uint8_t action, 1323 uint8_t pagetype, uint32_t pageaddress, uint8_t pagenumber, 1324 uint8_t pageversion, uint8_t pagelength, uint32_t SGEflagslength, 1325 uint32_t SGEaddress32); 1326 int mptsas_send_extended_config_request_msg(mptsas_t *mpt, uint8_t action, 1327 uint8_t extpagetype, uint32_t pageaddress, uint8_t pagenumber, 1328 uint8_t pageversion, uint16_t extpagelength, 1329 uint32_t SGEflagslength, uint32_t SGEaddress32); 1330 1331 int mptsas_request_from_pool(mptsas_t *mpt, mptsas_cmd_t **cmd, 1332 struct scsi_pkt **pkt); 1333 void mptsas_return_to_pool(mptsas_t *mpt, mptsas_cmd_t *cmd); 1334 void mptsas_destroy_ioc_event_cmd(mptsas_t *mpt); 1335 void mptsas_start_config_page_access(mptsas_t *mpt, mptsas_cmd_t *cmd); 1336 int mptsas_access_config_page(mptsas_t *mpt, uint8_t action, uint8_t page_type, 1337 uint8_t page_number, uint32_t page_address, int (*callback) (mptsas_t *, 1338 caddr_t, ddi_acc_handle_t, uint16_t, uint32_t, va_list), ...); 1339 1340 int mptsas_ioc_task_management(mptsas_t *mpt, int task_type, 1341 uint16_t dev_handle, int lun, uint8_t *reply, uint32_t reply_size, 1342 int mode); 1343 int mptsas_send_event_ack(mptsas_t *mpt, uint32_t event, uint32_t eventcntx); 1344 void mptsas_send_pending_event_ack(mptsas_t *mpt); 1345 void mptsas_set_throttle(struct mptsas *mpt, mptsas_target_t *ptgt, int what); 1346 int mptsas_restart_ioc(mptsas_t *mpt); 1347 void mptsas_update_driver_data(struct mptsas *mpt); 1348 uint64_t mptsas_get_sata_guid(mptsas_t *mpt, mptsas_target_t *ptgt, int lun); 1349 1350 /* 1351 * init functions 1352 */ 1353 int mptsas_ioc_get_facts(mptsas_t *mpt); 1354 int mptsas_ioc_get_port_facts(mptsas_t *mpt, int port); 1355 int mptsas_ioc_enable_port(mptsas_t *mpt); 1356 int mptsas_ioc_enable_event_notification(mptsas_t *mpt); 1357 int mptsas_ioc_init(mptsas_t *mpt); 1358 1359 /* 1360 * configuration pages operation 1361 */ 1362 int mptsas_get_sas_device_page0(mptsas_t *mpt, uint32_t page_address, 1363 uint16_t *dev_handle, uint64_t *sas_wwn, uint32_t *dev_info, 1364 uint8_t *physport, uint8_t *phynum, uint16_t *pdevhandle, 1365 uint16_t *slot_num, uint16_t *enclosure); 1366 int mptsas_get_sas_io_unit_page(mptsas_t *mpt); 1367 int mptsas_get_sas_io_unit_page_hndshk(mptsas_t *mpt); 1368 int mptsas_get_sas_expander_page0(mptsas_t *mpt, uint32_t page_address, 1369 mptsas_smp_t *info); 1370 int mptsas_set_ioc_params(mptsas_t *mpt); 1371 int mptsas_get_manufacture_page5(mptsas_t *mpt); 1372 int mptsas_get_sas_port_page0(mptsas_t *mpt, uint32_t page_address, 1373 uint64_t *sas_wwn, uint8_t *portwidth); 1374 int mptsas_get_bios_page3(mptsas_t *mpt, uint32_t *bios_version); 1375 int 1376 mptsas_get_sas_phy_page0(mptsas_t *mpt, uint32_t page_address, 1377 smhba_info_t *info); 1378 int 1379 mptsas_get_sas_phy_page1(mptsas_t *mpt, uint32_t page_address, 1380 smhba_info_t *info); 1381 int 1382 mptsas_get_manufacture_page0(mptsas_t *mpt); 1383 void 1384 mptsas_create_phy_stats(mptsas_t *mpt, char *iport, dev_info_t *dip); 1385 void mptsas_destroy_phy_stats(mptsas_t *mpt); 1386 int mptsas_smhba_phy_init(mptsas_t *mpt); 1387 /* 1388 * RAID functions 1389 */ 1390 int mptsas_get_raid_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol); 1391 int mptsas_get_raid_info(mptsas_t *mpt); 1392 int mptsas_get_physdisk_settings(mptsas_t *mpt, mptsas_raidvol_t *raidvol, 1393 uint8_t physdisknum); 1394 int mptsas_delete_volume(mptsas_t *mpt, uint16_t volid); 1395 void mptsas_raid_action_system_shutdown(mptsas_t *mpt); 1396 1397 #define MPTSAS_IOCSTATUS(status) (status & MPI2_IOCSTATUS_MASK) 1398 /* 1399 * debugging. 1400 */ 1401 #if defined(MPTSAS_DEBUG) 1402 1403 void mptsas_printf(char *fmt, ...); 1404 1405 #define MPTSAS_DBGPR(m, args) \ 1406 if (mptsas_debug_flags & (m)) \ 1407 mptsas_printf args 1408 #else /* ! defined(MPTSAS_DEBUG) */ 1409 #define MPTSAS_DBGPR(m, args) 1410 #endif /* defined(MPTSAS_DEBUG) */ 1411 1412 #define NDBG0(args) MPTSAS_DBGPR(0x01, args) /* init */ 1413 #define NDBG1(args) MPTSAS_DBGPR(0x02, args) /* normal running */ 1414 #define NDBG2(args) MPTSAS_DBGPR(0x04, args) /* property handling */ 1415 #define NDBG3(args) MPTSAS_DBGPR(0x08, args) /* pkt handling */ 1416 1417 #define NDBG4(args) MPTSAS_DBGPR(0x10, args) /* kmem alloc/free */ 1418 #define NDBG5(args) MPTSAS_DBGPR(0x20, args) /* polled cmds */ 1419 #define NDBG6(args) MPTSAS_DBGPR(0x40, args) /* interrupts */ 1420 #define NDBG7(args) MPTSAS_DBGPR(0x80, args) /* queue handling */ 1421 1422 #define NDBG8(args) MPTSAS_DBGPR(0x0100, args) /* arq */ 1423 #define NDBG9(args) MPTSAS_DBGPR(0x0200, args) /* Tagged Q'ing */ 1424 #define NDBG10(args) MPTSAS_DBGPR(0x0400, args) /* halting chip */ 1425 #define NDBG11(args) MPTSAS_DBGPR(0x0800, args) /* power management */ 1426 1427 #define NDBG12(args) MPTSAS_DBGPR(0x1000, args) /* enumeration */ 1428 #define NDBG13(args) MPTSAS_DBGPR(0x2000, args) /* configuration page */ 1429 #define NDBG14(args) MPTSAS_DBGPR(0x4000, args) /* LED control */ 1430 #define NDBG15(args) MPTSAS_DBGPR(0x8000, args) 1431 1432 #define NDBG16(args) MPTSAS_DBGPR(0x010000, args) 1433 #define NDBG17(args) MPTSAS_DBGPR(0x020000, args) /* scatter/gather */ 1434 #define NDBG18(args) MPTSAS_DBGPR(0x040000, args) 1435 #define NDBG19(args) MPTSAS_DBGPR(0x080000, args) /* handshaking */ 1436 1437 #define NDBG20(args) MPTSAS_DBGPR(0x100000, args) /* events */ 1438 #define NDBG21(args) MPTSAS_DBGPR(0x200000, args) /* dma */ 1439 #define NDBG22(args) MPTSAS_DBGPR(0x400000, args) /* reset */ 1440 #define NDBG23(args) MPTSAS_DBGPR(0x800000, args) /* abort */ 1441 1442 #define NDBG24(args) MPTSAS_DBGPR(0x1000000, args) /* capabilities */ 1443 #define NDBG25(args) MPTSAS_DBGPR(0x2000000, args) /* flushing */ 1444 #define NDBG26(args) MPTSAS_DBGPR(0x4000000, args) 1445 #define NDBG27(args) MPTSAS_DBGPR(0x8000000, args) 1446 1447 #define NDBG28(args) MPTSAS_DBGPR(0x10000000, args) /* hotplug */ 1448 #define NDBG29(args) MPTSAS_DBGPR(0x20000000, args) /* timeouts */ 1449 #define NDBG30(args) MPTSAS_DBGPR(0x40000000, args) /* mptsas_watch */ 1450 #define NDBG31(args) MPTSAS_DBGPR(0x80000000, args) /* negotations */ 1451 1452 /* 1453 * auto request sense 1454 */ 1455 #define RQ_MAKECOM_COMMON(pkt, flag, cmd) \ 1456 (pkt)->pkt_flags = (flag), \ 1457 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_cmd = (cmd), \ 1458 ((union scsi_cdb *)(pkt)->pkt_cdbp)->scc_lun = \ 1459 (pkt)->pkt_address.a_lun 1460 1461 #define RQ_MAKECOM_G0(pkt, flag, cmd, addr, cnt) \ 1462 RQ_MAKECOM_COMMON((pkt), (flag), (cmd)), \ 1463 FORMG0ADDR(((union scsi_cdb *)(pkt)->pkt_cdbp), (addr)), \ 1464 FORMG0COUNT(((union scsi_cdb *)(pkt)->pkt_cdbp), (cnt)) 1465 1466 1467 #ifdef __cplusplus 1468 } 1469 #endif 1470 1471 #endif /* _SYS_SCSI_ADAPTERS_MPTVAR_H */ 1472