10e751525SEric Saxe /* 20e751525SEric Saxe * CDDL HEADER START 30e751525SEric Saxe * 40e751525SEric Saxe * The contents of this file are subject to the terms of the 50e751525SEric Saxe * Common Development and Distribution License (the "License"). 60e751525SEric Saxe * You may not use this file except in compliance with the License. 70e751525SEric Saxe * 80e751525SEric Saxe * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 90e751525SEric Saxe * or http://www.opensolaris.org/os/licensing. 100e751525SEric Saxe * See the License for the specific language governing permissions 110e751525SEric Saxe * and limitations under the License. 120e751525SEric Saxe * 130e751525SEric Saxe * When distributing Covered Code, include this CDDL HEADER in each 140e751525SEric Saxe * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 150e751525SEric Saxe * If applicable, add the following below this CDDL HEADER, with the 160e751525SEric Saxe * fields enclosed by brackets "[]" replaced with your own identifying 170e751525SEric Saxe * information: Portions Copyright [yyyy] [name of copyright owner] 180e751525SEric Saxe * 190e751525SEric Saxe * CDDL HEADER END 200e751525SEric Saxe */ 210e751525SEric Saxe /* 220e751525SEric Saxe * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 230e751525SEric Saxe * Use is subject to license terms. 240e751525SEric Saxe */ 25cef70d2cSBill Holler /* 26cef70d2cSBill Holler * Copyright (c) 2009, Intel Corporation. 27cef70d2cSBill Holler * All rights reserved. 28cef70d2cSBill Holler */ 290e751525SEric Saxe 300e751525SEric Saxe #ifndef _CPUIDLE_H 310e751525SEric Saxe #define _CPUIDLE_H 320e751525SEric Saxe 330e751525SEric Saxe #include <sys/cpupm.h> 34*fb2caebeSRandy Fishel #include <sys/cpu.h> 350e751525SEric Saxe 360e751525SEric Saxe #ifdef __cplusplus 370e751525SEric Saxe extern "C" { 380e751525SEric Saxe #endif 390e751525SEric Saxe #define CPU_MAX_CSTATES 8 400e751525SEric Saxe 41*fb2caebeSRandy Fishel #define CPU_ACPI_C0 IDLE_STATE_C0 42*fb2caebeSRandy Fishel #define CPU_ACPI_C1 IDLE_STATE_C1 43*fb2caebeSRandy Fishel #define CPU_ACPI_C2 IDLE_STATE_C2 44*fb2caebeSRandy Fishel #define CPU_ACPI_C3 IDLE_STATE_C3 450e751525SEric Saxe 460e751525SEric Saxe #define BM_CTL 0x1 470e751525SEric Saxe #define BM_RLD 0x2 480e751525SEric Saxe #define BM_ARB_DIS 0x4 490e751525SEric Saxe 500e751525SEric Saxe #define CPUID_TSC_INVARIANCE 0x100 510e751525SEric Saxe 520e751525SEric Saxe #define CPU_IDLE_DEEP_CFG (0x1) /* Deep Idle disabled by user */ 530e751525SEric Saxe #define CPU_IDLE_CPR_CFG (0x2) /* In CPR */ 540e751525SEric Saxe 550e751525SEric Saxe typedef struct cpu_idle_kstat_s { 560e751525SEric Saxe struct kstat_named addr_space_id; /* register address space id */ 570e751525SEric Saxe struct kstat_named cs_latency; /* worst latency */ 580e751525SEric Saxe struct kstat_named cs_power; /* average power consumption */ 590e751525SEric Saxe } cpu_idle_kstat_t; 600e751525SEric Saxe 610e751525SEric Saxe extern cpupm_state_ops_t cpu_idle_ops; 620e751525SEric Saxe 630e751525SEric Saxe extern void cpu_acpi_idle(void); 640e751525SEric Saxe extern void cstate_wakeup(cpu_t *, int); 650e751525SEric Saxe extern boolean_t cpu_deep_cstates_supported(void); 660e751525SEric Saxe extern void cpu_wakeup(cpu_t *, int); 670e751525SEric Saxe extern void cpu_wakeup_mwait(cpu_t *, int); 680e751525SEric Saxe extern void cpuidle_manage_cstates(void *); 69cef70d2cSBill Holler extern boolean_t cstate_timer_callback(int code); 700e751525SEric Saxe 710e751525SEric Saxe #ifdef __cplusplus 720e751525SEric Saxe } 730e751525SEric Saxe #endif 740e751525SEric Saxe 750e751525SEric Saxe #endif /* _CPUIDLE_H */ 76