1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #include <sys/types.h> 28 #include <sys/modctl.h> 29 #include <sys/debug.h> 30 #include <sys/promif.h> 31 #include <sys/pci.h> 32 #include <sys/errno.h> 33 #include <sys/open.h> 34 #include <sys/uio.h> 35 #include <sys/cred.h> 36 #include <sys/cpu.h> 37 #include "ata_common.h" 38 #include "ata_disk.h" 39 #include "atapi.h" 40 #include "ata_blacklist.h" 41 #include "sil3xxx.h" 42 43 /* 44 * Solaris Entry Points. 45 */ 46 47 static int ata_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 48 static int ata_detach(dev_info_t *dip, ddi_detach_cmd_t cmd); 49 static int ata_bus_ctl(dev_info_t *d, dev_info_t *r, ddi_ctl_enum_t o, 50 void *a, void *v); 51 static uint_t ata_intr(caddr_t arg); 52 53 /* 54 * GHD Entry points 55 */ 56 57 static int ata_get_status(void *hba_handle, void *intr_status); 58 static void ata_process_intr(void *hba_handle, void *intr_status); 59 static int ata_hba_start(void *handle, gcmd_t *gcmdp); 60 static void ata_hba_complete(void *handle, gcmd_t *gcmdp, int do_callback); 61 static int ata_timeout_func(void *hba_handle, gcmd_t *gcmdp, 62 gtgt_t *gtgtp, gact_t action, int calltype); 63 64 /* 65 * Local Function Prototypes 66 */ 67 static int ata_prop_lookup_int(dev_t match_dev, dev_info_t *dip, 68 uint_t flags, char *name, int defvalue); 69 static int ata_ctlr_fsm(uchar_t fsm_func, ata_ctl_t *ata_ctlp, 70 ata_drv_t *ata_drvp, ata_pkt_t *ata_pktp, 71 int *DoneFlgp); 72 static void ata_destroy_controller(dev_info_t *dip); 73 static int ata_drive_type(uchar_t drvhd, 74 ddi_acc_handle_t io_hdl1, caddr_t ioaddr1, 75 ddi_acc_handle_t io_hdl2, caddr_t ioaddr2, 76 struct ata_id *ata_id_bufp); 77 static ata_ctl_t *ata_init_controller(dev_info_t *dip); 78 static ata_drv_t *ata_init_drive(ata_ctl_t *ata_ctlp, 79 uchar_t targ, uchar_t lun); 80 static int ata_init_drive_pcidma(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 81 dev_info_t *tdip); 82 static int ata_flush_cache(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp); 83 static void ata_init_pciide(dev_info_t *dip, ata_ctl_t *ata_ctlp); 84 static int ata_reset_bus(ata_ctl_t *ata_ctlp); 85 static int ata_setup_ioaddr(dev_info_t *dip, 86 ddi_acc_handle_t *iohandle1, caddr_t *ioaddr1p, 87 ddi_acc_handle_t *iohandle2, caddr_t *ioaddr2p, 88 ddi_acc_handle_t *bm_hdlp, caddr_t *bm_addrp); 89 static int ata_software_reset(ata_ctl_t *ata_ctlp); 90 static int ata_start_arq(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 91 ata_pkt_t *ata_pktp); 92 static int ata_strncmp(char *p1, char *p2, int cnt); 93 static void ata_uninit_drive(ata_drv_t *ata_drvp); 94 95 static int ata_check_pciide_blacklist(dev_info_t *dip, uint_t flags); 96 static int ata_check_revert_to_defaults(ata_drv_t *ata_drvp); 97 static void ata_show_transfer_mode(ata_ctl_t *, ata_drv_t *); 98 static int ata_spec_init_controller(dev_info_t *dip); 99 100 static void ata_init_pm(dev_info_t *); 101 static int ata_suspend(dev_info_t *); 102 static int ata_resume(dev_info_t *); 103 static int ata_power(dev_info_t *, int, int); 104 static int ata_change_power(dev_info_t *, uint8_t); 105 static int ata_is_pci(dev_info_t *); 106 static void ata_disable_DMA(ata_drv_t *ata_drvp); 107 static int ata_check_dma_mode(ata_drv_t *ata_drvp); 108 109 /* 110 * Local static data 111 */ 112 static void *ata_state; 113 114 static tmr_t ata_timer_conf; /* single timeout list for all instances */ 115 static int ata_watchdog_usec = 100000; /* check timeouts every 100 ms */ 116 117 int ata_hba_start_watchdog = 1000; 118 int ata_process_intr_watchdog = 1000; 119 int ata_reset_bus_watchdog = 1000; 120 121 122 /* 123 * Use local or framework power management 124 */ 125 126 #ifdef ATA_USE_AUTOPM 127 #define ATA_BUSY_COMPONENT(d, c) ((void)pm_busy_component(d, c)) 128 #define ATA_IDLE_COMPONENT(d, c) ((void)pm_idle_component(d, c)) 129 #define ATA_RAISE_POWER(d, c, l) pm_raise_power(d, c, l) 130 #define ATA_LOWER_POWER(d, c, l) pm_lower_power(d, c, l) 131 #else 132 #define ATA_BUSY_COMPONENT(d, c) 133 #define ATA_IDLE_COMPONENT(d, c) 134 #define ATA_RAISE_POWER(d, c, l) ata_power(d, c, l) 135 #define ATA_LOWER_POWER(d, c, l) ata_power(d, c, l) 136 #endif 137 /* 138 * number of seconds to wait during various operations 139 */ 140 int ata_flush_delay = 5 * 1000000; 141 uint_t ata_set_feature_wait = 4 * 1000000; 142 uint_t ata_flush_cache_wait = 60 * 1000000; /* may take a long time */ 143 144 /* 145 * Change this for SFF-8070i support. Currently SFF-8070i is 146 * using a field in the IDENTIFY PACKET DEVICE response which 147 * already seems to be in use by some vendor's drives. I suspect 148 * SFF will either move their laslun field or provide a reliable 149 * way to validate it. 150 */ 151 int ata_enable_atapi_luns = FALSE; 152 153 /* 154 * set this to disable all DMA requests 155 */ 156 int ata_dma_disabled = FALSE; 157 158 /* 159 * set this to TRUE to enable storing the IDENTIFY DEVICE result in the 160 * "ata" or "atapi" property. 161 */ 162 int ata_id_debug = FALSE; 163 164 /* 165 * set this to TRUE to enable logging device-capability data 166 */ 167 int ata_capability_data = FALSE; 168 169 /* 170 * DMA selection message pointers 171 */ 172 char *ata_cntrl_DMA_sel_msg; 173 char *ata_dev_DMA_sel_msg; 174 175 /* 176 * bus nexus operations 177 */ 178 static struct bus_ops ata_bus_ops; 179 static struct bus_ops *scsa_bus_ops_p; 180 181 /* ARGSUSED */ 182 static int 183 ata_open(dev_t *devp, int flag, int otyp, cred_t *cred_p) 184 { 185 if (ddi_get_soft_state(ata_state, getminor(*devp)) == NULL) 186 return (ENXIO); 187 188 return (0); 189 } 190 191 /* 192 * The purpose of this function is to pass the ioaddress of the controller 193 * to the caller, specifically used for upgrade from pre-pciide 194 * to pciide nodes 195 */ 196 /* ARGSUSED */ 197 static int 198 ata_read(dev_t dev, struct uio *uio_p, cred_t *cred_p) 199 { 200 ata_ctl_t *ata_ctlp; 201 char buf[18]; 202 long len; 203 204 ata_ctlp = ddi_get_soft_state(ata_state, getminor(dev)); 205 206 if (ata_ctlp == NULL) 207 return (ENXIO); 208 209 (void) sprintf(buf, "%p\n", (void *) ata_ctlp->ac_ioaddr1); 210 211 len = strlen(buf) - uio_p->uio_offset; 212 len = min(uio_p->uio_resid, len); 213 if (len <= 0) 214 return (0); 215 216 return (uiomove((caddr_t)(buf + uio_p->uio_offset), len, 217 UIO_READ, uio_p)); 218 } 219 220 int 221 ata_devo_reset( 222 dev_info_t *dip, 223 ddi_reset_cmd_t cmd) 224 { 225 ata_ctl_t *ata_ctlp; 226 ata_drv_t *ata_drvp; 227 int instance; 228 int i; 229 int rc; 230 int flush_okay; 231 232 if (cmd != DDI_RESET_FORCE) 233 return (0); 234 235 instance = ddi_get_instance(dip); 236 ata_ctlp = ddi_get_soft_state(ata_state, instance); 237 238 if (!ata_ctlp) 239 return (0); 240 241 /* 242 * reset ATA drives and flush the write cache of any drives 243 */ 244 flush_okay = TRUE; 245 for (i = 0; i < ATA_MAXTARG; i++) { 246 if ((ata_drvp = CTL2DRV(ata_ctlp, i, 0)) == 0) 247 continue; 248 /* Don't revert to defaults for certain IBM drives */ 249 if ((ata_drvp->ad_flags & AD_DISK) != 0 && 250 ((ata_drvp->ad_flags & AD_NORVRT) == 0)) { 251 /* Enable revert to defaults when reset */ 252 (void) ata_set_feature(ata_ctlp, ata_drvp, 253 ATSF_ENA_REVPOD, 0); 254 } 255 256 /* 257 * skip flush cache if device type is cdrom 258 * 259 * notes: the structure definitions for ata_drvp->ad_id are 260 * defined for the ATA IDENTIFY_DEVICE, but if AD_ATAPI is set 261 * the struct holds data for the ATAPI IDENTIFY_PACKET_DEVICE 262 */ 263 if (!IS_CDROM(ata_drvp)) { 264 265 /* 266 * Try the ATA/ATAPI flush write cache command 267 */ 268 rc = ata_flush_cache(ata_ctlp, ata_drvp); 269 ADBG_WARN(("ata_flush_cache %s\n", 270 rc ? "okay" : "failed")); 271 272 if (!rc) 273 flush_okay = FALSE; 274 } 275 276 277 /* 278 * do something else if flush cache not supported 279 */ 280 } 281 282 /* 283 * just busy wait if any drive doesn't support FLUSH CACHE 284 */ 285 if (!flush_okay) 286 drv_usecwait(ata_flush_delay); 287 return (0); 288 } 289 290 /* 291 * quiesce(9E) entry point. 292 * 293 * This function is called when the system is single-threaded at high 294 * PIL with preemption disabled. Therefore, this function must not be 295 * blocked. 296 * 297 * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure. 298 * DDI_FAILURE indicates an error condition and should almost never happen. 299 */ 300 int 301 ata_quiesce(dev_info_t *dip) 302 { 303 #ifdef ATA_DEBUG 304 /* 305 * Turn off debugging 306 */ 307 ata_debug = 0; 308 #endif 309 310 return (ata_devo_reset(dip, DDI_RESET_FORCE)); 311 } 312 313 314 static struct cb_ops ata_cb_ops = { 315 ata_open, /* open */ 316 nulldev, /* close */ 317 nodev, /* strategy */ 318 nodev, /* print */ 319 nodev, /* dump */ 320 ata_read, /* read */ 321 nodev, /* write */ 322 nodev, /* ioctl */ 323 nodev, /* devmap */ 324 nodev, /* mmap */ 325 nodev, /* segmap */ 326 nochpoll, /* chpoll */ 327 ddi_prop_op, /* prop_op */ 328 NULL, /* stream info */ 329 D_MP, /* driver compatibility flag */ 330 CB_REV, /* cb_ops revision */ 331 nodev, /* aread */ 332 nodev /* awrite */ 333 }; 334 335 static struct dev_ops ata_ops = { 336 DEVO_REV, /* devo_rev, */ 337 0, /* refcnt */ 338 ddi_getinfo_1to1, /* info */ 339 nulldev, /* identify */ 340 NULL, /* probe */ 341 ata_attach, /* attach */ 342 ata_detach, /* detach */ 343 ata_devo_reset, /* reset */ 344 &ata_cb_ops, /* driver operations */ 345 NULL, /* bus operations */ 346 ata_power, /* power */ 347 ata_quiesce /* quiesce */ 348 }; 349 350 /* driver loadable module wrapper */ 351 static struct modldrv modldrv = { 352 &mod_driverops, /* Type of module. This one is a driver */ 353 "ATA AT-bus attachment disk controller Driver", /* module name */ 354 &ata_ops, /* driver ops */ 355 }; 356 357 static struct modlinkage modlinkage = { 358 MODREV_1, (void *)&modldrv, NULL 359 }; 360 361 #ifdef ATA_DEBUG 362 int ata_debug_init = FALSE; 363 int ata_debug_attach = FALSE; 364 365 int ata_debug = ADBG_FLAG_ERROR 366 /* | ADBG_FLAG_ARQ */ 367 /* | ADBG_FLAG_INIT */ 368 /* | ADBG_FLAG_TRACE */ 369 /* | ADBG_FLAG_TRANSPORT */ 370 /* | ADBG_FLAG_WARN */ 371 ; 372 #endif 373 374 int 375 _init(void) 376 { 377 int err; 378 379 #ifdef ATA_DEBUG 380 if (ata_debug_init) 381 debug_enter("\nATA _INIT\n"); 382 #endif 383 384 if ((err = ddi_soft_state_init(&ata_state, sizeof (ata_ctl_t), 0)) != 0) 385 return (err); 386 387 if ((err = scsi_hba_init(&modlinkage)) != 0) { 388 ddi_soft_state_fini(&ata_state); 389 return (err); 390 } 391 392 /* save pointer to SCSA provided bus_ops struct */ 393 scsa_bus_ops_p = ata_ops.devo_bus_ops; 394 395 /* make a copy of SCSA bus_ops */ 396 ata_bus_ops = *(ata_ops.devo_bus_ops); 397 398 /* 399 * Modify our bus_ops to call our routines. Our implementation 400 * will determine if the device is ATA or ATAPI/SCSA and react 401 * accordingly. 402 */ 403 ata_bus_ops.bus_ctl = ata_bus_ctl; 404 405 /* patch our bus_ops into the dev_ops struct */ 406 ata_ops.devo_bus_ops = &ata_bus_ops; 407 408 if ((err = mod_install(&modlinkage)) != 0) { 409 scsi_hba_fini(&modlinkage); 410 ddi_soft_state_fini(&ata_state); 411 } 412 413 /* 414 * Initialize the per driver timer info. 415 */ 416 417 ghd_timer_init(&ata_timer_conf, drv_usectohz(ata_watchdog_usec)); 418 419 return (err); 420 } 421 422 int 423 _fini(void) 424 { 425 int err; 426 427 if ((err = mod_remove(&modlinkage)) == 0) { 428 ghd_timer_fini(&ata_timer_conf); 429 scsi_hba_fini(&modlinkage); 430 ddi_soft_state_fini(&ata_state); 431 } 432 433 return (err); 434 } 435 436 int 437 _info(struct modinfo *modinfop) 438 { 439 return (mod_info(&modlinkage, modinfop)); 440 } 441 442 443 /* 444 * 445 * driver attach entry point 446 * 447 */ 448 449 static int 450 ata_attach( 451 dev_info_t *dip, 452 ddi_attach_cmd_t cmd) 453 { 454 ata_ctl_t *ata_ctlp; 455 ata_drv_t *ata_drvp; 456 ata_drv_t *first_drvp = NULL; 457 uchar_t targ; 458 uchar_t lun; 459 uchar_t lastlun; 460 int atapi_count = 0; 461 int disk_count = 0; 462 463 ADBG_TRACE(("ata_attach entered\n")); 464 #ifdef ATA_DEBUG 465 if (ata_debug_attach) 466 debug_enter("\nATA_ATTACH\n\n"); 467 #endif 468 469 switch (cmd) { 470 case DDI_ATTACH: 471 break; 472 case DDI_RESUME: 473 return (ata_resume(dip)); 474 default: 475 return (DDI_FAILURE); 476 } 477 478 /* initialize controller */ 479 ata_ctlp = ata_init_controller(dip); 480 481 if (ata_ctlp == NULL) 482 goto errout; 483 484 mutex_enter(&ata_ctlp->ac_ccc.ccc_hba_mutex); 485 486 /* initialize drives */ 487 488 for (targ = 0; targ < ATA_MAXTARG; targ++) { 489 490 ata_drvp = ata_init_drive(ata_ctlp, targ, 0); 491 if (ata_drvp == NULL) 492 continue; 493 494 if (first_drvp == NULL) 495 first_drvp = ata_drvp; 496 497 if (ATAPIDRV(ata_drvp)) { 498 atapi_count++; 499 lastlun = ata_drvp->ad_id.ai_lastlun; 500 } else { 501 disk_count++; 502 lastlun = 0; 503 } 504 505 /* 506 * LUN support is currently disabled. Check with SFF-8070i 507 * before enabling. 508 */ 509 if (!ata_enable_atapi_luns) 510 lastlun = 0; 511 512 /* Initialize higher LUNs, if there are any */ 513 for (lun = 1; lun <= lastlun && lun < ATA_MAXLUN; lun++) { 514 if ((ata_drvp = 515 ata_init_drive(ata_ctlp, targ, lun)) != NULL) { 516 ata_show_transfer_mode(ata_ctlp, ata_drvp); 517 } 518 } 519 } 520 521 if ((atapi_count == 0) && (disk_count == 0)) { 522 ADBG_WARN(("ata_attach: no drives detected\n")); 523 goto errout1; 524 } 525 526 /* 527 * Always make certain that a valid drive is selected so 528 * that routines which poll the status register don't get 529 * confused by non-existent drives. 530 */ 531 ddi_put8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_drvhd, 532 first_drvp->ad_drive_bits); 533 ata_nsecwait(400); 534 535 /* 536 * make certain the drive selected 537 */ 538 if (!ata_wait(ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2, 539 0, ATS_BSY, 5000000)) { 540 ADBG_ERROR(("ata_attach: select failed\n")); 541 } 542 543 /* 544 * initialize atapi/ata_dsk modules if we have at least 545 * one drive of that type. 546 */ 547 548 if (atapi_count) { 549 if (!atapi_attach(ata_ctlp)) 550 goto errout1; 551 ata_ctlp->ac_flags |= AC_ATAPI_INIT; 552 } 553 554 if (disk_count) { 555 if (!ata_disk_attach(ata_ctlp)) 556 goto errout1; 557 ata_ctlp->ac_flags |= AC_DISK_INIT; 558 } 559 560 /* 561 * make certain the interrupt and error latches are clear 562 */ 563 if (ata_ctlp->ac_pciide) { 564 565 int instance = ddi_get_instance(dip); 566 if (ddi_create_minor_node(dip, "control", S_IFCHR, instance, 567 DDI_PSEUDO, 0) != DDI_SUCCESS) { 568 goto errout1; 569 } 570 571 (void) ata_pciide_status_clear(ata_ctlp); 572 573 } 574 575 /* 576 * enable the interrupt handler and drop the mutex 577 */ 578 ata_ctlp->ac_flags |= AC_ATTACHED; 579 mutex_exit(&ata_ctlp->ac_ccc.ccc_hba_mutex); 580 581 ata_init_pm(dip); 582 583 ddi_report_dev(dip); 584 return (DDI_SUCCESS); 585 586 errout1: 587 mutex_exit(&ata_ctlp->ac_ccc.ccc_hba_mutex); 588 errout: 589 (void) ata_detach(dip, DDI_DETACH); 590 return (DDI_FAILURE); 591 } 592 593 /* driver detach entry point */ 594 595 static int 596 ata_detach( 597 dev_info_t *dip, 598 ddi_detach_cmd_t cmd) 599 { 600 ata_ctl_t *ata_ctlp; 601 ata_drv_t *ata_drvp; 602 int instance; 603 int i; 604 int j; 605 606 ADBG_TRACE(("ata_detach entered\n")); 607 608 switch (cmd) { 609 case DDI_DETACH: 610 break; 611 case DDI_SUSPEND: 612 return (ata_suspend(dip)); 613 default: 614 return (DDI_FAILURE); 615 } 616 617 instance = ddi_get_instance(dip); 618 ata_ctlp = ddi_get_soft_state(ata_state, instance); 619 620 if (!ata_ctlp) 621 return (DDI_SUCCESS); 622 623 if (ata_ctlp->ac_pm_support) { 624 ATA_BUSY_COMPONENT(dip, 0); 625 if (ata_ctlp->ac_pm_level != PM_LEVEL_D0) { 626 if (ATA_RAISE_POWER(dip, 0, PM_LEVEL_D0) != 627 DDI_SUCCESS) { 628 ATA_IDLE_COMPONENT(dip, 0); 629 return (DDI_FAILURE); 630 } 631 } 632 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "pm-components"); 633 } 634 ata_ctlp->ac_flags &= ~AC_ATTACHED; 635 636 /* destroy ata module */ 637 if (ata_ctlp->ac_flags & AC_DISK_INIT) 638 ata_disk_detach(ata_ctlp); 639 640 /* destroy atapi module */ 641 if (ata_ctlp->ac_flags & AC_ATAPI_INIT) 642 atapi_detach(ata_ctlp); 643 644 ddi_remove_minor_node(dip, NULL); 645 646 /* destroy drives */ 647 for (i = 0; i < ATA_MAXTARG; i++) { 648 for (j = 0; j < ATA_MAXLUN; j++) { 649 ata_drvp = CTL2DRV(ata_ctlp, i, j); 650 if (ata_drvp != NULL) 651 ata_uninit_drive(ata_drvp); 652 } 653 } 654 655 if (ata_ctlp->ac_iohandle1) 656 ddi_regs_map_free(&ata_ctlp->ac_iohandle1); 657 if (ata_ctlp->ac_iohandle2) 658 ddi_regs_map_free(&ata_ctlp->ac_iohandle2); 659 if (ata_ctlp->ac_bmhandle) 660 ddi_regs_map_free(&ata_ctlp->ac_bmhandle); 661 662 /* destroy controller */ 663 ata_destroy_controller(dip); 664 665 ddi_prop_remove_all(dip); 666 667 return (DDI_SUCCESS); 668 } 669 670 /* 671 * Nexus driver bus_ctl entry point 672 */ 673 /*ARGSUSED*/ 674 static int 675 ata_bus_ctl( 676 dev_info_t *d, 677 dev_info_t *r, 678 ddi_ctl_enum_t o, 679 void *a, 680 void *v) 681 { 682 dev_info_t *tdip; 683 int target_type; 684 int rc; 685 char *bufp; 686 687 ADBG_TRACE(("ata_bus_ctl entered\n")); 688 689 switch (o) { 690 691 case DDI_CTLOPS_SIDDEV: 692 return (DDI_FAILURE); 693 694 case DDI_CTLOPS_IOMIN: 695 696 /* 697 * Since we use PIO, we return a minimum I/O size of 698 * one byte. This will need to be updated when we 699 * implement DMA support 700 */ 701 702 *((int *)v) = 1; 703 return (DDI_SUCCESS); 704 705 case DDI_CTLOPS_DMAPMAPC: 706 case DDI_CTLOPS_REPORTINT: 707 case DDI_CTLOPS_REGSIZE: 708 case DDI_CTLOPS_NREGS: 709 case DDI_CTLOPS_SLAVEONLY: 710 case DDI_CTLOPS_AFFINITY: 711 case DDI_CTLOPS_POKE: 712 case DDI_CTLOPS_PEEK: 713 714 /* These ops shouldn't be called by a target driver */ 715 ADBG_ERROR(("ata_bus_ctl: %s%d: invalid op (%d) from %s%d\n", 716 ddi_driver_name(d), ddi_get_instance(d), o, 717 ddi_driver_name(r), ddi_get_instance(r))); 718 719 return (DDI_FAILURE); 720 721 case DDI_CTLOPS_REPORTDEV: 722 case DDI_CTLOPS_INITCHILD: 723 case DDI_CTLOPS_UNINITCHILD: 724 725 /* these require special handling below */ 726 break; 727 728 default: 729 return (ddi_ctlops(d, r, o, a, v)); 730 } 731 732 /* get targets dip */ 733 734 if (o == DDI_CTLOPS_INITCHILD || o == DDI_CTLOPS_UNINITCHILD) 735 tdip = (dev_info_t *)a; 736 else 737 tdip = r; 738 739 /* 740 * XXX - Get class of target 741 * Before the "class" entry in a conf file becomes 742 * a real property, we use an additional property 743 * tentatively called "class_prop". We will require that 744 * new classes (ie. direct) export "class_prop". 745 * SCSA target drivers will not have this property, so 746 * no property implies SCSA. 747 */ 748 if ((ddi_prop_lookup_string(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 749 "class", &bufp) == DDI_PROP_SUCCESS) || 750 (ddi_prop_lookup_string(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 751 "class_prop", &bufp) == DDI_PROP_SUCCESS)) { 752 if (strcmp(bufp, "dada") == 0) 753 target_type = ATA_DEV_DISK; 754 else if (strcmp(bufp, "scsi") == 0) 755 target_type = ATA_DEV_ATAPI; 756 else { 757 ADBG_WARN(("ata_bus_ctl: invalid target class %s\n", 758 bufp)); 759 ddi_prop_free(bufp); 760 return (DDI_FAILURE); 761 } 762 ddi_prop_free(bufp); 763 } else { 764 target_type = ATA_DEV_ATAPI; /* no class prop, assume SCSI */ 765 } 766 767 if (o == DDI_CTLOPS_INITCHILD) { 768 int instance = ddi_get_instance(d); 769 ata_ctl_t *ata_ctlp = ddi_get_soft_state(ata_state, instance); 770 ata_drv_t *ata_drvp; 771 int targ; 772 int lun; 773 int drive_type; 774 char *disk_prop; 775 char *class_prop; 776 777 if (ata_ctlp == NULL) { 778 ADBG_WARN(("ata_bus_ctl: failed to find ctl struct\n")); 779 return (DDI_FAILURE); 780 } 781 782 /* get (target,lun) of child device */ 783 784 targ = ddi_prop_get_int(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 785 "target", -1); 786 if (targ == -1) { 787 ADBG_WARN(("ata_bus_ctl: failed to get targ num\n")); 788 return (DDI_FAILURE); 789 } 790 791 lun = ddi_prop_get_int(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 792 "lun", 0); 793 794 if ((targ < 0) || (targ >= ATA_MAXTARG) || 795 (lun < 0) || (lun >= ATA_MAXLUN)) { 796 return (DDI_FAILURE); 797 } 798 799 ata_drvp = CTL2DRV(ata_ctlp, targ, lun); 800 801 if (ata_drvp == NULL) 802 return (DDI_FAILURE); /* no drive */ 803 804 /* get type of device */ 805 806 if (ATAPIDRV(ata_drvp)) 807 drive_type = ATA_DEV_ATAPI; 808 else 809 drive_type = ATA_DEV_DISK; 810 811 /* 812 * Check for special handling when child driver is 813 * cmdk (which morphs to the correct interface) 814 */ 815 if (strcmp(ddi_get_name(tdip), "cmdk") == 0) { 816 817 if ((target_type == ATA_DEV_DISK) && 818 (target_type != drive_type)) 819 return (DDI_FAILURE); 820 821 target_type = drive_type; 822 823 if (drive_type == ATA_DEV_ATAPI) { 824 class_prop = "scsi"; 825 } else { 826 disk_prop = "dadk"; 827 class_prop = "dada"; 828 829 if (ndi_prop_update_string(DDI_DEV_T_NONE, tdip, 830 "disk", disk_prop) != DDI_PROP_SUCCESS) { 831 ADBG_WARN(("ata_bus_ctl: failed to " 832 "create disk prop\n")); 833 return (DDI_FAILURE); 834 } 835 } 836 837 if (ndi_prop_update_string(DDI_DEV_T_NONE, tdip, 838 "class_prop", class_prop) != DDI_PROP_SUCCESS) { 839 ADBG_WARN(("ata_bus_ctl: failed to " 840 "create class prop\n")); 841 return (DDI_FAILURE); 842 } 843 } 844 845 /* Check that target class matches the device */ 846 847 if (target_type != drive_type) 848 return (DDI_FAILURE); 849 850 /* save pointer to drive struct for ata_disk_bus_ctl */ 851 ddi_set_driver_private(tdip, ata_drvp); 852 853 /* 854 * Determine whether to enable DMA support for this drive. This 855 * check is deferred to this point so that the various dma 856 * properties could reside on the devinfo node should finer 857 * grained dma control be required. 858 */ 859 if (ata_drvp->ad_pciide_dma == ATA_DMA_UNINITIALIZED) { 860 ata_drvp->ad_pciide_dma = 861 ata_init_drive_pcidma(ata_ctlp, ata_drvp, tdip); 862 ata_show_transfer_mode(ata_ctlp, ata_drvp); 863 } 864 } 865 866 if (target_type == ATA_DEV_ATAPI) { 867 rc = scsa_bus_ops_p->bus_ctl(d, r, o, a, v); 868 } else { 869 rc = ata_disk_bus_ctl(d, r, o, a, v); 870 } 871 872 return (rc); 873 } 874 875 /* 876 * 877 * GHD ccc_hba_complete callback 878 * 879 */ 880 881 /* ARGSUSED */ 882 static void 883 ata_hba_complete( 884 void *hba_handle, 885 gcmd_t *gcmdp, 886 int do_callback) 887 { 888 ata_drv_t *ata_drvp; 889 ata_pkt_t *ata_pktp; 890 891 ADBG_TRACE(("ata_hba_complete entered\n")); 892 893 ata_drvp = GCMD2DRV(gcmdp); 894 ata_pktp = GCMD2APKT(gcmdp); 895 if (ata_pktp->ap_complete) 896 (*ata_pktp->ap_complete)(ata_drvp, ata_pktp, 897 do_callback); 898 } 899 900 /* GHD ccc_timeout_func callback */ 901 902 /* ARGSUSED */ 903 static int 904 ata_timeout_func( 905 void *hba_handle, 906 gcmd_t *gcmdp, 907 gtgt_t *gtgtp, 908 gact_t action, 909 int calltype) 910 { 911 ata_ctl_t *ata_ctlp; 912 ata_pkt_t *ata_pktp; 913 ata_drv_t *ata_drvp; 914 915 ADBG_TRACE(("ata_timeout_func entered\n")); 916 917 ata_ctlp = (ata_ctl_t *)hba_handle; 918 919 if (gcmdp != NULL) 920 ata_pktp = GCMD2APKT(gcmdp); 921 else 922 ata_pktp = NULL; 923 924 switch (action) { 925 case GACTION_EARLY_ABORT: 926 /* abort before request was started */ 927 if (ata_pktp != NULL) { 928 ata_pktp->ap_flags |= AP_ABORT; 929 } 930 ghd_complete(&ata_ctlp->ac_ccc, gcmdp); 931 return (TRUE); 932 933 case GACTION_EARLY_TIMEOUT: 934 /* timeout before request was started */ 935 if (ata_pktp != NULL) { 936 ata_pktp->ap_flags |= AP_TIMEOUT; 937 } 938 ghd_complete(&ata_ctlp->ac_ccc, gcmdp); 939 return (TRUE); 940 941 case GACTION_RESET_TARGET: 942 /* 943 * Reset a device is not supported. Resetting a specific 944 * device can't be done at all to an ATA device and if 945 * you send a RESET to an ATAPI device you have to 946 * reset the whole bus to make certain both devices 947 * on the bus stay in sync regarding which device is 948 * the currently selected one. 949 */ 950 return (FALSE); 951 952 case GACTION_RESET_BUS: 953 /* 954 * Issue bus reset and reinitialize both drives. 955 * But only if this is a timed-out request. Target 956 * driver reset requests are ignored because ATA 957 * and ATAPI devices shouldn't be gratuitously reset. 958 * Also disable DMA if it is a CF device. 959 */ 960 if (gcmdp == NULL) 961 break; 962 ata_drvp = GCMD2DRV(gcmdp); 963 if (ata_drvp != NULL) 964 if (ata_drvp->ad_id.ai_config == ATA_ID_CF_TO_ATA) 965 ata_disable_DMA(ata_drvp); 966 return (ata_reset_bus(ata_ctlp)); 967 default: 968 break; 969 } 970 return (FALSE); 971 } 972 973 /* 974 * 975 * Initialize controller's soft-state structure 976 * 977 */ 978 979 static ata_ctl_t * 980 ata_init_controller( 981 dev_info_t *dip) 982 { 983 ata_ctl_t *ata_ctlp; 984 int instance; 985 caddr_t ioaddr1; 986 caddr_t ioaddr2; 987 988 ADBG_TRACE(("ata_init_controller entered\n")); 989 990 instance = ddi_get_instance(dip); 991 992 /* allocate controller structure */ 993 if (ddi_soft_state_zalloc(ata_state, instance) != DDI_SUCCESS) { 994 ADBG_WARN(("ata_init_controller: soft_state_zalloc failed\n")); 995 return (NULL); 996 } 997 998 ata_ctlp = ddi_get_soft_state(ata_state, instance); 999 1000 if (ata_ctlp == NULL) { 1001 ADBG_WARN(("ata_init_controller: failed to find " 1002 "controller struct\n")); 1003 return (NULL); 1004 } 1005 1006 /* 1007 * initialize per-controller data 1008 */ 1009 ata_ctlp->ac_dip = dip; 1010 ata_ctlp->ac_arq_pktp = kmem_zalloc(sizeof (ata_pkt_t), KM_SLEEP); 1011 1012 /* 1013 * map the device registers 1014 */ 1015 if (!ata_setup_ioaddr(dip, &ata_ctlp->ac_iohandle1, &ioaddr1, 1016 &ata_ctlp->ac_iohandle2, &ioaddr2, 1017 &ata_ctlp->ac_bmhandle, &ata_ctlp->ac_bmaddr)) { 1018 (void) ata_detach(dip, DDI_DETACH); 1019 return (NULL); 1020 } 1021 1022 ADBG_INIT(("ata_init_controller: ioaddr1 = 0x%p, ioaddr2 = 0x%p\n", 1023 ioaddr1, ioaddr2)); 1024 1025 /* 1026 * Do ARQ setup 1027 */ 1028 atapi_init_arq(ata_ctlp); 1029 1030 /* 1031 * Do PCI-IDE setup 1032 */ 1033 ata_init_pciide(dip, ata_ctlp); 1034 1035 /* 1036 * port addresses associated with ioaddr1 1037 */ 1038 ata_ctlp->ac_ioaddr1 = ioaddr1; 1039 ata_ctlp->ac_data = (ushort_t *)ioaddr1 + AT_DATA; 1040 ata_ctlp->ac_error = (uchar_t *)ioaddr1 + AT_ERROR; 1041 ata_ctlp->ac_feature = (uchar_t *)ioaddr1 + AT_FEATURE; 1042 ata_ctlp->ac_count = (uchar_t *)ioaddr1 + AT_COUNT; 1043 ata_ctlp->ac_sect = (uchar_t *)ioaddr1 + AT_SECT; 1044 ata_ctlp->ac_lcyl = (uchar_t *)ioaddr1 + AT_LCYL; 1045 ata_ctlp->ac_hcyl = (uchar_t *)ioaddr1 + AT_HCYL; 1046 ata_ctlp->ac_drvhd = (uchar_t *)ioaddr1 + AT_DRVHD; 1047 ata_ctlp->ac_status = (uchar_t *)ioaddr1 + AT_STATUS; 1048 ata_ctlp->ac_cmd = (uchar_t *)ioaddr1 + AT_CMD; 1049 1050 /* 1051 * port addresses associated with ioaddr2 1052 */ 1053 ata_ctlp->ac_ioaddr2 = ioaddr2; 1054 ata_ctlp->ac_altstatus = (uchar_t *)ioaddr2 + AT_ALTSTATUS; 1055 ata_ctlp->ac_devctl = (uchar_t *)ioaddr2 + AT_DEVCTL; 1056 1057 /* 1058 * If AC_BSY_WAIT needs to be set for laptops that do 1059 * suspend/resume but do not correctly wait for the busy bit to 1060 * drop after a resume. 1061 */ 1062 ata_ctlp->ac_timing_flags = ddi_prop_get_int(DDI_DEV_T_ANY, 1063 dip, DDI_PROP_DONTPASS, "timing_flags", 0); 1064 /* 1065 * get max transfer size, default to 256 sectors 1066 */ 1067 ata_ctlp->ac_max_transfer = ddi_prop_get_int(DDI_DEV_T_ANY, 1068 dip, DDI_PROP_DONTPASS, "max_transfer", 0x100); 1069 if (ata_ctlp->ac_max_transfer < 1) 1070 ata_ctlp->ac_max_transfer = 1; 1071 if (ata_ctlp->ac_max_transfer > 0x100) 1072 ata_ctlp->ac_max_transfer = 0x100; 1073 1074 /* 1075 * Get the standby timer value 1076 */ 1077 ata_ctlp->ac_standby_time = ddi_prop_get_int(DDI_DEV_T_ANY, 1078 dip, DDI_PROP_DONTPASS, "standby", -1); 1079 1080 /* 1081 * If this is a /pci/pci-ide instance check to see if 1082 * it's supposed to be attached as an /isa/ata 1083 */ 1084 if (ata_ctlp->ac_pciide) { 1085 static char prop_buf[] = "SUNW-ata-ffff-isa"; 1086 int addr1 = (intptr_t)ioaddr1; 1087 1088 1089 if (addr1 < 0 || addr1 > 0xffff) { 1090 (void) ata_detach(dip, DDI_DETACH); 1091 return (NULL); 1092 } 1093 (void) sprintf(prop_buf, "SUNW-ata-%04x-isa", 1094 addr1); 1095 if (ddi_prop_exists(DDI_DEV_T_ANY, ddi_root_node(), 1096 DDI_PROP_DONTPASS, prop_buf)) { 1097 (void) ata_detach(dip, DDI_DETACH); 1098 return (NULL); 1099 } 1100 } 1101 1102 /* Init controller specific stuff */ 1103 (void) ata_spec_init_controller(dip); 1104 1105 /* 1106 * initialize GHD 1107 */ 1108 1109 GHD_WAITQ_INIT(&ata_ctlp->ac_ccc.ccc_waitq, NULL, 1); 1110 1111 if (!ghd_register("ata", &ata_ctlp->ac_ccc, dip, 0, ata_ctlp, 1112 atapi_ccballoc, atapi_ccbfree, 1113 ata_pciide_dma_sg_func, ata_hba_start, 1114 ata_hba_complete, ata_intr, 1115 ata_get_status, ata_process_intr, ata_timeout_func, 1116 &ata_timer_conf, NULL)) { 1117 (void) ata_detach(dip, DDI_DETACH); 1118 return (NULL); 1119 } 1120 1121 ata_ctlp->ac_flags |= AC_GHD_INIT; 1122 return (ata_ctlp); 1123 } 1124 1125 /* destroy a controller */ 1126 1127 static void 1128 ata_destroy_controller( 1129 dev_info_t *dip) 1130 { 1131 ata_ctl_t *ata_ctlp; 1132 int instance; 1133 1134 ADBG_TRACE(("ata_destroy_controller entered\n")); 1135 1136 instance = ddi_get_instance(dip); 1137 ata_ctlp = ddi_get_soft_state(ata_state, instance); 1138 1139 if (ata_ctlp == NULL) 1140 return; 1141 1142 /* destroy ghd */ 1143 if (ata_ctlp->ac_flags & AC_GHD_INIT) 1144 ghd_unregister(&ata_ctlp->ac_ccc); 1145 1146 /* free the pciide buffer (if any) */ 1147 ata_pciide_free(ata_ctlp); 1148 1149 /* destroy controller struct */ 1150 kmem_free(ata_ctlp->ac_arq_pktp, sizeof (ata_pkt_t)); 1151 ddi_soft_state_free(ata_state, instance); 1152 1153 } 1154 1155 1156 /* 1157 * 1158 * initialize a drive 1159 * 1160 */ 1161 1162 static ata_drv_t * 1163 ata_init_drive( 1164 ata_ctl_t *ata_ctlp, 1165 uchar_t targ, 1166 uchar_t lun) 1167 { 1168 static char nec_260[] = "NEC CD-ROM DRIVE"; 1169 ata_drv_t *ata_drvp; 1170 struct ata_id *aidp; 1171 char buf[80]; 1172 int drive_type; 1173 int i; 1174 int valid_version = 0; 1175 1176 ADBG_TRACE(("ata_init_drive entered, targ = %d, lun = %d\n", 1177 targ, lun)); 1178 1179 /* check if device already exists */ 1180 1181 ata_drvp = CTL2DRV(ata_ctlp, targ, lun); 1182 1183 if (ata_drvp != NULL) 1184 return (ata_drvp); 1185 1186 /* allocate new device structure */ 1187 1188 ata_drvp = kmem_zalloc(sizeof (ata_drv_t), KM_SLEEP); 1189 aidp = &ata_drvp->ad_id; 1190 1191 /* 1192 * set up drive struct 1193 */ 1194 ata_drvp->ad_ctlp = ata_ctlp; 1195 ata_drvp->ad_pciide_dma = ATA_DMA_UNINITIALIZED; 1196 ata_drvp->ad_targ = targ; 1197 ata_drvp->ad_drive_bits = 1198 (ata_drvp->ad_targ == 0 ? ATDH_DRIVE0 : ATDH_DRIVE1); 1199 /* 1200 * Add the LUN for SFF-8070i support 1201 */ 1202 ata_drvp->ad_lun = lun; 1203 ata_drvp->ad_drive_bits |= ata_drvp->ad_lun; 1204 1205 /* 1206 * get drive type, side effect is to collect 1207 * IDENTIFY DRIVE data 1208 */ 1209 1210 drive_type = ata_drive_type(ata_drvp->ad_drive_bits, 1211 ata_ctlp->ac_iohandle1, 1212 ata_ctlp->ac_ioaddr1, 1213 ata_ctlp->ac_iohandle2, 1214 ata_ctlp->ac_ioaddr2, 1215 aidp); 1216 1217 switch (drive_type) { 1218 case ATA_DEV_NONE: 1219 /* no drive found */ 1220 goto errout; 1221 case ATA_DEV_ATAPI: 1222 ata_drvp->ad_flags |= AD_ATAPI; 1223 break; 1224 case ATA_DEV_DISK: 1225 ata_drvp->ad_flags |= AD_DISK; 1226 break; 1227 } 1228 1229 /* 1230 * swap bytes of all text fields 1231 */ 1232 if (!ata_strncmp(nec_260, aidp->ai_model, sizeof (aidp->ai_model))) { 1233 swab(aidp->ai_drvser, aidp->ai_drvser, 1234 sizeof (aidp->ai_drvser)); 1235 swab(aidp->ai_fw, aidp->ai_fw, 1236 sizeof (aidp->ai_fw)); 1237 swab(aidp->ai_model, aidp->ai_model, 1238 sizeof (aidp->ai_model)); 1239 } 1240 1241 /* 1242 * Check if this drive has the Single Sector bug 1243 */ 1244 1245 if (ata_check_drive_blacklist(&ata_drvp->ad_id, ATA_BL_1SECTOR)) 1246 ata_drvp->ad_flags |= AD_1SECTOR; 1247 else 1248 ata_drvp->ad_flags &= ~AD_1SECTOR; 1249 1250 if (ata_check_drive_blacklist(&ata_drvp->ad_id, ATA_BL_LBA48)) 1251 ata_drvp->ad_flags |= AD_BLLBA48; 1252 else 1253 ata_drvp->ad_flags &= ~AD_BLLBA48; 1254 1255 /* Check if this drive has the "revert to defaults" bug */ 1256 if (!ata_check_revert_to_defaults(ata_drvp)) 1257 ata_drvp->ad_flags |= AD_NORVRT; 1258 1259 /* Dump the drive info */ 1260 (void) strncpy(buf, aidp->ai_model, sizeof (aidp->ai_model)); 1261 buf[sizeof (aidp->ai_model)-1] = '\0'; 1262 for (i = sizeof (aidp->ai_model) - 2; buf[i] == ' '; i--) 1263 buf[i] = '\0'; 1264 1265 ATAPRT(("?\t%s device at targ %d, lun %d lastlun 0x%x\n", 1266 (ATAPIDRV(ata_drvp) ? "ATAPI":"IDE"), 1267 ata_drvp->ad_targ, ata_drvp->ad_lun, aidp->ai_lastlun)); 1268 1269 ATAPRT(("?\tmodel %s\n", buf)); 1270 1271 if (aidp->ai_majorversion != 0 && aidp->ai_majorversion != 0xffff) { 1272 for (i = 14; i >= 2; i--) { 1273 if (aidp->ai_majorversion & (1 << i)) { 1274 valid_version = i; 1275 break; 1276 } 1277 } 1278 ATAPRT(( 1279 "?\tATA/ATAPI-%d supported, majver 0x%x minver 0x%x\n", 1280 valid_version, 1281 aidp->ai_majorversion, 1282 aidp->ai_minorversion)); 1283 } 1284 1285 if (ata_capability_data) { 1286 1287 ATAPRT(("?\t\tstat %x, err %x\n", 1288 ddi_get8(ata_ctlp->ac_iohandle2, 1289 ata_ctlp->ac_altstatus), 1290 ddi_get8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_error))); 1291 1292 ATAPRT(("?\t\tcfg 0x%x, cap 0x%x\n", 1293 aidp->ai_config, 1294 aidp->ai_cap)); 1295 1296 /* 1297 * Be aware that ATA-6 and later drives may not provide valid 1298 * geometry information and other obsoleted info. 1299 * Select what is printed based on supported ATA model (skip 1300 * anything below ATA/ATAPI-3) 1301 */ 1302 1303 if (valid_version == 0 || aidp->ai_majorversion < 1304 ATAC_MAJVER_6) { 1305 /* 1306 * Supported version less then ATA-6 1307 */ 1308 ATAPRT(("?\t\tcyl %d, hd %d, sec/trk %d\n", 1309 aidp->ai_fixcyls, 1310 aidp->ai_heads, 1311 aidp->ai_sectors)); 1312 } 1313 ATAPRT(("?\t\tmult1 0x%x, mult2 0x%x\n", 1314 aidp->ai_mult1, 1315 aidp->ai_mult2)); 1316 if (valid_version && aidp->ai_majorversion < ATAC_MAJVER_4) { 1317 ATAPRT(( 1318 "?\t\tpiomode 0x%x, dmamode 0x%x, advpiomode 0x%x\n", 1319 aidp->ai_piomode, 1320 aidp->ai_dmamode, 1321 aidp->ai_advpiomode)); 1322 } else { 1323 ATAPRT(("?\t\tadvpiomode 0x%x\n", 1324 aidp->ai_advpiomode)); 1325 } 1326 ATAPRT(("?\t\tminpio %d, minpioflow %d\n", 1327 aidp->ai_minpio, 1328 aidp->ai_minpioflow)); 1329 if (valid_version && aidp->ai_majorversion >= ATAC_MAJVER_4 && 1330 (aidp->ai_validinfo & ATAC_VALIDINFO_83)) { 1331 ATAPRT(("?\t\tdwdma 0x%x, ultradma 0x%x\n", 1332 aidp->ai_dworddma, 1333 aidp->ai_ultradma)); 1334 } else { 1335 ATAPRT(("?\t\tdwdma 0x%x\n", 1336 aidp->ai_dworddma)); 1337 } 1338 } 1339 1340 if (ATAPIDRV(ata_drvp)) { 1341 if (!atapi_init_drive(ata_drvp)) 1342 goto errout; 1343 } else { 1344 if (!ata_disk_init_drive(ata_drvp)) 1345 goto errout; 1346 } 1347 1348 /* 1349 * store pointer in controller struct 1350 */ 1351 CTL2DRV(ata_ctlp, targ, lun) = ata_drvp; 1352 1353 /* 1354 * lock the drive's current settings in case I have to 1355 * reset the drive due to some sort of error 1356 */ 1357 (void) ata_set_feature(ata_ctlp, ata_drvp, ATSF_DIS_REVPOD, 0); 1358 1359 return (ata_drvp); 1360 1361 errout: 1362 ata_uninit_drive(ata_drvp); 1363 return (NULL); 1364 } 1365 1366 /* destroy a drive */ 1367 1368 static void 1369 ata_uninit_drive( 1370 ata_drv_t *ata_drvp) 1371 { 1372 #if 0 1373 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp; 1374 #endif 1375 1376 ADBG_TRACE(("ata_uninit_drive entered\n")); 1377 1378 #if 0 1379 /* 1380 * DON'T DO THIS. disabling interrupts floats the IRQ line 1381 * which generates spurious interrupts 1382 */ 1383 1384 /* 1385 * Select the correct drive 1386 */ 1387 ddi_put8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_drvhd, 1388 ata_drvp->ad_drive_bits); 1389 ata_nsecwait(400); 1390 1391 /* 1392 * Disable interrupts from the drive 1393 */ 1394 ddi_put8(ata_ctlp->ac_iohandle2, ata_ctlp->ac_devctl, 1395 (ATDC_D3 | ATDC_NIEN)); 1396 #endif 1397 1398 /* interface specific clean-ups */ 1399 1400 if (ata_drvp->ad_flags & AD_ATAPI) 1401 atapi_uninit_drive(ata_drvp); 1402 else if (ata_drvp->ad_flags & AD_DISK) 1403 ata_disk_uninit_drive(ata_drvp); 1404 1405 /* free drive struct */ 1406 1407 kmem_free(ata_drvp, sizeof (ata_drv_t)); 1408 } 1409 1410 1411 /* 1412 * ata_drive_type() 1413 * 1414 * The timeout values and exact sequence of checking is critical 1415 * especially for atapi device detection, and should not be changed lightly. 1416 * 1417 */ 1418 static int 1419 ata_drive_type( 1420 uchar_t drvhd, 1421 ddi_acc_handle_t io_hdl1, 1422 caddr_t ioaddr1, 1423 ddi_acc_handle_t io_hdl2, 1424 caddr_t ioaddr2, 1425 struct ata_id *ata_id_bufp) 1426 { 1427 uchar_t status; 1428 1429 ADBG_TRACE(("ata_drive_type entered\n")); 1430 1431 /* 1432 * select the appropriate drive and LUN 1433 */ 1434 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_DRVHD, drvhd); 1435 ata_nsecwait(400); 1436 1437 /* 1438 * make certain the drive is selected, and wait for not busy 1439 */ 1440 (void) ata_wait3(io_hdl2, ioaddr2, 0, ATS_BSY, 0x7f, 0, 0x7f, 0, 1441 5 * 1000000); 1442 1443 status = ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS); 1444 1445 if (status & ATS_BSY) { 1446 ADBG_TRACE(("ata_drive_type 0x%p 0x%x\n", ioaddr1, status)); 1447 return (ATA_DEV_NONE); 1448 } 1449 1450 if (ata_disk_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) 1451 return (ATA_DEV_DISK); 1452 1453 /* 1454 * No disk, check for atapi unit. 1455 */ 1456 if (!atapi_signature(io_hdl1, ioaddr1)) { 1457 #ifndef ATA_DISABLE_ATAPI_1_7 1458 /* 1459 * Check for old (but prevalent) atapi 1.7B 1460 * spec device, the only known example is the 1461 * NEC CDR-260 (not 260R which is (mostly) ATAPI 1.2 1462 * compliant). This device has no signature 1463 * and requires conversion from hex to BCD 1464 * for some scsi audio commands. 1465 */ 1466 if (atapi_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) { 1467 return (ATA_DEV_ATAPI); 1468 } 1469 #endif 1470 return (ATA_DEV_NONE); 1471 } 1472 1473 if (atapi_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) { 1474 return (ATA_DEV_ATAPI); 1475 } 1476 1477 return (ATA_DEV_NONE); 1478 1479 } 1480 1481 /* 1482 * nsec-granularity time delay function 1483 */ 1484 void 1485 ata_nsecwait(clock_t count) 1486 { 1487 extern int tsc_gethrtime_initted; 1488 1489 if (tsc_gethrtime_initted) { 1490 hrtime_t end = gethrtime() + count; 1491 1492 while (gethrtime() < end) { 1493 SMT_PAUSE(); 1494 } 1495 } else { 1496 drv_usecwait(1 + (count / 1000)); 1497 } 1498 } 1499 1500 1501 /* 1502 * Wait for a register of a controller to achieve a specific state. 1503 * To return normally, all the bits in the first sub-mask must be ON, 1504 * all the bits in the second sub-mask must be OFF. 1505 * If timeout_usec microseconds pass without the controller achieving 1506 * the desired bit configuration, we return TRUE, else FALSE. 1507 */ 1508 1509 int ata_usec_delay = 10; 1510 1511 int 1512 ata_wait( 1513 ddi_acc_handle_t io_hdl, 1514 caddr_t ioaddr, 1515 uchar_t onbits, 1516 uchar_t offbits, 1517 uint_t timeout_usec) 1518 { 1519 ushort_t val; 1520 hrtime_t deadline = gethrtime() + 1521 (hrtime_t)timeout_usec * (NANOSEC / MICROSEC); 1522 1523 1524 do { 1525 val = ddi_get8(io_hdl, (uchar_t *)ioaddr + AT_ALTSTATUS); 1526 if ((val & onbits) == onbits && (val & offbits) == 0) 1527 return (TRUE); 1528 drv_usecwait(ata_usec_delay); 1529 } while (gethrtime() < deadline); 1530 1531 return (FALSE); 1532 } 1533 1534 1535 /* 1536 * 1537 * This is a slightly more complicated version that checks 1538 * for error conditions and bails-out rather than looping 1539 * until the timeout expires 1540 */ 1541 int 1542 ata_wait3( 1543 ddi_acc_handle_t io_hdl, 1544 caddr_t ioaddr, 1545 uchar_t onbits1, 1546 uchar_t offbits1, 1547 uchar_t failure_onbits2, 1548 uchar_t failure_offbits2, 1549 uchar_t failure_onbits3, 1550 uchar_t failure_offbits3, 1551 uint_t timeout_usec) 1552 { 1553 ushort_t val; 1554 hrtime_t deadline = gethrtime() + 1555 (hrtime_t)timeout_usec * (NANOSEC / MICROSEC); 1556 1557 do { 1558 val = ddi_get8(io_hdl, (uchar_t *)ioaddr + AT_ALTSTATUS); 1559 1560 /* 1561 * check for expected condition 1562 */ 1563 if ((val & onbits1) == onbits1 && (val & offbits1) == 0) 1564 return (TRUE); 1565 1566 /* 1567 * check for error conditions 1568 */ 1569 if ((val & failure_onbits2) == failure_onbits2 && 1570 (val & failure_offbits2) == 0) { 1571 return (FALSE); 1572 } 1573 1574 if ((val & failure_onbits3) == failure_onbits3 && 1575 (val & failure_offbits3) == 0) { 1576 return (FALSE); 1577 } 1578 1579 drv_usecwait(ata_usec_delay); 1580 } while (gethrtime() < deadline); 1581 1582 return (FALSE); 1583 } 1584 1585 1586 /* 1587 * 1588 * low level routine for ata_disk_id() and atapi_id() 1589 * 1590 */ 1591 1592 int 1593 ata_id_common( 1594 uchar_t id_cmd, 1595 int expect_drdy, 1596 ddi_acc_handle_t io_hdl1, 1597 caddr_t ioaddr1, 1598 ddi_acc_handle_t io_hdl2, 1599 caddr_t ioaddr2, 1600 struct ata_id *aidp) 1601 { 1602 uchar_t status; 1603 1604 ADBG_TRACE(("ata_id_common entered\n")); 1605 1606 bzero(aidp, sizeof (struct ata_id)); 1607 1608 /* 1609 * clear the features register 1610 */ 1611 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_FEATURE, 0); 1612 1613 /* 1614 * Disable interrupts from the device. When the ata 1615 * hardware is sharing its interrupt with another 1616 * device, the shared interrupt might have already been 1617 * unmasked in the interrupt controller and 1618 * triggering ata device interrupts will result in an 1619 * interrupt storm and a hung system. 1620 */ 1621 ddi_put8(io_hdl2, (uchar_t *)ioaddr2 + AT_DEVCTL, ATDC_D3 | ATDC_NIEN); 1622 1623 /* 1624 * issue IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command 1625 */ 1626 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_CMD, id_cmd); 1627 1628 /* wait for the busy bit to settle */ 1629 ata_nsecwait(400); 1630 1631 /* 1632 * read alternate status and check for conditions which 1633 * may indicate the drive is not present, to prevent getting 1634 * stuck in ata_wait3() below. 1635 */ 1636 status = ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS); 1637 1638 /* 1639 * 0x0, 0x7f, or ATS_DF can happen when no drive is present 1640 */ 1641 if ((status == 0x0) || (status == 0x7f) || 1642 ((status & (ATS_BSY|ATS_DF)) == ATS_DF)) { 1643 /* invalid status, can't be an ATA or ATAPI device */ 1644 return (FALSE); 1645 } 1646 1647 /* 1648 * According to the ATA specification, some drives may have 1649 * to read the media to complete this command. We need to 1650 * make sure we give them enough time to respond. 1651 */ 1652 (void) ata_wait3(io_hdl2, ioaddr2, 0, ATS_BSY, 1653 ATS_ERR, ATS_BSY, 0x7f, 0, 5 * 1000000); 1654 1655 /* 1656 * read the status byte and clear the pending interrupt 1657 */ 1658 status = ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_STATUS); 1659 1660 /* 1661 * this happens if there's no drive present 1662 */ 1663 if (status == 0xff || status == 0x7f) { 1664 /* invalid status, can't be an ATA or ATAPI device */ 1665 return (FALSE); 1666 } 1667 1668 if (status & ATS_BSY) { 1669 ADBG_ERROR(("ata_id_common: BUSY status 0x%x error 0x%x\n", 1670 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 +AT_ALTSTATUS), 1671 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1672 return (FALSE); 1673 } 1674 1675 if (!(status & ATS_DRQ)) { 1676 if (status & (ATS_ERR | ATS_DF)) { 1677 return (FALSE); 1678 } 1679 /* 1680 * Give the drive another second to assert DRQ. Some older 1681 * drives de-assert BSY before asserting DRQ. 1682 */ 1683 if (!ata_wait(io_hdl2, ioaddr2, ATS_DRQ, ATS_BSY, 1000000)) { 1684 ADBG_WARN(("ata_id_common: !DRQ status 0x%x error 0x%x\n", 1685 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 +AT_ALTSTATUS), 1686 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1687 return (FALSE); 1688 } 1689 } 1690 1691 /* 1692 * transfer the data 1693 */ 1694 ddi_rep_get16(io_hdl1, (ushort_t *)aidp, (ushort_t *)ioaddr1 + AT_DATA, 1695 NBPSCTR >> 1, DDI_DEV_NO_AUTOINCR); 1696 1697 /* wait for the busy bit to settle */ 1698 ata_nsecwait(400); 1699 1700 1701 /* 1702 * Wait for the drive to recognize I've read all the data. 1703 * Some drives have been observed to take as much as 3msec to 1704 * deassert DRQ after reading the data; allow 10 msec just in case. 1705 * 1706 * Note: some non-compliant ATAPI drives (e.g., NEC Multispin 6V, 1707 * CDR-1350A) don't assert DRDY. If we've made it this far we can 1708 * safely ignore the DRDY bit since the ATAPI Packet command 1709 * actually doesn't require it to ever be asserted. 1710 * 1711 */ 1712 if (!ata_wait(io_hdl2, ioaddr2, (uchar_t)(expect_drdy ? ATS_DRDY : 0), 1713 (ATS_BSY | ATS_DRQ), 1000000)) { 1714 ADBG_WARN(("ata_id_common: bad status 0x%x error 0x%x\n", 1715 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS), 1716 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1717 return (FALSE); 1718 } 1719 1720 /* 1721 * Check to see if the command aborted. This happens if 1722 * an IDENTIFY DEVICE command is issued to an ATAPI PACKET device, 1723 * or if an IDENTIFY PACKET DEVICE command is issued to an ATA 1724 * (non-PACKET) device. 1725 */ 1726 if (status & (ATS_DF | ATS_ERR)) { 1727 ADBG_WARN(("ata_id_common: status 0x%x error 0x%x \n", 1728 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS), 1729 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1730 return (FALSE); 1731 } 1732 return (TRUE); 1733 } 1734 1735 1736 /* 1737 * Low level routine to issue a non-data command and busy wait for 1738 * the completion status. 1739 */ 1740 1741 int 1742 ata_command( 1743 ata_ctl_t *ata_ctlp, 1744 ata_drv_t *ata_drvp, 1745 int expect_drdy, 1746 int silent, 1747 uint_t busy_wait, 1748 uchar_t cmd, 1749 uchar_t feature, 1750 uchar_t count, 1751 uchar_t sector, 1752 uchar_t head, 1753 uchar_t cyl_low, 1754 uchar_t cyl_hi) 1755 { 1756 ddi_acc_handle_t io_hdl1 = ata_ctlp->ac_iohandle1; 1757 ddi_acc_handle_t io_hdl2 = ata_ctlp->ac_iohandle2; 1758 uchar_t status; 1759 1760 /* select the drive */ 1761 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, ata_drvp->ad_drive_bits); 1762 ata_nsecwait(400); 1763 1764 /* make certain the drive selected */ 1765 if (!ata_wait(io_hdl2, ata_ctlp->ac_ioaddr2, 1766 (uchar_t)(expect_drdy ? ATS_DRDY : 0), 1767 ATS_BSY, busy_wait)) { 1768 ADBG_ERROR(("ata_command: select failed " 1769 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x " 1770 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n", 1771 expect_drdy, cmd, feature, count, 1772 sector, head, cyl_low, cyl_hi)); 1773 return (FALSE); 1774 } 1775 1776 /* 1777 * set all the regs 1778 */ 1779 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, (head | ata_drvp->ad_drive_bits)); 1780 ddi_put8(io_hdl1, ata_ctlp->ac_sect, sector); 1781 ddi_put8(io_hdl1, ata_ctlp->ac_count, count); 1782 ddi_put8(io_hdl1, ata_ctlp->ac_lcyl, cyl_low); 1783 ddi_put8(io_hdl1, ata_ctlp->ac_hcyl, cyl_hi); 1784 ddi_put8(io_hdl1, ata_ctlp->ac_feature, feature); 1785 1786 /* send the command */ 1787 ddi_put8(io_hdl1, ata_ctlp->ac_cmd, cmd); 1788 1789 /* wait for the busy bit to settle */ 1790 ata_nsecwait(400); 1791 1792 /* wait for not busy */ 1793 if (!ata_wait(io_hdl2, ata_ctlp->ac_ioaddr2, 0, ATS_BSY, busy_wait)) { 1794 ADBG_ERROR(("ata_command: BSY too long!" 1795 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x " 1796 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n", 1797 expect_drdy, cmd, feature, count, 1798 sector, head, cyl_low, cyl_hi)); 1799 return (FALSE); 1800 } 1801 1802 /* 1803 * wait for DRDY before continuing 1804 */ 1805 (void) ata_wait3(io_hdl2, ata_ctlp->ac_ioaddr2, 1806 ATS_DRDY, ATS_BSY, /* okay */ 1807 ATS_ERR, ATS_BSY, /* cmd failed */ 1808 ATS_DF, ATS_BSY, /* drive failed */ 1809 busy_wait); 1810 1811 /* read status to clear IRQ, and check for error */ 1812 status = ddi_get8(io_hdl1, ata_ctlp->ac_status); 1813 1814 if ((status & (ATS_BSY | ATS_DF | ATS_ERR)) == 0) 1815 return (TRUE); 1816 1817 if (!silent) { 1818 ADBG_ERROR(("ata_command status 0x%x error 0x%x " 1819 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x " 1820 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n", 1821 ddi_get8(io_hdl1, ata_ctlp->ac_status), 1822 ddi_get8(io_hdl1, ata_ctlp->ac_error), 1823 expect_drdy, cmd, feature, count, 1824 sector, head, cyl_low, cyl_hi)); 1825 } 1826 return (FALSE); 1827 } 1828 1829 1830 1831 /* 1832 * 1833 * Issue a SET FEATURES command 1834 * 1835 */ 1836 1837 int 1838 ata_set_feature( 1839 ata_ctl_t *ata_ctlp, 1840 ata_drv_t *ata_drvp, 1841 uchar_t feature, 1842 uchar_t value) 1843 { 1844 int rc; 1845 1846 rc = ata_command(ata_ctlp, ata_drvp, TRUE, TRUE, ata_set_feature_wait, 1847 ATC_SET_FEAT, feature, value, 0, 0, 0, 0); 1848 /* feature, count, sector, head, cyl_low, cyl_hi */ 1849 1850 if (rc) { 1851 return (TRUE); 1852 } 1853 1854 ADBG_ERROR(("?ata_set_feature: (0x%x,0x%x) failed\n", feature, value)); 1855 return (FALSE); 1856 } 1857 1858 1859 1860 /* 1861 * 1862 * Issue a FLUSH CACHE command 1863 * 1864 */ 1865 1866 static int 1867 ata_flush_cache( 1868 ata_ctl_t *ata_ctlp, 1869 ata_drv_t *ata_drvp) 1870 { 1871 /* this command is optional so fail silently */ 1872 return (ata_command(ata_ctlp, ata_drvp, TRUE, TRUE, 1873 ata_flush_cache_wait, 1874 ATC_FLUSH_CACHE, 0, 0, 0, 0, 0, 0)); 1875 } 1876 1877 /* 1878 * ata_setup_ioaddr() 1879 * 1880 * Map the device registers and return the handles. 1881 * 1882 * If this is a ISA-ATA controller then only two handles are 1883 * initialized and returned. 1884 * 1885 * If this is a PCI-IDE controller than a third handle (for the 1886 * PCI-IDE Bus Mastering registers) is initialized and returned. 1887 * 1888 */ 1889 1890 static int 1891 ata_setup_ioaddr( 1892 dev_info_t *dip, 1893 ddi_acc_handle_t *handle1p, 1894 caddr_t *addr1p, 1895 ddi_acc_handle_t *handle2p, 1896 caddr_t *addr2p, 1897 ddi_acc_handle_t *bm_hdlp, 1898 caddr_t *bm_addrp) 1899 { 1900 ddi_device_acc_attr_t dev_attr; 1901 int rnumber; 1902 int rc; 1903 off_t regsize; 1904 1905 /* 1906 * Make certain the controller is enabled and its regs are map-able 1907 * 1908 */ 1909 rc = ddi_dev_regsize(dip, 0, ®size); 1910 if (rc != DDI_SUCCESS || regsize <= AT_CMD) { 1911 ADBG_INIT(("ata_setup_ioaddr(1): rc %d regsize %lld\n", 1912 rc, (long long)regsize)); 1913 return (FALSE); 1914 } 1915 1916 rc = ddi_dev_regsize(dip, 1, ®size); 1917 if (rc != DDI_SUCCESS || regsize <= AT_ALTSTATUS) { 1918 ADBG_INIT(("ata_setup_ioaddr(2): rc %d regsize %lld\n", 1919 rc, (long long)regsize)); 1920 return (FALSE); 1921 } 1922 1923 /* 1924 * setup the device attribute structure for little-endian, 1925 * strict ordering access. 1926 */ 1927 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 1928 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 1929 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1930 1931 *handle1p = NULL; 1932 *handle2p = NULL; 1933 *bm_hdlp = NULL; 1934 1935 /* 1936 * Determine whether this is a ISA, PNP-ISA, or PCI-IDE device 1937 */ 1938 if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "pnp-csn")) { 1939 /* it's PNP-ISA, skip over the extra reg tuple */ 1940 rnumber = 1; 1941 goto not_pciide; 1942 } 1943 1944 /* else, it's ISA or PCI-IDE, check further */ 1945 rnumber = 0; 1946 1947 if (!ata_is_pci(dip)) { 1948 /* 1949 * If it's not a PCI-IDE, there are only two reg tuples 1950 * and the first one contains the I/O base (170 or 1f0) 1951 * rather than the controller instance number. 1952 */ 1953 ADBG_TRACE(("ata_setup_ioaddr !pci-ide\n")); 1954 goto not_pciide; 1955 } 1956 1957 1958 /* 1959 * Map the correct half of the PCI-IDE Bus Master registers. 1960 * There's a single BAR that maps these registers for both 1961 * controller's in a dual-controller chip and it's upto my 1962 * parent nexus, pciide, to adjust which (based on my instance 1963 * number) half this call maps. 1964 */ 1965 rc = ddi_dev_regsize(dip, 2, ®size); 1966 if (rc != DDI_SUCCESS || regsize < 8) { 1967 ADBG_INIT(("ata_setup_ioaddr(3): rc %d regsize %lld\n", 1968 rc, (long long)regsize)); 1969 goto not_pciide; 1970 } 1971 1972 rc = ddi_regs_map_setup(dip, 2, bm_addrp, 0, 0, &dev_attr, bm_hdlp); 1973 1974 if (rc != DDI_SUCCESS) { 1975 /* map failed, try to use in non-pci-ide mode */ 1976 ADBG_WARN(("ata_setup_ioaddr bus master map failed, rc=0x%x\n", 1977 rc)); 1978 *bm_hdlp = NULL; 1979 } 1980 1981 not_pciide: 1982 /* 1983 * map the lower command block registers 1984 */ 1985 1986 rc = ddi_regs_map_setup(dip, rnumber, addr1p, 0, 0, &dev_attr, 1987 handle1p); 1988 1989 if (rc != DDI_SUCCESS) { 1990 cmn_err(CE_WARN, "ata: reg tuple 0 map failed, rc=0x%x\n", rc); 1991 goto out1; 1992 } 1993 1994 /* 1995 * If the controller is being used in compatibility mode 1996 * via /devices/isa/ata@1,{1f0,1f0}/..., the reg property 1997 * will specify zeros for the I/O ports for the PCI 1998 * instance. 1999 */ 2000 if (*addr1p == 0) { 2001 ADBG_TRACE(("ata_setup_ioaddr ioaddr1 0\n")); 2002 goto out2; 2003 } 2004 2005 /* 2006 * map the upper control block registers 2007 */ 2008 rc = ddi_regs_map_setup(dip, rnumber + 1, addr2p, 0, 0, &dev_attr, 2009 handle2p); 2010 if (rc == DDI_SUCCESS) 2011 return (TRUE); 2012 2013 cmn_err(CE_WARN, "ata: reg tuple 1 map failed, rc=0x%x", rc); 2014 2015 out2: 2016 if (*handle1p != NULL) { 2017 ddi_regs_map_free(handle1p); 2018 *handle1p = NULL; 2019 } 2020 2021 out1: 2022 if (*bm_hdlp != NULL) { 2023 ddi_regs_map_free(bm_hdlp); 2024 *bm_hdlp = NULL; 2025 } 2026 return (FALSE); 2027 2028 } 2029 2030 /* 2031 * 2032 * Currently, the only supported controllers are ones which 2033 * support the SFF-8038 Bus Mastering spec. 2034 * 2035 * Check the parent node's IEEE 1275 class-code property to 2036 * determine if it's an PCI-IDE instance which supports SFF-8038 2037 * Bus Mastering. It's perfectly valid to have a PCI-IDE controller 2038 * that doesn't do Bus Mastering. In that case, my interrupt handler 2039 * only uses the interrupt latch bit in PCI-IDE status register. 2040 * The assumption is that the programming interface byte of the 2041 * class-code property reflects the bus master DMA capability of 2042 * the controller. 2043 * 2044 * Whether the drive support supports the DMA option still needs 2045 * to be checked later. Each individual request also has to be 2046 * checked for alignment and size to decide whether to use the 2047 * DMA transfer mode. 2048 */ 2049 2050 static void 2051 ata_init_pciide( 2052 dev_info_t *dip, 2053 ata_ctl_t *ata_ctlp) 2054 { 2055 uint_t class_code; 2056 uchar_t status; 2057 2058 ata_cntrl_DMA_sel_msg = NULL; 2059 2060 if (ata_ctlp->ac_bmhandle == NULL) { 2061 ata_ctlp->ac_pciide = FALSE; 2062 ata_ctlp->ac_pciide_bm = FALSE; 2063 ata_cntrl_DMA_sel_msg = "cntrl not Bus Master DMA capable"; 2064 return; 2065 } 2066 2067 /* 2068 * check if it's a known bogus PCI-IDE chip 2069 */ 2070 if (ata_check_pciide_blacklist(dip, ATA_BL_BOGUS)) { 2071 ADBG_WARN(("ata_setup_ioaddr pci-ide blacklist\n")); 2072 ata_ctlp->ac_pciide = FALSE; 2073 ata_ctlp->ac_pciide_bm = FALSE; 2074 ata_cntrl_DMA_sel_msg = "cntrl blacklisted"; 2075 return; 2076 } 2077 ata_ctlp->ac_pciide = TRUE; 2078 2079 if (ata_check_pciide_blacklist(dip, ATA_BL_BMSTATREG_PIO_BROKEN)) { 2080 ata_ctlp->ac_flags |= AC_BMSTATREG_PIO_BROKEN; 2081 } 2082 2083 /* 2084 * check for a PCI-IDE chip with a broken DMA engine 2085 */ 2086 if (ata_check_pciide_blacklist(dip, ATA_BL_NODMA)) { 2087 ata_ctlp->ac_pciide_bm = FALSE; 2088 ata_cntrl_DMA_sel_msg = 2089 "cntrl blacklisted/DMA engine broken"; 2090 return; 2091 } 2092 2093 /* 2094 * Check the Programming Interface register to determine 2095 * if this device supports PCI-IDE Bus Mastering. Some PCI-IDE 2096 * devices don't support Bus Mastering or DMA. 2097 * Since we are dealing with pre-qualified pci-ide controller, 2098 * check programming interface byte only. 2099 */ 2100 2101 class_code = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 2102 DDI_PROP_DONTPASS, "class-code", 0); 2103 if ((class_code & PCIIDE_BM_CAP_MASK) != PCIIDE_BM_CAP_MASK) { 2104 ata_ctlp->ac_pciide_bm = FALSE; 2105 ata_cntrl_DMA_sel_msg = 2106 "cntrl not Bus Master DMA capable"; 2107 return; 2108 } 2109 2110 /* 2111 * Avoid doing DMA on "simplex" chips which share hardware 2112 * between channels 2113 */ 2114 status = ddi_get8(ata_ctlp->ac_bmhandle, 2115 (uchar_t *)ata_ctlp->ac_bmaddr + PCIIDE_BMISX_REG); 2116 /* 2117 * Some motherboards have CSB5's that are wired "to emulate CSB4 mode". 2118 * In such a mode, the simplex bit is asserted, but in fact testing 2119 * on such a motherboard has shown that the devices are not simplex 2120 * -- DMA can be used on both channels concurrently with no special 2121 * considerations. For chips like this, we have the ATA_BL_NO_SIMPLEX 2122 * flag set to indicate that the value of the simplex bit can be 2123 * ignored. 2124 */ 2125 2126 if (status & PCIIDE_BMISX_SIMPLEX) { 2127 if (ata_check_pciide_blacklist(dip, ATA_BL_NO_SIMPLEX)) { 2128 cmn_err(CE_WARN, "Ignoring false simplex bit \n"); 2129 2130 } else { 2131 2132 int simplex_dma_channel, *rp, proplen, channel; 2133 int dma_on = FALSE; 2134 2135 /* 2136 * By default,use DMA on channel 0 and PIO on channel 2137 * 1. This can be switched by setting 2138 * ata-simplex-dma-channel to: 2139 * 0 DMA on channel 0 (default without this 2140 * property) 2141 * 1 DMA on channel 1 2142 * any other value: DMA off on both channels. 2143 */ 2144 simplex_dma_channel = ata_prop_lookup_int(DDI_DEV_T_ANY, 2145 ata_ctlp->ac_dip, 0, "ata-simplex-dma-channel", 0); 2146 2147 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 2148 ata_ctlp->ac_dip, DDI_PROP_DONTPASS, "reg", &rp, 2149 (uint_t *)&proplen) == DDI_PROP_SUCCESS) { 2150 2151 channel = *rp; 2152 ddi_prop_free(rp); 2153 2154 if (simplex_dma_channel == channel) { 2155 cmn_err(CE_CONT, "?ata: simplex " 2156 "controller. DMA on channel" 2157 " %d PIO on channel %d", 2158 channel, channel ? 0:1); 2159 dma_on = TRUE; 2160 } else { 2161 ata_cntrl_DMA_sel_msg = 2162 "simplex controller"; 2163 } 2164 } 2165 2166 if (dma_on == FALSE) { 2167 ata_ctlp->ac_pciide_bm = FALSE; 2168 2169 return; 2170 } 2171 } 2172 } 2173 2174 /* 2175 * It's a compatible PCI-IDE Bus Mastering controller, 2176 * allocate and map the DMA Scatter/Gather list (PRDE table). 2177 */ 2178 if (ata_pciide_alloc(dip, ata_ctlp)) 2179 ata_ctlp->ac_pciide_bm = TRUE; 2180 else { 2181 ata_ctlp->ac_pciide_bm = FALSE; 2182 ata_cntrl_DMA_sel_msg = "unable to init DMA S/G list"; 2183 } 2184 } 2185 2186 /* 2187 * 2188 * Determine whether to enable DMA support for this drive. 2189 * The controller and the drive both have to support DMA. 2190 * The controller's capabilities were already checked in 2191 * ata_init_pciide(), now just check the drive's capabilities. 2192 * 2193 */ 2194 2195 static int 2196 ata_init_drive_pcidma( 2197 ata_ctl_t *ata_ctlp, 2198 ata_drv_t *ata_drvp, 2199 dev_info_t *tdip) 2200 { 2201 boolean_t dma; 2202 boolean_t cd_dma; 2203 boolean_t disk_dma; 2204 boolean_t atapi_dma; 2205 int ata_options; 2206 2207 ata_dev_DMA_sel_msg = NULL; 2208 2209 if (ata_ctlp->ac_pciide_bm != TRUE) { 2210 ata_dev_DMA_sel_msg = 2211 "controller is not Bus Master capable"; 2212 2213 return (ATA_DMA_OFF); 2214 } 2215 2216 ata_options = ddi_prop_get_int(DDI_DEV_T_ANY, ata_ctlp->ac_dip, 2217 0, "ata-options", 0); 2218 2219 if (!(ata_options & ATA_OPTIONS_DMA)) { 2220 /* 2221 * Either the ata-options property was not found or 2222 * DMA is not enabled by this property 2223 */ 2224 ata_dev_DMA_sel_msg = 2225 "disabled by \"ata-options\" property"; 2226 2227 return (ATA_DMA_OFF); 2228 } 2229 2230 if (ata_check_drive_blacklist(&ata_drvp->ad_id, ATA_BL_NODMA)) { 2231 ata_dev_DMA_sel_msg = "device not DMA capable; blacklisted"; 2232 2233 return (ATA_DMA_OFF); 2234 } 2235 2236 /* 2237 * DMA mode is mandatory on ATA-3 (or newer) drives but is 2238 * optional on ATA-2 (or older) drives. 2239 * 2240 * On ATA-2 drives the ai_majorversion word will probably 2241 * be 0xffff or 0x0000, check the (now obsolete) DMA bit in 2242 * the capabilities word instead. The order of these tests 2243 * is important since an ATA-3 drive doesn't have to set 2244 * the DMA bit in the capabilities word. 2245 * 2246 */ 2247 2248 if (!((ata_drvp->ad_id.ai_majorversion & 0x8000) == 0 && 2249 ata_drvp->ad_id.ai_majorversion >= (1 << 2)) && 2250 !(ata_drvp->ad_id.ai_cap & ATAC_DMA_SUPPORT)) { 2251 ata_dev_DMA_sel_msg = "device not DMA capable"; 2252 2253 return (ATA_DMA_OFF); 2254 } 2255 2256 /* 2257 * Disable DMA for ATAPI devices on controllers known to 2258 * have trouble with ATAPI DMA 2259 */ 2260 2261 if (ATAPIDRV(ata_drvp)) { 2262 if (ata_check_pciide_blacklist(ata_ctlp->ac_dip, 2263 ATA_BL_ATAPI_NODMA)) { 2264 ata_dev_DMA_sel_msg = 2265 "controller incapable of DMA for ATAPI device"; 2266 2267 return (ATA_DMA_OFF); 2268 } 2269 } 2270 dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2271 0, "ata-dma-enabled", TRUE); 2272 disk_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2273 0, "ata-disk-dma-enabled", TRUE); 2274 cd_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2275 0, "atapi-cd-dma-enabled", FALSE); 2276 atapi_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2277 0, "atapi-other-dma-enabled", TRUE); 2278 2279 if (dma == FALSE) { 2280 cmn_err(CE_CONT, "?ata_init_drive_pcidma: " 2281 "DMA disabled by \"ata-dma-enabled\" property"); 2282 ata_dev_DMA_sel_msg = "disabled by prop ata-dma-enabled"; 2283 2284 return (ATA_DMA_OFF); 2285 } 2286 2287 if (IS_CDROM(ata_drvp) == TRUE) { 2288 if (cd_dma == FALSE) { 2289 ata_dev_DMA_sel_msg = 2290 "disabled. Control with \"atapi-cd-dma-enabled\"" 2291 " property"; 2292 2293 return (ATA_DMA_OFF); 2294 } 2295 2296 } else if (ATAPIDRV(ata_drvp) == FALSE) { 2297 if (disk_dma == FALSE) { 2298 ata_dev_DMA_sel_msg = 2299 "disabled by \"ata-disk-dma-enabled\" property"; 2300 2301 return (ATA_DMA_OFF); 2302 } 2303 2304 } else if (atapi_dma == FALSE) { 2305 ata_dev_DMA_sel_msg = 2306 "disabled by \"atapi-other-dma-enabled\" property"; 2307 2308 return (ATA_DMA_OFF); 2309 } 2310 2311 return (ATA_DMA_ON); 2312 } 2313 2314 2315 2316 /* 2317 * this compare routine squeezes out extra blanks and 2318 * returns TRUE if p1 matches the leftmost substring of p2 2319 */ 2320 2321 static int 2322 ata_strncmp( 2323 char *p1, 2324 char *p2, 2325 int cnt) 2326 { 2327 2328 for (;;) { 2329 /* 2330 * skip over any extra blanks in both strings 2331 */ 2332 while (*p1 != '\0' && *p1 == ' ') 2333 p1++; 2334 2335 while (cnt != 0 && *p2 == ' ') { 2336 p2++; 2337 cnt--; 2338 } 2339 2340 /* 2341 * compare the two strings 2342 */ 2343 2344 if (cnt == 0 || *p1 != *p2) 2345 break; 2346 2347 while (cnt > 0 && *p1 == *p2) { 2348 p1++; 2349 p2++; 2350 cnt--; 2351 } 2352 2353 } 2354 2355 /* return TRUE if both strings ended at same point */ 2356 return ((*p1 == '\0') ? TRUE : FALSE); 2357 } 2358 2359 /* 2360 * Per PSARC/1997/281 create variant="atapi" property (if necessary) 2361 * on the target's dev_info node. Currently, the sd target driver 2362 * is the only driver which refers to this property. 2363 * 2364 * If the flag ata_id_debug is set also create the 2365 * the "ata" or "atapi" property on the target's dev_info node 2366 * 2367 */ 2368 2369 int 2370 ata_prop_create( 2371 dev_info_t *tgt_dip, 2372 ata_drv_t *ata_drvp, 2373 char *name) 2374 { 2375 int rc; 2376 2377 ADBG_TRACE(("ata_prop_create 0x%p 0x%p %s\n", tgt_dip, ata_drvp, name)); 2378 2379 if (strcmp("atapi", name) == 0) { 2380 rc = ndi_prop_update_string(DDI_DEV_T_NONE, tgt_dip, 2381 "variant", name); 2382 if (rc != DDI_PROP_SUCCESS) 2383 return (FALSE); 2384 } 2385 2386 if (!ata_id_debug) 2387 return (TRUE); 2388 2389 rc = ndi_prop_update_byte_array(DDI_DEV_T_NONE, tgt_dip, name, 2390 (uchar_t *)&ata_drvp->ad_id, sizeof (ata_drvp->ad_id)); 2391 if (rc != DDI_PROP_SUCCESS) { 2392 ADBG_ERROR(("ata_prop_create failed, rc=%d\n", rc)); 2393 } 2394 return (TRUE); 2395 } 2396 2397 2398 /* *********************************************************************** */ 2399 /* *********************************************************************** */ 2400 /* *********************************************************************** */ 2401 2402 /* 2403 * This state machine doesn't implement the ATAPI Optional Overlap 2404 * feature. You need that feature to efficiently support ATAPI 2405 * tape drives. See the 1394-ATA Tailgate spec (D97107), Figure 24, 2406 * for an example of how to add the necessary additional NextActions 2407 * and NextStates to this FSM and the atapi_fsm, in order to support 2408 * the Overlap Feature. 2409 */ 2410 2411 2412 uchar_t ata_ctlr_fsm_NextAction[ATA_CTLR_NSTATES][ATA_CTLR_NFUNCS] = { 2413 /* --------------------- next action --------------------- | - current - */ 2414 /* start0 --- start1 ---- intr ------ fini --- reset --- */ 2415 { AC_START, AC_START, AC_NADA, AC_NADA, AC_RESET_I }, /* idle */ 2416 { AC_BUSY, AC_BUSY, AC_INTR, AC_FINI, AC_RESET_A }, /* active0 */ 2417 { AC_BUSY, AC_BUSY, AC_INTR, AC_FINI, AC_RESET_A }, /* active1 */ 2418 }; 2419 2420 uchar_t ata_ctlr_fsm_NextState[ATA_CTLR_NSTATES][ATA_CTLR_NFUNCS] = { 2421 2422 /* --------------------- next state --------------------- | - current - */ 2423 /* start0 --- start1 ---- intr ------ fini --- reset --- */ 2424 { AS_ACTIVE0, AS_ACTIVE1, AS_IDLE, AS_IDLE, AS_IDLE }, /* idle */ 2425 { AS_ACTIVE0, AS_ACTIVE0, AS_ACTIVE0, AS_IDLE, AS_ACTIVE0 }, /* active0 */ 2426 { AS_ACTIVE1, AS_ACTIVE1, AS_ACTIVE1, AS_IDLE, AS_ACTIVE1 }, /* active1 */ 2427 }; 2428 2429 2430 static int 2431 ata_ctlr_fsm( 2432 uchar_t fsm_func, 2433 ata_ctl_t *ata_ctlp, 2434 ata_drv_t *ata_drvp, 2435 ata_pkt_t *ata_pktp, 2436 int *DoneFlgp) 2437 { 2438 uchar_t action; 2439 uchar_t current_state; 2440 uchar_t next_state; 2441 int rc; 2442 2443 current_state = ata_ctlp->ac_state; 2444 action = ata_ctlr_fsm_NextAction[current_state][fsm_func]; 2445 next_state = ata_ctlr_fsm_NextState[current_state][fsm_func]; 2446 2447 /* 2448 * Set the controller's new state 2449 */ 2450 ata_ctlp->ac_state = next_state; 2451 switch (action) { 2452 2453 case AC_BUSY: 2454 return (ATA_FSM_RC_BUSY); 2455 2456 case AC_NADA: 2457 return (ATA_FSM_RC_OKAY); 2458 2459 case AC_START: 2460 ASSERT(ata_ctlp->ac_active_pktp == NULL); 2461 ASSERT(ata_ctlp->ac_active_drvp == NULL); 2462 2463 ata_ctlp->ac_active_pktp = ata_pktp; 2464 ata_ctlp->ac_active_drvp = ata_drvp; 2465 2466 rc = (*ata_pktp->ap_start)(ata_ctlp, ata_drvp, ata_pktp); 2467 2468 if (rc == ATA_FSM_RC_BUSY) { 2469 /* the request didn't start, GHD will requeue it */ 2470 ata_ctlp->ac_state = AS_IDLE; 2471 ata_ctlp->ac_active_pktp = NULL; 2472 ata_ctlp->ac_active_drvp = NULL; 2473 } 2474 return (rc); 2475 2476 case AC_INTR: 2477 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2478 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2479 2480 ata_drvp = ata_ctlp->ac_active_drvp; 2481 ata_pktp = ata_ctlp->ac_active_pktp; 2482 return ((*ata_pktp->ap_intr)(ata_ctlp, ata_drvp, ata_pktp)); 2483 2484 case AC_RESET_A: /* Reset, controller active */ 2485 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2486 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2487 2488 /* clean up the active request */ 2489 ata_pktp = ata_ctlp->ac_active_pktp; 2490 ata_pktp->ap_flags |= AP_DEV_RESET | AP_BUS_RESET; 2491 2492 /* halt the DMA engine */ 2493 if (ata_pktp->ap_pciide_dma) { 2494 ata_pciide_dma_stop(ata_ctlp); 2495 (void) ata_pciide_status_clear(ata_ctlp); 2496 } 2497 2498 /* Do a Software Reset to unwedge the bus */ 2499 if (!ata_software_reset(ata_ctlp)) { 2500 return (ATA_FSM_RC_BUSY); 2501 } 2502 2503 /* Then send a DEVICE RESET cmd to each ATAPI device */ 2504 atapi_fsm_reset(ata_ctlp); 2505 return (ATA_FSM_RC_FINI); 2506 2507 case AC_RESET_I: /* Reset, controller idle */ 2508 /* Do a Software Reset to unwedge the bus */ 2509 if (!ata_software_reset(ata_ctlp)) { 2510 return (ATA_FSM_RC_BUSY); 2511 } 2512 2513 /* Then send a DEVICE RESET cmd to each ATAPI device */ 2514 atapi_fsm_reset(ata_ctlp); 2515 return (ATA_FSM_RC_OKAY); 2516 2517 case AC_FINI: 2518 break; 2519 } 2520 2521 /* 2522 * AC_FINI, check ARQ needs to be started or finished 2523 */ 2524 2525 ASSERT(action == AC_FINI); 2526 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2527 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2528 2529 /* 2530 * The active request is done now. 2531 * Disconnect the request from the controller and 2532 * add it to the done queue. 2533 */ 2534 ata_drvp = ata_ctlp->ac_active_drvp; 2535 ata_pktp = ata_ctlp->ac_active_pktp; 2536 2537 /* 2538 * If ARQ pkt is done, get ptr to original pkt and wrap it up. 2539 */ 2540 if (ata_pktp == ata_ctlp->ac_arq_pktp) { 2541 ata_pkt_t *arq_pktp; 2542 2543 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ done\n", ata_ctlp)); 2544 2545 arq_pktp = ata_pktp; 2546 ata_pktp = ata_ctlp->ac_fault_pktp; 2547 ata_ctlp->ac_fault_pktp = NULL; 2548 if (arq_pktp->ap_flags & (AP_ERROR | AP_BUS_RESET)) 2549 ata_pktp->ap_flags |= AP_ARQ_ERROR; 2550 else 2551 ata_pktp->ap_flags |= AP_ARQ_OKAY; 2552 goto all_done; 2553 } 2554 2555 2556 #define AP_ARQ_NEEDED (AP_ARQ_ON_ERROR | AP_GOT_STATUS | AP_ERROR) 2557 2558 /* 2559 * Start ARQ pkt if necessary 2560 */ 2561 if ((ata_pktp->ap_flags & AP_ARQ_NEEDED) == AP_ARQ_NEEDED && 2562 (ata_pktp->ap_status & ATS_ERR)) { 2563 2564 /* set controller state back to active */ 2565 ata_ctlp->ac_state = current_state; 2566 2567 /* try to start the ARQ pkt */ 2568 rc = ata_start_arq(ata_ctlp, ata_drvp, ata_pktp); 2569 2570 if (rc == ATA_FSM_RC_BUSY) { 2571 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ BUSY\n", ata_ctlp)); 2572 /* let the target driver handle the problem */ 2573 ata_ctlp->ac_state = AS_IDLE; 2574 ata_ctlp->ac_active_pktp = NULL; 2575 ata_ctlp->ac_active_drvp = NULL; 2576 ata_ctlp->ac_fault_pktp = NULL; 2577 goto all_done; 2578 } 2579 2580 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ started\n", ata_ctlp)); 2581 return (rc); 2582 } 2583 2584 /* 2585 * Normal completion, no error status, and not an ARQ pkt, 2586 * just fall through. 2587 */ 2588 2589 all_done: 2590 2591 /* 2592 * wrap everything up and tie a ribbon around it 2593 */ 2594 ata_ctlp->ac_active_pktp = NULL; 2595 ata_ctlp->ac_active_drvp = NULL; 2596 if (APKT2GCMD(ata_pktp) != (gcmd_t *)0) { 2597 ghd_complete(&ata_ctlp->ac_ccc, APKT2GCMD(ata_pktp)); 2598 if (DoneFlgp) 2599 *DoneFlgp = TRUE; 2600 } 2601 2602 return (ATA_FSM_RC_OKAY); 2603 } 2604 2605 2606 static int 2607 ata_start_arq( 2608 ata_ctl_t *ata_ctlp, 2609 ata_drv_t *ata_drvp, 2610 ata_pkt_t *ata_pktp) 2611 { 2612 ata_pkt_t *arq_pktp; 2613 int bytes; 2614 uint_t senselen; 2615 2616 ADBG_ARQ(("ata_start_arq 0x%p ARQ needed\n", ata_ctlp)); 2617 2618 /* 2619 * Determine just the size of the Request Sense Data buffer within 2620 * the scsi_arq_status structure. 2621 */ 2622 #define SIZEOF_ARQ_HEADER (sizeof (struct scsi_arq_status) \ 2623 - sizeof (struct scsi_extended_sense)) 2624 senselen = ata_pktp->ap_statuslen - SIZEOF_ARQ_HEADER; 2625 ASSERT(senselen > 0); 2626 2627 2628 /* save ptr to original pkt */ 2629 ata_ctlp->ac_fault_pktp = ata_pktp; 2630 2631 /* switch the controller's active pkt to the ARQ pkt */ 2632 arq_pktp = ata_ctlp->ac_arq_pktp; 2633 ata_ctlp->ac_active_pktp = arq_pktp; 2634 2635 /* finish initializing the ARQ CDB */ 2636 ata_ctlp->ac_arq_cdb[1] = ata_drvp->ad_lun << 4; 2637 ata_ctlp->ac_arq_cdb[4] = (uchar_t)senselen; 2638 2639 /* finish initializing the ARQ pkt */ 2640 arq_pktp->ap_v_addr = (caddr_t)&ata_pktp->ap_scbp->sts_sensedata; 2641 2642 arq_pktp->ap_resid = senselen; 2643 arq_pktp->ap_flags = AP_ATAPI | AP_READ; 2644 arq_pktp->ap_cdb_pad = 2645 ((unsigned)(ata_drvp->ad_cdb_len - arq_pktp->ap_cdb_len)) >> 1; 2646 2647 bytes = min(senselen, ATAPI_MAX_BYTES_PER_DRQ); 2648 arq_pktp->ap_hicyl = (uchar_t)(bytes >> 8); 2649 arq_pktp->ap_lwcyl = (uchar_t)bytes; 2650 2651 /* 2652 * This packet is shared by all drives on this controller 2653 * therefore we need to init the drive number on every ARQ. 2654 */ 2655 arq_pktp->ap_hd = ata_drvp->ad_drive_bits; 2656 2657 /* start it up */ 2658 return ((*arq_pktp->ap_start)(ata_ctlp, ata_drvp, arq_pktp)); 2659 } 2660 2661 /* 2662 * 2663 * reset the bus 2664 * 2665 */ 2666 2667 static int 2668 ata_reset_bus( 2669 ata_ctl_t *ata_ctlp) 2670 { 2671 int watchdog; 2672 uchar_t drive; 2673 int rc = FALSE; 2674 uchar_t fsm_func; 2675 int DoneFlg = FALSE; 2676 2677 /* 2678 * Do a Software Reset to unwedge the bus, and send 2679 * ATAPI DEVICE RESET to each ATAPI drive. 2680 */ 2681 fsm_func = ATA_FSM_RESET; 2682 for (watchdog = ata_reset_bus_watchdog; watchdog > 0; watchdog--) { 2683 switch (ata_ctlr_fsm(fsm_func, ata_ctlp, NULL, NULL, 2684 &DoneFlg)) { 2685 case ATA_FSM_RC_OKAY: 2686 rc = TRUE; 2687 goto fsm_done; 2688 2689 case ATA_FSM_RC_BUSY: 2690 return (FALSE); 2691 2692 case ATA_FSM_RC_INTR: 2693 fsm_func = ATA_FSM_INTR; 2694 rc = TRUE; 2695 continue; 2696 2697 case ATA_FSM_RC_FINI: 2698 fsm_func = ATA_FSM_FINI; 2699 rc = TRUE; 2700 continue; 2701 } 2702 } 2703 ADBG_WARN(("ata_reset_bus: watchdog\n")); 2704 2705 fsm_done: 2706 2707 /* 2708 * Reinitialize the ATA drives 2709 */ 2710 for (drive = 0; drive < ATA_MAXTARG; drive++) { 2711 ata_drv_t *ata_drvp; 2712 2713 if ((ata_drvp = CTL2DRV(ata_ctlp, drive, 0)) == NULL) 2714 continue; 2715 2716 if (ATAPIDRV(ata_drvp)) 2717 continue; 2718 2719 /* 2720 * Reprogram the Read/Write Multiple block factor 2721 * and current geometry into the drive. 2722 */ 2723 if (!ata_disk_setup_parms(ata_ctlp, ata_drvp)) 2724 rc = FALSE; 2725 } 2726 2727 /* If DoneFlg is TRUE, it means that ghd_complete() function */ 2728 /* has been already called. In this case ignore any errors and */ 2729 /* return TRUE to the caller, otherwise return the value of rc */ 2730 /* to the caller */ 2731 if (DoneFlg) 2732 return (TRUE); 2733 else 2734 return (rc); 2735 } 2736 2737 2738 /* 2739 * 2740 * Low level routine to toggle the Software Reset bit 2741 * 2742 */ 2743 2744 static int 2745 ata_software_reset( 2746 ata_ctl_t *ata_ctlp) 2747 { 2748 ddi_acc_handle_t io_hdl1 = ata_ctlp->ac_iohandle1; 2749 ddi_acc_handle_t io_hdl2 = ata_ctlp->ac_iohandle2; 2750 hrtime_t deadline; 2751 uint_t usecs_left; 2752 2753 ADBG_TRACE(("ata_reset_bus entered\n")); 2754 2755 /* disable interrupts and turn the software reset bit on */ 2756 ddi_put8(io_hdl2, ata_ctlp->ac_devctl, (ATDC_D3 | ATDC_SRST)); 2757 2758 /* why 30 milliseconds, the ATA/ATAPI-4 spec says 5 usec. */ 2759 drv_usecwait(30000); 2760 2761 /* turn the software reset bit back off */ 2762 ddi_put8(io_hdl2, ata_ctlp->ac_devctl, ATDC_D3); 2763 2764 /* 2765 * Wait for the controller to assert BUSY status. 2766 * I don't think 300 msecs is correct. The ATA/ATAPI-4 2767 * spec says 400 nsecs, (and 2 msecs if device 2768 * was in sleep mode; but we don't put drives to sleep 2769 * so it probably doesn't matter). 2770 */ 2771 drv_usecwait(300000); 2772 2773 /* 2774 * If drive 0 exists the test for completion is simple 2775 */ 2776 deadline = gethrtime() + ((hrtime_t)31 * NANOSEC); 2777 2778 if (CTL2DRV(ata_ctlp, 0, 0)) { 2779 goto wait_for_not_busy; 2780 } 2781 2782 ASSERT(CTL2DRV(ata_ctlp, 1, 0) != NULL); 2783 2784 /* 2785 * This must be a single device configuration, with drive 1 2786 * only. This complicates the test for completion because 2787 * issuing the software reset just caused drive 1 to 2788 * deselect. With drive 1 deselected, if I just read the 2789 * status register to test the BSY bit I get garbage, but 2790 * I can't re-select drive 1 until I'm certain the BSY bit 2791 * is de-asserted. Catch-22. 2792 * 2793 * In ATA/ATAPI-4, rev 15, section 9.16.2, it says to handle 2794 * this situation like this: 2795 */ 2796 2797 /* give up if the drive doesn't settle within 31 seconds */ 2798 while (gethrtime() < deadline) { 2799 /* 2800 * delay 10msec each time around the loop 2801 */ 2802 drv_usecwait(10000); 2803 2804 /* 2805 * try to select drive 1 2806 */ 2807 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, ATDH_DRIVE1); 2808 2809 ddi_put8(io_hdl1, ata_ctlp->ac_sect, 0x55); 2810 ddi_put8(io_hdl1, ata_ctlp->ac_sect, 0xaa); 2811 if (ddi_get8(io_hdl1, ata_ctlp->ac_sect) != 0xaa) 2812 continue; 2813 2814 ddi_put8(io_hdl1, ata_ctlp->ac_count, 0x55); 2815 ddi_put8(io_hdl1, ata_ctlp->ac_count, 0xaa); 2816 if (ddi_get8(io_hdl1, ata_ctlp->ac_count) != 0xaa) 2817 continue; 2818 2819 goto wait_for_not_busy; 2820 } 2821 return (FALSE); 2822 2823 wait_for_not_busy: 2824 2825 /* 2826 * Now wait up to 31 seconds for BUSY to clear. 2827 */ 2828 usecs_left = (deadline - gethrtime()) / 1000; 2829 (void) ata_wait3(io_hdl2, ata_ctlp->ac_ioaddr2, 0, ATS_BSY, 2830 ATS_ERR, ATS_BSY, ATS_DF, ATS_BSY, usecs_left); 2831 2832 return (TRUE); 2833 } 2834 2835 /* 2836 * 2837 * DDI interrupt handler 2838 * 2839 */ 2840 2841 static uint_t 2842 ata_intr( 2843 caddr_t arg) 2844 { 2845 ata_ctl_t *ata_ctlp; 2846 int one_shot = 1; 2847 2848 ata_ctlp = (ata_ctl_t *)arg; 2849 2850 return (ghd_intr(&ata_ctlp->ac_ccc, (void *)&one_shot)); 2851 } 2852 2853 2854 /* 2855 * 2856 * GHD ccc_get_status callback 2857 * 2858 */ 2859 2860 static int 2861 ata_get_status( 2862 void *hba_handle, 2863 void *intr_status) 2864 { 2865 ata_ctl_t *ata_ctlp = (ata_ctl_t *)hba_handle; 2866 uchar_t status; 2867 2868 ADBG_TRACE(("ata_get_status entered\n")); 2869 2870 /* 2871 * ignore interrupts before ata_attach completes 2872 */ 2873 if (!(ata_ctlp->ac_flags & AC_ATTACHED)) 2874 return (FALSE); 2875 2876 /* 2877 * can't be interrupt pending if nothing active 2878 */ 2879 switch (ata_ctlp->ac_state) { 2880 case AS_IDLE: 2881 return (FALSE); 2882 case AS_ACTIVE0: 2883 case AS_ACTIVE1: 2884 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2885 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2886 break; 2887 } 2888 2889 /* 2890 * If this is a PCI-IDE controller, check the PCI-IDE controller's 2891 * interrupt status latch. But don't clear it yet. 2892 * 2893 * AC_BMSTATREG_PIO_BROKEN flag is used currently for 2894 * CMD chips with device id 0x646. Since the interrupt bit on 2895 * Bus master IDE register is not usable when in PIO mode, 2896 * this chip is treated as a legacy device for interrupt 2897 * indication. The following code for CMD 2898 * chips may need to be revisited when we enable support for dma. 2899 * 2900 * CHANGE: DMA is not disabled for these devices. BM intr bit is 2901 * checked only if there was DMA used or BM intr is useable on PIO, 2902 * else treat it as before - as legacy device. 2903 */ 2904 2905 if ((ata_ctlp->ac_pciide) && 2906 ((ata_ctlp->ac_pciide_bm != FALSE) && 2907 ((ata_ctlp->ac_active_pktp->ap_pciide_dma == TRUE) || 2908 !(ata_ctlp->ac_flags & AC_BMSTATREG_PIO_BROKEN)))) { 2909 2910 if (!ata_pciide_status_pending(ata_ctlp)) 2911 return (FALSE); 2912 } else { 2913 /* 2914 * Interrupts from legacy ATA/IDE controllers are 2915 * edge-triggered but the dumb legacy ATA/IDE controllers 2916 * and drives don't have an interrupt status bit. 2917 * 2918 * Use a one_shot variable to make sure we only return 2919 * one status per interrupt. 2920 */ 2921 if (intr_status != NULL) { 2922 int *one_shot = (int *)intr_status; 2923 2924 if (*one_shot == 1) 2925 *one_shot = 0; 2926 else 2927 return (FALSE); 2928 } 2929 } 2930 2931 /* check if device is still busy */ 2932 2933 status = ddi_get8(ata_ctlp->ac_iohandle2, ata_ctlp->ac_altstatus); 2934 if (status & ATS_BSY) 2935 return (FALSE); 2936 return (TRUE); 2937 } 2938 2939 2940 /* 2941 * 2942 * get the current status and clear the IRQ 2943 * 2944 */ 2945 2946 int 2947 ata_get_status_clear_intr( 2948 ata_ctl_t *ata_ctlp, 2949 ata_pkt_t *ata_pktp) 2950 { 2951 uchar_t status; 2952 2953 /* 2954 * Here's where we clear the PCI-IDE interrupt latch. If this 2955 * request used DMA mode then we also have to check and clear 2956 * the DMA error latch at the same time. 2957 */ 2958 2959 if (ata_pktp->ap_pciide_dma) { 2960 if (ata_pciide_status_dmacheck_clear(ata_ctlp)) 2961 ata_pktp->ap_flags |= AP_ERROR | AP_TRAN_ERROR; 2962 } else if ((ata_ctlp->ac_pciide) && 2963 !(ata_ctlp->ac_flags & AC_BMSTATREG_PIO_BROKEN)) { 2964 /* 2965 * Some requests don't use DMA mode and therefore won't 2966 * set the DMA error latch, but we still have to clear 2967 * the interrupt latch. 2968 * Controllers with broken BM intr in PIO mode do not go 2969 * through this path. 2970 */ 2971 (void) ata_pciide_status_clear(ata_ctlp); 2972 } 2973 2974 /* 2975 * this clears the drive's interrupt 2976 */ 2977 status = ddi_get8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_status); 2978 ADBG_TRACE(("ata_get_status_clear_intr: 0x%x\n", status)); 2979 return (status); 2980 } 2981 2982 2983 2984 /* 2985 * 2986 * GHD interrupt handler 2987 * 2988 */ 2989 2990 /* ARGSUSED */ 2991 static void 2992 ata_process_intr( 2993 void *hba_handle, 2994 void *intr_status) 2995 { 2996 ata_ctl_t *ata_ctlp = (ata_ctl_t *)hba_handle; 2997 int watchdog; 2998 uchar_t fsm_func; 2999 int rc; 3000 3001 ADBG_TRACE(("ata_process_intr entered\n")); 3002 3003 /* 3004 * process the ATA or ATAPI interrupt 3005 */ 3006 3007 fsm_func = ATA_FSM_INTR; 3008 for (watchdog = ata_process_intr_watchdog; watchdog > 0; watchdog--) { 3009 rc = ata_ctlr_fsm(fsm_func, ata_ctlp, NULL, NULL, NULL); 3010 3011 switch (rc) { 3012 case ATA_FSM_RC_OKAY: 3013 return; 3014 3015 case ATA_FSM_RC_BUSY: /* wait for the next interrupt */ 3016 return; 3017 3018 case ATA_FSM_RC_INTR: /* re-invoke the FSM */ 3019 fsm_func = ATA_FSM_INTR; 3020 break; 3021 3022 case ATA_FSM_RC_FINI: /* move a request to done Q */ 3023 fsm_func = ATA_FSM_FINI; 3024 break; 3025 } 3026 } 3027 ADBG_WARN(("ata_process_intr: watchdog\n")); 3028 } 3029 3030 3031 3032 /* 3033 * 3034 * GHD ccc_hba_start callback 3035 * 3036 */ 3037 3038 static int 3039 ata_hba_start( 3040 void *hba_handle, 3041 gcmd_t *gcmdp) 3042 { 3043 ata_ctl_t *ata_ctlp; 3044 ata_drv_t *ata_drvp; 3045 ata_pkt_t *ata_pktp; 3046 uchar_t fsm_func; 3047 int request_started; 3048 int watchdog; 3049 3050 ADBG_TRACE(("ata_hba_start entered\n")); 3051 3052 ata_ctlp = (ata_ctl_t *)hba_handle; 3053 3054 if (ata_ctlp->ac_active_drvp != NULL) { 3055 ADBG_WARN(("ata_hba_start drvp not null\n")); 3056 return (FALSE); 3057 } 3058 if (ata_ctlp->ac_active_pktp != NULL) { 3059 ADBG_WARN(("ata_hba_start pktp not null\n")); 3060 return (FALSE); 3061 } 3062 3063 ata_pktp = GCMD2APKT(gcmdp); 3064 ata_drvp = GCMD2DRV(gcmdp); 3065 3066 /* 3067 * which drive? 3068 */ 3069 if (ata_drvp->ad_targ == 0) 3070 fsm_func = ATA_FSM_START0; 3071 else 3072 fsm_func = ATA_FSM_START1; 3073 3074 /* 3075 * start the request 3076 */ 3077 request_started = FALSE; 3078 for (watchdog = ata_hba_start_watchdog; watchdog > 0; watchdog--) { 3079 switch (ata_ctlr_fsm(fsm_func, ata_ctlp, ata_drvp, ata_pktp, 3080 NULL)) { 3081 case ATA_FSM_RC_OKAY: 3082 request_started = TRUE; 3083 goto fsm_done; 3084 3085 case ATA_FSM_RC_BUSY: 3086 /* if first time, tell GHD to requeue the request */ 3087 goto fsm_done; 3088 3089 case ATA_FSM_RC_INTR: 3090 /* 3091 * The start function polled for the next 3092 * bus phase, now fake an interrupt to process 3093 * the next action. 3094 */ 3095 request_started = TRUE; 3096 fsm_func = ATA_FSM_INTR; 3097 ata_drvp = NULL; 3098 ata_pktp = NULL; 3099 break; 3100 3101 case ATA_FSM_RC_FINI: /* move request to the done queue */ 3102 request_started = TRUE; 3103 fsm_func = ATA_FSM_FINI; 3104 ata_drvp = NULL; 3105 ata_pktp = NULL; 3106 break; 3107 } 3108 } 3109 ADBG_WARN(("ata_hba_start: watchdog\n")); 3110 3111 fsm_done: 3112 return (request_started); 3113 3114 } 3115 3116 static int 3117 ata_check_pciide_blacklist( 3118 dev_info_t *dip, 3119 uint_t flags) 3120 { 3121 ushort_t vendorid; 3122 ushort_t deviceid; 3123 pcibl_t *blp; 3124 int *propp; 3125 uint_t count; 3126 int rc; 3127 3128 3129 vendorid = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3130 DDI_PROP_DONTPASS, "vendor-id", 0); 3131 deviceid = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3132 DDI_PROP_DONTPASS, "device-id", 0); 3133 3134 /* 3135 * first check for a match in the "pci-ide-blacklist" property 3136 */ 3137 rc = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, 3138 "pci-ide-blacklist", &propp, &count); 3139 3140 if (rc == DDI_PROP_SUCCESS) { 3141 count = (count * sizeof (uint_t)) / sizeof (pcibl_t); 3142 blp = (pcibl_t *)propp; 3143 while (count--) { 3144 /* check for matching ID */ 3145 if ((vendorid & blp->b_vmask) 3146 != (blp->b_vendorid & blp->b_vmask)) { 3147 blp++; 3148 continue; 3149 } 3150 if ((deviceid & blp->b_dmask) 3151 != (blp->b_deviceid & blp->b_dmask)) { 3152 blp++; 3153 continue; 3154 } 3155 3156 /* got a match */ 3157 if (blp->b_flags & flags) { 3158 ddi_prop_free(propp); 3159 return (TRUE); 3160 } else { 3161 ddi_prop_free(propp); 3162 return (FALSE); 3163 } 3164 } 3165 ddi_prop_free(propp); 3166 } 3167 3168 /* 3169 * then check the built-in blacklist 3170 */ 3171 for (blp = ata_pciide_blacklist; blp->b_vendorid; blp++) { 3172 if ((vendorid & blp->b_vmask) != blp->b_vendorid) 3173 continue; 3174 if ((deviceid & blp->b_dmask) != blp->b_deviceid) 3175 continue; 3176 if (!(blp->b_flags & flags)) 3177 continue; 3178 return (TRUE); 3179 } 3180 return (FALSE); 3181 } 3182 3183 int 3184 ata_check_drive_blacklist( 3185 struct ata_id *aidp, 3186 uint_t flags) 3187 { 3188 atabl_t *blp; 3189 3190 for (blp = ata_drive_blacklist; blp->b_model != NULL; blp++) { 3191 if (!ata_strncmp(blp->b_model, aidp->ai_model, 3192 sizeof (aidp->ai_model))) 3193 continue; 3194 if (blp->b_fw != NULL) { 3195 if (!ata_strncmp(blp->b_fw, aidp->ai_fw, 3196 sizeof (aidp->ai_fw))) 3197 continue; 3198 } 3199 if (blp->b_flags & flags) 3200 return (TRUE); 3201 return (FALSE); 3202 } 3203 return (FALSE); 3204 } 3205 3206 /* 3207 * Queue a request to perform some sort of internally 3208 * generated command. When this request packet reaches 3209 * the front of the queue (*func)() is invoked. 3210 * 3211 */ 3212 3213 int 3214 ata_queue_cmd( 3215 int (*func)(ata_ctl_t *, ata_drv_t *, ata_pkt_t *), 3216 void *arg, 3217 ata_ctl_t *ata_ctlp, 3218 ata_drv_t *ata_drvp, 3219 gtgt_t *gtgtp) 3220 { 3221 ata_pkt_t *ata_pktp; 3222 gcmd_t *gcmdp; 3223 int rc; 3224 3225 if (!(gcmdp = ghd_gcmd_alloc(gtgtp, sizeof (*ata_pktp), TRUE))) { 3226 ADBG_ERROR(("atapi_id_update alloc failed\n")); 3227 return (FALSE); 3228 } 3229 3230 3231 /* set the back ptr from the ata_pkt to the gcmd_t */ 3232 ata_pktp = GCMD2APKT(gcmdp); 3233 ata_pktp->ap_gcmdp = gcmdp; 3234 ata_pktp->ap_hd = ata_drvp->ad_drive_bits; 3235 ata_pktp->ap_bytes_per_block = ata_drvp->ad_bytes_per_block; 3236 3237 /* 3238 * over-ride the default start function 3239 */ 3240 ata_pktp = GCMD2APKT(gcmdp); 3241 ata_pktp->ap_start = func; 3242 ata_pktp->ap_complete = NULL; 3243 ata_pktp->ap_v_addr = (caddr_t)arg; 3244 3245 /* 3246 * add it to the queue, when it gets to the front the 3247 * ap_start function is called. 3248 */ 3249 rc = ghd_transport(&ata_ctlp->ac_ccc, gcmdp, gcmdp->cmd_gtgtp, 3250 0, TRUE, NULL); 3251 3252 if (rc != TRAN_ACCEPT) { 3253 /* this should never, ever happen */ 3254 return (FALSE); 3255 } 3256 3257 if (ata_pktp->ap_flags & AP_ERROR) 3258 return (FALSE); 3259 return (TRUE); 3260 } 3261 3262 /* 3263 * Check if this drive has the "revert to defaults" bug 3264 * PSARC 2001/500 and 2001/xxx - check for the properties 3265 * ata-revert-to-defaults and atarvrt-<diskmodel> before 3266 * examining the blacklist. 3267 * <diskmodel> is made from the model number reported by Identify Drive 3268 * with uppercase letters converted to lowercase and all characters 3269 * except letters, digits, ".", "_", and "-" deleted. 3270 * Return value: 3271 * TRUE: enable revert to defaults 3272 * FALSE: disable revert to defaults 3273 * 3274 * NOTE: revert to power on defaults that includes reverting to MDMA 3275 * mode is allowed by ATA-6 & ATA-7 specs. 3276 * Therefore drives exhibiting this behaviour are not violating the spec. 3277 * Furthermore, the spec explicitly says that after the soft reset 3278 * host should check the current setting of the device features. 3279 * Correctly working BIOS would therefore reprogram either the drive 3280 * and/or the host controller to match transfer modes. 3281 * Devices with ATA_BL_NORVRT flag will be removed from 3282 * the ata_blacklist. 3283 * The default behaviour will be - no revert to power-on defaults 3284 * for all devices. The property is retained in case the user 3285 * explicitly requests revert-to-defaults before reboot. 3286 */ 3287 3288 #define ATA_REVERT_PROP_PREFIX "revert-" 3289 #define ATA_REVERT_PROP_GLOBAL "ata-revert-to-defaults" 3290 /* room for prefix + model number + terminating NUL character */ 3291 #define PROP_BUF_SIZE (sizeof (ATA_REVERT_PROP_PREFIX) + \ 3292 sizeof (aidp->ai_model) + 1) 3293 #define PROP_LEN_MAX (31) 3294 3295 static int 3296 ata_check_revert_to_defaults( 3297 ata_drv_t *ata_drvp) 3298 { 3299 struct ata_id *aidp = &ata_drvp->ad_id; 3300 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp; 3301 char prop_buf[PROP_BUF_SIZE]; 3302 int i, j; 3303 int propval; 3304 3305 /* put prefix into the buffer */ 3306 (void) strcpy(prop_buf, ATA_REVERT_PROP_PREFIX); 3307 j = strlen(prop_buf); 3308 3309 /* append the model number, leaving out invalid characters */ 3310 for (i = 0; i < sizeof (aidp->ai_model); ++i) { 3311 char c = aidp->ai_model[i]; 3312 if (c >= 'A' && c <= 'Z') /* uppercase -> lower */ 3313 c = c - 'A' + 'a'; 3314 if (c >= 'a' && c <= 'z' || c >= '0' && c <= '9' || 3315 c == '.' || c == '_' || c == '-') 3316 prop_buf[j++] = c; 3317 if (c == '\0') 3318 break; 3319 } 3320 3321 /* make sure there's a terminating NUL character */ 3322 if (j >= PROP_LEN_MAX) 3323 j = PROP_LEN_MAX; 3324 prop_buf[j] = '\0'; 3325 3326 /* look for a disk-specific "revert" property" */ 3327 propval = ddi_getprop(DDI_DEV_T_ANY, ata_ctlp->ac_dip, 3328 DDI_PROP_DONTPASS, prop_buf, -1); 3329 if (propval == 0) 3330 return (FALSE); 3331 else if (propval != -1) 3332 return (TRUE); 3333 3334 /* look for a global "revert" property" */ 3335 propval = ddi_getprop(DDI_DEV_T_ANY, ata_ctlp->ac_dip, 3336 0, ATA_REVERT_PROP_GLOBAL, -1); 3337 if (propval == 0) 3338 return (FALSE); 3339 else if (propval != -1) 3340 return (TRUE); 3341 3342 return (FALSE); 3343 } 3344 3345 void 3346 ata_show_transfer_mode(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp) 3347 { 3348 int i; 3349 3350 if (ata_ctlp->ac_pciide_bm == FALSE || 3351 ata_drvp->ad_pciide_dma != ATA_DMA_ON) { 3352 if (ata_cntrl_DMA_sel_msg) { 3353 ATAPRT(( 3354 "?\tATA DMA off: %s\n", ata_cntrl_DMA_sel_msg)); 3355 } else if (ata_dev_DMA_sel_msg) { 3356 ATAPRT(("?\tATA DMA off: %s\n", ata_dev_DMA_sel_msg)); 3357 } 3358 ATAPRT(("?\tPIO mode %d selected\n", 3359 (ata_drvp->ad_id.ai_advpiomode & ATAC_ADVPIO_4_SUP) == 3360 ATAC_ADVPIO_4_SUP ? 4 : 3)); 3361 } else { 3362 /* Using DMA */ 3363 if (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_SEL_MASK) { 3364 /* 3365 * Rely on the fact that either dwdma or udma is 3366 * selected, not both. 3367 */ 3368 ATAPRT(("?\tMultiwordDMA mode %d selected\n", 3369 (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_2_SEL) == 3370 ATAC_MDMA_2_SEL ? 2 : 3371 (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_1_SEL) == 3372 ATAC_MDMA_1_SEL ? 1 : 0)); 3373 } else { 3374 for (i = 0; i <= 6; i++) { 3375 if (ata_drvp->ad_id.ai_ultradma & 3376 (1 << (i + 8))) { 3377 ATAPRT(( 3378 "?\tUltraDMA mode %d selected\n", 3379 i)); 3380 break; 3381 } 3382 } 3383 } 3384 } 3385 } 3386 3387 /* 3388 * Controller-specific operation pointers. 3389 * Should be extended as needed - init only for now 3390 */ 3391 struct ata_ctl_spec_ops { 3392 uint_t (*cs_init)(dev_info_t *, ushort_t, ushort_t); /* ctlr init */ 3393 }; 3394 3395 3396 struct ata_ctl_spec { 3397 ushort_t cs_vendor_id; 3398 ushort_t cs_device_id; 3399 struct ata_ctl_spec_ops *cs_ops; 3400 }; 3401 3402 /* Sil3XXX-specific functions (init only for now) */ 3403 struct ata_ctl_spec_ops sil3xxx_ops = { 3404 &sil3xxx_init_controller /* Sil3XXX cntrl initialization */ 3405 }; 3406 3407 3408 struct ata_ctl_spec ata_cntrls_spec[] = { 3409 {0x1095, 0x3114, &sil3xxx_ops}, 3410 {0x1095, 0x3512, &sil3xxx_ops}, 3411 {0x1095, 0x3112, &sil3xxx_ops}, 3412 {0, 0, NULL} /* List must end with cs_ops set to NULL */ 3413 }; 3414 3415 /* 3416 * Do controller specific initialization if necessary. 3417 * Pick-up controller specific functions. 3418 */ 3419 3420 int 3421 ata_spec_init_controller(dev_info_t *dip) 3422 { 3423 ushort_t vendor_id; 3424 ushort_t device_id; 3425 struct ata_ctl_spec *ctlsp; 3426 3427 vendor_id = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3428 DDI_PROP_DONTPASS, "vendor-id", 0); 3429 device_id = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3430 DDI_PROP_DONTPASS, "device-id", 0); 3431 3432 /* Locate controller specific ops, if they exist */ 3433 ctlsp = ata_cntrls_spec; 3434 while (ctlsp->cs_ops != NULL) { 3435 if (ctlsp->cs_vendor_id == vendor_id && 3436 ctlsp->cs_device_id == device_id) 3437 break; 3438 ctlsp++; 3439 } 3440 3441 if (ctlsp->cs_ops != NULL) { 3442 if (ctlsp->cs_ops->cs_init != NULL) { 3443 /* Initialize controller */ 3444 if ((*(ctlsp->cs_ops->cs_init)) 3445 (dip, vendor_id, device_id) != TRUE) { 3446 cmn_err(CE_WARN, 3447 "pci%4x,%4x cntrl specific " 3448 "initialization failed", 3449 vendor_id, device_id); 3450 return (FALSE); 3451 } 3452 } 3453 } 3454 return (TRUE); 3455 } 3456 3457 /* 3458 * this routine works like ddi_prop_get_int, except that it works on 3459 * a string property that contains ascii representations 3460 * of an integer. 3461 * If the property is not found, the default value is returned. 3462 */ 3463 static int 3464 ata_prop_lookup_int(dev_t match_dev, dev_info_t *dip, 3465 uint_t flags, char *name, int defvalue) 3466 { 3467 3468 char *bufp, *cp; 3469 int rc = defvalue; 3470 int proprc; 3471 3472 proprc = ddi_prop_lookup_string(match_dev, dip, 3473 flags, name, &bufp); 3474 3475 if (proprc == DDI_PROP_SUCCESS) { 3476 cp = bufp; 3477 rc = stoi(&cp); 3478 ddi_prop_free(bufp); 3479 } else { 3480 /* 3481 * see if property is encoded as an int instead of string. 3482 */ 3483 rc = ddi_prop_get_int(match_dev, dip, flags, name, defvalue); 3484 } 3485 3486 return (rc); 3487 } 3488 3489 /* 3490 * Initialize the power management components 3491 */ 3492 static void 3493 ata_init_pm(dev_info_t *dip) 3494 { 3495 char pmc_name[16]; 3496 char *pmc[] = { 3497 NULL, 3498 "0=Sleep (PCI D3 State)", 3499 "3=PowerOn (PCI D0 State)", 3500 NULL 3501 }; 3502 int instance; 3503 ata_ctl_t *ata_ctlp; 3504 3505 3506 instance = ddi_get_instance(dip); 3507 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3508 ata_ctlp->ac_pm_support = 0; 3509 3510 /* check PCI capabilities */ 3511 if (!ata_is_pci(dip)) 3512 return; 3513 3514 (void) sprintf(pmc_name, "NAME=ata%d", instance); 3515 pmc[0] = pmc_name; 3516 3517 #ifdef ATA_USE_AUTOPM 3518 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, dip, 3519 "pm-components", pmc, 3) != DDI_PROP_SUCCESS) { 3520 return; 3521 } 3522 #endif 3523 3524 ata_ctlp->ac_pm_support = 1; 3525 ata_ctlp->ac_pm_level = PM_LEVEL_D0; 3526 3527 ATA_BUSY_COMPONENT(dip, 0); 3528 if (ATA_RAISE_POWER(dip, 0, PM_LEVEL_D0) != DDI_SUCCESS) { 3529 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "pm-components"); 3530 } 3531 ATA_IDLE_COMPONENT(dip, 0); 3532 } 3533 3534 /* 3535 * resume the hard drive 3536 */ 3537 static void 3538 ata_resume_drive(ata_drv_t *ata_drvp) 3539 { 3540 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp; 3541 int drive_type; 3542 struct ata_id id; 3543 3544 ADBG_TRACE(("ata_resume_drive entered\n")); 3545 3546 drive_type = ata_drive_type(ata_drvp->ad_drive_bits, 3547 ata_ctlp->ac_iohandle1, ata_ctlp->ac_ioaddr1, 3548 ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2, 3549 &id); 3550 if (drive_type == ATA_DEV_NONE) 3551 return; 3552 3553 if (!ATAPIDRV(ata_drvp)) { 3554 /* Reset Ultra DMA mode */ 3555 ata_reset_dma_mode(ata_drvp); 3556 if (!ata_disk_setup_parms(ata_ctlp, ata_drvp)) 3557 return; 3558 } else { 3559 (void) atapi_init_drive(ata_drvp); 3560 if (ata_drvp->ad_dma_mode != 0) { 3561 (void) atapi_reset_dma_mode(ata_drvp, FALSE); 3562 if (!ata_check_dma_mode(ata_drvp)) 3563 atapi_reset_dma_mode(ata_drvp, TRUE); 3564 if (ata_drvp->ad_id.ai_ultradma != 3565 ata_drvp->ad_dma_mode) { 3566 ata_drvp->ad_pciide_dma = ATA_DMA_OFF; 3567 } else { 3568 ata_drvp->ad_pciide_dma = ATA_DMA_ON; 3569 } 3570 } 3571 } 3572 (void) ata_set_feature(ata_ctlp, ata_drvp, ATSF_DIS_REVPOD, 0); 3573 3574 } 3575 3576 /* 3577 * resume routine, it will be run when get the command 3578 * DDI_RESUME at attach(9E) from system power management 3579 */ 3580 static int 3581 ata_resume(dev_info_t *dip) 3582 { 3583 int instance; 3584 ata_ctl_t *ata_ctlp; 3585 ddi_acc_handle_t io_hdl2; 3586 caddr_t ioaddr2; 3587 3588 instance = ddi_get_instance(dip); 3589 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3590 3591 if (!ata_ctlp->ac_pm_support) 3592 return (DDI_FAILURE); 3593 if (ata_ctlp->ac_pm_level == PM_LEVEL_D0) 3594 return (DDI_SUCCESS); 3595 3596 ATA_BUSY_COMPONENT(dip, 0); 3597 if (ATA_RAISE_POWER(dip, 0, PM_LEVEL_D0) == DDI_FAILURE) 3598 return (DDI_FAILURE); 3599 ATA_IDLE_COMPONENT(dip, 0); 3600 3601 /* enable interrupts from the device */ 3602 io_hdl2 = ata_ctlp->ac_iohandle2; 3603 ioaddr2 = ata_ctlp->ac_ioaddr2; 3604 ddi_put8(io_hdl2, (uchar_t *)ioaddr2 + AT_DEVCTL, ATDC_D3); 3605 ata_ctlp->ac_pm_level = PM_LEVEL_D0; 3606 3607 return (DDI_SUCCESS); 3608 } 3609 3610 /* 3611 * suspend routine, it will be run when get the command 3612 * DDI_SUSPEND at detach(9E) from system power management 3613 */ 3614 static int 3615 ata_suspend(dev_info_t *dip) 3616 { 3617 int instance; 3618 ata_ctl_t *ata_ctlp; 3619 ddi_acc_handle_t io_hdl2; 3620 3621 instance = ddi_get_instance(dip); 3622 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3623 3624 if (!ata_ctlp->ac_pm_support) 3625 return (DDI_FAILURE); 3626 if (ata_ctlp->ac_pm_level == PM_LEVEL_D3) 3627 return (DDI_SUCCESS); 3628 3629 /* disable interrupts and turn the software reset bit on */ 3630 io_hdl2 = ata_ctlp->ac_iohandle2; 3631 ddi_put8(io_hdl2, ata_ctlp->ac_devctl, (ATDC_D3 | ATDC_SRST)); 3632 3633 (void) ata_reset_bus(ata_ctlp); 3634 (void) ata_change_power(dip, ATC_SLEEP); 3635 ata_ctlp->ac_pm_level = PM_LEVEL_D3; 3636 return (DDI_SUCCESS); 3637 } 3638 3639 int ata_save_pci_config = 0; 3640 /* 3641 * ata specific power management entry point, it was 3642 * used to change the power management component 3643 */ 3644 static int 3645 ata_power(dev_info_t *dip, int component, int level) 3646 { 3647 int instance; 3648 ata_ctl_t *ata_ctlp; 3649 uint8_t cmd; 3650 3651 ADBG_TRACE(("ata_power entered, component = %d, level = %d\n", 3652 component, level)); 3653 3654 instance = ddi_get_instance(dip); 3655 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3656 if (ata_ctlp == NULL || component != 0) 3657 return (DDI_FAILURE); 3658 3659 if (!ata_ctlp->ac_pm_support) 3660 return (DDI_FAILURE); 3661 3662 if (ata_ctlp->ac_pm_level == level) 3663 return (DDI_SUCCESS); 3664 3665 switch (level) { 3666 case PM_LEVEL_D0: 3667 if (ata_save_pci_config) 3668 (void) pci_restore_config_regs(dip); 3669 ata_ctlp->ac_pm_level = PM_LEVEL_D0; 3670 cmd = ATC_IDLE_IMMED; 3671 break; 3672 case PM_LEVEL_D3: 3673 if (ata_save_pci_config) 3674 (void) pci_save_config_regs(dip); 3675 ata_ctlp->ac_pm_level = PM_LEVEL_D3; 3676 cmd = ATC_SLEEP; 3677 break; 3678 default: 3679 return (DDI_FAILURE); 3680 } 3681 return (ata_change_power(dip, cmd)); 3682 } 3683 3684 /* 3685 * sent commands to ata controller to change the power level 3686 */ 3687 static int 3688 ata_change_power(dev_info_t *dip, uint8_t cmd) 3689 { 3690 int instance; 3691 ata_ctl_t *ata_ctlp; 3692 ata_drv_t *ata_drvp; 3693 uchar_t targ; 3694 struct ata_id id; 3695 uchar_t lun; 3696 uchar_t lastlun; 3697 struct ata_id *aidp; 3698 3699 ADBG_TRACE(("ata_change_power entered, cmd = %d\n", cmd)); 3700 3701 instance = ddi_get_instance(dip); 3702 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3703 3704 /* 3705 * Issue command on each disk device on the bus. 3706 */ 3707 if (cmd == ATC_SLEEP) { 3708 for (targ = 0; targ < ATA_MAXTARG; targ++) { 3709 ata_drvp = CTL2DRV(ata_ctlp, targ, 0); 3710 if (ata_drvp == NULL) 3711 continue; 3712 if (ata_drvp->ad_dma_cap == 0 && 3713 ata_drvp->ad_pciide_dma == ATA_DMA_ON) { 3714 aidp = &ata_drvp->ad_id; 3715 if ((aidp->ai_validinfo & ATAC_VALIDINFO_83) && 3716 (aidp->ai_ultradma & ATAC_UDMA_SEL_MASK)) { 3717 ata_drvp->ad_dma_cap = 3718 ATA_DMA_ULTRAMODE; 3719 ata_drvp->ad_dma_mode = 3720 aidp->ai_ultradma; 3721 } else if (aidp->ai_dworddma & 3722 ATAC_MDMA_SEL_MASK) { 3723 ata_drvp->ad_dma_cap = 3724 ATA_DMA_MWORDMODE; 3725 ata_drvp->ad_dma_mode = 3726 aidp->ai_dworddma; 3727 } 3728 } 3729 if (ata_drive_type(ata_drvp->ad_drive_bits, 3730 ata_ctlp->ac_iohandle1, ata_ctlp->ac_ioaddr1, 3731 ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2, 3732 &id) != ATA_DEV_DISK) 3733 continue; 3734 (void) ata_flush_cache(ata_ctlp, ata_drvp); 3735 if (!ata_command(ata_ctlp, ata_drvp, TRUE, TRUE, 3736 5 * 1000000, cmd, 0, 0, 0, 0, 0, 0)) { 3737 cmn_err(CE_WARN, "!ata_controller - Can not " 3738 "put drive %d in to power mode %u", 3739 targ, cmd); 3740 (void) ata_devo_reset(dip, DDI_RESET_FORCE); 3741 return (DDI_FAILURE); 3742 } 3743 } 3744 return (DDI_SUCCESS); 3745 } 3746 3747 (void) ata_software_reset(ata_ctlp); 3748 for (targ = 0; targ < ATA_MAXTARG; targ++) { 3749 ata_drvp = CTL2DRV(ata_ctlp, targ, 0); 3750 if (ata_drvp == NULL) 3751 continue; 3752 ata_resume_drive(ata_drvp); 3753 3754 if (ATAPIDRV(ata_drvp)) 3755 lastlun = ata_drvp->ad_id.ai_lastlun; 3756 else 3757 lastlun = 0; 3758 if (!ata_enable_atapi_luns) 3759 lastlun = 0; 3760 for (lun = 1; lun <= lastlun && lun < ATA_MAXLUN; lun++) { 3761 ata_drvp = CTL2DRV(ata_ctlp, targ, lun); 3762 if (ata_drvp != NULL) 3763 ata_resume_drive(ata_drvp); 3764 } 3765 } 3766 3767 return (DDI_SUCCESS); 3768 } 3769 3770 /* 3771 * return 1 when ata controller is a pci device, 3772 * otherwise return 0 3773 */ 3774 static int 3775 ata_is_pci(dev_info_t *dip) 3776 { 3777 int rc; 3778 char *bufp; 3779 int ispci; 3780 3781 rc = ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_get_parent(dip), 3782 DDI_PROP_DONTPASS, "device_type", &bufp); 3783 3784 if (rc != DDI_PROP_SUCCESS) { 3785 ADBG_ERROR(("ata_is_pci !device_type\n")); 3786 return (0); 3787 } 3788 3789 ispci = (strcmp(bufp, "pci-ide") == 0); 3790 3791 ddi_prop_free(bufp); 3792 3793 return (ispci); 3794 } 3795 3796 /* 3797 * Disable DMA for this drive 3798 */ 3799 static void 3800 ata_disable_DMA(ata_drv_t *ata_drvp) 3801 { 3802 struct ata_id *aidp; 3803 char buf[sizeof (aidp->ai_model) +2]; 3804 int i; 3805 3806 if (ata_drvp == NULL) 3807 return; 3808 3809 if (ata_drvp->ad_pciide_dma == ATA_DMA_OFF) 3810 return; 3811 3812 ata_drvp->ad_pciide_dma = ATA_DMA_OFF; 3813 3814 /* Print the message */ 3815 buf[0] = '\0'; 3816 aidp = &ata_drvp->ad_id; 3817 if (aidp != NULL) { 3818 (void) strncpy(buf, aidp->ai_model, sizeof (aidp->ai_model)); 3819 buf[sizeof (aidp->ai_model) -1] = '\0'; 3820 for (i = sizeof (aidp->ai_model) - 2; buf[i] == ' '; i--) 3821 buf[i] = '\0'; 3822 } 3823 cmn_err(CE_CONT, 3824 "?DMA disabled on %s target=%d, lun=%d due to DMA errors,", 3825 buf, ata_drvp->ad_targ, ata_drvp->ad_lun); 3826 cmn_err(CE_CONT, "?most likely due to the CF-to-IDE adapter."); 3827 } 3828 3829 /* 3830 * Check and select DMA mode 3831 * 3832 * TRUE is returned when set feature is called successfully, 3833 * otherwise return FALSE 3834 */ 3835 int 3836 ata_set_dma_mode(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp) 3837 { 3838 struct ata_id *aidp; 3839 int mode, rval = FALSE; 3840 uint8_t subcmd; 3841 3842 aidp = &ata_drvp->ad_id; 3843 3844 /* Return directly if DMA is not supported */ 3845 if (!(aidp->ai_cap & ATAC_DMA_SUPPORT)) 3846 return (rval); 3847 3848 /* Return if DMA mode is already selected */ 3849 if (((aidp->ai_validinfo & ATAC_VALIDINFO_83) && 3850 (aidp->ai_ultradma & ATAC_UDMA_SEL_MASK)) || 3851 (aidp->ai_dworddma & ATAC_MDMA_SEL_MASK)) 3852 return (rval); 3853 3854 /* First check Ultra DMA mode if no DMA is selected */ 3855 if ((aidp->ai_validinfo & ATAC_VALIDINFO_83) && 3856 (aidp->ai_ultradma & ATAC_UDMA_SUP_MASK)) { 3857 for (mode = 6; mode >= 0; --mode) { 3858 if (aidp->ai_ultradma & (1 << mode)) 3859 break; 3860 } 3861 subcmd = ATF_XFRMOD_UDMA; 3862 3863 } else if (aidp->ai_dworddma & ATAC_MDMA_SUP_MASK) { 3864 /* Then check multi-word DMA mode */ 3865 for (mode = 2; mode >= 0; --mode) { 3866 if (aidp->ai_dworddma & (1 << mode)) 3867 break; 3868 } 3869 subcmd = ATF_XFRMOD_MDMA; 3870 3871 } else { 3872 return (rval); 3873 } 3874 3875 rval = ata_set_feature(ata_ctlp, ata_drvp, ATSF_SET_XFRMOD, 3876 subcmd|mode); 3877 3878 return (rval); 3879 } 3880 3881 /* 3882 * Reset Ultra DMA mode / MWDMA mode 3883 */ 3884 void 3885 ata_reset_dma_mode(ata_drv_t *ata_drvp) 3886 { 3887 uint8_t subcmd; 3888 int mode; 3889 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp; 3890 3891 switch (ata_drvp->ad_dma_cap) { 3892 case ATA_DMA_ULTRAMODE: 3893 subcmd = ATF_XFRMOD_UDMA; 3894 for (mode = 0; mode <= 6; mode++) { 3895 if (ata_drvp->ad_dma_mode & (1 << (mode + 8))) 3896 break; 3897 } 3898 break; 3899 case ATA_DMA_MWORDMODE: 3900 subcmd = ATF_XFRMOD_MDMA; 3901 mode = ((ata_drvp->ad_dma_mode & ATAC_MDMA_2_SEL) == 3902 ATAC_MDMA_2_SEL ? 2 : 3903 (ata_drvp->ad_dma_mode & ATAC_MDMA_1_SEL) == 3904 ATAC_MDMA_1_SEL ? 1 : 0); 3905 break; 3906 default: 3907 return; 3908 } 3909 3910 (void) ata_set_feature(ata_ctlp, ata_drvp, ATSF_SET_XFRMOD, 3911 (subcmd | mode)); 3912 } 3913 3914 /* 3915 * Check DMA mode is the same with saved info 3916 * return value: 0 - not same 3917 * 1 - same 3918 */ 3919 static int 3920 ata_check_dma_mode(ata_drv_t *ata_drvp) 3921 { 3922 struct ata_id *aidp; 3923 3924 aidp = &ata_drvp->ad_id; 3925 switch (ata_drvp->ad_dma_cap) { 3926 case ATA_DMA_ULTRAMODE: 3927 if ((aidp->ai_validinfo & ATAC_VALIDINFO_83) && 3928 (aidp->ai_ultradma & ATAC_UDMA_SEL_MASK) && 3929 (aidp->ai_ultradma == ata_drvp->ad_dma_mode)) 3930 break; 3931 else 3932 return (0); 3933 case ATA_DMA_MWORDMODE: 3934 if ((aidp->ai_dworddma & ATAC_MDMA_SEL_MASK) && 3935 (aidp->ai_dworddma == ata_drvp->ad_dma_mode)) 3936 break; 3937 else 3938 return (0); 3939 default: 3940 return (0); 3941 } 3942 return (1); 3943 } 3944