1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/modctl.h> 31 #include <sys/debug.h> 32 #include <sys/promif.h> 33 #include <sys/pci.h> 34 #include <sys/errno.h> 35 #include <sys/open.h> 36 #include <sys/uio.h> 37 #include <sys/cred.h> 38 #include <sys/cpu.h> 39 #include "ata_common.h" 40 #include "ata_disk.h" 41 #include "atapi.h" 42 #include "ata_blacklist.h" 43 #include "sil3xxx.h" 44 45 /* 46 * Solaris Entry Points. 47 */ 48 49 static int ata_probe(dev_info_t *dip); 50 static int ata_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 51 static int ata_detach(dev_info_t *dip, ddi_detach_cmd_t cmd); 52 static int ata_bus_ctl(dev_info_t *d, dev_info_t *r, ddi_ctl_enum_t o, 53 void *a, void *v); 54 static uint_t ata_intr(caddr_t arg); 55 56 /* 57 * GHD Entry points 58 */ 59 60 static int ata_get_status(void *hba_handle, void *intr_status); 61 static void ata_process_intr(void *hba_handle, void *intr_status); 62 static int ata_hba_start(void *handle, gcmd_t *gcmdp); 63 static void ata_hba_complete(void *handle, gcmd_t *gcmdp, int do_callback); 64 static int ata_timeout_func(void *hba_handle, gcmd_t *gcmdp, 65 gtgt_t *gtgtp, gact_t action, int calltype); 66 67 /* 68 * Local Function Prototypes 69 */ 70 static int ata_prop_lookup_int(dev_t match_dev, dev_info_t *dip, 71 uint_t flags, char *name, int defvalue); 72 static int ata_ctlr_fsm(uchar_t fsm_func, ata_ctl_t *ata_ctlp, 73 ata_drv_t *ata_drvp, ata_pkt_t *ata_pktp, 74 int *DoneFlgp); 75 static void ata_destroy_controller(dev_info_t *dip); 76 static int ata_drive_type(uchar_t drvhd, 77 ddi_acc_handle_t io_hdl1, caddr_t ioaddr1, 78 ddi_acc_handle_t io_hdl2, caddr_t ioaddr2, 79 struct ata_id *ata_id_bufp); 80 static ata_ctl_t *ata_init_controller(dev_info_t *dip); 81 static ata_drv_t *ata_init_drive(ata_ctl_t *ata_ctlp, 82 uchar_t targ, uchar_t lun); 83 static int ata_init_drive_pcidma(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 84 dev_info_t *tdip); 85 static int ata_flush_cache(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp); 86 static void ata_init_pciide(dev_info_t *dip, ata_ctl_t *ata_ctlp); 87 static int ata_reset_bus(ata_ctl_t *ata_ctlp); 88 static int ata_setup_ioaddr(dev_info_t *dip, 89 ddi_acc_handle_t *iohandle1, caddr_t *ioaddr1p, 90 ddi_acc_handle_t *iohandle2, caddr_t *ioaddr2p, 91 ddi_acc_handle_t *bm_hdlp, caddr_t *bm_addrp); 92 static int ata_software_reset(ata_ctl_t *ata_ctlp); 93 static int ata_start_arq(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 94 ata_pkt_t *ata_pktp); 95 static int ata_strncmp(char *p1, char *p2, int cnt); 96 static void ata_uninit_drive(ata_drv_t *ata_drvp); 97 98 static int ata_check_pciide_blacklist(dev_info_t *dip, uint_t flags); 99 static int ata_check_revert_to_defaults(ata_drv_t *ata_drvp); 100 static void ata_show_transfer_mode(ata_ctl_t *, ata_drv_t *); 101 static int ata_spec_init_controller(dev_info_t *dip); 102 103 104 /* 105 * Local static data 106 */ 107 static void *ata_state; 108 109 static tmr_t ata_timer_conf; /* single timeout list for all instances */ 110 static int ata_watchdog_usec = 100000; /* check timeouts every 100 ms */ 111 112 int ata_hba_start_watchdog = 1000; 113 int ata_process_intr_watchdog = 1000; 114 int ata_reset_bus_watchdog = 1000; 115 116 117 /* 118 * number of seconds to wait during various operations 119 */ 120 int ata_flush_delay = 5 * 1000000; 121 uint_t ata_set_feature_wait = 4 * 1000000; 122 uint_t ata_flush_cache_wait = 60 * 1000000; /* may take a long time */ 123 124 /* 125 * Change this for SFF-8070i support. Currently SFF-8070i is 126 * using a field in the IDENTIFY PACKET DEVICE response which 127 * already seems to be in use by some vendor's drives. I suspect 128 * SFF will either move their laslun field or provide a reliable 129 * way to validate it. 130 */ 131 int ata_enable_atapi_luns = FALSE; 132 133 /* 134 * set this to disable all DMA requests 135 */ 136 int ata_dma_disabled = FALSE; 137 138 /* 139 * set this to TRUE to enable storing the IDENTIFY DEVICE result in the 140 * "ata" or "atapi" property. 141 */ 142 int ata_id_debug = FALSE; 143 144 /* 145 * set this to TRUE to enable logging device-capability data 146 */ 147 int ata_capability_data = FALSE; 148 149 /* 150 * DMA selection message pointers 151 */ 152 char *ata_cntrl_DMA_sel_msg; 153 char *ata_dev_DMA_sel_msg; 154 155 /* 156 * bus nexus operations 157 */ 158 static struct bus_ops ata_bus_ops; 159 static struct bus_ops *scsa_bus_ops_p; 160 161 /* ARGSUSED */ 162 static int 163 ata_open(dev_t *devp, int flag, int otyp, cred_t *cred_p) 164 { 165 if (ddi_get_soft_state(ata_state, getminor(*devp)) == NULL) 166 return (ENXIO); 167 168 return (0); 169 } 170 171 /* 172 * The purpose of this function is to pass the ioaddress of the controller 173 * to the caller, specifically used for upgrade from pre-pciide 174 * to pciide nodes 175 */ 176 /* ARGSUSED */ 177 static int 178 ata_read(dev_t dev, struct uio *uio_p, cred_t *cred_p) 179 { 180 ata_ctl_t *ata_ctlp; 181 char buf[18]; 182 long len; 183 184 ata_ctlp = ddi_get_soft_state(ata_state, getminor(dev)); 185 186 if (ata_ctlp == NULL) 187 return (ENXIO); 188 189 (void) sprintf(buf, "%p\n", (void *) ata_ctlp->ac_ioaddr1); 190 191 len = strlen(buf) - uio_p->uio_offset; 192 len = min(uio_p->uio_resid, len); 193 if (len <= 0) 194 return (0); 195 196 return (uiomove((caddr_t)(buf + uio_p->uio_offset), len, 197 UIO_READ, uio_p)); 198 } 199 200 int 201 ata_devo_reset( 202 dev_info_t *dip, 203 ddi_reset_cmd_t cmd) 204 { 205 ata_ctl_t *ata_ctlp; 206 ata_drv_t *ata_drvp; 207 int instance; 208 int i; 209 int rc; 210 int flush_okay; 211 212 if (cmd != DDI_RESET_FORCE) 213 return (0); 214 215 instance = ddi_get_instance(dip); 216 ata_ctlp = ddi_get_soft_state(ata_state, instance); 217 218 if (!ata_ctlp) 219 return (0); 220 221 /* 222 * reset ATA drives and flush the write cache of any drives 223 */ 224 flush_okay = TRUE; 225 for (i = 0; i < ATA_MAXTARG; i++) { 226 if ((ata_drvp = CTL2DRV(ata_ctlp, i, 0)) == 0) 227 continue; 228 /* Don't revert to defaults for certain IBM drives */ 229 if ((ata_drvp->ad_flags & AD_DISK) != 0 && 230 ((ata_drvp->ad_flags & AD_NORVRT) == 0)) { 231 /* Enable revert to defaults when reset */ 232 (void) ata_set_feature(ata_ctlp, ata_drvp, 0xCC, 0); 233 } 234 235 /* 236 * skip flush cache if device type is cdrom 237 * 238 * notes: the structure definitions for ata_drvp->ad_id are 239 * defined for the ATA IDENTIFY_DEVICE, but if AD_ATAPI is set 240 * the struct holds data for the ATAPI IDENTIFY_PACKET_DEVICE 241 */ 242 if (!IS_CDROM(ata_drvp)) { 243 244 /* 245 * Try the ATA/ATAPI flush write cache command 246 */ 247 rc = ata_flush_cache(ata_ctlp, ata_drvp); 248 ADBG_WARN(("ata_flush_cache %s\n", 249 rc ? "okay" : "failed")); 250 251 if (!rc) 252 flush_okay = FALSE; 253 } 254 255 256 /* 257 * do something else if flush cache not supported 258 */ 259 } 260 261 /* 262 * just busy wait if any drive doesn't support FLUSH CACHE 263 */ 264 if (!flush_okay) 265 drv_usecwait(ata_flush_delay); 266 return (0); 267 } 268 269 270 static struct cb_ops ata_cb_ops = { 271 ata_open, /* open */ 272 nulldev, /* close */ 273 nodev, /* strategy */ 274 nodev, /* print */ 275 nodev, /* dump */ 276 ata_read, /* read */ 277 nodev, /* write */ 278 nodev, /* ioctl */ 279 nodev, /* devmap */ 280 nodev, /* mmap */ 281 nodev, /* segmap */ 282 nochpoll, /* chpoll */ 283 ddi_prop_op, /* prop_op */ 284 NULL, /* stream info */ 285 D_MP, /* driver compatibility flag */ 286 CB_REV, /* cb_ops revision */ 287 nodev, /* aread */ 288 nodev /* awrite */ 289 }; 290 291 static struct dev_ops ata_ops = { 292 DEVO_REV, /* devo_rev, */ 293 0, /* refcnt */ 294 ddi_getinfo_1to1, /* info */ 295 nulldev, /* identify */ 296 ata_probe, /* probe */ 297 ata_attach, /* attach */ 298 ata_detach, /* detach */ 299 ata_devo_reset, /* reset */ 300 &ata_cb_ops, /* driver operations */ 301 NULL /* bus operations */ 302 }; 303 304 /* driver loadable module wrapper */ 305 static struct modldrv modldrv = { 306 &mod_driverops, /* Type of module. This one is a driver */ 307 "ATA AT-bus attachment disk controller Driver", /* module name */ 308 &ata_ops, /* driver ops */ 309 }; 310 311 static struct modlinkage modlinkage = { 312 MODREV_1, (void *)&modldrv, NULL 313 }; 314 315 #ifdef ATA_DEBUG 316 int ata_debug_init = FALSE; 317 int ata_debug_probe = FALSE; 318 int ata_debug_attach = FALSE; 319 320 int ata_debug = ADBG_FLAG_ERROR 321 /* | ADBG_FLAG_ARQ */ 322 /* | ADBG_FLAG_INIT */ 323 /* | ADBG_FLAG_TRACE */ 324 /* | ADBG_FLAG_TRANSPORT */ 325 /* | ADBG_FLAG_WARN */ 326 ; 327 #endif 328 329 int 330 _init(void) 331 { 332 int err; 333 334 #ifdef ATA_DEBUG 335 if (ata_debug_init) 336 debug_enter("\nATA _INIT\n"); 337 #endif 338 339 if ((err = ddi_soft_state_init(&ata_state, sizeof (ata_ctl_t), 0)) != 0) 340 return (err); 341 342 if ((err = scsi_hba_init(&modlinkage)) != 0) { 343 ddi_soft_state_fini(&ata_state); 344 return (err); 345 } 346 347 /* save pointer to SCSA provided bus_ops struct */ 348 scsa_bus_ops_p = ata_ops.devo_bus_ops; 349 350 /* make a copy of SCSA bus_ops */ 351 ata_bus_ops = *(ata_ops.devo_bus_ops); 352 353 /* 354 * Modify our bus_ops to call our routines. Our implementation 355 * will determine if the device is ATA or ATAPI/SCSA and react 356 * accordingly. 357 */ 358 ata_bus_ops.bus_ctl = ata_bus_ctl; 359 360 /* patch our bus_ops into the dev_ops struct */ 361 ata_ops.devo_bus_ops = &ata_bus_ops; 362 363 if ((err = mod_install(&modlinkage)) != 0) { 364 scsi_hba_fini(&modlinkage); 365 ddi_soft_state_fini(&ata_state); 366 } 367 368 /* 369 * Initialize the per driver timer info. 370 */ 371 372 ghd_timer_init(&ata_timer_conf, drv_usectohz(ata_watchdog_usec)); 373 374 return (err); 375 } 376 377 int 378 _fini(void) 379 { 380 int err; 381 382 if ((err = mod_remove(&modlinkage)) == 0) { 383 ghd_timer_fini(&ata_timer_conf); 384 scsi_hba_fini(&modlinkage); 385 ddi_soft_state_fini(&ata_state); 386 } 387 388 return (err); 389 } 390 391 int 392 _info(struct modinfo *modinfop) 393 { 394 return (mod_info(&modlinkage, modinfop)); 395 } 396 397 398 /* driver probe entry point */ 399 400 static int 401 ata_probe( 402 dev_info_t *dip) 403 { 404 ddi_acc_handle_t io_hdl1 = NULL; 405 ddi_acc_handle_t io_hdl2 = NULL; 406 ddi_acc_handle_t bm_hdl = NULL; 407 caddr_t ioaddr1; 408 caddr_t ioaddr2; 409 caddr_t bm_addr; 410 int drive; 411 struct ata_id *ata_id_bufp; 412 int rc = DDI_PROBE_FAILURE; 413 414 ADBG_TRACE(("ata_probe entered\n")); 415 #ifdef ATA_DEBUG 416 if (ata_debug_probe) 417 debug_enter("\nATA_PROBE\n"); 418 #endif 419 420 if (!ata_setup_ioaddr(dip, &io_hdl1, &ioaddr1, &io_hdl2, &ioaddr2, 421 &bm_hdl, &bm_addr)) 422 return (rc); 423 424 ata_id_bufp = kmem_zalloc(sizeof (*ata_id_bufp), KM_SLEEP); 425 426 for (drive = 0; drive < ATA_MAXTARG; drive++) { 427 uchar_t drvhd; 428 429 /* set up drv/hd and feature registers */ 430 431 drvhd = (drive == 0 ? ATDH_DRIVE0 : ATDH_DRIVE1); 432 433 434 if (ata_drive_type(drvhd, io_hdl1, ioaddr1, io_hdl2, ioaddr2, 435 ata_id_bufp) != ATA_DEV_NONE) { 436 rc = (DDI_PROBE_SUCCESS); 437 break; 438 } 439 } 440 441 /* always leave the controller set to drive 0 */ 442 if (drive != 0) { 443 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_DRVHD, ATDH_DRIVE0); 444 ata_nsecwait(400); 445 } 446 447 out2: 448 kmem_free(ata_id_bufp, sizeof (*ata_id_bufp)); 449 450 if (io_hdl1) 451 ddi_regs_map_free(&io_hdl1); 452 if (io_hdl2) 453 ddi_regs_map_free(&io_hdl2); 454 if (bm_hdl) 455 ddi_regs_map_free(&bm_hdl); 456 return (rc); 457 } 458 459 /* 460 * 461 * driver attach entry point 462 * 463 */ 464 465 static int 466 ata_attach( 467 dev_info_t *dip, 468 ddi_attach_cmd_t cmd) 469 { 470 ata_ctl_t *ata_ctlp; 471 ata_drv_t *ata_drvp; 472 ata_drv_t *first_drvp = NULL; 473 uchar_t targ; 474 uchar_t lun; 475 uchar_t lastlun; 476 int atapi_count = 0; 477 int disk_count = 0; 478 479 ADBG_TRACE(("ata_attach entered\n")); 480 #ifdef ATA_DEBUG 481 if (ata_debug_attach) 482 debug_enter("\nATA_ATTACH\n\n"); 483 #endif 484 485 if (cmd != DDI_ATTACH) 486 return (DDI_FAILURE); 487 488 /* initialize controller */ 489 ata_ctlp = ata_init_controller(dip); 490 491 if (ata_ctlp == NULL) 492 goto errout; 493 494 mutex_enter(&ata_ctlp->ac_ccc.ccc_hba_mutex); 495 496 /* initialize drives */ 497 498 for (targ = 0; targ < ATA_MAXTARG; targ++) { 499 500 ata_drvp = ata_init_drive(ata_ctlp, targ, 0); 501 if (ata_drvp == NULL) 502 continue; 503 504 if (first_drvp == NULL) 505 first_drvp = ata_drvp; 506 507 if (ATAPIDRV(ata_drvp)) { 508 atapi_count++; 509 lastlun = ata_drvp->ad_id.ai_lastlun; 510 } else { 511 disk_count++; 512 lastlun = 0; 513 } 514 515 /* 516 * LUN support is currently disabled. Check with SFF-8070i 517 * before enabling. 518 */ 519 if (!ata_enable_atapi_luns) 520 lastlun = 0; 521 522 /* Initialize higher LUNs, if there are any */ 523 for (lun = 1; lun <= lastlun && lun < ATA_MAXLUN; lun++) { 524 if ((ata_drvp = 525 ata_init_drive(ata_ctlp, targ, lun)) != NULL) { 526 ata_show_transfer_mode(ata_ctlp, ata_drvp); 527 } 528 } 529 } 530 531 if ((atapi_count == 0) && (disk_count == 0)) { 532 ADBG_WARN(("ata_attach: no drives detected\n")); 533 goto errout1; 534 } 535 536 /* 537 * Always make certain that a valid drive is selected so 538 * that routines which poll the status register don't get 539 * confused by non-existent drives. 540 */ 541 ddi_put8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_drvhd, 542 first_drvp->ad_drive_bits); 543 ata_nsecwait(400); 544 545 /* 546 * make certain the drive selected 547 */ 548 if (!ata_wait(ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2, 549 0, ATS_BSY, 5000000)) { 550 ADBG_ERROR(("ata_attach: select failed\n")); 551 } 552 553 /* 554 * initialize atapi/ata_dsk modules if we have at least 555 * one drive of that type. 556 */ 557 558 if (atapi_count) { 559 if (!atapi_attach(ata_ctlp)) 560 goto errout1; 561 ata_ctlp->ac_flags |= AC_ATAPI_INIT; 562 } 563 564 if (disk_count) { 565 if (!ata_disk_attach(ata_ctlp)) 566 goto errout1; 567 ata_ctlp->ac_flags |= AC_DISK_INIT; 568 } 569 570 /* 571 * make certain the interrupt and error latches are clear 572 */ 573 if (ata_ctlp->ac_pciide) { 574 575 int instance = ddi_get_instance(dip); 576 if (ddi_create_minor_node(dip, "control", S_IFCHR, instance, 577 DDI_PSEUDO, 0) != DDI_SUCCESS) { 578 goto errout1; 579 } 580 581 (void) ata_pciide_status_clear(ata_ctlp); 582 583 } 584 585 /* 586 * enable the interrupt handler and drop the mutex 587 */ 588 ata_ctlp->ac_flags |= AC_ATTACHED; 589 mutex_exit(&ata_ctlp->ac_ccc.ccc_hba_mutex); 590 591 ddi_report_dev(dip); 592 return (DDI_SUCCESS); 593 594 errout1: 595 mutex_exit(&ata_ctlp->ac_ccc.ccc_hba_mutex); 596 errout: 597 (void) ata_detach(dip, DDI_DETACH); 598 return (DDI_FAILURE); 599 } 600 601 /* driver detach entry point */ 602 603 static int 604 ata_detach( 605 dev_info_t *dip, 606 ddi_detach_cmd_t cmd) 607 { 608 ata_ctl_t *ata_ctlp; 609 ata_drv_t *ata_drvp; 610 int instance; 611 int i; 612 int j; 613 614 ADBG_TRACE(("ata_detach entered\n")); 615 616 if (cmd != DDI_DETACH) 617 return (DDI_FAILURE); 618 619 instance = ddi_get_instance(dip); 620 ata_ctlp = ddi_get_soft_state(ata_state, instance); 621 622 if (!ata_ctlp) 623 return (DDI_SUCCESS); 624 625 ata_ctlp->ac_flags &= ~AC_ATTACHED; 626 627 /* destroy ata module */ 628 if (ata_ctlp->ac_flags & AC_DISK_INIT) 629 ata_disk_detach(ata_ctlp); 630 631 /* destroy atapi module */ 632 if (ata_ctlp->ac_flags & AC_ATAPI_INIT) 633 atapi_detach(ata_ctlp); 634 635 ddi_remove_minor_node(dip, NULL); 636 637 /* destroy drives */ 638 for (i = 0; i < ATA_MAXTARG; i++) { 639 for (j = 0; j < ATA_MAXLUN; j++) { 640 ata_drvp = CTL2DRV(ata_ctlp, i, j); 641 if (ata_drvp != NULL) 642 ata_uninit_drive(ata_drvp); 643 } 644 } 645 646 if (ata_ctlp->ac_iohandle1) 647 ddi_regs_map_free(&ata_ctlp->ac_iohandle1); 648 if (ata_ctlp->ac_iohandle2) 649 ddi_regs_map_free(&ata_ctlp->ac_iohandle2); 650 if (ata_ctlp->ac_bmhandle) 651 ddi_regs_map_free(&ata_ctlp->ac_bmhandle); 652 653 ddi_prop_remove_all(dip); 654 655 /* destroy controller */ 656 ata_destroy_controller(dip); 657 658 return (DDI_SUCCESS); 659 } 660 661 /* 662 * Nexus driver bus_ctl entry point 663 */ 664 /*ARGSUSED*/ 665 static int 666 ata_bus_ctl( 667 dev_info_t *d, 668 dev_info_t *r, 669 ddi_ctl_enum_t o, 670 void *a, 671 void *v) 672 { 673 dev_info_t *tdip; 674 int target_type; 675 int rc; 676 char *bufp; 677 678 ADBG_TRACE(("ata_bus_ctl entered\n")); 679 680 switch (o) { 681 682 case DDI_CTLOPS_SIDDEV: 683 return (DDI_FAILURE); 684 685 case DDI_CTLOPS_IOMIN: 686 687 /* 688 * Since we use PIO, we return a minimum I/O size of 689 * one byte. This will need to be updated when we 690 * implement DMA support 691 */ 692 693 *((int *)v) = 1; 694 return (DDI_SUCCESS); 695 696 case DDI_CTLOPS_DMAPMAPC: 697 case DDI_CTLOPS_REPORTINT: 698 case DDI_CTLOPS_REGSIZE: 699 case DDI_CTLOPS_NREGS: 700 case DDI_CTLOPS_SLAVEONLY: 701 case DDI_CTLOPS_AFFINITY: 702 case DDI_CTLOPS_POKE: 703 case DDI_CTLOPS_PEEK: 704 705 /* These ops shouldn't be called by a target driver */ 706 ADBG_ERROR(("ata_bus_ctl: %s%d: invalid op (%d) from %s%d\n", 707 ddi_driver_name(d), ddi_get_instance(d), o, 708 ddi_driver_name(r), ddi_get_instance(r))); 709 710 return (DDI_FAILURE); 711 712 case DDI_CTLOPS_REPORTDEV: 713 case DDI_CTLOPS_INITCHILD: 714 case DDI_CTLOPS_UNINITCHILD: 715 716 /* these require special handling below */ 717 break; 718 719 default: 720 return (ddi_ctlops(d, r, o, a, v)); 721 } 722 723 /* get targets dip */ 724 725 if (o == DDI_CTLOPS_INITCHILD || o == DDI_CTLOPS_UNINITCHILD) 726 tdip = (dev_info_t *)a; 727 else 728 tdip = r; 729 730 /* 731 * XXX - Get class of target 732 * Before the "class" entry in a conf file becomes 733 * a real property, we use an additional property 734 * tentatively called "class_prop". We will require that 735 * new classes (ie. direct) export "class_prop". 736 * SCSA target drivers will not have this property, so 737 * no property implies SCSA. 738 */ 739 if ((ddi_prop_lookup_string(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 740 "class", &bufp) == DDI_PROP_SUCCESS) || 741 (ddi_prop_lookup_string(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 742 "class_prop", &bufp) == DDI_PROP_SUCCESS)) { 743 if (strcmp(bufp, "dada") == 0) 744 target_type = ATA_DEV_DISK; 745 else if (strcmp(bufp, "scsi") == 0) 746 target_type = ATA_DEV_ATAPI; 747 else { 748 ADBG_WARN(("ata_bus_ctl: invalid target class %s\n", 749 bufp)); 750 ddi_prop_free(bufp); 751 return (DDI_FAILURE); 752 } 753 ddi_prop_free(bufp); 754 } else { 755 target_type = ATA_DEV_ATAPI; /* no class prop, assume SCSI */ 756 } 757 758 if (o == DDI_CTLOPS_INITCHILD) { 759 int instance = ddi_get_instance(d); 760 ata_ctl_t *ata_ctlp = ddi_get_soft_state(ata_state, instance); 761 ata_drv_t *ata_drvp; 762 int targ; 763 int lun; 764 int drive_type; 765 char *disk_prop; 766 char *class_prop; 767 768 if (ata_ctlp == NULL) { 769 ADBG_WARN(("ata_bus_ctl: failed to find ctl struct\n")); 770 return (DDI_FAILURE); 771 } 772 773 /* get (target,lun) of child device */ 774 775 targ = ddi_prop_get_int(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 776 "target", -1); 777 if (targ == -1) { 778 ADBG_WARN(("ata_bus_ctl: failed to get targ num\n")); 779 return (DDI_FAILURE); 780 } 781 782 lun = ddi_prop_get_int(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 783 "lun", 0); 784 785 if ((targ < 0) || (targ >= ATA_MAXTARG) || 786 (lun < 0) || (lun >= ATA_MAXLUN)) { 787 return (DDI_FAILURE); 788 } 789 790 ata_drvp = CTL2DRV(ata_ctlp, targ, lun); 791 792 if (ata_drvp == NULL) 793 return (DDI_FAILURE); /* no drive */ 794 795 /* get type of device */ 796 797 if (ATAPIDRV(ata_drvp)) 798 drive_type = ATA_DEV_ATAPI; 799 else 800 drive_type = ATA_DEV_DISK; 801 802 /* 803 * Check for special handling when child driver is 804 * cmdk (which morphs to the correct interface) 805 */ 806 if (strcmp(ddi_get_name(tdip), "cmdk") == 0) { 807 808 if ((target_type == ATA_DEV_DISK) && 809 (target_type != drive_type)) 810 return (DDI_FAILURE); 811 812 target_type = drive_type; 813 814 if (drive_type == ATA_DEV_ATAPI) { 815 class_prop = "scsi"; 816 } else { 817 disk_prop = "dadk"; 818 class_prop = "dada"; 819 820 if (ndi_prop_update_string(DDI_DEV_T_NONE, tdip, 821 "disk", disk_prop) != DDI_PROP_SUCCESS) { 822 ADBG_WARN(("ata_bus_ctl: failed to " 823 "create disk prop\n")); 824 return (DDI_FAILURE); 825 } 826 } 827 828 if (ndi_prop_update_string(DDI_DEV_T_NONE, tdip, 829 "class_prop", class_prop) != DDI_PROP_SUCCESS) { 830 ADBG_WARN(("ata_bus_ctl: failed to " 831 "create class prop\n")); 832 return (DDI_FAILURE); 833 } 834 } 835 836 /* Check that target class matches the device */ 837 838 if (target_type != drive_type) 839 return (DDI_FAILURE); 840 841 /* save pointer to drive struct for ata_disk_bus_ctl */ 842 ddi_set_driver_private(tdip, ata_drvp); 843 844 /* 845 * Determine whether to enable DMA support for this drive. This 846 * check is deferred to this point so that the various dma 847 * properties could reside on the devinfo node should finer 848 * grained dma control be required. 849 */ 850 ata_drvp->ad_pciide_dma = ata_init_drive_pcidma(ata_ctlp, 851 ata_drvp, tdip); 852 ata_show_transfer_mode(ata_ctlp, ata_drvp); 853 } 854 855 if (target_type == ATA_DEV_ATAPI) { 856 rc = scsa_bus_ops_p->bus_ctl(d, r, o, a, v); 857 } else { 858 rc = ata_disk_bus_ctl(d, r, o, a, v); 859 } 860 861 return (rc); 862 } 863 864 /* 865 * 866 * GHD ccc_hba_complete callback 867 * 868 */ 869 870 /* ARGSUSED */ 871 static void 872 ata_hba_complete( 873 void *hba_handle, 874 gcmd_t *gcmdp, 875 int do_callback) 876 { 877 ata_drv_t *ata_drvp; 878 ata_pkt_t *ata_pktp; 879 880 ADBG_TRACE(("ata_hba_complete entered\n")); 881 882 ata_drvp = GCMD2DRV(gcmdp); 883 ata_pktp = GCMD2APKT(gcmdp); 884 if (ata_pktp->ap_complete) 885 (*ata_pktp->ap_complete)(ata_drvp, ata_pktp, 886 do_callback); 887 } 888 889 /* GHD ccc_timeout_func callback */ 890 891 /* ARGSUSED */ 892 static int 893 ata_timeout_func( 894 void *hba_handle, 895 gcmd_t *gcmdp, 896 gtgt_t *gtgtp, 897 gact_t action, 898 int calltype) 899 { 900 ata_ctl_t *ata_ctlp; 901 ata_pkt_t *ata_pktp; 902 903 ADBG_TRACE(("ata_timeout_func entered\n")); 904 905 ata_ctlp = (ata_ctl_t *)hba_handle; 906 907 if (gcmdp != NULL) 908 ata_pktp = GCMD2APKT(gcmdp); 909 else 910 ata_pktp = NULL; 911 912 switch (action) { 913 case GACTION_EARLY_ABORT: 914 /* abort before request was started */ 915 if (ata_pktp != NULL) { 916 ata_pktp->ap_flags |= AP_ABORT; 917 } 918 ghd_complete(&ata_ctlp->ac_ccc, gcmdp); 919 return (TRUE); 920 921 case GACTION_EARLY_TIMEOUT: 922 /* timeout before request was started */ 923 if (ata_pktp != NULL) { 924 ata_pktp->ap_flags |= AP_TIMEOUT; 925 } 926 ghd_complete(&ata_ctlp->ac_ccc, gcmdp); 927 return (TRUE); 928 929 case GACTION_RESET_TARGET: 930 /* 931 * Reset a device is not supported. Resetting a specific 932 * device can't be done at all to an ATA device and if 933 * you send a RESET to an ATAPI device you have to 934 * reset the whole bus to make certain both devices 935 * on the bus stay in sync regarding which device is 936 * the currently selected one. 937 */ 938 return (FALSE); 939 940 case GACTION_RESET_BUS: 941 /* 942 * Issue bus reset and reinitialize both drives. 943 * But only if this is a timed-out request. Target 944 * driver reset requests are ignored because ATA 945 * and ATAPI devices shouldn't be gratuitously reset. 946 */ 947 if (gcmdp == NULL) 948 break; 949 return (ata_reset_bus(ata_ctlp)); 950 default: 951 break; 952 } 953 return (FALSE); 954 } 955 956 /* 957 * 958 * Initialize controller's soft-state structure 959 * 960 */ 961 962 static ata_ctl_t * 963 ata_init_controller( 964 dev_info_t *dip) 965 { 966 ata_ctl_t *ata_ctlp; 967 int instance; 968 caddr_t ioaddr1; 969 caddr_t ioaddr2; 970 971 ADBG_TRACE(("ata_init_controller entered\n")); 972 973 instance = ddi_get_instance(dip); 974 975 /* allocate controller structure */ 976 if (ddi_soft_state_zalloc(ata_state, instance) != DDI_SUCCESS) { 977 ADBG_WARN(("ata_init_controller: soft_state_zalloc failed\n")); 978 return (NULL); 979 } 980 981 ata_ctlp = ddi_get_soft_state(ata_state, instance); 982 983 if (ata_ctlp == NULL) { 984 ADBG_WARN(("ata_init_controller: failed to find " 985 "controller struct\n")); 986 return (NULL); 987 } 988 989 /* 990 * initialize per-controller data 991 */ 992 ata_ctlp->ac_dip = dip; 993 ata_ctlp->ac_arq_pktp = kmem_zalloc(sizeof (ata_pkt_t), KM_SLEEP); 994 995 /* 996 * map the device registers 997 */ 998 if (!ata_setup_ioaddr(dip, &ata_ctlp->ac_iohandle1, &ioaddr1, 999 &ata_ctlp->ac_iohandle2, &ioaddr2, 1000 &ata_ctlp->ac_bmhandle, &ata_ctlp->ac_bmaddr)) { 1001 (void) ata_detach(dip, DDI_DETACH); 1002 return (NULL); 1003 } 1004 1005 ADBG_INIT(("ata_init_controller: ioaddr1 = 0x%p, ioaddr2 = 0x%p\n", 1006 ioaddr1, ioaddr2)); 1007 1008 /* 1009 * Do ARQ setup 1010 */ 1011 atapi_init_arq(ata_ctlp); 1012 1013 /* 1014 * Do PCI-IDE setup 1015 */ 1016 ata_init_pciide(dip, ata_ctlp); 1017 1018 /* 1019 * port addresses associated with ioaddr1 1020 */ 1021 ata_ctlp->ac_ioaddr1 = ioaddr1; 1022 ata_ctlp->ac_data = (ushort_t *)ioaddr1 + AT_DATA; 1023 ata_ctlp->ac_error = (uchar_t *)ioaddr1 + AT_ERROR; 1024 ata_ctlp->ac_feature = (uchar_t *)ioaddr1 + AT_FEATURE; 1025 ata_ctlp->ac_count = (uchar_t *)ioaddr1 + AT_COUNT; 1026 ata_ctlp->ac_sect = (uchar_t *)ioaddr1 + AT_SECT; 1027 ata_ctlp->ac_lcyl = (uchar_t *)ioaddr1 + AT_LCYL; 1028 ata_ctlp->ac_hcyl = (uchar_t *)ioaddr1 + AT_HCYL; 1029 ata_ctlp->ac_drvhd = (uchar_t *)ioaddr1 + AT_DRVHD; 1030 ata_ctlp->ac_status = (uchar_t *)ioaddr1 + AT_STATUS; 1031 ata_ctlp->ac_cmd = (uchar_t *)ioaddr1 + AT_CMD; 1032 1033 /* 1034 * port addresses associated with ioaddr2 1035 */ 1036 ata_ctlp->ac_ioaddr2 = ioaddr2; 1037 ata_ctlp->ac_altstatus = (uchar_t *)ioaddr2 + AT_ALTSTATUS; 1038 ata_ctlp->ac_devctl = (uchar_t *)ioaddr2 + AT_DEVCTL; 1039 1040 /* 1041 * If AC_BSY_WAIT needs to be set for laptops that do 1042 * suspend/resume but do not correctly wait for the busy bit to 1043 * drop after a resume. 1044 */ 1045 ata_ctlp->ac_timing_flags = ddi_prop_get_int(DDI_DEV_T_ANY, 1046 dip, DDI_PROP_DONTPASS, "timing_flags", 0); 1047 /* 1048 * get max transfer size, default to 256 sectors 1049 */ 1050 ata_ctlp->ac_max_transfer = ddi_prop_get_int(DDI_DEV_T_ANY, 1051 dip, DDI_PROP_DONTPASS, "max_transfer", 0x100); 1052 if (ata_ctlp->ac_max_transfer < 1) 1053 ata_ctlp->ac_max_transfer = 1; 1054 if (ata_ctlp->ac_max_transfer > 0x100) 1055 ata_ctlp->ac_max_transfer = 0x100; 1056 1057 /* 1058 * Get the standby timer value 1059 */ 1060 ata_ctlp->ac_standby_time = ddi_prop_get_int(DDI_DEV_T_ANY, 1061 dip, DDI_PROP_DONTPASS, "standby", -1); 1062 1063 /* 1064 * If this is a /pci/pci-ide instance check to see if 1065 * it's supposed to be attached as an /isa/ata 1066 */ 1067 if (ata_ctlp->ac_pciide) { 1068 static char prop_buf[] = "SUNW-ata-ffff-isa"; 1069 int addr1 = (intptr_t)ioaddr1; 1070 1071 1072 if (addr1 < 0 || addr1 > 0xffff) { 1073 (void) ata_detach(dip, DDI_DETACH); 1074 return (NULL); 1075 } 1076 (void) sprintf(prop_buf, "SUNW-ata-%04x-isa", 1077 addr1); 1078 if (ddi_prop_exists(DDI_DEV_T_ANY, ddi_root_node(), 1079 DDI_PROP_DONTPASS, prop_buf)) { 1080 (void) ata_detach(dip, DDI_DETACH); 1081 return (NULL); 1082 } 1083 } 1084 1085 /* Init controller specific stuff */ 1086 (void) ata_spec_init_controller(dip); 1087 1088 /* 1089 * initialize GHD 1090 */ 1091 1092 GHD_WAITQ_INIT(&ata_ctlp->ac_ccc.ccc_waitq, NULL, 1); 1093 1094 if (!ghd_register("ata", &ata_ctlp->ac_ccc, dip, 0, ata_ctlp, 1095 atapi_ccballoc, atapi_ccbfree, 1096 ata_pciide_dma_sg_func, ata_hba_start, 1097 ata_hba_complete, ata_intr, 1098 ata_get_status, ata_process_intr, ata_timeout_func, 1099 &ata_timer_conf, NULL)) { 1100 (void) ata_detach(dip, DDI_DETACH); 1101 return (NULL); 1102 } 1103 1104 ata_ctlp->ac_flags |= AC_GHD_INIT; 1105 return (ata_ctlp); 1106 } 1107 1108 /* destroy a controller */ 1109 1110 static void 1111 ata_destroy_controller( 1112 dev_info_t *dip) 1113 { 1114 ata_ctl_t *ata_ctlp; 1115 int instance; 1116 1117 ADBG_TRACE(("ata_destroy_controller entered\n")); 1118 1119 instance = ddi_get_instance(dip); 1120 ata_ctlp = ddi_get_soft_state(ata_state, instance); 1121 1122 if (ata_ctlp == NULL) 1123 return; 1124 1125 /* destroy ghd */ 1126 if (ata_ctlp->ac_flags & AC_GHD_INIT) 1127 ghd_unregister(&ata_ctlp->ac_ccc); 1128 1129 /* free the pciide buffer (if any) */ 1130 ata_pciide_free(ata_ctlp); 1131 1132 /* destroy controller struct */ 1133 kmem_free(ata_ctlp->ac_arq_pktp, sizeof (ata_pkt_t)); 1134 ddi_soft_state_free(ata_state, instance); 1135 1136 } 1137 1138 1139 /* 1140 * 1141 * initialize a drive 1142 * 1143 */ 1144 1145 static ata_drv_t * 1146 ata_init_drive( 1147 ata_ctl_t *ata_ctlp, 1148 uchar_t targ, 1149 uchar_t lun) 1150 { 1151 static char nec_260[] = "NEC CD-ROM DRIVE"; 1152 ata_drv_t *ata_drvp; 1153 struct ata_id *aidp; 1154 char buf[80]; 1155 int drive_type; 1156 int i; 1157 int valid_version = 0; 1158 1159 ADBG_TRACE(("ata_init_drive entered, targ = %d, lun = %d\n", 1160 targ, lun)); 1161 1162 /* check if device already exists */ 1163 1164 ata_drvp = CTL2DRV(ata_ctlp, targ, lun); 1165 1166 if (ata_drvp != NULL) 1167 return (ata_drvp); 1168 1169 /* allocate new device structure */ 1170 1171 ata_drvp = kmem_zalloc(sizeof (ata_drv_t), KM_SLEEP); 1172 aidp = &ata_drvp->ad_id; 1173 1174 /* 1175 * set up drive struct 1176 */ 1177 ata_drvp->ad_ctlp = ata_ctlp; 1178 ata_drvp->ad_targ = targ; 1179 ata_drvp->ad_drive_bits = 1180 (ata_drvp->ad_targ == 0 ? ATDH_DRIVE0 : ATDH_DRIVE1); 1181 /* 1182 * Add the LUN for SFF-8070i support 1183 */ 1184 ata_drvp->ad_lun = lun; 1185 ata_drvp->ad_drive_bits |= ata_drvp->ad_lun; 1186 1187 /* 1188 * get drive type, side effect is to collect 1189 * IDENTIFY DRIVE data 1190 */ 1191 1192 drive_type = ata_drive_type(ata_drvp->ad_drive_bits, 1193 ata_ctlp->ac_iohandle1, 1194 ata_ctlp->ac_ioaddr1, 1195 ata_ctlp->ac_iohandle2, 1196 ata_ctlp->ac_ioaddr2, 1197 aidp); 1198 1199 switch (drive_type) { 1200 case ATA_DEV_NONE: 1201 /* no drive found */ 1202 goto errout; 1203 case ATA_DEV_ATAPI: 1204 ata_drvp->ad_flags |= AD_ATAPI; 1205 break; 1206 case ATA_DEV_DISK: 1207 ata_drvp->ad_flags |= AD_DISK; 1208 break; 1209 } 1210 1211 /* 1212 * swap bytes of all text fields 1213 */ 1214 if (!ata_strncmp(nec_260, aidp->ai_model, sizeof (aidp->ai_model))) { 1215 swab(aidp->ai_drvser, aidp->ai_drvser, 1216 sizeof (aidp->ai_drvser)); 1217 swab(aidp->ai_fw, aidp->ai_fw, 1218 sizeof (aidp->ai_fw)); 1219 swab(aidp->ai_model, aidp->ai_model, 1220 sizeof (aidp->ai_model)); 1221 } 1222 1223 /* 1224 * Check if this drive has the Single Sector bug 1225 */ 1226 1227 if (ata_check_drive_blacklist(&ata_drvp->ad_id, ATA_BL_1SECTOR)) 1228 ata_drvp->ad_flags |= AD_1SECTOR; 1229 else 1230 ata_drvp->ad_flags &= ~AD_1SECTOR; 1231 1232 /* Check if this drive has the "revert to defaults" bug */ 1233 if (!ata_check_revert_to_defaults(ata_drvp)) 1234 ata_drvp->ad_flags |= AD_NORVRT; 1235 1236 /* Dump the drive info */ 1237 (void) strncpy(buf, aidp->ai_model, sizeof (aidp->ai_model)); 1238 buf[sizeof (aidp->ai_model)-1] = '\0'; 1239 for (i = sizeof (aidp->ai_model) - 2; buf[i] == ' '; i--) 1240 buf[i] = '\0'; 1241 1242 ATAPRT(("?\t%s device at targ %d, lun %d lastlun 0x%x\n", 1243 (ATAPIDRV(ata_drvp) ? "ATAPI":"IDE"), 1244 ata_drvp->ad_targ, ata_drvp->ad_lun, aidp->ai_lastlun)); 1245 1246 ATAPRT(("?\tmodel %s\n", buf)); 1247 1248 if (aidp->ai_majorversion != 0 && aidp->ai_majorversion != 0xffff) { 1249 for (i = 14; i >= 2; i--) { 1250 if (aidp->ai_majorversion & (1 << i)) { 1251 valid_version = i; 1252 break; 1253 } 1254 } 1255 ATAPRT(( 1256 "?\tATA/ATAPI-%d supported, majver 0x%x minver 0x%x\n", 1257 valid_version, 1258 aidp->ai_majorversion, 1259 aidp->ai_minorversion)); 1260 } 1261 1262 if (ata_capability_data) { 1263 1264 ATAPRT(("?\t\tstat %x, err %x\n", 1265 ddi_get8(ata_ctlp->ac_iohandle2, 1266 ata_ctlp->ac_altstatus), 1267 ddi_get8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_error))); 1268 1269 ATAPRT(("?\t\tcfg 0x%x, cap 0x%x\n", 1270 aidp->ai_config, 1271 aidp->ai_cap)); 1272 1273 /* 1274 * Be aware that ATA-6 and later drives may not provide valid 1275 * geometry information and other obsoleted info. 1276 * Select what is printed based on supported ATA model (skip 1277 * anything below ATA/ATAPI-3) 1278 */ 1279 1280 if (valid_version == 0 || aidp->ai_majorversion < 1281 ATAC_MAJVER_6) { 1282 /* 1283 * Supported version less then ATA-6 1284 */ 1285 ATAPRT(("?\t\tcyl %d, hd %d, sec/trk %d\n", 1286 aidp->ai_fixcyls, 1287 aidp->ai_heads, 1288 aidp->ai_sectors)); 1289 } 1290 ATAPRT(("?\t\tmult1 0x%x, mult2 0x%x\n", 1291 aidp->ai_mult1, 1292 aidp->ai_mult2)); 1293 if (valid_version && aidp->ai_majorversion < ATAC_MAJVER_4) { 1294 ATAPRT(( 1295 "?\t\tpiomode 0x%x, dmamode 0x%x, advpiomode 0x%x\n", 1296 aidp->ai_piomode, 1297 aidp->ai_dmamode, 1298 aidp->ai_advpiomode)); 1299 } else { 1300 ATAPRT(("?\t\tadvpiomode 0x%x\n", 1301 aidp->ai_advpiomode)); 1302 } 1303 ATAPRT(("?\t\tminpio %d, minpioflow %d\n", 1304 aidp->ai_minpio, 1305 aidp->ai_minpioflow)); 1306 if (valid_version && aidp->ai_majorversion >= ATAC_MAJVER_4 && 1307 (aidp->ai_validinfo & ATAC_VALIDINFO_83)) { 1308 ATAPRT(("?\t\tdwdma 0x%x, ultradma 0x%x\n", 1309 aidp->ai_dworddma, 1310 aidp->ai_ultradma)); 1311 } else { 1312 ATAPRT(("?\t\tdwdma 0x%x\n", 1313 aidp->ai_dworddma)); 1314 } 1315 } 1316 1317 if (ATAPIDRV(ata_drvp)) { 1318 if (!atapi_init_drive(ata_drvp)) 1319 goto errout; 1320 } else { 1321 if (!ata_disk_init_drive(ata_drvp)) 1322 goto errout; 1323 } 1324 1325 /* 1326 * store pointer in controller struct 1327 */ 1328 CTL2DRV(ata_ctlp, targ, lun) = ata_drvp; 1329 1330 /* 1331 * lock the drive's current settings in case I have to 1332 * reset the drive due to some sort of error 1333 */ 1334 (void) ata_set_feature(ata_ctlp, ata_drvp, 0x66, 0); 1335 1336 return (ata_drvp); 1337 1338 errout: 1339 ata_uninit_drive(ata_drvp); 1340 return (NULL); 1341 } 1342 1343 /* destroy a drive */ 1344 1345 static void 1346 ata_uninit_drive( 1347 ata_drv_t *ata_drvp) 1348 { 1349 #if 0 1350 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp; 1351 #endif 1352 1353 ADBG_TRACE(("ata_uninit_drive entered\n")); 1354 1355 #if 0 1356 /* 1357 * DON'T DO THIS. disabling interrupts floats the IRQ line 1358 * which generates spurious interrupts 1359 */ 1360 1361 /* 1362 * Select the correct drive 1363 */ 1364 ddi_put8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_drvhd, 1365 ata_drvp->ad_drive_bits); 1366 ata_nsecwait(400); 1367 1368 /* 1369 * Disable interrupts from the drive 1370 */ 1371 ddi_put8(ata_ctlp->ac_iohandle2, ata_ctlp->ac_devctl, 1372 (ATDC_D3 | ATDC_NIEN)); 1373 #endif 1374 1375 /* interface specific clean-ups */ 1376 1377 if (ata_drvp->ad_flags & AD_ATAPI) 1378 atapi_uninit_drive(ata_drvp); 1379 else if (ata_drvp->ad_flags & AD_DISK) 1380 ata_disk_uninit_drive(ata_drvp); 1381 1382 /* free drive struct */ 1383 1384 kmem_free(ata_drvp, sizeof (ata_drv_t)); 1385 } 1386 1387 1388 /* 1389 * ata_drive_type() 1390 * 1391 * The timeout values and exact sequence of checking is critical 1392 * especially for atapi device detection, and should not be changed lightly. 1393 * 1394 */ 1395 static int 1396 ata_drive_type( 1397 uchar_t drvhd, 1398 ddi_acc_handle_t io_hdl1, 1399 caddr_t ioaddr1, 1400 ddi_acc_handle_t io_hdl2, 1401 caddr_t ioaddr2, 1402 struct ata_id *ata_id_bufp) 1403 { 1404 uchar_t status; 1405 1406 ADBG_TRACE(("ata_drive_type entered\n")); 1407 1408 /* 1409 * select the appropriate drive and LUN 1410 */ 1411 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_DRVHD, drvhd); 1412 ata_nsecwait(400); 1413 1414 /* 1415 * make certain the drive is selected, and wait for not busy 1416 */ 1417 (void) ata_wait3(io_hdl2, ioaddr2, 0, ATS_BSY, 0x7f, 0, 0x7f, 0, 1418 5 * 1000000); 1419 1420 status = ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS); 1421 1422 /* 1423 * 0x0, 0x7f, or 0xff can happen when no drive is present 1424 */ 1425 if ((status & ATS_BSY) || (status == 0x0) || (status == 0x7f) || 1426 (status == 0xff) || (status & ATS_DF)) { 1427 ADBG_TRACE(("ata_drive_type 0x%p 0x%x\n", ioaddr1, status)); 1428 return (ATA_DEV_NONE); 1429 } 1430 1431 if (ata_disk_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) 1432 return (ATA_DEV_DISK); 1433 1434 /* 1435 * No disk, check for atapi unit. 1436 */ 1437 if (!atapi_signature(io_hdl1, ioaddr1)) { 1438 #ifndef ATA_DISABLE_ATAPI_1_7 1439 /* 1440 * Check for old (but prevalent) atapi 1.7B 1441 * spec device, the only known example is the 1442 * NEC CDR-260 (not 260R which is (mostly) ATAPI 1.2 1443 * compliant). This device has no signature 1444 * and requires conversion from hex to BCD 1445 * for some scsi audio commands. 1446 */ 1447 if (atapi_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) { 1448 return (ATA_DEV_ATAPI); 1449 } 1450 #endif 1451 return (ATA_DEV_NONE); 1452 } 1453 1454 if (atapi_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) { 1455 return (ATA_DEV_ATAPI); 1456 } 1457 1458 return (ATA_DEV_NONE); 1459 1460 } 1461 1462 /* 1463 * nsec-granularity time delay function 1464 */ 1465 void 1466 ata_nsecwait(clock_t count) 1467 { 1468 extern int tsc_gethrtime_initted; 1469 1470 if (tsc_gethrtime_initted) { 1471 hrtime_t end = gethrtime() + count; 1472 1473 while (gethrtime() < end) { 1474 SMT_PAUSE(); 1475 } 1476 } else { 1477 drv_usecwait(1 + (count / 1000)); 1478 } 1479 } 1480 1481 1482 /* 1483 * Wait for a register of a controller to achieve a specific state. 1484 * To return normally, all the bits in the first sub-mask must be ON, 1485 * all the bits in the second sub-mask must be OFF. 1486 * If timeout_usec microseconds pass without the controller achieving 1487 * the desired bit configuration, we return TRUE, else FALSE. 1488 */ 1489 1490 int ata_usec_delay = 10; 1491 1492 int 1493 ata_wait( 1494 ddi_acc_handle_t io_hdl, 1495 caddr_t ioaddr, 1496 uchar_t onbits, 1497 uchar_t offbits, 1498 uint_t timeout_usec) 1499 { 1500 ushort_t val; 1501 hrtime_t deadline = gethrtime() + 1502 (hrtime_t)timeout_usec * (NANOSEC / MICROSEC); 1503 1504 1505 do { 1506 val = ddi_get8(io_hdl, (uchar_t *)ioaddr + AT_ALTSTATUS); 1507 if ((val & onbits) == onbits && (val & offbits) == 0) 1508 return (TRUE); 1509 drv_usecwait(ata_usec_delay); 1510 } while (gethrtime() < deadline); 1511 1512 return (FALSE); 1513 } 1514 1515 1516 /* 1517 * 1518 * This is a slightly more complicated version that checks 1519 * for error conditions and bails-out rather than looping 1520 * until the timeout expires 1521 */ 1522 int 1523 ata_wait3( 1524 ddi_acc_handle_t io_hdl, 1525 caddr_t ioaddr, 1526 uchar_t onbits1, 1527 uchar_t offbits1, 1528 uchar_t failure_onbits2, 1529 uchar_t failure_offbits2, 1530 uchar_t failure_onbits3, 1531 uchar_t failure_offbits3, 1532 uint_t timeout_usec) 1533 { 1534 ushort_t val; 1535 hrtime_t deadline = gethrtime() + 1536 (hrtime_t)timeout_usec * (NANOSEC / MICROSEC); 1537 1538 do { 1539 val = ddi_get8(io_hdl, (uchar_t *)ioaddr + AT_ALTSTATUS); 1540 1541 /* 1542 * check for expected condition 1543 */ 1544 if ((val & onbits1) == onbits1 && (val & offbits1) == 0) 1545 return (TRUE); 1546 1547 /* 1548 * check for error conditions 1549 */ 1550 if ((val & failure_onbits2) == failure_onbits2 && 1551 (val & failure_offbits2) == 0) { 1552 return (FALSE); 1553 } 1554 1555 if ((val & failure_onbits3) == failure_onbits3 && 1556 (val & failure_offbits3) == 0) { 1557 return (FALSE); 1558 } 1559 1560 drv_usecwait(ata_usec_delay); 1561 } while (gethrtime() < deadline); 1562 1563 return (FALSE); 1564 } 1565 1566 1567 /* 1568 * 1569 * low level routine for ata_disk_id() and atapi_id() 1570 * 1571 */ 1572 1573 int 1574 ata_id_common( 1575 uchar_t id_cmd, 1576 int expect_drdy, 1577 ddi_acc_handle_t io_hdl1, 1578 caddr_t ioaddr1, 1579 ddi_acc_handle_t io_hdl2, 1580 caddr_t ioaddr2, 1581 struct ata_id *aidp) 1582 { 1583 uchar_t status; 1584 1585 ADBG_TRACE(("ata_id_common entered\n")); 1586 1587 bzero(aidp, sizeof (struct ata_id)); 1588 1589 /* 1590 * clear the features register 1591 */ 1592 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_FEATURE, 0); 1593 1594 /* 1595 * Disable interrupts from the device. ata_id_common() is 1596 * called at device probe time before the interrupt handled is 1597 * registered. When the ata hardware is sharing its 1598 * interrupt with another device, the shared interrupt might 1599 * have already been unmasked in the interrupt controller and 1600 * triggering ata device interrupts will result in an 1601 * interrupt storm and a hung system. 1602 */ 1603 ddi_put8(io_hdl2, (uchar_t *)ioaddr2 + AT_DEVCTL, ATDC_D3 | ATDC_NIEN); 1604 1605 /* 1606 * issue IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command 1607 */ 1608 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_CMD, id_cmd); 1609 1610 /* wait for the busy bit to settle */ 1611 ata_nsecwait(400); 1612 1613 /* 1614 * According to the ATA specification, some drives may have 1615 * to read the media to complete this command. We need to 1616 * make sure we give them enough time to respond. 1617 */ 1618 1619 (void) ata_wait3(io_hdl2, ioaddr2, 0, ATS_BSY, 1620 ATS_ERR, ATS_BSY, 0x7f, 0, 5 * 1000000); 1621 1622 /* 1623 * read the status byte and clear the pending interrupt 1624 */ 1625 status = ddi_get8(io_hdl2, (uchar_t *)ioaddr1 + AT_STATUS); 1626 1627 /* 1628 * 0x0, 0x7f, or 0xff can happen when no drive is present 1629 */ 1630 if ((status == 0x0) || (status == 0x7f) || (status == 0xff) || 1631 (status & ATS_DF)) { 1632 /* invalid status, can't be an ATA or ATAPI device */ 1633 return (FALSE); 1634 } 1635 1636 if (status & ATS_BSY) { 1637 ADBG_ERROR(("ata_id_common: BUSY status 0x%x error 0x%x\n", 1638 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 +AT_ALTSTATUS), 1639 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1640 return (FALSE); 1641 } 1642 1643 if (!(status & ATS_DRQ)) { 1644 if (status & (ATS_ERR | ATS_DF)) { 1645 return (FALSE); 1646 } 1647 /* 1648 * Give the drive another second to assert DRQ. Some older 1649 * drives de-assert BSY before asserting DRQ. 1650 */ 1651 if (!ata_wait(io_hdl2, ioaddr2, ATS_DRQ, ATS_BSY, 1000000)) { 1652 ADBG_WARN(("ata_id_common: !DRQ status 0x%x error 0x%x\n", 1653 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 +AT_ALTSTATUS), 1654 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1655 return (FALSE); 1656 } 1657 } 1658 1659 /* 1660 * transfer the data 1661 */ 1662 ddi_rep_get16(io_hdl1, (ushort_t *)aidp, (ushort_t *)ioaddr1 + AT_DATA, 1663 NBPSCTR >> 1, DDI_DEV_NO_AUTOINCR); 1664 1665 /* wait for the busy bit to settle */ 1666 ata_nsecwait(400); 1667 1668 1669 /* 1670 * Wait for the drive to recognize I've read all the data. 1671 * Some drives have been observed to take as much as 3msec to 1672 * deassert DRQ after reading the data; allow 10 msec just in case. 1673 * 1674 * Note: some non-compliant ATAPI drives (e.g., NEC Multispin 6V, 1675 * CDR-1350A) don't assert DRDY. If we've made it this far we can 1676 * safely ignore the DRDY bit since the ATAPI Packet command 1677 * actually doesn't require it to ever be asserted. 1678 * 1679 */ 1680 if (!ata_wait(io_hdl2, ioaddr2, (uchar_t)(expect_drdy ? ATS_DRDY : 0), 1681 (ATS_BSY | ATS_DRQ), 1000000)) { 1682 ADBG_WARN(("ata_id_common: bad status 0x%x error 0x%x\n", 1683 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS), 1684 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1685 return (FALSE); 1686 } 1687 1688 /* 1689 * Check to see if the command aborted. This happens if 1690 * an IDENTIFY DEVICE command is issued to an ATAPI PACKET device, 1691 * or if an IDENTIFY PACKET DEVICE command is issued to an ATA 1692 * (non-PACKET) device. 1693 */ 1694 if (status & (ATS_DF | ATS_ERR)) { 1695 ADBG_WARN(("ata_id_common: status 0x%x error 0x%x \n", 1696 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS), 1697 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1698 return (FALSE); 1699 } 1700 return (TRUE); 1701 } 1702 1703 1704 /* 1705 * Low level routine to issue a non-data command and busy wait for 1706 * the completion status. 1707 */ 1708 1709 int 1710 ata_command( 1711 ata_ctl_t *ata_ctlp, 1712 ata_drv_t *ata_drvp, 1713 int expect_drdy, 1714 int silent, 1715 uint_t busy_wait, 1716 uchar_t cmd, 1717 uchar_t feature, 1718 uchar_t count, 1719 uchar_t sector, 1720 uchar_t head, 1721 uchar_t cyl_low, 1722 uchar_t cyl_hi) 1723 { 1724 ddi_acc_handle_t io_hdl1 = ata_ctlp->ac_iohandle1; 1725 ddi_acc_handle_t io_hdl2 = ata_ctlp->ac_iohandle2; 1726 uchar_t status; 1727 1728 /* select the drive */ 1729 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, ata_drvp->ad_drive_bits); 1730 ata_nsecwait(400); 1731 1732 /* make certain the drive selected */ 1733 if (!ata_wait(io_hdl2, ata_ctlp->ac_ioaddr2, 1734 (uchar_t)(expect_drdy ? ATS_DRDY : 0), 1735 ATS_BSY, busy_wait)) { 1736 ADBG_ERROR(("ata_command: select failed " 1737 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x " 1738 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n", 1739 expect_drdy, cmd, feature, count, 1740 sector, head, cyl_low, cyl_hi)); 1741 return (FALSE); 1742 } 1743 1744 /* 1745 * set all the regs 1746 */ 1747 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, (head | ata_drvp->ad_drive_bits)); 1748 ddi_put8(io_hdl1, ata_ctlp->ac_sect, sector); 1749 ddi_put8(io_hdl1, ata_ctlp->ac_count, count); 1750 ddi_put8(io_hdl1, ata_ctlp->ac_lcyl, cyl_low); 1751 ddi_put8(io_hdl1, ata_ctlp->ac_hcyl, cyl_hi); 1752 ddi_put8(io_hdl1, ata_ctlp->ac_feature, feature); 1753 1754 /* send the command */ 1755 ddi_put8(io_hdl1, ata_ctlp->ac_cmd, cmd); 1756 1757 /* wait for the busy bit to settle */ 1758 ata_nsecwait(400); 1759 1760 /* wait for not busy */ 1761 if (!ata_wait(io_hdl2, ata_ctlp->ac_ioaddr2, 0, ATS_BSY, busy_wait)) { 1762 ADBG_ERROR(("ata_command: BSY too long!" 1763 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x " 1764 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n", 1765 expect_drdy, cmd, feature, count, 1766 sector, head, cyl_low, cyl_hi)); 1767 return (FALSE); 1768 } 1769 1770 /* 1771 * wait for DRDY before continuing 1772 */ 1773 (void) ata_wait3(io_hdl2, ata_ctlp->ac_ioaddr2, 1774 ATS_DRDY, ATS_BSY, /* okay */ 1775 ATS_ERR, ATS_BSY, /* cmd failed */ 1776 ATS_DF, ATS_BSY, /* drive failed */ 1777 busy_wait); 1778 1779 /* read status to clear IRQ, and check for error */ 1780 status = ddi_get8(io_hdl1, ata_ctlp->ac_status); 1781 1782 if ((status & (ATS_BSY | ATS_DF | ATS_ERR)) == 0) 1783 return (TRUE); 1784 1785 if (!silent) { 1786 ADBG_ERROR(("ata_command status 0x%x error 0x%x " 1787 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x " 1788 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n", 1789 ddi_get8(io_hdl1, ata_ctlp->ac_status), 1790 ddi_get8(io_hdl1, ata_ctlp->ac_error), 1791 expect_drdy, cmd, feature, count, 1792 sector, head, cyl_low, cyl_hi)); 1793 } 1794 return (FALSE); 1795 } 1796 1797 1798 1799 /* 1800 * 1801 * Issue a SET FEATURES command 1802 * 1803 */ 1804 1805 int 1806 ata_set_feature( 1807 ata_ctl_t *ata_ctlp, 1808 ata_drv_t *ata_drvp, 1809 uchar_t feature, 1810 uchar_t value) 1811 { 1812 int rc; 1813 1814 rc = ata_command(ata_ctlp, ata_drvp, TRUE, TRUE, ata_set_feature_wait, 1815 ATC_SET_FEAT, feature, value, 0, 0, 0, 0); 1816 /* feature, count, sector, head, cyl_low, cyl_hi */ 1817 1818 if (rc) { 1819 return (TRUE); 1820 } 1821 1822 ADBG_ERROR(("?ata_set_feature: (0x%x,0x%x) failed\n", feature, value)); 1823 return (FALSE); 1824 } 1825 1826 1827 1828 /* 1829 * 1830 * Issue a FLUSH CACHE command 1831 * 1832 */ 1833 1834 static int 1835 ata_flush_cache( 1836 ata_ctl_t *ata_ctlp, 1837 ata_drv_t *ata_drvp) 1838 { 1839 /* this command is optional so fail silently */ 1840 return (ata_command(ata_ctlp, ata_drvp, TRUE, TRUE, 1841 ata_flush_cache_wait, 1842 ATC_FLUSH_CACHE, 0, 0, 0, 0, 0, 0)); 1843 } 1844 1845 /* 1846 * ata_setup_ioaddr() 1847 * 1848 * Map the device registers and return the handles. 1849 * 1850 * If this is a ISA-ATA controller then only two handles are 1851 * initialized and returned. 1852 * 1853 * If this is a PCI-IDE controller than a third handle (for the 1854 * PCI-IDE Bus Mastering registers) is initialized and returned. 1855 * 1856 */ 1857 1858 static int 1859 ata_setup_ioaddr( 1860 dev_info_t *dip, 1861 ddi_acc_handle_t *handle1p, 1862 caddr_t *addr1p, 1863 ddi_acc_handle_t *handle2p, 1864 caddr_t *addr2p, 1865 ddi_acc_handle_t *bm_hdlp, 1866 caddr_t *bm_addrp) 1867 { 1868 ddi_device_acc_attr_t dev_attr; 1869 char *bufp; 1870 int rnumber; 1871 int rc; 1872 off_t regsize; 1873 1874 /* 1875 * Make certain the controller is enabled and its regs are map-able 1876 * 1877 */ 1878 rc = ddi_dev_regsize(dip, 0, ®size); 1879 if (rc != DDI_SUCCESS || regsize <= AT_CMD) { 1880 ADBG_INIT(("ata_setup_ioaddr(1): rc %d regsize %lld\n", 1881 rc, (long long)regsize)); 1882 return (FALSE); 1883 } 1884 1885 rc = ddi_dev_regsize(dip, 1, ®size); 1886 if (rc != DDI_SUCCESS || regsize <= AT_ALTSTATUS) { 1887 ADBG_INIT(("ata_setup_ioaddr(2): rc %d regsize %lld\n", 1888 rc, (long long)regsize)); 1889 return (FALSE); 1890 } 1891 1892 /* 1893 * setup the device attribute structure for little-endian, 1894 * strict ordering access. 1895 */ 1896 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 1897 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 1898 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1899 1900 *handle1p = NULL; 1901 *handle2p = NULL; 1902 *bm_hdlp = NULL; 1903 1904 /* 1905 * Determine whether this is a ISA, PNP-ISA, or PCI-IDE device 1906 */ 1907 if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "pnp-csn")) { 1908 /* it's PNP-ISA, skip over the extra reg tuple */ 1909 rnumber = 1; 1910 goto not_pciide; 1911 } 1912 1913 /* else, it's ISA or PCI-IDE, check further */ 1914 rnumber = 0; 1915 1916 rc = ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_get_parent(dip), 1917 DDI_PROP_DONTPASS, "device_type", &bufp); 1918 if (rc != DDI_PROP_SUCCESS) { 1919 ADBG_ERROR(("ata_setup_ioaddr !device_type\n")); 1920 goto not_pciide; 1921 } 1922 1923 if (strcmp(bufp, "pci-ide") != 0) { 1924 /* 1925 * If it's not a PCI-IDE, there are only two reg tuples 1926 * and the first one contains the I/O base (170 or 1f0) 1927 * rather than the controller instance number. 1928 */ 1929 ADBG_TRACE(("ata_setup_ioaddr !pci-ide\n")); 1930 ddi_prop_free(bufp); 1931 goto not_pciide; 1932 } 1933 ddi_prop_free(bufp); 1934 1935 1936 /* 1937 * Map the correct half of the PCI-IDE Bus Master registers. 1938 * There's a single BAR that maps these registers for both 1939 * controller's in a dual-controller chip and it's upto my 1940 * parent nexus, pciide, to adjust which (based on my instance 1941 * number) half this call maps. 1942 */ 1943 rc = ddi_dev_regsize(dip, 2, ®size); 1944 if (rc != DDI_SUCCESS || regsize < 8) { 1945 ADBG_INIT(("ata_setup_ioaddr(3): rc %d regsize %lld\n", 1946 rc, (long long)regsize)); 1947 goto not_pciide; 1948 } 1949 1950 rc = ddi_regs_map_setup(dip, 2, bm_addrp, 0, 0, &dev_attr, bm_hdlp); 1951 1952 if (rc != DDI_SUCCESS) { 1953 /* map failed, try to use in non-pci-ide mode */ 1954 ADBG_WARN(("ata_setup_ioaddr bus master map failed, rc=0x%x\n", 1955 rc)); 1956 *bm_hdlp = NULL; 1957 } 1958 1959 not_pciide: 1960 /* 1961 * map the lower command block registers 1962 */ 1963 1964 rc = ddi_regs_map_setup(dip, rnumber, addr1p, 0, 0, &dev_attr, 1965 handle1p); 1966 1967 if (rc != DDI_SUCCESS) { 1968 cmn_err(CE_WARN, "ata: reg tuple 0 map failed, rc=0x%x\n", rc); 1969 goto out1; 1970 } 1971 1972 /* 1973 * If the controller is being used in compatibility mode 1974 * via /devices/isa/ata@1,{1f0,1f0}/..., the reg property 1975 * will specify zeros for the I/O ports for the PCI 1976 * instance. 1977 */ 1978 if (*addr1p == 0) { 1979 ADBG_TRACE(("ata_setup_ioaddr ioaddr1 0\n")); 1980 goto out2; 1981 } 1982 1983 /* 1984 * map the upper control block registers 1985 */ 1986 rc = ddi_regs_map_setup(dip, rnumber + 1, addr2p, 0, 0, &dev_attr, 1987 handle2p); 1988 if (rc == DDI_SUCCESS) 1989 return (TRUE); 1990 1991 cmn_err(CE_WARN, "ata: reg tuple 1 map failed, rc=0x%x", rc); 1992 1993 out2: 1994 if (*handle1p != NULL) { 1995 ddi_regs_map_free(handle1p); 1996 *handle1p = NULL; 1997 } 1998 1999 out1: 2000 if (*bm_hdlp != NULL) { 2001 ddi_regs_map_free(bm_hdlp); 2002 *bm_hdlp = NULL; 2003 } 2004 return (FALSE); 2005 2006 } 2007 2008 /* 2009 * 2010 * Currently, the only supported controllers are ones which 2011 * support the SFF-8038 Bus Mastering spec. 2012 * 2013 * Check the parent node's IEEE 1275 class-code property to 2014 * determine if it's an PCI-IDE instance which supports SFF-8038 2015 * Bus Mastering. It's perfectly valid to have a PCI-IDE controller 2016 * that doesn't do Bus Mastering. In that case, my interrupt handler 2017 * only uses the interrupt latch bit in PCI-IDE status register. 2018 * The assumption is that the programming interface byte of the 2019 * class-code property reflects the bus master DMA capability of 2020 * the controller. 2021 * 2022 * Whether the drive support supports the DMA option still needs 2023 * to be checked later. Each individual request also has to be 2024 * checked for alignment and size to decide whether to use the 2025 * DMA transfer mode. 2026 */ 2027 2028 static void 2029 ata_init_pciide( 2030 dev_info_t *dip, 2031 ata_ctl_t *ata_ctlp) 2032 { 2033 uint_t class_code; 2034 uchar_t status; 2035 2036 ata_cntrl_DMA_sel_msg = NULL; 2037 2038 if (ata_ctlp->ac_bmhandle == NULL) { 2039 ata_ctlp->ac_pciide = FALSE; 2040 ata_ctlp->ac_pciide_bm = FALSE; 2041 ata_cntrl_DMA_sel_msg = "cntrl not Bus Master DMA capable"; 2042 return; 2043 } 2044 2045 /* 2046 * check if it's a known bogus PCI-IDE chip 2047 */ 2048 if (ata_check_pciide_blacklist(dip, ATA_BL_BOGUS)) { 2049 ADBG_WARN(("ata_setup_ioaddr pci-ide blacklist\n")); 2050 ata_ctlp->ac_pciide = FALSE; 2051 ata_ctlp->ac_pciide_bm = FALSE; 2052 ata_cntrl_DMA_sel_msg = "cntrl blacklisted"; 2053 return; 2054 } 2055 ata_ctlp->ac_pciide = TRUE; 2056 2057 if (ata_check_pciide_blacklist(dip, ATA_BL_BMSTATREG_PIO_BROKEN)) { 2058 ata_ctlp->ac_flags |= AC_BMSTATREG_PIO_BROKEN; 2059 } 2060 2061 /* 2062 * check for a PCI-IDE chip with a broken DMA engine 2063 */ 2064 if (ata_check_pciide_blacklist(dip, ATA_BL_NODMA)) { 2065 ata_ctlp->ac_pciide_bm = FALSE; 2066 ata_cntrl_DMA_sel_msg = 2067 "cntrl blacklisted/DMA engine broken"; 2068 return; 2069 } 2070 2071 /* 2072 * Check the Programming Interface register to determine 2073 * if this device supports PCI-IDE Bus Mastering. Some PCI-IDE 2074 * devices don't support Bus Mastering or DMA. 2075 * Since we are dealing with pre-qualified pci-ide controller, 2076 * check programming interface byte only. 2077 */ 2078 2079 class_code = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 2080 DDI_PROP_DONTPASS, "class-code", 0); 2081 if ((class_code & PCIIDE_BM_CAP_MASK) != PCIIDE_BM_CAP_MASK) { 2082 ata_ctlp->ac_pciide_bm = FALSE; 2083 ata_cntrl_DMA_sel_msg = 2084 "cntrl not Bus Master DMA capable"; 2085 return; 2086 } 2087 2088 /* 2089 * Avoid doing DMA on "simplex" chips which share hardware 2090 * between channels 2091 */ 2092 status = ddi_get8(ata_ctlp->ac_bmhandle, 2093 (uchar_t *)ata_ctlp->ac_bmaddr + PCIIDE_BMISX_REG); 2094 /* 2095 * Some motherboards have CSB5's that are wired "to emulate CSB4 mode". 2096 * In such a mode, the simplex bit is asserted, but in fact testing 2097 * on such a motherboard has shown that the devices are not simplex 2098 * -- DMA can be used on both channels concurrently with no special 2099 * considerations. For chips like this, we have the ATA_BL_NO_SIMPLEX 2100 * flag set to indicate that the value of the simplex bit can be 2101 * ignored. 2102 */ 2103 2104 if (status & PCIIDE_BMISX_SIMPLEX) { 2105 if (ata_check_pciide_blacklist(dip, ATA_BL_NO_SIMPLEX)) { 2106 cmn_err(CE_WARN, "Ignoring false simplex bit \n"); 2107 2108 } else { 2109 2110 int simplex_dma_channel, *rp, proplen, channel; 2111 int dma_on = FALSE; 2112 2113 /* 2114 * By default,use DMA on channel 0 and PIO on channel 2115 * 1. This can be switched by setting 2116 * ata-simplex-dma-channel to: 2117 * 0 DMA on channel 0 (default without this 2118 * property) 2119 * 1 DMA on channel 1 2120 * any other value: DMA off on both channels. 2121 */ 2122 simplex_dma_channel = ata_prop_lookup_int(DDI_DEV_T_ANY, 2123 ata_ctlp->ac_dip, 0, "ata-simplex-dma-channel", 0); 2124 2125 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 2126 ata_ctlp->ac_dip, DDI_PROP_DONTPASS, "reg", &rp, 2127 (uint_t *)&proplen) == DDI_PROP_SUCCESS) { 2128 2129 channel = *rp; 2130 ddi_prop_free(rp); 2131 2132 if (simplex_dma_channel == channel) { 2133 cmn_err(CE_NOTE, "?ata: simplex " 2134 "controller. DMA on channel" 2135 " %d PIO on channel %d\n", 2136 channel, channel ? 0:1); 2137 dma_on = TRUE; 2138 } else { 2139 ata_cntrl_DMA_sel_msg = 2140 "simplex controller"; 2141 } 2142 } 2143 2144 if (dma_on == FALSE) { 2145 ata_ctlp->ac_pciide_bm = FALSE; 2146 2147 return; 2148 } 2149 } 2150 } 2151 2152 /* 2153 * It's a compatible PCI-IDE Bus Mastering controller, 2154 * allocate and map the DMA Scatter/Gather list (PRDE table). 2155 */ 2156 if (ata_pciide_alloc(dip, ata_ctlp)) 2157 ata_ctlp->ac_pciide_bm = TRUE; 2158 else { 2159 ata_ctlp->ac_pciide_bm = FALSE; 2160 ata_cntrl_DMA_sel_msg = "unable to init DMA S/G list"; 2161 } 2162 } 2163 2164 /* 2165 * 2166 * Determine whether to enable DMA support for this drive. 2167 * The controller and the drive both have to support DMA. 2168 * The controller's capabilities were already checked in 2169 * ata_init_pciide(), now just check the drive's capabilities. 2170 * 2171 */ 2172 2173 static int 2174 ata_init_drive_pcidma( 2175 ata_ctl_t *ata_ctlp, 2176 ata_drv_t *ata_drvp, 2177 dev_info_t *tdip) 2178 { 2179 boolean_t dma; 2180 boolean_t cd_dma; 2181 boolean_t disk_dma; 2182 boolean_t atapi_dma; 2183 int ata_options; 2184 2185 ata_dev_DMA_sel_msg = NULL; 2186 2187 if (ata_ctlp->ac_pciide_bm != TRUE) { 2188 ata_dev_DMA_sel_msg = 2189 "controller is not Bus Master capable"; 2190 2191 return (ATA_DMA_OFF); 2192 } 2193 2194 ata_options = ddi_prop_get_int(DDI_DEV_T_ANY, ata_ctlp->ac_dip, 2195 0, "ata-options", 0); 2196 2197 if (!(ata_options & ATA_OPTIONS_DMA)) { 2198 /* 2199 * Either the ata-options property was not found or 2200 * DMA is not enabled by this property 2201 */ 2202 ata_dev_DMA_sel_msg = 2203 "disabled by \"ata-options\" property"; 2204 2205 return (ATA_DMA_OFF); 2206 } 2207 2208 if (ata_check_drive_blacklist(&ata_drvp->ad_id, ATA_BL_NODMA)) { 2209 ata_dev_DMA_sel_msg = "device not DMA capable; blacklisted"; 2210 2211 return (ATA_DMA_OFF); 2212 } 2213 2214 /* 2215 * DMA mode is mandatory on ATA-3 (or newer) drives but is 2216 * optional on ATA-2 (or older) drives. 2217 * 2218 * On ATA-2 drives the ai_majorversion word will probably 2219 * be 0xffff or 0x0000, check the (now obsolete) DMA bit in 2220 * the capabilities word instead. The order of these tests 2221 * is important since an ATA-3 drive doesn't have to set 2222 * the DMA bit in the capabilities word. 2223 * 2224 */ 2225 2226 if (!((ata_drvp->ad_id.ai_majorversion & 0x8000) == 0 && 2227 ata_drvp->ad_id.ai_majorversion >= (1 << 2)) && 2228 !(ata_drvp->ad_id.ai_cap & ATAC_DMA_SUPPORT)) { 2229 ata_dev_DMA_sel_msg = "device not DMA capable"; 2230 2231 return (ATA_DMA_OFF); 2232 } 2233 2234 dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2235 0, "ata-dma-enabled", TRUE); 2236 disk_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2237 0, "ata-disk-dma-enabled", TRUE); 2238 cd_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2239 0, "atapi-cd-dma-enabled", FALSE); 2240 atapi_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2241 0, "atapi-other-dma-enabled", TRUE); 2242 2243 if (dma == FALSE) { 2244 cmn_err(CE_CONT, "?ata_init_drive_pcidma: " 2245 "DMA disabled by \"ata-dma-enabled\" property"); 2246 ata_dev_DMA_sel_msg = "disabled by prop ata-dma-enabled"; 2247 2248 return (ATA_DMA_OFF); 2249 } 2250 2251 if (IS_CDROM(ata_drvp) == TRUE) { 2252 if (cd_dma == FALSE) { 2253 ata_dev_DMA_sel_msg = 2254 "disabled. Control with \"atapi-cd-dma-enabled\"" 2255 " property"; 2256 2257 return (ATA_DMA_OFF); 2258 } 2259 2260 } else if (ATAPIDRV(ata_drvp) == FALSE) { 2261 if (disk_dma == FALSE) { 2262 ata_dev_DMA_sel_msg = 2263 "disabled by \"ata-disk-dma-enabled\" property"; 2264 2265 return (ATA_DMA_OFF); 2266 } 2267 2268 } else if (atapi_dma == FALSE) { 2269 ata_dev_DMA_sel_msg = 2270 "disabled by \"atapi-other-dma-enabled\" property"; 2271 2272 return (ATA_DMA_OFF); 2273 } 2274 2275 return (ATA_DMA_ON); 2276 } 2277 2278 2279 2280 /* 2281 * this compare routine squeezes out extra blanks and 2282 * returns TRUE if p1 matches the leftmost substring of p2 2283 */ 2284 2285 static int 2286 ata_strncmp( 2287 char *p1, 2288 char *p2, 2289 int cnt) 2290 { 2291 2292 for (;;) { 2293 /* 2294 * skip over any extra blanks in both strings 2295 */ 2296 while (*p1 != '\0' && *p1 == ' ') 2297 p1++; 2298 2299 while (cnt != 0 && *p2 == ' ') { 2300 p2++; 2301 cnt--; 2302 } 2303 2304 /* 2305 * compare the two strings 2306 */ 2307 2308 if (cnt == 0 || *p1 != *p2) 2309 break; 2310 2311 while (cnt > 0 && *p1 == *p2) { 2312 p1++; 2313 p2++; 2314 cnt--; 2315 } 2316 2317 } 2318 2319 /* return TRUE if both strings ended at same point */ 2320 return ((*p1 == '\0') ? TRUE : FALSE); 2321 } 2322 2323 /* 2324 * Per PSARC/1997/281 create variant="atapi" property (if necessary) 2325 * on the target's dev_info node. Currently, the sd target driver 2326 * is the only driver which refers to this property. 2327 * 2328 * If the flag ata_id_debug is set also create the 2329 * the "ata" or "atapi" property on the target's dev_info node 2330 * 2331 */ 2332 2333 int 2334 ata_prop_create( 2335 dev_info_t *tgt_dip, 2336 ata_drv_t *ata_drvp, 2337 char *name) 2338 { 2339 int rc; 2340 2341 ADBG_TRACE(("ata_prop_create 0x%p 0x%p %s\n", tgt_dip, ata_drvp, name)); 2342 2343 if (strcmp("atapi", name) == 0) { 2344 rc = ndi_prop_update_string(DDI_DEV_T_NONE, tgt_dip, 2345 "variant", name); 2346 if (rc != DDI_PROP_SUCCESS) 2347 return (FALSE); 2348 } 2349 2350 if (!ata_id_debug) 2351 return (TRUE); 2352 2353 rc = ndi_prop_update_byte_array(DDI_DEV_T_NONE, tgt_dip, name, 2354 (uchar_t *)&ata_drvp->ad_id, sizeof (ata_drvp->ad_id)); 2355 if (rc != DDI_PROP_SUCCESS) { 2356 ADBG_ERROR(("ata_prop_create failed, rc=%d\n", rc)); 2357 } 2358 return (TRUE); 2359 } 2360 2361 2362 /* *********************************************************************** */ 2363 /* *********************************************************************** */ 2364 /* *********************************************************************** */ 2365 2366 /* 2367 * This state machine doesn't implement the ATAPI Optional Overlap 2368 * feature. You need that feature to efficiently support ATAPI 2369 * tape drives. See the 1394-ATA Tailgate spec (D97107), Figure 24, 2370 * for an example of how to add the necessary additional NextActions 2371 * and NextStates to this FSM and the atapi_fsm, in order to support 2372 * the Overlap Feature. 2373 */ 2374 2375 2376 uchar_t ata_ctlr_fsm_NextAction[ATA_CTLR_NSTATES][ATA_CTLR_NFUNCS] = { 2377 /* --------------------- next action --------------------- | - current - */ 2378 /* start0 --- start1 ---- intr ------ fini --- reset --- */ 2379 { AC_START, AC_START, AC_NADA, AC_NADA, AC_RESET_I }, /* idle */ 2380 { AC_BUSY, AC_BUSY, AC_INTR, AC_FINI, AC_RESET_A }, /* active0 */ 2381 { AC_BUSY, AC_BUSY, AC_INTR, AC_FINI, AC_RESET_A }, /* active1 */ 2382 }; 2383 2384 uchar_t ata_ctlr_fsm_NextState[ATA_CTLR_NSTATES][ATA_CTLR_NFUNCS] = { 2385 2386 /* --------------------- next state --------------------- | - current - */ 2387 /* start0 --- start1 ---- intr ------ fini --- reset --- */ 2388 { AS_ACTIVE0, AS_ACTIVE1, AS_IDLE, AS_IDLE, AS_IDLE }, /* idle */ 2389 { AS_ACTIVE0, AS_ACTIVE0, AS_ACTIVE0, AS_IDLE, AS_ACTIVE0 }, /* active0 */ 2390 { AS_ACTIVE1, AS_ACTIVE1, AS_ACTIVE1, AS_IDLE, AS_ACTIVE1 }, /* active1 */ 2391 }; 2392 2393 2394 static int 2395 ata_ctlr_fsm( 2396 uchar_t fsm_func, 2397 ata_ctl_t *ata_ctlp, 2398 ata_drv_t *ata_drvp, 2399 ata_pkt_t *ata_pktp, 2400 int *DoneFlgp) 2401 { 2402 uchar_t action; 2403 uchar_t current_state; 2404 uchar_t next_state; 2405 int rc; 2406 2407 current_state = ata_ctlp->ac_state; 2408 action = ata_ctlr_fsm_NextAction[current_state][fsm_func]; 2409 next_state = ata_ctlr_fsm_NextState[current_state][fsm_func]; 2410 2411 /* 2412 * Set the controller's new state 2413 */ 2414 ata_ctlp->ac_state = next_state; 2415 switch (action) { 2416 2417 case AC_BUSY: 2418 return (ATA_FSM_RC_BUSY); 2419 2420 case AC_NADA: 2421 return (ATA_FSM_RC_OKAY); 2422 2423 case AC_START: 2424 ASSERT(ata_ctlp->ac_active_pktp == NULL); 2425 ASSERT(ata_ctlp->ac_active_drvp == NULL); 2426 2427 ata_ctlp->ac_active_pktp = ata_pktp; 2428 ata_ctlp->ac_active_drvp = ata_drvp; 2429 2430 rc = (*ata_pktp->ap_start)(ata_ctlp, ata_drvp, ata_pktp); 2431 2432 if (rc == ATA_FSM_RC_BUSY) { 2433 /* the request didn't start, GHD will requeue it */ 2434 ata_ctlp->ac_state = AS_IDLE; 2435 ata_ctlp->ac_active_pktp = NULL; 2436 ata_ctlp->ac_active_drvp = NULL; 2437 } 2438 return (rc); 2439 2440 case AC_INTR: 2441 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2442 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2443 2444 ata_drvp = ata_ctlp->ac_active_drvp; 2445 ata_pktp = ata_ctlp->ac_active_pktp; 2446 return ((*ata_pktp->ap_intr)(ata_ctlp, ata_drvp, ata_pktp)); 2447 2448 case AC_RESET_A: /* Reset, controller active */ 2449 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2450 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2451 2452 /* clean up the active request */ 2453 ata_pktp = ata_ctlp->ac_active_pktp; 2454 ata_pktp->ap_flags |= AP_DEV_RESET | AP_BUS_RESET; 2455 2456 /* halt the DMA engine */ 2457 if (ata_pktp->ap_pciide_dma) { 2458 ata_pciide_dma_stop(ata_ctlp); 2459 (void) ata_pciide_status_clear(ata_ctlp); 2460 } 2461 2462 /* Do a Software Reset to unwedge the bus */ 2463 if (!ata_software_reset(ata_ctlp)) { 2464 return (ATA_FSM_RC_BUSY); 2465 } 2466 2467 /* Then send a DEVICE RESET cmd to each ATAPI device */ 2468 atapi_fsm_reset(ata_ctlp); 2469 return (ATA_FSM_RC_FINI); 2470 2471 case AC_RESET_I: /* Reset, controller idle */ 2472 /* Do a Software Reset to unwedge the bus */ 2473 if (!ata_software_reset(ata_ctlp)) { 2474 return (ATA_FSM_RC_BUSY); 2475 } 2476 2477 /* Then send a DEVICE RESET cmd to each ATAPI device */ 2478 atapi_fsm_reset(ata_ctlp); 2479 return (ATA_FSM_RC_OKAY); 2480 2481 case AC_FINI: 2482 break; 2483 } 2484 2485 /* 2486 * AC_FINI, check ARQ needs to be started or finished 2487 */ 2488 2489 ASSERT(action == AC_FINI); 2490 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2491 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2492 2493 /* 2494 * The active request is done now. 2495 * Disconnect the request from the controller and 2496 * add it to the done queue. 2497 */ 2498 ata_drvp = ata_ctlp->ac_active_drvp; 2499 ata_pktp = ata_ctlp->ac_active_pktp; 2500 2501 /* 2502 * If ARQ pkt is done, get ptr to original pkt and wrap it up. 2503 */ 2504 if (ata_pktp == ata_ctlp->ac_arq_pktp) { 2505 ata_pkt_t *arq_pktp; 2506 2507 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ done\n", ata_ctlp)); 2508 2509 arq_pktp = ata_pktp; 2510 ata_pktp = ata_ctlp->ac_fault_pktp; 2511 ata_ctlp->ac_fault_pktp = NULL; 2512 if (arq_pktp->ap_flags & (AP_ERROR | AP_BUS_RESET)) 2513 ata_pktp->ap_flags |= AP_ARQ_ERROR; 2514 else 2515 ata_pktp->ap_flags |= AP_ARQ_OKAY; 2516 goto all_done; 2517 } 2518 2519 2520 #define AP_ARQ_NEEDED (AP_ARQ_ON_ERROR | AP_GOT_STATUS | AP_ERROR) 2521 2522 /* 2523 * Start ARQ pkt if necessary 2524 */ 2525 if ((ata_pktp->ap_flags & AP_ARQ_NEEDED) == AP_ARQ_NEEDED && 2526 (ata_pktp->ap_status & ATS_ERR)) { 2527 2528 /* set controller state back to active */ 2529 ata_ctlp->ac_state = current_state; 2530 2531 /* try to start the ARQ pkt */ 2532 rc = ata_start_arq(ata_ctlp, ata_drvp, ata_pktp); 2533 2534 if (rc == ATA_FSM_RC_BUSY) { 2535 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ BUSY\n", ata_ctlp)); 2536 /* let the target driver handle the problem */ 2537 ata_ctlp->ac_state = AS_IDLE; 2538 ata_ctlp->ac_active_pktp = NULL; 2539 ata_ctlp->ac_active_drvp = NULL; 2540 ata_ctlp->ac_fault_pktp = NULL; 2541 goto all_done; 2542 } 2543 2544 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ started\n", ata_ctlp)); 2545 return (rc); 2546 } 2547 2548 /* 2549 * Normal completion, no error status, and not an ARQ pkt, 2550 * just fall through. 2551 */ 2552 2553 all_done: 2554 2555 /* 2556 * wrap everything up and tie a ribbon around it 2557 */ 2558 ata_ctlp->ac_active_pktp = NULL; 2559 ata_ctlp->ac_active_drvp = NULL; 2560 if (APKT2GCMD(ata_pktp) != (gcmd_t *)0) { 2561 ghd_complete(&ata_ctlp->ac_ccc, APKT2GCMD(ata_pktp)); 2562 if (DoneFlgp) 2563 *DoneFlgp = TRUE; 2564 } 2565 2566 return (ATA_FSM_RC_OKAY); 2567 } 2568 2569 2570 static int 2571 ata_start_arq( 2572 ata_ctl_t *ata_ctlp, 2573 ata_drv_t *ata_drvp, 2574 ata_pkt_t *ata_pktp) 2575 { 2576 ata_pkt_t *arq_pktp; 2577 int bytes; 2578 uint_t senselen; 2579 2580 ADBG_ARQ(("ata_start_arq 0x%p ARQ needed\n", ata_ctlp)); 2581 2582 /* 2583 * Determine just the size of the Request Sense Data buffer within 2584 * the scsi_arq_status structure. 2585 */ 2586 #define SIZEOF_ARQ_HEADER (sizeof (struct scsi_arq_status) \ 2587 - sizeof (struct scsi_extended_sense)) 2588 senselen = ata_pktp->ap_statuslen - SIZEOF_ARQ_HEADER; 2589 ASSERT(senselen > 0); 2590 2591 2592 /* save ptr to original pkt */ 2593 ata_ctlp->ac_fault_pktp = ata_pktp; 2594 2595 /* switch the controller's active pkt to the ARQ pkt */ 2596 arq_pktp = ata_ctlp->ac_arq_pktp; 2597 ata_ctlp->ac_active_pktp = arq_pktp; 2598 2599 /* finish initializing the ARQ CDB */ 2600 ata_ctlp->ac_arq_cdb[1] = ata_drvp->ad_lun << 4; 2601 ata_ctlp->ac_arq_cdb[4] = senselen; 2602 2603 /* finish initializing the ARQ pkt */ 2604 arq_pktp->ap_v_addr = (caddr_t)&ata_pktp->ap_scbp->sts_sensedata; 2605 2606 arq_pktp->ap_resid = senselen; 2607 arq_pktp->ap_flags = AP_ATAPI | AP_READ; 2608 arq_pktp->ap_cdb_pad = 2609 ((unsigned)(ata_drvp->ad_cdb_len - arq_pktp->ap_cdb_len)) >> 1; 2610 2611 bytes = min(senselen, ATAPI_MAX_BYTES_PER_DRQ); 2612 arq_pktp->ap_hicyl = (uchar_t)(bytes >> 8); 2613 arq_pktp->ap_lwcyl = (uchar_t)bytes; 2614 2615 /* 2616 * This packet is shared by all drives on this controller 2617 * therefore we need to init the drive number on every ARQ. 2618 */ 2619 arq_pktp->ap_hd = ata_drvp->ad_drive_bits; 2620 2621 /* start it up */ 2622 return ((*arq_pktp->ap_start)(ata_ctlp, ata_drvp, arq_pktp)); 2623 } 2624 2625 /* 2626 * 2627 * reset the bus 2628 * 2629 */ 2630 2631 static int 2632 ata_reset_bus( 2633 ata_ctl_t *ata_ctlp) 2634 { 2635 int watchdog; 2636 uchar_t drive; 2637 int rc = FALSE; 2638 uchar_t fsm_func; 2639 int DoneFlg = FALSE; 2640 2641 /* 2642 * Do a Software Reset to unwedge the bus, and send 2643 * ATAPI DEVICE RESET to each ATAPI drive. 2644 */ 2645 fsm_func = ATA_FSM_RESET; 2646 for (watchdog = ata_reset_bus_watchdog; watchdog > 0; watchdog--) { 2647 switch (ata_ctlr_fsm(fsm_func, ata_ctlp, NULL, NULL, 2648 &DoneFlg)) { 2649 case ATA_FSM_RC_OKAY: 2650 rc = TRUE; 2651 goto fsm_done; 2652 2653 case ATA_FSM_RC_BUSY: 2654 return (FALSE); 2655 2656 case ATA_FSM_RC_INTR: 2657 fsm_func = ATA_FSM_INTR; 2658 rc = TRUE; 2659 continue; 2660 2661 case ATA_FSM_RC_FINI: 2662 fsm_func = ATA_FSM_FINI; 2663 rc = TRUE; 2664 continue; 2665 } 2666 } 2667 ADBG_WARN(("ata_reset_bus: watchdog\n")); 2668 2669 fsm_done: 2670 2671 /* 2672 * Reinitialize the ATA drives 2673 */ 2674 for (drive = 0; drive < ATA_MAXTARG; drive++) { 2675 ata_drv_t *ata_drvp; 2676 2677 if ((ata_drvp = CTL2DRV(ata_ctlp, drive, 0)) == NULL) 2678 continue; 2679 2680 if (ATAPIDRV(ata_drvp)) 2681 continue; 2682 2683 /* 2684 * Reprogram the Read/Write Multiple block factor 2685 * and current geometry into the drive. 2686 */ 2687 if (!ata_disk_setup_parms(ata_ctlp, ata_drvp)) 2688 rc = FALSE; 2689 } 2690 2691 /* If DoneFlg is TRUE, it means that ghd_complete() function */ 2692 /* has been already called. In this case ignore any errors and */ 2693 /* return TRUE to the caller, otherwise return the value of rc */ 2694 /* to the caller */ 2695 if (DoneFlg) 2696 return (TRUE); 2697 else 2698 return (rc); 2699 } 2700 2701 2702 /* 2703 * 2704 * Low level routine to toggle the Software Reset bit 2705 * 2706 */ 2707 2708 static int 2709 ata_software_reset( 2710 ata_ctl_t *ata_ctlp) 2711 { 2712 ddi_acc_handle_t io_hdl1 = ata_ctlp->ac_iohandle1; 2713 ddi_acc_handle_t io_hdl2 = ata_ctlp->ac_iohandle2; 2714 hrtime_t deadline; 2715 uint_t usecs_left; 2716 2717 ADBG_TRACE(("ata_reset_bus entered\n")); 2718 2719 /* disable interrupts and turn the software reset bit on */ 2720 ddi_put8(io_hdl2, ata_ctlp->ac_devctl, (ATDC_D3 | ATDC_SRST)); 2721 2722 /* why 30 milliseconds, the ATA/ATAPI-4 spec says 5 usec. */ 2723 drv_usecwait(30000); 2724 2725 /* turn the software reset bit back off */ 2726 ddi_put8(io_hdl2, ata_ctlp->ac_devctl, ATDC_D3); 2727 2728 /* 2729 * Wait for the controller to assert BUSY status. 2730 * I don't think 300 msecs is correct. The ATA/ATAPI-4 2731 * spec says 400 nsecs, (and 2 msecs if device 2732 * was in sleep mode; but we don't put drives to sleep 2733 * so it probably doesn't matter). 2734 */ 2735 drv_usecwait(300000); 2736 2737 /* 2738 * If drive 0 exists the test for completion is simple 2739 */ 2740 deadline = gethrtime() + ((hrtime_t)31 * NANOSEC); 2741 2742 if (CTL2DRV(ata_ctlp, 0, 0)) { 2743 goto wait_for_not_busy; 2744 } 2745 2746 ASSERT(CTL2DRV(ata_ctlp, 1, 0) != NULL); 2747 2748 /* 2749 * This must be a single device configuration, with drive 1 2750 * only. This complicates the test for completion because 2751 * issuing the software reset just caused drive 1 to 2752 * deselect. With drive 1 deselected, if I just read the 2753 * status register to test the BSY bit I get garbage, but 2754 * I can't re-select drive 1 until I'm certain the BSY bit 2755 * is de-asserted. Catch-22. 2756 * 2757 * In ATA/ATAPI-4, rev 15, section 9.16.2, it says to handle 2758 * this situation like this: 2759 */ 2760 2761 /* give up if the drive doesn't settle within 31 seconds */ 2762 while (gethrtime() < deadline) { 2763 /* 2764 * delay 10msec each time around the loop 2765 */ 2766 drv_usecwait(10000); 2767 2768 /* 2769 * try to select drive 1 2770 */ 2771 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, ATDH_DRIVE1); 2772 2773 ddi_put8(io_hdl1, ata_ctlp->ac_sect, 0x55); 2774 ddi_put8(io_hdl1, ata_ctlp->ac_sect, 0xaa); 2775 if (ddi_get8(io_hdl1, ata_ctlp->ac_sect) != 0xaa) 2776 continue; 2777 2778 ddi_put8(io_hdl1, ata_ctlp->ac_count, 0x55); 2779 ddi_put8(io_hdl1, ata_ctlp->ac_count, 0xaa); 2780 if (ddi_get8(io_hdl1, ata_ctlp->ac_count) != 0xaa) 2781 continue; 2782 2783 goto wait_for_not_busy; 2784 } 2785 return (FALSE); 2786 2787 wait_for_not_busy: 2788 2789 /* 2790 * Now wait up to 31 seconds for BUSY to clear. 2791 */ 2792 usecs_left = (deadline - gethrtime()) / 1000; 2793 (void) ata_wait3(io_hdl2, ata_ctlp->ac_ioaddr2, 0, ATS_BSY, 2794 ATS_ERR, ATS_BSY, ATS_DF, ATS_BSY, usecs_left); 2795 2796 return (TRUE); 2797 } 2798 2799 /* 2800 * 2801 * DDI interrupt handler 2802 * 2803 */ 2804 2805 static uint_t 2806 ata_intr( 2807 caddr_t arg) 2808 { 2809 ata_ctl_t *ata_ctlp; 2810 int one_shot = 1; 2811 2812 ata_ctlp = (ata_ctl_t *)arg; 2813 2814 return (ghd_intr(&ata_ctlp->ac_ccc, (void *)&one_shot)); 2815 } 2816 2817 2818 /* 2819 * 2820 * GHD ccc_get_status callback 2821 * 2822 */ 2823 2824 static int 2825 ata_get_status( 2826 void *hba_handle, 2827 void *intr_status) 2828 { 2829 ata_ctl_t *ata_ctlp = (ata_ctl_t *)hba_handle; 2830 uchar_t status; 2831 2832 ADBG_TRACE(("ata_get_status entered\n")); 2833 2834 /* 2835 * ignore interrupts before ata_attach completes 2836 */ 2837 if (!(ata_ctlp->ac_flags & AC_ATTACHED)) 2838 return (FALSE); 2839 2840 /* 2841 * can't be interrupt pending if nothing active 2842 */ 2843 switch (ata_ctlp->ac_state) { 2844 case AS_IDLE: 2845 return (FALSE); 2846 case AS_ACTIVE0: 2847 case AS_ACTIVE1: 2848 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2849 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2850 break; 2851 } 2852 2853 /* 2854 * If this is a PCI-IDE controller, check the PCI-IDE controller's 2855 * interrupt status latch. But don't clear it yet. 2856 * 2857 * AC_BMSTATREG_PIO_BROKEN flag is used currently for 2858 * CMD chips with device id 0x646. Since the interrupt bit on 2859 * Bus master IDE register is not usable when in PIO mode, 2860 * this chip is treated as a legacy device for interrupt 2861 * indication. The following code for CMD 2862 * chips may need to be revisited when we enable support for dma. 2863 * 2864 * CHANGE: DMA is not disabled for these devices. BM intr bit is 2865 * checked only if there was DMA used or BM intr is useable on PIO, 2866 * else treat it as before - as legacy device. 2867 */ 2868 2869 if ((ata_ctlp->ac_pciide) && 2870 ((ata_ctlp->ac_pciide_bm != FALSE) && 2871 ((ata_ctlp->ac_active_pktp->ap_pciide_dma == TRUE) || 2872 !(ata_ctlp->ac_flags & AC_BMSTATREG_PIO_BROKEN)))) { 2873 2874 if (!ata_pciide_status_pending(ata_ctlp)) 2875 return (FALSE); 2876 } else { 2877 /* 2878 * Interrupts from legacy ATA/IDE controllers are 2879 * edge-triggered but the dumb legacy ATA/IDE controllers 2880 * and drives don't have an interrupt status bit. 2881 * 2882 * Use a one_shot variable to make sure we only return 2883 * one status per interrupt. 2884 */ 2885 if (intr_status != NULL) { 2886 int *one_shot = (int *)intr_status; 2887 2888 if (*one_shot == 1) 2889 *one_shot = 0; 2890 else 2891 return (FALSE); 2892 } 2893 } 2894 2895 /* check if device is still busy */ 2896 2897 status = ddi_get8(ata_ctlp->ac_iohandle2, ata_ctlp->ac_altstatus); 2898 if (status & ATS_BSY) 2899 return (FALSE); 2900 return (TRUE); 2901 } 2902 2903 2904 /* 2905 * 2906 * get the current status and clear the IRQ 2907 * 2908 */ 2909 2910 int 2911 ata_get_status_clear_intr( 2912 ata_ctl_t *ata_ctlp, 2913 ata_pkt_t *ata_pktp) 2914 { 2915 uchar_t status; 2916 2917 /* 2918 * Here's where we clear the PCI-IDE interrupt latch. If this 2919 * request used DMA mode then we also have to check and clear 2920 * the DMA error latch at the same time. 2921 */ 2922 2923 if (ata_pktp->ap_pciide_dma) { 2924 if (ata_pciide_status_dmacheck_clear(ata_ctlp)) 2925 ata_pktp->ap_flags |= AP_ERROR | AP_TRAN_ERROR; 2926 } else if ((ata_ctlp->ac_pciide) && 2927 !(ata_ctlp->ac_flags & AC_BMSTATREG_PIO_BROKEN)) { 2928 /* 2929 * Some requests don't use DMA mode and therefore won't 2930 * set the DMA error latch, but we still have to clear 2931 * the interrupt latch. 2932 * Controllers with broken BM intr in PIO mode do not go 2933 * through this path. 2934 */ 2935 (void) ata_pciide_status_clear(ata_ctlp); 2936 } 2937 2938 /* 2939 * this clears the drive's interrupt 2940 */ 2941 status = ddi_get8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_status); 2942 ADBG_TRACE(("ata_get_status_clear_intr: 0x%x\n", status)); 2943 return (status); 2944 } 2945 2946 2947 2948 /* 2949 * 2950 * GHD interrupt handler 2951 * 2952 */ 2953 2954 /* ARGSUSED */ 2955 static void 2956 ata_process_intr( 2957 void *hba_handle, 2958 void *intr_status) 2959 { 2960 ata_ctl_t *ata_ctlp = (ata_ctl_t *)hba_handle; 2961 int watchdog; 2962 uchar_t fsm_func; 2963 int rc; 2964 2965 ADBG_TRACE(("ata_process_intr entered\n")); 2966 2967 /* 2968 * process the ATA or ATAPI interrupt 2969 */ 2970 2971 fsm_func = ATA_FSM_INTR; 2972 for (watchdog = ata_process_intr_watchdog; watchdog > 0; watchdog--) { 2973 rc = ata_ctlr_fsm(fsm_func, ata_ctlp, NULL, NULL, NULL); 2974 2975 switch (rc) { 2976 case ATA_FSM_RC_OKAY: 2977 return; 2978 2979 case ATA_FSM_RC_BUSY: /* wait for the next interrupt */ 2980 return; 2981 2982 case ATA_FSM_RC_INTR: /* re-invoke the FSM */ 2983 fsm_func = ATA_FSM_INTR; 2984 break; 2985 2986 case ATA_FSM_RC_FINI: /* move a request to done Q */ 2987 fsm_func = ATA_FSM_FINI; 2988 break; 2989 } 2990 } 2991 ADBG_WARN(("ata_process_intr: watchdog\n")); 2992 } 2993 2994 2995 2996 /* 2997 * 2998 * GHD ccc_hba_start callback 2999 * 3000 */ 3001 3002 static int 3003 ata_hba_start( 3004 void *hba_handle, 3005 gcmd_t *gcmdp) 3006 { 3007 ata_ctl_t *ata_ctlp; 3008 ata_drv_t *ata_drvp; 3009 ata_pkt_t *ata_pktp; 3010 uchar_t fsm_func; 3011 int request_started; 3012 int watchdog; 3013 3014 ADBG_TRACE(("ata_hba_start entered\n")); 3015 3016 ata_ctlp = (ata_ctl_t *)hba_handle; 3017 3018 if (ata_ctlp->ac_active_drvp != NULL) { 3019 ADBG_WARN(("ata_hba_start drvp not null\n")); 3020 return (FALSE); 3021 } 3022 if (ata_ctlp->ac_active_pktp != NULL) { 3023 ADBG_WARN(("ata_hba_start pktp not null\n")); 3024 return (FALSE); 3025 } 3026 3027 ata_pktp = GCMD2APKT(gcmdp); 3028 ata_drvp = GCMD2DRV(gcmdp); 3029 3030 /* 3031 * which drive? 3032 */ 3033 if (ata_drvp->ad_targ == 0) 3034 fsm_func = ATA_FSM_START0; 3035 else 3036 fsm_func = ATA_FSM_START1; 3037 3038 /* 3039 * start the request 3040 */ 3041 request_started = FALSE; 3042 for (watchdog = ata_hba_start_watchdog; watchdog > 0; watchdog--) { 3043 switch (ata_ctlr_fsm(fsm_func, ata_ctlp, ata_drvp, ata_pktp, 3044 NULL)) { 3045 case ATA_FSM_RC_OKAY: 3046 request_started = TRUE; 3047 goto fsm_done; 3048 3049 case ATA_FSM_RC_BUSY: 3050 /* if first time, tell GHD to requeue the request */ 3051 goto fsm_done; 3052 3053 case ATA_FSM_RC_INTR: 3054 /* 3055 * The start function polled for the next 3056 * bus phase, now fake an interrupt to process 3057 * the next action. 3058 */ 3059 request_started = TRUE; 3060 fsm_func = ATA_FSM_INTR; 3061 ata_drvp = NULL; 3062 ata_pktp = NULL; 3063 break; 3064 3065 case ATA_FSM_RC_FINI: /* move request to the done queue */ 3066 request_started = TRUE; 3067 fsm_func = ATA_FSM_FINI; 3068 ata_drvp = NULL; 3069 ata_pktp = NULL; 3070 break; 3071 } 3072 } 3073 ADBG_WARN(("ata_hba_start: watchdog\n")); 3074 3075 fsm_done: 3076 return (request_started); 3077 3078 } 3079 3080 static int 3081 ata_check_pciide_blacklist( 3082 dev_info_t *dip, 3083 uint_t flags) 3084 { 3085 ushort_t vendorid; 3086 ushort_t deviceid; 3087 pcibl_t *blp; 3088 int *propp; 3089 uint_t count; 3090 int rc; 3091 3092 3093 vendorid = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3094 DDI_PROP_DONTPASS, "vendor-id", 0); 3095 deviceid = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3096 DDI_PROP_DONTPASS, "device-id", 0); 3097 3098 /* 3099 * first check for a match in the "pci-ide-blacklist" property 3100 */ 3101 rc = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, 3102 "pci-ide-blacklist", &propp, &count); 3103 3104 if (rc == DDI_PROP_SUCCESS) { 3105 count = (count * sizeof (uint_t)) / sizeof (pcibl_t); 3106 blp = (pcibl_t *)propp; 3107 while (count--) { 3108 /* check for matching ID */ 3109 if ((vendorid & blp->b_vmask) 3110 != (blp->b_vendorid & blp->b_vmask)) { 3111 blp++; 3112 continue; 3113 } 3114 if ((deviceid & blp->b_dmask) 3115 != (blp->b_deviceid & blp->b_dmask)) { 3116 blp++; 3117 continue; 3118 } 3119 3120 /* got a match */ 3121 if (blp->b_flags & flags) { 3122 ddi_prop_free(propp); 3123 return (TRUE); 3124 } else { 3125 ddi_prop_free(propp); 3126 return (FALSE); 3127 } 3128 } 3129 ddi_prop_free(propp); 3130 } 3131 3132 /* 3133 * then check the built-in blacklist 3134 */ 3135 for (blp = ata_pciide_blacklist; blp->b_vendorid; blp++) { 3136 if ((vendorid & blp->b_vmask) != blp->b_vendorid) 3137 continue; 3138 if ((deviceid & blp->b_dmask) != blp->b_deviceid) 3139 continue; 3140 if (!(blp->b_flags & flags)) 3141 continue; 3142 return (TRUE); 3143 } 3144 return (FALSE); 3145 } 3146 3147 int 3148 ata_check_drive_blacklist( 3149 struct ata_id *aidp, 3150 uint_t flags) 3151 { 3152 atabl_t *blp; 3153 3154 for (blp = ata_drive_blacklist; blp->b_model; blp++) { 3155 if (!ata_strncmp(blp->b_model, aidp->ai_model, 3156 sizeof (aidp->ai_model))) 3157 continue; 3158 if (blp->b_flags & flags) 3159 return (TRUE); 3160 return (FALSE); 3161 } 3162 return (FALSE); 3163 } 3164 3165 /* 3166 * Queue a request to perform some sort of internally 3167 * generated command. When this request packet reaches 3168 * the front of the queue (*func)() is invoked. 3169 * 3170 */ 3171 3172 int 3173 ata_queue_cmd( 3174 int (*func)(ata_ctl_t *, ata_drv_t *, ata_pkt_t *), 3175 void *arg, 3176 ata_ctl_t *ata_ctlp, 3177 ata_drv_t *ata_drvp, 3178 gtgt_t *gtgtp) 3179 { 3180 ata_pkt_t *ata_pktp; 3181 gcmd_t *gcmdp; 3182 int rc; 3183 3184 if (!(gcmdp = ghd_gcmd_alloc(gtgtp, sizeof (*ata_pktp), TRUE))) { 3185 ADBG_ERROR(("atapi_id_update alloc failed\n")); 3186 return (FALSE); 3187 } 3188 3189 3190 /* set the back ptr from the ata_pkt to the gcmd_t */ 3191 ata_pktp = GCMD2APKT(gcmdp); 3192 ata_pktp->ap_gcmdp = gcmdp; 3193 ata_pktp->ap_hd = ata_drvp->ad_drive_bits; 3194 ata_pktp->ap_bytes_per_block = ata_drvp->ad_bytes_per_block; 3195 3196 /* 3197 * over-ride the default start function 3198 */ 3199 ata_pktp = GCMD2APKT(gcmdp); 3200 ata_pktp->ap_start = func; 3201 ata_pktp->ap_complete = NULL; 3202 ata_pktp->ap_v_addr = (caddr_t)arg; 3203 3204 /* 3205 * add it to the queue, when it gets to the front the 3206 * ap_start function is called. 3207 */ 3208 rc = ghd_transport(&ata_ctlp->ac_ccc, gcmdp, gcmdp->cmd_gtgtp, 3209 0, TRUE, NULL); 3210 3211 if (rc != TRAN_ACCEPT) { 3212 /* this should never, ever happen */ 3213 return (FALSE); 3214 } 3215 3216 if (ata_pktp->ap_flags & AP_ERROR) 3217 return (FALSE); 3218 return (TRUE); 3219 } 3220 3221 /* 3222 * Check if this drive has the "revert to defaults" bug 3223 * PSARC 2001/500 and 2001/xxx - check for the properties 3224 * ata-revert-to-defaults and atarvrt-<diskmodel> before 3225 * examining the blacklist. 3226 * <diskmodel> is made from the model number reported by Identify Drive 3227 * with uppercase letters converted to lowercase and all characters 3228 * except letters, digits, ".", "_", and "-" deleted. 3229 * Return value: 3230 * TRUE: enable revert to defaults 3231 * FALSE: disable revert to defaults 3232 * 3233 * NOTE: revert to power on defaults that includes reverting to MDMA 3234 * mode is allowed by ATA-6 & ATA-7 specs. 3235 * Therefore drives exhibiting this behaviour are not violating the spec. 3236 * Furthermore, the spec explicitly says that after the soft reset 3237 * host should check the current setting of the device features. 3238 * Correctly working BIOS would therefore reprogram either the drive 3239 * and/or the host controller to match transfer modes. 3240 * Devices with ATA_BL_NORVRT flag will be removed from 3241 * the ata_blacklist. 3242 * The default behaviour will be - no revert to power-on defaults 3243 * for all devices. The property is retained in case the user 3244 * explicitly requests revert-to-defaults before reboot. 3245 */ 3246 3247 #define ATA_REVERT_PROP_PREFIX "revert-" 3248 #define ATA_REVERT_PROP_GLOBAL "ata-revert-to-defaults" 3249 /* room for prefix + model number + terminating NUL character */ 3250 #define PROP_BUF_SIZE (sizeof (ATA_REVERT_PROP_PREFIX) + \ 3251 sizeof (aidp->ai_model) + 1) 3252 #define PROP_LEN_MAX (31) 3253 3254 static int 3255 ata_check_revert_to_defaults( 3256 ata_drv_t *ata_drvp) 3257 { 3258 struct ata_id *aidp = &ata_drvp->ad_id; 3259 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp; 3260 char prop_buf[PROP_BUF_SIZE]; 3261 int i, j; 3262 int propval; 3263 3264 /* put prefix into the buffer */ 3265 (void) strcpy(prop_buf, ATA_REVERT_PROP_PREFIX); 3266 j = strlen(prop_buf); 3267 3268 /* append the model number, leaving out invalid characters */ 3269 for (i = 0; i < sizeof (aidp->ai_model); ++i) { 3270 char c = aidp->ai_model[i]; 3271 if (c >= 'A' && c <= 'Z') /* uppercase -> lower */ 3272 c = c - 'A' + 'a'; 3273 if (c >= 'a' && c <= 'z' || c >= '0' && c <= '9' || 3274 c == '.' || c == '_' || c == '-') 3275 prop_buf[j++] = c; 3276 if (c == '\0') 3277 break; 3278 } 3279 3280 /* make sure there's a terminating NUL character */ 3281 if (j >= PROP_LEN_MAX) 3282 j = PROP_LEN_MAX; 3283 prop_buf[j] = '\0'; 3284 3285 /* look for a disk-specific "revert" property" */ 3286 propval = ddi_getprop(DDI_DEV_T_ANY, ata_ctlp->ac_dip, 3287 DDI_PROP_DONTPASS, prop_buf, -1); 3288 if (propval == 0) 3289 return (FALSE); 3290 else if (propval != -1) 3291 return (TRUE); 3292 3293 /* look for a global "revert" property" */ 3294 propval = ddi_getprop(DDI_DEV_T_ANY, ata_ctlp->ac_dip, 3295 0, ATA_REVERT_PROP_GLOBAL, -1); 3296 if (propval == 0) 3297 return (FALSE); 3298 else if (propval != -1) 3299 return (TRUE); 3300 3301 return (FALSE); 3302 } 3303 3304 void 3305 ata_show_transfer_mode(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp) 3306 { 3307 int i; 3308 3309 if (ata_ctlp->ac_pciide_bm == FALSE || 3310 ata_drvp->ad_pciide_dma != ATA_DMA_ON) { 3311 if (ata_cntrl_DMA_sel_msg) { 3312 ATAPRT(( 3313 "?\tATA DMA off: %s\n", ata_cntrl_DMA_sel_msg)); 3314 } else if (ata_dev_DMA_sel_msg) { 3315 ATAPRT(("?\tATA DMA off: %s\n", ata_dev_DMA_sel_msg)); 3316 } 3317 ATAPRT(("?\tPIO mode %d selected\n", 3318 (ata_drvp->ad_id.ai_advpiomode & ATAC_ADVPIO_4_SUP) == 3319 ATAC_ADVPIO_4_SUP ? 4 : 3)); 3320 } else { 3321 /* Using DMA */ 3322 if (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_SEL_MASK) { 3323 /* 3324 * Rely on the fact that either dwdma or udma is 3325 * selected, not both. 3326 */ 3327 ATAPRT(("?\tMultiwordDMA mode %d selected\n", 3328 (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_2_SEL) == 3329 ATAC_MDMA_2_SEL ? 2 : 3330 (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_1_SEL) == 3331 ATAC_MDMA_1_SEL ? 1 : 0)); 3332 } else { 3333 for (i = 0; i <= 6; i++) { 3334 if (ata_drvp->ad_id.ai_ultradma & 3335 (1 << (i + 8))) { 3336 ATAPRT(( 3337 "?\tUltraDMA mode %d selected\n", 3338 i)); 3339 break; 3340 } 3341 } 3342 } 3343 } 3344 } 3345 3346 /* 3347 * Controller-specific operation pointers. 3348 * Should be extended as needed - init only for now 3349 */ 3350 struct ata_ctl_spec_ops { 3351 uint_t (*cs_init)(dev_info_t *, ushort_t, ushort_t); /* ctlr init */ 3352 }; 3353 3354 3355 struct ata_ctl_spec { 3356 ushort_t cs_vendor_id; 3357 ushort_t cs_device_id; 3358 struct ata_ctl_spec_ops *cs_ops; 3359 }; 3360 3361 /* Sil3XXX-specific functions (init only for now) */ 3362 struct ata_ctl_spec_ops sil3xxx_ops = { 3363 &sil3xxx_init_controller /* Sil3XXX cntrl initialization */ 3364 }; 3365 3366 3367 struct ata_ctl_spec ata_cntrls_spec[] = { 3368 {0x1095, 0x3114, &sil3xxx_ops}, 3369 {0x1095, 0x3512, &sil3xxx_ops}, 3370 {0x1095, 0x3112, &sil3xxx_ops}, 3371 {0, 0, NULL} /* List must end with cs_ops set to NULL */ 3372 }; 3373 3374 /* 3375 * Do controller specific initialization if necessary. 3376 * Pick-up controller specific functions. 3377 */ 3378 3379 int 3380 ata_spec_init_controller(dev_info_t *dip) 3381 { 3382 ushort_t vendor_id; 3383 ushort_t device_id; 3384 struct ata_ctl_spec *ctlsp; 3385 3386 vendor_id = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3387 DDI_PROP_DONTPASS, "vendor-id", 0); 3388 device_id = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3389 DDI_PROP_DONTPASS, "device-id", 0); 3390 3391 /* Locate controller specific ops, if they exist */ 3392 ctlsp = ata_cntrls_spec; 3393 while (ctlsp->cs_ops != NULL) { 3394 if (ctlsp->cs_vendor_id == vendor_id && 3395 ctlsp->cs_device_id == device_id) 3396 break; 3397 ctlsp++; 3398 } 3399 3400 if (ctlsp->cs_ops != NULL) { 3401 if (ctlsp->cs_ops->cs_init != NULL) { 3402 /* Initialize controller */ 3403 if ((*(ctlsp->cs_ops->cs_init)) 3404 (dip, vendor_id, device_id) != TRUE) { 3405 cmn_err(CE_WARN, 3406 "pci%4x,%4x cntrl specific " 3407 "initialization failed", 3408 vendor_id, device_id); 3409 return (FALSE); 3410 } 3411 } 3412 } 3413 return (TRUE); 3414 } 3415 3416 /* 3417 * this routine works like ddi_prop_get_int, except that it works on 3418 * a string property that contains ascii representations 3419 * of an integer. 3420 * If the property is not found, the default value is returned. 3421 */ 3422 static int 3423 ata_prop_lookup_int(dev_t match_dev, dev_info_t *dip, 3424 uint_t flags, char *name, int defvalue) 3425 { 3426 3427 char *bufp, *cp; 3428 int rc = defvalue; 3429 int proprc; 3430 3431 proprc = ddi_prop_lookup_string(match_dev, dip, 3432 flags, name, &bufp); 3433 3434 if (proprc == DDI_PROP_SUCCESS) { 3435 cp = bufp; 3436 rc = stoi(&cp); 3437 ddi_prop_free(bufp); 3438 } else { 3439 /* 3440 * see if property is encoded as an int instead of string. 3441 */ 3442 rc = ddi_prop_get_int(match_dev, dip, flags, name, defvalue); 3443 } 3444 3445 return (rc); 3446 } 3447