1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/modctl.h> 31 #include <sys/debug.h> 32 #include <sys/promif.h> 33 #include <sys/pci.h> 34 #include <sys/errno.h> 35 #include <sys/open.h> 36 #include <sys/uio.h> 37 #include <sys/cred.h> 38 #include <sys/cpu.h> 39 #include "ata_common.h" 40 #include "ata_disk.h" 41 #include "atapi.h" 42 #include "ata_blacklist.h" 43 #include "sil3xxx.h" 44 45 /* 46 * Solaris Entry Points. 47 */ 48 49 static int ata_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 50 static int ata_detach(dev_info_t *dip, ddi_detach_cmd_t cmd); 51 static int ata_bus_ctl(dev_info_t *d, dev_info_t *r, ddi_ctl_enum_t o, 52 void *a, void *v); 53 static uint_t ata_intr(caddr_t arg); 54 55 /* 56 * GHD Entry points 57 */ 58 59 static int ata_get_status(void *hba_handle, void *intr_status); 60 static void ata_process_intr(void *hba_handle, void *intr_status); 61 static int ata_hba_start(void *handle, gcmd_t *gcmdp); 62 static void ata_hba_complete(void *handle, gcmd_t *gcmdp, int do_callback); 63 static int ata_timeout_func(void *hba_handle, gcmd_t *gcmdp, 64 gtgt_t *gtgtp, gact_t action, int calltype); 65 66 /* 67 * Local Function Prototypes 68 */ 69 static int ata_prop_lookup_int(dev_t match_dev, dev_info_t *dip, 70 uint_t flags, char *name, int defvalue); 71 static int ata_ctlr_fsm(uchar_t fsm_func, ata_ctl_t *ata_ctlp, 72 ata_drv_t *ata_drvp, ata_pkt_t *ata_pktp, 73 int *DoneFlgp); 74 static void ata_destroy_controller(dev_info_t *dip); 75 static int ata_drive_type(uchar_t drvhd, 76 ddi_acc_handle_t io_hdl1, caddr_t ioaddr1, 77 ddi_acc_handle_t io_hdl2, caddr_t ioaddr2, 78 struct ata_id *ata_id_bufp); 79 static ata_ctl_t *ata_init_controller(dev_info_t *dip); 80 static ata_drv_t *ata_init_drive(ata_ctl_t *ata_ctlp, 81 uchar_t targ, uchar_t lun); 82 static int ata_init_drive_pcidma(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 83 dev_info_t *tdip); 84 static int ata_flush_cache(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp); 85 static void ata_init_pciide(dev_info_t *dip, ata_ctl_t *ata_ctlp); 86 static int ata_reset_bus(ata_ctl_t *ata_ctlp); 87 static int ata_setup_ioaddr(dev_info_t *dip, 88 ddi_acc_handle_t *iohandle1, caddr_t *ioaddr1p, 89 ddi_acc_handle_t *iohandle2, caddr_t *ioaddr2p, 90 ddi_acc_handle_t *bm_hdlp, caddr_t *bm_addrp); 91 static int ata_software_reset(ata_ctl_t *ata_ctlp); 92 static int ata_start_arq(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 93 ata_pkt_t *ata_pktp); 94 static int ata_strncmp(char *p1, char *p2, int cnt); 95 static void ata_uninit_drive(ata_drv_t *ata_drvp); 96 97 static int ata_check_pciide_blacklist(dev_info_t *dip, uint_t flags); 98 static int ata_check_revert_to_defaults(ata_drv_t *ata_drvp); 99 static void ata_show_transfer_mode(ata_ctl_t *, ata_drv_t *); 100 static int ata_spec_init_controller(dev_info_t *dip); 101 102 static void ata_init_pm(dev_info_t *); 103 static int ata_suspend(dev_info_t *); 104 static int ata_resume(dev_info_t *); 105 static int ata_power(dev_info_t *, int, int); 106 static int ata_change_power(dev_info_t *, uint8_t); 107 static int ata_is_pci(dev_info_t *); 108 109 /* 110 * Local static data 111 */ 112 static void *ata_state; 113 114 static tmr_t ata_timer_conf; /* single timeout list for all instances */ 115 static int ata_watchdog_usec = 100000; /* check timeouts every 100 ms */ 116 117 int ata_hba_start_watchdog = 1000; 118 int ata_process_intr_watchdog = 1000; 119 int ata_reset_bus_watchdog = 1000; 120 121 122 /* 123 * Use local or framework power management 124 */ 125 126 #ifdef ATA_USE_AUTOPM 127 #define ATA_BUSY_COMPONENT(d, c) ((void)pm_busy_component(d, c)) 128 #define ATA_IDLE_COMPONENT(d, c) ((void)pm_idle_component(d, c)) 129 #define ATA_RAISE_POWER(d, c, l) pm_raise_power(d, c, l) 130 #define ATA_LOWER_POWER(d, c, l) pm_lower_power(d, c, l) 131 #else 132 #define ATA_BUSY_COMPONENT(d, c) 133 #define ATA_IDLE_COMPONENT(d, c) 134 #define ATA_RAISE_POWER(d, c, l) ata_power(d, c, l) 135 #define ATA_LOWER_POWER(d, c, l) ata_power(d, c, l) 136 #endif 137 /* 138 * number of seconds to wait during various operations 139 */ 140 int ata_flush_delay = 5 * 1000000; 141 uint_t ata_set_feature_wait = 4 * 1000000; 142 uint_t ata_flush_cache_wait = 60 * 1000000; /* may take a long time */ 143 144 /* 145 * Change this for SFF-8070i support. Currently SFF-8070i is 146 * using a field in the IDENTIFY PACKET DEVICE response which 147 * already seems to be in use by some vendor's drives. I suspect 148 * SFF will either move their laslun field or provide a reliable 149 * way to validate it. 150 */ 151 int ata_enable_atapi_luns = FALSE; 152 153 /* 154 * set this to disable all DMA requests 155 */ 156 int ata_dma_disabled = FALSE; 157 158 /* 159 * set this to TRUE to enable storing the IDENTIFY DEVICE result in the 160 * "ata" or "atapi" property. 161 */ 162 int ata_id_debug = FALSE; 163 164 /* 165 * set this to TRUE to enable logging device-capability data 166 */ 167 int ata_capability_data = FALSE; 168 169 /* 170 * DMA selection message pointers 171 */ 172 char *ata_cntrl_DMA_sel_msg; 173 char *ata_dev_DMA_sel_msg; 174 175 /* 176 * bus nexus operations 177 */ 178 static struct bus_ops ata_bus_ops; 179 static struct bus_ops *scsa_bus_ops_p; 180 181 /* ARGSUSED */ 182 static int 183 ata_open(dev_t *devp, int flag, int otyp, cred_t *cred_p) 184 { 185 if (ddi_get_soft_state(ata_state, getminor(*devp)) == NULL) 186 return (ENXIO); 187 188 return (0); 189 } 190 191 /* 192 * The purpose of this function is to pass the ioaddress of the controller 193 * to the caller, specifically used for upgrade from pre-pciide 194 * to pciide nodes 195 */ 196 /* ARGSUSED */ 197 static int 198 ata_read(dev_t dev, struct uio *uio_p, cred_t *cred_p) 199 { 200 ata_ctl_t *ata_ctlp; 201 char buf[18]; 202 long len; 203 204 ata_ctlp = ddi_get_soft_state(ata_state, getminor(dev)); 205 206 if (ata_ctlp == NULL) 207 return (ENXIO); 208 209 (void) sprintf(buf, "%p\n", (void *) ata_ctlp->ac_ioaddr1); 210 211 len = strlen(buf) - uio_p->uio_offset; 212 len = min(uio_p->uio_resid, len); 213 if (len <= 0) 214 return (0); 215 216 return (uiomove((caddr_t)(buf + uio_p->uio_offset), len, 217 UIO_READ, uio_p)); 218 } 219 220 int 221 ata_devo_reset( 222 dev_info_t *dip, 223 ddi_reset_cmd_t cmd) 224 { 225 ata_ctl_t *ata_ctlp; 226 ata_drv_t *ata_drvp; 227 int instance; 228 int i; 229 int rc; 230 int flush_okay; 231 232 if (cmd != DDI_RESET_FORCE) 233 return (0); 234 235 instance = ddi_get_instance(dip); 236 ata_ctlp = ddi_get_soft_state(ata_state, instance); 237 238 if (!ata_ctlp) 239 return (0); 240 241 /* 242 * reset ATA drives and flush the write cache of any drives 243 */ 244 flush_okay = TRUE; 245 for (i = 0; i < ATA_MAXTARG; i++) { 246 if ((ata_drvp = CTL2DRV(ata_ctlp, i, 0)) == 0) 247 continue; 248 /* Don't revert to defaults for certain IBM drives */ 249 if ((ata_drvp->ad_flags & AD_DISK) != 0 && 250 ((ata_drvp->ad_flags & AD_NORVRT) == 0)) { 251 /* Enable revert to defaults when reset */ 252 (void) ata_set_feature(ata_ctlp, ata_drvp, 253 ATSF_ENA_REVPOD, 0); 254 } 255 256 /* 257 * skip flush cache if device type is cdrom 258 * 259 * notes: the structure definitions for ata_drvp->ad_id are 260 * defined for the ATA IDENTIFY_DEVICE, but if AD_ATAPI is set 261 * the struct holds data for the ATAPI IDENTIFY_PACKET_DEVICE 262 */ 263 if (!IS_CDROM(ata_drvp)) { 264 265 /* 266 * Try the ATA/ATAPI flush write cache command 267 */ 268 rc = ata_flush_cache(ata_ctlp, ata_drvp); 269 ADBG_WARN(("ata_flush_cache %s\n", 270 rc ? "okay" : "failed")); 271 272 if (!rc) 273 flush_okay = FALSE; 274 } 275 276 277 /* 278 * do something else if flush cache not supported 279 */ 280 } 281 282 /* 283 * just busy wait if any drive doesn't support FLUSH CACHE 284 */ 285 if (!flush_okay) 286 drv_usecwait(ata_flush_delay); 287 return (0); 288 } 289 290 291 static struct cb_ops ata_cb_ops = { 292 ata_open, /* open */ 293 nulldev, /* close */ 294 nodev, /* strategy */ 295 nodev, /* print */ 296 nodev, /* dump */ 297 ata_read, /* read */ 298 nodev, /* write */ 299 nodev, /* ioctl */ 300 nodev, /* devmap */ 301 nodev, /* mmap */ 302 nodev, /* segmap */ 303 nochpoll, /* chpoll */ 304 ddi_prop_op, /* prop_op */ 305 NULL, /* stream info */ 306 D_MP, /* driver compatibility flag */ 307 CB_REV, /* cb_ops revision */ 308 nodev, /* aread */ 309 nodev /* awrite */ 310 }; 311 312 static struct dev_ops ata_ops = { 313 DEVO_REV, /* devo_rev, */ 314 0, /* refcnt */ 315 ddi_getinfo_1to1, /* info */ 316 nulldev, /* identify */ 317 NULL, /* probe */ 318 ata_attach, /* attach */ 319 ata_detach, /* detach */ 320 ata_devo_reset, /* reset */ 321 &ata_cb_ops, /* driver operations */ 322 NULL, /* bus operations */ 323 ata_power /* power */ 324 }; 325 326 /* driver loadable module wrapper */ 327 static struct modldrv modldrv = { 328 &mod_driverops, /* Type of module. This one is a driver */ 329 "ATA AT-bus attachment disk controller Driver", /* module name */ 330 &ata_ops, /* driver ops */ 331 }; 332 333 static struct modlinkage modlinkage = { 334 MODREV_1, (void *)&modldrv, NULL 335 }; 336 337 #ifdef ATA_DEBUG 338 int ata_debug_init = FALSE; 339 int ata_debug_attach = FALSE; 340 341 int ata_debug = ADBG_FLAG_ERROR 342 /* | ADBG_FLAG_ARQ */ 343 /* | ADBG_FLAG_INIT */ 344 /* | ADBG_FLAG_TRACE */ 345 /* | ADBG_FLAG_TRANSPORT */ 346 /* | ADBG_FLAG_WARN */ 347 ; 348 #endif 349 350 int 351 _init(void) 352 { 353 int err; 354 355 #ifdef ATA_DEBUG 356 if (ata_debug_init) 357 debug_enter("\nATA _INIT\n"); 358 #endif 359 360 if ((err = ddi_soft_state_init(&ata_state, sizeof (ata_ctl_t), 0)) != 0) 361 return (err); 362 363 if ((err = scsi_hba_init(&modlinkage)) != 0) { 364 ddi_soft_state_fini(&ata_state); 365 return (err); 366 } 367 368 /* save pointer to SCSA provided bus_ops struct */ 369 scsa_bus_ops_p = ata_ops.devo_bus_ops; 370 371 /* make a copy of SCSA bus_ops */ 372 ata_bus_ops = *(ata_ops.devo_bus_ops); 373 374 /* 375 * Modify our bus_ops to call our routines. Our implementation 376 * will determine if the device is ATA or ATAPI/SCSA and react 377 * accordingly. 378 */ 379 ata_bus_ops.bus_ctl = ata_bus_ctl; 380 381 /* patch our bus_ops into the dev_ops struct */ 382 ata_ops.devo_bus_ops = &ata_bus_ops; 383 384 if ((err = mod_install(&modlinkage)) != 0) { 385 scsi_hba_fini(&modlinkage); 386 ddi_soft_state_fini(&ata_state); 387 } 388 389 /* 390 * Initialize the per driver timer info. 391 */ 392 393 ghd_timer_init(&ata_timer_conf, drv_usectohz(ata_watchdog_usec)); 394 395 return (err); 396 } 397 398 int 399 _fini(void) 400 { 401 int err; 402 403 if ((err = mod_remove(&modlinkage)) == 0) { 404 ghd_timer_fini(&ata_timer_conf); 405 scsi_hba_fini(&modlinkage); 406 ddi_soft_state_fini(&ata_state); 407 } 408 409 return (err); 410 } 411 412 int 413 _info(struct modinfo *modinfop) 414 { 415 return (mod_info(&modlinkage, modinfop)); 416 } 417 418 419 /* 420 * 421 * driver attach entry point 422 * 423 */ 424 425 static int 426 ata_attach( 427 dev_info_t *dip, 428 ddi_attach_cmd_t cmd) 429 { 430 ata_ctl_t *ata_ctlp; 431 ata_drv_t *ata_drvp; 432 ata_drv_t *first_drvp = NULL; 433 uchar_t targ; 434 uchar_t lun; 435 uchar_t lastlun; 436 int atapi_count = 0; 437 int disk_count = 0; 438 439 ADBG_TRACE(("ata_attach entered\n")); 440 #ifdef ATA_DEBUG 441 if (ata_debug_attach) 442 debug_enter("\nATA_ATTACH\n\n"); 443 #endif 444 445 switch (cmd) { 446 case DDI_ATTACH: 447 break; 448 case DDI_RESUME: 449 return (ata_resume(dip)); 450 default: 451 return (DDI_FAILURE); 452 } 453 454 /* initialize controller */ 455 ata_ctlp = ata_init_controller(dip); 456 457 if (ata_ctlp == NULL) 458 goto errout; 459 460 mutex_enter(&ata_ctlp->ac_ccc.ccc_hba_mutex); 461 462 /* initialize drives */ 463 464 for (targ = 0; targ < ATA_MAXTARG; targ++) { 465 466 ata_drvp = ata_init_drive(ata_ctlp, targ, 0); 467 if (ata_drvp == NULL) 468 continue; 469 470 if (first_drvp == NULL) 471 first_drvp = ata_drvp; 472 473 if (ATAPIDRV(ata_drvp)) { 474 atapi_count++; 475 lastlun = ata_drvp->ad_id.ai_lastlun; 476 } else { 477 disk_count++; 478 lastlun = 0; 479 } 480 481 /* 482 * LUN support is currently disabled. Check with SFF-8070i 483 * before enabling. 484 */ 485 if (!ata_enable_atapi_luns) 486 lastlun = 0; 487 488 /* Initialize higher LUNs, if there are any */ 489 for (lun = 1; lun <= lastlun && lun < ATA_MAXLUN; lun++) { 490 if ((ata_drvp = 491 ata_init_drive(ata_ctlp, targ, lun)) != NULL) { 492 ata_show_transfer_mode(ata_ctlp, ata_drvp); 493 } 494 } 495 } 496 497 if ((atapi_count == 0) && (disk_count == 0)) { 498 ADBG_WARN(("ata_attach: no drives detected\n")); 499 goto errout1; 500 } 501 502 /* 503 * Always make certain that a valid drive is selected so 504 * that routines which poll the status register don't get 505 * confused by non-existent drives. 506 */ 507 ddi_put8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_drvhd, 508 first_drvp->ad_drive_bits); 509 ata_nsecwait(400); 510 511 /* 512 * make certain the drive selected 513 */ 514 if (!ata_wait(ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2, 515 0, ATS_BSY, 5000000)) { 516 ADBG_ERROR(("ata_attach: select failed\n")); 517 } 518 519 /* 520 * initialize atapi/ata_dsk modules if we have at least 521 * one drive of that type. 522 */ 523 524 if (atapi_count) { 525 if (!atapi_attach(ata_ctlp)) 526 goto errout1; 527 ata_ctlp->ac_flags |= AC_ATAPI_INIT; 528 } 529 530 if (disk_count) { 531 if (!ata_disk_attach(ata_ctlp)) 532 goto errout1; 533 ata_ctlp->ac_flags |= AC_DISK_INIT; 534 } 535 536 /* 537 * make certain the interrupt and error latches are clear 538 */ 539 if (ata_ctlp->ac_pciide) { 540 541 int instance = ddi_get_instance(dip); 542 if (ddi_create_minor_node(dip, "control", S_IFCHR, instance, 543 DDI_PSEUDO, 0) != DDI_SUCCESS) { 544 goto errout1; 545 } 546 547 (void) ata_pciide_status_clear(ata_ctlp); 548 549 } 550 551 /* 552 * enable the interrupt handler and drop the mutex 553 */ 554 ata_ctlp->ac_flags |= AC_ATTACHED; 555 mutex_exit(&ata_ctlp->ac_ccc.ccc_hba_mutex); 556 557 ata_init_pm(dip); 558 559 ddi_report_dev(dip); 560 return (DDI_SUCCESS); 561 562 errout1: 563 mutex_exit(&ata_ctlp->ac_ccc.ccc_hba_mutex); 564 errout: 565 (void) ata_detach(dip, DDI_DETACH); 566 return (DDI_FAILURE); 567 } 568 569 /* driver detach entry point */ 570 571 static int 572 ata_detach( 573 dev_info_t *dip, 574 ddi_detach_cmd_t cmd) 575 { 576 ata_ctl_t *ata_ctlp; 577 ata_drv_t *ata_drvp; 578 int instance; 579 int i; 580 int j; 581 582 ADBG_TRACE(("ata_detach entered\n")); 583 584 switch (cmd) { 585 case DDI_DETACH: 586 break; 587 case DDI_SUSPEND: 588 return (ata_suspend(dip)); 589 default: 590 return (DDI_FAILURE); 591 } 592 593 instance = ddi_get_instance(dip); 594 ata_ctlp = ddi_get_soft_state(ata_state, instance); 595 596 if (!ata_ctlp) 597 return (DDI_SUCCESS); 598 599 if (ata_ctlp->ac_pm_support) { 600 ATA_BUSY_COMPONENT(dip, 0); 601 if (ata_ctlp->ac_pm_level != PM_LEVEL_D0) { 602 if (ATA_RAISE_POWER(dip, 0, PM_LEVEL_D0) != 603 DDI_SUCCESS) { 604 ATA_IDLE_COMPONENT(dip, 0); 605 return (DDI_FAILURE); 606 } 607 } 608 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "pm-components"); 609 } 610 ata_ctlp->ac_flags &= ~AC_ATTACHED; 611 612 /* destroy ata module */ 613 if (ata_ctlp->ac_flags & AC_DISK_INIT) 614 ata_disk_detach(ata_ctlp); 615 616 /* destroy atapi module */ 617 if (ata_ctlp->ac_flags & AC_ATAPI_INIT) 618 atapi_detach(ata_ctlp); 619 620 ddi_remove_minor_node(dip, NULL); 621 622 /* destroy drives */ 623 for (i = 0; i < ATA_MAXTARG; i++) { 624 for (j = 0; j < ATA_MAXLUN; j++) { 625 ata_drvp = CTL2DRV(ata_ctlp, i, j); 626 if (ata_drvp != NULL) 627 ata_uninit_drive(ata_drvp); 628 } 629 } 630 631 if (ata_ctlp->ac_iohandle1) 632 ddi_regs_map_free(&ata_ctlp->ac_iohandle1); 633 if (ata_ctlp->ac_iohandle2) 634 ddi_regs_map_free(&ata_ctlp->ac_iohandle2); 635 if (ata_ctlp->ac_bmhandle) 636 ddi_regs_map_free(&ata_ctlp->ac_bmhandle); 637 638 /* destroy controller */ 639 ata_destroy_controller(dip); 640 641 ddi_prop_remove_all(dip); 642 643 return (DDI_SUCCESS); 644 } 645 646 /* 647 * Nexus driver bus_ctl entry point 648 */ 649 /*ARGSUSED*/ 650 static int 651 ata_bus_ctl( 652 dev_info_t *d, 653 dev_info_t *r, 654 ddi_ctl_enum_t o, 655 void *a, 656 void *v) 657 { 658 dev_info_t *tdip; 659 int target_type; 660 int rc; 661 char *bufp; 662 663 ADBG_TRACE(("ata_bus_ctl entered\n")); 664 665 switch (o) { 666 667 case DDI_CTLOPS_SIDDEV: 668 return (DDI_FAILURE); 669 670 case DDI_CTLOPS_IOMIN: 671 672 /* 673 * Since we use PIO, we return a minimum I/O size of 674 * one byte. This will need to be updated when we 675 * implement DMA support 676 */ 677 678 *((int *)v) = 1; 679 return (DDI_SUCCESS); 680 681 case DDI_CTLOPS_DMAPMAPC: 682 case DDI_CTLOPS_REPORTINT: 683 case DDI_CTLOPS_REGSIZE: 684 case DDI_CTLOPS_NREGS: 685 case DDI_CTLOPS_SLAVEONLY: 686 case DDI_CTLOPS_AFFINITY: 687 case DDI_CTLOPS_POKE: 688 case DDI_CTLOPS_PEEK: 689 690 /* These ops shouldn't be called by a target driver */ 691 ADBG_ERROR(("ata_bus_ctl: %s%d: invalid op (%d) from %s%d\n", 692 ddi_driver_name(d), ddi_get_instance(d), o, 693 ddi_driver_name(r), ddi_get_instance(r))); 694 695 return (DDI_FAILURE); 696 697 case DDI_CTLOPS_REPORTDEV: 698 case DDI_CTLOPS_INITCHILD: 699 case DDI_CTLOPS_UNINITCHILD: 700 701 /* these require special handling below */ 702 break; 703 704 default: 705 return (ddi_ctlops(d, r, o, a, v)); 706 } 707 708 /* get targets dip */ 709 710 if (o == DDI_CTLOPS_INITCHILD || o == DDI_CTLOPS_UNINITCHILD) 711 tdip = (dev_info_t *)a; 712 else 713 tdip = r; 714 715 /* 716 * XXX - Get class of target 717 * Before the "class" entry in a conf file becomes 718 * a real property, we use an additional property 719 * tentatively called "class_prop". We will require that 720 * new classes (ie. direct) export "class_prop". 721 * SCSA target drivers will not have this property, so 722 * no property implies SCSA. 723 */ 724 if ((ddi_prop_lookup_string(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 725 "class", &bufp) == DDI_PROP_SUCCESS) || 726 (ddi_prop_lookup_string(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 727 "class_prop", &bufp) == DDI_PROP_SUCCESS)) { 728 if (strcmp(bufp, "dada") == 0) 729 target_type = ATA_DEV_DISK; 730 else if (strcmp(bufp, "scsi") == 0) 731 target_type = ATA_DEV_ATAPI; 732 else { 733 ADBG_WARN(("ata_bus_ctl: invalid target class %s\n", 734 bufp)); 735 ddi_prop_free(bufp); 736 return (DDI_FAILURE); 737 } 738 ddi_prop_free(bufp); 739 } else { 740 target_type = ATA_DEV_ATAPI; /* no class prop, assume SCSI */ 741 } 742 743 if (o == DDI_CTLOPS_INITCHILD) { 744 int instance = ddi_get_instance(d); 745 ata_ctl_t *ata_ctlp = ddi_get_soft_state(ata_state, instance); 746 ata_drv_t *ata_drvp; 747 int targ; 748 int lun; 749 int drive_type; 750 char *disk_prop; 751 char *class_prop; 752 753 if (ata_ctlp == NULL) { 754 ADBG_WARN(("ata_bus_ctl: failed to find ctl struct\n")); 755 return (DDI_FAILURE); 756 } 757 758 /* get (target,lun) of child device */ 759 760 targ = ddi_prop_get_int(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 761 "target", -1); 762 if (targ == -1) { 763 ADBG_WARN(("ata_bus_ctl: failed to get targ num\n")); 764 return (DDI_FAILURE); 765 } 766 767 lun = ddi_prop_get_int(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 768 "lun", 0); 769 770 if ((targ < 0) || (targ >= ATA_MAXTARG) || 771 (lun < 0) || (lun >= ATA_MAXLUN)) { 772 return (DDI_FAILURE); 773 } 774 775 ata_drvp = CTL2DRV(ata_ctlp, targ, lun); 776 777 if (ata_drvp == NULL) 778 return (DDI_FAILURE); /* no drive */ 779 780 /* get type of device */ 781 782 if (ATAPIDRV(ata_drvp)) 783 drive_type = ATA_DEV_ATAPI; 784 else 785 drive_type = ATA_DEV_DISK; 786 787 /* 788 * Check for special handling when child driver is 789 * cmdk (which morphs to the correct interface) 790 */ 791 if (strcmp(ddi_get_name(tdip), "cmdk") == 0) { 792 793 if ((target_type == ATA_DEV_DISK) && 794 (target_type != drive_type)) 795 return (DDI_FAILURE); 796 797 target_type = drive_type; 798 799 if (drive_type == ATA_DEV_ATAPI) { 800 class_prop = "scsi"; 801 } else { 802 disk_prop = "dadk"; 803 class_prop = "dada"; 804 805 if (ndi_prop_update_string(DDI_DEV_T_NONE, tdip, 806 "disk", disk_prop) != DDI_PROP_SUCCESS) { 807 ADBG_WARN(("ata_bus_ctl: failed to " 808 "create disk prop\n")); 809 return (DDI_FAILURE); 810 } 811 } 812 813 if (ndi_prop_update_string(DDI_DEV_T_NONE, tdip, 814 "class_prop", class_prop) != DDI_PROP_SUCCESS) { 815 ADBG_WARN(("ata_bus_ctl: failed to " 816 "create class prop\n")); 817 return (DDI_FAILURE); 818 } 819 } 820 821 /* Check that target class matches the device */ 822 823 if (target_type != drive_type) 824 return (DDI_FAILURE); 825 826 /* save pointer to drive struct for ata_disk_bus_ctl */ 827 ddi_set_driver_private(tdip, ata_drvp); 828 829 /* 830 * Determine whether to enable DMA support for this drive. This 831 * check is deferred to this point so that the various dma 832 * properties could reside on the devinfo node should finer 833 * grained dma control be required. 834 */ 835 ata_drvp->ad_pciide_dma = ata_init_drive_pcidma(ata_ctlp, 836 ata_drvp, tdip); 837 ata_show_transfer_mode(ata_ctlp, ata_drvp); 838 } 839 840 if (target_type == ATA_DEV_ATAPI) { 841 rc = scsa_bus_ops_p->bus_ctl(d, r, o, a, v); 842 } else { 843 rc = ata_disk_bus_ctl(d, r, o, a, v); 844 } 845 846 return (rc); 847 } 848 849 /* 850 * 851 * GHD ccc_hba_complete callback 852 * 853 */ 854 855 /* ARGSUSED */ 856 static void 857 ata_hba_complete( 858 void *hba_handle, 859 gcmd_t *gcmdp, 860 int do_callback) 861 { 862 ata_drv_t *ata_drvp; 863 ata_pkt_t *ata_pktp; 864 865 ADBG_TRACE(("ata_hba_complete entered\n")); 866 867 ata_drvp = GCMD2DRV(gcmdp); 868 ata_pktp = GCMD2APKT(gcmdp); 869 if (ata_pktp->ap_complete) 870 (*ata_pktp->ap_complete)(ata_drvp, ata_pktp, 871 do_callback); 872 } 873 874 /* GHD ccc_timeout_func callback */ 875 876 /* ARGSUSED */ 877 static int 878 ata_timeout_func( 879 void *hba_handle, 880 gcmd_t *gcmdp, 881 gtgt_t *gtgtp, 882 gact_t action, 883 int calltype) 884 { 885 ata_ctl_t *ata_ctlp; 886 ata_pkt_t *ata_pktp; 887 888 ADBG_TRACE(("ata_timeout_func entered\n")); 889 890 ata_ctlp = (ata_ctl_t *)hba_handle; 891 892 if (gcmdp != NULL) 893 ata_pktp = GCMD2APKT(gcmdp); 894 else 895 ata_pktp = NULL; 896 897 switch (action) { 898 case GACTION_EARLY_ABORT: 899 /* abort before request was started */ 900 if (ata_pktp != NULL) { 901 ata_pktp->ap_flags |= AP_ABORT; 902 } 903 ghd_complete(&ata_ctlp->ac_ccc, gcmdp); 904 return (TRUE); 905 906 case GACTION_EARLY_TIMEOUT: 907 /* timeout before request was started */ 908 if (ata_pktp != NULL) { 909 ata_pktp->ap_flags |= AP_TIMEOUT; 910 } 911 ghd_complete(&ata_ctlp->ac_ccc, gcmdp); 912 return (TRUE); 913 914 case GACTION_RESET_TARGET: 915 /* 916 * Reset a device is not supported. Resetting a specific 917 * device can't be done at all to an ATA device and if 918 * you send a RESET to an ATAPI device you have to 919 * reset the whole bus to make certain both devices 920 * on the bus stay in sync regarding which device is 921 * the currently selected one. 922 */ 923 return (FALSE); 924 925 case GACTION_RESET_BUS: 926 /* 927 * Issue bus reset and reinitialize both drives. 928 * But only if this is a timed-out request. Target 929 * driver reset requests are ignored because ATA 930 * and ATAPI devices shouldn't be gratuitously reset. 931 */ 932 if (gcmdp == NULL) 933 break; 934 return (ata_reset_bus(ata_ctlp)); 935 default: 936 break; 937 } 938 return (FALSE); 939 } 940 941 /* 942 * 943 * Initialize controller's soft-state structure 944 * 945 */ 946 947 static ata_ctl_t * 948 ata_init_controller( 949 dev_info_t *dip) 950 { 951 ata_ctl_t *ata_ctlp; 952 int instance; 953 caddr_t ioaddr1; 954 caddr_t ioaddr2; 955 956 ADBG_TRACE(("ata_init_controller entered\n")); 957 958 instance = ddi_get_instance(dip); 959 960 /* allocate controller structure */ 961 if (ddi_soft_state_zalloc(ata_state, instance) != DDI_SUCCESS) { 962 ADBG_WARN(("ata_init_controller: soft_state_zalloc failed\n")); 963 return (NULL); 964 } 965 966 ata_ctlp = ddi_get_soft_state(ata_state, instance); 967 968 if (ata_ctlp == NULL) { 969 ADBG_WARN(("ata_init_controller: failed to find " 970 "controller struct\n")); 971 return (NULL); 972 } 973 974 /* 975 * initialize per-controller data 976 */ 977 ata_ctlp->ac_dip = dip; 978 ata_ctlp->ac_arq_pktp = kmem_zalloc(sizeof (ata_pkt_t), KM_SLEEP); 979 980 /* 981 * map the device registers 982 */ 983 if (!ata_setup_ioaddr(dip, &ata_ctlp->ac_iohandle1, &ioaddr1, 984 &ata_ctlp->ac_iohandle2, &ioaddr2, 985 &ata_ctlp->ac_bmhandle, &ata_ctlp->ac_bmaddr)) { 986 (void) ata_detach(dip, DDI_DETACH); 987 return (NULL); 988 } 989 990 ADBG_INIT(("ata_init_controller: ioaddr1 = 0x%p, ioaddr2 = 0x%p\n", 991 ioaddr1, ioaddr2)); 992 993 /* 994 * Do ARQ setup 995 */ 996 atapi_init_arq(ata_ctlp); 997 998 /* 999 * Do PCI-IDE setup 1000 */ 1001 ata_init_pciide(dip, ata_ctlp); 1002 1003 /* 1004 * port addresses associated with ioaddr1 1005 */ 1006 ata_ctlp->ac_ioaddr1 = ioaddr1; 1007 ata_ctlp->ac_data = (ushort_t *)ioaddr1 + AT_DATA; 1008 ata_ctlp->ac_error = (uchar_t *)ioaddr1 + AT_ERROR; 1009 ata_ctlp->ac_feature = (uchar_t *)ioaddr1 + AT_FEATURE; 1010 ata_ctlp->ac_count = (uchar_t *)ioaddr1 + AT_COUNT; 1011 ata_ctlp->ac_sect = (uchar_t *)ioaddr1 + AT_SECT; 1012 ata_ctlp->ac_lcyl = (uchar_t *)ioaddr1 + AT_LCYL; 1013 ata_ctlp->ac_hcyl = (uchar_t *)ioaddr1 + AT_HCYL; 1014 ata_ctlp->ac_drvhd = (uchar_t *)ioaddr1 + AT_DRVHD; 1015 ata_ctlp->ac_status = (uchar_t *)ioaddr1 + AT_STATUS; 1016 ata_ctlp->ac_cmd = (uchar_t *)ioaddr1 + AT_CMD; 1017 1018 /* 1019 * port addresses associated with ioaddr2 1020 */ 1021 ata_ctlp->ac_ioaddr2 = ioaddr2; 1022 ata_ctlp->ac_altstatus = (uchar_t *)ioaddr2 + AT_ALTSTATUS; 1023 ata_ctlp->ac_devctl = (uchar_t *)ioaddr2 + AT_DEVCTL; 1024 1025 /* 1026 * If AC_BSY_WAIT needs to be set for laptops that do 1027 * suspend/resume but do not correctly wait for the busy bit to 1028 * drop after a resume. 1029 */ 1030 ata_ctlp->ac_timing_flags = ddi_prop_get_int(DDI_DEV_T_ANY, 1031 dip, DDI_PROP_DONTPASS, "timing_flags", 0); 1032 /* 1033 * get max transfer size, default to 256 sectors 1034 */ 1035 ata_ctlp->ac_max_transfer = ddi_prop_get_int(DDI_DEV_T_ANY, 1036 dip, DDI_PROP_DONTPASS, "max_transfer", 0x100); 1037 if (ata_ctlp->ac_max_transfer < 1) 1038 ata_ctlp->ac_max_transfer = 1; 1039 if (ata_ctlp->ac_max_transfer > 0x100) 1040 ata_ctlp->ac_max_transfer = 0x100; 1041 1042 /* 1043 * Get the standby timer value 1044 */ 1045 ata_ctlp->ac_standby_time = ddi_prop_get_int(DDI_DEV_T_ANY, 1046 dip, DDI_PROP_DONTPASS, "standby", -1); 1047 1048 /* 1049 * If this is a /pci/pci-ide instance check to see if 1050 * it's supposed to be attached as an /isa/ata 1051 */ 1052 if (ata_ctlp->ac_pciide) { 1053 static char prop_buf[] = "SUNW-ata-ffff-isa"; 1054 int addr1 = (intptr_t)ioaddr1; 1055 1056 1057 if (addr1 < 0 || addr1 > 0xffff) { 1058 (void) ata_detach(dip, DDI_DETACH); 1059 return (NULL); 1060 } 1061 (void) sprintf(prop_buf, "SUNW-ata-%04x-isa", 1062 addr1); 1063 if (ddi_prop_exists(DDI_DEV_T_ANY, ddi_root_node(), 1064 DDI_PROP_DONTPASS, prop_buf)) { 1065 (void) ata_detach(dip, DDI_DETACH); 1066 return (NULL); 1067 } 1068 } 1069 1070 /* Init controller specific stuff */ 1071 (void) ata_spec_init_controller(dip); 1072 1073 /* 1074 * initialize GHD 1075 */ 1076 1077 GHD_WAITQ_INIT(&ata_ctlp->ac_ccc.ccc_waitq, NULL, 1); 1078 1079 if (!ghd_register("ata", &ata_ctlp->ac_ccc, dip, 0, ata_ctlp, 1080 atapi_ccballoc, atapi_ccbfree, 1081 ata_pciide_dma_sg_func, ata_hba_start, 1082 ata_hba_complete, ata_intr, 1083 ata_get_status, ata_process_intr, ata_timeout_func, 1084 &ata_timer_conf, NULL)) { 1085 (void) ata_detach(dip, DDI_DETACH); 1086 return (NULL); 1087 } 1088 1089 ata_ctlp->ac_flags |= AC_GHD_INIT; 1090 return (ata_ctlp); 1091 } 1092 1093 /* destroy a controller */ 1094 1095 static void 1096 ata_destroy_controller( 1097 dev_info_t *dip) 1098 { 1099 ata_ctl_t *ata_ctlp; 1100 int instance; 1101 1102 ADBG_TRACE(("ata_destroy_controller entered\n")); 1103 1104 instance = ddi_get_instance(dip); 1105 ata_ctlp = ddi_get_soft_state(ata_state, instance); 1106 1107 if (ata_ctlp == NULL) 1108 return; 1109 1110 /* destroy ghd */ 1111 if (ata_ctlp->ac_flags & AC_GHD_INIT) 1112 ghd_unregister(&ata_ctlp->ac_ccc); 1113 1114 /* free the pciide buffer (if any) */ 1115 ata_pciide_free(ata_ctlp); 1116 1117 /* destroy controller struct */ 1118 kmem_free(ata_ctlp->ac_arq_pktp, sizeof (ata_pkt_t)); 1119 ddi_soft_state_free(ata_state, instance); 1120 1121 } 1122 1123 1124 /* 1125 * 1126 * initialize a drive 1127 * 1128 */ 1129 1130 static ata_drv_t * 1131 ata_init_drive( 1132 ata_ctl_t *ata_ctlp, 1133 uchar_t targ, 1134 uchar_t lun) 1135 { 1136 static char nec_260[] = "NEC CD-ROM DRIVE"; 1137 ata_drv_t *ata_drvp; 1138 struct ata_id *aidp; 1139 char buf[80]; 1140 int drive_type; 1141 int i; 1142 int valid_version = 0; 1143 1144 ADBG_TRACE(("ata_init_drive entered, targ = %d, lun = %d\n", 1145 targ, lun)); 1146 1147 /* check if device already exists */ 1148 1149 ata_drvp = CTL2DRV(ata_ctlp, targ, lun); 1150 1151 if (ata_drvp != NULL) 1152 return (ata_drvp); 1153 1154 /* allocate new device structure */ 1155 1156 ata_drvp = kmem_zalloc(sizeof (ata_drv_t), KM_SLEEP); 1157 aidp = &ata_drvp->ad_id; 1158 1159 /* 1160 * set up drive struct 1161 */ 1162 ata_drvp->ad_ctlp = ata_ctlp; 1163 ata_drvp->ad_targ = targ; 1164 ata_drvp->ad_drive_bits = 1165 (ata_drvp->ad_targ == 0 ? ATDH_DRIVE0 : ATDH_DRIVE1); 1166 /* 1167 * Add the LUN for SFF-8070i support 1168 */ 1169 ata_drvp->ad_lun = lun; 1170 ata_drvp->ad_drive_bits |= ata_drvp->ad_lun; 1171 1172 /* 1173 * get drive type, side effect is to collect 1174 * IDENTIFY DRIVE data 1175 */ 1176 1177 drive_type = ata_drive_type(ata_drvp->ad_drive_bits, 1178 ata_ctlp->ac_iohandle1, 1179 ata_ctlp->ac_ioaddr1, 1180 ata_ctlp->ac_iohandle2, 1181 ata_ctlp->ac_ioaddr2, 1182 aidp); 1183 1184 switch (drive_type) { 1185 case ATA_DEV_NONE: 1186 /* no drive found */ 1187 goto errout; 1188 case ATA_DEV_ATAPI: 1189 ata_drvp->ad_flags |= AD_ATAPI; 1190 break; 1191 case ATA_DEV_DISK: 1192 ata_drvp->ad_flags |= AD_DISK; 1193 break; 1194 } 1195 1196 /* 1197 * swap bytes of all text fields 1198 */ 1199 if (!ata_strncmp(nec_260, aidp->ai_model, sizeof (aidp->ai_model))) { 1200 swab(aidp->ai_drvser, aidp->ai_drvser, 1201 sizeof (aidp->ai_drvser)); 1202 swab(aidp->ai_fw, aidp->ai_fw, 1203 sizeof (aidp->ai_fw)); 1204 swab(aidp->ai_model, aidp->ai_model, 1205 sizeof (aidp->ai_model)); 1206 } 1207 1208 /* 1209 * Check if this drive has the Single Sector bug 1210 */ 1211 1212 if (ata_check_drive_blacklist(&ata_drvp->ad_id, ATA_BL_1SECTOR)) 1213 ata_drvp->ad_flags |= AD_1SECTOR; 1214 else 1215 ata_drvp->ad_flags &= ~AD_1SECTOR; 1216 1217 /* Check if this drive has the "revert to defaults" bug */ 1218 if (!ata_check_revert_to_defaults(ata_drvp)) 1219 ata_drvp->ad_flags |= AD_NORVRT; 1220 1221 /* Dump the drive info */ 1222 (void) strncpy(buf, aidp->ai_model, sizeof (aidp->ai_model)); 1223 buf[sizeof (aidp->ai_model)-1] = '\0'; 1224 for (i = sizeof (aidp->ai_model) - 2; buf[i] == ' '; i--) 1225 buf[i] = '\0'; 1226 1227 ATAPRT(("?\t%s device at targ %d, lun %d lastlun 0x%x\n", 1228 (ATAPIDRV(ata_drvp) ? "ATAPI":"IDE"), 1229 ata_drvp->ad_targ, ata_drvp->ad_lun, aidp->ai_lastlun)); 1230 1231 ATAPRT(("?\tmodel %s\n", buf)); 1232 1233 if (aidp->ai_majorversion != 0 && aidp->ai_majorversion != 0xffff) { 1234 for (i = 14; i >= 2; i--) { 1235 if (aidp->ai_majorversion & (1 << i)) { 1236 valid_version = i; 1237 break; 1238 } 1239 } 1240 ATAPRT(( 1241 "?\tATA/ATAPI-%d supported, majver 0x%x minver 0x%x\n", 1242 valid_version, 1243 aidp->ai_majorversion, 1244 aidp->ai_minorversion)); 1245 } 1246 1247 if (ata_capability_data) { 1248 1249 ATAPRT(("?\t\tstat %x, err %x\n", 1250 ddi_get8(ata_ctlp->ac_iohandle2, 1251 ata_ctlp->ac_altstatus), 1252 ddi_get8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_error))); 1253 1254 ATAPRT(("?\t\tcfg 0x%x, cap 0x%x\n", 1255 aidp->ai_config, 1256 aidp->ai_cap)); 1257 1258 /* 1259 * Be aware that ATA-6 and later drives may not provide valid 1260 * geometry information and other obsoleted info. 1261 * Select what is printed based on supported ATA model (skip 1262 * anything below ATA/ATAPI-3) 1263 */ 1264 1265 if (valid_version == 0 || aidp->ai_majorversion < 1266 ATAC_MAJVER_6) { 1267 /* 1268 * Supported version less then ATA-6 1269 */ 1270 ATAPRT(("?\t\tcyl %d, hd %d, sec/trk %d\n", 1271 aidp->ai_fixcyls, 1272 aidp->ai_heads, 1273 aidp->ai_sectors)); 1274 } 1275 ATAPRT(("?\t\tmult1 0x%x, mult2 0x%x\n", 1276 aidp->ai_mult1, 1277 aidp->ai_mult2)); 1278 if (valid_version && aidp->ai_majorversion < ATAC_MAJVER_4) { 1279 ATAPRT(( 1280 "?\t\tpiomode 0x%x, dmamode 0x%x, advpiomode 0x%x\n", 1281 aidp->ai_piomode, 1282 aidp->ai_dmamode, 1283 aidp->ai_advpiomode)); 1284 } else { 1285 ATAPRT(("?\t\tadvpiomode 0x%x\n", 1286 aidp->ai_advpiomode)); 1287 } 1288 ATAPRT(("?\t\tminpio %d, minpioflow %d\n", 1289 aidp->ai_minpio, 1290 aidp->ai_minpioflow)); 1291 if (valid_version && aidp->ai_majorversion >= ATAC_MAJVER_4 && 1292 (aidp->ai_validinfo & ATAC_VALIDINFO_83)) { 1293 ATAPRT(("?\t\tdwdma 0x%x, ultradma 0x%x\n", 1294 aidp->ai_dworddma, 1295 aidp->ai_ultradma)); 1296 } else { 1297 ATAPRT(("?\t\tdwdma 0x%x\n", 1298 aidp->ai_dworddma)); 1299 } 1300 } 1301 1302 if (ATAPIDRV(ata_drvp)) { 1303 if (!atapi_init_drive(ata_drvp)) 1304 goto errout; 1305 } else { 1306 if (!ata_disk_init_drive(ata_drvp)) 1307 goto errout; 1308 } 1309 1310 /* 1311 * store pointer in controller struct 1312 */ 1313 CTL2DRV(ata_ctlp, targ, lun) = ata_drvp; 1314 1315 /* 1316 * lock the drive's current settings in case I have to 1317 * reset the drive due to some sort of error 1318 */ 1319 (void) ata_set_feature(ata_ctlp, ata_drvp, ATSF_DIS_REVPOD, 0); 1320 1321 return (ata_drvp); 1322 1323 errout: 1324 ata_uninit_drive(ata_drvp); 1325 return (NULL); 1326 } 1327 1328 /* destroy a drive */ 1329 1330 static void 1331 ata_uninit_drive( 1332 ata_drv_t *ata_drvp) 1333 { 1334 #if 0 1335 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp; 1336 #endif 1337 1338 ADBG_TRACE(("ata_uninit_drive entered\n")); 1339 1340 #if 0 1341 /* 1342 * DON'T DO THIS. disabling interrupts floats the IRQ line 1343 * which generates spurious interrupts 1344 */ 1345 1346 /* 1347 * Select the correct drive 1348 */ 1349 ddi_put8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_drvhd, 1350 ata_drvp->ad_drive_bits); 1351 ata_nsecwait(400); 1352 1353 /* 1354 * Disable interrupts from the drive 1355 */ 1356 ddi_put8(ata_ctlp->ac_iohandle2, ata_ctlp->ac_devctl, 1357 (ATDC_D3 | ATDC_NIEN)); 1358 #endif 1359 1360 /* interface specific clean-ups */ 1361 1362 if (ata_drvp->ad_flags & AD_ATAPI) 1363 atapi_uninit_drive(ata_drvp); 1364 else if (ata_drvp->ad_flags & AD_DISK) 1365 ata_disk_uninit_drive(ata_drvp); 1366 1367 /* free drive struct */ 1368 1369 kmem_free(ata_drvp, sizeof (ata_drv_t)); 1370 } 1371 1372 1373 /* 1374 * ata_drive_type() 1375 * 1376 * The timeout values and exact sequence of checking is critical 1377 * especially for atapi device detection, and should not be changed lightly. 1378 * 1379 */ 1380 static int 1381 ata_drive_type( 1382 uchar_t drvhd, 1383 ddi_acc_handle_t io_hdl1, 1384 caddr_t ioaddr1, 1385 ddi_acc_handle_t io_hdl2, 1386 caddr_t ioaddr2, 1387 struct ata_id *ata_id_bufp) 1388 { 1389 uchar_t status; 1390 1391 ADBG_TRACE(("ata_drive_type entered\n")); 1392 1393 /* 1394 * select the appropriate drive and LUN 1395 */ 1396 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_DRVHD, drvhd); 1397 ata_nsecwait(400); 1398 1399 /* 1400 * make certain the drive is selected, and wait for not busy 1401 */ 1402 (void) ata_wait3(io_hdl2, ioaddr2, 0, ATS_BSY, 0x7f, 0, 0x7f, 0, 1403 5 * 1000000); 1404 1405 status = ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS); 1406 1407 if (status & ATS_BSY) { 1408 ADBG_TRACE(("ata_drive_type 0x%p 0x%x\n", ioaddr1, status)); 1409 return (ATA_DEV_NONE); 1410 } 1411 1412 if (ata_disk_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) 1413 return (ATA_DEV_DISK); 1414 1415 /* 1416 * No disk, check for atapi unit. 1417 */ 1418 if (!atapi_signature(io_hdl1, ioaddr1)) { 1419 #ifndef ATA_DISABLE_ATAPI_1_7 1420 /* 1421 * Check for old (but prevalent) atapi 1.7B 1422 * spec device, the only known example is the 1423 * NEC CDR-260 (not 260R which is (mostly) ATAPI 1.2 1424 * compliant). This device has no signature 1425 * and requires conversion from hex to BCD 1426 * for some scsi audio commands. 1427 */ 1428 if (atapi_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) { 1429 return (ATA_DEV_ATAPI); 1430 } 1431 #endif 1432 return (ATA_DEV_NONE); 1433 } 1434 1435 if (atapi_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) { 1436 return (ATA_DEV_ATAPI); 1437 } 1438 1439 return (ATA_DEV_NONE); 1440 1441 } 1442 1443 /* 1444 * nsec-granularity time delay function 1445 */ 1446 void 1447 ata_nsecwait(clock_t count) 1448 { 1449 extern int tsc_gethrtime_initted; 1450 1451 if (tsc_gethrtime_initted) { 1452 hrtime_t end = gethrtime() + count; 1453 1454 while (gethrtime() < end) { 1455 SMT_PAUSE(); 1456 } 1457 } else { 1458 drv_usecwait(1 + (count / 1000)); 1459 } 1460 } 1461 1462 1463 /* 1464 * Wait for a register of a controller to achieve a specific state. 1465 * To return normally, all the bits in the first sub-mask must be ON, 1466 * all the bits in the second sub-mask must be OFF. 1467 * If timeout_usec microseconds pass without the controller achieving 1468 * the desired bit configuration, we return TRUE, else FALSE. 1469 */ 1470 1471 int ata_usec_delay = 10; 1472 1473 int 1474 ata_wait( 1475 ddi_acc_handle_t io_hdl, 1476 caddr_t ioaddr, 1477 uchar_t onbits, 1478 uchar_t offbits, 1479 uint_t timeout_usec) 1480 { 1481 ushort_t val; 1482 hrtime_t deadline = gethrtime() + 1483 (hrtime_t)timeout_usec * (NANOSEC / MICROSEC); 1484 1485 1486 do { 1487 val = ddi_get8(io_hdl, (uchar_t *)ioaddr + AT_ALTSTATUS); 1488 if ((val & onbits) == onbits && (val & offbits) == 0) 1489 return (TRUE); 1490 drv_usecwait(ata_usec_delay); 1491 } while (gethrtime() < deadline); 1492 1493 return (FALSE); 1494 } 1495 1496 1497 /* 1498 * 1499 * This is a slightly more complicated version that checks 1500 * for error conditions and bails-out rather than looping 1501 * until the timeout expires 1502 */ 1503 int 1504 ata_wait3( 1505 ddi_acc_handle_t io_hdl, 1506 caddr_t ioaddr, 1507 uchar_t onbits1, 1508 uchar_t offbits1, 1509 uchar_t failure_onbits2, 1510 uchar_t failure_offbits2, 1511 uchar_t failure_onbits3, 1512 uchar_t failure_offbits3, 1513 uint_t timeout_usec) 1514 { 1515 ushort_t val; 1516 hrtime_t deadline = gethrtime() + 1517 (hrtime_t)timeout_usec * (NANOSEC / MICROSEC); 1518 1519 do { 1520 val = ddi_get8(io_hdl, (uchar_t *)ioaddr + AT_ALTSTATUS); 1521 1522 /* 1523 * check for expected condition 1524 */ 1525 if ((val & onbits1) == onbits1 && (val & offbits1) == 0) 1526 return (TRUE); 1527 1528 /* 1529 * check for error conditions 1530 */ 1531 if ((val & failure_onbits2) == failure_onbits2 && 1532 (val & failure_offbits2) == 0) { 1533 return (FALSE); 1534 } 1535 1536 if ((val & failure_onbits3) == failure_onbits3 && 1537 (val & failure_offbits3) == 0) { 1538 return (FALSE); 1539 } 1540 1541 drv_usecwait(ata_usec_delay); 1542 } while (gethrtime() < deadline); 1543 1544 return (FALSE); 1545 } 1546 1547 1548 /* 1549 * 1550 * low level routine for ata_disk_id() and atapi_id() 1551 * 1552 */ 1553 1554 int 1555 ata_id_common( 1556 uchar_t id_cmd, 1557 int expect_drdy, 1558 ddi_acc_handle_t io_hdl1, 1559 caddr_t ioaddr1, 1560 ddi_acc_handle_t io_hdl2, 1561 caddr_t ioaddr2, 1562 struct ata_id *aidp) 1563 { 1564 uchar_t status; 1565 1566 ADBG_TRACE(("ata_id_common entered\n")); 1567 1568 bzero(aidp, sizeof (struct ata_id)); 1569 1570 /* 1571 * clear the features register 1572 */ 1573 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_FEATURE, 0); 1574 1575 /* 1576 * Disable interrupts from the device. When the ata 1577 * hardware is sharing its interrupt with another 1578 * device, the shared interrupt might have already been 1579 * unmasked in the interrupt controller and 1580 * triggering ata device interrupts will result in an 1581 * interrupt storm and a hung system. 1582 */ 1583 ddi_put8(io_hdl2, (uchar_t *)ioaddr2 + AT_DEVCTL, ATDC_D3 | ATDC_NIEN); 1584 1585 /* 1586 * issue IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command 1587 */ 1588 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_CMD, id_cmd); 1589 1590 /* wait for the busy bit to settle */ 1591 ata_nsecwait(400); 1592 1593 /* 1594 * read alternate status and check for conditions which 1595 * may indicate the drive is not present, to prevent getting 1596 * stuck in ata_wait3() below. 1597 */ 1598 status = ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS); 1599 1600 /* 1601 * 0x0, 0x7f, or ATS_DF can happen when no drive is present 1602 */ 1603 if ((status == 0x0) || (status == 0x7f) || 1604 ((status & (ATS_BSY|ATS_DF)) == ATS_DF)) { 1605 /* invalid status, can't be an ATA or ATAPI device */ 1606 return (FALSE); 1607 } 1608 1609 /* 1610 * According to the ATA specification, some drives may have 1611 * to read the media to complete this command. We need to 1612 * make sure we give them enough time to respond. 1613 */ 1614 (void) ata_wait3(io_hdl2, ioaddr2, 0, ATS_BSY, 1615 ATS_ERR, ATS_BSY, 0x7f, 0, 5 * 1000000); 1616 1617 /* 1618 * read the status byte and clear the pending interrupt 1619 */ 1620 status = ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_STATUS); 1621 1622 /* 1623 * this happens if there's no drive present 1624 */ 1625 if (status == 0xff || status == 0x7f) { 1626 /* invalid status, can't be an ATA or ATAPI device */ 1627 return (FALSE); 1628 } 1629 1630 if (status & ATS_BSY) { 1631 ADBG_ERROR(("ata_id_common: BUSY status 0x%x error 0x%x\n", 1632 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 +AT_ALTSTATUS), 1633 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1634 return (FALSE); 1635 } 1636 1637 if (!(status & ATS_DRQ)) { 1638 if (status & (ATS_ERR | ATS_DF)) { 1639 return (FALSE); 1640 } 1641 /* 1642 * Give the drive another second to assert DRQ. Some older 1643 * drives de-assert BSY before asserting DRQ. 1644 */ 1645 if (!ata_wait(io_hdl2, ioaddr2, ATS_DRQ, ATS_BSY, 1000000)) { 1646 ADBG_WARN(("ata_id_common: !DRQ status 0x%x error 0x%x\n", 1647 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 +AT_ALTSTATUS), 1648 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1649 return (FALSE); 1650 } 1651 } 1652 1653 /* 1654 * transfer the data 1655 */ 1656 ddi_rep_get16(io_hdl1, (ushort_t *)aidp, (ushort_t *)ioaddr1 + AT_DATA, 1657 NBPSCTR >> 1, DDI_DEV_NO_AUTOINCR); 1658 1659 /* wait for the busy bit to settle */ 1660 ata_nsecwait(400); 1661 1662 1663 /* 1664 * Wait for the drive to recognize I've read all the data. 1665 * Some drives have been observed to take as much as 3msec to 1666 * deassert DRQ after reading the data; allow 10 msec just in case. 1667 * 1668 * Note: some non-compliant ATAPI drives (e.g., NEC Multispin 6V, 1669 * CDR-1350A) don't assert DRDY. If we've made it this far we can 1670 * safely ignore the DRDY bit since the ATAPI Packet command 1671 * actually doesn't require it to ever be asserted. 1672 * 1673 */ 1674 if (!ata_wait(io_hdl2, ioaddr2, (uchar_t)(expect_drdy ? ATS_DRDY : 0), 1675 (ATS_BSY | ATS_DRQ), 1000000)) { 1676 ADBG_WARN(("ata_id_common: bad status 0x%x error 0x%x\n", 1677 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS), 1678 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1679 return (FALSE); 1680 } 1681 1682 /* 1683 * Check to see if the command aborted. This happens if 1684 * an IDENTIFY DEVICE command is issued to an ATAPI PACKET device, 1685 * or if an IDENTIFY PACKET DEVICE command is issued to an ATA 1686 * (non-PACKET) device. 1687 */ 1688 if (status & (ATS_DF | ATS_ERR)) { 1689 ADBG_WARN(("ata_id_common: status 0x%x error 0x%x \n", 1690 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS), 1691 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1692 return (FALSE); 1693 } 1694 return (TRUE); 1695 } 1696 1697 1698 /* 1699 * Low level routine to issue a non-data command and busy wait for 1700 * the completion status. 1701 */ 1702 1703 int 1704 ata_command( 1705 ata_ctl_t *ata_ctlp, 1706 ata_drv_t *ata_drvp, 1707 int expect_drdy, 1708 int silent, 1709 uint_t busy_wait, 1710 uchar_t cmd, 1711 uchar_t feature, 1712 uchar_t count, 1713 uchar_t sector, 1714 uchar_t head, 1715 uchar_t cyl_low, 1716 uchar_t cyl_hi) 1717 { 1718 ddi_acc_handle_t io_hdl1 = ata_ctlp->ac_iohandle1; 1719 ddi_acc_handle_t io_hdl2 = ata_ctlp->ac_iohandle2; 1720 uchar_t status; 1721 1722 /* select the drive */ 1723 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, ata_drvp->ad_drive_bits); 1724 ata_nsecwait(400); 1725 1726 /* make certain the drive selected */ 1727 if (!ata_wait(io_hdl2, ata_ctlp->ac_ioaddr2, 1728 (uchar_t)(expect_drdy ? ATS_DRDY : 0), 1729 ATS_BSY, busy_wait)) { 1730 ADBG_ERROR(("ata_command: select failed " 1731 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x " 1732 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n", 1733 expect_drdy, cmd, feature, count, 1734 sector, head, cyl_low, cyl_hi)); 1735 return (FALSE); 1736 } 1737 1738 /* 1739 * set all the regs 1740 */ 1741 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, (head | ata_drvp->ad_drive_bits)); 1742 ddi_put8(io_hdl1, ata_ctlp->ac_sect, sector); 1743 ddi_put8(io_hdl1, ata_ctlp->ac_count, count); 1744 ddi_put8(io_hdl1, ata_ctlp->ac_lcyl, cyl_low); 1745 ddi_put8(io_hdl1, ata_ctlp->ac_hcyl, cyl_hi); 1746 ddi_put8(io_hdl1, ata_ctlp->ac_feature, feature); 1747 1748 /* send the command */ 1749 ddi_put8(io_hdl1, ata_ctlp->ac_cmd, cmd); 1750 1751 /* wait for the busy bit to settle */ 1752 ata_nsecwait(400); 1753 1754 /* wait for not busy */ 1755 if (!ata_wait(io_hdl2, ata_ctlp->ac_ioaddr2, 0, ATS_BSY, busy_wait)) { 1756 ADBG_ERROR(("ata_command: BSY too long!" 1757 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x " 1758 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n", 1759 expect_drdy, cmd, feature, count, 1760 sector, head, cyl_low, cyl_hi)); 1761 return (FALSE); 1762 } 1763 1764 /* 1765 * wait for DRDY before continuing 1766 */ 1767 (void) ata_wait3(io_hdl2, ata_ctlp->ac_ioaddr2, 1768 ATS_DRDY, ATS_BSY, /* okay */ 1769 ATS_ERR, ATS_BSY, /* cmd failed */ 1770 ATS_DF, ATS_BSY, /* drive failed */ 1771 busy_wait); 1772 1773 /* read status to clear IRQ, and check for error */ 1774 status = ddi_get8(io_hdl1, ata_ctlp->ac_status); 1775 1776 if ((status & (ATS_BSY | ATS_DF | ATS_ERR)) == 0) 1777 return (TRUE); 1778 1779 if (!silent) { 1780 ADBG_ERROR(("ata_command status 0x%x error 0x%x " 1781 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x " 1782 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n", 1783 ddi_get8(io_hdl1, ata_ctlp->ac_status), 1784 ddi_get8(io_hdl1, ata_ctlp->ac_error), 1785 expect_drdy, cmd, feature, count, 1786 sector, head, cyl_low, cyl_hi)); 1787 } 1788 return (FALSE); 1789 } 1790 1791 1792 1793 /* 1794 * 1795 * Issue a SET FEATURES command 1796 * 1797 */ 1798 1799 int 1800 ata_set_feature( 1801 ata_ctl_t *ata_ctlp, 1802 ata_drv_t *ata_drvp, 1803 uchar_t feature, 1804 uchar_t value) 1805 { 1806 int rc; 1807 1808 rc = ata_command(ata_ctlp, ata_drvp, TRUE, TRUE, ata_set_feature_wait, 1809 ATC_SET_FEAT, feature, value, 0, 0, 0, 0); 1810 /* feature, count, sector, head, cyl_low, cyl_hi */ 1811 1812 if (rc) { 1813 return (TRUE); 1814 } 1815 1816 ADBG_ERROR(("?ata_set_feature: (0x%x,0x%x) failed\n", feature, value)); 1817 return (FALSE); 1818 } 1819 1820 1821 1822 /* 1823 * 1824 * Issue a FLUSH CACHE command 1825 * 1826 */ 1827 1828 static int 1829 ata_flush_cache( 1830 ata_ctl_t *ata_ctlp, 1831 ata_drv_t *ata_drvp) 1832 { 1833 /* this command is optional so fail silently */ 1834 return (ata_command(ata_ctlp, ata_drvp, TRUE, TRUE, 1835 ata_flush_cache_wait, 1836 ATC_FLUSH_CACHE, 0, 0, 0, 0, 0, 0)); 1837 } 1838 1839 /* 1840 * ata_setup_ioaddr() 1841 * 1842 * Map the device registers and return the handles. 1843 * 1844 * If this is a ISA-ATA controller then only two handles are 1845 * initialized and returned. 1846 * 1847 * If this is a PCI-IDE controller than a third handle (for the 1848 * PCI-IDE Bus Mastering registers) is initialized and returned. 1849 * 1850 */ 1851 1852 static int 1853 ata_setup_ioaddr( 1854 dev_info_t *dip, 1855 ddi_acc_handle_t *handle1p, 1856 caddr_t *addr1p, 1857 ddi_acc_handle_t *handle2p, 1858 caddr_t *addr2p, 1859 ddi_acc_handle_t *bm_hdlp, 1860 caddr_t *bm_addrp) 1861 { 1862 ddi_device_acc_attr_t dev_attr; 1863 int rnumber; 1864 int rc; 1865 off_t regsize; 1866 1867 /* 1868 * Make certain the controller is enabled and its regs are map-able 1869 * 1870 */ 1871 rc = ddi_dev_regsize(dip, 0, ®size); 1872 if (rc != DDI_SUCCESS || regsize <= AT_CMD) { 1873 ADBG_INIT(("ata_setup_ioaddr(1): rc %d regsize %lld\n", 1874 rc, (long long)regsize)); 1875 return (FALSE); 1876 } 1877 1878 rc = ddi_dev_regsize(dip, 1, ®size); 1879 if (rc != DDI_SUCCESS || regsize <= AT_ALTSTATUS) { 1880 ADBG_INIT(("ata_setup_ioaddr(2): rc %d regsize %lld\n", 1881 rc, (long long)regsize)); 1882 return (FALSE); 1883 } 1884 1885 /* 1886 * setup the device attribute structure for little-endian, 1887 * strict ordering access. 1888 */ 1889 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 1890 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 1891 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1892 1893 *handle1p = NULL; 1894 *handle2p = NULL; 1895 *bm_hdlp = NULL; 1896 1897 /* 1898 * Determine whether this is a ISA, PNP-ISA, or PCI-IDE device 1899 */ 1900 if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "pnp-csn")) { 1901 /* it's PNP-ISA, skip over the extra reg tuple */ 1902 rnumber = 1; 1903 goto not_pciide; 1904 } 1905 1906 /* else, it's ISA or PCI-IDE, check further */ 1907 rnumber = 0; 1908 1909 if (!ata_is_pci(dip)) { 1910 /* 1911 * If it's not a PCI-IDE, there are only two reg tuples 1912 * and the first one contains the I/O base (170 or 1f0) 1913 * rather than the controller instance number. 1914 */ 1915 ADBG_TRACE(("ata_setup_ioaddr !pci-ide\n")); 1916 goto not_pciide; 1917 } 1918 1919 1920 /* 1921 * Map the correct half of the PCI-IDE Bus Master registers. 1922 * There's a single BAR that maps these registers for both 1923 * controller's in a dual-controller chip and it's upto my 1924 * parent nexus, pciide, to adjust which (based on my instance 1925 * number) half this call maps. 1926 */ 1927 rc = ddi_dev_regsize(dip, 2, ®size); 1928 if (rc != DDI_SUCCESS || regsize < 8) { 1929 ADBG_INIT(("ata_setup_ioaddr(3): rc %d regsize %lld\n", 1930 rc, (long long)regsize)); 1931 goto not_pciide; 1932 } 1933 1934 rc = ddi_regs_map_setup(dip, 2, bm_addrp, 0, 0, &dev_attr, bm_hdlp); 1935 1936 if (rc != DDI_SUCCESS) { 1937 /* map failed, try to use in non-pci-ide mode */ 1938 ADBG_WARN(("ata_setup_ioaddr bus master map failed, rc=0x%x\n", 1939 rc)); 1940 *bm_hdlp = NULL; 1941 } 1942 1943 not_pciide: 1944 /* 1945 * map the lower command block registers 1946 */ 1947 1948 rc = ddi_regs_map_setup(dip, rnumber, addr1p, 0, 0, &dev_attr, 1949 handle1p); 1950 1951 if (rc != DDI_SUCCESS) { 1952 cmn_err(CE_WARN, "ata: reg tuple 0 map failed, rc=0x%x\n", rc); 1953 goto out1; 1954 } 1955 1956 /* 1957 * If the controller is being used in compatibility mode 1958 * via /devices/isa/ata@1,{1f0,1f0}/..., the reg property 1959 * will specify zeros for the I/O ports for the PCI 1960 * instance. 1961 */ 1962 if (*addr1p == 0) { 1963 ADBG_TRACE(("ata_setup_ioaddr ioaddr1 0\n")); 1964 goto out2; 1965 } 1966 1967 /* 1968 * map the upper control block registers 1969 */ 1970 rc = ddi_regs_map_setup(dip, rnumber + 1, addr2p, 0, 0, &dev_attr, 1971 handle2p); 1972 if (rc == DDI_SUCCESS) 1973 return (TRUE); 1974 1975 cmn_err(CE_WARN, "ata: reg tuple 1 map failed, rc=0x%x", rc); 1976 1977 out2: 1978 if (*handle1p != NULL) { 1979 ddi_regs_map_free(handle1p); 1980 *handle1p = NULL; 1981 } 1982 1983 out1: 1984 if (*bm_hdlp != NULL) { 1985 ddi_regs_map_free(bm_hdlp); 1986 *bm_hdlp = NULL; 1987 } 1988 return (FALSE); 1989 1990 } 1991 1992 /* 1993 * 1994 * Currently, the only supported controllers are ones which 1995 * support the SFF-8038 Bus Mastering spec. 1996 * 1997 * Check the parent node's IEEE 1275 class-code property to 1998 * determine if it's an PCI-IDE instance which supports SFF-8038 1999 * Bus Mastering. It's perfectly valid to have a PCI-IDE controller 2000 * that doesn't do Bus Mastering. In that case, my interrupt handler 2001 * only uses the interrupt latch bit in PCI-IDE status register. 2002 * The assumption is that the programming interface byte of the 2003 * class-code property reflects the bus master DMA capability of 2004 * the controller. 2005 * 2006 * Whether the drive support supports the DMA option still needs 2007 * to be checked later. Each individual request also has to be 2008 * checked for alignment and size to decide whether to use the 2009 * DMA transfer mode. 2010 */ 2011 2012 static void 2013 ata_init_pciide( 2014 dev_info_t *dip, 2015 ata_ctl_t *ata_ctlp) 2016 { 2017 uint_t class_code; 2018 uchar_t status; 2019 2020 ata_cntrl_DMA_sel_msg = NULL; 2021 2022 if (ata_ctlp->ac_bmhandle == NULL) { 2023 ata_ctlp->ac_pciide = FALSE; 2024 ata_ctlp->ac_pciide_bm = FALSE; 2025 ata_cntrl_DMA_sel_msg = "cntrl not Bus Master DMA capable"; 2026 return; 2027 } 2028 2029 /* 2030 * check if it's a known bogus PCI-IDE chip 2031 */ 2032 if (ata_check_pciide_blacklist(dip, ATA_BL_BOGUS)) { 2033 ADBG_WARN(("ata_setup_ioaddr pci-ide blacklist\n")); 2034 ata_ctlp->ac_pciide = FALSE; 2035 ata_ctlp->ac_pciide_bm = FALSE; 2036 ata_cntrl_DMA_sel_msg = "cntrl blacklisted"; 2037 return; 2038 } 2039 ata_ctlp->ac_pciide = TRUE; 2040 2041 if (ata_check_pciide_blacklist(dip, ATA_BL_BMSTATREG_PIO_BROKEN)) { 2042 ata_ctlp->ac_flags |= AC_BMSTATREG_PIO_BROKEN; 2043 } 2044 2045 /* 2046 * check for a PCI-IDE chip with a broken DMA engine 2047 */ 2048 if (ata_check_pciide_blacklist(dip, ATA_BL_NODMA)) { 2049 ata_ctlp->ac_pciide_bm = FALSE; 2050 ata_cntrl_DMA_sel_msg = 2051 "cntrl blacklisted/DMA engine broken"; 2052 return; 2053 } 2054 2055 /* 2056 * Check the Programming Interface register to determine 2057 * if this device supports PCI-IDE Bus Mastering. Some PCI-IDE 2058 * devices don't support Bus Mastering or DMA. 2059 * Since we are dealing with pre-qualified pci-ide controller, 2060 * check programming interface byte only. 2061 */ 2062 2063 class_code = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 2064 DDI_PROP_DONTPASS, "class-code", 0); 2065 if ((class_code & PCIIDE_BM_CAP_MASK) != PCIIDE_BM_CAP_MASK) { 2066 ata_ctlp->ac_pciide_bm = FALSE; 2067 ata_cntrl_DMA_sel_msg = 2068 "cntrl not Bus Master DMA capable"; 2069 return; 2070 } 2071 2072 /* 2073 * Avoid doing DMA on "simplex" chips which share hardware 2074 * between channels 2075 */ 2076 status = ddi_get8(ata_ctlp->ac_bmhandle, 2077 (uchar_t *)ata_ctlp->ac_bmaddr + PCIIDE_BMISX_REG); 2078 /* 2079 * Some motherboards have CSB5's that are wired "to emulate CSB4 mode". 2080 * In such a mode, the simplex bit is asserted, but in fact testing 2081 * on such a motherboard has shown that the devices are not simplex 2082 * -- DMA can be used on both channels concurrently with no special 2083 * considerations. For chips like this, we have the ATA_BL_NO_SIMPLEX 2084 * flag set to indicate that the value of the simplex bit can be 2085 * ignored. 2086 */ 2087 2088 if (status & PCIIDE_BMISX_SIMPLEX) { 2089 if (ata_check_pciide_blacklist(dip, ATA_BL_NO_SIMPLEX)) { 2090 cmn_err(CE_WARN, "Ignoring false simplex bit \n"); 2091 2092 } else { 2093 2094 int simplex_dma_channel, *rp, proplen, channel; 2095 int dma_on = FALSE; 2096 2097 /* 2098 * By default,use DMA on channel 0 and PIO on channel 2099 * 1. This can be switched by setting 2100 * ata-simplex-dma-channel to: 2101 * 0 DMA on channel 0 (default without this 2102 * property) 2103 * 1 DMA on channel 1 2104 * any other value: DMA off on both channels. 2105 */ 2106 simplex_dma_channel = ata_prop_lookup_int(DDI_DEV_T_ANY, 2107 ata_ctlp->ac_dip, 0, "ata-simplex-dma-channel", 0); 2108 2109 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 2110 ata_ctlp->ac_dip, DDI_PROP_DONTPASS, "reg", &rp, 2111 (uint_t *)&proplen) == DDI_PROP_SUCCESS) { 2112 2113 channel = *rp; 2114 ddi_prop_free(rp); 2115 2116 if (simplex_dma_channel == channel) { 2117 cmn_err(CE_NOTE, "?ata: simplex " 2118 "controller. DMA on channel" 2119 " %d PIO on channel %d\n", 2120 channel, channel ? 0:1); 2121 dma_on = TRUE; 2122 } else { 2123 ata_cntrl_DMA_sel_msg = 2124 "simplex controller"; 2125 } 2126 } 2127 2128 if (dma_on == FALSE) { 2129 ata_ctlp->ac_pciide_bm = FALSE; 2130 2131 return; 2132 } 2133 } 2134 } 2135 2136 /* 2137 * It's a compatible PCI-IDE Bus Mastering controller, 2138 * allocate and map the DMA Scatter/Gather list (PRDE table). 2139 */ 2140 if (ata_pciide_alloc(dip, ata_ctlp)) 2141 ata_ctlp->ac_pciide_bm = TRUE; 2142 else { 2143 ata_ctlp->ac_pciide_bm = FALSE; 2144 ata_cntrl_DMA_sel_msg = "unable to init DMA S/G list"; 2145 } 2146 } 2147 2148 /* 2149 * 2150 * Determine whether to enable DMA support for this drive. 2151 * The controller and the drive both have to support DMA. 2152 * The controller's capabilities were already checked in 2153 * ata_init_pciide(), now just check the drive's capabilities. 2154 * 2155 */ 2156 2157 static int 2158 ata_init_drive_pcidma( 2159 ata_ctl_t *ata_ctlp, 2160 ata_drv_t *ata_drvp, 2161 dev_info_t *tdip) 2162 { 2163 boolean_t dma; 2164 boolean_t cd_dma; 2165 boolean_t disk_dma; 2166 boolean_t atapi_dma; 2167 int ata_options; 2168 2169 ata_dev_DMA_sel_msg = NULL; 2170 2171 if (ata_ctlp->ac_pciide_bm != TRUE) { 2172 ata_dev_DMA_sel_msg = 2173 "controller is not Bus Master capable"; 2174 2175 return (ATA_DMA_OFF); 2176 } 2177 2178 ata_options = ddi_prop_get_int(DDI_DEV_T_ANY, ata_ctlp->ac_dip, 2179 0, "ata-options", 0); 2180 2181 if (!(ata_options & ATA_OPTIONS_DMA)) { 2182 /* 2183 * Either the ata-options property was not found or 2184 * DMA is not enabled by this property 2185 */ 2186 ata_dev_DMA_sel_msg = 2187 "disabled by \"ata-options\" property"; 2188 2189 return (ATA_DMA_OFF); 2190 } 2191 2192 if (ata_check_drive_blacklist(&ata_drvp->ad_id, ATA_BL_NODMA)) { 2193 ata_dev_DMA_sel_msg = "device not DMA capable; blacklisted"; 2194 2195 return (ATA_DMA_OFF); 2196 } 2197 2198 /* 2199 * DMA mode is mandatory on ATA-3 (or newer) drives but is 2200 * optional on ATA-2 (or older) drives. 2201 * 2202 * On ATA-2 drives the ai_majorversion word will probably 2203 * be 0xffff or 0x0000, check the (now obsolete) DMA bit in 2204 * the capabilities word instead. The order of these tests 2205 * is important since an ATA-3 drive doesn't have to set 2206 * the DMA bit in the capabilities word. 2207 * 2208 */ 2209 2210 if (!((ata_drvp->ad_id.ai_majorversion & 0x8000) == 0 && 2211 ata_drvp->ad_id.ai_majorversion >= (1 << 2)) && 2212 !(ata_drvp->ad_id.ai_cap & ATAC_DMA_SUPPORT)) { 2213 ata_dev_DMA_sel_msg = "device not DMA capable"; 2214 2215 return (ATA_DMA_OFF); 2216 } 2217 2218 dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2219 0, "ata-dma-enabled", TRUE); 2220 disk_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2221 0, "ata-disk-dma-enabled", TRUE); 2222 cd_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2223 0, "atapi-cd-dma-enabled", FALSE); 2224 atapi_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2225 0, "atapi-other-dma-enabled", TRUE); 2226 2227 if (dma == FALSE) { 2228 cmn_err(CE_CONT, "?ata_init_drive_pcidma: " 2229 "DMA disabled by \"ata-dma-enabled\" property"); 2230 ata_dev_DMA_sel_msg = "disabled by prop ata-dma-enabled"; 2231 2232 return (ATA_DMA_OFF); 2233 } 2234 2235 if (IS_CDROM(ata_drvp) == TRUE) { 2236 if (cd_dma == FALSE) { 2237 ata_dev_DMA_sel_msg = 2238 "disabled. Control with \"atapi-cd-dma-enabled\"" 2239 " property"; 2240 2241 return (ATA_DMA_OFF); 2242 } 2243 2244 } else if (ATAPIDRV(ata_drvp) == FALSE) { 2245 if (disk_dma == FALSE) { 2246 ata_dev_DMA_sel_msg = 2247 "disabled by \"ata-disk-dma-enabled\" property"; 2248 2249 return (ATA_DMA_OFF); 2250 } 2251 2252 } else if (atapi_dma == FALSE) { 2253 ata_dev_DMA_sel_msg = 2254 "disabled by \"atapi-other-dma-enabled\" property"; 2255 2256 return (ATA_DMA_OFF); 2257 } 2258 2259 return (ATA_DMA_ON); 2260 } 2261 2262 2263 2264 /* 2265 * this compare routine squeezes out extra blanks and 2266 * returns TRUE if p1 matches the leftmost substring of p2 2267 */ 2268 2269 static int 2270 ata_strncmp( 2271 char *p1, 2272 char *p2, 2273 int cnt) 2274 { 2275 2276 for (;;) { 2277 /* 2278 * skip over any extra blanks in both strings 2279 */ 2280 while (*p1 != '\0' && *p1 == ' ') 2281 p1++; 2282 2283 while (cnt != 0 && *p2 == ' ') { 2284 p2++; 2285 cnt--; 2286 } 2287 2288 /* 2289 * compare the two strings 2290 */ 2291 2292 if (cnt == 0 || *p1 != *p2) 2293 break; 2294 2295 while (cnt > 0 && *p1 == *p2) { 2296 p1++; 2297 p2++; 2298 cnt--; 2299 } 2300 2301 } 2302 2303 /* return TRUE if both strings ended at same point */ 2304 return ((*p1 == '\0') ? TRUE : FALSE); 2305 } 2306 2307 /* 2308 * Per PSARC/1997/281 create variant="atapi" property (if necessary) 2309 * on the target's dev_info node. Currently, the sd target driver 2310 * is the only driver which refers to this property. 2311 * 2312 * If the flag ata_id_debug is set also create the 2313 * the "ata" or "atapi" property on the target's dev_info node 2314 * 2315 */ 2316 2317 int 2318 ata_prop_create( 2319 dev_info_t *tgt_dip, 2320 ata_drv_t *ata_drvp, 2321 char *name) 2322 { 2323 int rc; 2324 2325 ADBG_TRACE(("ata_prop_create 0x%p 0x%p %s\n", tgt_dip, ata_drvp, name)); 2326 2327 if (strcmp("atapi", name) == 0) { 2328 rc = ndi_prop_update_string(DDI_DEV_T_NONE, tgt_dip, 2329 "variant", name); 2330 if (rc != DDI_PROP_SUCCESS) 2331 return (FALSE); 2332 } 2333 2334 if (!ata_id_debug) 2335 return (TRUE); 2336 2337 rc = ndi_prop_update_byte_array(DDI_DEV_T_NONE, tgt_dip, name, 2338 (uchar_t *)&ata_drvp->ad_id, sizeof (ata_drvp->ad_id)); 2339 if (rc != DDI_PROP_SUCCESS) { 2340 ADBG_ERROR(("ata_prop_create failed, rc=%d\n", rc)); 2341 } 2342 return (TRUE); 2343 } 2344 2345 2346 /* *********************************************************************** */ 2347 /* *********************************************************************** */ 2348 /* *********************************************************************** */ 2349 2350 /* 2351 * This state machine doesn't implement the ATAPI Optional Overlap 2352 * feature. You need that feature to efficiently support ATAPI 2353 * tape drives. See the 1394-ATA Tailgate spec (D97107), Figure 24, 2354 * for an example of how to add the necessary additional NextActions 2355 * and NextStates to this FSM and the atapi_fsm, in order to support 2356 * the Overlap Feature. 2357 */ 2358 2359 2360 uchar_t ata_ctlr_fsm_NextAction[ATA_CTLR_NSTATES][ATA_CTLR_NFUNCS] = { 2361 /* --------------------- next action --------------------- | - current - */ 2362 /* start0 --- start1 ---- intr ------ fini --- reset --- */ 2363 { AC_START, AC_START, AC_NADA, AC_NADA, AC_RESET_I }, /* idle */ 2364 { AC_BUSY, AC_BUSY, AC_INTR, AC_FINI, AC_RESET_A }, /* active0 */ 2365 { AC_BUSY, AC_BUSY, AC_INTR, AC_FINI, AC_RESET_A }, /* active1 */ 2366 }; 2367 2368 uchar_t ata_ctlr_fsm_NextState[ATA_CTLR_NSTATES][ATA_CTLR_NFUNCS] = { 2369 2370 /* --------------------- next state --------------------- | - current - */ 2371 /* start0 --- start1 ---- intr ------ fini --- reset --- */ 2372 { AS_ACTIVE0, AS_ACTIVE1, AS_IDLE, AS_IDLE, AS_IDLE }, /* idle */ 2373 { AS_ACTIVE0, AS_ACTIVE0, AS_ACTIVE0, AS_IDLE, AS_ACTIVE0 }, /* active0 */ 2374 { AS_ACTIVE1, AS_ACTIVE1, AS_ACTIVE1, AS_IDLE, AS_ACTIVE1 }, /* active1 */ 2375 }; 2376 2377 2378 static int 2379 ata_ctlr_fsm( 2380 uchar_t fsm_func, 2381 ata_ctl_t *ata_ctlp, 2382 ata_drv_t *ata_drvp, 2383 ata_pkt_t *ata_pktp, 2384 int *DoneFlgp) 2385 { 2386 uchar_t action; 2387 uchar_t current_state; 2388 uchar_t next_state; 2389 int rc; 2390 2391 current_state = ata_ctlp->ac_state; 2392 action = ata_ctlr_fsm_NextAction[current_state][fsm_func]; 2393 next_state = ata_ctlr_fsm_NextState[current_state][fsm_func]; 2394 2395 /* 2396 * Set the controller's new state 2397 */ 2398 ata_ctlp->ac_state = next_state; 2399 switch (action) { 2400 2401 case AC_BUSY: 2402 return (ATA_FSM_RC_BUSY); 2403 2404 case AC_NADA: 2405 return (ATA_FSM_RC_OKAY); 2406 2407 case AC_START: 2408 ASSERT(ata_ctlp->ac_active_pktp == NULL); 2409 ASSERT(ata_ctlp->ac_active_drvp == NULL); 2410 2411 ata_ctlp->ac_active_pktp = ata_pktp; 2412 ata_ctlp->ac_active_drvp = ata_drvp; 2413 2414 rc = (*ata_pktp->ap_start)(ata_ctlp, ata_drvp, ata_pktp); 2415 2416 if (rc == ATA_FSM_RC_BUSY) { 2417 /* the request didn't start, GHD will requeue it */ 2418 ata_ctlp->ac_state = AS_IDLE; 2419 ata_ctlp->ac_active_pktp = NULL; 2420 ata_ctlp->ac_active_drvp = NULL; 2421 } 2422 return (rc); 2423 2424 case AC_INTR: 2425 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2426 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2427 2428 ata_drvp = ata_ctlp->ac_active_drvp; 2429 ata_pktp = ata_ctlp->ac_active_pktp; 2430 return ((*ata_pktp->ap_intr)(ata_ctlp, ata_drvp, ata_pktp)); 2431 2432 case AC_RESET_A: /* Reset, controller active */ 2433 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2434 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2435 2436 /* clean up the active request */ 2437 ata_pktp = ata_ctlp->ac_active_pktp; 2438 ata_pktp->ap_flags |= AP_DEV_RESET | AP_BUS_RESET; 2439 2440 /* halt the DMA engine */ 2441 if (ata_pktp->ap_pciide_dma) { 2442 ata_pciide_dma_stop(ata_ctlp); 2443 (void) ata_pciide_status_clear(ata_ctlp); 2444 } 2445 2446 /* Do a Software Reset to unwedge the bus */ 2447 if (!ata_software_reset(ata_ctlp)) { 2448 return (ATA_FSM_RC_BUSY); 2449 } 2450 2451 /* Then send a DEVICE RESET cmd to each ATAPI device */ 2452 atapi_fsm_reset(ata_ctlp); 2453 return (ATA_FSM_RC_FINI); 2454 2455 case AC_RESET_I: /* Reset, controller idle */ 2456 /* Do a Software Reset to unwedge the bus */ 2457 if (!ata_software_reset(ata_ctlp)) { 2458 return (ATA_FSM_RC_BUSY); 2459 } 2460 2461 /* Then send a DEVICE RESET cmd to each ATAPI device */ 2462 atapi_fsm_reset(ata_ctlp); 2463 return (ATA_FSM_RC_OKAY); 2464 2465 case AC_FINI: 2466 break; 2467 } 2468 2469 /* 2470 * AC_FINI, check ARQ needs to be started or finished 2471 */ 2472 2473 ASSERT(action == AC_FINI); 2474 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2475 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2476 2477 /* 2478 * The active request is done now. 2479 * Disconnect the request from the controller and 2480 * add it to the done queue. 2481 */ 2482 ata_drvp = ata_ctlp->ac_active_drvp; 2483 ata_pktp = ata_ctlp->ac_active_pktp; 2484 2485 /* 2486 * If ARQ pkt is done, get ptr to original pkt and wrap it up. 2487 */ 2488 if (ata_pktp == ata_ctlp->ac_arq_pktp) { 2489 ata_pkt_t *arq_pktp; 2490 2491 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ done\n", ata_ctlp)); 2492 2493 arq_pktp = ata_pktp; 2494 ata_pktp = ata_ctlp->ac_fault_pktp; 2495 ata_ctlp->ac_fault_pktp = NULL; 2496 if (arq_pktp->ap_flags & (AP_ERROR | AP_BUS_RESET)) 2497 ata_pktp->ap_flags |= AP_ARQ_ERROR; 2498 else 2499 ata_pktp->ap_flags |= AP_ARQ_OKAY; 2500 goto all_done; 2501 } 2502 2503 2504 #define AP_ARQ_NEEDED (AP_ARQ_ON_ERROR | AP_GOT_STATUS | AP_ERROR) 2505 2506 /* 2507 * Start ARQ pkt if necessary 2508 */ 2509 if ((ata_pktp->ap_flags & AP_ARQ_NEEDED) == AP_ARQ_NEEDED && 2510 (ata_pktp->ap_status & ATS_ERR)) { 2511 2512 /* set controller state back to active */ 2513 ata_ctlp->ac_state = current_state; 2514 2515 /* try to start the ARQ pkt */ 2516 rc = ata_start_arq(ata_ctlp, ata_drvp, ata_pktp); 2517 2518 if (rc == ATA_FSM_RC_BUSY) { 2519 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ BUSY\n", ata_ctlp)); 2520 /* let the target driver handle the problem */ 2521 ata_ctlp->ac_state = AS_IDLE; 2522 ata_ctlp->ac_active_pktp = NULL; 2523 ata_ctlp->ac_active_drvp = NULL; 2524 ata_ctlp->ac_fault_pktp = NULL; 2525 goto all_done; 2526 } 2527 2528 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ started\n", ata_ctlp)); 2529 return (rc); 2530 } 2531 2532 /* 2533 * Normal completion, no error status, and not an ARQ pkt, 2534 * just fall through. 2535 */ 2536 2537 all_done: 2538 2539 /* 2540 * wrap everything up and tie a ribbon around it 2541 */ 2542 ata_ctlp->ac_active_pktp = NULL; 2543 ata_ctlp->ac_active_drvp = NULL; 2544 if (APKT2GCMD(ata_pktp) != (gcmd_t *)0) { 2545 ghd_complete(&ata_ctlp->ac_ccc, APKT2GCMD(ata_pktp)); 2546 if (DoneFlgp) 2547 *DoneFlgp = TRUE; 2548 } 2549 2550 return (ATA_FSM_RC_OKAY); 2551 } 2552 2553 2554 static int 2555 ata_start_arq( 2556 ata_ctl_t *ata_ctlp, 2557 ata_drv_t *ata_drvp, 2558 ata_pkt_t *ata_pktp) 2559 { 2560 ata_pkt_t *arq_pktp; 2561 int bytes; 2562 uint_t senselen; 2563 2564 ADBG_ARQ(("ata_start_arq 0x%p ARQ needed\n", ata_ctlp)); 2565 2566 /* 2567 * Determine just the size of the Request Sense Data buffer within 2568 * the scsi_arq_status structure. 2569 */ 2570 #define SIZEOF_ARQ_HEADER (sizeof (struct scsi_arq_status) \ 2571 - sizeof (struct scsi_extended_sense)) 2572 senselen = ata_pktp->ap_statuslen - SIZEOF_ARQ_HEADER; 2573 ASSERT(senselen > 0); 2574 2575 2576 /* save ptr to original pkt */ 2577 ata_ctlp->ac_fault_pktp = ata_pktp; 2578 2579 /* switch the controller's active pkt to the ARQ pkt */ 2580 arq_pktp = ata_ctlp->ac_arq_pktp; 2581 ata_ctlp->ac_active_pktp = arq_pktp; 2582 2583 /* finish initializing the ARQ CDB */ 2584 ata_ctlp->ac_arq_cdb[1] = ata_drvp->ad_lun << 4; 2585 ata_ctlp->ac_arq_cdb[4] = senselen; 2586 2587 /* finish initializing the ARQ pkt */ 2588 arq_pktp->ap_v_addr = (caddr_t)&ata_pktp->ap_scbp->sts_sensedata; 2589 2590 arq_pktp->ap_resid = senselen; 2591 arq_pktp->ap_flags = AP_ATAPI | AP_READ; 2592 arq_pktp->ap_cdb_pad = 2593 ((unsigned)(ata_drvp->ad_cdb_len - arq_pktp->ap_cdb_len)) >> 1; 2594 2595 bytes = min(senselen, ATAPI_MAX_BYTES_PER_DRQ); 2596 arq_pktp->ap_hicyl = (uchar_t)(bytes >> 8); 2597 arq_pktp->ap_lwcyl = (uchar_t)bytes; 2598 2599 /* 2600 * This packet is shared by all drives on this controller 2601 * therefore we need to init the drive number on every ARQ. 2602 */ 2603 arq_pktp->ap_hd = ata_drvp->ad_drive_bits; 2604 2605 /* start it up */ 2606 return ((*arq_pktp->ap_start)(ata_ctlp, ata_drvp, arq_pktp)); 2607 } 2608 2609 /* 2610 * 2611 * reset the bus 2612 * 2613 */ 2614 2615 static int 2616 ata_reset_bus( 2617 ata_ctl_t *ata_ctlp) 2618 { 2619 int watchdog; 2620 uchar_t drive; 2621 int rc = FALSE; 2622 uchar_t fsm_func; 2623 int DoneFlg = FALSE; 2624 2625 /* 2626 * Do a Software Reset to unwedge the bus, and send 2627 * ATAPI DEVICE RESET to each ATAPI drive. 2628 */ 2629 fsm_func = ATA_FSM_RESET; 2630 for (watchdog = ata_reset_bus_watchdog; watchdog > 0; watchdog--) { 2631 switch (ata_ctlr_fsm(fsm_func, ata_ctlp, NULL, NULL, 2632 &DoneFlg)) { 2633 case ATA_FSM_RC_OKAY: 2634 rc = TRUE; 2635 goto fsm_done; 2636 2637 case ATA_FSM_RC_BUSY: 2638 return (FALSE); 2639 2640 case ATA_FSM_RC_INTR: 2641 fsm_func = ATA_FSM_INTR; 2642 rc = TRUE; 2643 continue; 2644 2645 case ATA_FSM_RC_FINI: 2646 fsm_func = ATA_FSM_FINI; 2647 rc = TRUE; 2648 continue; 2649 } 2650 } 2651 ADBG_WARN(("ata_reset_bus: watchdog\n")); 2652 2653 fsm_done: 2654 2655 /* 2656 * Reinitialize the ATA drives 2657 */ 2658 for (drive = 0; drive < ATA_MAXTARG; drive++) { 2659 ata_drv_t *ata_drvp; 2660 2661 if ((ata_drvp = CTL2DRV(ata_ctlp, drive, 0)) == NULL) 2662 continue; 2663 2664 if (ATAPIDRV(ata_drvp)) 2665 continue; 2666 2667 /* 2668 * Reprogram the Read/Write Multiple block factor 2669 * and current geometry into the drive. 2670 */ 2671 if (!ata_disk_setup_parms(ata_ctlp, ata_drvp)) 2672 rc = FALSE; 2673 } 2674 2675 /* If DoneFlg is TRUE, it means that ghd_complete() function */ 2676 /* has been already called. In this case ignore any errors and */ 2677 /* return TRUE to the caller, otherwise return the value of rc */ 2678 /* to the caller */ 2679 if (DoneFlg) 2680 return (TRUE); 2681 else 2682 return (rc); 2683 } 2684 2685 2686 /* 2687 * 2688 * Low level routine to toggle the Software Reset bit 2689 * 2690 */ 2691 2692 static int 2693 ata_software_reset( 2694 ata_ctl_t *ata_ctlp) 2695 { 2696 ddi_acc_handle_t io_hdl1 = ata_ctlp->ac_iohandle1; 2697 ddi_acc_handle_t io_hdl2 = ata_ctlp->ac_iohandle2; 2698 hrtime_t deadline; 2699 uint_t usecs_left; 2700 2701 ADBG_TRACE(("ata_reset_bus entered\n")); 2702 2703 /* disable interrupts and turn the software reset bit on */ 2704 ddi_put8(io_hdl2, ata_ctlp->ac_devctl, (ATDC_D3 | ATDC_SRST)); 2705 2706 /* why 30 milliseconds, the ATA/ATAPI-4 spec says 5 usec. */ 2707 drv_usecwait(30000); 2708 2709 /* turn the software reset bit back off */ 2710 ddi_put8(io_hdl2, ata_ctlp->ac_devctl, ATDC_D3); 2711 2712 /* 2713 * Wait for the controller to assert BUSY status. 2714 * I don't think 300 msecs is correct. The ATA/ATAPI-4 2715 * spec says 400 nsecs, (and 2 msecs if device 2716 * was in sleep mode; but we don't put drives to sleep 2717 * so it probably doesn't matter). 2718 */ 2719 drv_usecwait(300000); 2720 2721 /* 2722 * If drive 0 exists the test for completion is simple 2723 */ 2724 deadline = gethrtime() + ((hrtime_t)31 * NANOSEC); 2725 2726 if (CTL2DRV(ata_ctlp, 0, 0)) { 2727 goto wait_for_not_busy; 2728 } 2729 2730 ASSERT(CTL2DRV(ata_ctlp, 1, 0) != NULL); 2731 2732 /* 2733 * This must be a single device configuration, with drive 1 2734 * only. This complicates the test for completion because 2735 * issuing the software reset just caused drive 1 to 2736 * deselect. With drive 1 deselected, if I just read the 2737 * status register to test the BSY bit I get garbage, but 2738 * I can't re-select drive 1 until I'm certain the BSY bit 2739 * is de-asserted. Catch-22. 2740 * 2741 * In ATA/ATAPI-4, rev 15, section 9.16.2, it says to handle 2742 * this situation like this: 2743 */ 2744 2745 /* give up if the drive doesn't settle within 31 seconds */ 2746 while (gethrtime() < deadline) { 2747 /* 2748 * delay 10msec each time around the loop 2749 */ 2750 drv_usecwait(10000); 2751 2752 /* 2753 * try to select drive 1 2754 */ 2755 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, ATDH_DRIVE1); 2756 2757 ddi_put8(io_hdl1, ata_ctlp->ac_sect, 0x55); 2758 ddi_put8(io_hdl1, ata_ctlp->ac_sect, 0xaa); 2759 if (ddi_get8(io_hdl1, ata_ctlp->ac_sect) != 0xaa) 2760 continue; 2761 2762 ddi_put8(io_hdl1, ata_ctlp->ac_count, 0x55); 2763 ddi_put8(io_hdl1, ata_ctlp->ac_count, 0xaa); 2764 if (ddi_get8(io_hdl1, ata_ctlp->ac_count) != 0xaa) 2765 continue; 2766 2767 goto wait_for_not_busy; 2768 } 2769 return (FALSE); 2770 2771 wait_for_not_busy: 2772 2773 /* 2774 * Now wait up to 31 seconds for BUSY to clear. 2775 */ 2776 usecs_left = (deadline - gethrtime()) / 1000; 2777 (void) ata_wait3(io_hdl2, ata_ctlp->ac_ioaddr2, 0, ATS_BSY, 2778 ATS_ERR, ATS_BSY, ATS_DF, ATS_BSY, usecs_left); 2779 2780 return (TRUE); 2781 } 2782 2783 /* 2784 * 2785 * DDI interrupt handler 2786 * 2787 */ 2788 2789 static uint_t 2790 ata_intr( 2791 caddr_t arg) 2792 { 2793 ata_ctl_t *ata_ctlp; 2794 int one_shot = 1; 2795 2796 ata_ctlp = (ata_ctl_t *)arg; 2797 2798 return (ghd_intr(&ata_ctlp->ac_ccc, (void *)&one_shot)); 2799 } 2800 2801 2802 /* 2803 * 2804 * GHD ccc_get_status callback 2805 * 2806 */ 2807 2808 static int 2809 ata_get_status( 2810 void *hba_handle, 2811 void *intr_status) 2812 { 2813 ata_ctl_t *ata_ctlp = (ata_ctl_t *)hba_handle; 2814 uchar_t status; 2815 2816 ADBG_TRACE(("ata_get_status entered\n")); 2817 2818 /* 2819 * ignore interrupts before ata_attach completes 2820 */ 2821 if (!(ata_ctlp->ac_flags & AC_ATTACHED)) 2822 return (FALSE); 2823 2824 /* 2825 * can't be interrupt pending if nothing active 2826 */ 2827 switch (ata_ctlp->ac_state) { 2828 case AS_IDLE: 2829 return (FALSE); 2830 case AS_ACTIVE0: 2831 case AS_ACTIVE1: 2832 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2833 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2834 break; 2835 } 2836 2837 /* 2838 * If this is a PCI-IDE controller, check the PCI-IDE controller's 2839 * interrupt status latch. But don't clear it yet. 2840 * 2841 * AC_BMSTATREG_PIO_BROKEN flag is used currently for 2842 * CMD chips with device id 0x646. Since the interrupt bit on 2843 * Bus master IDE register is not usable when in PIO mode, 2844 * this chip is treated as a legacy device for interrupt 2845 * indication. The following code for CMD 2846 * chips may need to be revisited when we enable support for dma. 2847 * 2848 * CHANGE: DMA is not disabled for these devices. BM intr bit is 2849 * checked only if there was DMA used or BM intr is useable on PIO, 2850 * else treat it as before - as legacy device. 2851 */ 2852 2853 if ((ata_ctlp->ac_pciide) && 2854 ((ata_ctlp->ac_pciide_bm != FALSE) && 2855 ((ata_ctlp->ac_active_pktp->ap_pciide_dma == TRUE) || 2856 !(ata_ctlp->ac_flags & AC_BMSTATREG_PIO_BROKEN)))) { 2857 2858 if (!ata_pciide_status_pending(ata_ctlp)) 2859 return (FALSE); 2860 } else { 2861 /* 2862 * Interrupts from legacy ATA/IDE controllers are 2863 * edge-triggered but the dumb legacy ATA/IDE controllers 2864 * and drives don't have an interrupt status bit. 2865 * 2866 * Use a one_shot variable to make sure we only return 2867 * one status per interrupt. 2868 */ 2869 if (intr_status != NULL) { 2870 int *one_shot = (int *)intr_status; 2871 2872 if (*one_shot == 1) 2873 *one_shot = 0; 2874 else 2875 return (FALSE); 2876 } 2877 } 2878 2879 /* check if device is still busy */ 2880 2881 status = ddi_get8(ata_ctlp->ac_iohandle2, ata_ctlp->ac_altstatus); 2882 if (status & ATS_BSY) 2883 return (FALSE); 2884 return (TRUE); 2885 } 2886 2887 2888 /* 2889 * 2890 * get the current status and clear the IRQ 2891 * 2892 */ 2893 2894 int 2895 ata_get_status_clear_intr( 2896 ata_ctl_t *ata_ctlp, 2897 ata_pkt_t *ata_pktp) 2898 { 2899 uchar_t status; 2900 2901 /* 2902 * Here's where we clear the PCI-IDE interrupt latch. If this 2903 * request used DMA mode then we also have to check and clear 2904 * the DMA error latch at the same time. 2905 */ 2906 2907 if (ata_pktp->ap_pciide_dma) { 2908 if (ata_pciide_status_dmacheck_clear(ata_ctlp)) 2909 ata_pktp->ap_flags |= AP_ERROR | AP_TRAN_ERROR; 2910 } else if ((ata_ctlp->ac_pciide) && 2911 !(ata_ctlp->ac_flags & AC_BMSTATREG_PIO_BROKEN)) { 2912 /* 2913 * Some requests don't use DMA mode and therefore won't 2914 * set the DMA error latch, but we still have to clear 2915 * the interrupt latch. 2916 * Controllers with broken BM intr in PIO mode do not go 2917 * through this path. 2918 */ 2919 (void) ata_pciide_status_clear(ata_ctlp); 2920 } 2921 2922 /* 2923 * this clears the drive's interrupt 2924 */ 2925 status = ddi_get8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_status); 2926 ADBG_TRACE(("ata_get_status_clear_intr: 0x%x\n", status)); 2927 return (status); 2928 } 2929 2930 2931 2932 /* 2933 * 2934 * GHD interrupt handler 2935 * 2936 */ 2937 2938 /* ARGSUSED */ 2939 static void 2940 ata_process_intr( 2941 void *hba_handle, 2942 void *intr_status) 2943 { 2944 ata_ctl_t *ata_ctlp = (ata_ctl_t *)hba_handle; 2945 int watchdog; 2946 uchar_t fsm_func; 2947 int rc; 2948 2949 ADBG_TRACE(("ata_process_intr entered\n")); 2950 2951 /* 2952 * process the ATA or ATAPI interrupt 2953 */ 2954 2955 fsm_func = ATA_FSM_INTR; 2956 for (watchdog = ata_process_intr_watchdog; watchdog > 0; watchdog--) { 2957 rc = ata_ctlr_fsm(fsm_func, ata_ctlp, NULL, NULL, NULL); 2958 2959 switch (rc) { 2960 case ATA_FSM_RC_OKAY: 2961 return; 2962 2963 case ATA_FSM_RC_BUSY: /* wait for the next interrupt */ 2964 return; 2965 2966 case ATA_FSM_RC_INTR: /* re-invoke the FSM */ 2967 fsm_func = ATA_FSM_INTR; 2968 break; 2969 2970 case ATA_FSM_RC_FINI: /* move a request to done Q */ 2971 fsm_func = ATA_FSM_FINI; 2972 break; 2973 } 2974 } 2975 ADBG_WARN(("ata_process_intr: watchdog\n")); 2976 } 2977 2978 2979 2980 /* 2981 * 2982 * GHD ccc_hba_start callback 2983 * 2984 */ 2985 2986 static int 2987 ata_hba_start( 2988 void *hba_handle, 2989 gcmd_t *gcmdp) 2990 { 2991 ata_ctl_t *ata_ctlp; 2992 ata_drv_t *ata_drvp; 2993 ata_pkt_t *ata_pktp; 2994 uchar_t fsm_func; 2995 int request_started; 2996 int watchdog; 2997 2998 ADBG_TRACE(("ata_hba_start entered\n")); 2999 3000 ata_ctlp = (ata_ctl_t *)hba_handle; 3001 3002 if (ata_ctlp->ac_active_drvp != NULL) { 3003 ADBG_WARN(("ata_hba_start drvp not null\n")); 3004 return (FALSE); 3005 } 3006 if (ata_ctlp->ac_active_pktp != NULL) { 3007 ADBG_WARN(("ata_hba_start pktp not null\n")); 3008 return (FALSE); 3009 } 3010 3011 ata_pktp = GCMD2APKT(gcmdp); 3012 ata_drvp = GCMD2DRV(gcmdp); 3013 3014 /* 3015 * which drive? 3016 */ 3017 if (ata_drvp->ad_targ == 0) 3018 fsm_func = ATA_FSM_START0; 3019 else 3020 fsm_func = ATA_FSM_START1; 3021 3022 /* 3023 * start the request 3024 */ 3025 request_started = FALSE; 3026 for (watchdog = ata_hba_start_watchdog; watchdog > 0; watchdog--) { 3027 switch (ata_ctlr_fsm(fsm_func, ata_ctlp, ata_drvp, ata_pktp, 3028 NULL)) { 3029 case ATA_FSM_RC_OKAY: 3030 request_started = TRUE; 3031 goto fsm_done; 3032 3033 case ATA_FSM_RC_BUSY: 3034 /* if first time, tell GHD to requeue the request */ 3035 goto fsm_done; 3036 3037 case ATA_FSM_RC_INTR: 3038 /* 3039 * The start function polled for the next 3040 * bus phase, now fake an interrupt to process 3041 * the next action. 3042 */ 3043 request_started = TRUE; 3044 fsm_func = ATA_FSM_INTR; 3045 ata_drvp = NULL; 3046 ata_pktp = NULL; 3047 break; 3048 3049 case ATA_FSM_RC_FINI: /* move request to the done queue */ 3050 request_started = TRUE; 3051 fsm_func = ATA_FSM_FINI; 3052 ata_drvp = NULL; 3053 ata_pktp = NULL; 3054 break; 3055 } 3056 } 3057 ADBG_WARN(("ata_hba_start: watchdog\n")); 3058 3059 fsm_done: 3060 return (request_started); 3061 3062 } 3063 3064 static int 3065 ata_check_pciide_blacklist( 3066 dev_info_t *dip, 3067 uint_t flags) 3068 { 3069 ushort_t vendorid; 3070 ushort_t deviceid; 3071 pcibl_t *blp; 3072 int *propp; 3073 uint_t count; 3074 int rc; 3075 3076 3077 vendorid = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3078 DDI_PROP_DONTPASS, "vendor-id", 0); 3079 deviceid = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3080 DDI_PROP_DONTPASS, "device-id", 0); 3081 3082 /* 3083 * first check for a match in the "pci-ide-blacklist" property 3084 */ 3085 rc = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, 3086 "pci-ide-blacklist", &propp, &count); 3087 3088 if (rc == DDI_PROP_SUCCESS) { 3089 count = (count * sizeof (uint_t)) / sizeof (pcibl_t); 3090 blp = (pcibl_t *)propp; 3091 while (count--) { 3092 /* check for matching ID */ 3093 if ((vendorid & blp->b_vmask) 3094 != (blp->b_vendorid & blp->b_vmask)) { 3095 blp++; 3096 continue; 3097 } 3098 if ((deviceid & blp->b_dmask) 3099 != (blp->b_deviceid & blp->b_dmask)) { 3100 blp++; 3101 continue; 3102 } 3103 3104 /* got a match */ 3105 if (blp->b_flags & flags) { 3106 ddi_prop_free(propp); 3107 return (TRUE); 3108 } else { 3109 ddi_prop_free(propp); 3110 return (FALSE); 3111 } 3112 } 3113 ddi_prop_free(propp); 3114 } 3115 3116 /* 3117 * then check the built-in blacklist 3118 */ 3119 for (blp = ata_pciide_blacklist; blp->b_vendorid; blp++) { 3120 if ((vendorid & blp->b_vmask) != blp->b_vendorid) 3121 continue; 3122 if ((deviceid & blp->b_dmask) != blp->b_deviceid) 3123 continue; 3124 if (!(blp->b_flags & flags)) 3125 continue; 3126 return (TRUE); 3127 } 3128 return (FALSE); 3129 } 3130 3131 int 3132 ata_check_drive_blacklist( 3133 struct ata_id *aidp, 3134 uint_t flags) 3135 { 3136 atabl_t *blp; 3137 3138 for (blp = ata_drive_blacklist; blp->b_model; blp++) { 3139 if (!ata_strncmp(blp->b_model, aidp->ai_model, 3140 sizeof (aidp->ai_model))) 3141 continue; 3142 if (blp->b_flags & flags) 3143 return (TRUE); 3144 return (FALSE); 3145 } 3146 return (FALSE); 3147 } 3148 3149 /* 3150 * Queue a request to perform some sort of internally 3151 * generated command. When this request packet reaches 3152 * the front of the queue (*func)() is invoked. 3153 * 3154 */ 3155 3156 int 3157 ata_queue_cmd( 3158 int (*func)(ata_ctl_t *, ata_drv_t *, ata_pkt_t *), 3159 void *arg, 3160 ata_ctl_t *ata_ctlp, 3161 ata_drv_t *ata_drvp, 3162 gtgt_t *gtgtp) 3163 { 3164 ata_pkt_t *ata_pktp; 3165 gcmd_t *gcmdp; 3166 int rc; 3167 3168 if (!(gcmdp = ghd_gcmd_alloc(gtgtp, sizeof (*ata_pktp), TRUE))) { 3169 ADBG_ERROR(("atapi_id_update alloc failed\n")); 3170 return (FALSE); 3171 } 3172 3173 3174 /* set the back ptr from the ata_pkt to the gcmd_t */ 3175 ata_pktp = GCMD2APKT(gcmdp); 3176 ata_pktp->ap_gcmdp = gcmdp; 3177 ata_pktp->ap_hd = ata_drvp->ad_drive_bits; 3178 ata_pktp->ap_bytes_per_block = ata_drvp->ad_bytes_per_block; 3179 3180 /* 3181 * over-ride the default start function 3182 */ 3183 ata_pktp = GCMD2APKT(gcmdp); 3184 ata_pktp->ap_start = func; 3185 ata_pktp->ap_complete = NULL; 3186 ata_pktp->ap_v_addr = (caddr_t)arg; 3187 3188 /* 3189 * add it to the queue, when it gets to the front the 3190 * ap_start function is called. 3191 */ 3192 rc = ghd_transport(&ata_ctlp->ac_ccc, gcmdp, gcmdp->cmd_gtgtp, 3193 0, TRUE, NULL); 3194 3195 if (rc != TRAN_ACCEPT) { 3196 /* this should never, ever happen */ 3197 return (FALSE); 3198 } 3199 3200 if (ata_pktp->ap_flags & AP_ERROR) 3201 return (FALSE); 3202 return (TRUE); 3203 } 3204 3205 /* 3206 * Check if this drive has the "revert to defaults" bug 3207 * PSARC 2001/500 and 2001/xxx - check for the properties 3208 * ata-revert-to-defaults and atarvrt-<diskmodel> before 3209 * examining the blacklist. 3210 * <diskmodel> is made from the model number reported by Identify Drive 3211 * with uppercase letters converted to lowercase and all characters 3212 * except letters, digits, ".", "_", and "-" deleted. 3213 * Return value: 3214 * TRUE: enable revert to defaults 3215 * FALSE: disable revert to defaults 3216 * 3217 * NOTE: revert to power on defaults that includes reverting to MDMA 3218 * mode is allowed by ATA-6 & ATA-7 specs. 3219 * Therefore drives exhibiting this behaviour are not violating the spec. 3220 * Furthermore, the spec explicitly says that after the soft reset 3221 * host should check the current setting of the device features. 3222 * Correctly working BIOS would therefore reprogram either the drive 3223 * and/or the host controller to match transfer modes. 3224 * Devices with ATA_BL_NORVRT flag will be removed from 3225 * the ata_blacklist. 3226 * The default behaviour will be - no revert to power-on defaults 3227 * for all devices. The property is retained in case the user 3228 * explicitly requests revert-to-defaults before reboot. 3229 */ 3230 3231 #define ATA_REVERT_PROP_PREFIX "revert-" 3232 #define ATA_REVERT_PROP_GLOBAL "ata-revert-to-defaults" 3233 /* room for prefix + model number + terminating NUL character */ 3234 #define PROP_BUF_SIZE (sizeof (ATA_REVERT_PROP_PREFIX) + \ 3235 sizeof (aidp->ai_model) + 1) 3236 #define PROP_LEN_MAX (31) 3237 3238 static int 3239 ata_check_revert_to_defaults( 3240 ata_drv_t *ata_drvp) 3241 { 3242 struct ata_id *aidp = &ata_drvp->ad_id; 3243 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp; 3244 char prop_buf[PROP_BUF_SIZE]; 3245 int i, j; 3246 int propval; 3247 3248 /* put prefix into the buffer */ 3249 (void) strcpy(prop_buf, ATA_REVERT_PROP_PREFIX); 3250 j = strlen(prop_buf); 3251 3252 /* append the model number, leaving out invalid characters */ 3253 for (i = 0; i < sizeof (aidp->ai_model); ++i) { 3254 char c = aidp->ai_model[i]; 3255 if (c >= 'A' && c <= 'Z') /* uppercase -> lower */ 3256 c = c - 'A' + 'a'; 3257 if (c >= 'a' && c <= 'z' || c >= '0' && c <= '9' || 3258 c == '.' || c == '_' || c == '-') 3259 prop_buf[j++] = c; 3260 if (c == '\0') 3261 break; 3262 } 3263 3264 /* make sure there's a terminating NUL character */ 3265 if (j >= PROP_LEN_MAX) 3266 j = PROP_LEN_MAX; 3267 prop_buf[j] = '\0'; 3268 3269 /* look for a disk-specific "revert" property" */ 3270 propval = ddi_getprop(DDI_DEV_T_ANY, ata_ctlp->ac_dip, 3271 DDI_PROP_DONTPASS, prop_buf, -1); 3272 if (propval == 0) 3273 return (FALSE); 3274 else if (propval != -1) 3275 return (TRUE); 3276 3277 /* look for a global "revert" property" */ 3278 propval = ddi_getprop(DDI_DEV_T_ANY, ata_ctlp->ac_dip, 3279 0, ATA_REVERT_PROP_GLOBAL, -1); 3280 if (propval == 0) 3281 return (FALSE); 3282 else if (propval != -1) 3283 return (TRUE); 3284 3285 return (FALSE); 3286 } 3287 3288 void 3289 ata_show_transfer_mode(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp) 3290 { 3291 int i; 3292 3293 if (ata_ctlp->ac_pciide_bm == FALSE || 3294 ata_drvp->ad_pciide_dma != ATA_DMA_ON) { 3295 if (ata_cntrl_DMA_sel_msg) { 3296 ATAPRT(( 3297 "?\tATA DMA off: %s\n", ata_cntrl_DMA_sel_msg)); 3298 } else if (ata_dev_DMA_sel_msg) { 3299 ATAPRT(("?\tATA DMA off: %s\n", ata_dev_DMA_sel_msg)); 3300 } 3301 ATAPRT(("?\tPIO mode %d selected\n", 3302 (ata_drvp->ad_id.ai_advpiomode & ATAC_ADVPIO_4_SUP) == 3303 ATAC_ADVPIO_4_SUP ? 4 : 3)); 3304 } else { 3305 /* Using DMA */ 3306 if (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_SEL_MASK) { 3307 /* 3308 * Rely on the fact that either dwdma or udma is 3309 * selected, not both. 3310 */ 3311 ATAPRT(("?\tMultiwordDMA mode %d selected\n", 3312 (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_2_SEL) == 3313 ATAC_MDMA_2_SEL ? 2 : 3314 (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_1_SEL) == 3315 ATAC_MDMA_1_SEL ? 1 : 0)); 3316 } else { 3317 for (i = 0; i <= 6; i++) { 3318 if (ata_drvp->ad_id.ai_ultradma & 3319 (1 << (i + 8))) { 3320 ATAPRT(( 3321 "?\tUltraDMA mode %d selected\n", 3322 i)); 3323 break; 3324 } 3325 } 3326 } 3327 } 3328 } 3329 3330 /* 3331 * Controller-specific operation pointers. 3332 * Should be extended as needed - init only for now 3333 */ 3334 struct ata_ctl_spec_ops { 3335 uint_t (*cs_init)(dev_info_t *, ushort_t, ushort_t); /* ctlr init */ 3336 }; 3337 3338 3339 struct ata_ctl_spec { 3340 ushort_t cs_vendor_id; 3341 ushort_t cs_device_id; 3342 struct ata_ctl_spec_ops *cs_ops; 3343 }; 3344 3345 /* Sil3XXX-specific functions (init only for now) */ 3346 struct ata_ctl_spec_ops sil3xxx_ops = { 3347 &sil3xxx_init_controller /* Sil3XXX cntrl initialization */ 3348 }; 3349 3350 3351 struct ata_ctl_spec ata_cntrls_spec[] = { 3352 {0x1095, 0x3114, &sil3xxx_ops}, 3353 {0x1095, 0x3512, &sil3xxx_ops}, 3354 {0x1095, 0x3112, &sil3xxx_ops}, 3355 {0, 0, NULL} /* List must end with cs_ops set to NULL */ 3356 }; 3357 3358 /* 3359 * Do controller specific initialization if necessary. 3360 * Pick-up controller specific functions. 3361 */ 3362 3363 int 3364 ata_spec_init_controller(dev_info_t *dip) 3365 { 3366 ushort_t vendor_id; 3367 ushort_t device_id; 3368 struct ata_ctl_spec *ctlsp; 3369 3370 vendor_id = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3371 DDI_PROP_DONTPASS, "vendor-id", 0); 3372 device_id = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3373 DDI_PROP_DONTPASS, "device-id", 0); 3374 3375 /* Locate controller specific ops, if they exist */ 3376 ctlsp = ata_cntrls_spec; 3377 while (ctlsp->cs_ops != NULL) { 3378 if (ctlsp->cs_vendor_id == vendor_id && 3379 ctlsp->cs_device_id == device_id) 3380 break; 3381 ctlsp++; 3382 } 3383 3384 if (ctlsp->cs_ops != NULL) { 3385 if (ctlsp->cs_ops->cs_init != NULL) { 3386 /* Initialize controller */ 3387 if ((*(ctlsp->cs_ops->cs_init)) 3388 (dip, vendor_id, device_id) != TRUE) { 3389 cmn_err(CE_WARN, 3390 "pci%4x,%4x cntrl specific " 3391 "initialization failed", 3392 vendor_id, device_id); 3393 return (FALSE); 3394 } 3395 } 3396 } 3397 return (TRUE); 3398 } 3399 3400 /* 3401 * this routine works like ddi_prop_get_int, except that it works on 3402 * a string property that contains ascii representations 3403 * of an integer. 3404 * If the property is not found, the default value is returned. 3405 */ 3406 static int 3407 ata_prop_lookup_int(dev_t match_dev, dev_info_t *dip, 3408 uint_t flags, char *name, int defvalue) 3409 { 3410 3411 char *bufp, *cp; 3412 int rc = defvalue; 3413 int proprc; 3414 3415 proprc = ddi_prop_lookup_string(match_dev, dip, 3416 flags, name, &bufp); 3417 3418 if (proprc == DDI_PROP_SUCCESS) { 3419 cp = bufp; 3420 rc = stoi(&cp); 3421 ddi_prop_free(bufp); 3422 } else { 3423 /* 3424 * see if property is encoded as an int instead of string. 3425 */ 3426 rc = ddi_prop_get_int(match_dev, dip, flags, name, defvalue); 3427 } 3428 3429 return (rc); 3430 } 3431 3432 /* 3433 * Initialize the power management components 3434 */ 3435 static void 3436 ata_init_pm(dev_info_t *dip) 3437 { 3438 char pmc_name[16]; 3439 char *pmc[] = { 3440 NULL, 3441 "0=Sleep (PCI D3 State)", 3442 "3=PowerOn (PCI D0 State)", 3443 NULL 3444 }; 3445 int instance; 3446 ata_ctl_t *ata_ctlp; 3447 3448 3449 instance = ddi_get_instance(dip); 3450 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3451 ata_ctlp->ac_pm_support = 0; 3452 3453 /* check PCI capabilities */ 3454 if (!ata_is_pci(dip)) 3455 return; 3456 3457 (void) sprintf(pmc_name, "NAME=ata%d", instance); 3458 pmc[0] = pmc_name; 3459 3460 #ifdef ATA_USE_AUTOPM 3461 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, dip, 3462 "pm-components", pmc, 3) != DDI_PROP_SUCCESS) { 3463 return; 3464 } 3465 #endif 3466 3467 ata_ctlp->ac_pm_support = 1; 3468 ata_ctlp->ac_pm_level = PM_LEVEL_D0; 3469 3470 ATA_BUSY_COMPONENT(dip, 0); 3471 if (ATA_RAISE_POWER(dip, 0, PM_LEVEL_D0) != DDI_SUCCESS) { 3472 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "pm-components"); 3473 } 3474 ATA_IDLE_COMPONENT(dip, 0); 3475 } 3476 3477 /* 3478 * resume the hard drive 3479 */ 3480 static void 3481 ata_resume_drive(ata_drv_t *ata_drvp) 3482 { 3483 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp; 3484 int drive_type; 3485 struct ata_id id; 3486 uint8_t udma; 3487 3488 ADBG_TRACE(("ata_resume_drive entered\n")); 3489 3490 drive_type = ata_drive_type(ata_drvp->ad_drive_bits, 3491 ata_ctlp->ac_iohandle1, ata_ctlp->ac_ioaddr1, 3492 ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2, 3493 &id); 3494 if (drive_type == ATA_DEV_NONE) 3495 return; 3496 3497 /* Reset Ultra DMA mode */ 3498 udma = ATACM_UDMA_SEL(&ata_drvp->ad_id); 3499 if (udma != 0) { 3500 uint8_t mode; 3501 for (mode = 0; mode < 8; mode++) 3502 if (((1 << mode) & udma) != 0) 3503 break; 3504 ASSERT(mode != 8); 3505 3506 mode |= ATF_XFRMOD_UDMA; 3507 3508 if (!ata_set_feature(ata_ctlp, ata_drvp, ATSF_SET_XFRMOD, mode)) 3509 return; 3510 } 3511 3512 if (!ATAPIDRV(ata_drvp)) { 3513 if (!ata_disk_setup_parms(ata_ctlp, ata_drvp)) 3514 return; 3515 (void) ata_set_feature(ata_ctlp, ata_drvp, ATSF_DIS_REVPOD, 0); 3516 } 3517 } 3518 3519 /* 3520 * resume routine, it will be run when get the command 3521 * DDI_RESUME at attach(9E) from system power management 3522 */ 3523 static int 3524 ata_resume(dev_info_t *dip) 3525 { 3526 int instance; 3527 ata_ctl_t *ata_ctlp; 3528 ddi_acc_handle_t io_hdl2; 3529 caddr_t ioaddr2; 3530 3531 instance = ddi_get_instance(dip); 3532 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3533 3534 if (!ata_ctlp->ac_pm_support) 3535 return (DDI_FAILURE); 3536 if (ata_ctlp->ac_pm_level == PM_LEVEL_D0) 3537 return (DDI_SUCCESS); 3538 3539 ATA_BUSY_COMPONENT(dip, 0); 3540 if (ATA_RAISE_POWER(dip, 0, PM_LEVEL_D0) == DDI_FAILURE) 3541 return (DDI_FAILURE); 3542 ATA_IDLE_COMPONENT(dip, 0); 3543 3544 /* enable interrupts from the device */ 3545 io_hdl2 = ata_ctlp->ac_iohandle2; 3546 ioaddr2 = ata_ctlp->ac_ioaddr2; 3547 ddi_put8(io_hdl2, (uchar_t *)ioaddr2 + AT_DEVCTL, ATDC_D3); 3548 ata_ctlp->ac_pm_level = PM_LEVEL_D0; 3549 3550 return (DDI_SUCCESS); 3551 } 3552 3553 /* 3554 * suspend routine, it will be run when get the command 3555 * DDI_SUSPEND at detach(9E) from system power management 3556 */ 3557 static int 3558 ata_suspend(dev_info_t *dip) 3559 { 3560 int instance; 3561 ata_ctl_t *ata_ctlp; 3562 ddi_acc_handle_t io_hdl2; 3563 3564 instance = ddi_get_instance(dip); 3565 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3566 3567 if (!ata_ctlp->ac_pm_support) 3568 return (DDI_FAILURE); 3569 if (ata_ctlp->ac_pm_level == PM_LEVEL_D3) 3570 return (DDI_SUCCESS); 3571 3572 /* disable interrupts and turn the software reset bit on */ 3573 io_hdl2 = ata_ctlp->ac_iohandle2; 3574 ddi_put8(io_hdl2, ata_ctlp->ac_devctl, (ATDC_D3 | ATDC_SRST)); 3575 3576 (void) ata_reset_bus(ata_ctlp); 3577 (void) ata_change_power(dip, ATC_SLEEP); 3578 ata_ctlp->ac_pm_level = PM_LEVEL_D3; 3579 return (DDI_SUCCESS); 3580 } 3581 3582 int ata_save_pci_config = 0; 3583 /* 3584 * ata specific power management entry point, it was 3585 * used to change the power management component 3586 */ 3587 static int 3588 ata_power(dev_info_t *dip, int component, int level) 3589 { 3590 int instance; 3591 ata_ctl_t *ata_ctlp; 3592 uint8_t cmd; 3593 3594 ADBG_TRACE(("ata_power entered, component = %d, level = %d\n", 3595 component, level)); 3596 3597 instance = ddi_get_instance(dip); 3598 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3599 if (ata_ctlp == NULL || component != 0) 3600 return (DDI_FAILURE); 3601 3602 if (!ata_ctlp->ac_pm_support) 3603 return (DDI_FAILURE); 3604 3605 switch (level) { 3606 case PM_LEVEL_D0: 3607 if (ata_save_pci_config) 3608 (void) pci_restore_config_regs(dip); 3609 ata_ctlp->ac_pm_level = PM_LEVEL_D0; 3610 cmd = ATC_STANDBY_IM; 3611 break; 3612 case PM_LEVEL_D3: 3613 if (ata_save_pci_config) 3614 (void) pci_save_config_regs(dip); 3615 ata_ctlp->ac_pm_level = PM_LEVEL_D3; 3616 cmd = ATC_SLEEP; 3617 break; 3618 default: 3619 return (DDI_FAILURE); 3620 } 3621 return (ata_change_power(dip, cmd)); 3622 } 3623 3624 /* 3625 * sent commands to ata controller to change the power level 3626 */ 3627 static int 3628 ata_change_power(dev_info_t *dip, uint8_t cmd) 3629 { 3630 int instance; 3631 ata_ctl_t *ata_ctlp; 3632 ata_drv_t *ata_drvp; 3633 uchar_t targ; 3634 struct ata_id id; 3635 uchar_t lun; 3636 uchar_t lastlun; 3637 3638 ADBG_TRACE(("ata_change_power entered, cmd = %d\n", cmd)); 3639 3640 instance = ddi_get_instance(dip); 3641 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3642 /* 3643 * Issue command on each disk device on the bus. 3644 */ 3645 for (targ = 0; targ < ATA_MAXTARG; targ++) { 3646 ata_drvp = CTL2DRV(ata_ctlp, targ, 0); 3647 if (ata_drvp == NULL) 3648 continue; 3649 if (ata_drive_type(ata_drvp->ad_drive_bits, 3650 ata_ctlp->ac_iohandle1, ata_ctlp->ac_ioaddr1, 3651 ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2, 3652 &id) != ATA_DEV_DISK) 3653 continue; 3654 (void) ata_flush_cache(ata_ctlp, ata_drvp); 3655 if (!ata_command(ata_ctlp, ata_drvp, TRUE, TRUE, 5 * 1000000, 3656 cmd, 0, 0, 0, 0, 0, 0)) { 3657 cmn_err(CE_WARN, "!ata_controller - Can not put " 3658 "drive %d in to power mode %u", targ, cmd); 3659 (void) ata_devo_reset(dip, DDI_RESET_FORCE); 3660 return (DDI_FAILURE); 3661 } 3662 } 3663 3664 if (cmd == ATC_SLEEP) 3665 return (DDI_SUCCESS); 3666 3667 for (targ = 0; targ < ATA_MAXTARG; targ++) { 3668 ata_drvp = CTL2DRV(ata_ctlp, targ, 0); 3669 if ((ata_drvp == NULL) || !(ata_drvp->ad_flags & AD_DISK)) 3670 continue; 3671 ata_resume_drive(ata_drvp); 3672 3673 if (ATAPIDRV(ata_drvp)) 3674 lastlun = ata_drvp->ad_id.ai_lastlun; 3675 else 3676 lastlun = 0; 3677 if (!ata_enable_atapi_luns) 3678 lastlun = 0; 3679 for (lun = 1; lun <= lastlun && lun < ATA_MAXLUN; lun++) { 3680 ata_drvp = CTL2DRV(ata_ctlp, targ, lun); 3681 if (ata_drvp != NULL) 3682 ata_resume_drive(ata_drvp); 3683 } 3684 (void) ata_software_reset(ata_ctlp); 3685 } 3686 3687 return (DDI_SUCCESS); 3688 } 3689 3690 /* 3691 * return 1 when ata controller is a pci device, 3692 * otherwise return 0 3693 */ 3694 static int 3695 ata_is_pci(dev_info_t *dip) 3696 { 3697 int rc; 3698 char *bufp; 3699 int ispci; 3700 3701 rc = ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_get_parent(dip), 3702 DDI_PROP_DONTPASS, "device_type", &bufp); 3703 3704 if (rc != DDI_PROP_SUCCESS) { 3705 ADBG_ERROR(("ata_is_pci !device_type\n")); 3706 return (0); 3707 } 3708 3709 ispci = (strcmp(bufp, "pci-ide") == 0); 3710 3711 ddi_prop_free(bufp); 3712 3713 return (ispci); 3714 } 3715