1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #include <sys/types.h> 28 #include <sys/modctl.h> 29 #include <sys/debug.h> 30 #include <sys/promif.h> 31 #include <sys/pci.h> 32 #include <sys/errno.h> 33 #include <sys/open.h> 34 #include <sys/uio.h> 35 #include <sys/cred.h> 36 #include <sys/cpu.h> 37 #include "ata_common.h" 38 #include "ata_disk.h" 39 #include "atapi.h" 40 #include "ata_blacklist.h" 41 #include "sil3xxx.h" 42 43 /* 44 * Solaris Entry Points. 45 */ 46 47 static int ata_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 48 static int ata_detach(dev_info_t *dip, ddi_detach_cmd_t cmd); 49 static int ata_bus_ctl(dev_info_t *d, dev_info_t *r, ddi_ctl_enum_t o, 50 void *a, void *v); 51 static uint_t ata_intr(caddr_t arg); 52 53 /* 54 * GHD Entry points 55 */ 56 57 static int ata_get_status(void *hba_handle, void *intr_status); 58 static void ata_process_intr(void *hba_handle, void *intr_status); 59 static int ata_hba_start(void *handle, gcmd_t *gcmdp); 60 static void ata_hba_complete(void *handle, gcmd_t *gcmdp, int do_callback); 61 static int ata_timeout_func(void *hba_handle, gcmd_t *gcmdp, 62 gtgt_t *gtgtp, gact_t action, int calltype); 63 64 /* 65 * Local Function Prototypes 66 */ 67 static int ata_prop_lookup_int(dev_t match_dev, dev_info_t *dip, 68 uint_t flags, char *name, int defvalue); 69 static int ata_ctlr_fsm(uchar_t fsm_func, ata_ctl_t *ata_ctlp, 70 ata_drv_t *ata_drvp, ata_pkt_t *ata_pktp, 71 int *DoneFlgp); 72 static void ata_destroy_controller(dev_info_t *dip); 73 static int ata_drive_type(uchar_t drvhd, 74 ddi_acc_handle_t io_hdl1, caddr_t ioaddr1, 75 ddi_acc_handle_t io_hdl2, caddr_t ioaddr2, 76 struct ata_id *ata_id_bufp); 77 static ata_ctl_t *ata_init_controller(dev_info_t *dip); 78 static ata_drv_t *ata_init_drive(ata_ctl_t *ata_ctlp, 79 uchar_t targ, uchar_t lun); 80 static int ata_init_drive_pcidma(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 81 dev_info_t *tdip); 82 static int ata_flush_cache(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp); 83 static void ata_init_pciide(dev_info_t *dip, ata_ctl_t *ata_ctlp); 84 static int ata_reset_bus(ata_ctl_t *ata_ctlp); 85 static int ata_setup_ioaddr(dev_info_t *dip, 86 ddi_acc_handle_t *iohandle1, caddr_t *ioaddr1p, 87 ddi_acc_handle_t *iohandle2, caddr_t *ioaddr2p, 88 ddi_acc_handle_t *bm_hdlp, caddr_t *bm_addrp); 89 static int ata_software_reset(ata_ctl_t *ata_ctlp); 90 static int ata_start_arq(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 91 ata_pkt_t *ata_pktp); 92 static int ata_strncmp(char *p1, char *p2, int cnt); 93 static void ata_uninit_drive(ata_drv_t *ata_drvp); 94 95 static int ata_check_pciide_blacklist(dev_info_t *dip, uint_t flags); 96 static int ata_check_revert_to_defaults(ata_drv_t *ata_drvp); 97 static void ata_show_transfer_mode(ata_ctl_t *, ata_drv_t *); 98 static int ata_spec_init_controller(dev_info_t *dip); 99 100 static void ata_init_pm(dev_info_t *); 101 static int ata_suspend(dev_info_t *); 102 static int ata_resume(dev_info_t *); 103 static int ata_power(dev_info_t *, int, int); 104 static int ata_change_power(dev_info_t *, uint8_t); 105 static int ata_is_pci(dev_info_t *); 106 static void ata_disable_DMA(ata_drv_t *ata_drvp); 107 108 /* 109 * Local static data 110 */ 111 static void *ata_state; 112 113 static tmr_t ata_timer_conf; /* single timeout list for all instances */ 114 static int ata_watchdog_usec = 100000; /* check timeouts every 100 ms */ 115 116 int ata_hba_start_watchdog = 1000; 117 int ata_process_intr_watchdog = 1000; 118 int ata_reset_bus_watchdog = 1000; 119 120 121 /* 122 * Use local or framework power management 123 */ 124 125 #ifdef ATA_USE_AUTOPM 126 #define ATA_BUSY_COMPONENT(d, c) ((void)pm_busy_component(d, c)) 127 #define ATA_IDLE_COMPONENT(d, c) ((void)pm_idle_component(d, c)) 128 #define ATA_RAISE_POWER(d, c, l) pm_raise_power(d, c, l) 129 #define ATA_LOWER_POWER(d, c, l) pm_lower_power(d, c, l) 130 #else 131 #define ATA_BUSY_COMPONENT(d, c) 132 #define ATA_IDLE_COMPONENT(d, c) 133 #define ATA_RAISE_POWER(d, c, l) ata_power(d, c, l) 134 #define ATA_LOWER_POWER(d, c, l) ata_power(d, c, l) 135 #endif 136 /* 137 * number of seconds to wait during various operations 138 */ 139 int ata_flush_delay = 5 * 1000000; 140 uint_t ata_set_feature_wait = 4 * 1000000; 141 uint_t ata_flush_cache_wait = 60 * 1000000; /* may take a long time */ 142 143 /* 144 * Change this for SFF-8070i support. Currently SFF-8070i is 145 * using a field in the IDENTIFY PACKET DEVICE response which 146 * already seems to be in use by some vendor's drives. I suspect 147 * SFF will either move their laslun field or provide a reliable 148 * way to validate it. 149 */ 150 int ata_enable_atapi_luns = FALSE; 151 152 /* 153 * set this to disable all DMA requests 154 */ 155 int ata_dma_disabled = FALSE; 156 157 /* 158 * set this to TRUE to enable storing the IDENTIFY DEVICE result in the 159 * "ata" or "atapi" property. 160 */ 161 int ata_id_debug = FALSE; 162 163 /* 164 * set this to TRUE to enable logging device-capability data 165 */ 166 int ata_capability_data = FALSE; 167 168 /* 169 * DMA selection message pointers 170 */ 171 char *ata_cntrl_DMA_sel_msg; 172 char *ata_dev_DMA_sel_msg; 173 174 /* 175 * bus nexus operations 176 */ 177 static struct bus_ops ata_bus_ops; 178 static struct bus_ops *scsa_bus_ops_p; 179 180 /* ARGSUSED */ 181 static int 182 ata_open(dev_t *devp, int flag, int otyp, cred_t *cred_p) 183 { 184 if (ddi_get_soft_state(ata_state, getminor(*devp)) == NULL) 185 return (ENXIO); 186 187 return (0); 188 } 189 190 /* 191 * The purpose of this function is to pass the ioaddress of the controller 192 * to the caller, specifically used for upgrade from pre-pciide 193 * to pciide nodes 194 */ 195 /* ARGSUSED */ 196 static int 197 ata_read(dev_t dev, struct uio *uio_p, cred_t *cred_p) 198 { 199 ata_ctl_t *ata_ctlp; 200 char buf[18]; 201 long len; 202 203 ata_ctlp = ddi_get_soft_state(ata_state, getminor(dev)); 204 205 if (ata_ctlp == NULL) 206 return (ENXIO); 207 208 (void) sprintf(buf, "%p\n", (void *) ata_ctlp->ac_ioaddr1); 209 210 len = strlen(buf) - uio_p->uio_offset; 211 len = min(uio_p->uio_resid, len); 212 if (len <= 0) 213 return (0); 214 215 return (uiomove((caddr_t)(buf + uio_p->uio_offset), len, 216 UIO_READ, uio_p)); 217 } 218 219 int 220 ata_devo_reset( 221 dev_info_t *dip, 222 ddi_reset_cmd_t cmd) 223 { 224 ata_ctl_t *ata_ctlp; 225 ata_drv_t *ata_drvp; 226 int instance; 227 int i; 228 int rc; 229 int flush_okay; 230 231 if (cmd != DDI_RESET_FORCE) 232 return (0); 233 234 instance = ddi_get_instance(dip); 235 ata_ctlp = ddi_get_soft_state(ata_state, instance); 236 237 if (!ata_ctlp) 238 return (0); 239 240 /* 241 * reset ATA drives and flush the write cache of any drives 242 */ 243 flush_okay = TRUE; 244 for (i = 0; i < ATA_MAXTARG; i++) { 245 if ((ata_drvp = CTL2DRV(ata_ctlp, i, 0)) == 0) 246 continue; 247 /* Don't revert to defaults for certain IBM drives */ 248 if ((ata_drvp->ad_flags & AD_DISK) != 0 && 249 ((ata_drvp->ad_flags & AD_NORVRT) == 0)) { 250 /* Enable revert to defaults when reset */ 251 (void) ata_set_feature(ata_ctlp, ata_drvp, 252 ATSF_ENA_REVPOD, 0); 253 } 254 255 /* 256 * skip flush cache if device type is cdrom 257 * 258 * notes: the structure definitions for ata_drvp->ad_id are 259 * defined for the ATA IDENTIFY_DEVICE, but if AD_ATAPI is set 260 * the struct holds data for the ATAPI IDENTIFY_PACKET_DEVICE 261 */ 262 if (!IS_CDROM(ata_drvp)) { 263 264 /* 265 * Try the ATA/ATAPI flush write cache command 266 */ 267 rc = ata_flush_cache(ata_ctlp, ata_drvp); 268 ADBG_WARN(("ata_flush_cache %s\n", 269 rc ? "okay" : "failed")); 270 271 if (!rc) 272 flush_okay = FALSE; 273 } 274 275 276 /* 277 * do something else if flush cache not supported 278 */ 279 } 280 281 /* 282 * just busy wait if any drive doesn't support FLUSH CACHE 283 */ 284 if (!flush_okay) 285 drv_usecwait(ata_flush_delay); 286 return (0); 287 } 288 289 290 static struct cb_ops ata_cb_ops = { 291 ata_open, /* open */ 292 nulldev, /* close */ 293 nodev, /* strategy */ 294 nodev, /* print */ 295 nodev, /* dump */ 296 ata_read, /* read */ 297 nodev, /* write */ 298 nodev, /* ioctl */ 299 nodev, /* devmap */ 300 nodev, /* mmap */ 301 nodev, /* segmap */ 302 nochpoll, /* chpoll */ 303 ddi_prop_op, /* prop_op */ 304 NULL, /* stream info */ 305 D_MP, /* driver compatibility flag */ 306 CB_REV, /* cb_ops revision */ 307 nodev, /* aread */ 308 nodev /* awrite */ 309 }; 310 311 static struct dev_ops ata_ops = { 312 DEVO_REV, /* devo_rev, */ 313 0, /* refcnt */ 314 ddi_getinfo_1to1, /* info */ 315 nulldev, /* identify */ 316 NULL, /* probe */ 317 ata_attach, /* attach */ 318 ata_detach, /* detach */ 319 ata_devo_reset, /* reset */ 320 &ata_cb_ops, /* driver operations */ 321 NULL, /* bus operations */ 322 ata_power /* power */ 323 }; 324 325 /* driver loadable module wrapper */ 326 static struct modldrv modldrv = { 327 &mod_driverops, /* Type of module. This one is a driver */ 328 "ATA AT-bus attachment disk controller Driver", /* module name */ 329 &ata_ops, /* driver ops */ 330 }; 331 332 static struct modlinkage modlinkage = { 333 MODREV_1, (void *)&modldrv, NULL 334 }; 335 336 #ifdef ATA_DEBUG 337 int ata_debug_init = FALSE; 338 int ata_debug_attach = FALSE; 339 340 int ata_debug = ADBG_FLAG_ERROR 341 /* | ADBG_FLAG_ARQ */ 342 /* | ADBG_FLAG_INIT */ 343 /* | ADBG_FLAG_TRACE */ 344 /* | ADBG_FLAG_TRANSPORT */ 345 /* | ADBG_FLAG_WARN */ 346 ; 347 #endif 348 349 int 350 _init(void) 351 { 352 int err; 353 354 #ifdef ATA_DEBUG 355 if (ata_debug_init) 356 debug_enter("\nATA _INIT\n"); 357 #endif 358 359 if ((err = ddi_soft_state_init(&ata_state, sizeof (ata_ctl_t), 0)) != 0) 360 return (err); 361 362 if ((err = scsi_hba_init(&modlinkage)) != 0) { 363 ddi_soft_state_fini(&ata_state); 364 return (err); 365 } 366 367 /* save pointer to SCSA provided bus_ops struct */ 368 scsa_bus_ops_p = ata_ops.devo_bus_ops; 369 370 /* make a copy of SCSA bus_ops */ 371 ata_bus_ops = *(ata_ops.devo_bus_ops); 372 373 /* 374 * Modify our bus_ops to call our routines. Our implementation 375 * will determine if the device is ATA or ATAPI/SCSA and react 376 * accordingly. 377 */ 378 ata_bus_ops.bus_ctl = ata_bus_ctl; 379 380 /* patch our bus_ops into the dev_ops struct */ 381 ata_ops.devo_bus_ops = &ata_bus_ops; 382 383 if ((err = mod_install(&modlinkage)) != 0) { 384 scsi_hba_fini(&modlinkage); 385 ddi_soft_state_fini(&ata_state); 386 } 387 388 /* 389 * Initialize the per driver timer info. 390 */ 391 392 ghd_timer_init(&ata_timer_conf, drv_usectohz(ata_watchdog_usec)); 393 394 return (err); 395 } 396 397 int 398 _fini(void) 399 { 400 int err; 401 402 if ((err = mod_remove(&modlinkage)) == 0) { 403 ghd_timer_fini(&ata_timer_conf); 404 scsi_hba_fini(&modlinkage); 405 ddi_soft_state_fini(&ata_state); 406 } 407 408 return (err); 409 } 410 411 int 412 _info(struct modinfo *modinfop) 413 { 414 return (mod_info(&modlinkage, modinfop)); 415 } 416 417 418 /* 419 * 420 * driver attach entry point 421 * 422 */ 423 424 static int 425 ata_attach( 426 dev_info_t *dip, 427 ddi_attach_cmd_t cmd) 428 { 429 ata_ctl_t *ata_ctlp; 430 ata_drv_t *ata_drvp; 431 ata_drv_t *first_drvp = NULL; 432 uchar_t targ; 433 uchar_t lun; 434 uchar_t lastlun; 435 int atapi_count = 0; 436 int disk_count = 0; 437 438 ADBG_TRACE(("ata_attach entered\n")); 439 #ifdef ATA_DEBUG 440 if (ata_debug_attach) 441 debug_enter("\nATA_ATTACH\n\n"); 442 #endif 443 444 switch (cmd) { 445 case DDI_ATTACH: 446 break; 447 case DDI_RESUME: 448 return (ata_resume(dip)); 449 default: 450 return (DDI_FAILURE); 451 } 452 453 /* initialize controller */ 454 ata_ctlp = ata_init_controller(dip); 455 456 if (ata_ctlp == NULL) 457 goto errout; 458 459 mutex_enter(&ata_ctlp->ac_ccc.ccc_hba_mutex); 460 461 /* initialize drives */ 462 463 for (targ = 0; targ < ATA_MAXTARG; targ++) { 464 465 ata_drvp = ata_init_drive(ata_ctlp, targ, 0); 466 if (ata_drvp == NULL) 467 continue; 468 469 if (first_drvp == NULL) 470 first_drvp = ata_drvp; 471 472 if (ATAPIDRV(ata_drvp)) { 473 atapi_count++; 474 lastlun = ata_drvp->ad_id.ai_lastlun; 475 } else { 476 disk_count++; 477 lastlun = 0; 478 } 479 480 /* 481 * LUN support is currently disabled. Check with SFF-8070i 482 * before enabling. 483 */ 484 if (!ata_enable_atapi_luns) 485 lastlun = 0; 486 487 /* Initialize higher LUNs, if there are any */ 488 for (lun = 1; lun <= lastlun && lun < ATA_MAXLUN; lun++) { 489 if ((ata_drvp = 490 ata_init_drive(ata_ctlp, targ, lun)) != NULL) { 491 ata_show_transfer_mode(ata_ctlp, ata_drvp); 492 } 493 } 494 } 495 496 if ((atapi_count == 0) && (disk_count == 0)) { 497 ADBG_WARN(("ata_attach: no drives detected\n")); 498 goto errout1; 499 } 500 501 /* 502 * Always make certain that a valid drive is selected so 503 * that routines which poll the status register don't get 504 * confused by non-existent drives. 505 */ 506 ddi_put8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_drvhd, 507 first_drvp->ad_drive_bits); 508 ata_nsecwait(400); 509 510 /* 511 * make certain the drive selected 512 */ 513 if (!ata_wait(ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2, 514 0, ATS_BSY, 5000000)) { 515 ADBG_ERROR(("ata_attach: select failed\n")); 516 } 517 518 /* 519 * initialize atapi/ata_dsk modules if we have at least 520 * one drive of that type. 521 */ 522 523 if (atapi_count) { 524 if (!atapi_attach(ata_ctlp)) 525 goto errout1; 526 ata_ctlp->ac_flags |= AC_ATAPI_INIT; 527 } 528 529 if (disk_count) { 530 if (!ata_disk_attach(ata_ctlp)) 531 goto errout1; 532 ata_ctlp->ac_flags |= AC_DISK_INIT; 533 } 534 535 /* 536 * make certain the interrupt and error latches are clear 537 */ 538 if (ata_ctlp->ac_pciide) { 539 540 int instance = ddi_get_instance(dip); 541 if (ddi_create_minor_node(dip, "control", S_IFCHR, instance, 542 DDI_PSEUDO, 0) != DDI_SUCCESS) { 543 goto errout1; 544 } 545 546 (void) ata_pciide_status_clear(ata_ctlp); 547 548 } 549 550 /* 551 * enable the interrupt handler and drop the mutex 552 */ 553 ata_ctlp->ac_flags |= AC_ATTACHED; 554 mutex_exit(&ata_ctlp->ac_ccc.ccc_hba_mutex); 555 556 ata_init_pm(dip); 557 558 ddi_report_dev(dip); 559 return (DDI_SUCCESS); 560 561 errout1: 562 mutex_exit(&ata_ctlp->ac_ccc.ccc_hba_mutex); 563 errout: 564 (void) ata_detach(dip, DDI_DETACH); 565 return (DDI_FAILURE); 566 } 567 568 /* driver detach entry point */ 569 570 static int 571 ata_detach( 572 dev_info_t *dip, 573 ddi_detach_cmd_t cmd) 574 { 575 ata_ctl_t *ata_ctlp; 576 ata_drv_t *ata_drvp; 577 int instance; 578 int i; 579 int j; 580 581 ADBG_TRACE(("ata_detach entered\n")); 582 583 switch (cmd) { 584 case DDI_DETACH: 585 break; 586 case DDI_SUSPEND: 587 return (ata_suspend(dip)); 588 default: 589 return (DDI_FAILURE); 590 } 591 592 instance = ddi_get_instance(dip); 593 ata_ctlp = ddi_get_soft_state(ata_state, instance); 594 595 if (!ata_ctlp) 596 return (DDI_SUCCESS); 597 598 if (ata_ctlp->ac_pm_support) { 599 ATA_BUSY_COMPONENT(dip, 0); 600 if (ata_ctlp->ac_pm_level != PM_LEVEL_D0) { 601 if (ATA_RAISE_POWER(dip, 0, PM_LEVEL_D0) != 602 DDI_SUCCESS) { 603 ATA_IDLE_COMPONENT(dip, 0); 604 return (DDI_FAILURE); 605 } 606 } 607 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "pm-components"); 608 } 609 ata_ctlp->ac_flags &= ~AC_ATTACHED; 610 611 /* destroy ata module */ 612 if (ata_ctlp->ac_flags & AC_DISK_INIT) 613 ata_disk_detach(ata_ctlp); 614 615 /* destroy atapi module */ 616 if (ata_ctlp->ac_flags & AC_ATAPI_INIT) 617 atapi_detach(ata_ctlp); 618 619 ddi_remove_minor_node(dip, NULL); 620 621 /* destroy drives */ 622 for (i = 0; i < ATA_MAXTARG; i++) { 623 for (j = 0; j < ATA_MAXLUN; j++) { 624 ata_drvp = CTL2DRV(ata_ctlp, i, j); 625 if (ata_drvp != NULL) 626 ata_uninit_drive(ata_drvp); 627 } 628 } 629 630 if (ata_ctlp->ac_iohandle1) 631 ddi_regs_map_free(&ata_ctlp->ac_iohandle1); 632 if (ata_ctlp->ac_iohandle2) 633 ddi_regs_map_free(&ata_ctlp->ac_iohandle2); 634 if (ata_ctlp->ac_bmhandle) 635 ddi_regs_map_free(&ata_ctlp->ac_bmhandle); 636 637 /* destroy controller */ 638 ata_destroy_controller(dip); 639 640 ddi_prop_remove_all(dip); 641 642 return (DDI_SUCCESS); 643 } 644 645 /* 646 * Nexus driver bus_ctl entry point 647 */ 648 /*ARGSUSED*/ 649 static int 650 ata_bus_ctl( 651 dev_info_t *d, 652 dev_info_t *r, 653 ddi_ctl_enum_t o, 654 void *a, 655 void *v) 656 { 657 dev_info_t *tdip; 658 int target_type; 659 int rc; 660 char *bufp; 661 662 ADBG_TRACE(("ata_bus_ctl entered\n")); 663 664 switch (o) { 665 666 case DDI_CTLOPS_SIDDEV: 667 return (DDI_FAILURE); 668 669 case DDI_CTLOPS_IOMIN: 670 671 /* 672 * Since we use PIO, we return a minimum I/O size of 673 * one byte. This will need to be updated when we 674 * implement DMA support 675 */ 676 677 *((int *)v) = 1; 678 return (DDI_SUCCESS); 679 680 case DDI_CTLOPS_DMAPMAPC: 681 case DDI_CTLOPS_REPORTINT: 682 case DDI_CTLOPS_REGSIZE: 683 case DDI_CTLOPS_NREGS: 684 case DDI_CTLOPS_SLAVEONLY: 685 case DDI_CTLOPS_AFFINITY: 686 case DDI_CTLOPS_POKE: 687 case DDI_CTLOPS_PEEK: 688 689 /* These ops shouldn't be called by a target driver */ 690 ADBG_ERROR(("ata_bus_ctl: %s%d: invalid op (%d) from %s%d\n", 691 ddi_driver_name(d), ddi_get_instance(d), o, 692 ddi_driver_name(r), ddi_get_instance(r))); 693 694 return (DDI_FAILURE); 695 696 case DDI_CTLOPS_REPORTDEV: 697 case DDI_CTLOPS_INITCHILD: 698 case DDI_CTLOPS_UNINITCHILD: 699 700 /* these require special handling below */ 701 break; 702 703 default: 704 return (ddi_ctlops(d, r, o, a, v)); 705 } 706 707 /* get targets dip */ 708 709 if (o == DDI_CTLOPS_INITCHILD || o == DDI_CTLOPS_UNINITCHILD) 710 tdip = (dev_info_t *)a; 711 else 712 tdip = r; 713 714 /* 715 * XXX - Get class of target 716 * Before the "class" entry in a conf file becomes 717 * a real property, we use an additional property 718 * tentatively called "class_prop". We will require that 719 * new classes (ie. direct) export "class_prop". 720 * SCSA target drivers will not have this property, so 721 * no property implies SCSA. 722 */ 723 if ((ddi_prop_lookup_string(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 724 "class", &bufp) == DDI_PROP_SUCCESS) || 725 (ddi_prop_lookup_string(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 726 "class_prop", &bufp) == DDI_PROP_SUCCESS)) { 727 if (strcmp(bufp, "dada") == 0) 728 target_type = ATA_DEV_DISK; 729 else if (strcmp(bufp, "scsi") == 0) 730 target_type = ATA_DEV_ATAPI; 731 else { 732 ADBG_WARN(("ata_bus_ctl: invalid target class %s\n", 733 bufp)); 734 ddi_prop_free(bufp); 735 return (DDI_FAILURE); 736 } 737 ddi_prop_free(bufp); 738 } else { 739 target_type = ATA_DEV_ATAPI; /* no class prop, assume SCSI */ 740 } 741 742 if (o == DDI_CTLOPS_INITCHILD) { 743 int instance = ddi_get_instance(d); 744 ata_ctl_t *ata_ctlp = ddi_get_soft_state(ata_state, instance); 745 ata_drv_t *ata_drvp; 746 int targ; 747 int lun; 748 int drive_type; 749 char *disk_prop; 750 char *class_prop; 751 752 if (ata_ctlp == NULL) { 753 ADBG_WARN(("ata_bus_ctl: failed to find ctl struct\n")); 754 return (DDI_FAILURE); 755 } 756 757 /* get (target,lun) of child device */ 758 759 targ = ddi_prop_get_int(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 760 "target", -1); 761 if (targ == -1) { 762 ADBG_WARN(("ata_bus_ctl: failed to get targ num\n")); 763 return (DDI_FAILURE); 764 } 765 766 lun = ddi_prop_get_int(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 767 "lun", 0); 768 769 if ((targ < 0) || (targ >= ATA_MAXTARG) || 770 (lun < 0) || (lun >= ATA_MAXLUN)) { 771 return (DDI_FAILURE); 772 } 773 774 ata_drvp = CTL2DRV(ata_ctlp, targ, lun); 775 776 if (ata_drvp == NULL) 777 return (DDI_FAILURE); /* no drive */ 778 779 /* get type of device */ 780 781 if (ATAPIDRV(ata_drvp)) 782 drive_type = ATA_DEV_ATAPI; 783 else 784 drive_type = ATA_DEV_DISK; 785 786 /* 787 * Check for special handling when child driver is 788 * cmdk (which morphs to the correct interface) 789 */ 790 if (strcmp(ddi_get_name(tdip), "cmdk") == 0) { 791 792 if ((target_type == ATA_DEV_DISK) && 793 (target_type != drive_type)) 794 return (DDI_FAILURE); 795 796 target_type = drive_type; 797 798 if (drive_type == ATA_DEV_ATAPI) { 799 class_prop = "scsi"; 800 } else { 801 disk_prop = "dadk"; 802 class_prop = "dada"; 803 804 if (ndi_prop_update_string(DDI_DEV_T_NONE, tdip, 805 "disk", disk_prop) != DDI_PROP_SUCCESS) { 806 ADBG_WARN(("ata_bus_ctl: failed to " 807 "create disk prop\n")); 808 return (DDI_FAILURE); 809 } 810 } 811 812 if (ndi_prop_update_string(DDI_DEV_T_NONE, tdip, 813 "class_prop", class_prop) != DDI_PROP_SUCCESS) { 814 ADBG_WARN(("ata_bus_ctl: failed to " 815 "create class prop\n")); 816 return (DDI_FAILURE); 817 } 818 } 819 820 /* Check that target class matches the device */ 821 822 if (target_type != drive_type) 823 return (DDI_FAILURE); 824 825 /* save pointer to drive struct for ata_disk_bus_ctl */ 826 ddi_set_driver_private(tdip, ata_drvp); 827 828 /* 829 * Determine whether to enable DMA support for this drive. This 830 * check is deferred to this point so that the various dma 831 * properties could reside on the devinfo node should finer 832 * grained dma control be required. 833 */ 834 if (ata_drvp->ad_pciide_dma == ATA_DMA_UNINITIALIZED) { 835 ata_drvp->ad_pciide_dma = 836 ata_init_drive_pcidma(ata_ctlp, ata_drvp, tdip); 837 ata_show_transfer_mode(ata_ctlp, ata_drvp); 838 } 839 } 840 841 if (target_type == ATA_DEV_ATAPI) { 842 rc = scsa_bus_ops_p->bus_ctl(d, r, o, a, v); 843 } else { 844 rc = ata_disk_bus_ctl(d, r, o, a, v); 845 } 846 847 return (rc); 848 } 849 850 /* 851 * 852 * GHD ccc_hba_complete callback 853 * 854 */ 855 856 /* ARGSUSED */ 857 static void 858 ata_hba_complete( 859 void *hba_handle, 860 gcmd_t *gcmdp, 861 int do_callback) 862 { 863 ata_drv_t *ata_drvp; 864 ata_pkt_t *ata_pktp; 865 866 ADBG_TRACE(("ata_hba_complete entered\n")); 867 868 ata_drvp = GCMD2DRV(gcmdp); 869 ata_pktp = GCMD2APKT(gcmdp); 870 if (ata_pktp->ap_complete) 871 (*ata_pktp->ap_complete)(ata_drvp, ata_pktp, 872 do_callback); 873 } 874 875 /* GHD ccc_timeout_func callback */ 876 877 /* ARGSUSED */ 878 static int 879 ata_timeout_func( 880 void *hba_handle, 881 gcmd_t *gcmdp, 882 gtgt_t *gtgtp, 883 gact_t action, 884 int calltype) 885 { 886 ata_ctl_t *ata_ctlp; 887 ata_pkt_t *ata_pktp; 888 ata_drv_t *ata_drvp; 889 890 ADBG_TRACE(("ata_timeout_func entered\n")); 891 892 ata_ctlp = (ata_ctl_t *)hba_handle; 893 894 if (gcmdp != NULL) 895 ata_pktp = GCMD2APKT(gcmdp); 896 else 897 ata_pktp = NULL; 898 899 switch (action) { 900 case GACTION_EARLY_ABORT: 901 /* abort before request was started */ 902 if (ata_pktp != NULL) { 903 ata_pktp->ap_flags |= AP_ABORT; 904 } 905 ghd_complete(&ata_ctlp->ac_ccc, gcmdp); 906 return (TRUE); 907 908 case GACTION_EARLY_TIMEOUT: 909 /* timeout before request was started */ 910 if (ata_pktp != NULL) { 911 ata_pktp->ap_flags |= AP_TIMEOUT; 912 } 913 ghd_complete(&ata_ctlp->ac_ccc, gcmdp); 914 return (TRUE); 915 916 case GACTION_RESET_TARGET: 917 /* 918 * Reset a device is not supported. Resetting a specific 919 * device can't be done at all to an ATA device and if 920 * you send a RESET to an ATAPI device you have to 921 * reset the whole bus to make certain both devices 922 * on the bus stay in sync regarding which device is 923 * the currently selected one. 924 */ 925 return (FALSE); 926 927 case GACTION_RESET_BUS: 928 /* 929 * Issue bus reset and reinitialize both drives. 930 * But only if this is a timed-out request. Target 931 * driver reset requests are ignored because ATA 932 * and ATAPI devices shouldn't be gratuitously reset. 933 * Also disable DMA if it is a CF device. 934 */ 935 if (gcmdp == NULL) 936 break; 937 ata_drvp = GCMD2DRV(gcmdp); 938 if (ata_drvp != NULL) 939 if (ata_drvp->ad_id.ai_config == ATA_ID_CF_TO_ATA) 940 ata_disable_DMA(ata_drvp); 941 return (ata_reset_bus(ata_ctlp)); 942 default: 943 break; 944 } 945 return (FALSE); 946 } 947 948 /* 949 * 950 * Initialize controller's soft-state structure 951 * 952 */ 953 954 static ata_ctl_t * 955 ata_init_controller( 956 dev_info_t *dip) 957 { 958 ata_ctl_t *ata_ctlp; 959 int instance; 960 caddr_t ioaddr1; 961 caddr_t ioaddr2; 962 963 ADBG_TRACE(("ata_init_controller entered\n")); 964 965 instance = ddi_get_instance(dip); 966 967 /* allocate controller structure */ 968 if (ddi_soft_state_zalloc(ata_state, instance) != DDI_SUCCESS) { 969 ADBG_WARN(("ata_init_controller: soft_state_zalloc failed\n")); 970 return (NULL); 971 } 972 973 ata_ctlp = ddi_get_soft_state(ata_state, instance); 974 975 if (ata_ctlp == NULL) { 976 ADBG_WARN(("ata_init_controller: failed to find " 977 "controller struct\n")); 978 return (NULL); 979 } 980 981 /* 982 * initialize per-controller data 983 */ 984 ata_ctlp->ac_dip = dip; 985 ata_ctlp->ac_arq_pktp = kmem_zalloc(sizeof (ata_pkt_t), KM_SLEEP); 986 987 /* 988 * map the device registers 989 */ 990 if (!ata_setup_ioaddr(dip, &ata_ctlp->ac_iohandle1, &ioaddr1, 991 &ata_ctlp->ac_iohandle2, &ioaddr2, 992 &ata_ctlp->ac_bmhandle, &ata_ctlp->ac_bmaddr)) { 993 (void) ata_detach(dip, DDI_DETACH); 994 return (NULL); 995 } 996 997 ADBG_INIT(("ata_init_controller: ioaddr1 = 0x%p, ioaddr2 = 0x%p\n", 998 ioaddr1, ioaddr2)); 999 1000 /* 1001 * Do ARQ setup 1002 */ 1003 atapi_init_arq(ata_ctlp); 1004 1005 /* 1006 * Do PCI-IDE setup 1007 */ 1008 ata_init_pciide(dip, ata_ctlp); 1009 1010 /* 1011 * port addresses associated with ioaddr1 1012 */ 1013 ata_ctlp->ac_ioaddr1 = ioaddr1; 1014 ata_ctlp->ac_data = (ushort_t *)ioaddr1 + AT_DATA; 1015 ata_ctlp->ac_error = (uchar_t *)ioaddr1 + AT_ERROR; 1016 ata_ctlp->ac_feature = (uchar_t *)ioaddr1 + AT_FEATURE; 1017 ata_ctlp->ac_count = (uchar_t *)ioaddr1 + AT_COUNT; 1018 ata_ctlp->ac_sect = (uchar_t *)ioaddr1 + AT_SECT; 1019 ata_ctlp->ac_lcyl = (uchar_t *)ioaddr1 + AT_LCYL; 1020 ata_ctlp->ac_hcyl = (uchar_t *)ioaddr1 + AT_HCYL; 1021 ata_ctlp->ac_drvhd = (uchar_t *)ioaddr1 + AT_DRVHD; 1022 ata_ctlp->ac_status = (uchar_t *)ioaddr1 + AT_STATUS; 1023 ata_ctlp->ac_cmd = (uchar_t *)ioaddr1 + AT_CMD; 1024 1025 /* 1026 * port addresses associated with ioaddr2 1027 */ 1028 ata_ctlp->ac_ioaddr2 = ioaddr2; 1029 ata_ctlp->ac_altstatus = (uchar_t *)ioaddr2 + AT_ALTSTATUS; 1030 ata_ctlp->ac_devctl = (uchar_t *)ioaddr2 + AT_DEVCTL; 1031 1032 /* 1033 * If AC_BSY_WAIT needs to be set for laptops that do 1034 * suspend/resume but do not correctly wait for the busy bit to 1035 * drop after a resume. 1036 */ 1037 ata_ctlp->ac_timing_flags = ddi_prop_get_int(DDI_DEV_T_ANY, 1038 dip, DDI_PROP_DONTPASS, "timing_flags", 0); 1039 /* 1040 * get max transfer size, default to 256 sectors 1041 */ 1042 ata_ctlp->ac_max_transfer = ddi_prop_get_int(DDI_DEV_T_ANY, 1043 dip, DDI_PROP_DONTPASS, "max_transfer", 0x100); 1044 if (ata_ctlp->ac_max_transfer < 1) 1045 ata_ctlp->ac_max_transfer = 1; 1046 if (ata_ctlp->ac_max_transfer > 0x100) 1047 ata_ctlp->ac_max_transfer = 0x100; 1048 1049 /* 1050 * Get the standby timer value 1051 */ 1052 ata_ctlp->ac_standby_time = ddi_prop_get_int(DDI_DEV_T_ANY, 1053 dip, DDI_PROP_DONTPASS, "standby", -1); 1054 1055 /* 1056 * If this is a /pci/pci-ide instance check to see if 1057 * it's supposed to be attached as an /isa/ata 1058 */ 1059 if (ata_ctlp->ac_pciide) { 1060 static char prop_buf[] = "SUNW-ata-ffff-isa"; 1061 int addr1 = (intptr_t)ioaddr1; 1062 1063 1064 if (addr1 < 0 || addr1 > 0xffff) { 1065 (void) ata_detach(dip, DDI_DETACH); 1066 return (NULL); 1067 } 1068 (void) sprintf(prop_buf, "SUNW-ata-%04x-isa", 1069 addr1); 1070 if (ddi_prop_exists(DDI_DEV_T_ANY, ddi_root_node(), 1071 DDI_PROP_DONTPASS, prop_buf)) { 1072 (void) ata_detach(dip, DDI_DETACH); 1073 return (NULL); 1074 } 1075 } 1076 1077 /* Init controller specific stuff */ 1078 (void) ata_spec_init_controller(dip); 1079 1080 /* 1081 * initialize GHD 1082 */ 1083 1084 GHD_WAITQ_INIT(&ata_ctlp->ac_ccc.ccc_waitq, NULL, 1); 1085 1086 if (!ghd_register("ata", &ata_ctlp->ac_ccc, dip, 0, ata_ctlp, 1087 atapi_ccballoc, atapi_ccbfree, 1088 ata_pciide_dma_sg_func, ata_hba_start, 1089 ata_hba_complete, ata_intr, 1090 ata_get_status, ata_process_intr, ata_timeout_func, 1091 &ata_timer_conf, NULL)) { 1092 (void) ata_detach(dip, DDI_DETACH); 1093 return (NULL); 1094 } 1095 1096 ata_ctlp->ac_flags |= AC_GHD_INIT; 1097 return (ata_ctlp); 1098 } 1099 1100 /* destroy a controller */ 1101 1102 static void 1103 ata_destroy_controller( 1104 dev_info_t *dip) 1105 { 1106 ata_ctl_t *ata_ctlp; 1107 int instance; 1108 1109 ADBG_TRACE(("ata_destroy_controller entered\n")); 1110 1111 instance = ddi_get_instance(dip); 1112 ata_ctlp = ddi_get_soft_state(ata_state, instance); 1113 1114 if (ata_ctlp == NULL) 1115 return; 1116 1117 /* destroy ghd */ 1118 if (ata_ctlp->ac_flags & AC_GHD_INIT) 1119 ghd_unregister(&ata_ctlp->ac_ccc); 1120 1121 /* free the pciide buffer (if any) */ 1122 ata_pciide_free(ata_ctlp); 1123 1124 /* destroy controller struct */ 1125 kmem_free(ata_ctlp->ac_arq_pktp, sizeof (ata_pkt_t)); 1126 ddi_soft_state_free(ata_state, instance); 1127 1128 } 1129 1130 1131 /* 1132 * 1133 * initialize a drive 1134 * 1135 */ 1136 1137 static ata_drv_t * 1138 ata_init_drive( 1139 ata_ctl_t *ata_ctlp, 1140 uchar_t targ, 1141 uchar_t lun) 1142 { 1143 static char nec_260[] = "NEC CD-ROM DRIVE"; 1144 ata_drv_t *ata_drvp; 1145 struct ata_id *aidp; 1146 char buf[80]; 1147 int drive_type; 1148 int i; 1149 int valid_version = 0; 1150 1151 ADBG_TRACE(("ata_init_drive entered, targ = %d, lun = %d\n", 1152 targ, lun)); 1153 1154 /* check if device already exists */ 1155 1156 ata_drvp = CTL2DRV(ata_ctlp, targ, lun); 1157 1158 if (ata_drvp != NULL) 1159 return (ata_drvp); 1160 1161 /* allocate new device structure */ 1162 1163 ata_drvp = kmem_zalloc(sizeof (ata_drv_t), KM_SLEEP); 1164 aidp = &ata_drvp->ad_id; 1165 1166 /* 1167 * set up drive struct 1168 */ 1169 ata_drvp->ad_ctlp = ata_ctlp; 1170 ata_drvp->ad_pciide_dma = ATA_DMA_UNINITIALIZED; 1171 ata_drvp->ad_targ = targ; 1172 ata_drvp->ad_drive_bits = 1173 (ata_drvp->ad_targ == 0 ? ATDH_DRIVE0 : ATDH_DRIVE1); 1174 /* 1175 * Add the LUN for SFF-8070i support 1176 */ 1177 ata_drvp->ad_lun = lun; 1178 ata_drvp->ad_drive_bits |= ata_drvp->ad_lun; 1179 1180 /* 1181 * get drive type, side effect is to collect 1182 * IDENTIFY DRIVE data 1183 */ 1184 1185 drive_type = ata_drive_type(ata_drvp->ad_drive_bits, 1186 ata_ctlp->ac_iohandle1, 1187 ata_ctlp->ac_ioaddr1, 1188 ata_ctlp->ac_iohandle2, 1189 ata_ctlp->ac_ioaddr2, 1190 aidp); 1191 1192 switch (drive_type) { 1193 case ATA_DEV_NONE: 1194 /* no drive found */ 1195 goto errout; 1196 case ATA_DEV_ATAPI: 1197 ata_drvp->ad_flags |= AD_ATAPI; 1198 break; 1199 case ATA_DEV_DISK: 1200 ata_drvp->ad_flags |= AD_DISK; 1201 break; 1202 } 1203 1204 /* 1205 * swap bytes of all text fields 1206 */ 1207 if (!ata_strncmp(nec_260, aidp->ai_model, sizeof (aidp->ai_model))) { 1208 swab(aidp->ai_drvser, aidp->ai_drvser, 1209 sizeof (aidp->ai_drvser)); 1210 swab(aidp->ai_fw, aidp->ai_fw, 1211 sizeof (aidp->ai_fw)); 1212 swab(aidp->ai_model, aidp->ai_model, 1213 sizeof (aidp->ai_model)); 1214 } 1215 1216 /* 1217 * Check if this drive has the Single Sector bug 1218 */ 1219 1220 if (ata_check_drive_blacklist(&ata_drvp->ad_id, ATA_BL_1SECTOR)) 1221 ata_drvp->ad_flags |= AD_1SECTOR; 1222 else 1223 ata_drvp->ad_flags &= ~AD_1SECTOR; 1224 1225 /* Check if this drive has the "revert to defaults" bug */ 1226 if (!ata_check_revert_to_defaults(ata_drvp)) 1227 ata_drvp->ad_flags |= AD_NORVRT; 1228 1229 /* Dump the drive info */ 1230 (void) strncpy(buf, aidp->ai_model, sizeof (aidp->ai_model)); 1231 buf[sizeof (aidp->ai_model)-1] = '\0'; 1232 for (i = sizeof (aidp->ai_model) - 2; buf[i] == ' '; i--) 1233 buf[i] = '\0'; 1234 1235 ATAPRT(("?\t%s device at targ %d, lun %d lastlun 0x%x\n", 1236 (ATAPIDRV(ata_drvp) ? "ATAPI":"IDE"), 1237 ata_drvp->ad_targ, ata_drvp->ad_lun, aidp->ai_lastlun)); 1238 1239 ATAPRT(("?\tmodel %s\n", buf)); 1240 1241 if (aidp->ai_majorversion != 0 && aidp->ai_majorversion != 0xffff) { 1242 for (i = 14; i >= 2; i--) { 1243 if (aidp->ai_majorversion & (1 << i)) { 1244 valid_version = i; 1245 break; 1246 } 1247 } 1248 ATAPRT(( 1249 "?\tATA/ATAPI-%d supported, majver 0x%x minver 0x%x\n", 1250 valid_version, 1251 aidp->ai_majorversion, 1252 aidp->ai_minorversion)); 1253 } 1254 1255 if (ata_capability_data) { 1256 1257 ATAPRT(("?\t\tstat %x, err %x\n", 1258 ddi_get8(ata_ctlp->ac_iohandle2, 1259 ata_ctlp->ac_altstatus), 1260 ddi_get8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_error))); 1261 1262 ATAPRT(("?\t\tcfg 0x%x, cap 0x%x\n", 1263 aidp->ai_config, 1264 aidp->ai_cap)); 1265 1266 /* 1267 * Be aware that ATA-6 and later drives may not provide valid 1268 * geometry information and other obsoleted info. 1269 * Select what is printed based on supported ATA model (skip 1270 * anything below ATA/ATAPI-3) 1271 */ 1272 1273 if (valid_version == 0 || aidp->ai_majorversion < 1274 ATAC_MAJVER_6) { 1275 /* 1276 * Supported version less then ATA-6 1277 */ 1278 ATAPRT(("?\t\tcyl %d, hd %d, sec/trk %d\n", 1279 aidp->ai_fixcyls, 1280 aidp->ai_heads, 1281 aidp->ai_sectors)); 1282 } 1283 ATAPRT(("?\t\tmult1 0x%x, mult2 0x%x\n", 1284 aidp->ai_mult1, 1285 aidp->ai_mult2)); 1286 if (valid_version && aidp->ai_majorversion < ATAC_MAJVER_4) { 1287 ATAPRT(( 1288 "?\t\tpiomode 0x%x, dmamode 0x%x, advpiomode 0x%x\n", 1289 aidp->ai_piomode, 1290 aidp->ai_dmamode, 1291 aidp->ai_advpiomode)); 1292 } else { 1293 ATAPRT(("?\t\tadvpiomode 0x%x\n", 1294 aidp->ai_advpiomode)); 1295 } 1296 ATAPRT(("?\t\tminpio %d, minpioflow %d\n", 1297 aidp->ai_minpio, 1298 aidp->ai_minpioflow)); 1299 if (valid_version && aidp->ai_majorversion >= ATAC_MAJVER_4 && 1300 (aidp->ai_validinfo & ATAC_VALIDINFO_83)) { 1301 ATAPRT(("?\t\tdwdma 0x%x, ultradma 0x%x\n", 1302 aidp->ai_dworddma, 1303 aidp->ai_ultradma)); 1304 } else { 1305 ATAPRT(("?\t\tdwdma 0x%x\n", 1306 aidp->ai_dworddma)); 1307 } 1308 } 1309 1310 if (ATAPIDRV(ata_drvp)) { 1311 if (!atapi_init_drive(ata_drvp)) 1312 goto errout; 1313 } else { 1314 if (!ata_disk_init_drive(ata_drvp)) 1315 goto errout; 1316 } 1317 1318 /* 1319 * store pointer in controller struct 1320 */ 1321 CTL2DRV(ata_ctlp, targ, lun) = ata_drvp; 1322 1323 /* 1324 * lock the drive's current settings in case I have to 1325 * reset the drive due to some sort of error 1326 */ 1327 (void) ata_set_feature(ata_ctlp, ata_drvp, ATSF_DIS_REVPOD, 0); 1328 1329 return (ata_drvp); 1330 1331 errout: 1332 ata_uninit_drive(ata_drvp); 1333 return (NULL); 1334 } 1335 1336 /* destroy a drive */ 1337 1338 static void 1339 ata_uninit_drive( 1340 ata_drv_t *ata_drvp) 1341 { 1342 #if 0 1343 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp; 1344 #endif 1345 1346 ADBG_TRACE(("ata_uninit_drive entered\n")); 1347 1348 #if 0 1349 /* 1350 * DON'T DO THIS. disabling interrupts floats the IRQ line 1351 * which generates spurious interrupts 1352 */ 1353 1354 /* 1355 * Select the correct drive 1356 */ 1357 ddi_put8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_drvhd, 1358 ata_drvp->ad_drive_bits); 1359 ata_nsecwait(400); 1360 1361 /* 1362 * Disable interrupts from the drive 1363 */ 1364 ddi_put8(ata_ctlp->ac_iohandle2, ata_ctlp->ac_devctl, 1365 (ATDC_D3 | ATDC_NIEN)); 1366 #endif 1367 1368 /* interface specific clean-ups */ 1369 1370 if (ata_drvp->ad_flags & AD_ATAPI) 1371 atapi_uninit_drive(ata_drvp); 1372 else if (ata_drvp->ad_flags & AD_DISK) 1373 ata_disk_uninit_drive(ata_drvp); 1374 1375 /* free drive struct */ 1376 1377 kmem_free(ata_drvp, sizeof (ata_drv_t)); 1378 } 1379 1380 1381 /* 1382 * ata_drive_type() 1383 * 1384 * The timeout values and exact sequence of checking is critical 1385 * especially for atapi device detection, and should not be changed lightly. 1386 * 1387 */ 1388 static int 1389 ata_drive_type( 1390 uchar_t drvhd, 1391 ddi_acc_handle_t io_hdl1, 1392 caddr_t ioaddr1, 1393 ddi_acc_handle_t io_hdl2, 1394 caddr_t ioaddr2, 1395 struct ata_id *ata_id_bufp) 1396 { 1397 uchar_t status; 1398 1399 ADBG_TRACE(("ata_drive_type entered\n")); 1400 1401 /* 1402 * select the appropriate drive and LUN 1403 */ 1404 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_DRVHD, drvhd); 1405 ata_nsecwait(400); 1406 1407 /* 1408 * make certain the drive is selected, and wait for not busy 1409 */ 1410 (void) ata_wait3(io_hdl2, ioaddr2, 0, ATS_BSY, 0x7f, 0, 0x7f, 0, 1411 5 * 1000000); 1412 1413 status = ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS); 1414 1415 if (status & ATS_BSY) { 1416 ADBG_TRACE(("ata_drive_type 0x%p 0x%x\n", ioaddr1, status)); 1417 return (ATA_DEV_NONE); 1418 } 1419 1420 if (ata_disk_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) 1421 return (ATA_DEV_DISK); 1422 1423 /* 1424 * No disk, check for atapi unit. 1425 */ 1426 if (!atapi_signature(io_hdl1, ioaddr1)) { 1427 #ifndef ATA_DISABLE_ATAPI_1_7 1428 /* 1429 * Check for old (but prevalent) atapi 1.7B 1430 * spec device, the only known example is the 1431 * NEC CDR-260 (not 260R which is (mostly) ATAPI 1.2 1432 * compliant). This device has no signature 1433 * and requires conversion from hex to BCD 1434 * for some scsi audio commands. 1435 */ 1436 if (atapi_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) { 1437 return (ATA_DEV_ATAPI); 1438 } 1439 #endif 1440 return (ATA_DEV_NONE); 1441 } 1442 1443 if (atapi_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) { 1444 return (ATA_DEV_ATAPI); 1445 } 1446 1447 return (ATA_DEV_NONE); 1448 1449 } 1450 1451 /* 1452 * nsec-granularity time delay function 1453 */ 1454 void 1455 ata_nsecwait(clock_t count) 1456 { 1457 extern int tsc_gethrtime_initted; 1458 1459 if (tsc_gethrtime_initted) { 1460 hrtime_t end = gethrtime() + count; 1461 1462 while (gethrtime() < end) { 1463 SMT_PAUSE(); 1464 } 1465 } else { 1466 drv_usecwait(1 + (count / 1000)); 1467 } 1468 } 1469 1470 1471 /* 1472 * Wait for a register of a controller to achieve a specific state. 1473 * To return normally, all the bits in the first sub-mask must be ON, 1474 * all the bits in the second sub-mask must be OFF. 1475 * If timeout_usec microseconds pass without the controller achieving 1476 * the desired bit configuration, we return TRUE, else FALSE. 1477 */ 1478 1479 int ata_usec_delay = 10; 1480 1481 int 1482 ata_wait( 1483 ddi_acc_handle_t io_hdl, 1484 caddr_t ioaddr, 1485 uchar_t onbits, 1486 uchar_t offbits, 1487 uint_t timeout_usec) 1488 { 1489 ushort_t val; 1490 hrtime_t deadline = gethrtime() + 1491 (hrtime_t)timeout_usec * (NANOSEC / MICROSEC); 1492 1493 1494 do { 1495 val = ddi_get8(io_hdl, (uchar_t *)ioaddr + AT_ALTSTATUS); 1496 if ((val & onbits) == onbits && (val & offbits) == 0) 1497 return (TRUE); 1498 drv_usecwait(ata_usec_delay); 1499 } while (gethrtime() < deadline); 1500 1501 return (FALSE); 1502 } 1503 1504 1505 /* 1506 * 1507 * This is a slightly more complicated version that checks 1508 * for error conditions and bails-out rather than looping 1509 * until the timeout expires 1510 */ 1511 int 1512 ata_wait3( 1513 ddi_acc_handle_t io_hdl, 1514 caddr_t ioaddr, 1515 uchar_t onbits1, 1516 uchar_t offbits1, 1517 uchar_t failure_onbits2, 1518 uchar_t failure_offbits2, 1519 uchar_t failure_onbits3, 1520 uchar_t failure_offbits3, 1521 uint_t timeout_usec) 1522 { 1523 ushort_t val; 1524 hrtime_t deadline = gethrtime() + 1525 (hrtime_t)timeout_usec * (NANOSEC / MICROSEC); 1526 1527 do { 1528 val = ddi_get8(io_hdl, (uchar_t *)ioaddr + AT_ALTSTATUS); 1529 1530 /* 1531 * check for expected condition 1532 */ 1533 if ((val & onbits1) == onbits1 && (val & offbits1) == 0) 1534 return (TRUE); 1535 1536 /* 1537 * check for error conditions 1538 */ 1539 if ((val & failure_onbits2) == failure_onbits2 && 1540 (val & failure_offbits2) == 0) { 1541 return (FALSE); 1542 } 1543 1544 if ((val & failure_onbits3) == failure_onbits3 && 1545 (val & failure_offbits3) == 0) { 1546 return (FALSE); 1547 } 1548 1549 drv_usecwait(ata_usec_delay); 1550 } while (gethrtime() < deadline); 1551 1552 return (FALSE); 1553 } 1554 1555 1556 /* 1557 * 1558 * low level routine for ata_disk_id() and atapi_id() 1559 * 1560 */ 1561 1562 int 1563 ata_id_common( 1564 uchar_t id_cmd, 1565 int expect_drdy, 1566 ddi_acc_handle_t io_hdl1, 1567 caddr_t ioaddr1, 1568 ddi_acc_handle_t io_hdl2, 1569 caddr_t ioaddr2, 1570 struct ata_id *aidp) 1571 { 1572 uchar_t status; 1573 1574 ADBG_TRACE(("ata_id_common entered\n")); 1575 1576 bzero(aidp, sizeof (struct ata_id)); 1577 1578 /* 1579 * clear the features register 1580 */ 1581 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_FEATURE, 0); 1582 1583 /* 1584 * Disable interrupts from the device. When the ata 1585 * hardware is sharing its interrupt with another 1586 * device, the shared interrupt might have already been 1587 * unmasked in the interrupt controller and 1588 * triggering ata device interrupts will result in an 1589 * interrupt storm and a hung system. 1590 */ 1591 ddi_put8(io_hdl2, (uchar_t *)ioaddr2 + AT_DEVCTL, ATDC_D3 | ATDC_NIEN); 1592 1593 /* 1594 * issue IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command 1595 */ 1596 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_CMD, id_cmd); 1597 1598 /* wait for the busy bit to settle */ 1599 ata_nsecwait(400); 1600 1601 /* 1602 * read alternate status and check for conditions which 1603 * may indicate the drive is not present, to prevent getting 1604 * stuck in ata_wait3() below. 1605 */ 1606 status = ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS); 1607 1608 /* 1609 * 0x0, 0x7f, or ATS_DF can happen when no drive is present 1610 */ 1611 if ((status == 0x0) || (status == 0x7f) || 1612 ((status & (ATS_BSY|ATS_DF)) == ATS_DF)) { 1613 /* invalid status, can't be an ATA or ATAPI device */ 1614 return (FALSE); 1615 } 1616 1617 /* 1618 * According to the ATA specification, some drives may have 1619 * to read the media to complete this command. We need to 1620 * make sure we give them enough time to respond. 1621 */ 1622 (void) ata_wait3(io_hdl2, ioaddr2, 0, ATS_BSY, 1623 ATS_ERR, ATS_BSY, 0x7f, 0, 5 * 1000000); 1624 1625 /* 1626 * read the status byte and clear the pending interrupt 1627 */ 1628 status = ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_STATUS); 1629 1630 /* 1631 * this happens if there's no drive present 1632 */ 1633 if (status == 0xff || status == 0x7f) { 1634 /* invalid status, can't be an ATA or ATAPI device */ 1635 return (FALSE); 1636 } 1637 1638 if (status & ATS_BSY) { 1639 ADBG_ERROR(("ata_id_common: BUSY status 0x%x error 0x%x\n", 1640 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 +AT_ALTSTATUS), 1641 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1642 return (FALSE); 1643 } 1644 1645 if (!(status & ATS_DRQ)) { 1646 if (status & (ATS_ERR | ATS_DF)) { 1647 return (FALSE); 1648 } 1649 /* 1650 * Give the drive another second to assert DRQ. Some older 1651 * drives de-assert BSY before asserting DRQ. 1652 */ 1653 if (!ata_wait(io_hdl2, ioaddr2, ATS_DRQ, ATS_BSY, 1000000)) { 1654 ADBG_WARN(("ata_id_common: !DRQ status 0x%x error 0x%x\n", 1655 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 +AT_ALTSTATUS), 1656 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1657 return (FALSE); 1658 } 1659 } 1660 1661 /* 1662 * transfer the data 1663 */ 1664 ddi_rep_get16(io_hdl1, (ushort_t *)aidp, (ushort_t *)ioaddr1 + AT_DATA, 1665 NBPSCTR >> 1, DDI_DEV_NO_AUTOINCR); 1666 1667 /* wait for the busy bit to settle */ 1668 ata_nsecwait(400); 1669 1670 1671 /* 1672 * Wait for the drive to recognize I've read all the data. 1673 * Some drives have been observed to take as much as 3msec to 1674 * deassert DRQ after reading the data; allow 10 msec just in case. 1675 * 1676 * Note: some non-compliant ATAPI drives (e.g., NEC Multispin 6V, 1677 * CDR-1350A) don't assert DRDY. If we've made it this far we can 1678 * safely ignore the DRDY bit since the ATAPI Packet command 1679 * actually doesn't require it to ever be asserted. 1680 * 1681 */ 1682 if (!ata_wait(io_hdl2, ioaddr2, (uchar_t)(expect_drdy ? ATS_DRDY : 0), 1683 (ATS_BSY | ATS_DRQ), 1000000)) { 1684 ADBG_WARN(("ata_id_common: bad status 0x%x error 0x%x\n", 1685 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS), 1686 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1687 return (FALSE); 1688 } 1689 1690 /* 1691 * Check to see if the command aborted. This happens if 1692 * an IDENTIFY DEVICE command is issued to an ATAPI PACKET device, 1693 * or if an IDENTIFY PACKET DEVICE command is issued to an ATA 1694 * (non-PACKET) device. 1695 */ 1696 if (status & (ATS_DF | ATS_ERR)) { 1697 ADBG_WARN(("ata_id_common: status 0x%x error 0x%x \n", 1698 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS), 1699 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1700 return (FALSE); 1701 } 1702 return (TRUE); 1703 } 1704 1705 1706 /* 1707 * Low level routine to issue a non-data command and busy wait for 1708 * the completion status. 1709 */ 1710 1711 int 1712 ata_command( 1713 ata_ctl_t *ata_ctlp, 1714 ata_drv_t *ata_drvp, 1715 int expect_drdy, 1716 int silent, 1717 uint_t busy_wait, 1718 uchar_t cmd, 1719 uchar_t feature, 1720 uchar_t count, 1721 uchar_t sector, 1722 uchar_t head, 1723 uchar_t cyl_low, 1724 uchar_t cyl_hi) 1725 { 1726 ddi_acc_handle_t io_hdl1 = ata_ctlp->ac_iohandle1; 1727 ddi_acc_handle_t io_hdl2 = ata_ctlp->ac_iohandle2; 1728 uchar_t status; 1729 1730 /* select the drive */ 1731 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, ata_drvp->ad_drive_bits); 1732 ata_nsecwait(400); 1733 1734 /* make certain the drive selected */ 1735 if (!ata_wait(io_hdl2, ata_ctlp->ac_ioaddr2, 1736 (uchar_t)(expect_drdy ? ATS_DRDY : 0), 1737 ATS_BSY, busy_wait)) { 1738 ADBG_ERROR(("ata_command: select failed " 1739 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x " 1740 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n", 1741 expect_drdy, cmd, feature, count, 1742 sector, head, cyl_low, cyl_hi)); 1743 return (FALSE); 1744 } 1745 1746 /* 1747 * set all the regs 1748 */ 1749 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, (head | ata_drvp->ad_drive_bits)); 1750 ddi_put8(io_hdl1, ata_ctlp->ac_sect, sector); 1751 ddi_put8(io_hdl1, ata_ctlp->ac_count, count); 1752 ddi_put8(io_hdl1, ata_ctlp->ac_lcyl, cyl_low); 1753 ddi_put8(io_hdl1, ata_ctlp->ac_hcyl, cyl_hi); 1754 ddi_put8(io_hdl1, ata_ctlp->ac_feature, feature); 1755 1756 /* send the command */ 1757 ddi_put8(io_hdl1, ata_ctlp->ac_cmd, cmd); 1758 1759 /* wait for the busy bit to settle */ 1760 ata_nsecwait(400); 1761 1762 /* wait for not busy */ 1763 if (!ata_wait(io_hdl2, ata_ctlp->ac_ioaddr2, 0, ATS_BSY, busy_wait)) { 1764 ADBG_ERROR(("ata_command: BSY too long!" 1765 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x " 1766 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n", 1767 expect_drdy, cmd, feature, count, 1768 sector, head, cyl_low, cyl_hi)); 1769 return (FALSE); 1770 } 1771 1772 /* 1773 * wait for DRDY before continuing 1774 */ 1775 (void) ata_wait3(io_hdl2, ata_ctlp->ac_ioaddr2, 1776 ATS_DRDY, ATS_BSY, /* okay */ 1777 ATS_ERR, ATS_BSY, /* cmd failed */ 1778 ATS_DF, ATS_BSY, /* drive failed */ 1779 busy_wait); 1780 1781 /* read status to clear IRQ, and check for error */ 1782 status = ddi_get8(io_hdl1, ata_ctlp->ac_status); 1783 1784 if ((status & (ATS_BSY | ATS_DF | ATS_ERR)) == 0) 1785 return (TRUE); 1786 1787 if (!silent) { 1788 ADBG_ERROR(("ata_command status 0x%x error 0x%x " 1789 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x " 1790 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n", 1791 ddi_get8(io_hdl1, ata_ctlp->ac_status), 1792 ddi_get8(io_hdl1, ata_ctlp->ac_error), 1793 expect_drdy, cmd, feature, count, 1794 sector, head, cyl_low, cyl_hi)); 1795 } 1796 return (FALSE); 1797 } 1798 1799 1800 1801 /* 1802 * 1803 * Issue a SET FEATURES command 1804 * 1805 */ 1806 1807 int 1808 ata_set_feature( 1809 ata_ctl_t *ata_ctlp, 1810 ata_drv_t *ata_drvp, 1811 uchar_t feature, 1812 uchar_t value) 1813 { 1814 int rc; 1815 1816 rc = ata_command(ata_ctlp, ata_drvp, TRUE, TRUE, ata_set_feature_wait, 1817 ATC_SET_FEAT, feature, value, 0, 0, 0, 0); 1818 /* feature, count, sector, head, cyl_low, cyl_hi */ 1819 1820 if (rc) { 1821 return (TRUE); 1822 } 1823 1824 ADBG_ERROR(("?ata_set_feature: (0x%x,0x%x) failed\n", feature, value)); 1825 return (FALSE); 1826 } 1827 1828 1829 1830 /* 1831 * 1832 * Issue a FLUSH CACHE command 1833 * 1834 */ 1835 1836 static int 1837 ata_flush_cache( 1838 ata_ctl_t *ata_ctlp, 1839 ata_drv_t *ata_drvp) 1840 { 1841 /* this command is optional so fail silently */ 1842 return (ata_command(ata_ctlp, ata_drvp, TRUE, TRUE, 1843 ata_flush_cache_wait, 1844 ATC_FLUSH_CACHE, 0, 0, 0, 0, 0, 0)); 1845 } 1846 1847 /* 1848 * ata_setup_ioaddr() 1849 * 1850 * Map the device registers and return the handles. 1851 * 1852 * If this is a ISA-ATA controller then only two handles are 1853 * initialized and returned. 1854 * 1855 * If this is a PCI-IDE controller than a third handle (for the 1856 * PCI-IDE Bus Mastering registers) is initialized and returned. 1857 * 1858 */ 1859 1860 static int 1861 ata_setup_ioaddr( 1862 dev_info_t *dip, 1863 ddi_acc_handle_t *handle1p, 1864 caddr_t *addr1p, 1865 ddi_acc_handle_t *handle2p, 1866 caddr_t *addr2p, 1867 ddi_acc_handle_t *bm_hdlp, 1868 caddr_t *bm_addrp) 1869 { 1870 ddi_device_acc_attr_t dev_attr; 1871 int rnumber; 1872 int rc; 1873 off_t regsize; 1874 1875 /* 1876 * Make certain the controller is enabled and its regs are map-able 1877 * 1878 */ 1879 rc = ddi_dev_regsize(dip, 0, ®size); 1880 if (rc != DDI_SUCCESS || regsize <= AT_CMD) { 1881 ADBG_INIT(("ata_setup_ioaddr(1): rc %d regsize %lld\n", 1882 rc, (long long)regsize)); 1883 return (FALSE); 1884 } 1885 1886 rc = ddi_dev_regsize(dip, 1, ®size); 1887 if (rc != DDI_SUCCESS || regsize <= AT_ALTSTATUS) { 1888 ADBG_INIT(("ata_setup_ioaddr(2): rc %d regsize %lld\n", 1889 rc, (long long)regsize)); 1890 return (FALSE); 1891 } 1892 1893 /* 1894 * setup the device attribute structure for little-endian, 1895 * strict ordering access. 1896 */ 1897 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 1898 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 1899 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1900 1901 *handle1p = NULL; 1902 *handle2p = NULL; 1903 *bm_hdlp = NULL; 1904 1905 /* 1906 * Determine whether this is a ISA, PNP-ISA, or PCI-IDE device 1907 */ 1908 if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "pnp-csn")) { 1909 /* it's PNP-ISA, skip over the extra reg tuple */ 1910 rnumber = 1; 1911 goto not_pciide; 1912 } 1913 1914 /* else, it's ISA or PCI-IDE, check further */ 1915 rnumber = 0; 1916 1917 if (!ata_is_pci(dip)) { 1918 /* 1919 * If it's not a PCI-IDE, there are only two reg tuples 1920 * and the first one contains the I/O base (170 or 1f0) 1921 * rather than the controller instance number. 1922 */ 1923 ADBG_TRACE(("ata_setup_ioaddr !pci-ide\n")); 1924 goto not_pciide; 1925 } 1926 1927 1928 /* 1929 * Map the correct half of the PCI-IDE Bus Master registers. 1930 * There's a single BAR that maps these registers for both 1931 * controller's in a dual-controller chip and it's upto my 1932 * parent nexus, pciide, to adjust which (based on my instance 1933 * number) half this call maps. 1934 */ 1935 rc = ddi_dev_regsize(dip, 2, ®size); 1936 if (rc != DDI_SUCCESS || regsize < 8) { 1937 ADBG_INIT(("ata_setup_ioaddr(3): rc %d regsize %lld\n", 1938 rc, (long long)regsize)); 1939 goto not_pciide; 1940 } 1941 1942 rc = ddi_regs_map_setup(dip, 2, bm_addrp, 0, 0, &dev_attr, bm_hdlp); 1943 1944 if (rc != DDI_SUCCESS) { 1945 /* map failed, try to use in non-pci-ide mode */ 1946 ADBG_WARN(("ata_setup_ioaddr bus master map failed, rc=0x%x\n", 1947 rc)); 1948 *bm_hdlp = NULL; 1949 } 1950 1951 not_pciide: 1952 /* 1953 * map the lower command block registers 1954 */ 1955 1956 rc = ddi_regs_map_setup(dip, rnumber, addr1p, 0, 0, &dev_attr, 1957 handle1p); 1958 1959 if (rc != DDI_SUCCESS) { 1960 cmn_err(CE_WARN, "ata: reg tuple 0 map failed, rc=0x%x\n", rc); 1961 goto out1; 1962 } 1963 1964 /* 1965 * If the controller is being used in compatibility mode 1966 * via /devices/isa/ata@1,{1f0,1f0}/..., the reg property 1967 * will specify zeros for the I/O ports for the PCI 1968 * instance. 1969 */ 1970 if (*addr1p == 0) { 1971 ADBG_TRACE(("ata_setup_ioaddr ioaddr1 0\n")); 1972 goto out2; 1973 } 1974 1975 /* 1976 * map the upper control block registers 1977 */ 1978 rc = ddi_regs_map_setup(dip, rnumber + 1, addr2p, 0, 0, &dev_attr, 1979 handle2p); 1980 if (rc == DDI_SUCCESS) 1981 return (TRUE); 1982 1983 cmn_err(CE_WARN, "ata: reg tuple 1 map failed, rc=0x%x", rc); 1984 1985 out2: 1986 if (*handle1p != NULL) { 1987 ddi_regs_map_free(handle1p); 1988 *handle1p = NULL; 1989 } 1990 1991 out1: 1992 if (*bm_hdlp != NULL) { 1993 ddi_regs_map_free(bm_hdlp); 1994 *bm_hdlp = NULL; 1995 } 1996 return (FALSE); 1997 1998 } 1999 2000 /* 2001 * 2002 * Currently, the only supported controllers are ones which 2003 * support the SFF-8038 Bus Mastering spec. 2004 * 2005 * Check the parent node's IEEE 1275 class-code property to 2006 * determine if it's an PCI-IDE instance which supports SFF-8038 2007 * Bus Mastering. It's perfectly valid to have a PCI-IDE controller 2008 * that doesn't do Bus Mastering. In that case, my interrupt handler 2009 * only uses the interrupt latch bit in PCI-IDE status register. 2010 * The assumption is that the programming interface byte of the 2011 * class-code property reflects the bus master DMA capability of 2012 * the controller. 2013 * 2014 * Whether the drive support supports the DMA option still needs 2015 * to be checked later. Each individual request also has to be 2016 * checked for alignment and size to decide whether to use the 2017 * DMA transfer mode. 2018 */ 2019 2020 static void 2021 ata_init_pciide( 2022 dev_info_t *dip, 2023 ata_ctl_t *ata_ctlp) 2024 { 2025 uint_t class_code; 2026 uchar_t status; 2027 2028 ata_cntrl_DMA_sel_msg = NULL; 2029 2030 if (ata_ctlp->ac_bmhandle == NULL) { 2031 ata_ctlp->ac_pciide = FALSE; 2032 ata_ctlp->ac_pciide_bm = FALSE; 2033 ata_cntrl_DMA_sel_msg = "cntrl not Bus Master DMA capable"; 2034 return; 2035 } 2036 2037 /* 2038 * check if it's a known bogus PCI-IDE chip 2039 */ 2040 if (ata_check_pciide_blacklist(dip, ATA_BL_BOGUS)) { 2041 ADBG_WARN(("ata_setup_ioaddr pci-ide blacklist\n")); 2042 ata_ctlp->ac_pciide = FALSE; 2043 ata_ctlp->ac_pciide_bm = FALSE; 2044 ata_cntrl_DMA_sel_msg = "cntrl blacklisted"; 2045 return; 2046 } 2047 ata_ctlp->ac_pciide = TRUE; 2048 2049 if (ata_check_pciide_blacklist(dip, ATA_BL_BMSTATREG_PIO_BROKEN)) { 2050 ata_ctlp->ac_flags |= AC_BMSTATREG_PIO_BROKEN; 2051 } 2052 2053 /* 2054 * check for a PCI-IDE chip with a broken DMA engine 2055 */ 2056 if (ata_check_pciide_blacklist(dip, ATA_BL_NODMA)) { 2057 ata_ctlp->ac_pciide_bm = FALSE; 2058 ata_cntrl_DMA_sel_msg = 2059 "cntrl blacklisted/DMA engine broken"; 2060 return; 2061 } 2062 2063 /* 2064 * Check the Programming Interface register to determine 2065 * if this device supports PCI-IDE Bus Mastering. Some PCI-IDE 2066 * devices don't support Bus Mastering or DMA. 2067 * Since we are dealing with pre-qualified pci-ide controller, 2068 * check programming interface byte only. 2069 */ 2070 2071 class_code = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 2072 DDI_PROP_DONTPASS, "class-code", 0); 2073 if ((class_code & PCIIDE_BM_CAP_MASK) != PCIIDE_BM_CAP_MASK) { 2074 ata_ctlp->ac_pciide_bm = FALSE; 2075 ata_cntrl_DMA_sel_msg = 2076 "cntrl not Bus Master DMA capable"; 2077 return; 2078 } 2079 2080 /* 2081 * Avoid doing DMA on "simplex" chips which share hardware 2082 * between channels 2083 */ 2084 status = ddi_get8(ata_ctlp->ac_bmhandle, 2085 (uchar_t *)ata_ctlp->ac_bmaddr + PCIIDE_BMISX_REG); 2086 /* 2087 * Some motherboards have CSB5's that are wired "to emulate CSB4 mode". 2088 * In such a mode, the simplex bit is asserted, but in fact testing 2089 * on such a motherboard has shown that the devices are not simplex 2090 * -- DMA can be used on both channels concurrently with no special 2091 * considerations. For chips like this, we have the ATA_BL_NO_SIMPLEX 2092 * flag set to indicate that the value of the simplex bit can be 2093 * ignored. 2094 */ 2095 2096 if (status & PCIIDE_BMISX_SIMPLEX) { 2097 if (ata_check_pciide_blacklist(dip, ATA_BL_NO_SIMPLEX)) { 2098 cmn_err(CE_WARN, "Ignoring false simplex bit \n"); 2099 2100 } else { 2101 2102 int simplex_dma_channel, *rp, proplen, channel; 2103 int dma_on = FALSE; 2104 2105 /* 2106 * By default,use DMA on channel 0 and PIO on channel 2107 * 1. This can be switched by setting 2108 * ata-simplex-dma-channel to: 2109 * 0 DMA on channel 0 (default without this 2110 * property) 2111 * 1 DMA on channel 1 2112 * any other value: DMA off on both channels. 2113 */ 2114 simplex_dma_channel = ata_prop_lookup_int(DDI_DEV_T_ANY, 2115 ata_ctlp->ac_dip, 0, "ata-simplex-dma-channel", 0); 2116 2117 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 2118 ata_ctlp->ac_dip, DDI_PROP_DONTPASS, "reg", &rp, 2119 (uint_t *)&proplen) == DDI_PROP_SUCCESS) { 2120 2121 channel = *rp; 2122 ddi_prop_free(rp); 2123 2124 if (simplex_dma_channel == channel) { 2125 cmn_err(CE_CONT, "?ata: simplex " 2126 "controller. DMA on channel" 2127 " %d PIO on channel %d", 2128 channel, channel ? 0:1); 2129 dma_on = TRUE; 2130 } else { 2131 ata_cntrl_DMA_sel_msg = 2132 "simplex controller"; 2133 } 2134 } 2135 2136 if (dma_on == FALSE) { 2137 ata_ctlp->ac_pciide_bm = FALSE; 2138 2139 return; 2140 } 2141 } 2142 } 2143 2144 /* 2145 * It's a compatible PCI-IDE Bus Mastering controller, 2146 * allocate and map the DMA Scatter/Gather list (PRDE table). 2147 */ 2148 if (ata_pciide_alloc(dip, ata_ctlp)) 2149 ata_ctlp->ac_pciide_bm = TRUE; 2150 else { 2151 ata_ctlp->ac_pciide_bm = FALSE; 2152 ata_cntrl_DMA_sel_msg = "unable to init DMA S/G list"; 2153 } 2154 } 2155 2156 /* 2157 * 2158 * Determine whether to enable DMA support for this drive. 2159 * The controller and the drive both have to support DMA. 2160 * The controller's capabilities were already checked in 2161 * ata_init_pciide(), now just check the drive's capabilities. 2162 * 2163 */ 2164 2165 static int 2166 ata_init_drive_pcidma( 2167 ata_ctl_t *ata_ctlp, 2168 ata_drv_t *ata_drvp, 2169 dev_info_t *tdip) 2170 { 2171 boolean_t dma; 2172 boolean_t cd_dma; 2173 boolean_t disk_dma; 2174 boolean_t atapi_dma; 2175 int ata_options; 2176 2177 ata_dev_DMA_sel_msg = NULL; 2178 2179 if (ata_ctlp->ac_pciide_bm != TRUE) { 2180 ata_dev_DMA_sel_msg = 2181 "controller is not Bus Master capable"; 2182 2183 return (ATA_DMA_OFF); 2184 } 2185 2186 ata_options = ddi_prop_get_int(DDI_DEV_T_ANY, ata_ctlp->ac_dip, 2187 0, "ata-options", 0); 2188 2189 if (!(ata_options & ATA_OPTIONS_DMA)) { 2190 /* 2191 * Either the ata-options property was not found or 2192 * DMA is not enabled by this property 2193 */ 2194 ata_dev_DMA_sel_msg = 2195 "disabled by \"ata-options\" property"; 2196 2197 return (ATA_DMA_OFF); 2198 } 2199 2200 if (ata_check_drive_blacklist(&ata_drvp->ad_id, ATA_BL_NODMA)) { 2201 ata_dev_DMA_sel_msg = "device not DMA capable; blacklisted"; 2202 2203 return (ATA_DMA_OFF); 2204 } 2205 2206 /* 2207 * DMA mode is mandatory on ATA-3 (or newer) drives but is 2208 * optional on ATA-2 (or older) drives. 2209 * 2210 * On ATA-2 drives the ai_majorversion word will probably 2211 * be 0xffff or 0x0000, check the (now obsolete) DMA bit in 2212 * the capabilities word instead. The order of these tests 2213 * is important since an ATA-3 drive doesn't have to set 2214 * the DMA bit in the capabilities word. 2215 * 2216 */ 2217 2218 if (!((ata_drvp->ad_id.ai_majorversion & 0x8000) == 0 && 2219 ata_drvp->ad_id.ai_majorversion >= (1 << 2)) && 2220 !(ata_drvp->ad_id.ai_cap & ATAC_DMA_SUPPORT)) { 2221 ata_dev_DMA_sel_msg = "device not DMA capable"; 2222 2223 return (ATA_DMA_OFF); 2224 } 2225 2226 dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2227 0, "ata-dma-enabled", TRUE); 2228 disk_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2229 0, "ata-disk-dma-enabled", TRUE); 2230 cd_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2231 0, "atapi-cd-dma-enabled", FALSE); 2232 atapi_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2233 0, "atapi-other-dma-enabled", TRUE); 2234 2235 if (dma == FALSE) { 2236 cmn_err(CE_CONT, "?ata_init_drive_pcidma: " 2237 "DMA disabled by \"ata-dma-enabled\" property"); 2238 ata_dev_DMA_sel_msg = "disabled by prop ata-dma-enabled"; 2239 2240 return (ATA_DMA_OFF); 2241 } 2242 2243 if (IS_CDROM(ata_drvp) == TRUE) { 2244 if (cd_dma == FALSE) { 2245 ata_dev_DMA_sel_msg = 2246 "disabled. Control with \"atapi-cd-dma-enabled\"" 2247 " property"; 2248 2249 return (ATA_DMA_OFF); 2250 } 2251 2252 } else if (ATAPIDRV(ata_drvp) == FALSE) { 2253 if (disk_dma == FALSE) { 2254 ata_dev_DMA_sel_msg = 2255 "disabled by \"ata-disk-dma-enabled\" property"; 2256 2257 return (ATA_DMA_OFF); 2258 } 2259 2260 } else if (atapi_dma == FALSE) { 2261 ata_dev_DMA_sel_msg = 2262 "disabled by \"atapi-other-dma-enabled\" property"; 2263 2264 return (ATA_DMA_OFF); 2265 } 2266 2267 return (ATA_DMA_ON); 2268 } 2269 2270 2271 2272 /* 2273 * this compare routine squeezes out extra blanks and 2274 * returns TRUE if p1 matches the leftmost substring of p2 2275 */ 2276 2277 static int 2278 ata_strncmp( 2279 char *p1, 2280 char *p2, 2281 int cnt) 2282 { 2283 2284 for (;;) { 2285 /* 2286 * skip over any extra blanks in both strings 2287 */ 2288 while (*p1 != '\0' && *p1 == ' ') 2289 p1++; 2290 2291 while (cnt != 0 && *p2 == ' ') { 2292 p2++; 2293 cnt--; 2294 } 2295 2296 /* 2297 * compare the two strings 2298 */ 2299 2300 if (cnt == 0 || *p1 != *p2) 2301 break; 2302 2303 while (cnt > 0 && *p1 == *p2) { 2304 p1++; 2305 p2++; 2306 cnt--; 2307 } 2308 2309 } 2310 2311 /* return TRUE if both strings ended at same point */ 2312 return ((*p1 == '\0') ? TRUE : FALSE); 2313 } 2314 2315 /* 2316 * Per PSARC/1997/281 create variant="atapi" property (if necessary) 2317 * on the target's dev_info node. Currently, the sd target driver 2318 * is the only driver which refers to this property. 2319 * 2320 * If the flag ata_id_debug is set also create the 2321 * the "ata" or "atapi" property on the target's dev_info node 2322 * 2323 */ 2324 2325 int 2326 ata_prop_create( 2327 dev_info_t *tgt_dip, 2328 ata_drv_t *ata_drvp, 2329 char *name) 2330 { 2331 int rc; 2332 2333 ADBG_TRACE(("ata_prop_create 0x%p 0x%p %s\n", tgt_dip, ata_drvp, name)); 2334 2335 if (strcmp("atapi", name) == 0) { 2336 rc = ndi_prop_update_string(DDI_DEV_T_NONE, tgt_dip, 2337 "variant", name); 2338 if (rc != DDI_PROP_SUCCESS) 2339 return (FALSE); 2340 } 2341 2342 if (!ata_id_debug) 2343 return (TRUE); 2344 2345 rc = ndi_prop_update_byte_array(DDI_DEV_T_NONE, tgt_dip, name, 2346 (uchar_t *)&ata_drvp->ad_id, sizeof (ata_drvp->ad_id)); 2347 if (rc != DDI_PROP_SUCCESS) { 2348 ADBG_ERROR(("ata_prop_create failed, rc=%d\n", rc)); 2349 } 2350 return (TRUE); 2351 } 2352 2353 2354 /* *********************************************************************** */ 2355 /* *********************************************************************** */ 2356 /* *********************************************************************** */ 2357 2358 /* 2359 * This state machine doesn't implement the ATAPI Optional Overlap 2360 * feature. You need that feature to efficiently support ATAPI 2361 * tape drives. See the 1394-ATA Tailgate spec (D97107), Figure 24, 2362 * for an example of how to add the necessary additional NextActions 2363 * and NextStates to this FSM and the atapi_fsm, in order to support 2364 * the Overlap Feature. 2365 */ 2366 2367 2368 uchar_t ata_ctlr_fsm_NextAction[ATA_CTLR_NSTATES][ATA_CTLR_NFUNCS] = { 2369 /* --------------------- next action --------------------- | - current - */ 2370 /* start0 --- start1 ---- intr ------ fini --- reset --- */ 2371 { AC_START, AC_START, AC_NADA, AC_NADA, AC_RESET_I }, /* idle */ 2372 { AC_BUSY, AC_BUSY, AC_INTR, AC_FINI, AC_RESET_A }, /* active0 */ 2373 { AC_BUSY, AC_BUSY, AC_INTR, AC_FINI, AC_RESET_A }, /* active1 */ 2374 }; 2375 2376 uchar_t ata_ctlr_fsm_NextState[ATA_CTLR_NSTATES][ATA_CTLR_NFUNCS] = { 2377 2378 /* --------------------- next state --------------------- | - current - */ 2379 /* start0 --- start1 ---- intr ------ fini --- reset --- */ 2380 { AS_ACTIVE0, AS_ACTIVE1, AS_IDLE, AS_IDLE, AS_IDLE }, /* idle */ 2381 { AS_ACTIVE0, AS_ACTIVE0, AS_ACTIVE0, AS_IDLE, AS_ACTIVE0 }, /* active0 */ 2382 { AS_ACTIVE1, AS_ACTIVE1, AS_ACTIVE1, AS_IDLE, AS_ACTIVE1 }, /* active1 */ 2383 }; 2384 2385 2386 static int 2387 ata_ctlr_fsm( 2388 uchar_t fsm_func, 2389 ata_ctl_t *ata_ctlp, 2390 ata_drv_t *ata_drvp, 2391 ata_pkt_t *ata_pktp, 2392 int *DoneFlgp) 2393 { 2394 uchar_t action; 2395 uchar_t current_state; 2396 uchar_t next_state; 2397 int rc; 2398 2399 current_state = ata_ctlp->ac_state; 2400 action = ata_ctlr_fsm_NextAction[current_state][fsm_func]; 2401 next_state = ata_ctlr_fsm_NextState[current_state][fsm_func]; 2402 2403 /* 2404 * Set the controller's new state 2405 */ 2406 ata_ctlp->ac_state = next_state; 2407 switch (action) { 2408 2409 case AC_BUSY: 2410 return (ATA_FSM_RC_BUSY); 2411 2412 case AC_NADA: 2413 return (ATA_FSM_RC_OKAY); 2414 2415 case AC_START: 2416 ASSERT(ata_ctlp->ac_active_pktp == NULL); 2417 ASSERT(ata_ctlp->ac_active_drvp == NULL); 2418 2419 ata_ctlp->ac_active_pktp = ata_pktp; 2420 ata_ctlp->ac_active_drvp = ata_drvp; 2421 2422 rc = (*ata_pktp->ap_start)(ata_ctlp, ata_drvp, ata_pktp); 2423 2424 if (rc == ATA_FSM_RC_BUSY) { 2425 /* the request didn't start, GHD will requeue it */ 2426 ata_ctlp->ac_state = AS_IDLE; 2427 ata_ctlp->ac_active_pktp = NULL; 2428 ata_ctlp->ac_active_drvp = NULL; 2429 } 2430 return (rc); 2431 2432 case AC_INTR: 2433 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2434 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2435 2436 ata_drvp = ata_ctlp->ac_active_drvp; 2437 ata_pktp = ata_ctlp->ac_active_pktp; 2438 return ((*ata_pktp->ap_intr)(ata_ctlp, ata_drvp, ata_pktp)); 2439 2440 case AC_RESET_A: /* Reset, controller active */ 2441 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2442 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2443 2444 /* clean up the active request */ 2445 ata_pktp = ata_ctlp->ac_active_pktp; 2446 ata_pktp->ap_flags |= AP_DEV_RESET | AP_BUS_RESET; 2447 2448 /* halt the DMA engine */ 2449 if (ata_pktp->ap_pciide_dma) { 2450 ata_pciide_dma_stop(ata_ctlp); 2451 (void) ata_pciide_status_clear(ata_ctlp); 2452 } 2453 2454 /* Do a Software Reset to unwedge the bus */ 2455 if (!ata_software_reset(ata_ctlp)) { 2456 return (ATA_FSM_RC_BUSY); 2457 } 2458 2459 /* Then send a DEVICE RESET cmd to each ATAPI device */ 2460 atapi_fsm_reset(ata_ctlp); 2461 return (ATA_FSM_RC_FINI); 2462 2463 case AC_RESET_I: /* Reset, controller idle */ 2464 /* Do a Software Reset to unwedge the bus */ 2465 if (!ata_software_reset(ata_ctlp)) { 2466 return (ATA_FSM_RC_BUSY); 2467 } 2468 2469 /* Then send a DEVICE RESET cmd to each ATAPI device */ 2470 atapi_fsm_reset(ata_ctlp); 2471 return (ATA_FSM_RC_OKAY); 2472 2473 case AC_FINI: 2474 break; 2475 } 2476 2477 /* 2478 * AC_FINI, check ARQ needs to be started or finished 2479 */ 2480 2481 ASSERT(action == AC_FINI); 2482 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2483 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2484 2485 /* 2486 * The active request is done now. 2487 * Disconnect the request from the controller and 2488 * add it to the done queue. 2489 */ 2490 ata_drvp = ata_ctlp->ac_active_drvp; 2491 ata_pktp = ata_ctlp->ac_active_pktp; 2492 2493 /* 2494 * If ARQ pkt is done, get ptr to original pkt and wrap it up. 2495 */ 2496 if (ata_pktp == ata_ctlp->ac_arq_pktp) { 2497 ata_pkt_t *arq_pktp; 2498 2499 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ done\n", ata_ctlp)); 2500 2501 arq_pktp = ata_pktp; 2502 ata_pktp = ata_ctlp->ac_fault_pktp; 2503 ata_ctlp->ac_fault_pktp = NULL; 2504 if (arq_pktp->ap_flags & (AP_ERROR | AP_BUS_RESET)) 2505 ata_pktp->ap_flags |= AP_ARQ_ERROR; 2506 else 2507 ata_pktp->ap_flags |= AP_ARQ_OKAY; 2508 goto all_done; 2509 } 2510 2511 2512 #define AP_ARQ_NEEDED (AP_ARQ_ON_ERROR | AP_GOT_STATUS | AP_ERROR) 2513 2514 /* 2515 * Start ARQ pkt if necessary 2516 */ 2517 if ((ata_pktp->ap_flags & AP_ARQ_NEEDED) == AP_ARQ_NEEDED && 2518 (ata_pktp->ap_status & ATS_ERR)) { 2519 2520 /* set controller state back to active */ 2521 ata_ctlp->ac_state = current_state; 2522 2523 /* try to start the ARQ pkt */ 2524 rc = ata_start_arq(ata_ctlp, ata_drvp, ata_pktp); 2525 2526 if (rc == ATA_FSM_RC_BUSY) { 2527 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ BUSY\n", ata_ctlp)); 2528 /* let the target driver handle the problem */ 2529 ata_ctlp->ac_state = AS_IDLE; 2530 ata_ctlp->ac_active_pktp = NULL; 2531 ata_ctlp->ac_active_drvp = NULL; 2532 ata_ctlp->ac_fault_pktp = NULL; 2533 goto all_done; 2534 } 2535 2536 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ started\n", ata_ctlp)); 2537 return (rc); 2538 } 2539 2540 /* 2541 * Normal completion, no error status, and not an ARQ pkt, 2542 * just fall through. 2543 */ 2544 2545 all_done: 2546 2547 /* 2548 * wrap everything up and tie a ribbon around it 2549 */ 2550 ata_ctlp->ac_active_pktp = NULL; 2551 ata_ctlp->ac_active_drvp = NULL; 2552 if (APKT2GCMD(ata_pktp) != (gcmd_t *)0) { 2553 ghd_complete(&ata_ctlp->ac_ccc, APKT2GCMD(ata_pktp)); 2554 if (DoneFlgp) 2555 *DoneFlgp = TRUE; 2556 } 2557 2558 return (ATA_FSM_RC_OKAY); 2559 } 2560 2561 2562 static int 2563 ata_start_arq( 2564 ata_ctl_t *ata_ctlp, 2565 ata_drv_t *ata_drvp, 2566 ata_pkt_t *ata_pktp) 2567 { 2568 ata_pkt_t *arq_pktp; 2569 int bytes; 2570 uint_t senselen; 2571 2572 ADBG_ARQ(("ata_start_arq 0x%p ARQ needed\n", ata_ctlp)); 2573 2574 /* 2575 * Determine just the size of the Request Sense Data buffer within 2576 * the scsi_arq_status structure. 2577 */ 2578 #define SIZEOF_ARQ_HEADER (sizeof (struct scsi_arq_status) \ 2579 - sizeof (struct scsi_extended_sense)) 2580 senselen = ata_pktp->ap_statuslen - SIZEOF_ARQ_HEADER; 2581 ASSERT(senselen > 0); 2582 2583 2584 /* save ptr to original pkt */ 2585 ata_ctlp->ac_fault_pktp = ata_pktp; 2586 2587 /* switch the controller's active pkt to the ARQ pkt */ 2588 arq_pktp = ata_ctlp->ac_arq_pktp; 2589 ata_ctlp->ac_active_pktp = arq_pktp; 2590 2591 /* finish initializing the ARQ CDB */ 2592 ata_ctlp->ac_arq_cdb[1] = ata_drvp->ad_lun << 4; 2593 ata_ctlp->ac_arq_cdb[4] = senselen; 2594 2595 /* finish initializing the ARQ pkt */ 2596 arq_pktp->ap_v_addr = (caddr_t)&ata_pktp->ap_scbp->sts_sensedata; 2597 2598 arq_pktp->ap_resid = senselen; 2599 arq_pktp->ap_flags = AP_ATAPI | AP_READ; 2600 arq_pktp->ap_cdb_pad = 2601 ((unsigned)(ata_drvp->ad_cdb_len - arq_pktp->ap_cdb_len)) >> 1; 2602 2603 bytes = min(senselen, ATAPI_MAX_BYTES_PER_DRQ); 2604 arq_pktp->ap_hicyl = (uchar_t)(bytes >> 8); 2605 arq_pktp->ap_lwcyl = (uchar_t)bytes; 2606 2607 /* 2608 * This packet is shared by all drives on this controller 2609 * therefore we need to init the drive number on every ARQ. 2610 */ 2611 arq_pktp->ap_hd = ata_drvp->ad_drive_bits; 2612 2613 /* start it up */ 2614 return ((*arq_pktp->ap_start)(ata_ctlp, ata_drvp, arq_pktp)); 2615 } 2616 2617 /* 2618 * 2619 * reset the bus 2620 * 2621 */ 2622 2623 static int 2624 ata_reset_bus( 2625 ata_ctl_t *ata_ctlp) 2626 { 2627 int watchdog; 2628 uchar_t drive; 2629 int rc = FALSE; 2630 uchar_t fsm_func; 2631 int DoneFlg = FALSE; 2632 2633 /* 2634 * Do a Software Reset to unwedge the bus, and send 2635 * ATAPI DEVICE RESET to each ATAPI drive. 2636 */ 2637 fsm_func = ATA_FSM_RESET; 2638 for (watchdog = ata_reset_bus_watchdog; watchdog > 0; watchdog--) { 2639 switch (ata_ctlr_fsm(fsm_func, ata_ctlp, NULL, NULL, 2640 &DoneFlg)) { 2641 case ATA_FSM_RC_OKAY: 2642 rc = TRUE; 2643 goto fsm_done; 2644 2645 case ATA_FSM_RC_BUSY: 2646 return (FALSE); 2647 2648 case ATA_FSM_RC_INTR: 2649 fsm_func = ATA_FSM_INTR; 2650 rc = TRUE; 2651 continue; 2652 2653 case ATA_FSM_RC_FINI: 2654 fsm_func = ATA_FSM_FINI; 2655 rc = TRUE; 2656 continue; 2657 } 2658 } 2659 ADBG_WARN(("ata_reset_bus: watchdog\n")); 2660 2661 fsm_done: 2662 2663 /* 2664 * Reinitialize the ATA drives 2665 */ 2666 for (drive = 0; drive < ATA_MAXTARG; drive++) { 2667 ata_drv_t *ata_drvp; 2668 2669 if ((ata_drvp = CTL2DRV(ata_ctlp, drive, 0)) == NULL) 2670 continue; 2671 2672 if (ATAPIDRV(ata_drvp)) 2673 continue; 2674 2675 /* 2676 * Reprogram the Read/Write Multiple block factor 2677 * and current geometry into the drive. 2678 */ 2679 if (!ata_disk_setup_parms(ata_ctlp, ata_drvp)) 2680 rc = FALSE; 2681 } 2682 2683 /* If DoneFlg is TRUE, it means that ghd_complete() function */ 2684 /* has been already called. In this case ignore any errors and */ 2685 /* return TRUE to the caller, otherwise return the value of rc */ 2686 /* to the caller */ 2687 if (DoneFlg) 2688 return (TRUE); 2689 else 2690 return (rc); 2691 } 2692 2693 2694 /* 2695 * 2696 * Low level routine to toggle the Software Reset bit 2697 * 2698 */ 2699 2700 static int 2701 ata_software_reset( 2702 ata_ctl_t *ata_ctlp) 2703 { 2704 ddi_acc_handle_t io_hdl1 = ata_ctlp->ac_iohandle1; 2705 ddi_acc_handle_t io_hdl2 = ata_ctlp->ac_iohandle2; 2706 hrtime_t deadline; 2707 uint_t usecs_left; 2708 2709 ADBG_TRACE(("ata_reset_bus entered\n")); 2710 2711 /* disable interrupts and turn the software reset bit on */ 2712 ddi_put8(io_hdl2, ata_ctlp->ac_devctl, (ATDC_D3 | ATDC_SRST)); 2713 2714 /* why 30 milliseconds, the ATA/ATAPI-4 spec says 5 usec. */ 2715 drv_usecwait(30000); 2716 2717 /* turn the software reset bit back off */ 2718 ddi_put8(io_hdl2, ata_ctlp->ac_devctl, ATDC_D3); 2719 2720 /* 2721 * Wait for the controller to assert BUSY status. 2722 * I don't think 300 msecs is correct. The ATA/ATAPI-4 2723 * spec says 400 nsecs, (and 2 msecs if device 2724 * was in sleep mode; but we don't put drives to sleep 2725 * so it probably doesn't matter). 2726 */ 2727 drv_usecwait(300000); 2728 2729 /* 2730 * If drive 0 exists the test for completion is simple 2731 */ 2732 deadline = gethrtime() + ((hrtime_t)31 * NANOSEC); 2733 2734 if (CTL2DRV(ata_ctlp, 0, 0)) { 2735 goto wait_for_not_busy; 2736 } 2737 2738 ASSERT(CTL2DRV(ata_ctlp, 1, 0) != NULL); 2739 2740 /* 2741 * This must be a single device configuration, with drive 1 2742 * only. This complicates the test for completion because 2743 * issuing the software reset just caused drive 1 to 2744 * deselect. With drive 1 deselected, if I just read the 2745 * status register to test the BSY bit I get garbage, but 2746 * I can't re-select drive 1 until I'm certain the BSY bit 2747 * is de-asserted. Catch-22. 2748 * 2749 * In ATA/ATAPI-4, rev 15, section 9.16.2, it says to handle 2750 * this situation like this: 2751 */ 2752 2753 /* give up if the drive doesn't settle within 31 seconds */ 2754 while (gethrtime() < deadline) { 2755 /* 2756 * delay 10msec each time around the loop 2757 */ 2758 drv_usecwait(10000); 2759 2760 /* 2761 * try to select drive 1 2762 */ 2763 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, ATDH_DRIVE1); 2764 2765 ddi_put8(io_hdl1, ata_ctlp->ac_sect, 0x55); 2766 ddi_put8(io_hdl1, ata_ctlp->ac_sect, 0xaa); 2767 if (ddi_get8(io_hdl1, ata_ctlp->ac_sect) != 0xaa) 2768 continue; 2769 2770 ddi_put8(io_hdl1, ata_ctlp->ac_count, 0x55); 2771 ddi_put8(io_hdl1, ata_ctlp->ac_count, 0xaa); 2772 if (ddi_get8(io_hdl1, ata_ctlp->ac_count) != 0xaa) 2773 continue; 2774 2775 goto wait_for_not_busy; 2776 } 2777 return (FALSE); 2778 2779 wait_for_not_busy: 2780 2781 /* 2782 * Now wait up to 31 seconds for BUSY to clear. 2783 */ 2784 usecs_left = (deadline - gethrtime()) / 1000; 2785 (void) ata_wait3(io_hdl2, ata_ctlp->ac_ioaddr2, 0, ATS_BSY, 2786 ATS_ERR, ATS_BSY, ATS_DF, ATS_BSY, usecs_left); 2787 2788 return (TRUE); 2789 } 2790 2791 /* 2792 * 2793 * DDI interrupt handler 2794 * 2795 */ 2796 2797 static uint_t 2798 ata_intr( 2799 caddr_t arg) 2800 { 2801 ata_ctl_t *ata_ctlp; 2802 int one_shot = 1; 2803 2804 ata_ctlp = (ata_ctl_t *)arg; 2805 2806 return (ghd_intr(&ata_ctlp->ac_ccc, (void *)&one_shot)); 2807 } 2808 2809 2810 /* 2811 * 2812 * GHD ccc_get_status callback 2813 * 2814 */ 2815 2816 static int 2817 ata_get_status( 2818 void *hba_handle, 2819 void *intr_status) 2820 { 2821 ata_ctl_t *ata_ctlp = (ata_ctl_t *)hba_handle; 2822 uchar_t status; 2823 2824 ADBG_TRACE(("ata_get_status entered\n")); 2825 2826 /* 2827 * ignore interrupts before ata_attach completes 2828 */ 2829 if (!(ata_ctlp->ac_flags & AC_ATTACHED)) 2830 return (FALSE); 2831 2832 /* 2833 * can't be interrupt pending if nothing active 2834 */ 2835 switch (ata_ctlp->ac_state) { 2836 case AS_IDLE: 2837 return (FALSE); 2838 case AS_ACTIVE0: 2839 case AS_ACTIVE1: 2840 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2841 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2842 break; 2843 } 2844 2845 /* 2846 * If this is a PCI-IDE controller, check the PCI-IDE controller's 2847 * interrupt status latch. But don't clear it yet. 2848 * 2849 * AC_BMSTATREG_PIO_BROKEN flag is used currently for 2850 * CMD chips with device id 0x646. Since the interrupt bit on 2851 * Bus master IDE register is not usable when in PIO mode, 2852 * this chip is treated as a legacy device for interrupt 2853 * indication. The following code for CMD 2854 * chips may need to be revisited when we enable support for dma. 2855 * 2856 * CHANGE: DMA is not disabled for these devices. BM intr bit is 2857 * checked only if there was DMA used or BM intr is useable on PIO, 2858 * else treat it as before - as legacy device. 2859 */ 2860 2861 if ((ata_ctlp->ac_pciide) && 2862 ((ata_ctlp->ac_pciide_bm != FALSE) && 2863 ((ata_ctlp->ac_active_pktp->ap_pciide_dma == TRUE) || 2864 !(ata_ctlp->ac_flags & AC_BMSTATREG_PIO_BROKEN)))) { 2865 2866 if (!ata_pciide_status_pending(ata_ctlp)) 2867 return (FALSE); 2868 } else { 2869 /* 2870 * Interrupts from legacy ATA/IDE controllers are 2871 * edge-triggered but the dumb legacy ATA/IDE controllers 2872 * and drives don't have an interrupt status bit. 2873 * 2874 * Use a one_shot variable to make sure we only return 2875 * one status per interrupt. 2876 */ 2877 if (intr_status != NULL) { 2878 int *one_shot = (int *)intr_status; 2879 2880 if (*one_shot == 1) 2881 *one_shot = 0; 2882 else 2883 return (FALSE); 2884 } 2885 } 2886 2887 /* check if device is still busy */ 2888 2889 status = ddi_get8(ata_ctlp->ac_iohandle2, ata_ctlp->ac_altstatus); 2890 if (status & ATS_BSY) 2891 return (FALSE); 2892 return (TRUE); 2893 } 2894 2895 2896 /* 2897 * 2898 * get the current status and clear the IRQ 2899 * 2900 */ 2901 2902 int 2903 ata_get_status_clear_intr( 2904 ata_ctl_t *ata_ctlp, 2905 ata_pkt_t *ata_pktp) 2906 { 2907 uchar_t status; 2908 2909 /* 2910 * Here's where we clear the PCI-IDE interrupt latch. If this 2911 * request used DMA mode then we also have to check and clear 2912 * the DMA error latch at the same time. 2913 */ 2914 2915 if (ata_pktp->ap_pciide_dma) { 2916 if (ata_pciide_status_dmacheck_clear(ata_ctlp)) 2917 ata_pktp->ap_flags |= AP_ERROR | AP_TRAN_ERROR; 2918 } else if ((ata_ctlp->ac_pciide) && 2919 !(ata_ctlp->ac_flags & AC_BMSTATREG_PIO_BROKEN)) { 2920 /* 2921 * Some requests don't use DMA mode and therefore won't 2922 * set the DMA error latch, but we still have to clear 2923 * the interrupt latch. 2924 * Controllers with broken BM intr in PIO mode do not go 2925 * through this path. 2926 */ 2927 (void) ata_pciide_status_clear(ata_ctlp); 2928 } 2929 2930 /* 2931 * this clears the drive's interrupt 2932 */ 2933 status = ddi_get8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_status); 2934 ADBG_TRACE(("ata_get_status_clear_intr: 0x%x\n", status)); 2935 return (status); 2936 } 2937 2938 2939 2940 /* 2941 * 2942 * GHD interrupt handler 2943 * 2944 */ 2945 2946 /* ARGSUSED */ 2947 static void 2948 ata_process_intr( 2949 void *hba_handle, 2950 void *intr_status) 2951 { 2952 ata_ctl_t *ata_ctlp = (ata_ctl_t *)hba_handle; 2953 int watchdog; 2954 uchar_t fsm_func; 2955 int rc; 2956 2957 ADBG_TRACE(("ata_process_intr entered\n")); 2958 2959 /* 2960 * process the ATA or ATAPI interrupt 2961 */ 2962 2963 fsm_func = ATA_FSM_INTR; 2964 for (watchdog = ata_process_intr_watchdog; watchdog > 0; watchdog--) { 2965 rc = ata_ctlr_fsm(fsm_func, ata_ctlp, NULL, NULL, NULL); 2966 2967 switch (rc) { 2968 case ATA_FSM_RC_OKAY: 2969 return; 2970 2971 case ATA_FSM_RC_BUSY: /* wait for the next interrupt */ 2972 return; 2973 2974 case ATA_FSM_RC_INTR: /* re-invoke the FSM */ 2975 fsm_func = ATA_FSM_INTR; 2976 break; 2977 2978 case ATA_FSM_RC_FINI: /* move a request to done Q */ 2979 fsm_func = ATA_FSM_FINI; 2980 break; 2981 } 2982 } 2983 ADBG_WARN(("ata_process_intr: watchdog\n")); 2984 } 2985 2986 2987 2988 /* 2989 * 2990 * GHD ccc_hba_start callback 2991 * 2992 */ 2993 2994 static int 2995 ata_hba_start( 2996 void *hba_handle, 2997 gcmd_t *gcmdp) 2998 { 2999 ata_ctl_t *ata_ctlp; 3000 ata_drv_t *ata_drvp; 3001 ata_pkt_t *ata_pktp; 3002 uchar_t fsm_func; 3003 int request_started; 3004 int watchdog; 3005 3006 ADBG_TRACE(("ata_hba_start entered\n")); 3007 3008 ata_ctlp = (ata_ctl_t *)hba_handle; 3009 3010 if (ata_ctlp->ac_active_drvp != NULL) { 3011 ADBG_WARN(("ata_hba_start drvp not null\n")); 3012 return (FALSE); 3013 } 3014 if (ata_ctlp->ac_active_pktp != NULL) { 3015 ADBG_WARN(("ata_hba_start pktp not null\n")); 3016 return (FALSE); 3017 } 3018 3019 ata_pktp = GCMD2APKT(gcmdp); 3020 ata_drvp = GCMD2DRV(gcmdp); 3021 3022 /* 3023 * which drive? 3024 */ 3025 if (ata_drvp->ad_targ == 0) 3026 fsm_func = ATA_FSM_START0; 3027 else 3028 fsm_func = ATA_FSM_START1; 3029 3030 /* 3031 * start the request 3032 */ 3033 request_started = FALSE; 3034 for (watchdog = ata_hba_start_watchdog; watchdog > 0; watchdog--) { 3035 switch (ata_ctlr_fsm(fsm_func, ata_ctlp, ata_drvp, ata_pktp, 3036 NULL)) { 3037 case ATA_FSM_RC_OKAY: 3038 request_started = TRUE; 3039 goto fsm_done; 3040 3041 case ATA_FSM_RC_BUSY: 3042 /* if first time, tell GHD to requeue the request */ 3043 goto fsm_done; 3044 3045 case ATA_FSM_RC_INTR: 3046 /* 3047 * The start function polled for the next 3048 * bus phase, now fake an interrupt to process 3049 * the next action. 3050 */ 3051 request_started = TRUE; 3052 fsm_func = ATA_FSM_INTR; 3053 ata_drvp = NULL; 3054 ata_pktp = NULL; 3055 break; 3056 3057 case ATA_FSM_RC_FINI: /* move request to the done queue */ 3058 request_started = TRUE; 3059 fsm_func = ATA_FSM_FINI; 3060 ata_drvp = NULL; 3061 ata_pktp = NULL; 3062 break; 3063 } 3064 } 3065 ADBG_WARN(("ata_hba_start: watchdog\n")); 3066 3067 fsm_done: 3068 return (request_started); 3069 3070 } 3071 3072 static int 3073 ata_check_pciide_blacklist( 3074 dev_info_t *dip, 3075 uint_t flags) 3076 { 3077 ushort_t vendorid; 3078 ushort_t deviceid; 3079 pcibl_t *blp; 3080 int *propp; 3081 uint_t count; 3082 int rc; 3083 3084 3085 vendorid = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3086 DDI_PROP_DONTPASS, "vendor-id", 0); 3087 deviceid = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3088 DDI_PROP_DONTPASS, "device-id", 0); 3089 3090 /* 3091 * first check for a match in the "pci-ide-blacklist" property 3092 */ 3093 rc = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, 3094 "pci-ide-blacklist", &propp, &count); 3095 3096 if (rc == DDI_PROP_SUCCESS) { 3097 count = (count * sizeof (uint_t)) / sizeof (pcibl_t); 3098 blp = (pcibl_t *)propp; 3099 while (count--) { 3100 /* check for matching ID */ 3101 if ((vendorid & blp->b_vmask) 3102 != (blp->b_vendorid & blp->b_vmask)) { 3103 blp++; 3104 continue; 3105 } 3106 if ((deviceid & blp->b_dmask) 3107 != (blp->b_deviceid & blp->b_dmask)) { 3108 blp++; 3109 continue; 3110 } 3111 3112 /* got a match */ 3113 if (blp->b_flags & flags) { 3114 ddi_prop_free(propp); 3115 return (TRUE); 3116 } else { 3117 ddi_prop_free(propp); 3118 return (FALSE); 3119 } 3120 } 3121 ddi_prop_free(propp); 3122 } 3123 3124 /* 3125 * then check the built-in blacklist 3126 */ 3127 for (blp = ata_pciide_blacklist; blp->b_vendorid; blp++) { 3128 if ((vendorid & blp->b_vmask) != blp->b_vendorid) 3129 continue; 3130 if ((deviceid & blp->b_dmask) != blp->b_deviceid) 3131 continue; 3132 if (!(blp->b_flags & flags)) 3133 continue; 3134 return (TRUE); 3135 } 3136 return (FALSE); 3137 } 3138 3139 int 3140 ata_check_drive_blacklist( 3141 struct ata_id *aidp, 3142 uint_t flags) 3143 { 3144 atabl_t *blp; 3145 3146 for (blp = ata_drive_blacklist; blp->b_model; blp++) { 3147 if (!ata_strncmp(blp->b_model, aidp->ai_model, 3148 sizeof (aidp->ai_model))) 3149 continue; 3150 if (blp->b_flags & flags) 3151 return (TRUE); 3152 return (FALSE); 3153 } 3154 return (FALSE); 3155 } 3156 3157 /* 3158 * Queue a request to perform some sort of internally 3159 * generated command. When this request packet reaches 3160 * the front of the queue (*func)() is invoked. 3161 * 3162 */ 3163 3164 int 3165 ata_queue_cmd( 3166 int (*func)(ata_ctl_t *, ata_drv_t *, ata_pkt_t *), 3167 void *arg, 3168 ata_ctl_t *ata_ctlp, 3169 ata_drv_t *ata_drvp, 3170 gtgt_t *gtgtp) 3171 { 3172 ata_pkt_t *ata_pktp; 3173 gcmd_t *gcmdp; 3174 int rc; 3175 3176 if (!(gcmdp = ghd_gcmd_alloc(gtgtp, sizeof (*ata_pktp), TRUE))) { 3177 ADBG_ERROR(("atapi_id_update alloc failed\n")); 3178 return (FALSE); 3179 } 3180 3181 3182 /* set the back ptr from the ata_pkt to the gcmd_t */ 3183 ata_pktp = GCMD2APKT(gcmdp); 3184 ata_pktp->ap_gcmdp = gcmdp; 3185 ata_pktp->ap_hd = ata_drvp->ad_drive_bits; 3186 ata_pktp->ap_bytes_per_block = ata_drvp->ad_bytes_per_block; 3187 3188 /* 3189 * over-ride the default start function 3190 */ 3191 ata_pktp = GCMD2APKT(gcmdp); 3192 ata_pktp->ap_start = func; 3193 ata_pktp->ap_complete = NULL; 3194 ata_pktp->ap_v_addr = (caddr_t)arg; 3195 3196 /* 3197 * add it to the queue, when it gets to the front the 3198 * ap_start function is called. 3199 */ 3200 rc = ghd_transport(&ata_ctlp->ac_ccc, gcmdp, gcmdp->cmd_gtgtp, 3201 0, TRUE, NULL); 3202 3203 if (rc != TRAN_ACCEPT) { 3204 /* this should never, ever happen */ 3205 return (FALSE); 3206 } 3207 3208 if (ata_pktp->ap_flags & AP_ERROR) 3209 return (FALSE); 3210 return (TRUE); 3211 } 3212 3213 /* 3214 * Check if this drive has the "revert to defaults" bug 3215 * PSARC 2001/500 and 2001/xxx - check for the properties 3216 * ata-revert-to-defaults and atarvrt-<diskmodel> before 3217 * examining the blacklist. 3218 * <diskmodel> is made from the model number reported by Identify Drive 3219 * with uppercase letters converted to lowercase and all characters 3220 * except letters, digits, ".", "_", and "-" deleted. 3221 * Return value: 3222 * TRUE: enable revert to defaults 3223 * FALSE: disable revert to defaults 3224 * 3225 * NOTE: revert to power on defaults that includes reverting to MDMA 3226 * mode is allowed by ATA-6 & ATA-7 specs. 3227 * Therefore drives exhibiting this behaviour are not violating the spec. 3228 * Furthermore, the spec explicitly says that after the soft reset 3229 * host should check the current setting of the device features. 3230 * Correctly working BIOS would therefore reprogram either the drive 3231 * and/or the host controller to match transfer modes. 3232 * Devices with ATA_BL_NORVRT flag will be removed from 3233 * the ata_blacklist. 3234 * The default behaviour will be - no revert to power-on defaults 3235 * for all devices. The property is retained in case the user 3236 * explicitly requests revert-to-defaults before reboot. 3237 */ 3238 3239 #define ATA_REVERT_PROP_PREFIX "revert-" 3240 #define ATA_REVERT_PROP_GLOBAL "ata-revert-to-defaults" 3241 /* room for prefix + model number + terminating NUL character */ 3242 #define PROP_BUF_SIZE (sizeof (ATA_REVERT_PROP_PREFIX) + \ 3243 sizeof (aidp->ai_model) + 1) 3244 #define PROP_LEN_MAX (31) 3245 3246 static int 3247 ata_check_revert_to_defaults( 3248 ata_drv_t *ata_drvp) 3249 { 3250 struct ata_id *aidp = &ata_drvp->ad_id; 3251 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp; 3252 char prop_buf[PROP_BUF_SIZE]; 3253 int i, j; 3254 int propval; 3255 3256 /* put prefix into the buffer */ 3257 (void) strcpy(prop_buf, ATA_REVERT_PROP_PREFIX); 3258 j = strlen(prop_buf); 3259 3260 /* append the model number, leaving out invalid characters */ 3261 for (i = 0; i < sizeof (aidp->ai_model); ++i) { 3262 char c = aidp->ai_model[i]; 3263 if (c >= 'A' && c <= 'Z') /* uppercase -> lower */ 3264 c = c - 'A' + 'a'; 3265 if (c >= 'a' && c <= 'z' || c >= '0' && c <= '9' || 3266 c == '.' || c == '_' || c == '-') 3267 prop_buf[j++] = c; 3268 if (c == '\0') 3269 break; 3270 } 3271 3272 /* make sure there's a terminating NUL character */ 3273 if (j >= PROP_LEN_MAX) 3274 j = PROP_LEN_MAX; 3275 prop_buf[j] = '\0'; 3276 3277 /* look for a disk-specific "revert" property" */ 3278 propval = ddi_getprop(DDI_DEV_T_ANY, ata_ctlp->ac_dip, 3279 DDI_PROP_DONTPASS, prop_buf, -1); 3280 if (propval == 0) 3281 return (FALSE); 3282 else if (propval != -1) 3283 return (TRUE); 3284 3285 /* look for a global "revert" property" */ 3286 propval = ddi_getprop(DDI_DEV_T_ANY, ata_ctlp->ac_dip, 3287 0, ATA_REVERT_PROP_GLOBAL, -1); 3288 if (propval == 0) 3289 return (FALSE); 3290 else if (propval != -1) 3291 return (TRUE); 3292 3293 return (FALSE); 3294 } 3295 3296 void 3297 ata_show_transfer_mode(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp) 3298 { 3299 int i; 3300 3301 if (ata_ctlp->ac_pciide_bm == FALSE || 3302 ata_drvp->ad_pciide_dma != ATA_DMA_ON) { 3303 if (ata_cntrl_DMA_sel_msg) { 3304 ATAPRT(( 3305 "?\tATA DMA off: %s\n", ata_cntrl_DMA_sel_msg)); 3306 } else if (ata_dev_DMA_sel_msg) { 3307 ATAPRT(("?\tATA DMA off: %s\n", ata_dev_DMA_sel_msg)); 3308 } 3309 ATAPRT(("?\tPIO mode %d selected\n", 3310 (ata_drvp->ad_id.ai_advpiomode & ATAC_ADVPIO_4_SUP) == 3311 ATAC_ADVPIO_4_SUP ? 4 : 3)); 3312 } else { 3313 /* Using DMA */ 3314 if (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_SEL_MASK) { 3315 /* 3316 * Rely on the fact that either dwdma or udma is 3317 * selected, not both. 3318 */ 3319 ATAPRT(("?\tMultiwordDMA mode %d selected\n", 3320 (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_2_SEL) == 3321 ATAC_MDMA_2_SEL ? 2 : 3322 (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_1_SEL) == 3323 ATAC_MDMA_1_SEL ? 1 : 0)); 3324 } else { 3325 for (i = 0; i <= 6; i++) { 3326 if (ata_drvp->ad_id.ai_ultradma & 3327 (1 << (i + 8))) { 3328 ATAPRT(( 3329 "?\tUltraDMA mode %d selected\n", 3330 i)); 3331 break; 3332 } 3333 } 3334 } 3335 } 3336 } 3337 3338 /* 3339 * Controller-specific operation pointers. 3340 * Should be extended as needed - init only for now 3341 */ 3342 struct ata_ctl_spec_ops { 3343 uint_t (*cs_init)(dev_info_t *, ushort_t, ushort_t); /* ctlr init */ 3344 }; 3345 3346 3347 struct ata_ctl_spec { 3348 ushort_t cs_vendor_id; 3349 ushort_t cs_device_id; 3350 struct ata_ctl_spec_ops *cs_ops; 3351 }; 3352 3353 /* Sil3XXX-specific functions (init only for now) */ 3354 struct ata_ctl_spec_ops sil3xxx_ops = { 3355 &sil3xxx_init_controller /* Sil3XXX cntrl initialization */ 3356 }; 3357 3358 3359 struct ata_ctl_spec ata_cntrls_spec[] = { 3360 {0x1095, 0x3114, &sil3xxx_ops}, 3361 {0x1095, 0x3512, &sil3xxx_ops}, 3362 {0x1095, 0x3112, &sil3xxx_ops}, 3363 {0, 0, NULL} /* List must end with cs_ops set to NULL */ 3364 }; 3365 3366 /* 3367 * Do controller specific initialization if necessary. 3368 * Pick-up controller specific functions. 3369 */ 3370 3371 int 3372 ata_spec_init_controller(dev_info_t *dip) 3373 { 3374 ushort_t vendor_id; 3375 ushort_t device_id; 3376 struct ata_ctl_spec *ctlsp; 3377 3378 vendor_id = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3379 DDI_PROP_DONTPASS, "vendor-id", 0); 3380 device_id = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3381 DDI_PROP_DONTPASS, "device-id", 0); 3382 3383 /* Locate controller specific ops, if they exist */ 3384 ctlsp = ata_cntrls_spec; 3385 while (ctlsp->cs_ops != NULL) { 3386 if (ctlsp->cs_vendor_id == vendor_id && 3387 ctlsp->cs_device_id == device_id) 3388 break; 3389 ctlsp++; 3390 } 3391 3392 if (ctlsp->cs_ops != NULL) { 3393 if (ctlsp->cs_ops->cs_init != NULL) { 3394 /* Initialize controller */ 3395 if ((*(ctlsp->cs_ops->cs_init)) 3396 (dip, vendor_id, device_id) != TRUE) { 3397 cmn_err(CE_WARN, 3398 "pci%4x,%4x cntrl specific " 3399 "initialization failed", 3400 vendor_id, device_id); 3401 return (FALSE); 3402 } 3403 } 3404 } 3405 return (TRUE); 3406 } 3407 3408 /* 3409 * this routine works like ddi_prop_get_int, except that it works on 3410 * a string property that contains ascii representations 3411 * of an integer. 3412 * If the property is not found, the default value is returned. 3413 */ 3414 static int 3415 ata_prop_lookup_int(dev_t match_dev, dev_info_t *dip, 3416 uint_t flags, char *name, int defvalue) 3417 { 3418 3419 char *bufp, *cp; 3420 int rc = defvalue; 3421 int proprc; 3422 3423 proprc = ddi_prop_lookup_string(match_dev, dip, 3424 flags, name, &bufp); 3425 3426 if (proprc == DDI_PROP_SUCCESS) { 3427 cp = bufp; 3428 rc = stoi(&cp); 3429 ddi_prop_free(bufp); 3430 } else { 3431 /* 3432 * see if property is encoded as an int instead of string. 3433 */ 3434 rc = ddi_prop_get_int(match_dev, dip, flags, name, defvalue); 3435 } 3436 3437 return (rc); 3438 } 3439 3440 /* 3441 * Initialize the power management components 3442 */ 3443 static void 3444 ata_init_pm(dev_info_t *dip) 3445 { 3446 char pmc_name[16]; 3447 char *pmc[] = { 3448 NULL, 3449 "0=Sleep (PCI D3 State)", 3450 "3=PowerOn (PCI D0 State)", 3451 NULL 3452 }; 3453 int instance; 3454 ata_ctl_t *ata_ctlp; 3455 3456 3457 instance = ddi_get_instance(dip); 3458 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3459 ata_ctlp->ac_pm_support = 0; 3460 3461 /* check PCI capabilities */ 3462 if (!ata_is_pci(dip)) 3463 return; 3464 3465 (void) sprintf(pmc_name, "NAME=ata%d", instance); 3466 pmc[0] = pmc_name; 3467 3468 #ifdef ATA_USE_AUTOPM 3469 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, dip, 3470 "pm-components", pmc, 3) != DDI_PROP_SUCCESS) { 3471 return; 3472 } 3473 #endif 3474 3475 ata_ctlp->ac_pm_support = 1; 3476 ata_ctlp->ac_pm_level = PM_LEVEL_D0; 3477 3478 ATA_BUSY_COMPONENT(dip, 0); 3479 if (ATA_RAISE_POWER(dip, 0, PM_LEVEL_D0) != DDI_SUCCESS) { 3480 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "pm-components"); 3481 } 3482 ATA_IDLE_COMPONENT(dip, 0); 3483 } 3484 3485 /* 3486 * resume the hard drive 3487 */ 3488 static void 3489 ata_resume_drive(ata_drv_t *ata_drvp) 3490 { 3491 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp; 3492 int drive_type; 3493 struct ata_id id; 3494 3495 ADBG_TRACE(("ata_resume_drive entered\n")); 3496 3497 drive_type = ata_drive_type(ata_drvp->ad_drive_bits, 3498 ata_ctlp->ac_iohandle1, ata_ctlp->ac_ioaddr1, 3499 ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2, 3500 &id); 3501 if (drive_type == ATA_DEV_NONE) 3502 return; 3503 3504 if (!ATAPIDRV(ata_drvp)) { 3505 /* Reset Ultra DMA mode */ 3506 (void) ata_set_dma_mode(ata_ctlp, ata_drvp); 3507 if (!ata_disk_setup_parms(ata_ctlp, ata_drvp)) 3508 return; 3509 } else { 3510 (void) atapi_init_drive(ata_drvp); 3511 } 3512 (void) ata_set_feature(ata_ctlp, ata_drvp, ATSF_DIS_REVPOD, 0); 3513 3514 } 3515 3516 /* 3517 * resume routine, it will be run when get the command 3518 * DDI_RESUME at attach(9E) from system power management 3519 */ 3520 static int 3521 ata_resume(dev_info_t *dip) 3522 { 3523 int instance; 3524 ata_ctl_t *ata_ctlp; 3525 ddi_acc_handle_t io_hdl2; 3526 caddr_t ioaddr2; 3527 3528 instance = ddi_get_instance(dip); 3529 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3530 3531 if (!ata_ctlp->ac_pm_support) 3532 return (DDI_FAILURE); 3533 if (ata_ctlp->ac_pm_level == PM_LEVEL_D0) 3534 return (DDI_SUCCESS); 3535 3536 ATA_BUSY_COMPONENT(dip, 0); 3537 if (ATA_RAISE_POWER(dip, 0, PM_LEVEL_D0) == DDI_FAILURE) 3538 return (DDI_FAILURE); 3539 ATA_IDLE_COMPONENT(dip, 0); 3540 3541 /* enable interrupts from the device */ 3542 io_hdl2 = ata_ctlp->ac_iohandle2; 3543 ioaddr2 = ata_ctlp->ac_ioaddr2; 3544 ddi_put8(io_hdl2, (uchar_t *)ioaddr2 + AT_DEVCTL, ATDC_D3); 3545 ata_ctlp->ac_pm_level = PM_LEVEL_D0; 3546 3547 return (DDI_SUCCESS); 3548 } 3549 3550 /* 3551 * suspend routine, it will be run when get the command 3552 * DDI_SUSPEND at detach(9E) from system power management 3553 */ 3554 static int 3555 ata_suspend(dev_info_t *dip) 3556 { 3557 int instance; 3558 ata_ctl_t *ata_ctlp; 3559 ddi_acc_handle_t io_hdl2; 3560 3561 instance = ddi_get_instance(dip); 3562 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3563 3564 if (!ata_ctlp->ac_pm_support) 3565 return (DDI_FAILURE); 3566 if (ata_ctlp->ac_pm_level == PM_LEVEL_D3) 3567 return (DDI_SUCCESS); 3568 3569 /* disable interrupts and turn the software reset bit on */ 3570 io_hdl2 = ata_ctlp->ac_iohandle2; 3571 ddi_put8(io_hdl2, ata_ctlp->ac_devctl, (ATDC_D3 | ATDC_SRST)); 3572 3573 (void) ata_reset_bus(ata_ctlp); 3574 (void) ata_change_power(dip, ATC_SLEEP); 3575 ata_ctlp->ac_pm_level = PM_LEVEL_D3; 3576 return (DDI_SUCCESS); 3577 } 3578 3579 int ata_save_pci_config = 0; 3580 /* 3581 * ata specific power management entry point, it was 3582 * used to change the power management component 3583 */ 3584 static int 3585 ata_power(dev_info_t *dip, int component, int level) 3586 { 3587 int instance; 3588 ata_ctl_t *ata_ctlp; 3589 uint8_t cmd; 3590 3591 ADBG_TRACE(("ata_power entered, component = %d, level = %d\n", 3592 component, level)); 3593 3594 instance = ddi_get_instance(dip); 3595 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3596 if (ata_ctlp == NULL || component != 0) 3597 return (DDI_FAILURE); 3598 3599 if (!ata_ctlp->ac_pm_support) 3600 return (DDI_FAILURE); 3601 3602 switch (level) { 3603 case PM_LEVEL_D0: 3604 if (ata_save_pci_config) 3605 (void) pci_restore_config_regs(dip); 3606 ata_ctlp->ac_pm_level = PM_LEVEL_D0; 3607 cmd = ATC_IDLE_IMMED; 3608 break; 3609 case PM_LEVEL_D3: 3610 if (ata_save_pci_config) 3611 (void) pci_save_config_regs(dip); 3612 ata_ctlp->ac_pm_level = PM_LEVEL_D3; 3613 cmd = ATC_SLEEP; 3614 break; 3615 default: 3616 return (DDI_FAILURE); 3617 } 3618 return (ata_change_power(dip, cmd)); 3619 } 3620 3621 /* 3622 * sent commands to ata controller to change the power level 3623 */ 3624 static int 3625 ata_change_power(dev_info_t *dip, uint8_t cmd) 3626 { 3627 int instance; 3628 ata_ctl_t *ata_ctlp; 3629 ata_drv_t *ata_drvp; 3630 uchar_t targ; 3631 struct ata_id id; 3632 uchar_t lun; 3633 uchar_t lastlun; 3634 3635 ADBG_TRACE(("ata_change_power entered, cmd = %d\n", cmd)); 3636 3637 instance = ddi_get_instance(dip); 3638 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3639 /* 3640 * Issue command on each disk device on the bus. 3641 */ 3642 if (cmd == ATC_SLEEP) { 3643 for (targ = 0; targ < ATA_MAXTARG; targ++) { 3644 ata_drvp = CTL2DRV(ata_ctlp, targ, 0); 3645 if (ata_drvp == NULL) 3646 continue; 3647 if (ata_drive_type(ata_drvp->ad_drive_bits, 3648 ata_ctlp->ac_iohandle1, ata_ctlp->ac_ioaddr1, 3649 ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2, 3650 &id) != ATA_DEV_DISK) 3651 continue; 3652 (void) ata_flush_cache(ata_ctlp, ata_drvp); 3653 if (!ata_command(ata_ctlp, ata_drvp, TRUE, TRUE, 3654 5 * 1000000, cmd, 0, 0, 0, 0, 0, 0)) { 3655 cmn_err(CE_WARN, "!ata_controller - Can not " 3656 "put drive %d in to power mode %u", 3657 targ, cmd); 3658 (void) ata_devo_reset(dip, DDI_RESET_FORCE); 3659 return (DDI_FAILURE); 3660 } 3661 } 3662 return (DDI_SUCCESS); 3663 } 3664 3665 (void) ata_software_reset(ata_ctlp); 3666 for (targ = 0; targ < ATA_MAXTARG; targ++) { 3667 ata_drvp = CTL2DRV(ata_ctlp, targ, 0); 3668 if (ata_drvp == NULL) 3669 continue; 3670 ata_resume_drive(ata_drvp); 3671 3672 if (ATAPIDRV(ata_drvp)) 3673 lastlun = ata_drvp->ad_id.ai_lastlun; 3674 else 3675 lastlun = 0; 3676 if (!ata_enable_atapi_luns) 3677 lastlun = 0; 3678 for (lun = 1; lun <= lastlun && lun < ATA_MAXLUN; lun++) { 3679 ata_drvp = CTL2DRV(ata_ctlp, targ, lun); 3680 if (ata_drvp != NULL) 3681 ata_resume_drive(ata_drvp); 3682 } 3683 } 3684 3685 return (DDI_SUCCESS); 3686 } 3687 3688 /* 3689 * return 1 when ata controller is a pci device, 3690 * otherwise return 0 3691 */ 3692 static int 3693 ata_is_pci(dev_info_t *dip) 3694 { 3695 int rc; 3696 char *bufp; 3697 int ispci; 3698 3699 rc = ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_get_parent(dip), 3700 DDI_PROP_DONTPASS, "device_type", &bufp); 3701 3702 if (rc != DDI_PROP_SUCCESS) { 3703 ADBG_ERROR(("ata_is_pci !device_type\n")); 3704 return (0); 3705 } 3706 3707 ispci = (strcmp(bufp, "pci-ide") == 0); 3708 3709 ddi_prop_free(bufp); 3710 3711 return (ispci); 3712 } 3713 3714 /* 3715 * Disable DMA for this drive 3716 */ 3717 static void 3718 ata_disable_DMA(ata_drv_t *ata_drvp) 3719 { 3720 struct ata_id *aidp; 3721 char buf[sizeof (aidp->ai_model) +2]; 3722 int i; 3723 3724 if (ata_drvp == NULL) 3725 return; 3726 3727 if (ata_drvp->ad_pciide_dma == ATA_DMA_OFF) 3728 return; 3729 3730 ata_drvp->ad_pciide_dma = ATA_DMA_OFF; 3731 3732 /* Print the message */ 3733 buf[0] = '\0'; 3734 aidp = &ata_drvp->ad_id; 3735 if (aidp != NULL) { 3736 (void) strncpy(buf, aidp->ai_model, sizeof (aidp->ai_model)); 3737 buf[sizeof (aidp->ai_model) -1] = '\0'; 3738 for (i = sizeof (aidp->ai_model) - 2; buf[i] == ' '; i--) 3739 buf[i] = '\0'; 3740 } 3741 cmn_err(CE_CONT, 3742 "?DMA disabled on %s target=%d, lun=%d due to DMA errors,", 3743 buf, ata_drvp->ad_targ, ata_drvp->ad_lun); 3744 cmn_err(CE_CONT, "?most likely due to the CF-to-IDE adapter."); 3745 } 3746 3747 /* 3748 * Check and select DMA mode 3749 * 3750 * TRUE is returned when set feature is called successfully, 3751 * otherwise return FALSE 3752 */ 3753 int 3754 ata_set_dma_mode(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp) 3755 { 3756 struct ata_id *aidp; 3757 int mode, rval = FALSE; 3758 uint8_t subcmd; 3759 3760 aidp = &ata_drvp->ad_id; 3761 3762 /* Return directly if DMA is not supported */ 3763 if (!(aidp->ai_cap & ATAC_DMA_SUPPORT)) 3764 return (rval); 3765 3766 /* First check Ultra DMA mode if no DMA is selected */ 3767 if ((aidp->ai_validinfo & ATAC_VALIDINFO_83) && 3768 (aidp->ai_ultradma & ATAC_UDMA_SUP_MASK)) { 3769 for (mode = 6; mode >= 0; --mode) { 3770 if (aidp->ai_ultradma & (1 << mode)) 3771 break; 3772 } 3773 subcmd = ATF_XFRMOD_UDMA; 3774 3775 } else if (aidp->ai_dworddma & ATAC_MDMA_SUP_MASK) { 3776 /* Then check multi-word DMA mode */ 3777 for (mode = 2; mode >= 0; --mode) { 3778 if (aidp->ai_dworddma & (1 << mode)) 3779 break; 3780 } 3781 subcmd = ATF_XFRMOD_MDMA; 3782 3783 } else { 3784 return (rval); 3785 } 3786 3787 rval = ata_set_feature(ata_ctlp, ata_drvp, ATSF_SET_XFRMOD, 3788 subcmd|mode); 3789 3790 return (rval); 3791 } 3792