1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/modctl.h> 31 #include <sys/debug.h> 32 #include <sys/promif.h> 33 #include <sys/pci.h> 34 #include <sys/errno.h> 35 #include <sys/open.h> 36 #include <sys/uio.h> 37 #include <sys/cred.h> 38 #include <sys/cpu.h> 39 #include "ata_common.h" 40 #include "ata_disk.h" 41 #include "atapi.h" 42 #include "ata_blacklist.h" 43 #include "sil3xxx.h" 44 45 /* 46 * Solaris Entry Points. 47 */ 48 49 static int ata_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 50 static int ata_detach(dev_info_t *dip, ddi_detach_cmd_t cmd); 51 static int ata_bus_ctl(dev_info_t *d, dev_info_t *r, ddi_ctl_enum_t o, 52 void *a, void *v); 53 static uint_t ata_intr(caddr_t arg); 54 55 /* 56 * GHD Entry points 57 */ 58 59 static int ata_get_status(void *hba_handle, void *intr_status); 60 static void ata_process_intr(void *hba_handle, void *intr_status); 61 static int ata_hba_start(void *handle, gcmd_t *gcmdp); 62 static void ata_hba_complete(void *handle, gcmd_t *gcmdp, int do_callback); 63 static int ata_timeout_func(void *hba_handle, gcmd_t *gcmdp, 64 gtgt_t *gtgtp, gact_t action, int calltype); 65 66 /* 67 * Local Function Prototypes 68 */ 69 static int ata_prop_lookup_int(dev_t match_dev, dev_info_t *dip, 70 uint_t flags, char *name, int defvalue); 71 static int ata_ctlr_fsm(uchar_t fsm_func, ata_ctl_t *ata_ctlp, 72 ata_drv_t *ata_drvp, ata_pkt_t *ata_pktp, 73 int *DoneFlgp); 74 static void ata_destroy_controller(dev_info_t *dip); 75 static int ata_drive_type(uchar_t drvhd, 76 ddi_acc_handle_t io_hdl1, caddr_t ioaddr1, 77 ddi_acc_handle_t io_hdl2, caddr_t ioaddr2, 78 struct ata_id *ata_id_bufp); 79 static ata_ctl_t *ata_init_controller(dev_info_t *dip); 80 static ata_drv_t *ata_init_drive(ata_ctl_t *ata_ctlp, 81 uchar_t targ, uchar_t lun); 82 static int ata_init_drive_pcidma(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 83 dev_info_t *tdip); 84 static int ata_flush_cache(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp); 85 static void ata_init_pciide(dev_info_t *dip, ata_ctl_t *ata_ctlp); 86 static int ata_reset_bus(ata_ctl_t *ata_ctlp); 87 static int ata_setup_ioaddr(dev_info_t *dip, 88 ddi_acc_handle_t *iohandle1, caddr_t *ioaddr1p, 89 ddi_acc_handle_t *iohandle2, caddr_t *ioaddr2p, 90 ddi_acc_handle_t *bm_hdlp, caddr_t *bm_addrp); 91 static int ata_software_reset(ata_ctl_t *ata_ctlp); 92 static int ata_start_arq(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 93 ata_pkt_t *ata_pktp); 94 static int ata_strncmp(char *p1, char *p2, int cnt); 95 static void ata_uninit_drive(ata_drv_t *ata_drvp); 96 97 static int ata_check_pciide_blacklist(dev_info_t *dip, uint_t flags); 98 static int ata_check_revert_to_defaults(ata_drv_t *ata_drvp); 99 static void ata_show_transfer_mode(ata_ctl_t *, ata_drv_t *); 100 static int ata_spec_init_controller(dev_info_t *dip); 101 102 static void ata_init_pm(dev_info_t *); 103 static int ata_suspend(dev_info_t *); 104 static int ata_resume(dev_info_t *); 105 static int ata_power(dev_info_t *, int, int); 106 static int ata_change_power(dev_info_t *, uint8_t); 107 static int ata_is_pci(dev_info_t *); 108 static void ata_disable_DMA(ata_drv_t *ata_drvp); 109 110 /* 111 * Local static data 112 */ 113 static void *ata_state; 114 115 static tmr_t ata_timer_conf; /* single timeout list for all instances */ 116 static int ata_watchdog_usec = 100000; /* check timeouts every 100 ms */ 117 118 int ata_hba_start_watchdog = 1000; 119 int ata_process_intr_watchdog = 1000; 120 int ata_reset_bus_watchdog = 1000; 121 122 123 /* 124 * Use local or framework power management 125 */ 126 127 #ifdef ATA_USE_AUTOPM 128 #define ATA_BUSY_COMPONENT(d, c) ((void)pm_busy_component(d, c)) 129 #define ATA_IDLE_COMPONENT(d, c) ((void)pm_idle_component(d, c)) 130 #define ATA_RAISE_POWER(d, c, l) pm_raise_power(d, c, l) 131 #define ATA_LOWER_POWER(d, c, l) pm_lower_power(d, c, l) 132 #else 133 #define ATA_BUSY_COMPONENT(d, c) 134 #define ATA_IDLE_COMPONENT(d, c) 135 #define ATA_RAISE_POWER(d, c, l) ata_power(d, c, l) 136 #define ATA_LOWER_POWER(d, c, l) ata_power(d, c, l) 137 #endif 138 /* 139 * number of seconds to wait during various operations 140 */ 141 int ata_flush_delay = 5 * 1000000; 142 uint_t ata_set_feature_wait = 4 * 1000000; 143 uint_t ata_flush_cache_wait = 60 * 1000000; /* may take a long time */ 144 145 /* 146 * Change this for SFF-8070i support. Currently SFF-8070i is 147 * using a field in the IDENTIFY PACKET DEVICE response which 148 * already seems to be in use by some vendor's drives. I suspect 149 * SFF will either move their laslun field or provide a reliable 150 * way to validate it. 151 */ 152 int ata_enable_atapi_luns = FALSE; 153 154 /* 155 * set this to disable all DMA requests 156 */ 157 int ata_dma_disabled = FALSE; 158 159 /* 160 * set this to TRUE to enable storing the IDENTIFY DEVICE result in the 161 * "ata" or "atapi" property. 162 */ 163 int ata_id_debug = FALSE; 164 165 /* 166 * set this to TRUE to enable logging device-capability data 167 */ 168 int ata_capability_data = FALSE; 169 170 /* 171 * DMA selection message pointers 172 */ 173 char *ata_cntrl_DMA_sel_msg; 174 char *ata_dev_DMA_sel_msg; 175 176 /* 177 * bus nexus operations 178 */ 179 static struct bus_ops ata_bus_ops; 180 static struct bus_ops *scsa_bus_ops_p; 181 182 /* ARGSUSED */ 183 static int 184 ata_open(dev_t *devp, int flag, int otyp, cred_t *cred_p) 185 { 186 if (ddi_get_soft_state(ata_state, getminor(*devp)) == NULL) 187 return (ENXIO); 188 189 return (0); 190 } 191 192 /* 193 * The purpose of this function is to pass the ioaddress of the controller 194 * to the caller, specifically used for upgrade from pre-pciide 195 * to pciide nodes 196 */ 197 /* ARGSUSED */ 198 static int 199 ata_read(dev_t dev, struct uio *uio_p, cred_t *cred_p) 200 { 201 ata_ctl_t *ata_ctlp; 202 char buf[18]; 203 long len; 204 205 ata_ctlp = ddi_get_soft_state(ata_state, getminor(dev)); 206 207 if (ata_ctlp == NULL) 208 return (ENXIO); 209 210 (void) sprintf(buf, "%p\n", (void *) ata_ctlp->ac_ioaddr1); 211 212 len = strlen(buf) - uio_p->uio_offset; 213 len = min(uio_p->uio_resid, len); 214 if (len <= 0) 215 return (0); 216 217 return (uiomove((caddr_t)(buf + uio_p->uio_offset), len, 218 UIO_READ, uio_p)); 219 } 220 221 int 222 ata_devo_reset( 223 dev_info_t *dip, 224 ddi_reset_cmd_t cmd) 225 { 226 ata_ctl_t *ata_ctlp; 227 ata_drv_t *ata_drvp; 228 int instance; 229 int i; 230 int rc; 231 int flush_okay; 232 233 if (cmd != DDI_RESET_FORCE) 234 return (0); 235 236 instance = ddi_get_instance(dip); 237 ata_ctlp = ddi_get_soft_state(ata_state, instance); 238 239 if (!ata_ctlp) 240 return (0); 241 242 /* 243 * reset ATA drives and flush the write cache of any drives 244 */ 245 flush_okay = TRUE; 246 for (i = 0; i < ATA_MAXTARG; i++) { 247 if ((ata_drvp = CTL2DRV(ata_ctlp, i, 0)) == 0) 248 continue; 249 /* Don't revert to defaults for certain IBM drives */ 250 if ((ata_drvp->ad_flags & AD_DISK) != 0 && 251 ((ata_drvp->ad_flags & AD_NORVRT) == 0)) { 252 /* Enable revert to defaults when reset */ 253 (void) ata_set_feature(ata_ctlp, ata_drvp, 254 ATSF_ENA_REVPOD, 0); 255 } 256 257 /* 258 * skip flush cache if device type is cdrom 259 * 260 * notes: the structure definitions for ata_drvp->ad_id are 261 * defined for the ATA IDENTIFY_DEVICE, but if AD_ATAPI is set 262 * the struct holds data for the ATAPI IDENTIFY_PACKET_DEVICE 263 */ 264 if (!IS_CDROM(ata_drvp)) { 265 266 /* 267 * Try the ATA/ATAPI flush write cache command 268 */ 269 rc = ata_flush_cache(ata_ctlp, ata_drvp); 270 ADBG_WARN(("ata_flush_cache %s\n", 271 rc ? "okay" : "failed")); 272 273 if (!rc) 274 flush_okay = FALSE; 275 } 276 277 278 /* 279 * do something else if flush cache not supported 280 */ 281 } 282 283 /* 284 * just busy wait if any drive doesn't support FLUSH CACHE 285 */ 286 if (!flush_okay) 287 drv_usecwait(ata_flush_delay); 288 return (0); 289 } 290 291 292 static struct cb_ops ata_cb_ops = { 293 ata_open, /* open */ 294 nulldev, /* close */ 295 nodev, /* strategy */ 296 nodev, /* print */ 297 nodev, /* dump */ 298 ata_read, /* read */ 299 nodev, /* write */ 300 nodev, /* ioctl */ 301 nodev, /* devmap */ 302 nodev, /* mmap */ 303 nodev, /* segmap */ 304 nochpoll, /* chpoll */ 305 ddi_prop_op, /* prop_op */ 306 NULL, /* stream info */ 307 D_MP, /* driver compatibility flag */ 308 CB_REV, /* cb_ops revision */ 309 nodev, /* aread */ 310 nodev /* awrite */ 311 }; 312 313 static struct dev_ops ata_ops = { 314 DEVO_REV, /* devo_rev, */ 315 0, /* refcnt */ 316 ddi_getinfo_1to1, /* info */ 317 nulldev, /* identify */ 318 NULL, /* probe */ 319 ata_attach, /* attach */ 320 ata_detach, /* detach */ 321 ata_devo_reset, /* reset */ 322 &ata_cb_ops, /* driver operations */ 323 NULL, /* bus operations */ 324 ata_power /* power */ 325 }; 326 327 /* driver loadable module wrapper */ 328 static struct modldrv modldrv = { 329 &mod_driverops, /* Type of module. This one is a driver */ 330 "ATA AT-bus attachment disk controller Driver", /* module name */ 331 &ata_ops, /* driver ops */ 332 }; 333 334 static struct modlinkage modlinkage = { 335 MODREV_1, (void *)&modldrv, NULL 336 }; 337 338 #ifdef ATA_DEBUG 339 int ata_debug_init = FALSE; 340 int ata_debug_attach = FALSE; 341 342 int ata_debug = ADBG_FLAG_ERROR 343 /* | ADBG_FLAG_ARQ */ 344 /* | ADBG_FLAG_INIT */ 345 /* | ADBG_FLAG_TRACE */ 346 /* | ADBG_FLAG_TRANSPORT */ 347 /* | ADBG_FLAG_WARN */ 348 ; 349 #endif 350 351 int 352 _init(void) 353 { 354 int err; 355 356 #ifdef ATA_DEBUG 357 if (ata_debug_init) 358 debug_enter("\nATA _INIT\n"); 359 #endif 360 361 if ((err = ddi_soft_state_init(&ata_state, sizeof (ata_ctl_t), 0)) != 0) 362 return (err); 363 364 if ((err = scsi_hba_init(&modlinkage)) != 0) { 365 ddi_soft_state_fini(&ata_state); 366 return (err); 367 } 368 369 /* save pointer to SCSA provided bus_ops struct */ 370 scsa_bus_ops_p = ata_ops.devo_bus_ops; 371 372 /* make a copy of SCSA bus_ops */ 373 ata_bus_ops = *(ata_ops.devo_bus_ops); 374 375 /* 376 * Modify our bus_ops to call our routines. Our implementation 377 * will determine if the device is ATA or ATAPI/SCSA and react 378 * accordingly. 379 */ 380 ata_bus_ops.bus_ctl = ata_bus_ctl; 381 382 /* patch our bus_ops into the dev_ops struct */ 383 ata_ops.devo_bus_ops = &ata_bus_ops; 384 385 if ((err = mod_install(&modlinkage)) != 0) { 386 scsi_hba_fini(&modlinkage); 387 ddi_soft_state_fini(&ata_state); 388 } 389 390 /* 391 * Initialize the per driver timer info. 392 */ 393 394 ghd_timer_init(&ata_timer_conf, drv_usectohz(ata_watchdog_usec)); 395 396 return (err); 397 } 398 399 int 400 _fini(void) 401 { 402 int err; 403 404 if ((err = mod_remove(&modlinkage)) == 0) { 405 ghd_timer_fini(&ata_timer_conf); 406 scsi_hba_fini(&modlinkage); 407 ddi_soft_state_fini(&ata_state); 408 } 409 410 return (err); 411 } 412 413 int 414 _info(struct modinfo *modinfop) 415 { 416 return (mod_info(&modlinkage, modinfop)); 417 } 418 419 420 /* 421 * 422 * driver attach entry point 423 * 424 */ 425 426 static int 427 ata_attach( 428 dev_info_t *dip, 429 ddi_attach_cmd_t cmd) 430 { 431 ata_ctl_t *ata_ctlp; 432 ata_drv_t *ata_drvp; 433 ata_drv_t *first_drvp = NULL; 434 uchar_t targ; 435 uchar_t lun; 436 uchar_t lastlun; 437 int atapi_count = 0; 438 int disk_count = 0; 439 440 ADBG_TRACE(("ata_attach entered\n")); 441 #ifdef ATA_DEBUG 442 if (ata_debug_attach) 443 debug_enter("\nATA_ATTACH\n\n"); 444 #endif 445 446 switch (cmd) { 447 case DDI_ATTACH: 448 break; 449 case DDI_RESUME: 450 return (ata_resume(dip)); 451 default: 452 return (DDI_FAILURE); 453 } 454 455 /* initialize controller */ 456 ata_ctlp = ata_init_controller(dip); 457 458 if (ata_ctlp == NULL) 459 goto errout; 460 461 mutex_enter(&ata_ctlp->ac_ccc.ccc_hba_mutex); 462 463 /* initialize drives */ 464 465 for (targ = 0; targ < ATA_MAXTARG; targ++) { 466 467 ata_drvp = ata_init_drive(ata_ctlp, targ, 0); 468 if (ata_drvp == NULL) 469 continue; 470 471 if (first_drvp == NULL) 472 first_drvp = ata_drvp; 473 474 if (ATAPIDRV(ata_drvp)) { 475 atapi_count++; 476 lastlun = ata_drvp->ad_id.ai_lastlun; 477 } else { 478 disk_count++; 479 lastlun = 0; 480 } 481 482 /* 483 * LUN support is currently disabled. Check with SFF-8070i 484 * before enabling. 485 */ 486 if (!ata_enable_atapi_luns) 487 lastlun = 0; 488 489 /* Initialize higher LUNs, if there are any */ 490 for (lun = 1; lun <= lastlun && lun < ATA_MAXLUN; lun++) { 491 if ((ata_drvp = 492 ata_init_drive(ata_ctlp, targ, lun)) != NULL) { 493 ata_show_transfer_mode(ata_ctlp, ata_drvp); 494 } 495 } 496 } 497 498 if ((atapi_count == 0) && (disk_count == 0)) { 499 ADBG_WARN(("ata_attach: no drives detected\n")); 500 goto errout1; 501 } 502 503 /* 504 * Always make certain that a valid drive is selected so 505 * that routines which poll the status register don't get 506 * confused by non-existent drives. 507 */ 508 ddi_put8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_drvhd, 509 first_drvp->ad_drive_bits); 510 ata_nsecwait(400); 511 512 /* 513 * make certain the drive selected 514 */ 515 if (!ata_wait(ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2, 516 0, ATS_BSY, 5000000)) { 517 ADBG_ERROR(("ata_attach: select failed\n")); 518 } 519 520 /* 521 * initialize atapi/ata_dsk modules if we have at least 522 * one drive of that type. 523 */ 524 525 if (atapi_count) { 526 if (!atapi_attach(ata_ctlp)) 527 goto errout1; 528 ata_ctlp->ac_flags |= AC_ATAPI_INIT; 529 } 530 531 if (disk_count) { 532 if (!ata_disk_attach(ata_ctlp)) 533 goto errout1; 534 ata_ctlp->ac_flags |= AC_DISK_INIT; 535 } 536 537 /* 538 * make certain the interrupt and error latches are clear 539 */ 540 if (ata_ctlp->ac_pciide) { 541 542 int instance = ddi_get_instance(dip); 543 if (ddi_create_minor_node(dip, "control", S_IFCHR, instance, 544 DDI_PSEUDO, 0) != DDI_SUCCESS) { 545 goto errout1; 546 } 547 548 (void) ata_pciide_status_clear(ata_ctlp); 549 550 } 551 552 /* 553 * enable the interrupt handler and drop the mutex 554 */ 555 ata_ctlp->ac_flags |= AC_ATTACHED; 556 mutex_exit(&ata_ctlp->ac_ccc.ccc_hba_mutex); 557 558 ata_init_pm(dip); 559 560 ddi_report_dev(dip); 561 return (DDI_SUCCESS); 562 563 errout1: 564 mutex_exit(&ata_ctlp->ac_ccc.ccc_hba_mutex); 565 errout: 566 (void) ata_detach(dip, DDI_DETACH); 567 return (DDI_FAILURE); 568 } 569 570 /* driver detach entry point */ 571 572 static int 573 ata_detach( 574 dev_info_t *dip, 575 ddi_detach_cmd_t cmd) 576 { 577 ata_ctl_t *ata_ctlp; 578 ata_drv_t *ata_drvp; 579 int instance; 580 int i; 581 int j; 582 583 ADBG_TRACE(("ata_detach entered\n")); 584 585 switch (cmd) { 586 case DDI_DETACH: 587 break; 588 case DDI_SUSPEND: 589 return (ata_suspend(dip)); 590 default: 591 return (DDI_FAILURE); 592 } 593 594 instance = ddi_get_instance(dip); 595 ata_ctlp = ddi_get_soft_state(ata_state, instance); 596 597 if (!ata_ctlp) 598 return (DDI_SUCCESS); 599 600 if (ata_ctlp->ac_pm_support) { 601 ATA_BUSY_COMPONENT(dip, 0); 602 if (ata_ctlp->ac_pm_level != PM_LEVEL_D0) { 603 if (ATA_RAISE_POWER(dip, 0, PM_LEVEL_D0) != 604 DDI_SUCCESS) { 605 ATA_IDLE_COMPONENT(dip, 0); 606 return (DDI_FAILURE); 607 } 608 } 609 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "pm-components"); 610 } 611 ata_ctlp->ac_flags &= ~AC_ATTACHED; 612 613 /* destroy ata module */ 614 if (ata_ctlp->ac_flags & AC_DISK_INIT) 615 ata_disk_detach(ata_ctlp); 616 617 /* destroy atapi module */ 618 if (ata_ctlp->ac_flags & AC_ATAPI_INIT) 619 atapi_detach(ata_ctlp); 620 621 ddi_remove_minor_node(dip, NULL); 622 623 /* destroy drives */ 624 for (i = 0; i < ATA_MAXTARG; i++) { 625 for (j = 0; j < ATA_MAXLUN; j++) { 626 ata_drvp = CTL2DRV(ata_ctlp, i, j); 627 if (ata_drvp != NULL) 628 ata_uninit_drive(ata_drvp); 629 } 630 } 631 632 if (ata_ctlp->ac_iohandle1) 633 ddi_regs_map_free(&ata_ctlp->ac_iohandle1); 634 if (ata_ctlp->ac_iohandle2) 635 ddi_regs_map_free(&ata_ctlp->ac_iohandle2); 636 if (ata_ctlp->ac_bmhandle) 637 ddi_regs_map_free(&ata_ctlp->ac_bmhandle); 638 639 /* destroy controller */ 640 ata_destroy_controller(dip); 641 642 ddi_prop_remove_all(dip); 643 644 return (DDI_SUCCESS); 645 } 646 647 /* 648 * Nexus driver bus_ctl entry point 649 */ 650 /*ARGSUSED*/ 651 static int 652 ata_bus_ctl( 653 dev_info_t *d, 654 dev_info_t *r, 655 ddi_ctl_enum_t o, 656 void *a, 657 void *v) 658 { 659 dev_info_t *tdip; 660 int target_type; 661 int rc; 662 char *bufp; 663 664 ADBG_TRACE(("ata_bus_ctl entered\n")); 665 666 switch (o) { 667 668 case DDI_CTLOPS_SIDDEV: 669 return (DDI_FAILURE); 670 671 case DDI_CTLOPS_IOMIN: 672 673 /* 674 * Since we use PIO, we return a minimum I/O size of 675 * one byte. This will need to be updated when we 676 * implement DMA support 677 */ 678 679 *((int *)v) = 1; 680 return (DDI_SUCCESS); 681 682 case DDI_CTLOPS_DMAPMAPC: 683 case DDI_CTLOPS_REPORTINT: 684 case DDI_CTLOPS_REGSIZE: 685 case DDI_CTLOPS_NREGS: 686 case DDI_CTLOPS_SLAVEONLY: 687 case DDI_CTLOPS_AFFINITY: 688 case DDI_CTLOPS_POKE: 689 case DDI_CTLOPS_PEEK: 690 691 /* These ops shouldn't be called by a target driver */ 692 ADBG_ERROR(("ata_bus_ctl: %s%d: invalid op (%d) from %s%d\n", 693 ddi_driver_name(d), ddi_get_instance(d), o, 694 ddi_driver_name(r), ddi_get_instance(r))); 695 696 return (DDI_FAILURE); 697 698 case DDI_CTLOPS_REPORTDEV: 699 case DDI_CTLOPS_INITCHILD: 700 case DDI_CTLOPS_UNINITCHILD: 701 702 /* these require special handling below */ 703 break; 704 705 default: 706 return (ddi_ctlops(d, r, o, a, v)); 707 } 708 709 /* get targets dip */ 710 711 if (o == DDI_CTLOPS_INITCHILD || o == DDI_CTLOPS_UNINITCHILD) 712 tdip = (dev_info_t *)a; 713 else 714 tdip = r; 715 716 /* 717 * XXX - Get class of target 718 * Before the "class" entry in a conf file becomes 719 * a real property, we use an additional property 720 * tentatively called "class_prop". We will require that 721 * new classes (ie. direct) export "class_prop". 722 * SCSA target drivers will not have this property, so 723 * no property implies SCSA. 724 */ 725 if ((ddi_prop_lookup_string(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 726 "class", &bufp) == DDI_PROP_SUCCESS) || 727 (ddi_prop_lookup_string(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 728 "class_prop", &bufp) == DDI_PROP_SUCCESS)) { 729 if (strcmp(bufp, "dada") == 0) 730 target_type = ATA_DEV_DISK; 731 else if (strcmp(bufp, "scsi") == 0) 732 target_type = ATA_DEV_ATAPI; 733 else { 734 ADBG_WARN(("ata_bus_ctl: invalid target class %s\n", 735 bufp)); 736 ddi_prop_free(bufp); 737 return (DDI_FAILURE); 738 } 739 ddi_prop_free(bufp); 740 } else { 741 target_type = ATA_DEV_ATAPI; /* no class prop, assume SCSI */ 742 } 743 744 if (o == DDI_CTLOPS_INITCHILD) { 745 int instance = ddi_get_instance(d); 746 ata_ctl_t *ata_ctlp = ddi_get_soft_state(ata_state, instance); 747 ata_drv_t *ata_drvp; 748 int targ; 749 int lun; 750 int drive_type; 751 char *disk_prop; 752 char *class_prop; 753 754 if (ata_ctlp == NULL) { 755 ADBG_WARN(("ata_bus_ctl: failed to find ctl struct\n")); 756 return (DDI_FAILURE); 757 } 758 759 /* get (target,lun) of child device */ 760 761 targ = ddi_prop_get_int(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 762 "target", -1); 763 if (targ == -1) { 764 ADBG_WARN(("ata_bus_ctl: failed to get targ num\n")); 765 return (DDI_FAILURE); 766 } 767 768 lun = ddi_prop_get_int(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 769 "lun", 0); 770 771 if ((targ < 0) || (targ >= ATA_MAXTARG) || 772 (lun < 0) || (lun >= ATA_MAXLUN)) { 773 return (DDI_FAILURE); 774 } 775 776 ata_drvp = CTL2DRV(ata_ctlp, targ, lun); 777 778 if (ata_drvp == NULL) 779 return (DDI_FAILURE); /* no drive */ 780 781 /* get type of device */ 782 783 if (ATAPIDRV(ata_drvp)) 784 drive_type = ATA_DEV_ATAPI; 785 else 786 drive_type = ATA_DEV_DISK; 787 788 /* 789 * Check for special handling when child driver is 790 * cmdk (which morphs to the correct interface) 791 */ 792 if (strcmp(ddi_get_name(tdip), "cmdk") == 0) { 793 794 if ((target_type == ATA_DEV_DISK) && 795 (target_type != drive_type)) 796 return (DDI_FAILURE); 797 798 target_type = drive_type; 799 800 if (drive_type == ATA_DEV_ATAPI) { 801 class_prop = "scsi"; 802 } else { 803 disk_prop = "dadk"; 804 class_prop = "dada"; 805 806 if (ndi_prop_update_string(DDI_DEV_T_NONE, tdip, 807 "disk", disk_prop) != DDI_PROP_SUCCESS) { 808 ADBG_WARN(("ata_bus_ctl: failed to " 809 "create disk prop\n")); 810 return (DDI_FAILURE); 811 } 812 } 813 814 if (ndi_prop_update_string(DDI_DEV_T_NONE, tdip, 815 "class_prop", class_prop) != DDI_PROP_SUCCESS) { 816 ADBG_WARN(("ata_bus_ctl: failed to " 817 "create class prop\n")); 818 return (DDI_FAILURE); 819 } 820 } 821 822 /* Check that target class matches the device */ 823 824 if (target_type != drive_type) 825 return (DDI_FAILURE); 826 827 /* save pointer to drive struct for ata_disk_bus_ctl */ 828 ddi_set_driver_private(tdip, ata_drvp); 829 830 /* 831 * Determine whether to enable DMA support for this drive. This 832 * check is deferred to this point so that the various dma 833 * properties could reside on the devinfo node should finer 834 * grained dma control be required. 835 */ 836 if (ata_drvp->ad_pciide_dma == ATA_DMA_UNINITIALIZED) { 837 ata_drvp->ad_pciide_dma = 838 ata_init_drive_pcidma(ata_ctlp, ata_drvp, tdip); 839 ata_show_transfer_mode(ata_ctlp, ata_drvp); 840 } 841 } 842 843 if (target_type == ATA_DEV_ATAPI) { 844 rc = scsa_bus_ops_p->bus_ctl(d, r, o, a, v); 845 } else { 846 rc = ata_disk_bus_ctl(d, r, o, a, v); 847 } 848 849 return (rc); 850 } 851 852 /* 853 * 854 * GHD ccc_hba_complete callback 855 * 856 */ 857 858 /* ARGSUSED */ 859 static void 860 ata_hba_complete( 861 void *hba_handle, 862 gcmd_t *gcmdp, 863 int do_callback) 864 { 865 ata_drv_t *ata_drvp; 866 ata_pkt_t *ata_pktp; 867 868 ADBG_TRACE(("ata_hba_complete entered\n")); 869 870 ata_drvp = GCMD2DRV(gcmdp); 871 ata_pktp = GCMD2APKT(gcmdp); 872 if (ata_pktp->ap_complete) 873 (*ata_pktp->ap_complete)(ata_drvp, ata_pktp, 874 do_callback); 875 } 876 877 /* GHD ccc_timeout_func callback */ 878 879 /* ARGSUSED */ 880 static int 881 ata_timeout_func( 882 void *hba_handle, 883 gcmd_t *gcmdp, 884 gtgt_t *gtgtp, 885 gact_t action, 886 int calltype) 887 { 888 ata_ctl_t *ata_ctlp; 889 ata_pkt_t *ata_pktp; 890 ata_drv_t *ata_drvp; 891 892 ADBG_TRACE(("ata_timeout_func entered\n")); 893 894 ata_ctlp = (ata_ctl_t *)hba_handle; 895 896 if (gcmdp != NULL) 897 ata_pktp = GCMD2APKT(gcmdp); 898 else 899 ata_pktp = NULL; 900 901 switch (action) { 902 case GACTION_EARLY_ABORT: 903 /* abort before request was started */ 904 if (ata_pktp != NULL) { 905 ata_pktp->ap_flags |= AP_ABORT; 906 } 907 ghd_complete(&ata_ctlp->ac_ccc, gcmdp); 908 return (TRUE); 909 910 case GACTION_EARLY_TIMEOUT: 911 /* timeout before request was started */ 912 if (ata_pktp != NULL) { 913 ata_pktp->ap_flags |= AP_TIMEOUT; 914 } 915 ghd_complete(&ata_ctlp->ac_ccc, gcmdp); 916 return (TRUE); 917 918 case GACTION_RESET_TARGET: 919 /* 920 * Reset a device is not supported. Resetting a specific 921 * device can't be done at all to an ATA device and if 922 * you send a RESET to an ATAPI device you have to 923 * reset the whole bus to make certain both devices 924 * on the bus stay in sync regarding which device is 925 * the currently selected one. 926 */ 927 return (FALSE); 928 929 case GACTION_RESET_BUS: 930 /* 931 * Issue bus reset and reinitialize both drives. 932 * But only if this is a timed-out request. Target 933 * driver reset requests are ignored because ATA 934 * and ATAPI devices shouldn't be gratuitously reset. 935 * Also disable DMA if it is a CF device. 936 */ 937 if (gcmdp == NULL) 938 break; 939 ata_drvp = GCMD2DRV(gcmdp); 940 if (ata_drvp != NULL) 941 if (ata_drvp->ad_id.ai_config == ATA_ID_CF_TO_ATA) 942 ata_disable_DMA(ata_drvp); 943 return (ata_reset_bus(ata_ctlp)); 944 default: 945 break; 946 } 947 return (FALSE); 948 } 949 950 /* 951 * 952 * Initialize controller's soft-state structure 953 * 954 */ 955 956 static ata_ctl_t * 957 ata_init_controller( 958 dev_info_t *dip) 959 { 960 ata_ctl_t *ata_ctlp; 961 int instance; 962 caddr_t ioaddr1; 963 caddr_t ioaddr2; 964 965 ADBG_TRACE(("ata_init_controller entered\n")); 966 967 instance = ddi_get_instance(dip); 968 969 /* allocate controller structure */ 970 if (ddi_soft_state_zalloc(ata_state, instance) != DDI_SUCCESS) { 971 ADBG_WARN(("ata_init_controller: soft_state_zalloc failed\n")); 972 return (NULL); 973 } 974 975 ata_ctlp = ddi_get_soft_state(ata_state, instance); 976 977 if (ata_ctlp == NULL) { 978 ADBG_WARN(("ata_init_controller: failed to find " 979 "controller struct\n")); 980 return (NULL); 981 } 982 983 /* 984 * initialize per-controller data 985 */ 986 ata_ctlp->ac_dip = dip; 987 ata_ctlp->ac_arq_pktp = kmem_zalloc(sizeof (ata_pkt_t), KM_SLEEP); 988 989 /* 990 * map the device registers 991 */ 992 if (!ata_setup_ioaddr(dip, &ata_ctlp->ac_iohandle1, &ioaddr1, 993 &ata_ctlp->ac_iohandle2, &ioaddr2, 994 &ata_ctlp->ac_bmhandle, &ata_ctlp->ac_bmaddr)) { 995 (void) ata_detach(dip, DDI_DETACH); 996 return (NULL); 997 } 998 999 ADBG_INIT(("ata_init_controller: ioaddr1 = 0x%p, ioaddr2 = 0x%p\n", 1000 ioaddr1, ioaddr2)); 1001 1002 /* 1003 * Do ARQ setup 1004 */ 1005 atapi_init_arq(ata_ctlp); 1006 1007 /* 1008 * Do PCI-IDE setup 1009 */ 1010 ata_init_pciide(dip, ata_ctlp); 1011 1012 /* 1013 * port addresses associated with ioaddr1 1014 */ 1015 ata_ctlp->ac_ioaddr1 = ioaddr1; 1016 ata_ctlp->ac_data = (ushort_t *)ioaddr1 + AT_DATA; 1017 ata_ctlp->ac_error = (uchar_t *)ioaddr1 + AT_ERROR; 1018 ata_ctlp->ac_feature = (uchar_t *)ioaddr1 + AT_FEATURE; 1019 ata_ctlp->ac_count = (uchar_t *)ioaddr1 + AT_COUNT; 1020 ata_ctlp->ac_sect = (uchar_t *)ioaddr1 + AT_SECT; 1021 ata_ctlp->ac_lcyl = (uchar_t *)ioaddr1 + AT_LCYL; 1022 ata_ctlp->ac_hcyl = (uchar_t *)ioaddr1 + AT_HCYL; 1023 ata_ctlp->ac_drvhd = (uchar_t *)ioaddr1 + AT_DRVHD; 1024 ata_ctlp->ac_status = (uchar_t *)ioaddr1 + AT_STATUS; 1025 ata_ctlp->ac_cmd = (uchar_t *)ioaddr1 + AT_CMD; 1026 1027 /* 1028 * port addresses associated with ioaddr2 1029 */ 1030 ata_ctlp->ac_ioaddr2 = ioaddr2; 1031 ata_ctlp->ac_altstatus = (uchar_t *)ioaddr2 + AT_ALTSTATUS; 1032 ata_ctlp->ac_devctl = (uchar_t *)ioaddr2 + AT_DEVCTL; 1033 1034 /* 1035 * If AC_BSY_WAIT needs to be set for laptops that do 1036 * suspend/resume but do not correctly wait for the busy bit to 1037 * drop after a resume. 1038 */ 1039 ata_ctlp->ac_timing_flags = ddi_prop_get_int(DDI_DEV_T_ANY, 1040 dip, DDI_PROP_DONTPASS, "timing_flags", 0); 1041 /* 1042 * get max transfer size, default to 256 sectors 1043 */ 1044 ata_ctlp->ac_max_transfer = ddi_prop_get_int(DDI_DEV_T_ANY, 1045 dip, DDI_PROP_DONTPASS, "max_transfer", 0x100); 1046 if (ata_ctlp->ac_max_transfer < 1) 1047 ata_ctlp->ac_max_transfer = 1; 1048 if (ata_ctlp->ac_max_transfer > 0x100) 1049 ata_ctlp->ac_max_transfer = 0x100; 1050 1051 /* 1052 * Get the standby timer value 1053 */ 1054 ata_ctlp->ac_standby_time = ddi_prop_get_int(DDI_DEV_T_ANY, 1055 dip, DDI_PROP_DONTPASS, "standby", -1); 1056 1057 /* 1058 * If this is a /pci/pci-ide instance check to see if 1059 * it's supposed to be attached as an /isa/ata 1060 */ 1061 if (ata_ctlp->ac_pciide) { 1062 static char prop_buf[] = "SUNW-ata-ffff-isa"; 1063 int addr1 = (intptr_t)ioaddr1; 1064 1065 1066 if (addr1 < 0 || addr1 > 0xffff) { 1067 (void) ata_detach(dip, DDI_DETACH); 1068 return (NULL); 1069 } 1070 (void) sprintf(prop_buf, "SUNW-ata-%04x-isa", 1071 addr1); 1072 if (ddi_prop_exists(DDI_DEV_T_ANY, ddi_root_node(), 1073 DDI_PROP_DONTPASS, prop_buf)) { 1074 (void) ata_detach(dip, DDI_DETACH); 1075 return (NULL); 1076 } 1077 } 1078 1079 /* Init controller specific stuff */ 1080 (void) ata_spec_init_controller(dip); 1081 1082 /* 1083 * initialize GHD 1084 */ 1085 1086 GHD_WAITQ_INIT(&ata_ctlp->ac_ccc.ccc_waitq, NULL, 1); 1087 1088 if (!ghd_register("ata", &ata_ctlp->ac_ccc, dip, 0, ata_ctlp, 1089 atapi_ccballoc, atapi_ccbfree, 1090 ata_pciide_dma_sg_func, ata_hba_start, 1091 ata_hba_complete, ata_intr, 1092 ata_get_status, ata_process_intr, ata_timeout_func, 1093 &ata_timer_conf, NULL)) { 1094 (void) ata_detach(dip, DDI_DETACH); 1095 return (NULL); 1096 } 1097 1098 ata_ctlp->ac_flags |= AC_GHD_INIT; 1099 return (ata_ctlp); 1100 } 1101 1102 /* destroy a controller */ 1103 1104 static void 1105 ata_destroy_controller( 1106 dev_info_t *dip) 1107 { 1108 ata_ctl_t *ata_ctlp; 1109 int instance; 1110 1111 ADBG_TRACE(("ata_destroy_controller entered\n")); 1112 1113 instance = ddi_get_instance(dip); 1114 ata_ctlp = ddi_get_soft_state(ata_state, instance); 1115 1116 if (ata_ctlp == NULL) 1117 return; 1118 1119 /* destroy ghd */ 1120 if (ata_ctlp->ac_flags & AC_GHD_INIT) 1121 ghd_unregister(&ata_ctlp->ac_ccc); 1122 1123 /* free the pciide buffer (if any) */ 1124 ata_pciide_free(ata_ctlp); 1125 1126 /* destroy controller struct */ 1127 kmem_free(ata_ctlp->ac_arq_pktp, sizeof (ata_pkt_t)); 1128 ddi_soft_state_free(ata_state, instance); 1129 1130 } 1131 1132 1133 /* 1134 * 1135 * initialize a drive 1136 * 1137 */ 1138 1139 static ata_drv_t * 1140 ata_init_drive( 1141 ata_ctl_t *ata_ctlp, 1142 uchar_t targ, 1143 uchar_t lun) 1144 { 1145 static char nec_260[] = "NEC CD-ROM DRIVE"; 1146 ata_drv_t *ata_drvp; 1147 struct ata_id *aidp; 1148 char buf[80]; 1149 int drive_type; 1150 int i; 1151 int valid_version = 0; 1152 1153 ADBG_TRACE(("ata_init_drive entered, targ = %d, lun = %d\n", 1154 targ, lun)); 1155 1156 /* check if device already exists */ 1157 1158 ata_drvp = CTL2DRV(ata_ctlp, targ, lun); 1159 1160 if (ata_drvp != NULL) 1161 return (ata_drvp); 1162 1163 /* allocate new device structure */ 1164 1165 ata_drvp = kmem_zalloc(sizeof (ata_drv_t), KM_SLEEP); 1166 aidp = &ata_drvp->ad_id; 1167 1168 /* 1169 * set up drive struct 1170 */ 1171 ata_drvp->ad_ctlp = ata_ctlp; 1172 ata_drvp->ad_pciide_dma = ATA_DMA_UNINITIALIZED; 1173 ata_drvp->ad_targ = targ; 1174 ata_drvp->ad_drive_bits = 1175 (ata_drvp->ad_targ == 0 ? ATDH_DRIVE0 : ATDH_DRIVE1); 1176 /* 1177 * Add the LUN for SFF-8070i support 1178 */ 1179 ata_drvp->ad_lun = lun; 1180 ata_drvp->ad_drive_bits |= ata_drvp->ad_lun; 1181 1182 /* 1183 * get drive type, side effect is to collect 1184 * IDENTIFY DRIVE data 1185 */ 1186 1187 drive_type = ata_drive_type(ata_drvp->ad_drive_bits, 1188 ata_ctlp->ac_iohandle1, 1189 ata_ctlp->ac_ioaddr1, 1190 ata_ctlp->ac_iohandle2, 1191 ata_ctlp->ac_ioaddr2, 1192 aidp); 1193 1194 switch (drive_type) { 1195 case ATA_DEV_NONE: 1196 /* no drive found */ 1197 goto errout; 1198 case ATA_DEV_ATAPI: 1199 ata_drvp->ad_flags |= AD_ATAPI; 1200 break; 1201 case ATA_DEV_DISK: 1202 ata_drvp->ad_flags |= AD_DISK; 1203 break; 1204 } 1205 1206 /* 1207 * swap bytes of all text fields 1208 */ 1209 if (!ata_strncmp(nec_260, aidp->ai_model, sizeof (aidp->ai_model))) { 1210 swab(aidp->ai_drvser, aidp->ai_drvser, 1211 sizeof (aidp->ai_drvser)); 1212 swab(aidp->ai_fw, aidp->ai_fw, 1213 sizeof (aidp->ai_fw)); 1214 swab(aidp->ai_model, aidp->ai_model, 1215 sizeof (aidp->ai_model)); 1216 } 1217 1218 /* 1219 * Check if this drive has the Single Sector bug 1220 */ 1221 1222 if (ata_check_drive_blacklist(&ata_drvp->ad_id, ATA_BL_1SECTOR)) 1223 ata_drvp->ad_flags |= AD_1SECTOR; 1224 else 1225 ata_drvp->ad_flags &= ~AD_1SECTOR; 1226 1227 /* Check if this drive has the "revert to defaults" bug */ 1228 if (!ata_check_revert_to_defaults(ata_drvp)) 1229 ata_drvp->ad_flags |= AD_NORVRT; 1230 1231 /* Dump the drive info */ 1232 (void) strncpy(buf, aidp->ai_model, sizeof (aidp->ai_model)); 1233 buf[sizeof (aidp->ai_model)-1] = '\0'; 1234 for (i = sizeof (aidp->ai_model) - 2; buf[i] == ' '; i--) 1235 buf[i] = '\0'; 1236 1237 ATAPRT(("?\t%s device at targ %d, lun %d lastlun 0x%x\n", 1238 (ATAPIDRV(ata_drvp) ? "ATAPI":"IDE"), 1239 ata_drvp->ad_targ, ata_drvp->ad_lun, aidp->ai_lastlun)); 1240 1241 ATAPRT(("?\tmodel %s\n", buf)); 1242 1243 if (aidp->ai_majorversion != 0 && aidp->ai_majorversion != 0xffff) { 1244 for (i = 14; i >= 2; i--) { 1245 if (aidp->ai_majorversion & (1 << i)) { 1246 valid_version = i; 1247 break; 1248 } 1249 } 1250 ATAPRT(( 1251 "?\tATA/ATAPI-%d supported, majver 0x%x minver 0x%x\n", 1252 valid_version, 1253 aidp->ai_majorversion, 1254 aidp->ai_minorversion)); 1255 } 1256 1257 if (ata_capability_data) { 1258 1259 ATAPRT(("?\t\tstat %x, err %x\n", 1260 ddi_get8(ata_ctlp->ac_iohandle2, 1261 ata_ctlp->ac_altstatus), 1262 ddi_get8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_error))); 1263 1264 ATAPRT(("?\t\tcfg 0x%x, cap 0x%x\n", 1265 aidp->ai_config, 1266 aidp->ai_cap)); 1267 1268 /* 1269 * Be aware that ATA-6 and later drives may not provide valid 1270 * geometry information and other obsoleted info. 1271 * Select what is printed based on supported ATA model (skip 1272 * anything below ATA/ATAPI-3) 1273 */ 1274 1275 if (valid_version == 0 || aidp->ai_majorversion < 1276 ATAC_MAJVER_6) { 1277 /* 1278 * Supported version less then ATA-6 1279 */ 1280 ATAPRT(("?\t\tcyl %d, hd %d, sec/trk %d\n", 1281 aidp->ai_fixcyls, 1282 aidp->ai_heads, 1283 aidp->ai_sectors)); 1284 } 1285 ATAPRT(("?\t\tmult1 0x%x, mult2 0x%x\n", 1286 aidp->ai_mult1, 1287 aidp->ai_mult2)); 1288 if (valid_version && aidp->ai_majorversion < ATAC_MAJVER_4) { 1289 ATAPRT(( 1290 "?\t\tpiomode 0x%x, dmamode 0x%x, advpiomode 0x%x\n", 1291 aidp->ai_piomode, 1292 aidp->ai_dmamode, 1293 aidp->ai_advpiomode)); 1294 } else { 1295 ATAPRT(("?\t\tadvpiomode 0x%x\n", 1296 aidp->ai_advpiomode)); 1297 } 1298 ATAPRT(("?\t\tminpio %d, minpioflow %d\n", 1299 aidp->ai_minpio, 1300 aidp->ai_minpioflow)); 1301 if (valid_version && aidp->ai_majorversion >= ATAC_MAJVER_4 && 1302 (aidp->ai_validinfo & ATAC_VALIDINFO_83)) { 1303 ATAPRT(("?\t\tdwdma 0x%x, ultradma 0x%x\n", 1304 aidp->ai_dworddma, 1305 aidp->ai_ultradma)); 1306 } else { 1307 ATAPRT(("?\t\tdwdma 0x%x\n", 1308 aidp->ai_dworddma)); 1309 } 1310 } 1311 1312 if (ATAPIDRV(ata_drvp)) { 1313 if (!atapi_init_drive(ata_drvp)) 1314 goto errout; 1315 } else { 1316 if (!ata_disk_init_drive(ata_drvp)) 1317 goto errout; 1318 } 1319 1320 /* 1321 * store pointer in controller struct 1322 */ 1323 CTL2DRV(ata_ctlp, targ, lun) = ata_drvp; 1324 1325 /* 1326 * lock the drive's current settings in case I have to 1327 * reset the drive due to some sort of error 1328 */ 1329 (void) ata_set_feature(ata_ctlp, ata_drvp, ATSF_DIS_REVPOD, 0); 1330 1331 return (ata_drvp); 1332 1333 errout: 1334 ata_uninit_drive(ata_drvp); 1335 return (NULL); 1336 } 1337 1338 /* destroy a drive */ 1339 1340 static void 1341 ata_uninit_drive( 1342 ata_drv_t *ata_drvp) 1343 { 1344 #if 0 1345 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp; 1346 #endif 1347 1348 ADBG_TRACE(("ata_uninit_drive entered\n")); 1349 1350 #if 0 1351 /* 1352 * DON'T DO THIS. disabling interrupts floats the IRQ line 1353 * which generates spurious interrupts 1354 */ 1355 1356 /* 1357 * Select the correct drive 1358 */ 1359 ddi_put8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_drvhd, 1360 ata_drvp->ad_drive_bits); 1361 ata_nsecwait(400); 1362 1363 /* 1364 * Disable interrupts from the drive 1365 */ 1366 ddi_put8(ata_ctlp->ac_iohandle2, ata_ctlp->ac_devctl, 1367 (ATDC_D3 | ATDC_NIEN)); 1368 #endif 1369 1370 /* interface specific clean-ups */ 1371 1372 if (ata_drvp->ad_flags & AD_ATAPI) 1373 atapi_uninit_drive(ata_drvp); 1374 else if (ata_drvp->ad_flags & AD_DISK) 1375 ata_disk_uninit_drive(ata_drvp); 1376 1377 /* free drive struct */ 1378 1379 kmem_free(ata_drvp, sizeof (ata_drv_t)); 1380 } 1381 1382 1383 /* 1384 * ata_drive_type() 1385 * 1386 * The timeout values and exact sequence of checking is critical 1387 * especially for atapi device detection, and should not be changed lightly. 1388 * 1389 */ 1390 static int 1391 ata_drive_type( 1392 uchar_t drvhd, 1393 ddi_acc_handle_t io_hdl1, 1394 caddr_t ioaddr1, 1395 ddi_acc_handle_t io_hdl2, 1396 caddr_t ioaddr2, 1397 struct ata_id *ata_id_bufp) 1398 { 1399 uchar_t status; 1400 1401 ADBG_TRACE(("ata_drive_type entered\n")); 1402 1403 /* 1404 * select the appropriate drive and LUN 1405 */ 1406 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_DRVHD, drvhd); 1407 ata_nsecwait(400); 1408 1409 /* 1410 * make certain the drive is selected, and wait for not busy 1411 */ 1412 (void) ata_wait3(io_hdl2, ioaddr2, 0, ATS_BSY, 0x7f, 0, 0x7f, 0, 1413 5 * 1000000); 1414 1415 status = ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS); 1416 1417 if (status & ATS_BSY) { 1418 ADBG_TRACE(("ata_drive_type 0x%p 0x%x\n", ioaddr1, status)); 1419 return (ATA_DEV_NONE); 1420 } 1421 1422 if (ata_disk_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) 1423 return (ATA_DEV_DISK); 1424 1425 /* 1426 * No disk, check for atapi unit. 1427 */ 1428 if (!atapi_signature(io_hdl1, ioaddr1)) { 1429 #ifndef ATA_DISABLE_ATAPI_1_7 1430 /* 1431 * Check for old (but prevalent) atapi 1.7B 1432 * spec device, the only known example is the 1433 * NEC CDR-260 (not 260R which is (mostly) ATAPI 1.2 1434 * compliant). This device has no signature 1435 * and requires conversion from hex to BCD 1436 * for some scsi audio commands. 1437 */ 1438 if (atapi_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) { 1439 return (ATA_DEV_ATAPI); 1440 } 1441 #endif 1442 return (ATA_DEV_NONE); 1443 } 1444 1445 if (atapi_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) { 1446 return (ATA_DEV_ATAPI); 1447 } 1448 1449 return (ATA_DEV_NONE); 1450 1451 } 1452 1453 /* 1454 * nsec-granularity time delay function 1455 */ 1456 void 1457 ata_nsecwait(clock_t count) 1458 { 1459 extern int tsc_gethrtime_initted; 1460 1461 if (tsc_gethrtime_initted) { 1462 hrtime_t end = gethrtime() + count; 1463 1464 while (gethrtime() < end) { 1465 SMT_PAUSE(); 1466 } 1467 } else { 1468 drv_usecwait(1 + (count / 1000)); 1469 } 1470 } 1471 1472 1473 /* 1474 * Wait for a register of a controller to achieve a specific state. 1475 * To return normally, all the bits in the first sub-mask must be ON, 1476 * all the bits in the second sub-mask must be OFF. 1477 * If timeout_usec microseconds pass without the controller achieving 1478 * the desired bit configuration, we return TRUE, else FALSE. 1479 */ 1480 1481 int ata_usec_delay = 10; 1482 1483 int 1484 ata_wait( 1485 ddi_acc_handle_t io_hdl, 1486 caddr_t ioaddr, 1487 uchar_t onbits, 1488 uchar_t offbits, 1489 uint_t timeout_usec) 1490 { 1491 ushort_t val; 1492 hrtime_t deadline = gethrtime() + 1493 (hrtime_t)timeout_usec * (NANOSEC / MICROSEC); 1494 1495 1496 do { 1497 val = ddi_get8(io_hdl, (uchar_t *)ioaddr + AT_ALTSTATUS); 1498 if ((val & onbits) == onbits && (val & offbits) == 0) 1499 return (TRUE); 1500 drv_usecwait(ata_usec_delay); 1501 } while (gethrtime() < deadline); 1502 1503 return (FALSE); 1504 } 1505 1506 1507 /* 1508 * 1509 * This is a slightly more complicated version that checks 1510 * for error conditions and bails-out rather than looping 1511 * until the timeout expires 1512 */ 1513 int 1514 ata_wait3( 1515 ddi_acc_handle_t io_hdl, 1516 caddr_t ioaddr, 1517 uchar_t onbits1, 1518 uchar_t offbits1, 1519 uchar_t failure_onbits2, 1520 uchar_t failure_offbits2, 1521 uchar_t failure_onbits3, 1522 uchar_t failure_offbits3, 1523 uint_t timeout_usec) 1524 { 1525 ushort_t val; 1526 hrtime_t deadline = gethrtime() + 1527 (hrtime_t)timeout_usec * (NANOSEC / MICROSEC); 1528 1529 do { 1530 val = ddi_get8(io_hdl, (uchar_t *)ioaddr + AT_ALTSTATUS); 1531 1532 /* 1533 * check for expected condition 1534 */ 1535 if ((val & onbits1) == onbits1 && (val & offbits1) == 0) 1536 return (TRUE); 1537 1538 /* 1539 * check for error conditions 1540 */ 1541 if ((val & failure_onbits2) == failure_onbits2 && 1542 (val & failure_offbits2) == 0) { 1543 return (FALSE); 1544 } 1545 1546 if ((val & failure_onbits3) == failure_onbits3 && 1547 (val & failure_offbits3) == 0) { 1548 return (FALSE); 1549 } 1550 1551 drv_usecwait(ata_usec_delay); 1552 } while (gethrtime() < deadline); 1553 1554 return (FALSE); 1555 } 1556 1557 1558 /* 1559 * 1560 * low level routine for ata_disk_id() and atapi_id() 1561 * 1562 */ 1563 1564 int 1565 ata_id_common( 1566 uchar_t id_cmd, 1567 int expect_drdy, 1568 ddi_acc_handle_t io_hdl1, 1569 caddr_t ioaddr1, 1570 ddi_acc_handle_t io_hdl2, 1571 caddr_t ioaddr2, 1572 struct ata_id *aidp) 1573 { 1574 uchar_t status; 1575 1576 ADBG_TRACE(("ata_id_common entered\n")); 1577 1578 bzero(aidp, sizeof (struct ata_id)); 1579 1580 /* 1581 * clear the features register 1582 */ 1583 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_FEATURE, 0); 1584 1585 /* 1586 * Disable interrupts from the device. When the ata 1587 * hardware is sharing its interrupt with another 1588 * device, the shared interrupt might have already been 1589 * unmasked in the interrupt controller and 1590 * triggering ata device interrupts will result in an 1591 * interrupt storm and a hung system. 1592 */ 1593 ddi_put8(io_hdl2, (uchar_t *)ioaddr2 + AT_DEVCTL, ATDC_D3 | ATDC_NIEN); 1594 1595 /* 1596 * issue IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command 1597 */ 1598 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_CMD, id_cmd); 1599 1600 /* wait for the busy bit to settle */ 1601 ata_nsecwait(400); 1602 1603 /* 1604 * read alternate status and check for conditions which 1605 * may indicate the drive is not present, to prevent getting 1606 * stuck in ata_wait3() below. 1607 */ 1608 status = ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS); 1609 1610 /* 1611 * 0x0, 0x7f, or ATS_DF can happen when no drive is present 1612 */ 1613 if ((status == 0x0) || (status == 0x7f) || 1614 ((status & (ATS_BSY|ATS_DF)) == ATS_DF)) { 1615 /* invalid status, can't be an ATA or ATAPI device */ 1616 return (FALSE); 1617 } 1618 1619 /* 1620 * According to the ATA specification, some drives may have 1621 * to read the media to complete this command. We need to 1622 * make sure we give them enough time to respond. 1623 */ 1624 (void) ata_wait3(io_hdl2, ioaddr2, 0, ATS_BSY, 1625 ATS_ERR, ATS_BSY, 0x7f, 0, 5 * 1000000); 1626 1627 /* 1628 * read the status byte and clear the pending interrupt 1629 */ 1630 status = ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_STATUS); 1631 1632 /* 1633 * this happens if there's no drive present 1634 */ 1635 if (status == 0xff || status == 0x7f) { 1636 /* invalid status, can't be an ATA or ATAPI device */ 1637 return (FALSE); 1638 } 1639 1640 if (status & ATS_BSY) { 1641 ADBG_ERROR(("ata_id_common: BUSY status 0x%x error 0x%x\n", 1642 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 +AT_ALTSTATUS), 1643 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1644 return (FALSE); 1645 } 1646 1647 if (!(status & ATS_DRQ)) { 1648 if (status & (ATS_ERR | ATS_DF)) { 1649 return (FALSE); 1650 } 1651 /* 1652 * Give the drive another second to assert DRQ. Some older 1653 * drives de-assert BSY before asserting DRQ. 1654 */ 1655 if (!ata_wait(io_hdl2, ioaddr2, ATS_DRQ, ATS_BSY, 1000000)) { 1656 ADBG_WARN(("ata_id_common: !DRQ status 0x%x error 0x%x\n", 1657 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 +AT_ALTSTATUS), 1658 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1659 return (FALSE); 1660 } 1661 } 1662 1663 /* 1664 * transfer the data 1665 */ 1666 ddi_rep_get16(io_hdl1, (ushort_t *)aidp, (ushort_t *)ioaddr1 + AT_DATA, 1667 NBPSCTR >> 1, DDI_DEV_NO_AUTOINCR); 1668 1669 /* wait for the busy bit to settle */ 1670 ata_nsecwait(400); 1671 1672 1673 /* 1674 * Wait for the drive to recognize I've read all the data. 1675 * Some drives have been observed to take as much as 3msec to 1676 * deassert DRQ after reading the data; allow 10 msec just in case. 1677 * 1678 * Note: some non-compliant ATAPI drives (e.g., NEC Multispin 6V, 1679 * CDR-1350A) don't assert DRDY. If we've made it this far we can 1680 * safely ignore the DRDY bit since the ATAPI Packet command 1681 * actually doesn't require it to ever be asserted. 1682 * 1683 */ 1684 if (!ata_wait(io_hdl2, ioaddr2, (uchar_t)(expect_drdy ? ATS_DRDY : 0), 1685 (ATS_BSY | ATS_DRQ), 1000000)) { 1686 ADBG_WARN(("ata_id_common: bad status 0x%x error 0x%x\n", 1687 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS), 1688 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1689 return (FALSE); 1690 } 1691 1692 /* 1693 * Check to see if the command aborted. This happens if 1694 * an IDENTIFY DEVICE command is issued to an ATAPI PACKET device, 1695 * or if an IDENTIFY PACKET DEVICE command is issued to an ATA 1696 * (non-PACKET) device. 1697 */ 1698 if (status & (ATS_DF | ATS_ERR)) { 1699 ADBG_WARN(("ata_id_common: status 0x%x error 0x%x \n", 1700 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS), 1701 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1702 return (FALSE); 1703 } 1704 return (TRUE); 1705 } 1706 1707 1708 /* 1709 * Low level routine to issue a non-data command and busy wait for 1710 * the completion status. 1711 */ 1712 1713 int 1714 ata_command( 1715 ata_ctl_t *ata_ctlp, 1716 ata_drv_t *ata_drvp, 1717 int expect_drdy, 1718 int silent, 1719 uint_t busy_wait, 1720 uchar_t cmd, 1721 uchar_t feature, 1722 uchar_t count, 1723 uchar_t sector, 1724 uchar_t head, 1725 uchar_t cyl_low, 1726 uchar_t cyl_hi) 1727 { 1728 ddi_acc_handle_t io_hdl1 = ata_ctlp->ac_iohandle1; 1729 ddi_acc_handle_t io_hdl2 = ata_ctlp->ac_iohandle2; 1730 uchar_t status; 1731 1732 /* select the drive */ 1733 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, ata_drvp->ad_drive_bits); 1734 ata_nsecwait(400); 1735 1736 /* make certain the drive selected */ 1737 if (!ata_wait(io_hdl2, ata_ctlp->ac_ioaddr2, 1738 (uchar_t)(expect_drdy ? ATS_DRDY : 0), 1739 ATS_BSY, busy_wait)) { 1740 ADBG_ERROR(("ata_command: select failed " 1741 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x " 1742 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n", 1743 expect_drdy, cmd, feature, count, 1744 sector, head, cyl_low, cyl_hi)); 1745 return (FALSE); 1746 } 1747 1748 /* 1749 * set all the regs 1750 */ 1751 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, (head | ata_drvp->ad_drive_bits)); 1752 ddi_put8(io_hdl1, ata_ctlp->ac_sect, sector); 1753 ddi_put8(io_hdl1, ata_ctlp->ac_count, count); 1754 ddi_put8(io_hdl1, ata_ctlp->ac_lcyl, cyl_low); 1755 ddi_put8(io_hdl1, ata_ctlp->ac_hcyl, cyl_hi); 1756 ddi_put8(io_hdl1, ata_ctlp->ac_feature, feature); 1757 1758 /* send the command */ 1759 ddi_put8(io_hdl1, ata_ctlp->ac_cmd, cmd); 1760 1761 /* wait for the busy bit to settle */ 1762 ata_nsecwait(400); 1763 1764 /* wait for not busy */ 1765 if (!ata_wait(io_hdl2, ata_ctlp->ac_ioaddr2, 0, ATS_BSY, busy_wait)) { 1766 ADBG_ERROR(("ata_command: BSY too long!" 1767 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x " 1768 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n", 1769 expect_drdy, cmd, feature, count, 1770 sector, head, cyl_low, cyl_hi)); 1771 return (FALSE); 1772 } 1773 1774 /* 1775 * wait for DRDY before continuing 1776 */ 1777 (void) ata_wait3(io_hdl2, ata_ctlp->ac_ioaddr2, 1778 ATS_DRDY, ATS_BSY, /* okay */ 1779 ATS_ERR, ATS_BSY, /* cmd failed */ 1780 ATS_DF, ATS_BSY, /* drive failed */ 1781 busy_wait); 1782 1783 /* read status to clear IRQ, and check for error */ 1784 status = ddi_get8(io_hdl1, ata_ctlp->ac_status); 1785 1786 if ((status & (ATS_BSY | ATS_DF | ATS_ERR)) == 0) 1787 return (TRUE); 1788 1789 if (!silent) { 1790 ADBG_ERROR(("ata_command status 0x%x error 0x%x " 1791 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x " 1792 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n", 1793 ddi_get8(io_hdl1, ata_ctlp->ac_status), 1794 ddi_get8(io_hdl1, ata_ctlp->ac_error), 1795 expect_drdy, cmd, feature, count, 1796 sector, head, cyl_low, cyl_hi)); 1797 } 1798 return (FALSE); 1799 } 1800 1801 1802 1803 /* 1804 * 1805 * Issue a SET FEATURES command 1806 * 1807 */ 1808 1809 int 1810 ata_set_feature( 1811 ata_ctl_t *ata_ctlp, 1812 ata_drv_t *ata_drvp, 1813 uchar_t feature, 1814 uchar_t value) 1815 { 1816 int rc; 1817 1818 rc = ata_command(ata_ctlp, ata_drvp, TRUE, TRUE, ata_set_feature_wait, 1819 ATC_SET_FEAT, feature, value, 0, 0, 0, 0); 1820 /* feature, count, sector, head, cyl_low, cyl_hi */ 1821 1822 if (rc) { 1823 return (TRUE); 1824 } 1825 1826 ADBG_ERROR(("?ata_set_feature: (0x%x,0x%x) failed\n", feature, value)); 1827 return (FALSE); 1828 } 1829 1830 1831 1832 /* 1833 * 1834 * Issue a FLUSH CACHE command 1835 * 1836 */ 1837 1838 static int 1839 ata_flush_cache( 1840 ata_ctl_t *ata_ctlp, 1841 ata_drv_t *ata_drvp) 1842 { 1843 /* this command is optional so fail silently */ 1844 return (ata_command(ata_ctlp, ata_drvp, TRUE, TRUE, 1845 ata_flush_cache_wait, 1846 ATC_FLUSH_CACHE, 0, 0, 0, 0, 0, 0)); 1847 } 1848 1849 /* 1850 * ata_setup_ioaddr() 1851 * 1852 * Map the device registers and return the handles. 1853 * 1854 * If this is a ISA-ATA controller then only two handles are 1855 * initialized and returned. 1856 * 1857 * If this is a PCI-IDE controller than a third handle (for the 1858 * PCI-IDE Bus Mastering registers) is initialized and returned. 1859 * 1860 */ 1861 1862 static int 1863 ata_setup_ioaddr( 1864 dev_info_t *dip, 1865 ddi_acc_handle_t *handle1p, 1866 caddr_t *addr1p, 1867 ddi_acc_handle_t *handle2p, 1868 caddr_t *addr2p, 1869 ddi_acc_handle_t *bm_hdlp, 1870 caddr_t *bm_addrp) 1871 { 1872 ddi_device_acc_attr_t dev_attr; 1873 int rnumber; 1874 int rc; 1875 off_t regsize; 1876 1877 /* 1878 * Make certain the controller is enabled and its regs are map-able 1879 * 1880 */ 1881 rc = ddi_dev_regsize(dip, 0, ®size); 1882 if (rc != DDI_SUCCESS || regsize <= AT_CMD) { 1883 ADBG_INIT(("ata_setup_ioaddr(1): rc %d regsize %lld\n", 1884 rc, (long long)regsize)); 1885 return (FALSE); 1886 } 1887 1888 rc = ddi_dev_regsize(dip, 1, ®size); 1889 if (rc != DDI_SUCCESS || regsize <= AT_ALTSTATUS) { 1890 ADBG_INIT(("ata_setup_ioaddr(2): rc %d regsize %lld\n", 1891 rc, (long long)regsize)); 1892 return (FALSE); 1893 } 1894 1895 /* 1896 * setup the device attribute structure for little-endian, 1897 * strict ordering access. 1898 */ 1899 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 1900 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 1901 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1902 1903 *handle1p = NULL; 1904 *handle2p = NULL; 1905 *bm_hdlp = NULL; 1906 1907 /* 1908 * Determine whether this is a ISA, PNP-ISA, or PCI-IDE device 1909 */ 1910 if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "pnp-csn")) { 1911 /* it's PNP-ISA, skip over the extra reg tuple */ 1912 rnumber = 1; 1913 goto not_pciide; 1914 } 1915 1916 /* else, it's ISA or PCI-IDE, check further */ 1917 rnumber = 0; 1918 1919 if (!ata_is_pci(dip)) { 1920 /* 1921 * If it's not a PCI-IDE, there are only two reg tuples 1922 * and the first one contains the I/O base (170 or 1f0) 1923 * rather than the controller instance number. 1924 */ 1925 ADBG_TRACE(("ata_setup_ioaddr !pci-ide\n")); 1926 goto not_pciide; 1927 } 1928 1929 1930 /* 1931 * Map the correct half of the PCI-IDE Bus Master registers. 1932 * There's a single BAR that maps these registers for both 1933 * controller's in a dual-controller chip and it's upto my 1934 * parent nexus, pciide, to adjust which (based on my instance 1935 * number) half this call maps. 1936 */ 1937 rc = ddi_dev_regsize(dip, 2, ®size); 1938 if (rc != DDI_SUCCESS || regsize < 8) { 1939 ADBG_INIT(("ata_setup_ioaddr(3): rc %d regsize %lld\n", 1940 rc, (long long)regsize)); 1941 goto not_pciide; 1942 } 1943 1944 rc = ddi_regs_map_setup(dip, 2, bm_addrp, 0, 0, &dev_attr, bm_hdlp); 1945 1946 if (rc != DDI_SUCCESS) { 1947 /* map failed, try to use in non-pci-ide mode */ 1948 ADBG_WARN(("ata_setup_ioaddr bus master map failed, rc=0x%x\n", 1949 rc)); 1950 *bm_hdlp = NULL; 1951 } 1952 1953 not_pciide: 1954 /* 1955 * map the lower command block registers 1956 */ 1957 1958 rc = ddi_regs_map_setup(dip, rnumber, addr1p, 0, 0, &dev_attr, 1959 handle1p); 1960 1961 if (rc != DDI_SUCCESS) { 1962 cmn_err(CE_WARN, "ata: reg tuple 0 map failed, rc=0x%x\n", rc); 1963 goto out1; 1964 } 1965 1966 /* 1967 * If the controller is being used in compatibility mode 1968 * via /devices/isa/ata@1,{1f0,1f0}/..., the reg property 1969 * will specify zeros for the I/O ports for the PCI 1970 * instance. 1971 */ 1972 if (*addr1p == 0) { 1973 ADBG_TRACE(("ata_setup_ioaddr ioaddr1 0\n")); 1974 goto out2; 1975 } 1976 1977 /* 1978 * map the upper control block registers 1979 */ 1980 rc = ddi_regs_map_setup(dip, rnumber + 1, addr2p, 0, 0, &dev_attr, 1981 handle2p); 1982 if (rc == DDI_SUCCESS) 1983 return (TRUE); 1984 1985 cmn_err(CE_WARN, "ata: reg tuple 1 map failed, rc=0x%x", rc); 1986 1987 out2: 1988 if (*handle1p != NULL) { 1989 ddi_regs_map_free(handle1p); 1990 *handle1p = NULL; 1991 } 1992 1993 out1: 1994 if (*bm_hdlp != NULL) { 1995 ddi_regs_map_free(bm_hdlp); 1996 *bm_hdlp = NULL; 1997 } 1998 return (FALSE); 1999 2000 } 2001 2002 /* 2003 * 2004 * Currently, the only supported controllers are ones which 2005 * support the SFF-8038 Bus Mastering spec. 2006 * 2007 * Check the parent node's IEEE 1275 class-code property to 2008 * determine if it's an PCI-IDE instance which supports SFF-8038 2009 * Bus Mastering. It's perfectly valid to have a PCI-IDE controller 2010 * that doesn't do Bus Mastering. In that case, my interrupt handler 2011 * only uses the interrupt latch bit in PCI-IDE status register. 2012 * The assumption is that the programming interface byte of the 2013 * class-code property reflects the bus master DMA capability of 2014 * the controller. 2015 * 2016 * Whether the drive support supports the DMA option still needs 2017 * to be checked later. Each individual request also has to be 2018 * checked for alignment and size to decide whether to use the 2019 * DMA transfer mode. 2020 */ 2021 2022 static void 2023 ata_init_pciide( 2024 dev_info_t *dip, 2025 ata_ctl_t *ata_ctlp) 2026 { 2027 uint_t class_code; 2028 uchar_t status; 2029 2030 ata_cntrl_DMA_sel_msg = NULL; 2031 2032 if (ata_ctlp->ac_bmhandle == NULL) { 2033 ata_ctlp->ac_pciide = FALSE; 2034 ata_ctlp->ac_pciide_bm = FALSE; 2035 ata_cntrl_DMA_sel_msg = "cntrl not Bus Master DMA capable"; 2036 return; 2037 } 2038 2039 /* 2040 * check if it's a known bogus PCI-IDE chip 2041 */ 2042 if (ata_check_pciide_blacklist(dip, ATA_BL_BOGUS)) { 2043 ADBG_WARN(("ata_setup_ioaddr pci-ide blacklist\n")); 2044 ata_ctlp->ac_pciide = FALSE; 2045 ata_ctlp->ac_pciide_bm = FALSE; 2046 ata_cntrl_DMA_sel_msg = "cntrl blacklisted"; 2047 return; 2048 } 2049 ata_ctlp->ac_pciide = TRUE; 2050 2051 if (ata_check_pciide_blacklist(dip, ATA_BL_BMSTATREG_PIO_BROKEN)) { 2052 ata_ctlp->ac_flags |= AC_BMSTATREG_PIO_BROKEN; 2053 } 2054 2055 /* 2056 * check for a PCI-IDE chip with a broken DMA engine 2057 */ 2058 if (ata_check_pciide_blacklist(dip, ATA_BL_NODMA)) { 2059 ata_ctlp->ac_pciide_bm = FALSE; 2060 ata_cntrl_DMA_sel_msg = 2061 "cntrl blacklisted/DMA engine broken"; 2062 return; 2063 } 2064 2065 /* 2066 * Check the Programming Interface register to determine 2067 * if this device supports PCI-IDE Bus Mastering. Some PCI-IDE 2068 * devices don't support Bus Mastering or DMA. 2069 * Since we are dealing with pre-qualified pci-ide controller, 2070 * check programming interface byte only. 2071 */ 2072 2073 class_code = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 2074 DDI_PROP_DONTPASS, "class-code", 0); 2075 if ((class_code & PCIIDE_BM_CAP_MASK) != PCIIDE_BM_CAP_MASK) { 2076 ata_ctlp->ac_pciide_bm = FALSE; 2077 ata_cntrl_DMA_sel_msg = 2078 "cntrl not Bus Master DMA capable"; 2079 return; 2080 } 2081 2082 /* 2083 * Avoid doing DMA on "simplex" chips which share hardware 2084 * between channels 2085 */ 2086 status = ddi_get8(ata_ctlp->ac_bmhandle, 2087 (uchar_t *)ata_ctlp->ac_bmaddr + PCIIDE_BMISX_REG); 2088 /* 2089 * Some motherboards have CSB5's that are wired "to emulate CSB4 mode". 2090 * In such a mode, the simplex bit is asserted, but in fact testing 2091 * on such a motherboard has shown that the devices are not simplex 2092 * -- DMA can be used on both channels concurrently with no special 2093 * considerations. For chips like this, we have the ATA_BL_NO_SIMPLEX 2094 * flag set to indicate that the value of the simplex bit can be 2095 * ignored. 2096 */ 2097 2098 if (status & PCIIDE_BMISX_SIMPLEX) { 2099 if (ata_check_pciide_blacklist(dip, ATA_BL_NO_SIMPLEX)) { 2100 cmn_err(CE_WARN, "Ignoring false simplex bit \n"); 2101 2102 } else { 2103 2104 int simplex_dma_channel, *rp, proplen, channel; 2105 int dma_on = FALSE; 2106 2107 /* 2108 * By default,use DMA on channel 0 and PIO on channel 2109 * 1. This can be switched by setting 2110 * ata-simplex-dma-channel to: 2111 * 0 DMA on channel 0 (default without this 2112 * property) 2113 * 1 DMA on channel 1 2114 * any other value: DMA off on both channels. 2115 */ 2116 simplex_dma_channel = ata_prop_lookup_int(DDI_DEV_T_ANY, 2117 ata_ctlp->ac_dip, 0, "ata-simplex-dma-channel", 0); 2118 2119 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 2120 ata_ctlp->ac_dip, DDI_PROP_DONTPASS, "reg", &rp, 2121 (uint_t *)&proplen) == DDI_PROP_SUCCESS) { 2122 2123 channel = *rp; 2124 ddi_prop_free(rp); 2125 2126 if (simplex_dma_channel == channel) { 2127 cmn_err(CE_CONT, "?ata: simplex " 2128 "controller. DMA on channel" 2129 " %d PIO on channel %d", 2130 channel, channel ? 0:1); 2131 dma_on = TRUE; 2132 } else { 2133 ata_cntrl_DMA_sel_msg = 2134 "simplex controller"; 2135 } 2136 } 2137 2138 if (dma_on == FALSE) { 2139 ata_ctlp->ac_pciide_bm = FALSE; 2140 2141 return; 2142 } 2143 } 2144 } 2145 2146 /* 2147 * It's a compatible PCI-IDE Bus Mastering controller, 2148 * allocate and map the DMA Scatter/Gather list (PRDE table). 2149 */ 2150 if (ata_pciide_alloc(dip, ata_ctlp)) 2151 ata_ctlp->ac_pciide_bm = TRUE; 2152 else { 2153 ata_ctlp->ac_pciide_bm = FALSE; 2154 ata_cntrl_DMA_sel_msg = "unable to init DMA S/G list"; 2155 } 2156 } 2157 2158 /* 2159 * 2160 * Determine whether to enable DMA support for this drive. 2161 * The controller and the drive both have to support DMA. 2162 * The controller's capabilities were already checked in 2163 * ata_init_pciide(), now just check the drive's capabilities. 2164 * 2165 */ 2166 2167 static int 2168 ata_init_drive_pcidma( 2169 ata_ctl_t *ata_ctlp, 2170 ata_drv_t *ata_drvp, 2171 dev_info_t *tdip) 2172 { 2173 boolean_t dma; 2174 boolean_t cd_dma; 2175 boolean_t disk_dma; 2176 boolean_t atapi_dma; 2177 int ata_options; 2178 2179 ata_dev_DMA_sel_msg = NULL; 2180 2181 if (ata_ctlp->ac_pciide_bm != TRUE) { 2182 ata_dev_DMA_sel_msg = 2183 "controller is not Bus Master capable"; 2184 2185 return (ATA_DMA_OFF); 2186 } 2187 2188 ata_options = ddi_prop_get_int(DDI_DEV_T_ANY, ata_ctlp->ac_dip, 2189 0, "ata-options", 0); 2190 2191 if (!(ata_options & ATA_OPTIONS_DMA)) { 2192 /* 2193 * Either the ata-options property was not found or 2194 * DMA is not enabled by this property 2195 */ 2196 ata_dev_DMA_sel_msg = 2197 "disabled by \"ata-options\" property"; 2198 2199 return (ATA_DMA_OFF); 2200 } 2201 2202 if (ata_check_drive_blacklist(&ata_drvp->ad_id, ATA_BL_NODMA)) { 2203 ata_dev_DMA_sel_msg = "device not DMA capable; blacklisted"; 2204 2205 return (ATA_DMA_OFF); 2206 } 2207 2208 /* 2209 * DMA mode is mandatory on ATA-3 (or newer) drives but is 2210 * optional on ATA-2 (or older) drives. 2211 * 2212 * On ATA-2 drives the ai_majorversion word will probably 2213 * be 0xffff or 0x0000, check the (now obsolete) DMA bit in 2214 * the capabilities word instead. The order of these tests 2215 * is important since an ATA-3 drive doesn't have to set 2216 * the DMA bit in the capabilities word. 2217 * 2218 */ 2219 2220 if (!((ata_drvp->ad_id.ai_majorversion & 0x8000) == 0 && 2221 ata_drvp->ad_id.ai_majorversion >= (1 << 2)) && 2222 !(ata_drvp->ad_id.ai_cap & ATAC_DMA_SUPPORT)) { 2223 ata_dev_DMA_sel_msg = "device not DMA capable"; 2224 2225 return (ATA_DMA_OFF); 2226 } 2227 2228 dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2229 0, "ata-dma-enabled", TRUE); 2230 disk_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2231 0, "ata-disk-dma-enabled", TRUE); 2232 cd_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2233 0, "atapi-cd-dma-enabled", FALSE); 2234 atapi_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2235 0, "atapi-other-dma-enabled", TRUE); 2236 2237 if (dma == FALSE) { 2238 cmn_err(CE_CONT, "?ata_init_drive_pcidma: " 2239 "DMA disabled by \"ata-dma-enabled\" property"); 2240 ata_dev_DMA_sel_msg = "disabled by prop ata-dma-enabled"; 2241 2242 return (ATA_DMA_OFF); 2243 } 2244 2245 if (IS_CDROM(ata_drvp) == TRUE) { 2246 if (cd_dma == FALSE) { 2247 ata_dev_DMA_sel_msg = 2248 "disabled. Control with \"atapi-cd-dma-enabled\"" 2249 " property"; 2250 2251 return (ATA_DMA_OFF); 2252 } 2253 2254 } else if (ATAPIDRV(ata_drvp) == FALSE) { 2255 if (disk_dma == FALSE) { 2256 ata_dev_DMA_sel_msg = 2257 "disabled by \"ata-disk-dma-enabled\" property"; 2258 2259 return (ATA_DMA_OFF); 2260 } 2261 2262 } else if (atapi_dma == FALSE) { 2263 ata_dev_DMA_sel_msg = 2264 "disabled by \"atapi-other-dma-enabled\" property"; 2265 2266 return (ATA_DMA_OFF); 2267 } 2268 2269 return (ATA_DMA_ON); 2270 } 2271 2272 2273 2274 /* 2275 * this compare routine squeezes out extra blanks and 2276 * returns TRUE if p1 matches the leftmost substring of p2 2277 */ 2278 2279 static int 2280 ata_strncmp( 2281 char *p1, 2282 char *p2, 2283 int cnt) 2284 { 2285 2286 for (;;) { 2287 /* 2288 * skip over any extra blanks in both strings 2289 */ 2290 while (*p1 != '\0' && *p1 == ' ') 2291 p1++; 2292 2293 while (cnt != 0 && *p2 == ' ') { 2294 p2++; 2295 cnt--; 2296 } 2297 2298 /* 2299 * compare the two strings 2300 */ 2301 2302 if (cnt == 0 || *p1 != *p2) 2303 break; 2304 2305 while (cnt > 0 && *p1 == *p2) { 2306 p1++; 2307 p2++; 2308 cnt--; 2309 } 2310 2311 } 2312 2313 /* return TRUE if both strings ended at same point */ 2314 return ((*p1 == '\0') ? TRUE : FALSE); 2315 } 2316 2317 /* 2318 * Per PSARC/1997/281 create variant="atapi" property (if necessary) 2319 * on the target's dev_info node. Currently, the sd target driver 2320 * is the only driver which refers to this property. 2321 * 2322 * If the flag ata_id_debug is set also create the 2323 * the "ata" or "atapi" property on the target's dev_info node 2324 * 2325 */ 2326 2327 int 2328 ata_prop_create( 2329 dev_info_t *tgt_dip, 2330 ata_drv_t *ata_drvp, 2331 char *name) 2332 { 2333 int rc; 2334 2335 ADBG_TRACE(("ata_prop_create 0x%p 0x%p %s\n", tgt_dip, ata_drvp, name)); 2336 2337 if (strcmp("atapi", name) == 0) { 2338 rc = ndi_prop_update_string(DDI_DEV_T_NONE, tgt_dip, 2339 "variant", name); 2340 if (rc != DDI_PROP_SUCCESS) 2341 return (FALSE); 2342 } 2343 2344 if (!ata_id_debug) 2345 return (TRUE); 2346 2347 rc = ndi_prop_update_byte_array(DDI_DEV_T_NONE, tgt_dip, name, 2348 (uchar_t *)&ata_drvp->ad_id, sizeof (ata_drvp->ad_id)); 2349 if (rc != DDI_PROP_SUCCESS) { 2350 ADBG_ERROR(("ata_prop_create failed, rc=%d\n", rc)); 2351 } 2352 return (TRUE); 2353 } 2354 2355 2356 /* *********************************************************************** */ 2357 /* *********************************************************************** */ 2358 /* *********************************************************************** */ 2359 2360 /* 2361 * This state machine doesn't implement the ATAPI Optional Overlap 2362 * feature. You need that feature to efficiently support ATAPI 2363 * tape drives. See the 1394-ATA Tailgate spec (D97107), Figure 24, 2364 * for an example of how to add the necessary additional NextActions 2365 * and NextStates to this FSM and the atapi_fsm, in order to support 2366 * the Overlap Feature. 2367 */ 2368 2369 2370 uchar_t ata_ctlr_fsm_NextAction[ATA_CTLR_NSTATES][ATA_CTLR_NFUNCS] = { 2371 /* --------------------- next action --------------------- | - current - */ 2372 /* start0 --- start1 ---- intr ------ fini --- reset --- */ 2373 { AC_START, AC_START, AC_NADA, AC_NADA, AC_RESET_I }, /* idle */ 2374 { AC_BUSY, AC_BUSY, AC_INTR, AC_FINI, AC_RESET_A }, /* active0 */ 2375 { AC_BUSY, AC_BUSY, AC_INTR, AC_FINI, AC_RESET_A }, /* active1 */ 2376 }; 2377 2378 uchar_t ata_ctlr_fsm_NextState[ATA_CTLR_NSTATES][ATA_CTLR_NFUNCS] = { 2379 2380 /* --------------------- next state --------------------- | - current - */ 2381 /* start0 --- start1 ---- intr ------ fini --- reset --- */ 2382 { AS_ACTIVE0, AS_ACTIVE1, AS_IDLE, AS_IDLE, AS_IDLE }, /* idle */ 2383 { AS_ACTIVE0, AS_ACTIVE0, AS_ACTIVE0, AS_IDLE, AS_ACTIVE0 }, /* active0 */ 2384 { AS_ACTIVE1, AS_ACTIVE1, AS_ACTIVE1, AS_IDLE, AS_ACTIVE1 }, /* active1 */ 2385 }; 2386 2387 2388 static int 2389 ata_ctlr_fsm( 2390 uchar_t fsm_func, 2391 ata_ctl_t *ata_ctlp, 2392 ata_drv_t *ata_drvp, 2393 ata_pkt_t *ata_pktp, 2394 int *DoneFlgp) 2395 { 2396 uchar_t action; 2397 uchar_t current_state; 2398 uchar_t next_state; 2399 int rc; 2400 2401 current_state = ata_ctlp->ac_state; 2402 action = ata_ctlr_fsm_NextAction[current_state][fsm_func]; 2403 next_state = ata_ctlr_fsm_NextState[current_state][fsm_func]; 2404 2405 /* 2406 * Set the controller's new state 2407 */ 2408 ata_ctlp->ac_state = next_state; 2409 switch (action) { 2410 2411 case AC_BUSY: 2412 return (ATA_FSM_RC_BUSY); 2413 2414 case AC_NADA: 2415 return (ATA_FSM_RC_OKAY); 2416 2417 case AC_START: 2418 ASSERT(ata_ctlp->ac_active_pktp == NULL); 2419 ASSERT(ata_ctlp->ac_active_drvp == NULL); 2420 2421 ata_ctlp->ac_active_pktp = ata_pktp; 2422 ata_ctlp->ac_active_drvp = ata_drvp; 2423 2424 rc = (*ata_pktp->ap_start)(ata_ctlp, ata_drvp, ata_pktp); 2425 2426 if (rc == ATA_FSM_RC_BUSY) { 2427 /* the request didn't start, GHD will requeue it */ 2428 ata_ctlp->ac_state = AS_IDLE; 2429 ata_ctlp->ac_active_pktp = NULL; 2430 ata_ctlp->ac_active_drvp = NULL; 2431 } 2432 return (rc); 2433 2434 case AC_INTR: 2435 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2436 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2437 2438 ata_drvp = ata_ctlp->ac_active_drvp; 2439 ata_pktp = ata_ctlp->ac_active_pktp; 2440 return ((*ata_pktp->ap_intr)(ata_ctlp, ata_drvp, ata_pktp)); 2441 2442 case AC_RESET_A: /* Reset, controller active */ 2443 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2444 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2445 2446 /* clean up the active request */ 2447 ata_pktp = ata_ctlp->ac_active_pktp; 2448 ata_pktp->ap_flags |= AP_DEV_RESET | AP_BUS_RESET; 2449 2450 /* halt the DMA engine */ 2451 if (ata_pktp->ap_pciide_dma) { 2452 ata_pciide_dma_stop(ata_ctlp); 2453 (void) ata_pciide_status_clear(ata_ctlp); 2454 } 2455 2456 /* Do a Software Reset to unwedge the bus */ 2457 if (!ata_software_reset(ata_ctlp)) { 2458 return (ATA_FSM_RC_BUSY); 2459 } 2460 2461 /* Then send a DEVICE RESET cmd to each ATAPI device */ 2462 atapi_fsm_reset(ata_ctlp); 2463 return (ATA_FSM_RC_FINI); 2464 2465 case AC_RESET_I: /* Reset, controller idle */ 2466 /* Do a Software Reset to unwedge the bus */ 2467 if (!ata_software_reset(ata_ctlp)) { 2468 return (ATA_FSM_RC_BUSY); 2469 } 2470 2471 /* Then send a DEVICE RESET cmd to each ATAPI device */ 2472 atapi_fsm_reset(ata_ctlp); 2473 return (ATA_FSM_RC_OKAY); 2474 2475 case AC_FINI: 2476 break; 2477 } 2478 2479 /* 2480 * AC_FINI, check ARQ needs to be started or finished 2481 */ 2482 2483 ASSERT(action == AC_FINI); 2484 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2485 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2486 2487 /* 2488 * The active request is done now. 2489 * Disconnect the request from the controller and 2490 * add it to the done queue. 2491 */ 2492 ata_drvp = ata_ctlp->ac_active_drvp; 2493 ata_pktp = ata_ctlp->ac_active_pktp; 2494 2495 /* 2496 * If ARQ pkt is done, get ptr to original pkt and wrap it up. 2497 */ 2498 if (ata_pktp == ata_ctlp->ac_arq_pktp) { 2499 ata_pkt_t *arq_pktp; 2500 2501 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ done\n", ata_ctlp)); 2502 2503 arq_pktp = ata_pktp; 2504 ata_pktp = ata_ctlp->ac_fault_pktp; 2505 ata_ctlp->ac_fault_pktp = NULL; 2506 if (arq_pktp->ap_flags & (AP_ERROR | AP_BUS_RESET)) 2507 ata_pktp->ap_flags |= AP_ARQ_ERROR; 2508 else 2509 ata_pktp->ap_flags |= AP_ARQ_OKAY; 2510 goto all_done; 2511 } 2512 2513 2514 #define AP_ARQ_NEEDED (AP_ARQ_ON_ERROR | AP_GOT_STATUS | AP_ERROR) 2515 2516 /* 2517 * Start ARQ pkt if necessary 2518 */ 2519 if ((ata_pktp->ap_flags & AP_ARQ_NEEDED) == AP_ARQ_NEEDED && 2520 (ata_pktp->ap_status & ATS_ERR)) { 2521 2522 /* set controller state back to active */ 2523 ata_ctlp->ac_state = current_state; 2524 2525 /* try to start the ARQ pkt */ 2526 rc = ata_start_arq(ata_ctlp, ata_drvp, ata_pktp); 2527 2528 if (rc == ATA_FSM_RC_BUSY) { 2529 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ BUSY\n", ata_ctlp)); 2530 /* let the target driver handle the problem */ 2531 ata_ctlp->ac_state = AS_IDLE; 2532 ata_ctlp->ac_active_pktp = NULL; 2533 ata_ctlp->ac_active_drvp = NULL; 2534 ata_ctlp->ac_fault_pktp = NULL; 2535 goto all_done; 2536 } 2537 2538 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ started\n", ata_ctlp)); 2539 return (rc); 2540 } 2541 2542 /* 2543 * Normal completion, no error status, and not an ARQ pkt, 2544 * just fall through. 2545 */ 2546 2547 all_done: 2548 2549 /* 2550 * wrap everything up and tie a ribbon around it 2551 */ 2552 ata_ctlp->ac_active_pktp = NULL; 2553 ata_ctlp->ac_active_drvp = NULL; 2554 if (APKT2GCMD(ata_pktp) != (gcmd_t *)0) { 2555 ghd_complete(&ata_ctlp->ac_ccc, APKT2GCMD(ata_pktp)); 2556 if (DoneFlgp) 2557 *DoneFlgp = TRUE; 2558 } 2559 2560 return (ATA_FSM_RC_OKAY); 2561 } 2562 2563 2564 static int 2565 ata_start_arq( 2566 ata_ctl_t *ata_ctlp, 2567 ata_drv_t *ata_drvp, 2568 ata_pkt_t *ata_pktp) 2569 { 2570 ata_pkt_t *arq_pktp; 2571 int bytes; 2572 uint_t senselen; 2573 2574 ADBG_ARQ(("ata_start_arq 0x%p ARQ needed\n", ata_ctlp)); 2575 2576 /* 2577 * Determine just the size of the Request Sense Data buffer within 2578 * the scsi_arq_status structure. 2579 */ 2580 #define SIZEOF_ARQ_HEADER (sizeof (struct scsi_arq_status) \ 2581 - sizeof (struct scsi_extended_sense)) 2582 senselen = ata_pktp->ap_statuslen - SIZEOF_ARQ_HEADER; 2583 ASSERT(senselen > 0); 2584 2585 2586 /* save ptr to original pkt */ 2587 ata_ctlp->ac_fault_pktp = ata_pktp; 2588 2589 /* switch the controller's active pkt to the ARQ pkt */ 2590 arq_pktp = ata_ctlp->ac_arq_pktp; 2591 ata_ctlp->ac_active_pktp = arq_pktp; 2592 2593 /* finish initializing the ARQ CDB */ 2594 ata_ctlp->ac_arq_cdb[1] = ata_drvp->ad_lun << 4; 2595 ata_ctlp->ac_arq_cdb[4] = senselen; 2596 2597 /* finish initializing the ARQ pkt */ 2598 arq_pktp->ap_v_addr = (caddr_t)&ata_pktp->ap_scbp->sts_sensedata; 2599 2600 arq_pktp->ap_resid = senselen; 2601 arq_pktp->ap_flags = AP_ATAPI | AP_READ; 2602 arq_pktp->ap_cdb_pad = 2603 ((unsigned)(ata_drvp->ad_cdb_len - arq_pktp->ap_cdb_len)) >> 1; 2604 2605 bytes = min(senselen, ATAPI_MAX_BYTES_PER_DRQ); 2606 arq_pktp->ap_hicyl = (uchar_t)(bytes >> 8); 2607 arq_pktp->ap_lwcyl = (uchar_t)bytes; 2608 2609 /* 2610 * This packet is shared by all drives on this controller 2611 * therefore we need to init the drive number on every ARQ. 2612 */ 2613 arq_pktp->ap_hd = ata_drvp->ad_drive_bits; 2614 2615 /* start it up */ 2616 return ((*arq_pktp->ap_start)(ata_ctlp, ata_drvp, arq_pktp)); 2617 } 2618 2619 /* 2620 * 2621 * reset the bus 2622 * 2623 */ 2624 2625 static int 2626 ata_reset_bus( 2627 ata_ctl_t *ata_ctlp) 2628 { 2629 int watchdog; 2630 uchar_t drive; 2631 int rc = FALSE; 2632 uchar_t fsm_func; 2633 int DoneFlg = FALSE; 2634 2635 /* 2636 * Do a Software Reset to unwedge the bus, and send 2637 * ATAPI DEVICE RESET to each ATAPI drive. 2638 */ 2639 fsm_func = ATA_FSM_RESET; 2640 for (watchdog = ata_reset_bus_watchdog; watchdog > 0; watchdog--) { 2641 switch (ata_ctlr_fsm(fsm_func, ata_ctlp, NULL, NULL, 2642 &DoneFlg)) { 2643 case ATA_FSM_RC_OKAY: 2644 rc = TRUE; 2645 goto fsm_done; 2646 2647 case ATA_FSM_RC_BUSY: 2648 return (FALSE); 2649 2650 case ATA_FSM_RC_INTR: 2651 fsm_func = ATA_FSM_INTR; 2652 rc = TRUE; 2653 continue; 2654 2655 case ATA_FSM_RC_FINI: 2656 fsm_func = ATA_FSM_FINI; 2657 rc = TRUE; 2658 continue; 2659 } 2660 } 2661 ADBG_WARN(("ata_reset_bus: watchdog\n")); 2662 2663 fsm_done: 2664 2665 /* 2666 * Reinitialize the ATA drives 2667 */ 2668 for (drive = 0; drive < ATA_MAXTARG; drive++) { 2669 ata_drv_t *ata_drvp; 2670 2671 if ((ata_drvp = CTL2DRV(ata_ctlp, drive, 0)) == NULL) 2672 continue; 2673 2674 if (ATAPIDRV(ata_drvp)) 2675 continue; 2676 2677 /* 2678 * Reprogram the Read/Write Multiple block factor 2679 * and current geometry into the drive. 2680 */ 2681 if (!ata_disk_setup_parms(ata_ctlp, ata_drvp)) 2682 rc = FALSE; 2683 } 2684 2685 /* If DoneFlg is TRUE, it means that ghd_complete() function */ 2686 /* has been already called. In this case ignore any errors and */ 2687 /* return TRUE to the caller, otherwise return the value of rc */ 2688 /* to the caller */ 2689 if (DoneFlg) 2690 return (TRUE); 2691 else 2692 return (rc); 2693 } 2694 2695 2696 /* 2697 * 2698 * Low level routine to toggle the Software Reset bit 2699 * 2700 */ 2701 2702 static int 2703 ata_software_reset( 2704 ata_ctl_t *ata_ctlp) 2705 { 2706 ddi_acc_handle_t io_hdl1 = ata_ctlp->ac_iohandle1; 2707 ddi_acc_handle_t io_hdl2 = ata_ctlp->ac_iohandle2; 2708 hrtime_t deadline; 2709 uint_t usecs_left; 2710 2711 ADBG_TRACE(("ata_reset_bus entered\n")); 2712 2713 /* disable interrupts and turn the software reset bit on */ 2714 ddi_put8(io_hdl2, ata_ctlp->ac_devctl, (ATDC_D3 | ATDC_SRST)); 2715 2716 /* why 30 milliseconds, the ATA/ATAPI-4 spec says 5 usec. */ 2717 drv_usecwait(30000); 2718 2719 /* turn the software reset bit back off */ 2720 ddi_put8(io_hdl2, ata_ctlp->ac_devctl, ATDC_D3); 2721 2722 /* 2723 * Wait for the controller to assert BUSY status. 2724 * I don't think 300 msecs is correct. The ATA/ATAPI-4 2725 * spec says 400 nsecs, (and 2 msecs if device 2726 * was in sleep mode; but we don't put drives to sleep 2727 * so it probably doesn't matter). 2728 */ 2729 drv_usecwait(300000); 2730 2731 /* 2732 * If drive 0 exists the test for completion is simple 2733 */ 2734 deadline = gethrtime() + ((hrtime_t)31 * NANOSEC); 2735 2736 if (CTL2DRV(ata_ctlp, 0, 0)) { 2737 goto wait_for_not_busy; 2738 } 2739 2740 ASSERT(CTL2DRV(ata_ctlp, 1, 0) != NULL); 2741 2742 /* 2743 * This must be a single device configuration, with drive 1 2744 * only. This complicates the test for completion because 2745 * issuing the software reset just caused drive 1 to 2746 * deselect. With drive 1 deselected, if I just read the 2747 * status register to test the BSY bit I get garbage, but 2748 * I can't re-select drive 1 until I'm certain the BSY bit 2749 * is de-asserted. Catch-22. 2750 * 2751 * In ATA/ATAPI-4, rev 15, section 9.16.2, it says to handle 2752 * this situation like this: 2753 */ 2754 2755 /* give up if the drive doesn't settle within 31 seconds */ 2756 while (gethrtime() < deadline) { 2757 /* 2758 * delay 10msec each time around the loop 2759 */ 2760 drv_usecwait(10000); 2761 2762 /* 2763 * try to select drive 1 2764 */ 2765 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, ATDH_DRIVE1); 2766 2767 ddi_put8(io_hdl1, ata_ctlp->ac_sect, 0x55); 2768 ddi_put8(io_hdl1, ata_ctlp->ac_sect, 0xaa); 2769 if (ddi_get8(io_hdl1, ata_ctlp->ac_sect) != 0xaa) 2770 continue; 2771 2772 ddi_put8(io_hdl1, ata_ctlp->ac_count, 0x55); 2773 ddi_put8(io_hdl1, ata_ctlp->ac_count, 0xaa); 2774 if (ddi_get8(io_hdl1, ata_ctlp->ac_count) != 0xaa) 2775 continue; 2776 2777 goto wait_for_not_busy; 2778 } 2779 return (FALSE); 2780 2781 wait_for_not_busy: 2782 2783 /* 2784 * Now wait up to 31 seconds for BUSY to clear. 2785 */ 2786 usecs_left = (deadline - gethrtime()) / 1000; 2787 (void) ata_wait3(io_hdl2, ata_ctlp->ac_ioaddr2, 0, ATS_BSY, 2788 ATS_ERR, ATS_BSY, ATS_DF, ATS_BSY, usecs_left); 2789 2790 return (TRUE); 2791 } 2792 2793 /* 2794 * 2795 * DDI interrupt handler 2796 * 2797 */ 2798 2799 static uint_t 2800 ata_intr( 2801 caddr_t arg) 2802 { 2803 ata_ctl_t *ata_ctlp; 2804 int one_shot = 1; 2805 2806 ata_ctlp = (ata_ctl_t *)arg; 2807 2808 return (ghd_intr(&ata_ctlp->ac_ccc, (void *)&one_shot)); 2809 } 2810 2811 2812 /* 2813 * 2814 * GHD ccc_get_status callback 2815 * 2816 */ 2817 2818 static int 2819 ata_get_status( 2820 void *hba_handle, 2821 void *intr_status) 2822 { 2823 ata_ctl_t *ata_ctlp = (ata_ctl_t *)hba_handle; 2824 uchar_t status; 2825 2826 ADBG_TRACE(("ata_get_status entered\n")); 2827 2828 /* 2829 * ignore interrupts before ata_attach completes 2830 */ 2831 if (!(ata_ctlp->ac_flags & AC_ATTACHED)) 2832 return (FALSE); 2833 2834 /* 2835 * can't be interrupt pending if nothing active 2836 */ 2837 switch (ata_ctlp->ac_state) { 2838 case AS_IDLE: 2839 return (FALSE); 2840 case AS_ACTIVE0: 2841 case AS_ACTIVE1: 2842 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2843 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2844 break; 2845 } 2846 2847 /* 2848 * If this is a PCI-IDE controller, check the PCI-IDE controller's 2849 * interrupt status latch. But don't clear it yet. 2850 * 2851 * AC_BMSTATREG_PIO_BROKEN flag is used currently for 2852 * CMD chips with device id 0x646. Since the interrupt bit on 2853 * Bus master IDE register is not usable when in PIO mode, 2854 * this chip is treated as a legacy device for interrupt 2855 * indication. The following code for CMD 2856 * chips may need to be revisited when we enable support for dma. 2857 * 2858 * CHANGE: DMA is not disabled for these devices. BM intr bit is 2859 * checked only if there was DMA used or BM intr is useable on PIO, 2860 * else treat it as before - as legacy device. 2861 */ 2862 2863 if ((ata_ctlp->ac_pciide) && 2864 ((ata_ctlp->ac_pciide_bm != FALSE) && 2865 ((ata_ctlp->ac_active_pktp->ap_pciide_dma == TRUE) || 2866 !(ata_ctlp->ac_flags & AC_BMSTATREG_PIO_BROKEN)))) { 2867 2868 if (!ata_pciide_status_pending(ata_ctlp)) 2869 return (FALSE); 2870 } else { 2871 /* 2872 * Interrupts from legacy ATA/IDE controllers are 2873 * edge-triggered but the dumb legacy ATA/IDE controllers 2874 * and drives don't have an interrupt status bit. 2875 * 2876 * Use a one_shot variable to make sure we only return 2877 * one status per interrupt. 2878 */ 2879 if (intr_status != NULL) { 2880 int *one_shot = (int *)intr_status; 2881 2882 if (*one_shot == 1) 2883 *one_shot = 0; 2884 else 2885 return (FALSE); 2886 } 2887 } 2888 2889 /* check if device is still busy */ 2890 2891 status = ddi_get8(ata_ctlp->ac_iohandle2, ata_ctlp->ac_altstatus); 2892 if (status & ATS_BSY) 2893 return (FALSE); 2894 return (TRUE); 2895 } 2896 2897 2898 /* 2899 * 2900 * get the current status and clear the IRQ 2901 * 2902 */ 2903 2904 int 2905 ata_get_status_clear_intr( 2906 ata_ctl_t *ata_ctlp, 2907 ata_pkt_t *ata_pktp) 2908 { 2909 uchar_t status; 2910 2911 /* 2912 * Here's where we clear the PCI-IDE interrupt latch. If this 2913 * request used DMA mode then we also have to check and clear 2914 * the DMA error latch at the same time. 2915 */ 2916 2917 if (ata_pktp->ap_pciide_dma) { 2918 if (ata_pciide_status_dmacheck_clear(ata_ctlp)) 2919 ata_pktp->ap_flags |= AP_ERROR | AP_TRAN_ERROR; 2920 } else if ((ata_ctlp->ac_pciide) && 2921 !(ata_ctlp->ac_flags & AC_BMSTATREG_PIO_BROKEN)) { 2922 /* 2923 * Some requests don't use DMA mode and therefore won't 2924 * set the DMA error latch, but we still have to clear 2925 * the interrupt latch. 2926 * Controllers with broken BM intr in PIO mode do not go 2927 * through this path. 2928 */ 2929 (void) ata_pciide_status_clear(ata_ctlp); 2930 } 2931 2932 /* 2933 * this clears the drive's interrupt 2934 */ 2935 status = ddi_get8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_status); 2936 ADBG_TRACE(("ata_get_status_clear_intr: 0x%x\n", status)); 2937 return (status); 2938 } 2939 2940 2941 2942 /* 2943 * 2944 * GHD interrupt handler 2945 * 2946 */ 2947 2948 /* ARGSUSED */ 2949 static void 2950 ata_process_intr( 2951 void *hba_handle, 2952 void *intr_status) 2953 { 2954 ata_ctl_t *ata_ctlp = (ata_ctl_t *)hba_handle; 2955 int watchdog; 2956 uchar_t fsm_func; 2957 int rc; 2958 2959 ADBG_TRACE(("ata_process_intr entered\n")); 2960 2961 /* 2962 * process the ATA or ATAPI interrupt 2963 */ 2964 2965 fsm_func = ATA_FSM_INTR; 2966 for (watchdog = ata_process_intr_watchdog; watchdog > 0; watchdog--) { 2967 rc = ata_ctlr_fsm(fsm_func, ata_ctlp, NULL, NULL, NULL); 2968 2969 switch (rc) { 2970 case ATA_FSM_RC_OKAY: 2971 return; 2972 2973 case ATA_FSM_RC_BUSY: /* wait for the next interrupt */ 2974 return; 2975 2976 case ATA_FSM_RC_INTR: /* re-invoke the FSM */ 2977 fsm_func = ATA_FSM_INTR; 2978 break; 2979 2980 case ATA_FSM_RC_FINI: /* move a request to done Q */ 2981 fsm_func = ATA_FSM_FINI; 2982 break; 2983 } 2984 } 2985 ADBG_WARN(("ata_process_intr: watchdog\n")); 2986 } 2987 2988 2989 2990 /* 2991 * 2992 * GHD ccc_hba_start callback 2993 * 2994 */ 2995 2996 static int 2997 ata_hba_start( 2998 void *hba_handle, 2999 gcmd_t *gcmdp) 3000 { 3001 ata_ctl_t *ata_ctlp; 3002 ata_drv_t *ata_drvp; 3003 ata_pkt_t *ata_pktp; 3004 uchar_t fsm_func; 3005 int request_started; 3006 int watchdog; 3007 3008 ADBG_TRACE(("ata_hba_start entered\n")); 3009 3010 ata_ctlp = (ata_ctl_t *)hba_handle; 3011 3012 if (ata_ctlp->ac_active_drvp != NULL) { 3013 ADBG_WARN(("ata_hba_start drvp not null\n")); 3014 return (FALSE); 3015 } 3016 if (ata_ctlp->ac_active_pktp != NULL) { 3017 ADBG_WARN(("ata_hba_start pktp not null\n")); 3018 return (FALSE); 3019 } 3020 3021 ata_pktp = GCMD2APKT(gcmdp); 3022 ata_drvp = GCMD2DRV(gcmdp); 3023 3024 /* 3025 * which drive? 3026 */ 3027 if (ata_drvp->ad_targ == 0) 3028 fsm_func = ATA_FSM_START0; 3029 else 3030 fsm_func = ATA_FSM_START1; 3031 3032 /* 3033 * start the request 3034 */ 3035 request_started = FALSE; 3036 for (watchdog = ata_hba_start_watchdog; watchdog > 0; watchdog--) { 3037 switch (ata_ctlr_fsm(fsm_func, ata_ctlp, ata_drvp, ata_pktp, 3038 NULL)) { 3039 case ATA_FSM_RC_OKAY: 3040 request_started = TRUE; 3041 goto fsm_done; 3042 3043 case ATA_FSM_RC_BUSY: 3044 /* if first time, tell GHD to requeue the request */ 3045 goto fsm_done; 3046 3047 case ATA_FSM_RC_INTR: 3048 /* 3049 * The start function polled for the next 3050 * bus phase, now fake an interrupt to process 3051 * the next action. 3052 */ 3053 request_started = TRUE; 3054 fsm_func = ATA_FSM_INTR; 3055 ata_drvp = NULL; 3056 ata_pktp = NULL; 3057 break; 3058 3059 case ATA_FSM_RC_FINI: /* move request to the done queue */ 3060 request_started = TRUE; 3061 fsm_func = ATA_FSM_FINI; 3062 ata_drvp = NULL; 3063 ata_pktp = NULL; 3064 break; 3065 } 3066 } 3067 ADBG_WARN(("ata_hba_start: watchdog\n")); 3068 3069 fsm_done: 3070 return (request_started); 3071 3072 } 3073 3074 static int 3075 ata_check_pciide_blacklist( 3076 dev_info_t *dip, 3077 uint_t flags) 3078 { 3079 ushort_t vendorid; 3080 ushort_t deviceid; 3081 pcibl_t *blp; 3082 int *propp; 3083 uint_t count; 3084 int rc; 3085 3086 3087 vendorid = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3088 DDI_PROP_DONTPASS, "vendor-id", 0); 3089 deviceid = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3090 DDI_PROP_DONTPASS, "device-id", 0); 3091 3092 /* 3093 * first check for a match in the "pci-ide-blacklist" property 3094 */ 3095 rc = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, 3096 "pci-ide-blacklist", &propp, &count); 3097 3098 if (rc == DDI_PROP_SUCCESS) { 3099 count = (count * sizeof (uint_t)) / sizeof (pcibl_t); 3100 blp = (pcibl_t *)propp; 3101 while (count--) { 3102 /* check for matching ID */ 3103 if ((vendorid & blp->b_vmask) 3104 != (blp->b_vendorid & blp->b_vmask)) { 3105 blp++; 3106 continue; 3107 } 3108 if ((deviceid & blp->b_dmask) 3109 != (blp->b_deviceid & blp->b_dmask)) { 3110 blp++; 3111 continue; 3112 } 3113 3114 /* got a match */ 3115 if (blp->b_flags & flags) { 3116 ddi_prop_free(propp); 3117 return (TRUE); 3118 } else { 3119 ddi_prop_free(propp); 3120 return (FALSE); 3121 } 3122 } 3123 ddi_prop_free(propp); 3124 } 3125 3126 /* 3127 * then check the built-in blacklist 3128 */ 3129 for (blp = ata_pciide_blacklist; blp->b_vendorid; blp++) { 3130 if ((vendorid & blp->b_vmask) != blp->b_vendorid) 3131 continue; 3132 if ((deviceid & blp->b_dmask) != blp->b_deviceid) 3133 continue; 3134 if (!(blp->b_flags & flags)) 3135 continue; 3136 return (TRUE); 3137 } 3138 return (FALSE); 3139 } 3140 3141 int 3142 ata_check_drive_blacklist( 3143 struct ata_id *aidp, 3144 uint_t flags) 3145 { 3146 atabl_t *blp; 3147 3148 for (blp = ata_drive_blacklist; blp->b_model; blp++) { 3149 if (!ata_strncmp(blp->b_model, aidp->ai_model, 3150 sizeof (aidp->ai_model))) 3151 continue; 3152 if (blp->b_flags & flags) 3153 return (TRUE); 3154 return (FALSE); 3155 } 3156 return (FALSE); 3157 } 3158 3159 /* 3160 * Queue a request to perform some sort of internally 3161 * generated command. When this request packet reaches 3162 * the front of the queue (*func)() is invoked. 3163 * 3164 */ 3165 3166 int 3167 ata_queue_cmd( 3168 int (*func)(ata_ctl_t *, ata_drv_t *, ata_pkt_t *), 3169 void *arg, 3170 ata_ctl_t *ata_ctlp, 3171 ata_drv_t *ata_drvp, 3172 gtgt_t *gtgtp) 3173 { 3174 ata_pkt_t *ata_pktp; 3175 gcmd_t *gcmdp; 3176 int rc; 3177 3178 if (!(gcmdp = ghd_gcmd_alloc(gtgtp, sizeof (*ata_pktp), TRUE))) { 3179 ADBG_ERROR(("atapi_id_update alloc failed\n")); 3180 return (FALSE); 3181 } 3182 3183 3184 /* set the back ptr from the ata_pkt to the gcmd_t */ 3185 ata_pktp = GCMD2APKT(gcmdp); 3186 ata_pktp->ap_gcmdp = gcmdp; 3187 ata_pktp->ap_hd = ata_drvp->ad_drive_bits; 3188 ata_pktp->ap_bytes_per_block = ata_drvp->ad_bytes_per_block; 3189 3190 /* 3191 * over-ride the default start function 3192 */ 3193 ata_pktp = GCMD2APKT(gcmdp); 3194 ata_pktp->ap_start = func; 3195 ata_pktp->ap_complete = NULL; 3196 ata_pktp->ap_v_addr = (caddr_t)arg; 3197 3198 /* 3199 * add it to the queue, when it gets to the front the 3200 * ap_start function is called. 3201 */ 3202 rc = ghd_transport(&ata_ctlp->ac_ccc, gcmdp, gcmdp->cmd_gtgtp, 3203 0, TRUE, NULL); 3204 3205 if (rc != TRAN_ACCEPT) { 3206 /* this should never, ever happen */ 3207 return (FALSE); 3208 } 3209 3210 if (ata_pktp->ap_flags & AP_ERROR) 3211 return (FALSE); 3212 return (TRUE); 3213 } 3214 3215 /* 3216 * Check if this drive has the "revert to defaults" bug 3217 * PSARC 2001/500 and 2001/xxx - check for the properties 3218 * ata-revert-to-defaults and atarvrt-<diskmodel> before 3219 * examining the blacklist. 3220 * <diskmodel> is made from the model number reported by Identify Drive 3221 * with uppercase letters converted to lowercase and all characters 3222 * except letters, digits, ".", "_", and "-" deleted. 3223 * Return value: 3224 * TRUE: enable revert to defaults 3225 * FALSE: disable revert to defaults 3226 * 3227 * NOTE: revert to power on defaults that includes reverting to MDMA 3228 * mode is allowed by ATA-6 & ATA-7 specs. 3229 * Therefore drives exhibiting this behaviour are not violating the spec. 3230 * Furthermore, the spec explicitly says that after the soft reset 3231 * host should check the current setting of the device features. 3232 * Correctly working BIOS would therefore reprogram either the drive 3233 * and/or the host controller to match transfer modes. 3234 * Devices with ATA_BL_NORVRT flag will be removed from 3235 * the ata_blacklist. 3236 * The default behaviour will be - no revert to power-on defaults 3237 * for all devices. The property is retained in case the user 3238 * explicitly requests revert-to-defaults before reboot. 3239 */ 3240 3241 #define ATA_REVERT_PROP_PREFIX "revert-" 3242 #define ATA_REVERT_PROP_GLOBAL "ata-revert-to-defaults" 3243 /* room for prefix + model number + terminating NUL character */ 3244 #define PROP_BUF_SIZE (sizeof (ATA_REVERT_PROP_PREFIX) + \ 3245 sizeof (aidp->ai_model) + 1) 3246 #define PROP_LEN_MAX (31) 3247 3248 static int 3249 ata_check_revert_to_defaults( 3250 ata_drv_t *ata_drvp) 3251 { 3252 struct ata_id *aidp = &ata_drvp->ad_id; 3253 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp; 3254 char prop_buf[PROP_BUF_SIZE]; 3255 int i, j; 3256 int propval; 3257 3258 /* put prefix into the buffer */ 3259 (void) strcpy(prop_buf, ATA_REVERT_PROP_PREFIX); 3260 j = strlen(prop_buf); 3261 3262 /* append the model number, leaving out invalid characters */ 3263 for (i = 0; i < sizeof (aidp->ai_model); ++i) { 3264 char c = aidp->ai_model[i]; 3265 if (c >= 'A' && c <= 'Z') /* uppercase -> lower */ 3266 c = c - 'A' + 'a'; 3267 if (c >= 'a' && c <= 'z' || c >= '0' && c <= '9' || 3268 c == '.' || c == '_' || c == '-') 3269 prop_buf[j++] = c; 3270 if (c == '\0') 3271 break; 3272 } 3273 3274 /* make sure there's a terminating NUL character */ 3275 if (j >= PROP_LEN_MAX) 3276 j = PROP_LEN_MAX; 3277 prop_buf[j] = '\0'; 3278 3279 /* look for a disk-specific "revert" property" */ 3280 propval = ddi_getprop(DDI_DEV_T_ANY, ata_ctlp->ac_dip, 3281 DDI_PROP_DONTPASS, prop_buf, -1); 3282 if (propval == 0) 3283 return (FALSE); 3284 else if (propval != -1) 3285 return (TRUE); 3286 3287 /* look for a global "revert" property" */ 3288 propval = ddi_getprop(DDI_DEV_T_ANY, ata_ctlp->ac_dip, 3289 0, ATA_REVERT_PROP_GLOBAL, -1); 3290 if (propval == 0) 3291 return (FALSE); 3292 else if (propval != -1) 3293 return (TRUE); 3294 3295 return (FALSE); 3296 } 3297 3298 void 3299 ata_show_transfer_mode(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp) 3300 { 3301 int i; 3302 3303 if (ata_ctlp->ac_pciide_bm == FALSE || 3304 ata_drvp->ad_pciide_dma != ATA_DMA_ON) { 3305 if (ata_cntrl_DMA_sel_msg) { 3306 ATAPRT(( 3307 "?\tATA DMA off: %s\n", ata_cntrl_DMA_sel_msg)); 3308 } else if (ata_dev_DMA_sel_msg) { 3309 ATAPRT(("?\tATA DMA off: %s\n", ata_dev_DMA_sel_msg)); 3310 } 3311 ATAPRT(("?\tPIO mode %d selected\n", 3312 (ata_drvp->ad_id.ai_advpiomode & ATAC_ADVPIO_4_SUP) == 3313 ATAC_ADVPIO_4_SUP ? 4 : 3)); 3314 } else { 3315 /* Using DMA */ 3316 if (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_SEL_MASK) { 3317 /* 3318 * Rely on the fact that either dwdma or udma is 3319 * selected, not both. 3320 */ 3321 ATAPRT(("?\tMultiwordDMA mode %d selected\n", 3322 (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_2_SEL) == 3323 ATAC_MDMA_2_SEL ? 2 : 3324 (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_1_SEL) == 3325 ATAC_MDMA_1_SEL ? 1 : 0)); 3326 } else { 3327 for (i = 0; i <= 6; i++) { 3328 if (ata_drvp->ad_id.ai_ultradma & 3329 (1 << (i + 8))) { 3330 ATAPRT(( 3331 "?\tUltraDMA mode %d selected\n", 3332 i)); 3333 break; 3334 } 3335 } 3336 } 3337 } 3338 } 3339 3340 /* 3341 * Controller-specific operation pointers. 3342 * Should be extended as needed - init only for now 3343 */ 3344 struct ata_ctl_spec_ops { 3345 uint_t (*cs_init)(dev_info_t *, ushort_t, ushort_t); /* ctlr init */ 3346 }; 3347 3348 3349 struct ata_ctl_spec { 3350 ushort_t cs_vendor_id; 3351 ushort_t cs_device_id; 3352 struct ata_ctl_spec_ops *cs_ops; 3353 }; 3354 3355 /* Sil3XXX-specific functions (init only for now) */ 3356 struct ata_ctl_spec_ops sil3xxx_ops = { 3357 &sil3xxx_init_controller /* Sil3XXX cntrl initialization */ 3358 }; 3359 3360 3361 struct ata_ctl_spec ata_cntrls_spec[] = { 3362 {0x1095, 0x3114, &sil3xxx_ops}, 3363 {0x1095, 0x3512, &sil3xxx_ops}, 3364 {0x1095, 0x3112, &sil3xxx_ops}, 3365 {0, 0, NULL} /* List must end with cs_ops set to NULL */ 3366 }; 3367 3368 /* 3369 * Do controller specific initialization if necessary. 3370 * Pick-up controller specific functions. 3371 */ 3372 3373 int 3374 ata_spec_init_controller(dev_info_t *dip) 3375 { 3376 ushort_t vendor_id; 3377 ushort_t device_id; 3378 struct ata_ctl_spec *ctlsp; 3379 3380 vendor_id = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3381 DDI_PROP_DONTPASS, "vendor-id", 0); 3382 device_id = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3383 DDI_PROP_DONTPASS, "device-id", 0); 3384 3385 /* Locate controller specific ops, if they exist */ 3386 ctlsp = ata_cntrls_spec; 3387 while (ctlsp->cs_ops != NULL) { 3388 if (ctlsp->cs_vendor_id == vendor_id && 3389 ctlsp->cs_device_id == device_id) 3390 break; 3391 ctlsp++; 3392 } 3393 3394 if (ctlsp->cs_ops != NULL) { 3395 if (ctlsp->cs_ops->cs_init != NULL) { 3396 /* Initialize controller */ 3397 if ((*(ctlsp->cs_ops->cs_init)) 3398 (dip, vendor_id, device_id) != TRUE) { 3399 cmn_err(CE_WARN, 3400 "pci%4x,%4x cntrl specific " 3401 "initialization failed", 3402 vendor_id, device_id); 3403 return (FALSE); 3404 } 3405 } 3406 } 3407 return (TRUE); 3408 } 3409 3410 /* 3411 * this routine works like ddi_prop_get_int, except that it works on 3412 * a string property that contains ascii representations 3413 * of an integer. 3414 * If the property is not found, the default value is returned. 3415 */ 3416 static int 3417 ata_prop_lookup_int(dev_t match_dev, dev_info_t *dip, 3418 uint_t flags, char *name, int defvalue) 3419 { 3420 3421 char *bufp, *cp; 3422 int rc = defvalue; 3423 int proprc; 3424 3425 proprc = ddi_prop_lookup_string(match_dev, dip, 3426 flags, name, &bufp); 3427 3428 if (proprc == DDI_PROP_SUCCESS) { 3429 cp = bufp; 3430 rc = stoi(&cp); 3431 ddi_prop_free(bufp); 3432 } else { 3433 /* 3434 * see if property is encoded as an int instead of string. 3435 */ 3436 rc = ddi_prop_get_int(match_dev, dip, flags, name, defvalue); 3437 } 3438 3439 return (rc); 3440 } 3441 3442 /* 3443 * Initialize the power management components 3444 */ 3445 static void 3446 ata_init_pm(dev_info_t *dip) 3447 { 3448 char pmc_name[16]; 3449 char *pmc[] = { 3450 NULL, 3451 "0=Sleep (PCI D3 State)", 3452 "3=PowerOn (PCI D0 State)", 3453 NULL 3454 }; 3455 int instance; 3456 ata_ctl_t *ata_ctlp; 3457 3458 3459 instance = ddi_get_instance(dip); 3460 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3461 ata_ctlp->ac_pm_support = 0; 3462 3463 /* check PCI capabilities */ 3464 if (!ata_is_pci(dip)) 3465 return; 3466 3467 (void) sprintf(pmc_name, "NAME=ata%d", instance); 3468 pmc[0] = pmc_name; 3469 3470 #ifdef ATA_USE_AUTOPM 3471 if (ddi_prop_update_string_array(DDI_DEV_T_NONE, dip, 3472 "pm-components", pmc, 3) != DDI_PROP_SUCCESS) { 3473 return; 3474 } 3475 #endif 3476 3477 ata_ctlp->ac_pm_support = 1; 3478 ata_ctlp->ac_pm_level = PM_LEVEL_D0; 3479 3480 ATA_BUSY_COMPONENT(dip, 0); 3481 if (ATA_RAISE_POWER(dip, 0, PM_LEVEL_D0) != DDI_SUCCESS) { 3482 (void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "pm-components"); 3483 } 3484 ATA_IDLE_COMPONENT(dip, 0); 3485 } 3486 3487 /* 3488 * resume the hard drive 3489 */ 3490 static void 3491 ata_resume_drive(ata_drv_t *ata_drvp) 3492 { 3493 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp; 3494 int drive_type; 3495 struct ata_id id; 3496 uint8_t udma; 3497 3498 ADBG_TRACE(("ata_resume_drive entered\n")); 3499 3500 drive_type = ata_drive_type(ata_drvp->ad_drive_bits, 3501 ata_ctlp->ac_iohandle1, ata_ctlp->ac_ioaddr1, 3502 ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2, 3503 &id); 3504 if (drive_type == ATA_DEV_NONE) 3505 return; 3506 3507 /* Reset Ultra DMA mode */ 3508 udma = ATACM_UDMA_SEL(&ata_drvp->ad_id); 3509 if (udma != 0) { 3510 uint8_t mode; 3511 for (mode = 0; mode < 8; mode++) 3512 if (((1 << mode) & udma) != 0) 3513 break; 3514 ASSERT(mode != 8); 3515 3516 mode |= ATF_XFRMOD_UDMA; 3517 3518 if (!ata_set_feature(ata_ctlp, ata_drvp, ATSF_SET_XFRMOD, mode)) 3519 return; 3520 } 3521 3522 if (!ATAPIDRV(ata_drvp)) { 3523 if (!ata_disk_setup_parms(ata_ctlp, ata_drvp)) 3524 return; 3525 (void) ata_set_feature(ata_ctlp, ata_drvp, ATSF_DIS_REVPOD, 0); 3526 } 3527 } 3528 3529 /* 3530 * resume routine, it will be run when get the command 3531 * DDI_RESUME at attach(9E) from system power management 3532 */ 3533 static int 3534 ata_resume(dev_info_t *dip) 3535 { 3536 int instance; 3537 ata_ctl_t *ata_ctlp; 3538 ddi_acc_handle_t io_hdl2; 3539 caddr_t ioaddr2; 3540 3541 instance = ddi_get_instance(dip); 3542 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3543 3544 if (!ata_ctlp->ac_pm_support) 3545 return (DDI_FAILURE); 3546 if (ata_ctlp->ac_pm_level == PM_LEVEL_D0) 3547 return (DDI_SUCCESS); 3548 3549 ATA_BUSY_COMPONENT(dip, 0); 3550 if (ATA_RAISE_POWER(dip, 0, PM_LEVEL_D0) == DDI_FAILURE) 3551 return (DDI_FAILURE); 3552 ATA_IDLE_COMPONENT(dip, 0); 3553 3554 /* enable interrupts from the device */ 3555 io_hdl2 = ata_ctlp->ac_iohandle2; 3556 ioaddr2 = ata_ctlp->ac_ioaddr2; 3557 ddi_put8(io_hdl2, (uchar_t *)ioaddr2 + AT_DEVCTL, ATDC_D3); 3558 ata_ctlp->ac_pm_level = PM_LEVEL_D0; 3559 3560 return (DDI_SUCCESS); 3561 } 3562 3563 /* 3564 * suspend routine, it will be run when get the command 3565 * DDI_SUSPEND at detach(9E) from system power management 3566 */ 3567 static int 3568 ata_suspend(dev_info_t *dip) 3569 { 3570 int instance; 3571 ata_ctl_t *ata_ctlp; 3572 ddi_acc_handle_t io_hdl2; 3573 3574 instance = ddi_get_instance(dip); 3575 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3576 3577 if (!ata_ctlp->ac_pm_support) 3578 return (DDI_FAILURE); 3579 if (ata_ctlp->ac_pm_level == PM_LEVEL_D3) 3580 return (DDI_SUCCESS); 3581 3582 /* disable interrupts and turn the software reset bit on */ 3583 io_hdl2 = ata_ctlp->ac_iohandle2; 3584 ddi_put8(io_hdl2, ata_ctlp->ac_devctl, (ATDC_D3 | ATDC_SRST)); 3585 3586 (void) ata_reset_bus(ata_ctlp); 3587 (void) ata_change_power(dip, ATC_SLEEP); 3588 ata_ctlp->ac_pm_level = PM_LEVEL_D3; 3589 return (DDI_SUCCESS); 3590 } 3591 3592 int ata_save_pci_config = 0; 3593 /* 3594 * ata specific power management entry point, it was 3595 * used to change the power management component 3596 */ 3597 static int 3598 ata_power(dev_info_t *dip, int component, int level) 3599 { 3600 int instance; 3601 ata_ctl_t *ata_ctlp; 3602 uint8_t cmd; 3603 3604 ADBG_TRACE(("ata_power entered, component = %d, level = %d\n", 3605 component, level)); 3606 3607 instance = ddi_get_instance(dip); 3608 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3609 if (ata_ctlp == NULL || component != 0) 3610 return (DDI_FAILURE); 3611 3612 if (!ata_ctlp->ac_pm_support) 3613 return (DDI_FAILURE); 3614 3615 switch (level) { 3616 case PM_LEVEL_D0: 3617 if (ata_save_pci_config) 3618 (void) pci_restore_config_regs(dip); 3619 ata_ctlp->ac_pm_level = PM_LEVEL_D0; 3620 cmd = ATC_STANDBY_IM; 3621 break; 3622 case PM_LEVEL_D3: 3623 if (ata_save_pci_config) 3624 (void) pci_save_config_regs(dip); 3625 ata_ctlp->ac_pm_level = PM_LEVEL_D3; 3626 cmd = ATC_SLEEP; 3627 break; 3628 default: 3629 return (DDI_FAILURE); 3630 } 3631 return (ata_change_power(dip, cmd)); 3632 } 3633 3634 /* 3635 * sent commands to ata controller to change the power level 3636 */ 3637 static int 3638 ata_change_power(dev_info_t *dip, uint8_t cmd) 3639 { 3640 int instance; 3641 ata_ctl_t *ata_ctlp; 3642 ata_drv_t *ata_drvp; 3643 uchar_t targ; 3644 struct ata_id id; 3645 uchar_t lun; 3646 uchar_t lastlun; 3647 3648 ADBG_TRACE(("ata_change_power entered, cmd = %d\n", cmd)); 3649 3650 instance = ddi_get_instance(dip); 3651 ata_ctlp = ddi_get_soft_state(ata_state, instance); 3652 /* 3653 * Issue command on each disk device on the bus. 3654 */ 3655 for (targ = 0; targ < ATA_MAXTARG; targ++) { 3656 ata_drvp = CTL2DRV(ata_ctlp, targ, 0); 3657 if (ata_drvp == NULL) 3658 continue; 3659 if (ata_drive_type(ata_drvp->ad_drive_bits, 3660 ata_ctlp->ac_iohandle1, ata_ctlp->ac_ioaddr1, 3661 ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2, 3662 &id) != ATA_DEV_DISK) 3663 continue; 3664 (void) ata_flush_cache(ata_ctlp, ata_drvp); 3665 if (!ata_command(ata_ctlp, ata_drvp, TRUE, TRUE, 5 * 1000000, 3666 cmd, 0, 0, 0, 0, 0, 0)) { 3667 cmn_err(CE_WARN, "!ata_controller - Can not put " 3668 "drive %d in to power mode %u", targ, cmd); 3669 (void) ata_devo_reset(dip, DDI_RESET_FORCE); 3670 return (DDI_FAILURE); 3671 } 3672 } 3673 3674 if (cmd == ATC_SLEEP) 3675 return (DDI_SUCCESS); 3676 3677 for (targ = 0; targ < ATA_MAXTARG; targ++) { 3678 ata_drvp = CTL2DRV(ata_ctlp, targ, 0); 3679 if ((ata_drvp == NULL) || !(ata_drvp->ad_flags & AD_DISK)) 3680 continue; 3681 ata_resume_drive(ata_drvp); 3682 3683 if (ATAPIDRV(ata_drvp)) 3684 lastlun = ata_drvp->ad_id.ai_lastlun; 3685 else 3686 lastlun = 0; 3687 if (!ata_enable_atapi_luns) 3688 lastlun = 0; 3689 for (lun = 1; lun <= lastlun && lun < ATA_MAXLUN; lun++) { 3690 ata_drvp = CTL2DRV(ata_ctlp, targ, lun); 3691 if (ata_drvp != NULL) 3692 ata_resume_drive(ata_drvp); 3693 } 3694 (void) ata_software_reset(ata_ctlp); 3695 } 3696 3697 return (DDI_SUCCESS); 3698 } 3699 3700 /* 3701 * return 1 when ata controller is a pci device, 3702 * otherwise return 0 3703 */ 3704 static int 3705 ata_is_pci(dev_info_t *dip) 3706 { 3707 int rc; 3708 char *bufp; 3709 int ispci; 3710 3711 rc = ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_get_parent(dip), 3712 DDI_PROP_DONTPASS, "device_type", &bufp); 3713 3714 if (rc != DDI_PROP_SUCCESS) { 3715 ADBG_ERROR(("ata_is_pci !device_type\n")); 3716 return (0); 3717 } 3718 3719 ispci = (strcmp(bufp, "pci-ide") == 0); 3720 3721 ddi_prop_free(bufp); 3722 3723 return (ispci); 3724 } 3725 3726 /* 3727 * Disable DMA for this drive 3728 */ 3729 static void 3730 ata_disable_DMA(ata_drv_t *ata_drvp) 3731 { 3732 struct ata_id *aidp; 3733 char buf[sizeof (aidp->ai_model) +2]; 3734 int i; 3735 3736 if (ata_drvp == NULL) 3737 return; 3738 3739 if (ata_drvp->ad_pciide_dma == ATA_DMA_OFF) 3740 return; 3741 3742 ata_drvp->ad_pciide_dma = ATA_DMA_OFF; 3743 3744 /* Print the message */ 3745 buf[0] = '\0'; 3746 aidp = &ata_drvp->ad_id; 3747 if (aidp != NULL) { 3748 (void) strncpy(buf, aidp->ai_model, sizeof (aidp->ai_model)); 3749 buf[sizeof (aidp->ai_model) -1] = '\0'; 3750 for (i = sizeof (aidp->ai_model) - 2; buf[i] == ' '; i--) 3751 buf[i] = '\0'; 3752 } 3753 cmn_err(CE_CONT, 3754 "?DMA disabled on %s target=%d, lun=%d due to DMA errors,", 3755 buf, ata_drvp->ad_targ, ata_drvp->ad_lun); 3756 cmn_err(CE_CONT, "?most likely due to the CF-to-IDE adapter."); 3757 } 3758 3759 /* 3760 * Check and select DMA mode 3761 * 3762 * TRUE is returned when set feature is called successfully, 3763 * otherwise return FALSE 3764 */ 3765 int 3766 ata_set_dma_mode(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp) 3767 { 3768 struct ata_id *aidp; 3769 int mode, rval = FALSE; 3770 uint8_t subcmd; 3771 3772 aidp = &ata_drvp->ad_id; 3773 3774 /* Return directly if DMA is not supported */ 3775 if (!(aidp->ai_cap & ATAC_DMA_SUPPORT)) 3776 return (rval); 3777 3778 /* Return if DMA mode is already selected */ 3779 if (((aidp->ai_validinfo & ATAC_VALIDINFO_83) && 3780 (aidp->ai_ultradma & ATAC_UDMA_SEL_MASK)) || 3781 (aidp->ai_dworddma & ATAC_MDMA_SEL_MASK)) 3782 return (rval); 3783 3784 /* First check Ultra DMA mode if no DMA is selected */ 3785 if ((aidp->ai_validinfo & ATAC_VALIDINFO_83) && 3786 (aidp->ai_ultradma & ATAC_UDMA_SUP_MASK)) { 3787 for (mode = 6; mode >= 0; --mode) { 3788 if (aidp->ai_ultradma & (1 << mode)) 3789 break; 3790 } 3791 subcmd = ATF_XFRMOD_UDMA; 3792 3793 } else if (aidp->ai_dworddma & ATAC_MDMA_SUP_MASK) { 3794 /* Then check multi-word DMA mode */ 3795 for (mode = 2; mode >= 0; --mode) { 3796 if (aidp->ai_dworddma & (1 << mode)) 3797 break; 3798 } 3799 subcmd = ATF_XFRMOD_MDMA; 3800 3801 } else { 3802 return (rval); 3803 } 3804 3805 rval = ata_set_feature(ata_ctlp, ata_drvp, ATSF_SET_XFRMOD, 3806 subcmd|mode); 3807 3808 return (rval); 3809 } 3810