1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/modctl.h> 31 #include <sys/debug.h> 32 #include <sys/promif.h> 33 #include <sys/pci.h> 34 #include <sys/errno.h> 35 #include <sys/open.h> 36 #include <sys/uio.h> 37 #include <sys/cred.h> 38 39 #include "ata_common.h" 40 #include "ata_disk.h" 41 #include "atapi.h" 42 #include "ata_blacklist.h" 43 #include "sil3xxx.h" 44 45 /* 46 * Solaris Entry Points. 47 */ 48 49 static int ata_probe(dev_info_t *dip); 50 static int ata_attach(dev_info_t *dip, ddi_attach_cmd_t cmd); 51 static int ata_detach(dev_info_t *dip, ddi_detach_cmd_t cmd); 52 static int ata_bus_ctl(dev_info_t *d, dev_info_t *r, ddi_ctl_enum_t o, 53 void *a, void *v); 54 static uint_t ata_intr(caddr_t arg); 55 56 /* 57 * GHD Entry points 58 */ 59 60 static int ata_get_status(void *hba_handle, void *intr_status); 61 static void ata_process_intr(void *hba_handle, void *intr_status); 62 static int ata_hba_start(void *handle, gcmd_t *gcmdp); 63 static void ata_hba_complete(void *handle, gcmd_t *gcmdp, int do_callback); 64 static int ata_timeout_func(void *hba_handle, gcmd_t *gcmdp, 65 gtgt_t *gtgtp, gact_t action, int calltype); 66 67 /* 68 * Local Function Prototypes 69 */ 70 static int ata_prop_lookup_int(dev_t match_dev, dev_info_t *dip, 71 uint_t flags, char *name, int defvalue); 72 static int ata_ctlr_fsm(uchar_t fsm_func, ata_ctl_t *ata_ctlp, 73 ata_drv_t *ata_drvp, ata_pkt_t *ata_pktp, 74 int *DoneFlgp); 75 static void ata_destroy_controller(dev_info_t *dip); 76 static int ata_drive_type(uchar_t drvhd, 77 ddi_acc_handle_t io_hdl1, caddr_t ioaddr1, 78 ddi_acc_handle_t io_hdl2, caddr_t ioaddr2, 79 struct ata_id *ata_id_bufp); 80 static ata_ctl_t *ata_init_controller(dev_info_t *dip); 81 static ata_drv_t *ata_init_drive(ata_ctl_t *ata_ctlp, 82 uchar_t targ, uchar_t lun); 83 static int ata_init_drive_pcidma(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 84 dev_info_t *tdip); 85 static int ata_flush_cache(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp); 86 static void ata_init_pciide(dev_info_t *dip, ata_ctl_t *ata_ctlp); 87 static int ata_reset_bus(ata_ctl_t *ata_ctlp); 88 static int ata_setup_ioaddr(dev_info_t *dip, 89 ddi_acc_handle_t *iohandle1, caddr_t *ioaddr1p, 90 ddi_acc_handle_t *iohandle2, caddr_t *ioaddr2p, 91 ddi_acc_handle_t *bm_hdlp, caddr_t *bm_addrp); 92 static int ata_software_reset(ata_ctl_t *ata_ctlp); 93 static int ata_start_arq(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 94 ata_pkt_t *ata_pktp); 95 static int ata_strncmp(char *p1, char *p2, int cnt); 96 static void ata_uninit_drive(ata_drv_t *ata_drvp); 97 98 static int ata_check_pciide_blacklist(dev_info_t *dip, uint_t flags); 99 static int ata_check_revert_to_defaults(ata_drv_t *ata_drvp); 100 static void ata_show_transfer_mode(ata_ctl_t *, ata_drv_t *); 101 static int ata_spec_init_controller(dev_info_t *dip); 102 103 104 /* 105 * Local static data 106 */ 107 static void *ata_state; 108 109 static tmr_t ata_timer_conf; /* single timeout list for all instances */ 110 static int ata_watchdog_usec = 100000; /* check timeouts every 100 ms */ 111 112 int ata_hba_start_watchdog = 1000; 113 int ata_process_intr_watchdog = 1000; 114 int ata_reset_bus_watchdog = 1000; 115 116 117 /* 118 * number of seconds to wait during various operations 119 */ 120 int ata_flush_delay = 5 * 1000000; 121 uint_t ata_set_feature_wait = 4 * 1000000; 122 uint_t ata_flush_cache_wait = 60 * 1000000; /* may take a long time */ 123 124 /* 125 * Change this for SFF-8070i support. Currently SFF-8070i is 126 * using a field in the IDENTIFY PACKET DEVICE response which 127 * already seems to be in use by some vendor's drives. I suspect 128 * SFF will either move their laslun field or provide a reliable 129 * way to validate it. 130 */ 131 int ata_enable_atapi_luns = FALSE; 132 133 /* 134 * set this to disable all DMA requests 135 */ 136 int ata_dma_disabled = FALSE; 137 138 /* 139 * set this to TRUE to enable storing the IDENTIFY DEVICE result in the 140 * "ata" or "atapi" property. 141 */ 142 int ata_id_debug = FALSE; 143 144 /* 145 * set this to TRUE to enable logging device-capability data 146 */ 147 int ata_capability_data = FALSE; 148 149 /* 150 * DMA selection message pointers 151 */ 152 char *ata_cntrl_DMA_sel_msg; 153 char *ata_dev_DMA_sel_msg; 154 155 /* 156 * bus nexus operations 157 */ 158 static struct bus_ops ata_bus_ops; 159 static struct bus_ops *scsa_bus_ops_p; 160 161 /* ARGSUSED */ 162 static int 163 ata_open(dev_t *devp, int flag, int otyp, cred_t *cred_p) 164 { 165 if (ddi_get_soft_state(ata_state, getminor(*devp)) == NULL) 166 return (ENXIO); 167 168 return (0); 169 } 170 171 /* 172 * The purpose of this function is to pass the ioaddress of the controller 173 * to the caller, specifically used for upgrade from pre-pciide 174 * to pciide nodes 175 */ 176 /* ARGSUSED */ 177 static int 178 ata_read(dev_t dev, struct uio *uio_p, cred_t *cred_p) 179 { 180 ata_ctl_t *ata_ctlp; 181 char buf[18]; 182 long len; 183 184 ata_ctlp = ddi_get_soft_state(ata_state, getminor(dev)); 185 186 if (ata_ctlp == NULL) 187 return (ENXIO); 188 189 (void) sprintf(buf, "%p\n", (void *) ata_ctlp->ac_ioaddr1); 190 191 len = strlen(buf) - uio_p->uio_offset; 192 len = min(uio_p->uio_resid, len); 193 if (len <= 0) 194 return (0); 195 196 return (uiomove((caddr_t)(buf + uio_p->uio_offset), len, 197 UIO_READ, uio_p)); 198 } 199 200 int 201 ata_devo_reset( 202 dev_info_t *dip, 203 ddi_reset_cmd_t cmd) 204 { 205 ata_ctl_t *ata_ctlp; 206 ata_drv_t *ata_drvp; 207 int instance; 208 int i; 209 int rc; 210 int flush_okay; 211 212 if (cmd != DDI_RESET_FORCE) 213 return (0); 214 215 instance = ddi_get_instance(dip); 216 ata_ctlp = ddi_get_soft_state(ata_state, instance); 217 218 if (!ata_ctlp) 219 return (0); 220 221 /* 222 * reset ATA drives and flush the write cache of any drives 223 */ 224 flush_okay = TRUE; 225 for (i = 0; i < ATA_MAXTARG; i++) { 226 if ((ata_drvp = CTL2DRV(ata_ctlp, i, 0)) == 0) 227 continue; 228 /* Don't revert to defaults for certain IBM drives */ 229 if ((ata_drvp->ad_flags & AD_DISK) != 0 && 230 ((ata_drvp->ad_flags & AD_NORVRT) == 0)) { 231 /* Enable revert to defaults when reset */ 232 (void) ata_set_feature(ata_ctlp, ata_drvp, 0xCC, 0); 233 } 234 235 /* 236 * skip flush cache if device type is cdrom 237 * 238 * notes: the structure definitions for ata_drvp->ad_id are 239 * defined for the ATA IDENTIFY_DEVICE, but if AD_ATAPI is set 240 * the struct holds data for the ATAPI IDENTIFY_PACKET_DEVICE 241 */ 242 if (!IS_CDROM(ata_drvp)) { 243 244 /* 245 * Try the ATA/ATAPI flush write cache command 246 */ 247 rc = ata_flush_cache(ata_ctlp, ata_drvp); 248 ADBG_WARN(("ata_flush_cache %s\n", 249 rc ? "okay" : "failed")); 250 251 if (!rc) 252 flush_okay = FALSE; 253 } 254 255 256 /* 257 * do something else if flush cache not supported 258 */ 259 } 260 261 /* 262 * just busy wait if any drive doesn't support FLUSH CACHE 263 */ 264 if (!flush_okay) 265 drv_usecwait(ata_flush_delay); 266 return (0); 267 } 268 269 270 static struct cb_ops ata_cb_ops = { 271 ata_open, /* open */ 272 nulldev, /* close */ 273 nodev, /* strategy */ 274 nodev, /* print */ 275 nodev, /* dump */ 276 ata_read, /* read */ 277 nodev, /* write */ 278 nodev, /* ioctl */ 279 nodev, /* devmap */ 280 nodev, /* mmap */ 281 nodev, /* segmap */ 282 nochpoll, /* chpoll */ 283 ddi_prop_op, /* prop_op */ 284 NULL, /* stream info */ 285 D_MP, /* driver compatibility flag */ 286 CB_REV, /* cb_ops revision */ 287 nodev, /* aread */ 288 nodev /* awrite */ 289 }; 290 291 static struct dev_ops ata_ops = { 292 DEVO_REV, /* devo_rev, */ 293 0, /* refcnt */ 294 ddi_getinfo_1to1, /* info */ 295 nulldev, /* identify */ 296 ata_probe, /* probe */ 297 ata_attach, /* attach */ 298 ata_detach, /* detach */ 299 ata_devo_reset, /* reset */ 300 &ata_cb_ops, /* driver operations */ 301 NULL /* bus operations */ 302 }; 303 304 /* driver loadable module wrapper */ 305 static struct modldrv modldrv = { 306 &mod_driverops, /* Type of module. This one is a driver */ 307 "ATA AT-bus attachment disk controller Driver", /* module name */ 308 &ata_ops, /* driver ops */ 309 }; 310 311 static struct modlinkage modlinkage = { 312 MODREV_1, (void *)&modldrv, NULL 313 }; 314 315 #ifdef ATA_DEBUG 316 int ata_debug_init = FALSE; 317 int ata_debug_probe = FALSE; 318 int ata_debug_attach = FALSE; 319 320 int ata_debug = ADBG_FLAG_ERROR 321 /* | ADBG_FLAG_ARQ */ 322 /* | ADBG_FLAG_INIT */ 323 /* | ADBG_FLAG_TRACE */ 324 /* | ADBG_FLAG_TRANSPORT */ 325 /* | ADBG_FLAG_WARN */ 326 ; 327 #endif 328 329 int 330 _init(void) 331 { 332 int err; 333 334 #ifdef ATA_DEBUG 335 if (ata_debug_init) 336 debug_enter("\nATA _INIT\n"); 337 #endif 338 339 if ((err = ddi_soft_state_init(&ata_state, sizeof (ata_ctl_t), 0)) != 0) 340 return (err); 341 342 if ((err = scsi_hba_init(&modlinkage)) != 0) { 343 ddi_soft_state_fini(&ata_state); 344 return (err); 345 } 346 347 /* save pointer to SCSA provided bus_ops struct */ 348 scsa_bus_ops_p = ata_ops.devo_bus_ops; 349 350 /* make a copy of SCSA bus_ops */ 351 ata_bus_ops = *(ata_ops.devo_bus_ops); 352 353 /* 354 * Modify our bus_ops to call our routines. Our implementation 355 * will determine if the device is ATA or ATAPI/SCSA and react 356 * accordingly. 357 */ 358 ata_bus_ops.bus_ctl = ata_bus_ctl; 359 360 /* patch our bus_ops into the dev_ops struct */ 361 ata_ops.devo_bus_ops = &ata_bus_ops; 362 363 if ((err = mod_install(&modlinkage)) != 0) { 364 scsi_hba_fini(&modlinkage); 365 ddi_soft_state_fini(&ata_state); 366 } 367 368 /* 369 * Initialize the per driver timer info. 370 */ 371 372 ghd_timer_init(&ata_timer_conf, drv_usectohz(ata_watchdog_usec)); 373 374 return (err); 375 } 376 377 int 378 _fini(void) 379 { 380 int err; 381 382 if ((err = mod_remove(&modlinkage)) == 0) { 383 ghd_timer_fini(&ata_timer_conf); 384 scsi_hba_fini(&modlinkage); 385 ddi_soft_state_fini(&ata_state); 386 } 387 388 return (err); 389 } 390 391 int 392 _info(struct modinfo *modinfop) 393 { 394 return (mod_info(&modlinkage, modinfop)); 395 } 396 397 398 /* driver probe entry point */ 399 400 static int 401 ata_probe( 402 dev_info_t *dip) 403 { 404 ddi_acc_handle_t io_hdl1 = NULL; 405 ddi_acc_handle_t io_hdl2 = NULL; 406 ddi_acc_handle_t bm_hdl = NULL; 407 caddr_t ioaddr1; 408 caddr_t ioaddr2; 409 caddr_t bm_addr; 410 int drive; 411 struct ata_id *ata_id_bufp; 412 int rc = DDI_PROBE_FAILURE; 413 414 ADBG_TRACE(("ata_probe entered\n")); 415 #ifdef ATA_DEBUG 416 if (ata_debug_probe) 417 debug_enter("\nATA_PROBE\n"); 418 #endif 419 420 if (!ata_setup_ioaddr(dip, &io_hdl1, &ioaddr1, &io_hdl2, &ioaddr2, 421 &bm_hdl, &bm_addr)) 422 return (rc); 423 424 ata_id_bufp = kmem_zalloc(sizeof (*ata_id_bufp), KM_SLEEP); 425 426 for (drive = 0; drive < ATA_MAXTARG; drive++) { 427 uchar_t drvhd; 428 429 /* set up drv/hd and feature registers */ 430 431 drvhd = (drive == 0 ? ATDH_DRIVE0 : ATDH_DRIVE1); 432 433 434 if (ata_drive_type(drvhd, io_hdl1, ioaddr1, io_hdl2, ioaddr2, 435 ata_id_bufp) != ATA_DEV_NONE) { 436 rc = (DDI_PROBE_SUCCESS); 437 break; 438 } 439 } 440 441 /* always leave the controller set to drive 0 */ 442 if (drive != 0) { 443 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_DRVHD, ATDH_DRIVE0); 444 ATA_DELAY_400NSEC(io_hdl2, ioaddr2); 445 } 446 447 out2: 448 kmem_free(ata_id_bufp, sizeof (*ata_id_bufp)); 449 450 if (io_hdl1) 451 ddi_regs_map_free(&io_hdl1); 452 if (io_hdl2) 453 ddi_regs_map_free(&io_hdl2); 454 if (bm_hdl) 455 ddi_regs_map_free(&bm_hdl); 456 return (rc); 457 } 458 459 /* 460 * 461 * driver attach entry point 462 * 463 */ 464 465 static int 466 ata_attach( 467 dev_info_t *dip, 468 ddi_attach_cmd_t cmd) 469 { 470 ata_ctl_t *ata_ctlp; 471 ata_drv_t *ata_drvp; 472 ata_drv_t *first_drvp = NULL; 473 uchar_t targ; 474 uchar_t lun; 475 uchar_t lastlun; 476 int atapi_count = 0; 477 int disk_count = 0; 478 479 ADBG_TRACE(("ata_attach entered\n")); 480 #ifdef ATA_DEBUG 481 if (ata_debug_attach) 482 debug_enter("\nATA_ATTACH\n\n"); 483 #endif 484 485 if (cmd != DDI_ATTACH) 486 return (DDI_FAILURE); 487 488 /* initialize controller */ 489 ata_ctlp = ata_init_controller(dip); 490 491 if (ata_ctlp == NULL) 492 goto errout; 493 494 mutex_enter(&ata_ctlp->ac_ccc.ccc_hba_mutex); 495 496 /* initialize drives */ 497 498 for (targ = 0; targ < ATA_MAXTARG; targ++) { 499 500 ata_drvp = ata_init_drive(ata_ctlp, targ, 0); 501 if (ata_drvp == NULL) 502 continue; 503 504 if (first_drvp == NULL) 505 first_drvp = ata_drvp; 506 507 if (ATAPIDRV(ata_drvp)) { 508 atapi_count++; 509 lastlun = ata_drvp->ad_id.ai_lastlun; 510 } else { 511 disk_count++; 512 lastlun = 0; 513 } 514 515 /* 516 * LUN support is currently disabled. Check with SFF-8070i 517 * before enabling. 518 */ 519 if (!ata_enable_atapi_luns) 520 lastlun = 0; 521 522 /* Initialize higher LUNs, if there are any */ 523 for (lun = 1; lun <= lastlun && lun < ATA_MAXLUN; lun++) { 524 if ((ata_drvp = 525 ata_init_drive(ata_ctlp, targ, lun)) != NULL) { 526 ata_show_transfer_mode(ata_ctlp, ata_drvp); 527 } 528 } 529 } 530 531 if ((atapi_count == 0) && (disk_count == 0)) { 532 ADBG_WARN(("ata_attach: no drives detected\n")); 533 goto errout1; 534 } 535 536 /* 537 * Always make certain that a valid drive is selected so 538 * that routines which poll the status register don't get 539 * confused by non-existent drives. 540 */ 541 ddi_put8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_drvhd, 542 first_drvp->ad_drive_bits); 543 ATA_DELAY_400NSEC(ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2); 544 545 /* 546 * make certain the drive selected 547 */ 548 if (!ata_wait(ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2, 549 0, ATS_BSY, 5000000)) { 550 ADBG_ERROR(("ata_attach: select failed\n")); 551 } 552 553 /* 554 * initialize atapi/ata_dsk modules if we have at least 555 * one drive of that type. 556 */ 557 558 if (atapi_count) { 559 if (!atapi_attach(ata_ctlp)) 560 goto errout1; 561 ata_ctlp->ac_flags |= AC_ATAPI_INIT; 562 } 563 564 if (disk_count) { 565 if (!ata_disk_attach(ata_ctlp)) 566 goto errout1; 567 ata_ctlp->ac_flags |= AC_DISK_INIT; 568 } 569 570 /* 571 * make certain the interrupt and error latches are clear 572 */ 573 if (ata_ctlp->ac_pciide) { 574 575 int instance = ddi_get_instance(dip); 576 if (ddi_create_minor_node(dip, "control", S_IFCHR, instance, 577 DDI_PSEUDO, 0) != DDI_SUCCESS) { 578 goto errout1; 579 } 580 581 (void) ata_pciide_status_clear(ata_ctlp); 582 583 } 584 585 /* 586 * enable the interrupt handler and drop the mutex 587 */ 588 ata_ctlp->ac_flags |= AC_ATTACHED; 589 mutex_exit(&ata_ctlp->ac_ccc.ccc_hba_mutex); 590 591 ddi_report_dev(dip); 592 return (DDI_SUCCESS); 593 594 errout1: 595 mutex_exit(&ata_ctlp->ac_ccc.ccc_hba_mutex); 596 errout: 597 (void) ata_detach(dip, DDI_DETACH); 598 return (DDI_FAILURE); 599 } 600 601 /* driver detach entry point */ 602 603 static int 604 ata_detach( 605 dev_info_t *dip, 606 ddi_detach_cmd_t cmd) 607 { 608 ata_ctl_t *ata_ctlp; 609 ata_drv_t *ata_drvp; 610 int instance; 611 int i; 612 int j; 613 614 ADBG_TRACE(("ata_detach entered\n")); 615 616 if (cmd != DDI_DETACH) 617 return (DDI_FAILURE); 618 619 instance = ddi_get_instance(dip); 620 ata_ctlp = ddi_get_soft_state(ata_state, instance); 621 622 if (!ata_ctlp) 623 return (DDI_SUCCESS); 624 625 ata_ctlp->ac_flags &= ~AC_ATTACHED; 626 627 /* destroy ata module */ 628 if (ata_ctlp->ac_flags & AC_DISK_INIT) 629 ata_disk_detach(ata_ctlp); 630 631 /* destroy atapi module */ 632 if (ata_ctlp->ac_flags & AC_ATAPI_INIT) 633 atapi_detach(ata_ctlp); 634 635 ddi_remove_minor_node(dip, NULL); 636 637 /* destroy drives */ 638 for (i = 0; i < ATA_MAXTARG; i++) { 639 for (j = 0; j < ATA_MAXLUN; j++) { 640 ata_drvp = CTL2DRV(ata_ctlp, i, j); 641 if (ata_drvp != NULL) 642 ata_uninit_drive(ata_drvp); 643 } 644 } 645 646 if (ata_ctlp->ac_iohandle1) 647 ddi_regs_map_free(&ata_ctlp->ac_iohandle1); 648 if (ata_ctlp->ac_iohandle2) 649 ddi_regs_map_free(&ata_ctlp->ac_iohandle2); 650 if (ata_ctlp->ac_bmhandle) 651 ddi_regs_map_free(&ata_ctlp->ac_bmhandle); 652 653 ddi_prop_remove_all(dip); 654 655 /* destroy controller */ 656 ata_destroy_controller(dip); 657 658 return (DDI_SUCCESS); 659 } 660 661 /* 662 * Nexus driver bus_ctl entry point 663 */ 664 /*ARGSUSED*/ 665 static int 666 ata_bus_ctl( 667 dev_info_t *d, 668 dev_info_t *r, 669 ddi_ctl_enum_t o, 670 void *a, 671 void *v) 672 { 673 dev_info_t *tdip; 674 int target_type; 675 int rc; 676 char *bufp; 677 678 ADBG_TRACE(("ata_bus_ctl entered\n")); 679 680 switch (o) { 681 682 case DDI_CTLOPS_SIDDEV: 683 return (DDI_FAILURE); 684 685 case DDI_CTLOPS_IOMIN: 686 687 /* 688 * Since we use PIO, we return a minimum I/O size of 689 * one byte. This will need to be updated when we 690 * implement DMA support 691 */ 692 693 *((int *)v) = 1; 694 return (DDI_SUCCESS); 695 696 case DDI_CTLOPS_DMAPMAPC: 697 case DDI_CTLOPS_REPORTINT: 698 case DDI_CTLOPS_REGSIZE: 699 case DDI_CTLOPS_NREGS: 700 case DDI_CTLOPS_SLAVEONLY: 701 case DDI_CTLOPS_AFFINITY: 702 case DDI_CTLOPS_POKE: 703 case DDI_CTLOPS_PEEK: 704 705 /* These ops shouldn't be called by a target driver */ 706 ADBG_ERROR(("ata_bus_ctl: %s%d: invalid op (%d) from %s%d\n", 707 ddi_driver_name(d), ddi_get_instance(d), o, 708 ddi_driver_name(r), ddi_get_instance(r))); 709 710 return (DDI_FAILURE); 711 712 case DDI_CTLOPS_REPORTDEV: 713 case DDI_CTLOPS_INITCHILD: 714 case DDI_CTLOPS_UNINITCHILD: 715 716 /* these require special handling below */ 717 break; 718 719 default: 720 return (ddi_ctlops(d, r, o, a, v)); 721 } 722 723 /* get targets dip */ 724 725 if (o == DDI_CTLOPS_INITCHILD || o == DDI_CTLOPS_UNINITCHILD) 726 tdip = (dev_info_t *)a; 727 else 728 tdip = r; 729 730 /* 731 * XXX - Get class of target 732 * Before the "class" entry in a conf file becomes 733 * a real property, we use an additional property 734 * tentatively called "class_prop". We will require that 735 * new classes (ie. direct) export "class_prop". 736 * SCSA target drivers will not have this property, so 737 * no property implies SCSA. 738 */ 739 if ((ddi_prop_lookup_string(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 740 "class", &bufp) == DDI_PROP_SUCCESS) || 741 (ddi_prop_lookup_string(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 742 "class_prop", &bufp) == DDI_PROP_SUCCESS)) { 743 if (strcmp(bufp, "dada") == 0) 744 target_type = ATA_DEV_DISK; 745 else if (strcmp(bufp, "scsi") == 0) 746 target_type = ATA_DEV_ATAPI; 747 else { 748 ADBG_WARN(("ata_bus_ctl: invalid target class %s\n", 749 bufp)); 750 ddi_prop_free(bufp); 751 return (DDI_FAILURE); 752 } 753 ddi_prop_free(bufp); 754 } else { 755 target_type = ATA_DEV_ATAPI; /* no class prop, assume SCSI */ 756 } 757 758 if (o == DDI_CTLOPS_INITCHILD) { 759 int instance = ddi_get_instance(d); 760 ata_ctl_t *ata_ctlp = ddi_get_soft_state(ata_state, instance); 761 ata_drv_t *ata_drvp; 762 int targ; 763 int lun; 764 int drive_type; 765 char *disk_prop; 766 char *class_prop; 767 768 if (ata_ctlp == NULL) { 769 ADBG_WARN(("ata_bus_ctl: failed to find ctl struct\n")); 770 return (DDI_FAILURE); 771 } 772 773 /* get (target,lun) of child device */ 774 775 targ = ddi_prop_get_int(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 776 "target", -1); 777 if (targ == -1) { 778 ADBG_WARN(("ata_bus_ctl: failed to get targ num\n")); 779 return (DDI_FAILURE); 780 } 781 782 lun = ddi_prop_get_int(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS, 783 "lun", 0); 784 785 if ((targ < 0) || (targ >= ATA_MAXTARG) || 786 (lun < 0) || (lun >= ATA_MAXLUN)) { 787 return (DDI_FAILURE); 788 } 789 790 ata_drvp = CTL2DRV(ata_ctlp, targ, lun); 791 792 if (ata_drvp == NULL) 793 return (DDI_FAILURE); /* no drive */ 794 795 /* get type of device */ 796 797 if (ATAPIDRV(ata_drvp)) 798 drive_type = ATA_DEV_ATAPI; 799 else 800 drive_type = ATA_DEV_DISK; 801 802 /* 803 * Check for special handling when child driver is 804 * cmdk (which morphs to the correct interface) 805 */ 806 if (strcmp(ddi_get_name(tdip), "cmdk") == 0) { 807 808 if ((target_type == ATA_DEV_DISK) && 809 (target_type != drive_type)) 810 return (DDI_FAILURE); 811 812 target_type = drive_type; 813 814 if (drive_type == ATA_DEV_ATAPI) { 815 class_prop = "scsi"; 816 } else { 817 disk_prop = "dadk"; 818 class_prop = "dada"; 819 820 if (ndi_prop_update_string(DDI_DEV_T_NONE, tdip, 821 "disk", disk_prop) != DDI_PROP_SUCCESS) { 822 ADBG_WARN(("ata_bus_ctl: failed to " 823 "create disk prop\n")); 824 return (DDI_FAILURE); 825 } 826 } 827 828 if (ndi_prop_update_string(DDI_DEV_T_NONE, tdip, 829 "class_prop", class_prop) != DDI_PROP_SUCCESS) { 830 ADBG_WARN(("ata_bus_ctl: failed to " 831 "create class prop\n")); 832 return (DDI_FAILURE); 833 } 834 } 835 836 /* Check that target class matches the device */ 837 838 if (target_type != drive_type) 839 return (DDI_FAILURE); 840 841 /* save pointer to drive struct for ata_disk_bus_ctl */ 842 ddi_set_driver_private(tdip, ata_drvp); 843 844 /* 845 * Determine whether to enable DMA support for this drive. This 846 * check is deferred to this point so that the various dma 847 * properties could reside on the devinfo node should finer 848 * grained dma control be required. 849 */ 850 ata_drvp->ad_pciide_dma = ata_init_drive_pcidma(ata_ctlp, 851 ata_drvp, tdip); 852 ata_show_transfer_mode(ata_ctlp, ata_drvp); 853 } 854 855 if (target_type == ATA_DEV_ATAPI) { 856 rc = scsa_bus_ops_p->bus_ctl(d, r, o, a, v); 857 } else { 858 rc = ata_disk_bus_ctl(d, r, o, a, v); 859 } 860 861 return (rc); 862 } 863 864 /* 865 * 866 * GHD ccc_hba_complete callback 867 * 868 */ 869 870 /* ARGSUSED */ 871 static void 872 ata_hba_complete( 873 void *hba_handle, 874 gcmd_t *gcmdp, 875 int do_callback) 876 { 877 ata_drv_t *ata_drvp; 878 ata_pkt_t *ata_pktp; 879 880 ADBG_TRACE(("ata_hba_complete entered\n")); 881 882 ata_drvp = GCMD2DRV(gcmdp); 883 ata_pktp = GCMD2APKT(gcmdp); 884 if (ata_pktp->ap_complete) 885 (*ata_pktp->ap_complete)(ata_drvp, ata_pktp, 886 do_callback); 887 } 888 889 /* GHD ccc_timeout_func callback */ 890 891 /* ARGSUSED */ 892 static int 893 ata_timeout_func( 894 void *hba_handle, 895 gcmd_t *gcmdp, 896 gtgt_t *gtgtp, 897 gact_t action, 898 int calltype) 899 { 900 ata_ctl_t *ata_ctlp; 901 ata_pkt_t *ata_pktp; 902 903 ADBG_TRACE(("ata_timeout_func entered\n")); 904 905 ata_ctlp = (ata_ctl_t *)hba_handle; 906 907 if (gcmdp != NULL) 908 ata_pktp = GCMD2APKT(gcmdp); 909 else 910 ata_pktp = NULL; 911 912 switch (action) { 913 case GACTION_EARLY_ABORT: 914 /* abort before request was started */ 915 if (ata_pktp != NULL) { 916 ata_pktp->ap_flags |= AP_ABORT; 917 } 918 ghd_complete(&ata_ctlp->ac_ccc, gcmdp); 919 return (TRUE); 920 921 case GACTION_EARLY_TIMEOUT: 922 /* timeout before request was started */ 923 if (ata_pktp != NULL) { 924 ata_pktp->ap_flags |= AP_TIMEOUT; 925 } 926 ghd_complete(&ata_ctlp->ac_ccc, gcmdp); 927 return (TRUE); 928 929 case GACTION_RESET_TARGET: 930 /* 931 * Reset a device is not supported. Resetting a specific 932 * device can't be done at all to an ATA device and if 933 * you send a RESET to an ATAPI device you have to 934 * reset the whole bus to make certain both devices 935 * on the bus stay in sync regarding which device is 936 * the currently selected one. 937 */ 938 return (FALSE); 939 940 case GACTION_RESET_BUS: 941 /* 942 * Issue bus reset and reinitialize both drives. 943 * But only if this is a timed-out request. Target 944 * driver reset requests are ignored because ATA 945 * and ATAPI devices shouldn't be gratuitously reset. 946 */ 947 if (gcmdp == NULL) 948 break; 949 return (ata_reset_bus(ata_ctlp)); 950 default: 951 break; 952 } 953 return (FALSE); 954 } 955 956 /* 957 * 958 * Initialize controller's soft-state structure 959 * 960 */ 961 962 static ata_ctl_t * 963 ata_init_controller( 964 dev_info_t *dip) 965 { 966 ata_ctl_t *ata_ctlp; 967 int instance; 968 caddr_t ioaddr1; 969 caddr_t ioaddr2; 970 971 ADBG_TRACE(("ata_init_controller entered\n")); 972 973 instance = ddi_get_instance(dip); 974 975 /* allocate controller structure */ 976 if (ddi_soft_state_zalloc(ata_state, instance) != DDI_SUCCESS) { 977 ADBG_WARN(("ata_init_controller: soft_state_zalloc failed\n")); 978 return (NULL); 979 } 980 981 ata_ctlp = ddi_get_soft_state(ata_state, instance); 982 983 if (ata_ctlp == NULL) { 984 ADBG_WARN(("ata_init_controller: failed to find " 985 "controller struct\n")); 986 return (NULL); 987 } 988 989 /* 990 * initialize per-controller data 991 */ 992 ata_ctlp->ac_dip = dip; 993 ata_ctlp->ac_arq_pktp = kmem_zalloc(sizeof (ata_pkt_t), KM_SLEEP); 994 995 /* 996 * map the device registers 997 */ 998 if (!ata_setup_ioaddr(dip, &ata_ctlp->ac_iohandle1, &ioaddr1, 999 &ata_ctlp->ac_iohandle2, &ioaddr2, 1000 &ata_ctlp->ac_bmhandle, &ata_ctlp->ac_bmaddr)) { 1001 (void) ata_detach(dip, DDI_DETACH); 1002 return (NULL); 1003 } 1004 1005 ADBG_INIT(("ata_init_controller: ioaddr1 = 0x%p, ioaddr2 = 0x%p\n", 1006 ioaddr1, ioaddr2)); 1007 1008 /* 1009 * Do ARQ setup 1010 */ 1011 atapi_init_arq(ata_ctlp); 1012 1013 /* 1014 * Do PCI-IDE setup 1015 */ 1016 ata_init_pciide(dip, ata_ctlp); 1017 1018 /* 1019 * port addresses associated with ioaddr1 1020 */ 1021 ata_ctlp->ac_ioaddr1 = ioaddr1; 1022 ata_ctlp->ac_data = (ushort_t *)ioaddr1 + AT_DATA; 1023 ata_ctlp->ac_error = (uchar_t *)ioaddr1 + AT_ERROR; 1024 ata_ctlp->ac_feature = (uchar_t *)ioaddr1 + AT_FEATURE; 1025 ata_ctlp->ac_count = (uchar_t *)ioaddr1 + AT_COUNT; 1026 ata_ctlp->ac_sect = (uchar_t *)ioaddr1 + AT_SECT; 1027 ata_ctlp->ac_lcyl = (uchar_t *)ioaddr1 + AT_LCYL; 1028 ata_ctlp->ac_hcyl = (uchar_t *)ioaddr1 + AT_HCYL; 1029 ata_ctlp->ac_drvhd = (uchar_t *)ioaddr1 + AT_DRVHD; 1030 ata_ctlp->ac_status = (uchar_t *)ioaddr1 + AT_STATUS; 1031 ata_ctlp->ac_cmd = (uchar_t *)ioaddr1 + AT_CMD; 1032 1033 /* 1034 * port addresses associated with ioaddr2 1035 */ 1036 ata_ctlp->ac_ioaddr2 = ioaddr2; 1037 ata_ctlp->ac_altstatus = (uchar_t *)ioaddr2 + AT_ALTSTATUS; 1038 ata_ctlp->ac_devctl = (uchar_t *)ioaddr2 + AT_DEVCTL; 1039 1040 /* 1041 * If AC_BSY_WAIT needs to be set for laptops that do 1042 * suspend/resume but do not correctly wait for the busy bit to 1043 * drop after a resume. 1044 */ 1045 ata_ctlp->ac_timing_flags = ddi_prop_get_int(DDI_DEV_T_ANY, 1046 dip, DDI_PROP_DONTPASS, "timing_flags", 0); 1047 /* 1048 * get max transfer size, default to 256 sectors 1049 */ 1050 ata_ctlp->ac_max_transfer = ddi_prop_get_int(DDI_DEV_T_ANY, 1051 dip, DDI_PROP_DONTPASS, "max_transfer", 0x100); 1052 if (ata_ctlp->ac_max_transfer < 1) 1053 ata_ctlp->ac_max_transfer = 1; 1054 if (ata_ctlp->ac_max_transfer > 0x100) 1055 ata_ctlp->ac_max_transfer = 0x100; 1056 1057 /* 1058 * Get the standby timer value 1059 */ 1060 ata_ctlp->ac_standby_time = ddi_prop_get_int(DDI_DEV_T_ANY, 1061 dip, DDI_PROP_DONTPASS, "standby", -1); 1062 1063 /* 1064 * If this is a /pci/pci-ide instance check to see if 1065 * it's supposed to be attached as an /isa/ata 1066 */ 1067 if (ata_ctlp->ac_pciide) { 1068 static char prop_buf[] = "SUNW-ata-ffff-isa"; 1069 int addr1 = (intptr_t)ioaddr1; 1070 1071 1072 if (addr1 < 0 || addr1 > 0xffff) { 1073 (void) ata_detach(dip, DDI_DETACH); 1074 return (NULL); 1075 } 1076 (void) sprintf(prop_buf, "SUNW-ata-%04x-isa", 1077 addr1); 1078 if (ddi_prop_exists(DDI_DEV_T_ANY, ddi_root_node(), 1079 DDI_PROP_DONTPASS, prop_buf)) { 1080 (void) ata_detach(dip, DDI_DETACH); 1081 return (NULL); 1082 } 1083 } 1084 1085 /* Init controller specific stuff */ 1086 (void) ata_spec_init_controller(dip); 1087 1088 /* 1089 * initialize GHD 1090 */ 1091 1092 GHD_WAITQ_INIT(&ata_ctlp->ac_ccc.ccc_waitq, NULL, 1); 1093 1094 if (!ghd_register("ata", &ata_ctlp->ac_ccc, dip, 0, ata_ctlp, 1095 atapi_ccballoc, atapi_ccbfree, 1096 ata_pciide_dma_sg_func, ata_hba_start, 1097 ata_hba_complete, ata_intr, 1098 ata_get_status, ata_process_intr, ata_timeout_func, 1099 &ata_timer_conf, NULL)) { 1100 (void) ata_detach(dip, DDI_DETACH); 1101 return (NULL); 1102 } 1103 1104 ata_ctlp->ac_flags |= AC_GHD_INIT; 1105 return (ata_ctlp); 1106 } 1107 1108 /* destroy a controller */ 1109 1110 static void 1111 ata_destroy_controller( 1112 dev_info_t *dip) 1113 { 1114 ata_ctl_t *ata_ctlp; 1115 int instance; 1116 1117 ADBG_TRACE(("ata_destroy_controller entered\n")); 1118 1119 instance = ddi_get_instance(dip); 1120 ata_ctlp = ddi_get_soft_state(ata_state, instance); 1121 1122 if (ata_ctlp == NULL) 1123 return; 1124 1125 /* destroy ghd */ 1126 if (ata_ctlp->ac_flags & AC_GHD_INIT) 1127 ghd_unregister(&ata_ctlp->ac_ccc); 1128 1129 /* free the pciide buffer (if any) */ 1130 ata_pciide_free(ata_ctlp); 1131 1132 /* destroy controller struct */ 1133 kmem_free(ata_ctlp->ac_arq_pktp, sizeof (ata_pkt_t)); 1134 ddi_soft_state_free(ata_state, instance); 1135 1136 } 1137 1138 1139 /* 1140 * 1141 * initialize a drive 1142 * 1143 */ 1144 1145 static ata_drv_t * 1146 ata_init_drive( 1147 ata_ctl_t *ata_ctlp, 1148 uchar_t targ, 1149 uchar_t lun) 1150 { 1151 static char nec_260[] = "NEC CD-ROM DRIVE"; 1152 ata_drv_t *ata_drvp; 1153 struct ata_id *aidp; 1154 char buf[80]; 1155 int drive_type; 1156 int i; 1157 int valid_version = 0; 1158 1159 ADBG_TRACE(("ata_init_drive entered, targ = %d, lun = %d\n", 1160 targ, lun)); 1161 1162 /* check if device already exists */ 1163 1164 ata_drvp = CTL2DRV(ata_ctlp, targ, lun); 1165 1166 if (ata_drvp != NULL) 1167 return (ata_drvp); 1168 1169 /* allocate new device structure */ 1170 1171 ata_drvp = kmem_zalloc(sizeof (ata_drv_t), KM_SLEEP); 1172 aidp = &ata_drvp->ad_id; 1173 1174 /* 1175 * set up drive struct 1176 */ 1177 ata_drvp->ad_ctlp = ata_ctlp; 1178 ata_drvp->ad_targ = targ; 1179 ata_drvp->ad_drive_bits = 1180 (ata_drvp->ad_targ == 0 ? ATDH_DRIVE0 : ATDH_DRIVE1); 1181 /* 1182 * Add the LUN for SFF-8070i support 1183 */ 1184 ata_drvp->ad_lun = lun; 1185 ata_drvp->ad_drive_bits |= ata_drvp->ad_lun; 1186 1187 /* 1188 * get drive type, side effect is to collect 1189 * IDENTIFY DRIVE data 1190 */ 1191 1192 drive_type = ata_drive_type(ata_drvp->ad_drive_bits, 1193 ata_ctlp->ac_iohandle1, 1194 ata_ctlp->ac_ioaddr1, 1195 ata_ctlp->ac_iohandle2, 1196 ata_ctlp->ac_ioaddr2, 1197 aidp); 1198 1199 switch (drive_type) { 1200 case ATA_DEV_NONE: 1201 /* no drive found */ 1202 goto errout; 1203 case ATA_DEV_ATAPI: 1204 ata_drvp->ad_flags |= AD_ATAPI; 1205 break; 1206 case ATA_DEV_DISK: 1207 ata_drvp->ad_flags |= AD_DISK; 1208 break; 1209 } 1210 1211 /* 1212 * swap bytes of all text fields 1213 */ 1214 if (!ata_strncmp(nec_260, aidp->ai_model, sizeof (aidp->ai_model))) { 1215 swab(aidp->ai_drvser, aidp->ai_drvser, 1216 sizeof (aidp->ai_drvser)); 1217 swab(aidp->ai_fw, aidp->ai_fw, 1218 sizeof (aidp->ai_fw)); 1219 swab(aidp->ai_model, aidp->ai_model, 1220 sizeof (aidp->ai_model)); 1221 } 1222 1223 /* 1224 * Check if this drive has the Single Sector bug 1225 */ 1226 1227 if (ata_check_drive_blacklist(&ata_drvp->ad_id, ATA_BL_1SECTOR)) 1228 ata_drvp->ad_flags |= AD_1SECTOR; 1229 else 1230 ata_drvp->ad_flags &= ~AD_1SECTOR; 1231 1232 /* Check if this drive has the "revert to defaults" bug */ 1233 if (!ata_check_revert_to_defaults(ata_drvp)) 1234 ata_drvp->ad_flags |= AD_NORVRT; 1235 1236 /* Dump the drive info */ 1237 (void) strncpy(buf, aidp->ai_model, sizeof (aidp->ai_model)); 1238 buf[sizeof (aidp->ai_model)-1] = '\0'; 1239 for (i = sizeof (aidp->ai_model) - 2; buf[i] == ' '; i--) 1240 buf[i] = '\0'; 1241 1242 ATAPRT(("?\t%s device at targ %d, lun %d lastlun 0x%x\n", 1243 (ATAPIDRV(ata_drvp) ? "ATAPI":"IDE"), 1244 ata_drvp->ad_targ, ata_drvp->ad_lun, aidp->ai_lastlun)); 1245 1246 ATAPRT(("?\tmodel %s\n", buf)); 1247 1248 if (aidp->ai_majorversion != 0 && aidp->ai_majorversion != 0xffff) { 1249 for (i = 14; i >= 2; i--) { 1250 if (aidp->ai_majorversion & (1 << i)) { 1251 valid_version = i; 1252 break; 1253 } 1254 } 1255 ATAPRT(( 1256 "?\tATA/ATAPI-%d supported, majver 0x%x minver 0x%x\n", 1257 valid_version, 1258 aidp->ai_majorversion, 1259 aidp->ai_minorversion)); 1260 } 1261 1262 if (ata_capability_data) { 1263 1264 ATAPRT(("?\t\tstat %x, err %x\n", 1265 ddi_get8(ata_ctlp->ac_iohandle2, 1266 ata_ctlp->ac_altstatus), 1267 ddi_get8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_error))); 1268 1269 ATAPRT(("?\t\tcfg 0x%x, cap 0x%x\n", 1270 aidp->ai_config, 1271 aidp->ai_cap)); 1272 1273 /* 1274 * Be aware that ATA-6 and later drives may not provide valid 1275 * geometry information and other obsoleted info. 1276 * Select what is printed based on supported ATA model (skip 1277 * anything below ATA/ATAPI-3) 1278 */ 1279 1280 if (valid_version == 0 || aidp->ai_majorversion < 1281 ATAC_MAJVER_6) { 1282 /* 1283 * Supported version less then ATA-6 1284 */ 1285 ATAPRT(("?\t\tcyl %d, hd %d, sec/trk %d\n", 1286 aidp->ai_fixcyls, 1287 aidp->ai_heads, 1288 aidp->ai_sectors)); 1289 } 1290 ATAPRT(("?\t\tmult1 0x%x, mult2 0x%x\n", 1291 aidp->ai_mult1, 1292 aidp->ai_mult2)); 1293 if (valid_version && aidp->ai_majorversion < ATAC_MAJVER_4) { 1294 ATAPRT(( 1295 "?\t\tpiomode 0x%x, dmamode 0x%x, advpiomode 0x%x\n", 1296 aidp->ai_piomode, 1297 aidp->ai_dmamode, 1298 aidp->ai_advpiomode)); 1299 } else { 1300 ATAPRT(("?\t\tadvpiomode 0x%x\n", 1301 aidp->ai_advpiomode)); 1302 } 1303 ATAPRT(("?\t\tminpio %d, minpioflow %d\n", 1304 aidp->ai_minpio, 1305 aidp->ai_minpioflow)); 1306 if (valid_version && aidp->ai_majorversion >= ATAC_MAJVER_4 && 1307 (aidp->ai_validinfo & ATAC_VALIDINFO_83)) { 1308 ATAPRT(("?\t\tdwdma 0x%x, ultradma 0x%x\n", 1309 aidp->ai_dworddma, 1310 aidp->ai_ultradma)); 1311 } else { 1312 ATAPRT(("?\t\tdwdma 0x%x\n", 1313 aidp->ai_dworddma)); 1314 } 1315 } 1316 1317 if (ATAPIDRV(ata_drvp)) { 1318 if (!atapi_init_drive(ata_drvp)) 1319 goto errout; 1320 } else { 1321 if (!ata_disk_init_drive(ata_drvp)) 1322 goto errout; 1323 } 1324 1325 /* 1326 * store pointer in controller struct 1327 */ 1328 CTL2DRV(ata_ctlp, targ, lun) = ata_drvp; 1329 1330 /* 1331 * lock the drive's current settings in case I have to 1332 * reset the drive due to some sort of error 1333 */ 1334 (void) ata_set_feature(ata_ctlp, ata_drvp, 0x66, 0); 1335 1336 return (ata_drvp); 1337 1338 errout: 1339 ata_uninit_drive(ata_drvp); 1340 return (NULL); 1341 } 1342 1343 /* destroy a drive */ 1344 1345 static void 1346 ata_uninit_drive( 1347 ata_drv_t *ata_drvp) 1348 { 1349 #if 0 1350 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp; 1351 #endif 1352 1353 ADBG_TRACE(("ata_uninit_drive entered\n")); 1354 1355 #if 0 1356 /* 1357 * DON'T DO THIS. disabling interrupts floats the IRQ line 1358 * which generates spurious interrupts 1359 */ 1360 1361 /* 1362 * Select the correct drive 1363 */ 1364 ddi_put8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_drvhd, 1365 ata_drvp->ad_drive_bits); 1366 ATA_DELAY_400NSEC(ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2); 1367 1368 /* 1369 * Disable interrupts from the drive 1370 */ 1371 ddi_put8(ata_ctlp->ac_iohandle2, ata_ctlp->ac_devctl, 1372 (ATDC_D3 | ATDC_NIEN)); 1373 #endif 1374 1375 /* interface specific clean-ups */ 1376 1377 if (ata_drvp->ad_flags & AD_ATAPI) 1378 atapi_uninit_drive(ata_drvp); 1379 else if (ata_drvp->ad_flags & AD_DISK) 1380 ata_disk_uninit_drive(ata_drvp); 1381 1382 /* free drive struct */ 1383 1384 kmem_free(ata_drvp, sizeof (ata_drv_t)); 1385 } 1386 1387 1388 /* 1389 * ata_drive_type() 1390 * 1391 * The timeout values and exact sequence of checking is critical 1392 * especially for atapi device detection, and should not be changed lightly. 1393 * 1394 */ 1395 static int 1396 ata_drive_type( 1397 uchar_t drvhd, 1398 ddi_acc_handle_t io_hdl1, 1399 caddr_t ioaddr1, 1400 ddi_acc_handle_t io_hdl2, 1401 caddr_t ioaddr2, 1402 struct ata_id *ata_id_bufp) 1403 { 1404 uchar_t status; 1405 1406 ADBG_TRACE(("ata_drive_type entered\n")); 1407 1408 /* 1409 * select the appropriate drive and LUN 1410 */ 1411 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_DRVHD, drvhd); 1412 ATA_DELAY_400NSEC(io_hdl2, ioaddr2); 1413 1414 /* 1415 * make certain the drive is selected, and wait for not busy 1416 */ 1417 (void) ata_wait3(io_hdl2, ioaddr2, 0, ATS_BSY, 0x7f, 0, 0x7f, 0, 1418 5 * 1000000); 1419 1420 status = ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS); 1421 1422 if (status & ATS_BSY) { 1423 ADBG_TRACE(("ata_drive_type BUSY 0x%p 0x%x\n", 1424 ioaddr1, status)); 1425 return (ATA_DEV_NONE); 1426 } 1427 1428 if (ata_disk_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) 1429 return (ATA_DEV_DISK); 1430 1431 /* 1432 * No disk, check for atapi unit. 1433 */ 1434 if (!atapi_signature(io_hdl1, ioaddr1)) { 1435 #ifndef ATA_DISABLE_ATAPI_1_7 1436 /* 1437 * Check for old (but prevalent) atapi 1.7B 1438 * spec device, the only known example is the 1439 * NEC CDR-260 (not 260R which is (mostly) ATAPI 1.2 1440 * compliant). This device has no signature 1441 * and requires conversion from hex to BCD 1442 * for some scsi audio commands. 1443 */ 1444 if (atapi_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) { 1445 return (ATA_DEV_ATAPI); 1446 } 1447 #endif 1448 return (ATA_DEV_NONE); 1449 } 1450 1451 if (atapi_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) { 1452 return (ATA_DEV_ATAPI); 1453 } 1454 1455 return (ATA_DEV_NONE); 1456 1457 } 1458 1459 /* 1460 * Wait for a register of a controller to achieve a specific state. 1461 * To return normally, all the bits in the first sub-mask must be ON, 1462 * all the bits in the second sub-mask must be OFF. 1463 * If timeout_usec microseconds pass without the controller achieving 1464 * the desired bit configuration, we return TRUE, else FALSE. 1465 */ 1466 1467 int ata_usec_delay = 10; 1468 1469 int 1470 ata_wait( 1471 ddi_acc_handle_t io_hdl, 1472 caddr_t ioaddr, 1473 uchar_t onbits, 1474 uchar_t offbits, 1475 uint_t timeout_usec) 1476 { 1477 ushort_t val; 1478 1479 do { 1480 val = ddi_get8(io_hdl, (uchar_t *)ioaddr + AT_ALTSTATUS); 1481 if ((val & onbits) == onbits && (val & offbits) == 0) 1482 return (TRUE); 1483 drv_usecwait(ata_usec_delay); 1484 timeout_usec -= ata_usec_delay; 1485 } while (timeout_usec > 0); 1486 1487 return (FALSE); 1488 } 1489 1490 1491 1492 /* 1493 * 1494 * This is a slightly more complicated version that checks 1495 * for error conditions and bails-out rather than looping 1496 * until the timeout expires 1497 */ 1498 int 1499 ata_wait3( 1500 ddi_acc_handle_t io_hdl, 1501 caddr_t ioaddr, 1502 uchar_t onbits1, 1503 uchar_t offbits1, 1504 uchar_t failure_onbits2, 1505 uchar_t failure_offbits2, 1506 uchar_t failure_onbits3, 1507 uchar_t failure_offbits3, 1508 uint_t timeout_usec) 1509 { 1510 ushort_t val; 1511 1512 do { 1513 val = ddi_get8(io_hdl, (uchar_t *)ioaddr + AT_ALTSTATUS); 1514 1515 /* 1516 * check for expected condition 1517 */ 1518 if ((val & onbits1) == onbits1 && (val & offbits1) == 0) 1519 return (TRUE); 1520 1521 /* 1522 * check for error conditions 1523 */ 1524 if ((val & failure_onbits2) == failure_onbits2 && 1525 (val & failure_offbits2) == 0) { 1526 return (FALSE); 1527 } 1528 1529 if ((val & failure_onbits3) == failure_onbits3 && 1530 (val & failure_offbits3) == 0) { 1531 return (FALSE); 1532 } 1533 1534 drv_usecwait(ata_usec_delay); 1535 timeout_usec -= ata_usec_delay; 1536 } while (timeout_usec > 0); 1537 1538 return (FALSE); 1539 } 1540 1541 1542 /* 1543 * 1544 * low level routine for ata_disk_id() and atapi_id() 1545 * 1546 */ 1547 1548 int 1549 ata_id_common( 1550 uchar_t id_cmd, 1551 int expect_drdy, 1552 ddi_acc_handle_t io_hdl1, 1553 caddr_t ioaddr1, 1554 ddi_acc_handle_t io_hdl2, 1555 caddr_t ioaddr2, 1556 struct ata_id *aidp) 1557 { 1558 uchar_t status; 1559 1560 ADBG_TRACE(("ata_id_common entered\n")); 1561 1562 bzero(aidp, sizeof (struct ata_id)); 1563 1564 /* 1565 * clear the features register 1566 */ 1567 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_FEATURE, 0); 1568 1569 /* 1570 * enable interrupts from the device 1571 */ 1572 ddi_put8(io_hdl2, (uchar_t *)ioaddr2 + AT_DEVCTL, ATDC_D3); 1573 1574 /* 1575 * issue IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command 1576 */ 1577 ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_CMD, id_cmd); 1578 1579 /* wait for the busy bit to settle */ 1580 ATA_DELAY_400NSEC(io_hdl2, ioaddr2); 1581 1582 /* 1583 * According to the ATA specification, some drives may have 1584 * to read the media to complete this command. We need to 1585 * make sure we give them enough time to respond. 1586 */ 1587 1588 (void) ata_wait3(io_hdl2, ioaddr2, 0, ATS_BSY, 1589 ATS_ERR, ATS_BSY, 0x7f, 0, 5 * 1000000); 1590 1591 /* 1592 * read the status byte and clear the pending interrupt 1593 */ 1594 status = ddi_get8(io_hdl2, (uchar_t *)ioaddr1 + AT_STATUS); 1595 1596 /* 1597 * this happens if there's no drive present 1598 */ 1599 if (status == 0xff || status == 0x7f) { 1600 /* invalid status, can't be an ATA or ATAPI device */ 1601 return (FALSE); 1602 } 1603 1604 if (status & ATS_BSY) { 1605 ADBG_ERROR(("ata_id_common: BUSY status 0x%x error 0x%x\n", 1606 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 +AT_ALTSTATUS), 1607 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1608 return (FALSE); 1609 } 1610 1611 if (!(status & ATS_DRQ)) { 1612 if (status & (ATS_ERR | ATS_DF)) { 1613 return (FALSE); 1614 } 1615 /* 1616 * Give the drive another second to assert DRQ. Some older 1617 * drives de-assert BSY before asserting DRQ. 1618 */ 1619 if (!ata_wait(io_hdl2, ioaddr2, ATS_DRQ, ATS_BSY, 1000000)) { 1620 ADBG_WARN(("ata_id_common: !DRQ status 0x%x error 0x%x\n", 1621 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 +AT_ALTSTATUS), 1622 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1623 return (FALSE); 1624 } 1625 } 1626 1627 /* 1628 * transfer the data 1629 */ 1630 ddi_rep_get16(io_hdl1, (ushort_t *)aidp, (ushort_t *)ioaddr1 + AT_DATA, 1631 NBPSCTR >> 1, DDI_DEV_NO_AUTOINCR); 1632 1633 /* wait for the busy bit to settle */ 1634 ATA_DELAY_400NSEC(io_hdl2, ioaddr2); 1635 1636 1637 /* 1638 * Wait for the drive to recognize I've read all the data. 1639 * Some drives have been observed to take as much as 3msec to 1640 * deassert DRQ after reading the data; allow 10 msec just in case. 1641 * 1642 * Note: some non-compliant ATAPI drives (e.g., NEC Multispin 6V, 1643 * CDR-1350A) don't assert DRDY. If we've made it this far we can 1644 * safely ignore the DRDY bit since the ATAPI Packet command 1645 * actually doesn't require it to ever be asserted. 1646 * 1647 */ 1648 if (!ata_wait(io_hdl2, ioaddr2, (uchar_t)(expect_drdy ? ATS_DRDY : 0), 1649 (ATS_BSY | ATS_DRQ), 1000000)) { 1650 ADBG_WARN(("ata_id_common: bad status 0x%x error 0x%x\n", 1651 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS), 1652 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1653 return (FALSE); 1654 } 1655 1656 /* 1657 * Check to see if the command aborted. This happens if 1658 * an IDENTIFY DEVICE command is issued to an ATAPI PACKET device, 1659 * or if an IDENTIFY PACKET DEVICE command is issued to an ATA 1660 * (non-PACKET) device. 1661 */ 1662 if (status & (ATS_DF | ATS_ERR)) { 1663 ADBG_WARN(("ata_id_common: status 0x%x error 0x%x \n", 1664 ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS), 1665 ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR))); 1666 return (FALSE); 1667 } 1668 return (TRUE); 1669 } 1670 1671 1672 /* 1673 * Low level routine to issue a non-data command and busy wait for 1674 * the completion status. 1675 */ 1676 1677 int 1678 ata_command( 1679 ata_ctl_t *ata_ctlp, 1680 ata_drv_t *ata_drvp, 1681 int expect_drdy, 1682 int silent, 1683 uint_t busy_wait, 1684 uchar_t cmd, 1685 uchar_t feature, 1686 uchar_t count, 1687 uchar_t sector, 1688 uchar_t head, 1689 uchar_t cyl_low, 1690 uchar_t cyl_hi) 1691 { 1692 ddi_acc_handle_t io_hdl1 = ata_ctlp->ac_iohandle1; 1693 ddi_acc_handle_t io_hdl2 = ata_ctlp->ac_iohandle2; 1694 uchar_t status; 1695 1696 /* select the drive */ 1697 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, ata_drvp->ad_drive_bits); 1698 ATA_DELAY_400NSEC(io_hdl2, ata_ctlp->ac_ioaddr2); 1699 1700 /* make certain the drive selected */ 1701 if (!ata_wait(io_hdl2, ata_ctlp->ac_ioaddr2, 1702 (uchar_t)(expect_drdy ? ATS_DRDY : 0), 1703 ATS_BSY, busy_wait)) { 1704 ADBG_ERROR(("ata_command: select failed " 1705 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x " 1706 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n", 1707 expect_drdy, cmd, feature, count, 1708 sector, head, cyl_low, cyl_hi)); 1709 return (FALSE); 1710 } 1711 1712 /* 1713 * set all the regs 1714 */ 1715 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, (head | ata_drvp->ad_drive_bits)); 1716 ddi_put8(io_hdl1, ata_ctlp->ac_sect, sector); 1717 ddi_put8(io_hdl1, ata_ctlp->ac_count, count); 1718 ddi_put8(io_hdl1, ata_ctlp->ac_lcyl, cyl_low); 1719 ddi_put8(io_hdl1, ata_ctlp->ac_hcyl, cyl_hi); 1720 ddi_put8(io_hdl1, ata_ctlp->ac_feature, feature); 1721 1722 /* send the command */ 1723 ddi_put8(io_hdl1, ata_ctlp->ac_cmd, cmd); 1724 1725 /* wait for the busy bit to settle */ 1726 ATA_DELAY_400NSEC(io_hdl2, ata_ctlp->ac_ioaddr2); 1727 1728 /* wait for not busy */ 1729 if (!ata_wait(io_hdl2, ata_ctlp->ac_ioaddr2, 0, ATS_BSY, busy_wait)) { 1730 ADBG_ERROR(("ata_command: BSY too long!" 1731 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x " 1732 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n", 1733 expect_drdy, cmd, feature, count, 1734 sector, head, cyl_low, cyl_hi)); 1735 return (FALSE); 1736 } 1737 1738 /* 1739 * wait for DRDY before continuing 1740 */ 1741 (void) ata_wait3(io_hdl2, ata_ctlp->ac_ioaddr2, 1742 ATS_DRDY, ATS_BSY, /* okay */ 1743 ATS_ERR, ATS_BSY, /* cmd failed */ 1744 ATS_DF, ATS_BSY, /* drive failed */ 1745 busy_wait); 1746 1747 /* read status to clear IRQ, and check for error */ 1748 status = ddi_get8(io_hdl1, ata_ctlp->ac_status); 1749 1750 if ((status & (ATS_BSY | ATS_DF | ATS_ERR)) == 0) 1751 return (TRUE); 1752 1753 if (!silent) { 1754 ADBG_ERROR(("ata_command status 0x%x error 0x%x " 1755 "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x " 1756 "S 0x%x H 0x%x CL 0x%x CH 0x%x\n", 1757 ddi_get8(io_hdl1, ata_ctlp->ac_status), 1758 ddi_get8(io_hdl1, ata_ctlp->ac_error), 1759 expect_drdy, cmd, feature, count, 1760 sector, head, cyl_low, cyl_hi)); 1761 } 1762 return (FALSE); 1763 } 1764 1765 1766 1767 /* 1768 * 1769 * Issue a SET FEATURES command 1770 * 1771 */ 1772 1773 int 1774 ata_set_feature( 1775 ata_ctl_t *ata_ctlp, 1776 ata_drv_t *ata_drvp, 1777 uchar_t feature, 1778 uchar_t value) 1779 { 1780 int rc; 1781 1782 rc = ata_command(ata_ctlp, ata_drvp, TRUE, TRUE, ata_set_feature_wait, 1783 ATC_SET_FEAT, feature, value, 0, 0, 0, 0); 1784 /* feature, count, sector, head, cyl_low, cyl_hi */ 1785 1786 if (rc) { 1787 return (TRUE); 1788 } 1789 1790 ADBG_ERROR(("?ata_set_feature: (0x%x,0x%x) failed\n", feature, value)); 1791 return (FALSE); 1792 } 1793 1794 1795 1796 /* 1797 * 1798 * Issue a FLUSH CACHE command 1799 * 1800 */ 1801 1802 static int 1803 ata_flush_cache( 1804 ata_ctl_t *ata_ctlp, 1805 ata_drv_t *ata_drvp) 1806 { 1807 /* this command is optional so fail silently */ 1808 return (ata_command(ata_ctlp, ata_drvp, TRUE, TRUE, 1809 ata_flush_cache_wait, 1810 ATC_FLUSH_CACHE, 0, 0, 0, 0, 0, 0)); 1811 } 1812 1813 /* 1814 * ata_setup_ioaddr() 1815 * 1816 * Map the device registers and return the handles. 1817 * 1818 * If this is a ISA-ATA controller then only two handles are 1819 * initialized and returned. 1820 * 1821 * If this is a PCI-IDE controller than a third handle (for the 1822 * PCI-IDE Bus Mastering registers) is initialized and returned. 1823 * 1824 */ 1825 1826 static int 1827 ata_setup_ioaddr( 1828 dev_info_t *dip, 1829 ddi_acc_handle_t *handle1p, 1830 caddr_t *addr1p, 1831 ddi_acc_handle_t *handle2p, 1832 caddr_t *addr2p, 1833 ddi_acc_handle_t *bm_hdlp, 1834 caddr_t *bm_addrp) 1835 { 1836 ddi_device_acc_attr_t dev_attr; 1837 char *bufp; 1838 int rnumber; 1839 int rc; 1840 off_t regsize; 1841 1842 /* 1843 * Make certain the controller is enabled and its regs are map-able 1844 * 1845 */ 1846 rc = ddi_dev_regsize(dip, 0, ®size); 1847 if (rc != DDI_SUCCESS || regsize <= AT_CMD) { 1848 ADBG_INIT(("ata_setup_ioaddr(1): rc %d regsize %lld\n", 1849 rc, (long long)regsize)); 1850 return (FALSE); 1851 } 1852 1853 rc = ddi_dev_regsize(dip, 1, ®size); 1854 if (rc != DDI_SUCCESS || regsize <= AT_ALTSTATUS) { 1855 ADBG_INIT(("ata_setup_ioaddr(2): rc %d regsize %lld\n", 1856 rc, (long long)regsize)); 1857 return (FALSE); 1858 } 1859 1860 /* 1861 * setup the device attribute structure for little-endian, 1862 * strict ordering access. 1863 */ 1864 dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 1865 dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 1866 dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1867 1868 *handle1p = NULL; 1869 *handle2p = NULL; 1870 *bm_hdlp = NULL; 1871 1872 /* 1873 * Determine whether this is a ISA, PNP-ISA, or PCI-IDE device 1874 */ 1875 if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "pnp-csn")) { 1876 /* it's PNP-ISA, skip over the extra reg tuple */ 1877 rnumber = 1; 1878 goto not_pciide; 1879 } 1880 1881 /* else, it's ISA or PCI-IDE, check further */ 1882 rnumber = 0; 1883 1884 rc = ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_get_parent(dip), 1885 DDI_PROP_DONTPASS, "device_type", &bufp); 1886 if (rc != DDI_PROP_SUCCESS) { 1887 ADBG_ERROR(("ata_setup_ioaddr !device_type\n")); 1888 goto not_pciide; 1889 } 1890 1891 if (strcmp(bufp, "pci-ide") != 0) { 1892 /* 1893 * If it's not a PCI-IDE, there are only two reg tuples 1894 * and the first one contains the I/O base (170 or 1f0) 1895 * rather than the controller instance number. 1896 */ 1897 ADBG_TRACE(("ata_setup_ioaddr !pci-ide\n")); 1898 ddi_prop_free(bufp); 1899 goto not_pciide; 1900 } 1901 ddi_prop_free(bufp); 1902 1903 1904 /* 1905 * Map the correct half of the PCI-IDE Bus Master registers. 1906 * There's a single BAR that maps these registers for both 1907 * controller's in a dual-controller chip and it's upto my 1908 * parent nexus, pciide, to adjust which (based on my instance 1909 * number) half this call maps. 1910 */ 1911 rc = ddi_dev_regsize(dip, 2, ®size); 1912 if (rc != DDI_SUCCESS || regsize < 8) { 1913 ADBG_INIT(("ata_setup_ioaddr(3): rc %d regsize %lld\n", 1914 rc, (long long)regsize)); 1915 goto not_pciide; 1916 } 1917 1918 rc = ddi_regs_map_setup(dip, 2, bm_addrp, 0, 0, &dev_attr, bm_hdlp); 1919 1920 if (rc != DDI_SUCCESS) { 1921 /* map failed, try to use in non-pci-ide mode */ 1922 ADBG_WARN(("ata_setup_ioaddr bus master map failed, rc=0x%x\n", 1923 rc)); 1924 *bm_hdlp = NULL; 1925 } 1926 1927 not_pciide: 1928 /* 1929 * map the lower command block registers 1930 */ 1931 1932 rc = ddi_regs_map_setup(dip, rnumber, addr1p, 0, 0, &dev_attr, 1933 handle1p); 1934 1935 if (rc != DDI_SUCCESS) { 1936 cmn_err(CE_WARN, "ata: reg tuple 0 map failed, rc=0x%x\n", rc); 1937 goto out1; 1938 } 1939 1940 /* 1941 * If the controller is being used in compatibility mode 1942 * via /devices/isa/ata@1,{1f0,1f0}/..., the reg property 1943 * will specify zeros for the I/O ports for the PCI 1944 * instance. 1945 */ 1946 if (*addr1p == 0) { 1947 ADBG_TRACE(("ata_setup_ioaddr ioaddr1 0\n")); 1948 goto out2; 1949 } 1950 1951 /* 1952 * map the upper control block registers 1953 */ 1954 rc = ddi_regs_map_setup(dip, rnumber + 1, addr2p, 0, 0, &dev_attr, 1955 handle2p); 1956 if (rc == DDI_SUCCESS) 1957 return (TRUE); 1958 1959 cmn_err(CE_WARN, "ata: reg tuple 1 map failed, rc=0x%x", rc); 1960 1961 out2: 1962 if (*handle1p != NULL) { 1963 ddi_regs_map_free(handle1p); 1964 *handle1p = NULL; 1965 } 1966 1967 out1: 1968 if (*bm_hdlp != NULL) { 1969 ddi_regs_map_free(bm_hdlp); 1970 *bm_hdlp = NULL; 1971 } 1972 return (FALSE); 1973 1974 } 1975 1976 /* 1977 * 1978 * Currently, the only supported controllers are ones which 1979 * support the SFF-8038 Bus Mastering spec. 1980 * 1981 * Check the parent node's IEEE 1275 class-code property to 1982 * determine if it's an PCI-IDE instance which supports SFF-8038 1983 * Bus Mastering. It's perfectly valid to have a PCI-IDE controller 1984 * that doesn't do Bus Mastering. In that case, my interrupt handler 1985 * only uses the interrupt latch bit in PCI-IDE status register. 1986 * The assumption is that the programming interface byte of the 1987 * class-code property reflects the bus master DMA capability of 1988 * the controller. 1989 * 1990 * Whether the drive support supports the DMA option still needs 1991 * to be checked later. Each individual request also has to be 1992 * checked for alignment and size to decide whether to use the 1993 * DMA transfer mode. 1994 */ 1995 1996 static void 1997 ata_init_pciide( 1998 dev_info_t *dip, 1999 ata_ctl_t *ata_ctlp) 2000 { 2001 uint_t class_code; 2002 uchar_t status; 2003 2004 ata_cntrl_DMA_sel_msg = NULL; 2005 2006 if (ata_ctlp->ac_bmhandle == NULL) { 2007 ata_ctlp->ac_pciide = FALSE; 2008 ata_ctlp->ac_pciide_bm = FALSE; 2009 ata_cntrl_DMA_sel_msg = "cntrl not Bus Master DMA capable"; 2010 return; 2011 } 2012 2013 /* 2014 * check if it's a known bogus PCI-IDE chip 2015 */ 2016 if (ata_check_pciide_blacklist(dip, ATA_BL_BOGUS)) { 2017 ADBG_WARN(("ata_setup_ioaddr pci-ide blacklist\n")); 2018 ata_ctlp->ac_pciide = FALSE; 2019 ata_ctlp->ac_pciide_bm = FALSE; 2020 ata_cntrl_DMA_sel_msg = "cntrl blacklisted"; 2021 return; 2022 } 2023 ata_ctlp->ac_pciide = TRUE; 2024 2025 if (ata_check_pciide_blacklist(dip, ATA_BL_BMSTATREG_PIO_BROKEN)) { 2026 ata_ctlp->ac_flags |= AC_BMSTATREG_PIO_BROKEN; 2027 } 2028 2029 /* 2030 * check for a PCI-IDE chip with a broken DMA engine 2031 */ 2032 if (ata_check_pciide_blacklist(dip, ATA_BL_NODMA)) { 2033 ata_ctlp->ac_pciide_bm = FALSE; 2034 ata_cntrl_DMA_sel_msg = 2035 "cntrl blacklisted/DMA engine broken"; 2036 return; 2037 } 2038 2039 /* 2040 * Check the Programming Interface register to determine 2041 * if this device supports PCI-IDE Bus Mastering. Some PCI-IDE 2042 * devices don't support Bus Mastering or DMA. 2043 * Since we are dealing with pre-qualified pci-ide controller, 2044 * check programming interface byte only. 2045 */ 2046 2047 class_code = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 2048 DDI_PROP_DONTPASS, "class-code", 0); 2049 if ((class_code & PCIIDE_BM_CAP_MASK) != PCIIDE_BM_CAP_MASK) { 2050 ata_ctlp->ac_pciide_bm = FALSE; 2051 ata_cntrl_DMA_sel_msg = 2052 "cntrl not Bus Master DMA capable"; 2053 return; 2054 } 2055 2056 /* 2057 * Avoid doing DMA on "simplex" chips which share hardware 2058 * between channels 2059 */ 2060 status = ddi_get8(ata_ctlp->ac_bmhandle, 2061 (uchar_t *)ata_ctlp->ac_bmaddr + PCIIDE_BMISX_REG); 2062 /* 2063 * Some motherboards have CSB5's that are wired "to emulate CSB4 mode". 2064 * In such a mode, the simplex bit is asserted, but in fact testing 2065 * on such a motherboard has shown that the devices are not simplex 2066 * -- DMA can be used on both channels concurrently with no special 2067 * considerations. For chips like this, we have the ATA_BL_NO_SIMPLEX 2068 * flag set to indicate that the value of the simplex bit can be 2069 * ignored. 2070 */ 2071 2072 if (status & PCIIDE_BMISX_SIMPLEX) { 2073 if (ata_check_pciide_blacklist(dip, ATA_BL_NO_SIMPLEX)) { 2074 cmn_err(CE_WARN, "Ignoring false simplex bit \n"); 2075 2076 } else { 2077 2078 int simplex_dma_channel, *rp, proplen, channel; 2079 int dma_on = FALSE; 2080 2081 /* 2082 * By default,use DMA on channel 0 and PIO on channel 2083 * 1. This can be switched by setting 2084 * ata-simplex-dma-channel to: 2085 * 0 DMA on channel 0 (default without this 2086 * property) 2087 * 1 DMA on channel 1 2088 * any other value: DMA off on both channels. 2089 */ 2090 simplex_dma_channel = ata_prop_lookup_int(DDI_DEV_T_ANY, 2091 ata_ctlp->ac_dip, 0, "ata-simplex-dma-channel", 0); 2092 2093 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, 2094 ata_ctlp->ac_dip, DDI_PROP_DONTPASS, "reg", &rp, 2095 (uint_t *)&proplen) == DDI_PROP_SUCCESS) { 2096 2097 channel = *rp; 2098 ddi_prop_free(rp); 2099 2100 if (simplex_dma_channel == channel) { 2101 cmn_err(CE_NOTE, "?ata: simplex " 2102 "controller. DMA on channel" 2103 " %d PIO on channel %d\n", 2104 channel, channel ? 0:1); 2105 dma_on = TRUE; 2106 } else { 2107 ata_cntrl_DMA_sel_msg = 2108 "simplex controller"; 2109 } 2110 } 2111 2112 if (dma_on == FALSE) { 2113 ata_ctlp->ac_pciide_bm = FALSE; 2114 2115 return; 2116 } 2117 } 2118 } 2119 2120 /* 2121 * It's a compatible PCI-IDE Bus Mastering controller, 2122 * allocate and map the DMA Scatter/Gather list (PRDE table). 2123 */ 2124 if (ata_pciide_alloc(dip, ata_ctlp)) 2125 ata_ctlp->ac_pciide_bm = TRUE; 2126 else { 2127 ata_ctlp->ac_pciide_bm = FALSE; 2128 ata_cntrl_DMA_sel_msg = "unable to init DMA S/G list"; 2129 } 2130 } 2131 2132 /* 2133 * 2134 * Determine whether to enable DMA support for this drive. 2135 * The controller and the drive both have to support DMA. 2136 * The controller's capabilities were already checked in 2137 * ata_init_pciide(), now just check the drive's capabilities. 2138 * 2139 */ 2140 2141 static int 2142 ata_init_drive_pcidma( 2143 ata_ctl_t *ata_ctlp, 2144 ata_drv_t *ata_drvp, 2145 dev_info_t *tdip) 2146 { 2147 boolean_t dma; 2148 boolean_t cd_dma; 2149 boolean_t disk_dma; 2150 boolean_t atapi_dma; 2151 int ata_options; 2152 2153 ata_dev_DMA_sel_msg = NULL; 2154 2155 if (ata_ctlp->ac_pciide_bm != TRUE) { 2156 ata_dev_DMA_sel_msg = 2157 "controller is not Bus Master capable"; 2158 2159 return (ATA_DMA_OFF); 2160 } 2161 2162 ata_options = ddi_prop_get_int(DDI_DEV_T_ANY, ata_ctlp->ac_dip, 2163 0, "ata-options", 0); 2164 2165 if (!(ata_options & ATA_OPTIONS_DMA)) { 2166 /* 2167 * Either the ata-options property was not found or 2168 * DMA is not enabled by this property 2169 */ 2170 ata_dev_DMA_sel_msg = 2171 "disabled by \"ata-options\" property"; 2172 2173 return (ATA_DMA_OFF); 2174 } 2175 2176 if (ata_check_drive_blacklist(&ata_drvp->ad_id, ATA_BL_NODMA)) { 2177 ata_dev_DMA_sel_msg = "device not DMA capable; blacklisted"; 2178 2179 return (ATA_DMA_OFF); 2180 } 2181 2182 /* 2183 * DMA mode is mandatory on ATA-3 (or newer) drives but is 2184 * optional on ATA-2 (or older) drives. 2185 * 2186 * On ATA-2 drives the ai_majorversion word will probably 2187 * be 0xffff or 0x0000, check the (now obsolete) DMA bit in 2188 * the capabilities word instead. The order of these tests 2189 * is important since an ATA-3 drive doesn't have to set 2190 * the DMA bit in the capabilities word. 2191 * 2192 */ 2193 2194 if (!((ata_drvp->ad_id.ai_majorversion & 0x8000) == 0 && 2195 ata_drvp->ad_id.ai_majorversion >= (1 << 2)) && 2196 !(ata_drvp->ad_id.ai_cap & ATAC_DMA_SUPPORT)) { 2197 ata_dev_DMA_sel_msg = "device not DMA capable"; 2198 2199 return (ATA_DMA_OFF); 2200 } 2201 2202 dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2203 0, "ata-dma-enabled", TRUE); 2204 disk_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2205 0, "ata-disk-dma-enabled", TRUE); 2206 cd_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2207 0, "atapi-cd-dma-enabled", FALSE); 2208 atapi_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip, 2209 0, "atapi-other-dma-enabled", TRUE); 2210 2211 if (dma == FALSE) { 2212 cmn_err(CE_CONT, "?ata_init_drive_pcidma: " 2213 "DMA disabled by \"ata-dma-enabled\" property"); 2214 ata_dev_DMA_sel_msg = "disabled by prop ata-dma-enabled"; 2215 2216 return (ATA_DMA_OFF); 2217 } 2218 2219 if (IS_CDROM(ata_drvp) == TRUE) { 2220 if (cd_dma == FALSE) { 2221 ata_dev_DMA_sel_msg = 2222 "disabled. Control with \"atapi-cd-dma-enabled\"" 2223 " property"; 2224 2225 return (ATA_DMA_OFF); 2226 } 2227 2228 } else if (ATAPIDRV(ata_drvp) == FALSE) { 2229 if (disk_dma == FALSE) { 2230 ata_dev_DMA_sel_msg = 2231 "disabled by \"ata-disk-dma-enabled\" property"; 2232 2233 return (ATA_DMA_OFF); 2234 } 2235 2236 } else if (atapi_dma == FALSE) { 2237 ata_dev_DMA_sel_msg = 2238 "disabled by \"atapi-other-dma-enabled\" property"; 2239 2240 return (ATA_DMA_OFF); 2241 } 2242 2243 return (ATA_DMA_ON); 2244 } 2245 2246 2247 2248 /* 2249 * this compare routine squeezes out extra blanks and 2250 * returns TRUE if p1 matches the leftmost substring of p2 2251 */ 2252 2253 static int 2254 ata_strncmp( 2255 char *p1, 2256 char *p2, 2257 int cnt) 2258 { 2259 2260 for (;;) { 2261 /* 2262 * skip over any extra blanks in both strings 2263 */ 2264 while (*p1 != '\0' && *p1 == ' ') 2265 p1++; 2266 2267 while (cnt != 0 && *p2 == ' ') { 2268 p2++; 2269 cnt--; 2270 } 2271 2272 /* 2273 * compare the two strings 2274 */ 2275 2276 if (cnt == 0 || *p1 != *p2) 2277 break; 2278 2279 while (cnt > 0 && *p1 == *p2) { 2280 p1++; 2281 p2++; 2282 cnt--; 2283 } 2284 2285 } 2286 2287 /* return TRUE if both strings ended at same point */ 2288 return ((*p1 == '\0') ? TRUE : FALSE); 2289 } 2290 2291 /* 2292 * Per PSARC/1997/281 create variant="atapi" property (if necessary) 2293 * on the target's dev_info node. Currently, the sd target driver 2294 * is the only driver which refers to this property. 2295 * 2296 * If the flag ata_id_debug is set also create the 2297 * the "ata" or "atapi" property on the target's dev_info node 2298 * 2299 */ 2300 2301 int 2302 ata_prop_create( 2303 dev_info_t *tgt_dip, 2304 ata_drv_t *ata_drvp, 2305 char *name) 2306 { 2307 int rc; 2308 2309 ADBG_TRACE(("ata_prop_create 0x%p 0x%p %s\n", tgt_dip, ata_drvp, name)); 2310 2311 if (strcmp("atapi", name) == 0) { 2312 rc = ndi_prop_update_string(DDI_DEV_T_NONE, tgt_dip, 2313 "variant", name); 2314 if (rc != DDI_PROP_SUCCESS) 2315 return (FALSE); 2316 } 2317 2318 if (!ata_id_debug) 2319 return (TRUE); 2320 2321 rc = ndi_prop_update_byte_array(DDI_DEV_T_NONE, tgt_dip, name, 2322 (uchar_t *)&ata_drvp->ad_id, sizeof (ata_drvp->ad_id)); 2323 if (rc != DDI_PROP_SUCCESS) { 2324 ADBG_ERROR(("ata_prop_create failed, rc=%d\n", rc)); 2325 } 2326 return (TRUE); 2327 } 2328 2329 2330 /* *********************************************************************** */ 2331 /* *********************************************************************** */ 2332 /* *********************************************************************** */ 2333 2334 /* 2335 * This state machine doesn't implement the ATAPI Optional Overlap 2336 * feature. You need that feature to efficiently support ATAPI 2337 * tape drives. See the 1394-ATA Tailgate spec (D97107), Figure 24, 2338 * for an example of how to add the necessary additional NextActions 2339 * and NextStates to this FSM and the atapi_fsm, in order to support 2340 * the Overlap Feature. 2341 */ 2342 2343 2344 uchar_t ata_ctlr_fsm_NextAction[ATA_CTLR_NSTATES][ATA_CTLR_NFUNCS] = { 2345 /* --------------------- next action --------------------- | - current - */ 2346 /* start0 --- start1 ---- intr ------ fini --- reset --- */ 2347 { AC_START, AC_START, AC_NADA, AC_NADA, AC_RESET_I }, /* idle */ 2348 { AC_BUSY, AC_BUSY, AC_INTR, AC_FINI, AC_RESET_A }, /* active0 */ 2349 { AC_BUSY, AC_BUSY, AC_INTR, AC_FINI, AC_RESET_A }, /* active1 */ 2350 }; 2351 2352 uchar_t ata_ctlr_fsm_NextState[ATA_CTLR_NSTATES][ATA_CTLR_NFUNCS] = { 2353 2354 /* --------------------- next state --------------------- | - current - */ 2355 /* start0 --- start1 ---- intr ------ fini --- reset --- */ 2356 { AS_ACTIVE0, AS_ACTIVE1, AS_IDLE, AS_IDLE, AS_IDLE }, /* idle */ 2357 { AS_ACTIVE0, AS_ACTIVE0, AS_ACTIVE0, AS_IDLE, AS_ACTIVE0 }, /* active0 */ 2358 { AS_ACTIVE1, AS_ACTIVE1, AS_ACTIVE1, AS_IDLE, AS_ACTIVE1 }, /* active1 */ 2359 }; 2360 2361 2362 static int 2363 ata_ctlr_fsm( 2364 uchar_t fsm_func, 2365 ata_ctl_t *ata_ctlp, 2366 ata_drv_t *ata_drvp, 2367 ata_pkt_t *ata_pktp, 2368 int *DoneFlgp) 2369 { 2370 uchar_t action; 2371 uchar_t current_state; 2372 uchar_t next_state; 2373 int rc; 2374 2375 current_state = ata_ctlp->ac_state; 2376 action = ata_ctlr_fsm_NextAction[current_state][fsm_func]; 2377 next_state = ata_ctlr_fsm_NextState[current_state][fsm_func]; 2378 2379 /* 2380 * Set the controller's new state 2381 */ 2382 ata_ctlp->ac_state = next_state; 2383 switch (action) { 2384 2385 case AC_BUSY: 2386 return (ATA_FSM_RC_BUSY); 2387 2388 case AC_NADA: 2389 return (ATA_FSM_RC_OKAY); 2390 2391 case AC_START: 2392 ASSERT(ata_ctlp->ac_active_pktp == NULL); 2393 ASSERT(ata_ctlp->ac_active_drvp == NULL); 2394 2395 ata_ctlp->ac_active_pktp = ata_pktp; 2396 ata_ctlp->ac_active_drvp = ata_drvp; 2397 2398 rc = (*ata_pktp->ap_start)(ata_ctlp, ata_drvp, ata_pktp); 2399 2400 if (rc == ATA_FSM_RC_BUSY) { 2401 /* the request didn't start, GHD will requeue it */ 2402 ata_ctlp->ac_state = AS_IDLE; 2403 ata_ctlp->ac_active_pktp = NULL; 2404 ata_ctlp->ac_active_drvp = NULL; 2405 } 2406 return (rc); 2407 2408 case AC_INTR: 2409 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2410 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2411 2412 ata_drvp = ata_ctlp->ac_active_drvp; 2413 ata_pktp = ata_ctlp->ac_active_pktp; 2414 return ((*ata_pktp->ap_intr)(ata_ctlp, ata_drvp, ata_pktp)); 2415 2416 case AC_RESET_A: /* Reset, controller active */ 2417 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2418 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2419 2420 /* clean up the active request */ 2421 ata_pktp = ata_ctlp->ac_active_pktp; 2422 ata_pktp->ap_flags |= AP_DEV_RESET | AP_BUS_RESET; 2423 2424 /* halt the DMA engine */ 2425 if (ata_pktp->ap_pciide_dma) { 2426 ata_pciide_dma_stop(ata_ctlp); 2427 (void) ata_pciide_status_clear(ata_ctlp); 2428 } 2429 2430 /* Do a Software Reset to unwedge the bus */ 2431 if (!ata_software_reset(ata_ctlp)) { 2432 return (ATA_FSM_RC_BUSY); 2433 } 2434 2435 /* Then send a DEVICE RESET cmd to each ATAPI device */ 2436 atapi_fsm_reset(ata_ctlp); 2437 return (ATA_FSM_RC_FINI); 2438 2439 case AC_RESET_I: /* Reset, controller idle */ 2440 /* Do a Software Reset to unwedge the bus */ 2441 if (!ata_software_reset(ata_ctlp)) { 2442 return (ATA_FSM_RC_BUSY); 2443 } 2444 2445 /* Then send a DEVICE RESET cmd to each ATAPI device */ 2446 atapi_fsm_reset(ata_ctlp); 2447 return (ATA_FSM_RC_OKAY); 2448 2449 case AC_FINI: 2450 break; 2451 } 2452 2453 /* 2454 * AC_FINI, check ARQ needs to be started or finished 2455 */ 2456 2457 ASSERT(action == AC_FINI); 2458 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2459 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2460 2461 /* 2462 * The active request is done now. 2463 * Disconnect the request from the controller and 2464 * add it to the done queue. 2465 */ 2466 ata_drvp = ata_ctlp->ac_active_drvp; 2467 ata_pktp = ata_ctlp->ac_active_pktp; 2468 2469 /* 2470 * If ARQ pkt is done, get ptr to original pkt and wrap it up. 2471 */ 2472 if (ata_pktp == ata_ctlp->ac_arq_pktp) { 2473 ata_pkt_t *arq_pktp; 2474 2475 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ done\n", ata_ctlp)); 2476 2477 arq_pktp = ata_pktp; 2478 ata_pktp = ata_ctlp->ac_fault_pktp; 2479 ata_ctlp->ac_fault_pktp = NULL; 2480 if (arq_pktp->ap_flags & (AP_ERROR | AP_BUS_RESET)) 2481 ata_pktp->ap_flags |= AP_ARQ_ERROR; 2482 else 2483 ata_pktp->ap_flags |= AP_ARQ_OKAY; 2484 goto all_done; 2485 } 2486 2487 2488 #define AP_ARQ_NEEDED (AP_ARQ_ON_ERROR | AP_GOT_STATUS | AP_ERROR) 2489 2490 /* 2491 * Start ARQ pkt if necessary 2492 */ 2493 if ((ata_pktp->ap_flags & AP_ARQ_NEEDED) == AP_ARQ_NEEDED && 2494 (ata_pktp->ap_status & ATS_ERR)) { 2495 2496 /* set controller state back to active */ 2497 ata_ctlp->ac_state = current_state; 2498 2499 /* try to start the ARQ pkt */ 2500 rc = ata_start_arq(ata_ctlp, ata_drvp, ata_pktp); 2501 2502 if (rc == ATA_FSM_RC_BUSY) { 2503 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ BUSY\n", ata_ctlp)); 2504 /* let the target driver handle the problem */ 2505 ata_ctlp->ac_state = AS_IDLE; 2506 ata_ctlp->ac_active_pktp = NULL; 2507 ata_ctlp->ac_active_drvp = NULL; 2508 ata_ctlp->ac_fault_pktp = NULL; 2509 goto all_done; 2510 } 2511 2512 ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ started\n", ata_ctlp)); 2513 return (rc); 2514 } 2515 2516 /* 2517 * Normal completion, no error status, and not an ARQ pkt, 2518 * just fall through. 2519 */ 2520 2521 all_done: 2522 2523 /* 2524 * wrap everything up and tie a ribbon around it 2525 */ 2526 ata_ctlp->ac_active_pktp = NULL; 2527 ata_ctlp->ac_active_drvp = NULL; 2528 if (APKT2GCMD(ata_pktp) != (gcmd_t *)0) { 2529 ghd_complete(&ata_ctlp->ac_ccc, APKT2GCMD(ata_pktp)); 2530 if (DoneFlgp) 2531 *DoneFlgp = TRUE; 2532 } 2533 2534 return (ATA_FSM_RC_OKAY); 2535 } 2536 2537 2538 static int 2539 ata_start_arq( 2540 ata_ctl_t *ata_ctlp, 2541 ata_drv_t *ata_drvp, 2542 ata_pkt_t *ata_pktp) 2543 { 2544 ata_pkt_t *arq_pktp; 2545 int bytes; 2546 uint_t senselen; 2547 2548 ADBG_ARQ(("ata_start_arq 0x%p ARQ needed\n", ata_ctlp)); 2549 2550 /* 2551 * Determine just the size of the Request Sense Data buffer within 2552 * the scsi_arq_status structure. 2553 */ 2554 #define SIZEOF_ARQ_HEADER (sizeof (struct scsi_arq_status) \ 2555 - sizeof (struct scsi_extended_sense)) 2556 senselen = ata_pktp->ap_statuslen - SIZEOF_ARQ_HEADER; 2557 ASSERT(senselen > 0); 2558 2559 2560 /* save ptr to original pkt */ 2561 ata_ctlp->ac_fault_pktp = ata_pktp; 2562 2563 /* switch the controller's active pkt to the ARQ pkt */ 2564 arq_pktp = ata_ctlp->ac_arq_pktp; 2565 ata_ctlp->ac_active_pktp = arq_pktp; 2566 2567 /* finish initializing the ARQ CDB */ 2568 ata_ctlp->ac_arq_cdb[1] = ata_drvp->ad_lun << 4; 2569 ata_ctlp->ac_arq_cdb[4] = senselen; 2570 2571 /* finish initializing the ARQ pkt */ 2572 arq_pktp->ap_v_addr = (caddr_t)&ata_pktp->ap_scbp->sts_sensedata; 2573 2574 arq_pktp->ap_resid = senselen; 2575 arq_pktp->ap_flags = AP_ATAPI | AP_READ; 2576 arq_pktp->ap_cdb_pad = 2577 ((unsigned)(ata_drvp->ad_cdb_len - arq_pktp->ap_cdb_len)) >> 1; 2578 2579 bytes = min(senselen, ATAPI_MAX_BYTES_PER_DRQ); 2580 arq_pktp->ap_hicyl = (uchar_t)(bytes >> 8); 2581 arq_pktp->ap_lwcyl = (uchar_t)bytes; 2582 2583 /* 2584 * This packet is shared by all drives on this controller 2585 * therefore we need to init the drive number on every ARQ. 2586 */ 2587 arq_pktp->ap_hd = ata_drvp->ad_drive_bits; 2588 2589 /* start it up */ 2590 return ((*arq_pktp->ap_start)(ata_ctlp, ata_drvp, arq_pktp)); 2591 } 2592 2593 /* 2594 * 2595 * reset the bus 2596 * 2597 */ 2598 2599 static int 2600 ata_reset_bus( 2601 ata_ctl_t *ata_ctlp) 2602 { 2603 int watchdog; 2604 uchar_t drive; 2605 int rc = FALSE; 2606 uchar_t fsm_func; 2607 int DoneFlg = FALSE; 2608 2609 /* 2610 * Do a Software Reset to unwedge the bus, and send 2611 * ATAPI DEVICE RESET to each ATAPI drive. 2612 */ 2613 fsm_func = ATA_FSM_RESET; 2614 for (watchdog = ata_reset_bus_watchdog; watchdog > 0; watchdog--) { 2615 switch (ata_ctlr_fsm(fsm_func, ata_ctlp, NULL, NULL, 2616 &DoneFlg)) { 2617 case ATA_FSM_RC_OKAY: 2618 rc = TRUE; 2619 goto fsm_done; 2620 2621 case ATA_FSM_RC_BUSY: 2622 return (FALSE); 2623 2624 case ATA_FSM_RC_INTR: 2625 fsm_func = ATA_FSM_INTR; 2626 rc = TRUE; 2627 continue; 2628 2629 case ATA_FSM_RC_FINI: 2630 fsm_func = ATA_FSM_FINI; 2631 rc = TRUE; 2632 continue; 2633 } 2634 } 2635 ADBG_WARN(("ata_reset_bus: watchdog\n")); 2636 2637 fsm_done: 2638 2639 /* 2640 * Reinitialize the ATA drives 2641 */ 2642 for (drive = 0; drive < ATA_MAXTARG; drive++) { 2643 ata_drv_t *ata_drvp; 2644 2645 if ((ata_drvp = CTL2DRV(ata_ctlp, drive, 0)) == NULL) 2646 continue; 2647 2648 if (ATAPIDRV(ata_drvp)) 2649 continue; 2650 2651 /* 2652 * Reprogram the Read/Write Multiple block factor 2653 * and current geometry into the drive. 2654 */ 2655 if (!ata_disk_setup_parms(ata_ctlp, ata_drvp)) 2656 rc = FALSE; 2657 } 2658 2659 /* If DoneFlg is TRUE, it means that ghd_complete() function */ 2660 /* has been already called. In this case ignore any errors and */ 2661 /* return TRUE to the caller, otherwise return the value of rc */ 2662 /* to the caller */ 2663 if (DoneFlg) 2664 return (TRUE); 2665 else 2666 return (rc); 2667 } 2668 2669 2670 /* 2671 * 2672 * Low level routine to toggle the Software Reset bit 2673 * 2674 */ 2675 2676 static int 2677 ata_software_reset( 2678 ata_ctl_t *ata_ctlp) 2679 { 2680 ddi_acc_handle_t io_hdl1 = ata_ctlp->ac_iohandle1; 2681 ddi_acc_handle_t io_hdl2 = ata_ctlp->ac_iohandle2; 2682 int time_left; 2683 2684 ADBG_TRACE(("ata_reset_bus entered\n")); 2685 2686 /* disable interrupts and turn the software reset bit on */ 2687 ddi_put8(io_hdl2, ata_ctlp->ac_devctl, (ATDC_D3 | ATDC_SRST)); 2688 2689 /* why 30 milliseconds, the ATA/ATAPI-4 spec says 5 usec. */ 2690 drv_usecwait(30000); 2691 2692 /* turn the software reset bit back off */ 2693 ddi_put8(io_hdl2, ata_ctlp->ac_devctl, ATDC_D3); 2694 2695 /* 2696 * Wait for the controller to assert BUSY status. 2697 * I don't think 300 msecs is correct. The ATA/ATAPI-4 2698 * spec says 400 nsecs, (and 2 msecs if device 2699 * was in sleep mode; but we don't put drives to sleep 2700 * so it probably doesn't matter). 2701 */ 2702 drv_usecwait(300000); 2703 2704 /* 2705 * If drive 0 exists the test for completion is simple 2706 */ 2707 time_left = 31 * 1000000; 2708 if (CTL2DRV(ata_ctlp, 0, 0)) { 2709 goto wait_for_not_busy; 2710 } 2711 2712 ASSERT(CTL2DRV(ata_ctlp, 1, 0) != NULL); 2713 2714 /* 2715 * This must be a single device configuration, with drive 1 2716 * only. This complicates the test for completion because 2717 * issuing the software reset just caused drive 1 to 2718 * deselect. With drive 1 deselected, if I just read the 2719 * status register to test the BSY bit I get garbage, but 2720 * I can't re-select drive 1 until I'm certain the BSY bit 2721 * is de-asserted. Catch-22. 2722 * 2723 * In ATA/ATAPI-4, rev 15, section 9.16.2, it says to handle 2724 * this situation like this: 2725 */ 2726 2727 /* give up if the drive doesn't settle within 31 seconds */ 2728 while (time_left > 0) { 2729 /* 2730 * delay 10msec each time around the loop 2731 */ 2732 drv_usecwait(10000); 2733 time_left -= 10000; 2734 2735 /* 2736 * try to select drive 1 2737 */ 2738 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, ATDH_DRIVE1); 2739 2740 ddi_put8(io_hdl1, ata_ctlp->ac_sect, 0x55); 2741 ddi_put8(io_hdl1, ata_ctlp->ac_sect, 0xaa); 2742 if (ddi_get8(io_hdl1, ata_ctlp->ac_sect) != 0xaa) 2743 continue; 2744 2745 ddi_put8(io_hdl1, ata_ctlp->ac_count, 0x55); 2746 ddi_put8(io_hdl1, ata_ctlp->ac_count, 0xaa); 2747 if (ddi_get8(io_hdl1, ata_ctlp->ac_count) != 0xaa) 2748 continue; 2749 2750 goto wait_for_not_busy; 2751 } 2752 return (FALSE); 2753 2754 wait_for_not_busy: 2755 2756 /* 2757 * Now wait upto 31 seconds for BUSY to clear. 2758 */ 2759 (void) ata_wait3(io_hdl2, ata_ctlp->ac_ioaddr2, 0, ATS_BSY, 2760 ATS_ERR, ATS_BSY, ATS_DF, ATS_BSY, time_left); 2761 2762 return (TRUE); 2763 } 2764 2765 /* 2766 * 2767 * DDI interrupt handler 2768 * 2769 */ 2770 2771 static uint_t 2772 ata_intr( 2773 caddr_t arg) 2774 { 2775 ata_ctl_t *ata_ctlp; 2776 int one_shot = 1; 2777 2778 ata_ctlp = (ata_ctl_t *)arg; 2779 2780 return (ghd_intr(&ata_ctlp->ac_ccc, (void *)&one_shot)); 2781 } 2782 2783 2784 /* 2785 * 2786 * GHD ccc_get_status callback 2787 * 2788 */ 2789 2790 static int 2791 ata_get_status( 2792 void *hba_handle, 2793 void *intr_status) 2794 { 2795 ata_ctl_t *ata_ctlp = (ata_ctl_t *)hba_handle; 2796 uchar_t status; 2797 2798 ADBG_TRACE(("ata_get_status entered\n")); 2799 2800 /* 2801 * ignore interrupts before ata_attach completes 2802 */ 2803 if (!(ata_ctlp->ac_flags & AC_ATTACHED)) 2804 return (FALSE); 2805 2806 /* 2807 * can't be interrupt pending if nothing active 2808 */ 2809 switch (ata_ctlp->ac_state) { 2810 case AS_IDLE: 2811 return (FALSE); 2812 case AS_ACTIVE0: 2813 case AS_ACTIVE1: 2814 ASSERT(ata_ctlp->ac_active_drvp != NULL); 2815 ASSERT(ata_ctlp->ac_active_pktp != NULL); 2816 break; 2817 } 2818 2819 /* 2820 * If this is a PCI-IDE controller, check the PCI-IDE controller's 2821 * interrupt status latch. But don't clear it yet. 2822 * 2823 * AC_BMSTATREG_PIO_BROKEN flag is used currently for 2824 * CMD chips with device id 0x646. Since the interrupt bit on 2825 * Bus master IDE register is not usable when in PIO mode, 2826 * this chip is treated as a legacy device for interrupt 2827 * indication. The following code for CMD 2828 * chips may need to be revisited when we enable support for dma. 2829 * 2830 * CHANGE: DMA is not disabled for these devices. BM intr bit is 2831 * checked only if there was DMA used or BM intr is useable on PIO, 2832 * else treat it as before - as legacy device. 2833 */ 2834 2835 if ((ata_ctlp->ac_pciide) && 2836 ((ata_ctlp->ac_pciide_bm != FALSE) && 2837 ((ata_ctlp->ac_active_pktp->ap_pciide_dma == TRUE) || 2838 !(ata_ctlp->ac_flags & AC_BMSTATREG_PIO_BROKEN)))) { 2839 2840 if (!ata_pciide_status_pending(ata_ctlp)) 2841 return (FALSE); 2842 } else { 2843 /* 2844 * Interrupts from legacy ATA/IDE controllers are 2845 * edge-triggered but the dumb legacy ATA/IDE controllers 2846 * and drives don't have an interrupt status bit. 2847 * 2848 * Use a one_shot variable to make sure we only return 2849 * one status per interrupt. 2850 */ 2851 if (intr_status != NULL) { 2852 int *one_shot = (int *)intr_status; 2853 2854 if (*one_shot == 1) 2855 *one_shot = 0; 2856 else 2857 return (FALSE); 2858 } 2859 } 2860 2861 /* check if device is still busy */ 2862 2863 status = ddi_get8(ata_ctlp->ac_iohandle2, ata_ctlp->ac_altstatus); 2864 if (status & ATS_BSY) 2865 return (FALSE); 2866 return (TRUE); 2867 } 2868 2869 2870 /* 2871 * 2872 * get the current status and clear the IRQ 2873 * 2874 */ 2875 2876 int 2877 ata_get_status_clear_intr( 2878 ata_ctl_t *ata_ctlp, 2879 ata_pkt_t *ata_pktp) 2880 { 2881 uchar_t status; 2882 2883 /* 2884 * Here's where we clear the PCI-IDE interrupt latch. If this 2885 * request used DMA mode then we also have to check and clear 2886 * the DMA error latch at the same time. 2887 */ 2888 2889 if (ata_pktp->ap_pciide_dma) { 2890 if (ata_pciide_status_dmacheck_clear(ata_ctlp)) 2891 ata_pktp->ap_flags |= AP_ERROR | AP_TRAN_ERROR; 2892 } else if ((ata_ctlp->ac_pciide) && 2893 !(ata_ctlp->ac_flags & AC_BMSTATREG_PIO_BROKEN)) { 2894 /* 2895 * Some requests don't use DMA mode and therefore won't 2896 * set the DMA error latch, but we still have to clear 2897 * the interrupt latch. 2898 * Controllers with broken BM intr in PIO mode do not go 2899 * through this path. 2900 */ 2901 (void) ata_pciide_status_clear(ata_ctlp); 2902 } 2903 2904 /* 2905 * this clears the drive's interrupt 2906 */ 2907 status = ddi_get8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_status); 2908 ADBG_TRACE(("ata_get_status_clear_intr: 0x%x\n", status)); 2909 return (status); 2910 } 2911 2912 2913 2914 /* 2915 * 2916 * GHD interrupt handler 2917 * 2918 */ 2919 2920 /* ARGSUSED */ 2921 static void 2922 ata_process_intr( 2923 void *hba_handle, 2924 void *intr_status) 2925 { 2926 ata_ctl_t *ata_ctlp = (ata_ctl_t *)hba_handle; 2927 int watchdog; 2928 uchar_t fsm_func; 2929 int rc; 2930 2931 ADBG_TRACE(("ata_process_intr entered\n")); 2932 2933 /* 2934 * process the ATA or ATAPI interrupt 2935 */ 2936 2937 fsm_func = ATA_FSM_INTR; 2938 for (watchdog = ata_process_intr_watchdog; watchdog > 0; watchdog--) { 2939 rc = ata_ctlr_fsm(fsm_func, ata_ctlp, NULL, NULL, NULL); 2940 2941 switch (rc) { 2942 case ATA_FSM_RC_OKAY: 2943 return; 2944 2945 case ATA_FSM_RC_BUSY: /* wait for the next interrupt */ 2946 return; 2947 2948 case ATA_FSM_RC_INTR: /* re-invoke the FSM */ 2949 fsm_func = ATA_FSM_INTR; 2950 break; 2951 2952 case ATA_FSM_RC_FINI: /* move a request to done Q */ 2953 fsm_func = ATA_FSM_FINI; 2954 break; 2955 } 2956 } 2957 ADBG_WARN(("ata_process_intr: watchdog\n")); 2958 } 2959 2960 2961 2962 /* 2963 * 2964 * GHD ccc_hba_start callback 2965 * 2966 */ 2967 2968 static int 2969 ata_hba_start( 2970 void *hba_handle, 2971 gcmd_t *gcmdp) 2972 { 2973 ata_ctl_t *ata_ctlp; 2974 ata_drv_t *ata_drvp; 2975 ata_pkt_t *ata_pktp; 2976 uchar_t fsm_func; 2977 int request_started; 2978 int watchdog; 2979 2980 ADBG_TRACE(("ata_hba_start entered\n")); 2981 2982 ata_ctlp = (ata_ctl_t *)hba_handle; 2983 2984 if (ata_ctlp->ac_active_drvp != NULL) { 2985 ADBG_WARN(("ata_hba_start drvp not null\n")); 2986 return (FALSE); 2987 } 2988 if (ata_ctlp->ac_active_pktp != NULL) { 2989 ADBG_WARN(("ata_hba_start pktp not null\n")); 2990 return (FALSE); 2991 } 2992 2993 ata_pktp = GCMD2APKT(gcmdp); 2994 ata_drvp = GCMD2DRV(gcmdp); 2995 2996 /* 2997 * which drive? 2998 */ 2999 if (ata_drvp->ad_targ == 0) 3000 fsm_func = ATA_FSM_START0; 3001 else 3002 fsm_func = ATA_FSM_START1; 3003 3004 /* 3005 * start the request 3006 */ 3007 request_started = FALSE; 3008 for (watchdog = ata_hba_start_watchdog; watchdog > 0; watchdog--) { 3009 switch (ata_ctlr_fsm(fsm_func, ata_ctlp, ata_drvp, ata_pktp, 3010 NULL)) { 3011 case ATA_FSM_RC_OKAY: 3012 request_started = TRUE; 3013 goto fsm_done; 3014 3015 case ATA_FSM_RC_BUSY: 3016 /* if first time, tell GHD to requeue the request */ 3017 goto fsm_done; 3018 3019 case ATA_FSM_RC_INTR: 3020 /* 3021 * The start function polled for the next 3022 * bus phase, now fake an interrupt to process 3023 * the next action. 3024 */ 3025 request_started = TRUE; 3026 fsm_func = ATA_FSM_INTR; 3027 ata_drvp = NULL; 3028 ata_pktp = NULL; 3029 break; 3030 3031 case ATA_FSM_RC_FINI: /* move request to the done queue */ 3032 request_started = TRUE; 3033 fsm_func = ATA_FSM_FINI; 3034 ata_drvp = NULL; 3035 ata_pktp = NULL; 3036 break; 3037 } 3038 } 3039 ADBG_WARN(("ata_hba_start: watchdog\n")); 3040 3041 fsm_done: 3042 return (request_started); 3043 3044 } 3045 3046 static int 3047 ata_check_pciide_blacklist( 3048 dev_info_t *dip, 3049 uint_t flags) 3050 { 3051 ushort_t vendorid; 3052 ushort_t deviceid; 3053 pcibl_t *blp; 3054 int *propp; 3055 uint_t count; 3056 int rc; 3057 3058 3059 vendorid = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3060 DDI_PROP_DONTPASS, "vendor-id", 0); 3061 deviceid = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3062 DDI_PROP_DONTPASS, "device-id", 0); 3063 3064 /* 3065 * first check for a match in the "pci-ide-blacklist" property 3066 */ 3067 rc = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0, 3068 "pci-ide-blacklist", &propp, &count); 3069 3070 if (rc == DDI_PROP_SUCCESS) { 3071 count = (count * sizeof (uint_t)) / sizeof (pcibl_t); 3072 blp = (pcibl_t *)propp; 3073 while (count--) { 3074 /* check for matching ID */ 3075 if ((vendorid & blp->b_vmask) 3076 != (blp->b_vendorid & blp->b_vmask)) { 3077 blp++; 3078 continue; 3079 } 3080 if ((deviceid & blp->b_dmask) 3081 != (blp->b_deviceid & blp->b_dmask)) { 3082 blp++; 3083 continue; 3084 } 3085 3086 /* got a match */ 3087 if (blp->b_flags & flags) { 3088 ddi_prop_free(propp); 3089 return (TRUE); 3090 } else { 3091 ddi_prop_free(propp); 3092 return (FALSE); 3093 } 3094 } 3095 ddi_prop_free(propp); 3096 } 3097 3098 /* 3099 * then check the built-in blacklist 3100 */ 3101 for (blp = ata_pciide_blacklist; blp->b_vendorid; blp++) { 3102 if ((vendorid & blp->b_vmask) != blp->b_vendorid) 3103 continue; 3104 if ((deviceid & blp->b_dmask) != blp->b_deviceid) 3105 continue; 3106 if (!(blp->b_flags & flags)) 3107 continue; 3108 return (TRUE); 3109 } 3110 return (FALSE); 3111 } 3112 3113 int 3114 ata_check_drive_blacklist( 3115 struct ata_id *aidp, 3116 uint_t flags) 3117 { 3118 atabl_t *blp; 3119 3120 for (blp = ata_drive_blacklist; blp->b_model; blp++) { 3121 if (!ata_strncmp(blp->b_model, aidp->ai_model, 3122 sizeof (aidp->ai_model))) 3123 continue; 3124 if (blp->b_flags & flags) 3125 return (TRUE); 3126 return (FALSE); 3127 } 3128 return (FALSE); 3129 } 3130 3131 /* 3132 * Queue a request to perform some sort of internally 3133 * generated command. When this request packet reaches 3134 * the front of the queue (*func)() is invoked. 3135 * 3136 */ 3137 3138 int 3139 ata_queue_cmd( 3140 int (*func)(ata_ctl_t *, ata_drv_t *, ata_pkt_t *), 3141 void *arg, 3142 ata_ctl_t *ata_ctlp, 3143 ata_drv_t *ata_drvp, 3144 gtgt_t *gtgtp) 3145 { 3146 ata_pkt_t *ata_pktp; 3147 gcmd_t *gcmdp; 3148 int rc; 3149 3150 if (!(gcmdp = ghd_gcmd_alloc(gtgtp, sizeof (*ata_pktp), TRUE))) { 3151 ADBG_ERROR(("atapi_id_update alloc failed\n")); 3152 return (FALSE); 3153 } 3154 3155 3156 /* set the back ptr from the ata_pkt to the gcmd_t */ 3157 ata_pktp = GCMD2APKT(gcmdp); 3158 ata_pktp->ap_gcmdp = gcmdp; 3159 ata_pktp->ap_hd = ata_drvp->ad_drive_bits; 3160 ata_pktp->ap_bytes_per_block = ata_drvp->ad_bytes_per_block; 3161 3162 /* 3163 * over-ride the default start function 3164 */ 3165 ata_pktp = GCMD2APKT(gcmdp); 3166 ata_pktp->ap_start = func; 3167 ata_pktp->ap_complete = NULL; 3168 ata_pktp->ap_v_addr = (caddr_t)arg; 3169 3170 /* 3171 * add it to the queue, when it gets to the front the 3172 * ap_start function is called. 3173 */ 3174 rc = ghd_transport(&ata_ctlp->ac_ccc, gcmdp, gcmdp->cmd_gtgtp, 3175 0, TRUE, NULL); 3176 3177 if (rc != TRAN_ACCEPT) { 3178 /* this should never, ever happen */ 3179 return (FALSE); 3180 } 3181 3182 if (ata_pktp->ap_flags & AP_ERROR) 3183 return (FALSE); 3184 return (TRUE); 3185 } 3186 3187 /* 3188 * Check if this drive has the "revert to defaults" bug 3189 * PSARC 2001/500 and 2001/xxx - check for the properties 3190 * ata-revert-to-defaults and atarvrt-<diskmodel> before 3191 * examining the blacklist. 3192 * <diskmodel> is made from the model number reported by Identify Drive 3193 * with uppercase letters converted to lowercase and all characters 3194 * except letters, digits, ".", "_", and "-" deleted. 3195 * Return value: 3196 * TRUE: enable revert to defaults 3197 * FALSE: disable revert to defaults 3198 * 3199 * NOTE: revert to power on defaults that includes reverting to MDMA 3200 * mode is allowed by ATA-6 & ATA-7 specs. 3201 * Therefore drives exhibiting this behaviour are not violating the spec. 3202 * Furthermore, the spec explicitly says that after the soft reset 3203 * host should check the current setting of the device features. 3204 * Correctly working BIOS would therefore reprogram either the drive 3205 * and/or the host controller to match transfer modes. 3206 * Devices with ATA_BL_NORVRT flag will be removed from 3207 * the ata_blacklist. 3208 * The default behaviour will be - no revert to power-on defaults 3209 * for all devices. The property is retained in case the user 3210 * explicitly requests revert-to-defaults before reboot. 3211 */ 3212 3213 #define ATA_REVERT_PROP_PREFIX "revert-" 3214 #define ATA_REVERT_PROP_GLOBAL "ata-revert-to-defaults" 3215 /* room for prefix + model number + terminating NUL character */ 3216 #define PROP_BUF_SIZE (sizeof (ATA_REVERT_PROP_PREFIX) + \ 3217 sizeof (aidp->ai_model) + 1) 3218 #define PROP_LEN_MAX (31) 3219 3220 static int 3221 ata_check_revert_to_defaults( 3222 ata_drv_t *ata_drvp) 3223 { 3224 struct ata_id *aidp = &ata_drvp->ad_id; 3225 ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp; 3226 char prop_buf[PROP_BUF_SIZE]; 3227 int i, j; 3228 int propval; 3229 3230 /* put prefix into the buffer */ 3231 (void) strcpy(prop_buf, ATA_REVERT_PROP_PREFIX); 3232 j = strlen(prop_buf); 3233 3234 /* append the model number, leaving out invalid characters */ 3235 for (i = 0; i < sizeof (aidp->ai_model); ++i) { 3236 char c = aidp->ai_model[i]; 3237 if (c >= 'A' && c <= 'Z') /* uppercase -> lower */ 3238 c = c - 'A' + 'a'; 3239 if (c >= 'a' && c <= 'z' || c >= '0' && c <= '9' || 3240 c == '.' || c == '_' || c == '-') 3241 prop_buf[j++] = c; 3242 if (c == '\0') 3243 break; 3244 } 3245 3246 /* make sure there's a terminating NUL character */ 3247 if (j >= PROP_LEN_MAX) 3248 j = PROP_LEN_MAX; 3249 prop_buf[j] = '\0'; 3250 3251 /* look for a disk-specific "revert" property" */ 3252 propval = ddi_getprop(DDI_DEV_T_ANY, ata_ctlp->ac_dip, 3253 DDI_PROP_DONTPASS, prop_buf, -1); 3254 if (propval == 0) 3255 return (FALSE); 3256 else if (propval != -1) 3257 return (TRUE); 3258 3259 /* look for a global "revert" property" */ 3260 propval = ddi_getprop(DDI_DEV_T_ANY, ata_ctlp->ac_dip, 3261 0, ATA_REVERT_PROP_GLOBAL, -1); 3262 if (propval == 0) 3263 return (FALSE); 3264 else if (propval != -1) 3265 return (TRUE); 3266 3267 return (FALSE); 3268 } 3269 3270 void 3271 ata_show_transfer_mode(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp) 3272 { 3273 int i; 3274 3275 if (ata_ctlp->ac_pciide_bm == FALSE || 3276 ata_drvp->ad_pciide_dma != ATA_DMA_ON) { 3277 if (ata_cntrl_DMA_sel_msg) { 3278 ATAPRT(( 3279 "?\tATA DMA off: %s\n", ata_cntrl_DMA_sel_msg)); 3280 } else if (ata_dev_DMA_sel_msg) { 3281 ATAPRT(("?\tATA DMA off: %s\n", ata_dev_DMA_sel_msg)); 3282 } 3283 ATAPRT(("?\tPIO mode %d selected\n", 3284 (ata_drvp->ad_id.ai_advpiomode & ATAC_ADVPIO_4_SUP) == 3285 ATAC_ADVPIO_4_SUP ? 4 : 3)); 3286 } else { 3287 /* Using DMA */ 3288 if (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_SEL_MASK) { 3289 /* 3290 * Rely on the fact that either dwdma or udma is 3291 * selected, not both. 3292 */ 3293 ATAPRT(("?\tMultiwordDMA mode %d selected\n", 3294 (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_2_SEL) == 3295 ATAC_MDMA_2_SEL ? 2 : 3296 (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_1_SEL) == 3297 ATAC_MDMA_1_SEL ? 1 : 0)); 3298 } else { 3299 for (i = 0; i <= 6; i++) { 3300 if (ata_drvp->ad_id.ai_ultradma & 3301 (1 << (i + 8))) { 3302 ATAPRT(( 3303 "?\tUltraDMA mode %d selected\n", 3304 i)); 3305 break; 3306 } 3307 } 3308 } 3309 } 3310 } 3311 3312 /* 3313 * Controller-specific operation pointers. 3314 * Should be extended as needed - init only for now 3315 */ 3316 struct ata_ctl_spec_ops { 3317 uint_t (*cs_init)(dev_info_t *, ushort_t, ushort_t); /* ctlr init */ 3318 }; 3319 3320 3321 struct ata_ctl_spec { 3322 ushort_t cs_vendor_id; 3323 ushort_t cs_device_id; 3324 struct ata_ctl_spec_ops *cs_ops; 3325 }; 3326 3327 /* Sil3XXX-specific functions (init only for now) */ 3328 struct ata_ctl_spec_ops sil3xxx_ops = { 3329 &sil3xxx_init_controller /* Sil3XXX cntrl initialization */ 3330 }; 3331 3332 3333 struct ata_ctl_spec ata_cntrls_spec[] = { 3334 {0x1095, 0x3114, &sil3xxx_ops}, 3335 {0x1095, 0x3512, &sil3xxx_ops}, 3336 {0x1095, 0x3112, &sil3xxx_ops}, 3337 {0, 0, NULL} /* List must end with cs_ops set to NULL */ 3338 }; 3339 3340 /* 3341 * Do controller specific initialization if necessary. 3342 * Pick-up controller specific functions. 3343 */ 3344 3345 int 3346 ata_spec_init_controller(dev_info_t *dip) 3347 { 3348 ushort_t vendor_id; 3349 ushort_t device_id; 3350 struct ata_ctl_spec *ctlsp; 3351 3352 vendor_id = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3353 DDI_PROP_DONTPASS, "vendor-id", 0); 3354 device_id = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip), 3355 DDI_PROP_DONTPASS, "device-id", 0); 3356 3357 /* Locate controller specific ops, if they exist */ 3358 ctlsp = ata_cntrls_spec; 3359 while (ctlsp->cs_ops != NULL) { 3360 if (ctlsp->cs_vendor_id == vendor_id && 3361 ctlsp->cs_device_id == device_id) 3362 break; 3363 ctlsp++; 3364 } 3365 3366 if (ctlsp->cs_ops != NULL) { 3367 if (ctlsp->cs_ops->cs_init != NULL) { 3368 /* Initialize controller */ 3369 if ((*(ctlsp->cs_ops->cs_init)) 3370 (dip, vendor_id, device_id) != TRUE) { 3371 cmn_err(CE_WARN, 3372 "pci%4x,%4x cntrl specific " 3373 "initialization failed", 3374 vendor_id, device_id); 3375 return (FALSE); 3376 } 3377 } 3378 } 3379 return (TRUE); 3380 } 3381 3382 /* 3383 * this routine works like ddi_prop_get_int, except that it works on 3384 * a string property that contains ascii representations 3385 * of an integer. 3386 * If the property is not found, the default value is returned. 3387 */ 3388 static int 3389 ata_prop_lookup_int(dev_t match_dev, dev_info_t *dip, 3390 uint_t flags, char *name, int defvalue) 3391 { 3392 3393 char *bufp, *cp; 3394 int rc = defvalue; 3395 int proprc; 3396 3397 proprc = ddi_prop_lookup_string(match_dev, dip, 3398 flags, name, &bufp); 3399 3400 if (proprc == DDI_PROP_SUCCESS) { 3401 cp = bufp; 3402 rc = stoi(&cp); 3403 ddi_prop_free(bufp); 3404 } else { 3405 /* 3406 * see if property is encoded as an int instead of string. 3407 */ 3408 rc = ddi_prop_get_int(match_dev, dip, flags, name, defvalue); 3409 } 3410 3411 return (rc); 3412 } 3413