1*507c3241Smlf /*
2*507c3241Smlf * CDDL HEADER START
3*507c3241Smlf *
4*507c3241Smlf * The contents of this file are subject to the terms of the
5*507c3241Smlf * Common Development and Distribution License (the "License").
6*507c3241Smlf * You may not use this file except in compliance with the License.
7*507c3241Smlf *
8*507c3241Smlf * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*507c3241Smlf * or http://www.opensolaris.org/os/licensing.
10*507c3241Smlf * See the License for the specific language governing permissions
11*507c3241Smlf * and limitations under the License.
12*507c3241Smlf *
13*507c3241Smlf * When distributing Covered Code, include this CDDL HEADER in each
14*507c3241Smlf * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*507c3241Smlf * If applicable, add the following below this CDDL HEADER, with the
16*507c3241Smlf * fields enclosed by brackets "[]" replaced with your own identifying
17*507c3241Smlf * information: Portions Copyright [yyyy] [name of copyright owner]
18*507c3241Smlf *
19*507c3241Smlf * CDDL HEADER END
20*507c3241Smlf */
21*507c3241Smlf
22*507c3241Smlf /*
23*507c3241Smlf * Copyright 2004 Sun Microsystems, Inc. All rights reserved.
24*507c3241Smlf * Use is subject to license terms.
25*507c3241Smlf */
26*507c3241Smlf
27*507c3241Smlf #include <sys/types.h>
28*507c3241Smlf #include <sys/debug.h>
29*507c3241Smlf
30*507c3241Smlf #include "ata_common.h"
31*507c3241Smlf #include "ata_disk.h"
32*507c3241Smlf #include "atapi.h"
33*507c3241Smlf #include "pciide.h"
34*507c3241Smlf
35*507c3241Smlf /*
36*507c3241Smlf * grap the PCI-IDE status byte
37*507c3241Smlf */
38*507c3241Smlf #define PCIIDE_STATUS_GET(hdl, addr) \
39*507c3241Smlf ddi_get8((hdl), ((uchar_t *)(addr) + PCIIDE_BMISX_REG))
40*507c3241Smlf
41*507c3241Smlf /*
42*507c3241Smlf * DMA attributes for device I/O
43*507c3241Smlf */
44*507c3241Smlf
45*507c3241Smlf ddi_dma_attr_t ata_pciide_dma_attr = {
46*507c3241Smlf DMA_ATTR_V0, /* dma_attr_version */
47*507c3241Smlf 0, /* dma_attr_addr_lo */
48*507c3241Smlf 0xffffffffU, /* dma_attr_addr_hi */
49*507c3241Smlf 0xffff, /* dma_attr_count_max */
50*507c3241Smlf sizeof (int), /* dma_attr_align */
51*507c3241Smlf 1, /* dma_attr_burstsizes */
52*507c3241Smlf 1, /* dma_attr_minxfer */
53*507c3241Smlf 0x100 << SCTRSHFT, /* dma_attr_maxxfer */
54*507c3241Smlf /* note that this value can change */
55*507c3241Smlf /* based on max_transfer property */
56*507c3241Smlf 0xffff, /* dma_attr_seg */
57*507c3241Smlf ATA_DMA_NSEGS, /* dma_attr_sgllen */
58*507c3241Smlf 512, /* dma_attr_granular */
59*507c3241Smlf 0 /* dma_attr_flags */
60*507c3241Smlf };
61*507c3241Smlf
62*507c3241Smlf /*
63*507c3241Smlf * DMA attributes for the Bus Mastering PRD table
64*507c3241Smlf *
65*507c3241Smlf * PRD table Must not cross 4k boundary.
66*507c3241Smlf *
67*507c3241Smlf * NOTE: the SFF-8038i spec says don't cross a 64k boundary but
68*507c3241Smlf * some chip specs seem to think the spec says 4k boundary, Intel
69*507c3241Smlf * 82371AB, section 5.2.3. I don't know whether the 4k restriction
70*507c3241Smlf * is for real or just a typo. I've specified 4k just to be safe.
71*507c3241Smlf * The same Intel spec says the buffer must be 64K aligned, I don't
72*507c3241Smlf * believe that and have specified 4 byte alignment.
73*507c3241Smlf *
74*507c3241Smlf */
75*507c3241Smlf
76*507c3241Smlf #define PCIIDE_BOUNDARY (0x1000)
77*507c3241Smlf
78*507c3241Smlf ddi_dma_attr_t ata_prd_dma_attr = {
79*507c3241Smlf DMA_ATTR_V0, /* dma_attr_version */
80*507c3241Smlf 0, /* dma_attr_addr_lo */
81*507c3241Smlf 0xffffffffU, /* dma_attr_addr_hi */
82*507c3241Smlf PCIIDE_BOUNDARY - 1, /* dma_attr_count_max */
83*507c3241Smlf sizeof (int), /* dma_attr_align */
84*507c3241Smlf 1, /* dma_attr_burstsizes */
85*507c3241Smlf 1, /* dma_attr_minxfer */
86*507c3241Smlf PCIIDE_BOUNDARY, /* dma_attr_maxxfer */
87*507c3241Smlf PCIIDE_BOUNDARY - 1, /* dma_attr_seg */
88*507c3241Smlf 1, /* dma_attr_sgllen */
89*507c3241Smlf 1, /* dma_attr_granular */
90*507c3241Smlf 0 /* dma_attr_flags */
91*507c3241Smlf };
92*507c3241Smlf
93*507c3241Smlf
94*507c3241Smlf
95*507c3241Smlf size_t prd_size = sizeof (prde_t) * ATA_DMA_NSEGS;
96*507c3241Smlf
97*507c3241Smlf int
ata_pciide_alloc(dev_info_t * dip,ata_ctl_t * ata_ctlp)98*507c3241Smlf ata_pciide_alloc(
99*507c3241Smlf dev_info_t *dip,
100*507c3241Smlf ata_ctl_t *ata_ctlp)
101*507c3241Smlf {
102*507c3241Smlf ddi_device_acc_attr_t dev_attr;
103*507c3241Smlf ddi_dma_cookie_t cookie;
104*507c3241Smlf size_t buf_size;
105*507c3241Smlf uint_t count;
106*507c3241Smlf int rc;
107*507c3241Smlf
108*507c3241Smlf dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
109*507c3241Smlf dev_attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC;
110*507c3241Smlf dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
111*507c3241Smlf
112*507c3241Smlf
113*507c3241Smlf rc = ddi_dma_alloc_handle(dip, &ata_prd_dma_attr, DDI_DMA_SLEEP, NULL,
114*507c3241Smlf &ata_ctlp->ac_sg_handle);
115*507c3241Smlf if (rc != DDI_SUCCESS) {
116*507c3241Smlf ADBG_ERROR(("ata_pciide_alloc 0x%p handle %d\n",
117*507c3241Smlf (void *)ata_ctlp, rc));
118*507c3241Smlf goto err3;
119*507c3241Smlf }
120*507c3241Smlf
121*507c3241Smlf rc = ddi_dma_mem_alloc(ata_ctlp->ac_sg_handle, prd_size, &dev_attr,
122*507c3241Smlf DDI_DMA_CONSISTENT, DDI_DMA_SLEEP, NULL,
123*507c3241Smlf &ata_ctlp->ac_sg_list, &buf_size, &ata_ctlp->ac_sg_acc_handle);
124*507c3241Smlf if (rc != DDI_SUCCESS) {
125*507c3241Smlf ADBG_ERROR(("ata_pciide_alloc 0x%p mem %d\n",
126*507c3241Smlf (void *)ata_ctlp, rc));
127*507c3241Smlf goto err2;
128*507c3241Smlf }
129*507c3241Smlf
130*507c3241Smlf rc = ddi_dma_addr_bind_handle(ata_ctlp->ac_sg_handle, NULL,
131*507c3241Smlf ata_ctlp->ac_sg_list, buf_size,
132*507c3241Smlf DDI_DMA_WRITE | DDI_DMA_CONSISTENT,
133*507c3241Smlf DDI_DMA_SLEEP, NULL, &cookie, &count);
134*507c3241Smlf if (rc != DDI_DMA_MAPPED) {
135*507c3241Smlf ADBG_ERROR(("ata_pciide_alloc 0x%p bind %d\n",
136*507c3241Smlf (void *)ata_ctlp, rc));
137*507c3241Smlf goto err1;
138*507c3241Smlf }
139*507c3241Smlf
140*507c3241Smlf ASSERT(count == 1);
141*507c3241Smlf ASSERT((cookie.dmac_address & (sizeof (int) - 1)) == 0);
142*507c3241Smlf #define Mask4K 0xfffff000
143*507c3241Smlf ASSERT((cookie.dmac_address & Mask4K)
144*507c3241Smlf == ((cookie.dmac_address + cookie.dmac_size - 1) & Mask4K));
145*507c3241Smlf
146*507c3241Smlf ata_ctlp->ac_sg_paddr = cookie.dmac_address;
147*507c3241Smlf return (TRUE);
148*507c3241Smlf err1:
149*507c3241Smlf ddi_dma_mem_free(&ata_ctlp->ac_sg_acc_handle);
150*507c3241Smlf ata_ctlp->ac_sg_acc_handle = NULL;
151*507c3241Smlf err2:
152*507c3241Smlf ddi_dma_free_handle(&ata_ctlp->ac_sg_handle);
153*507c3241Smlf ata_ctlp->ac_sg_handle = NULL;
154*507c3241Smlf err3:
155*507c3241Smlf return (FALSE);
156*507c3241Smlf }
157*507c3241Smlf
158*507c3241Smlf
159*507c3241Smlf void
ata_pciide_free(ata_ctl_t * ata_ctlp)160*507c3241Smlf ata_pciide_free(ata_ctl_t *ata_ctlp)
161*507c3241Smlf {
162*507c3241Smlf if (ata_ctlp->ac_sg_handle == NULL)
163*507c3241Smlf return;
164*507c3241Smlf
165*507c3241Smlf (void) ddi_dma_unbind_handle(ata_ctlp->ac_sg_handle);
166*507c3241Smlf ddi_dma_mem_free(&ata_ctlp->ac_sg_acc_handle);
167*507c3241Smlf ddi_dma_free_handle(&ata_ctlp->ac_sg_handle);
168*507c3241Smlf ata_ctlp->ac_sg_handle = NULL;
169*507c3241Smlf ata_ctlp->ac_sg_acc_handle = NULL;
170*507c3241Smlf }
171*507c3241Smlf
172*507c3241Smlf
173*507c3241Smlf
174*507c3241Smlf void
ata_pciide_dma_setup(ata_ctl_t * ata_ctlp,prde_t * srcp,int sg_cnt)175*507c3241Smlf ata_pciide_dma_setup(
176*507c3241Smlf ata_ctl_t *ata_ctlp,
177*507c3241Smlf prde_t *srcp,
178*507c3241Smlf int sg_cnt)
179*507c3241Smlf {
180*507c3241Smlf ddi_acc_handle_t bmhandle = ata_ctlp->ac_bmhandle;
181*507c3241Smlf caddr_t bmaddr = ata_ctlp->ac_bmaddr;
182*507c3241Smlf ddi_acc_handle_t sg_acc_handle = ata_ctlp->ac_sg_acc_handle;
183*507c3241Smlf uint_t *dstp = (uint_t *)ata_ctlp->ac_sg_list;
184*507c3241Smlf int idx;
185*507c3241Smlf
186*507c3241Smlf ASSERT(dstp != 0);
187*507c3241Smlf ASSERT(sg_cnt != 0);
188*507c3241Smlf
189*507c3241Smlf ADBG_DMA(("ata dma_setup 0x%p 0x%p %d\n", ata_ctlp, srcp, sg_cnt));
190*507c3241Smlf /*
191*507c3241Smlf * Copy the PRD list to controller's phys buffer.
192*507c3241Smlf * Copying to a fixed location avoids having to check
193*507c3241Smlf * every ata_pkt for alignment and page boundaries.
194*507c3241Smlf */
195*507c3241Smlf for (idx = 0; idx < sg_cnt - 1; idx++, srcp++) {
196*507c3241Smlf ddi_put32(sg_acc_handle, dstp++, srcp->p_address);
197*507c3241Smlf ddi_put32(sg_acc_handle, dstp++, srcp->p_count);
198*507c3241Smlf }
199*507c3241Smlf
200*507c3241Smlf /*
201*507c3241Smlf * set the end of table flag in the last entry
202*507c3241Smlf */
203*507c3241Smlf srcp->p_count |= PCIIDE_PRDE_EOT;
204*507c3241Smlf ddi_put32(sg_acc_handle, dstp++, srcp->p_address);
205*507c3241Smlf ddi_put32(sg_acc_handle, dstp++, srcp->p_count);
206*507c3241Smlf
207*507c3241Smlf /*
208*507c3241Smlf * give the pciide chip the physical address of the PRDE table
209*507c3241Smlf */
210*507c3241Smlf ddi_put32(bmhandle, (uint_t *)(bmaddr + PCIIDE_BMIDTPX_REG),
211*507c3241Smlf ata_ctlp->ac_sg_paddr);
212*507c3241Smlf
213*507c3241Smlf ADBG_DMA(("ata dma_setup 0x%p 0x%llx\n",
214*507c3241Smlf bmaddr, (unsigned long long)ata_ctlp->ac_sg_paddr));
215*507c3241Smlf }
216*507c3241Smlf
217*507c3241Smlf
218*507c3241Smlf
219*507c3241Smlf void
ata_pciide_dma_start(ata_ctl_t * ata_ctlp,uchar_t direction)220*507c3241Smlf ata_pciide_dma_start(
221*507c3241Smlf ata_ctl_t *ata_ctlp,
222*507c3241Smlf uchar_t direction)
223*507c3241Smlf {
224*507c3241Smlf ddi_acc_handle_t bmhandle = ata_ctlp->ac_bmhandle;
225*507c3241Smlf caddr_t bmaddr = ata_ctlp->ac_bmaddr;
226*507c3241Smlf uchar_t tmp;
227*507c3241Smlf
228*507c3241Smlf ASSERT((ata_ctlp->ac_sg_paddr & PCIIDE_BMIDTPX_MASK) == 0);
229*507c3241Smlf ASSERT((direction == PCIIDE_BMICX_RWCON_WRITE_TO_MEMORY) ||
230*507c3241Smlf (direction == PCIIDE_BMICX_RWCON_READ_FROM_MEMORY));
231*507c3241Smlf
232*507c3241Smlf /*
233*507c3241Smlf * Set the direction control and start the PCIIDE DMA controller
234*507c3241Smlf */
235*507c3241Smlf tmp = ddi_get8(bmhandle, (uchar_t *)bmaddr + PCIIDE_BMICX_REG);
236*507c3241Smlf tmp &= PCIIDE_BMICX_MASK;
237*507c3241Smlf ddi_put8(bmhandle, (uchar_t *)bmaddr + PCIIDE_BMICX_REG,
238*507c3241Smlf (tmp | direction));
239*507c3241Smlf
240*507c3241Smlf ddi_put8(bmhandle, (uchar_t *)bmaddr + PCIIDE_BMICX_REG,
241*507c3241Smlf (tmp | PCIIDE_BMICX_SSBM_E | direction));
242*507c3241Smlf
243*507c3241Smlf return;
244*507c3241Smlf
245*507c3241Smlf }
246*507c3241Smlf
247*507c3241Smlf
248*507c3241Smlf void
ata_pciide_dma_stop(ata_ctl_t * ata_ctlp)249*507c3241Smlf ata_pciide_dma_stop(
250*507c3241Smlf ata_ctl_t *ata_ctlp)
251*507c3241Smlf {
252*507c3241Smlf ddi_acc_handle_t bmhandle = ata_ctlp->ac_bmhandle;
253*507c3241Smlf caddr_t bmaddr = ata_ctlp->ac_bmaddr;
254*507c3241Smlf uchar_t tmp;
255*507c3241Smlf
256*507c3241Smlf /*
257*507c3241Smlf * Stop the PCIIDE DMA controller
258*507c3241Smlf */
259*507c3241Smlf tmp = ddi_get8(bmhandle, (uchar_t *)bmaddr + PCIIDE_BMICX_REG);
260*507c3241Smlf tmp &= (PCIIDE_BMICX_MASK & (~PCIIDE_BMICX_SSBM));
261*507c3241Smlf
262*507c3241Smlf ADBG_DMA(("ata_pciide_dma_stop 0x%p 0x%x\n", bmaddr, tmp));
263*507c3241Smlf
264*507c3241Smlf ddi_put8(bmhandle, (uchar_t *)bmaddr + PCIIDE_BMICX_REG, tmp);
265*507c3241Smlf }
266*507c3241Smlf
267*507c3241Smlf /* ARGSUSED */
268*507c3241Smlf void
ata_pciide_dma_sg_func(gcmd_t * gcmdp,ddi_dma_cookie_t * dmackp,int single_segment,int seg_index)269*507c3241Smlf ata_pciide_dma_sg_func(
270*507c3241Smlf gcmd_t *gcmdp,
271*507c3241Smlf ddi_dma_cookie_t *dmackp,
272*507c3241Smlf int single_segment,
273*507c3241Smlf int seg_index)
274*507c3241Smlf {
275*507c3241Smlf ata_pkt_t *ata_pktp = GCMD2APKT(gcmdp);
276*507c3241Smlf prde_t *dmap;
277*507c3241Smlf
278*507c3241Smlf ASSERT(seg_index < ATA_DMA_NSEGS);
279*507c3241Smlf ASSERT(((uint_t)dmackp->dmac_address & PCIIDE_PRDE_ADDR_MASK) == 0);
280*507c3241Smlf ASSERT((dmackp->dmac_size & PCIIDE_PRDE_CNT_MASK) == 0);
281*507c3241Smlf ASSERT(dmackp->dmac_size <= PCIIDE_PRDE_CNT_MAX);
282*507c3241Smlf
283*507c3241Smlf ADBG_TRACE(("adp_dma_sg_func: gcmdp 0x%p dmackp 0x%p s %d idx %d\n",
284*507c3241Smlf gcmdp, dmackp, single_segment, seg_index));
285*507c3241Smlf
286*507c3241Smlf /* set address of current entry in scatter/gather list */
287*507c3241Smlf dmap = ata_pktp->ap_sg_list + seg_index;
288*507c3241Smlf
289*507c3241Smlf /* store the phys addr and count from the cookie */
290*507c3241Smlf dmap->p_address = (uint_t)dmackp->dmac_address;
291*507c3241Smlf dmap->p_count = (uint_t)dmackp->dmac_size;
292*507c3241Smlf
293*507c3241Smlf /* save the count of scatter/gather segments */
294*507c3241Smlf ata_pktp->ap_sg_cnt = seg_index + 1;
295*507c3241Smlf
296*507c3241Smlf /* compute the total bytes in this request */
297*507c3241Smlf if (seg_index == 0)
298*507c3241Smlf ata_pktp->ap_bcount = 0;
299*507c3241Smlf ata_pktp->ap_bcount += dmackp->dmac_size;
300*507c3241Smlf }
301*507c3241Smlf
302*507c3241Smlf
303*507c3241Smlf
304*507c3241Smlf int
ata_pciide_status_clear(ata_ctl_t * ata_ctlp)305*507c3241Smlf ata_pciide_status_clear(
306*507c3241Smlf ata_ctl_t *ata_ctlp)
307*507c3241Smlf {
308*507c3241Smlf ddi_acc_handle_t bmhandle = ata_ctlp->ac_bmhandle;
309*507c3241Smlf caddr_t bmaddr = ata_ctlp->ac_bmaddr;
310*507c3241Smlf uchar_t status;
311*507c3241Smlf uchar_t tmp;
312*507c3241Smlf
313*507c3241Smlf /*
314*507c3241Smlf * Get the current PCIIDE status
315*507c3241Smlf */
316*507c3241Smlf status = PCIIDE_STATUS_GET(ata_ctlp->ac_bmhandle, ata_ctlp->ac_bmaddr);
317*507c3241Smlf tmp = status & PCIIDE_BMISX_MASK;
318*507c3241Smlf tmp |= (PCIIDE_BMISX_IDERR | PCIIDE_BMISX_IDEINTS);
319*507c3241Smlf
320*507c3241Smlf ADBG_DMA(("ata_pciide_status_clear 0x%p 0x%x\n",
321*507c3241Smlf bmaddr, status));
322*507c3241Smlf
323*507c3241Smlf /*
324*507c3241Smlf * Clear the latches (and preserve the other bits)
325*507c3241Smlf */
326*507c3241Smlf ddi_put8(bmhandle, (uchar_t *)bmaddr + PCIIDE_BMISX_REG, tmp);
327*507c3241Smlf
328*507c3241Smlf #ifdef NAT_SEMI_PC87415_BUG
329*507c3241Smlf /* ??? chip errata ??? */
330*507c3241Smlf if (ata_ctlp->ac_nat_semi_bug) {
331*507c3241Smlf tmp = ddi_get8(bmhandle, bmaddr + PCIIDE_BMICX_REG);
332*507c3241Smlf tmp &= PCIIDE_BMICX_MASK;
333*507c3241Smlf ddi_put8(bmhandle, bmaddr + PCIIDE_BMICX_REG,
334*507c3241Smlf (tmp | PCIIDE_BMISX_IDERR | PCIIDE_BMISX_IDEINTS));
335*507c3241Smlf }
336*507c3241Smlf #endif
337*507c3241Smlf return (status);
338*507c3241Smlf }
339*507c3241Smlf
340*507c3241Smlf int
ata_pciide_status_dmacheck_clear(ata_ctl_t * ata_ctlp)341*507c3241Smlf ata_pciide_status_dmacheck_clear(
342*507c3241Smlf ata_ctl_t *ata_ctlp)
343*507c3241Smlf {
344*507c3241Smlf uchar_t status;
345*507c3241Smlf
346*507c3241Smlf /*
347*507c3241Smlf * Get the PCIIDE DMA controller's current status
348*507c3241Smlf */
349*507c3241Smlf status = ata_pciide_status_clear(ata_ctlp);
350*507c3241Smlf
351*507c3241Smlf ADBG_DMA(("ata_pciide_status_dmacheck_clear 0x%p 0x%x\n",
352*507c3241Smlf ata_ctlp->ac_bmaddr, status));
353*507c3241Smlf /*
354*507c3241Smlf * check for errors
355*507c3241Smlf */
356*507c3241Smlf if (status & PCIIDE_BMISX_IDERR) {
357*507c3241Smlf ADBG_WARN(("ata_pciide_status: 0x%x\n", status));
358*507c3241Smlf return (TRUE);
359*507c3241Smlf }
360*507c3241Smlf return (FALSE);
361*507c3241Smlf }
362*507c3241Smlf
363*507c3241Smlf
364*507c3241Smlf
365*507c3241Smlf /*
366*507c3241Smlf * Check for a pending PCI-IDE interrupt
367*507c3241Smlf */
368*507c3241Smlf
369*507c3241Smlf int
ata_pciide_status_pending(ata_ctl_t * ata_ctlp)370*507c3241Smlf ata_pciide_status_pending(
371*507c3241Smlf ata_ctl_t *ata_ctlp)
372*507c3241Smlf {
373*507c3241Smlf uchar_t status;
374*507c3241Smlf
375*507c3241Smlf status = PCIIDE_STATUS_GET(ata_ctlp->ac_bmhandle, ata_ctlp->ac_bmaddr);
376*507c3241Smlf ADBG_DMA(("ata_pciide_status_pending 0x%p 0x%x\n",
377*507c3241Smlf ata_ctlp->ac_bmaddr, status));
378*507c3241Smlf if (status & PCIIDE_BMISX_IDEINTS)
379*507c3241Smlf return (TRUE);
380*507c3241Smlf return (FALSE);
381*507c3241Smlf }
382