1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * Finite State Machines for ATA controller and ATAPI devices 31 */ 32 33 #include <sys/types.h> 34 35 #include "ata_common.h" 36 #include "atapi.h" 37 38 /* 39 * Local functions 40 */ 41 static int atapi_start_cmd(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 42 ata_pkt_t *ata_pktp); 43 static void atapi_send_cdb(ata_ctl_t *ata_ctlp, ata_pkt_t *ata_pktp); 44 static void atapi_start_dma(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp, 45 ata_pkt_t *ata_pktp); 46 static void atapi_pio_data_in(ata_ctl_t *ata_ctlp, ata_pkt_t *ata_pktp); 47 static void atapi_pio_data_out(ata_ctl_t *ata_ctlp, ata_pkt_t *ata_pktp); 48 static void atapi_status(ata_ctl_t *ata_ctlp, ata_pkt_t *ata_pktp, 49 uchar_t status, int dma_complete); 50 static void atapi_fsm_error(ata_ctl_t *ata_ctlp, uchar_t state, 51 uchar_t event); 52 53 54 55 56 static void 57 atapi_fsm_error( 58 ata_ctl_t *ata_ctlp, 59 uchar_t state, 60 uchar_t event) 61 { 62 ADBG_ERROR(("atapi protocol error: 0x%p 0x%x 0x%x\n", 63 ata_ctlp->ac_data, state, event)); 64 } 65 66 67 /* 68 * 69 * IO CoD DRQ 70 * -- --- --- 71 * 0 0 0 == 0 invalid 72 * 0 0 1 == 1 Data to device 73 * 0 1 0 == 2 Idle 74 * 0 1 1 == 3 Send ATAPI CDB to device 75 * 1 0 0 == 4 invalid 76 * 1 0 1 == 5 Data from device 77 * 1 1 0 == 6 Status ready 78 * 1 1 1 == 7 Future use 79 * 80 */ 81 82 /* 83 * Given the current state and the current event this 84 * table determines what action to take. Note, in the actual 85 * table I've left room for the invalid event codes: 0, 2, and 7. 86 * 87 * +----------------------------------------------------- 88 * | Current Event 89 * | 90 * State | dataout idle cdb datain status 91 * | 1 2 3 5 6 92 * |----------------------------------------------------- 93 * idle | sendcmd sendcmd sendcmd sendcmd sendcmd 94 * cmd | * * sendcdb * read-err-code 95 * cdb | xfer-out nada nada xfer-in read-err-code 96 * datain | * * * xfer-in read-err-code 97 * dataout | xfer-out * * * read-err-code 98 * DMA | * * * * read-err-code 99 * 100 */ 101 102 uchar_t atapi_PioAction[ATAPI_NSTATES][ATAPI_NEVENTS] = { 103 /* invalid dataout idle cdb invalid datain status future */ 104 { A_NADA, A_NADA, A_NADA, A_NADA, A_NADA, A_NADA, A_NADA, A_NADA }, /* Idle */ 105 { A_NADA, A_NADA, A_NADA, A_CDB, A_NADA, A_NADA, A_RE, A_NADA }, /* Cmd */ 106 { A_REX, A_OUT, A_NADA, A_NADA, A_IDLE, A_IN, A_RE, A_UNK }, /* Cdb */ 107 { A_REX, A_UNK, A_IDLE, A_UNK, A_IDLE, A_IN, A_RE, A_UNK }, /* DtaIn */ 108 { A_REX, A_OUT, A_IDLE, A_UNK, A_IDLE, A_UNK, A_RE, A_UNK }, /* DtaOut */ 109 { A_REX, A_UNK, A_UNK, A_UNK, A_UNK, A_UNK, A_RE, A_UNK } /* DmaAct */ 110 }; 111 112 /* 113 * 114 * Give the current state and the current event this table 115 * determines the new state of the device. 116 * 117 * +---------------------------------------------- 118 * | Current Event 119 * | 120 * State | dataout idle cdb datain status 121 * |---------------------------------------------- 122 * idle | cmd cmd cmd cmd cmd 123 * cmd | * * cdb * * 124 * cdb | dataout cdb cdb datain (idle) 125 * datain | * * * datain (idle) 126 * dataout | dataout * * * (idle) 127 * DMA | DMA DMA DMA DMA (idle) 128 * 129 * 130 * Note: the states enclosed in parens "(state)", are the accept states 131 * for this FSM. A separate table is used to encode the done 132 * states rather than extra state codes. 133 * 134 */ 135 136 uchar_t atapi_PioNextState[ATAPI_NSTATES][ATAPI_NEVENTS] = { 137 /* invalid dataout idle cdb invalid datain status future */ 138 { S_IDLE, S_IDLE, S_IDLE, S_IDLE, S_IDLE, S_IDLE, S_IDLE, S_IDLE}, /* idle */ 139 { S_CDB, S_CDB, S_CDB, S_CDB, S_CDB, S_CDB, S_IDLE, S_X }, /* cmd */ 140 { S_IDLE, S_OUT, S_CDB, S_CDB, S_CDB, S_IN, S_IDLE, S_X }, /* cdb */ 141 { S_IDLE, S_X, S_IN, S_X, S_IN, S_IN, S_IDLE, S_X }, /* datain */ 142 { S_IDLE, S_OUT, S_OUT, S_X, S_OUT, S_X, S_IDLE, S_X }, /* dataout */ 143 { S_IDLE, S_DMA, S_DMA, S_DMA, S_DMA, S_DMA, S_IDLE, S_DMA } /* dmaActv */ 144 }; 145 146 147 static int 148 atapi_start_cmd( 149 ata_ctl_t *ata_ctlp, 150 ata_drv_t *ata_drvp, 151 ata_pkt_t *ata_pktp) 152 { 153 ddi_acc_handle_t io_hdl1 = ata_ctlp->ac_iohandle1; 154 ddi_acc_handle_t io_hdl2 = ata_ctlp->ac_iohandle2; 155 156 /* 157 * Bug 1256489: 158 * 159 * If AC_BSY_WAIT is set, wait for controller to be not busy, 160 * before issuing a command. If AC_BSY_WAIT is not set, 161 * skip the wait. This is important for laptops that do 162 * suspend/resume but do not correctly wait for the busy bit to 163 * drop after a resume. 164 */ 165 166 if (ata_ctlp->ac_timing_flags & AC_BSY_WAIT) { 167 if (!ata_wait(io_hdl2, ata_ctlp->ac_ioaddr2, 168 0, ATS_BSY, 5000000)) { 169 ADBG_WARN(("atapi_start: BSY too long!\n")); 170 ata_pktp->ap_flags |= AP_ERROR; 171 return (ATA_FSM_RC_BUSY); 172 } 173 } 174 175 /* 176 * Select the drive 177 */ 178 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, ata_pktp->ap_hd); 179 ATA_DELAY_400NSEC(io_hdl2, ata_ctlp->ac_ioaddr2); 180 181 /* 182 * make certain the drive selected 183 */ 184 if (!ata_wait(io_hdl2, ata_ctlp->ac_ioaddr2, 0, ATS_BSY, 5000000)) { 185 ADBG_ERROR(("atapi_start_cmd: drive select failed\n")); 186 return (ATA_FSM_RC_BUSY); 187 } 188 189 /* 190 * Always make certain interrupts are enabled. It's been reported 191 * (but not confirmed) that some notebook computers don't 192 * clear the interrupt disable bit after being resumed. The 193 * easiest way to fix this is to always clear the disable bit 194 * before every command. 195 */ 196 ddi_put8(io_hdl2, ata_ctlp->ac_devctl, ATDC_D3); 197 198 ddi_put8(io_hdl1, ata_ctlp->ac_lcyl, ata_pktp->ap_lwcyl); 199 ddi_put8(io_hdl1, ata_ctlp->ac_hcyl, ata_pktp->ap_hicyl); 200 ddi_put8(io_hdl1, ata_ctlp->ac_sect, ata_pktp->ap_sec); 201 ddi_put8(io_hdl1, ata_ctlp->ac_count, ata_pktp->ap_count); 202 203 if (ata_pktp->ap_pciide_dma) { 204 205 ASSERT((ata_pktp->ap_flags & (AP_READ | AP_WRITE)) != 0); 206 207 /* 208 * DMA but no Overlap 209 */ 210 ddi_put8(io_hdl1, ata_ctlp->ac_feature, ATF_ATAPI_DMA); 211 212 /* 213 * copy the Scatter/Gather list to the controller's 214 * Physical Region Descriptor Table 215 */ 216 ata_pciide_dma_setup(ata_ctlp, ata_pktp->ap_sg_list, 217 ata_pktp->ap_sg_cnt); 218 } else { 219 /* 220 * no DMA and no Overlap 221 */ 222 ddi_put8(io_hdl1, ata_ctlp->ac_feature, 0); 223 } 224 225 /* 226 * This next one sets the device in motion 227 */ 228 ddi_put8(io_hdl1, ata_ctlp->ac_cmd, ata_pktp->ap_cmd); 229 230 /* wait for the busy bit to settle */ 231 ATA_DELAY_400NSEC(io_hdl2, ata_ctlp->ac_ioaddr2); 232 233 if (!(ata_drvp->ad_flags & AD_NO_CDB_INTR)) { 234 /* 235 * the device will send me an interrupt when it's 236 * ready for the packet 237 */ 238 return (ATA_FSM_RC_OKAY); 239 } 240 241 /* else */ 242 243 /* 244 * If we don't receive an interrupt requesting the scsi CDB, 245 * we must poll for DRQ, and then send out the CDB. 246 */ 247 248 /* 249 * Wait for DRQ before sending the CDB. Bailout early 250 * if an error occurs. 251 * 252 * I'm not certain what the correct timeout should be. 253 */ 254 if (ata_wait3(io_hdl2, ata_ctlp->ac_ioaddr2, 255 ATS_DRQ, ATS_BSY, /* okay */ 256 ATS_ERR, ATS_BSY, /* cmd failed */ 257 ATS_DF, ATS_BSY, /* cmd failed */ 258 4000000)) { 259 /* got good status */ 260 return (ATA_FSM_RC_INTR); 261 } 262 263 ADBG_WARN(("atapi_start_cmd: 0x%x status 0x%x error 0x%x\n", 264 ata_pktp->ap_cmd, 265 ddi_get8(io_hdl2, ata_ctlp->ac_altstatus), 266 ddi_get8(io_hdl1, ata_ctlp->ac_error))); 267 268 return (ATA_FSM_RC_INTR); 269 } 270 271 272 /* 273 * 274 * Send the SCSI CDB to the ATAPI device 275 * 276 */ 277 278 static void 279 atapi_send_cdb( 280 ata_ctl_t *ata_ctlp, 281 ata_pkt_t *ata_pktp) 282 { 283 ddi_acc_handle_t io_hdl1 = ata_ctlp->ac_iohandle1; 284 ddi_acc_handle_t io_hdl2 = ata_ctlp->ac_iohandle2; 285 int padding; 286 287 ADBG_TRACE(("atapi_send_cdb entered\n")); 288 289 /* 290 * send the CDB to the drive 291 */ 292 ddi_rep_put16(io_hdl1, (ushort_t *)ata_pktp->ap_cdbp, ata_ctlp->ac_data, 293 ata_pktp->ap_cdb_len >> 1, DDI_DEV_NO_AUTOINCR); 294 295 /* 296 * pad to ad_cdb_len bytes 297 */ 298 299 padding = ata_pktp->ap_cdb_pad; 300 301 while (padding) { 302 ddi_put16(io_hdl1, ata_ctlp->ac_data, 0); 303 padding--; 304 } 305 306 /* wait for the busy bit to settle */ 307 ATA_DELAY_400NSEC(io_hdl2, ata_ctlp->ac_ioaddr2); 308 309 #ifdef ATA_DEBUG_XXX 310 { 311 uchar_t *cp = ata_pktp->ap_cdbp; 312 313 ADBG_TRANSPORT(("\tatapi scsi cmd (%d bytes):\n ", 314 ata_pktp->ap_cdb_len)); 315 ADBG_TRANSPORT(("\t\t 0x%x 0x%x 0x%x 0x%x\n", 316 cp[0], cp[1], cp[2], cp[3])); 317 ADBG_TRANSPORT(("\t\t 0x%x 0x%x 0x%x 0x%x\n", 318 cp[4], cp[5], cp[6], cp[7])); 319 ADBG_TRANSPORT(("\t\t 0x%x 0x%x 0x%x 0x%x\n", 320 cp[8], cp[9], cp[10], cp[11])); 321 } 322 #endif 323 324 ata_pktp->ap_flags |= AP_SENT_CMD; 325 } 326 327 328 329 /* 330 * Start the DMA engine 331 */ 332 333 /* ARGSUSED */ 334 static void 335 atapi_start_dma( 336 ata_ctl_t *ata_ctlp, 337 ata_drv_t *ata_drvp, 338 ata_pkt_t *ata_pktp) 339 { 340 uchar_t rd_wr; 341 342 /* 343 * Determine the direction. This may look backwards 344 * but the command bit programmed into the DMA engine 345 * specifies the type of operation the engine performs 346 * on the PCI bus (not the ATA bus). Therefore when 347 * transferring data from the device to system memory, the 348 * DMA engine performs PCI Write operations. 349 */ 350 if (ata_pktp->ap_flags & AP_READ) 351 rd_wr = PCIIDE_BMICX_RWCON_WRITE_TO_MEMORY; 352 else 353 rd_wr = PCIIDE_BMICX_RWCON_READ_FROM_MEMORY; 354 355 /* 356 * Start the DMA engine 357 */ 358 ata_pciide_dma_start(ata_ctlp, rd_wr); 359 } 360 361 362 363 /* 364 * Transfer the data from the device 365 * 366 * Note: the atapi_pio_data_in() and atapi_pio_data_out() functions 367 * are complicated a lot by the requirement to handle an odd byte count. 368 * The only device we've seen which does this is the Hitachi CDR-7730. 369 * See bug ID 1214595. It's my understanding that Dell stopped shipping 370 * that drive after discovering all the problems it caused, so it may 371 * be impossible to find one for any sort of regression test. 372 * 373 * In the future, ATAPI tape drives will also probably support odd byte 374 * counts so this code will be excersized more often. 375 * 376 */ 377 378 static void 379 atapi_pio_data_in( 380 ata_ctl_t *ata_ctlp, 381 ata_pkt_t *ata_pktp) 382 { 383 ddi_acc_handle_t io_hdl1 = ata_ctlp->ac_iohandle1; 384 ddi_acc_handle_t io_hdl2 = ata_ctlp->ac_iohandle2; 385 int drive_bytes; 386 int xfer_bytes; 387 int xfer_words; 388 389 ata_pktp->ap_flags |= AP_XFERRED_DATA; 390 391 /* 392 * Get the device's byte count for this transfer 393 */ 394 drive_bytes = ((int)ddi_get8(io_hdl1, ata_ctlp->ac_hcyl) << 8) 395 + ddi_get8(io_hdl1, ata_ctlp->ac_lcyl); 396 397 /* 398 * Determine actual number I'm going to transfer. My 399 * buffer might have fewer bytes than what the device 400 * expects or handles on each interrupt. 401 */ 402 xfer_bytes = min(ata_pktp->ap_resid, drive_bytes); 403 404 ASSERT(xfer_bytes >= 0); 405 406 /* 407 * Round down my transfer count to whole words so that 408 * if the transfer count is odd it's still handled correctly. 409 */ 410 xfer_words = xfer_bytes / 2; 411 412 if (xfer_words) { 413 int byte_count = xfer_words * 2; 414 415 ddi_rep_get16(io_hdl1, (ushort_t *)ata_pktp->ap_v_addr, 416 ata_ctlp->ac_data, xfer_words, DDI_DEV_NO_AUTOINCR); 417 418 ata_pktp->ap_v_addr += byte_count; 419 drive_bytes -= byte_count; 420 } 421 422 /* 423 * Handle possible odd byte at end. Read a 16-bit 424 * word but discard the high-order byte. 425 */ 426 if (xfer_bytes & 1) { 427 ushort_t tmp_word; 428 429 tmp_word = ddi_get16(io_hdl1, ata_ctlp->ac_data); 430 *ata_pktp->ap_v_addr++ = tmp_word & 0xff; 431 drive_bytes -= 2; 432 } 433 434 ata_pktp->ap_resid -= xfer_bytes; 435 436 ADBG_TRANSPORT(("atapi_pio_data_in: read 0x%x bytes\n", xfer_bytes)); 437 438 /* 439 * Discard any unwanted data. 440 */ 441 if (drive_bytes > 0) { 442 ADBG_TRANSPORT(("atapi_pio_data_in: dump 0x%x bytes\n", 443 drive_bytes)); 444 445 /* rounded up if the drive_bytes count is odd */ 446 for (; drive_bytes > 0; drive_bytes -= 2) 447 (void) ddi_get16(io_hdl1, ata_ctlp->ac_data); 448 } 449 450 /* wait for the busy bit to settle */ 451 ATA_DELAY_400NSEC(io_hdl2, ata_ctlp->ac_ioaddr2); 452 } 453 454 455 /* 456 * Transfer the data to the device 457 */ 458 459 static void 460 atapi_pio_data_out( 461 ata_ctl_t *ata_ctlp, 462 ata_pkt_t *ata_pktp) 463 { 464 ddi_acc_handle_t io_hdl1 = ata_ctlp->ac_iohandle1; 465 ddi_acc_handle_t io_hdl2 = ata_ctlp->ac_iohandle2; 466 int drive_bytes; 467 int xfer_bytes; 468 int xfer_words; 469 470 ata_pktp->ap_flags |= AP_XFERRED_DATA; 471 472 /* 473 * Get the device's byte count for this transfer 474 */ 475 drive_bytes = ((int)ddi_get8(io_hdl1, ata_ctlp->ac_hcyl) << 8) 476 + ddi_get8(io_hdl1, ata_ctlp->ac_lcyl); 477 478 /* 479 * Determine actual number I'm going to transfer. My 480 * buffer might have fewer bytes than what the device 481 * expects or handles on each interrupt. 482 */ 483 xfer_bytes = min(ata_pktp->ap_resid, drive_bytes); 484 485 /* 486 * Round down my transfer count to whole words so that 487 * if the transfer count is odd it's handled correctly. 488 */ 489 xfer_words = xfer_bytes / 2; 490 491 if (xfer_words) { 492 int byte_count = xfer_words * 2; 493 494 ddi_rep_put16(io_hdl1, (ushort_t *)ata_pktp->ap_v_addr, 495 ata_ctlp->ac_data, xfer_words, DDI_DEV_NO_AUTOINCR); 496 ata_pktp->ap_v_addr += byte_count; 497 } 498 499 /* 500 * If odd byte count, transfer the last 501 * byte. Use a tmp so that I don't run off 502 * the end off the buffer and possibly page 503 * fault. 504 */ 505 if (xfer_bytes & 1) { 506 ushort_t tmp_word; 507 508 /* grab the last unsigned byte and widen it to 16-bits */ 509 tmp_word = *ata_pktp->ap_v_addr++; 510 ddi_put16(io_hdl1, ata_ctlp->ac_data, tmp_word); 511 } 512 513 ata_pktp->ap_resid -= xfer_bytes; 514 515 ADBG_TRANSPORT(("atapi_pio_data_out: wrote 0x%x bytes\n", xfer_bytes)); 516 517 /* wait for the busy bit to settle */ 518 ATA_DELAY_400NSEC(io_hdl2, ata_ctlp->ac_ioaddr2); 519 } 520 521 522 /* 523 * 524 * check status of completed command 525 * 526 */ 527 static void 528 atapi_status( 529 ata_ctl_t *ata_ctlp, 530 ata_pkt_t *ata_pktp, 531 uchar_t status, 532 int dma_completion) 533 { 534 ddi_acc_handle_t io_hdl1 = ata_ctlp->ac_iohandle1; 535 536 ata_pktp->ap_flags |= AP_GOT_STATUS; 537 538 if (status & (ATS_DF | ATS_ERR)) { 539 ata_pktp->ap_flags |= AP_ERROR; 540 } 541 542 if (ata_pktp->ap_flags & AP_ERROR) { 543 ata_pktp->ap_status = status; 544 ata_pktp->ap_error = ddi_get8(io_hdl1, ata_ctlp->ac_error); 545 } 546 547 548 /* 549 * If the DMA transfer failed leave the resid set to 550 * the original byte count. The target driver has 551 * to do a REQUEST SENSE to get the true residual 552 * byte count. Otherwise, it all transferred so update 553 * the flags and residual byte count. 554 */ 555 if (dma_completion && !(ata_pktp->ap_flags & AP_TRAN_ERROR)) { 556 ata_pktp->ap_flags |= AP_XFERRED_DATA; 557 ata_pktp->ap_resid = 0; 558 } 559 } 560 561 562 static void 563 atapi_device_reset( 564 ata_ctl_t *ata_ctlp, 565 ata_drv_t *ata_drvp) 566 { 567 ddi_acc_handle_t io_hdl1 = ata_ctlp->ac_iohandle1; 568 ddi_acc_handle_t io_hdl2 = ata_ctlp->ac_iohandle2; 569 570 /* select the drive */ 571 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, ata_drvp->ad_drive_bits); 572 ATA_DELAY_400NSEC(io_hdl2, ata_ctlp->ac_ioaddr2); 573 574 /* issue atapi DEVICE RESET */ 575 ddi_put8(io_hdl1, ata_ctlp->ac_cmd, ATC_DEVICE_RESET); 576 577 /* wait for the busy bit to settle */ 578 ATA_DELAY_400NSEC(io_hdl2, ata_ctlp->ac_ioaddr2); 579 580 /* 581 * Re-select the drive (this is probably only necessary 582 * when resetting drive 1). 583 */ 584 ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, ata_drvp->ad_drive_bits); 585 ATA_DELAY_400NSEC(io_hdl2, ata_ctlp->ac_ioaddr2); 586 587 /* allow the drive the full 6 seconds to respond */ 588 /* LINTED */ 589 if (!ata_wait(io_hdl2, ata_ctlp->ac_ioaddr2, 0, ATS_BSY, 6 * 1000000)) { 590 ADBG_WARN(("atapi_device_reset: still busy\n")); 591 /* 592 * It's not clear to me what to do at this point, 593 * the drive might be dead or might eventually 594 * recover. For now just ignore it and continue 595 * to attempt to use the drive. 596 */ 597 } 598 } 599 600 601 602 void 603 atapi_fsm_reset(ata_ctl_t *ata_ctlp) 604 { 605 ata_drv_t *ata_drvp; 606 int drive; 607 608 /* 609 * reset drive drive 0 and the drive 1 610 */ 611 for (drive = 0; drive <= 1; drive++) { 612 ata_drvp = CTL2DRV(ata_ctlp, drive, 0); 613 if (ata_drvp && ATAPIDRV(ata_drvp)) { 614 ata_drvp->ad_state = S_IDLE; 615 atapi_device_reset(ata_ctlp, ata_drvp); 616 } 617 } 618 } 619 620 621 int 622 atapi_fsm_start( 623 ata_ctl_t *ata_ctlp, 624 ata_drv_t *ata_drvp, 625 ata_pkt_t *ata_pktp) 626 { 627 int rc; 628 629 ADBG_TRACE(("atapi_start entered\n")); 630 ADBG_TRANSPORT(("atapi_start: pkt = 0x%p\n", ata_pktp)); 631 632 /* 633 * check for valid state 634 */ 635 if (ata_drvp->ad_state != S_IDLE) { 636 ADBG_ERROR(("atapi_fsm_start not idle 0x%x\n", 637 ata_drvp->ad_state)); 638 return (ATA_FSM_RC_BUSY); 639 } else { 640 ata_drvp->ad_state = S_CMD; 641 } 642 643 rc = atapi_start_cmd(ata_ctlp, ata_drvp, ata_pktp); 644 645 switch (rc) { 646 case ATA_FSM_RC_OKAY: 647 /* 648 * The command started okay. Just return. 649 */ 650 break; 651 case ATA_FSM_RC_INTR: 652 /* 653 * Got Command Phase. The upper layer will send 654 * the cdb by faking an interrupt. 655 */ 656 break; 657 case ATA_FSM_RC_FINI: 658 /* 659 * command completed immediately, stick on done q 660 */ 661 break; 662 case ATA_FSM_RC_BUSY: 663 /* 664 * The command wouldn't start, tell the upper layer to 665 * stick this request on the done queue. 666 */ 667 ata_drvp->ad_state = S_IDLE; 668 return (ATA_FSM_RC_BUSY); 669 } 670 return (rc); 671 } 672 673 /* 674 * 675 * All interrupts on an ATAPI device come through here. 676 * This function determines what to do next, based on 677 * the current state of the request and the drive's current 678 * status bits. See the FSM tables at the top of this file. 679 * 680 */ 681 682 int 683 atapi_fsm_intr( 684 ata_ctl_t *ata_ctlp, 685 ata_drv_t *ata_drvp, 686 ata_pkt_t *ata_pktp) 687 { 688 ddi_acc_handle_t io_hdl1 = ata_ctlp->ac_iohandle1; 689 uchar_t status; 690 uchar_t intr_reason; 691 uchar_t state; 692 uchar_t event; 693 uchar_t action; 694 695 696 /* 697 * get the prior state 698 */ 699 state = ata_drvp->ad_state; 700 701 /* 702 * If doing DMA, then: 703 * 704 * 1. halt the DMA engine 705 * 2. reset the interrupt and error latches 706 * 3. reset the drive's IRQ. 707 * 708 * I think the order of these operations must be 709 * exactly as listed. Otherwise we the PCI-IDE 710 * controller can hang or we can miss the next interrupt 711 * edge. 712 * 713 */ 714 switch (state) { 715 case S_DMA: 716 ASSERT(ata_pktp->ap_pciide_dma == TRUE); 717 /* 718 * Halt the DMA engine. When we reach this point 719 * we already know for certain that the device has 720 * an interrupt pending since the ata_get_status() 721 * function already checked the PCI-IDE interrupt 722 * status bit. 723 */ 724 ata_pciide_dma_stop(ata_ctlp); 725 /*FALLTHRU*/ 726 case S_IDLE: 727 case S_CMD: 728 case S_CDB: 729 case S_IN: 730 case S_OUT: 731 break; 732 } 733 734 735 /* 736 * Clear the PCI-IDE latches and the drive's IRQ 737 */ 738 status = ata_get_status_clear_intr(ata_ctlp, ata_pktp); 739 740 /* 741 * some non-compliant (i.e., NEC) drives don't 742 * set ATS_BSY within 400 nsec. and/or don't keep 743 * it asserted until they're actually non-busy. 744 * There's a small window between reading the alt_status 745 * and status registers where the drive might "bounce" 746 * the ATS_BSY bit. 747 */ 748 if (status & ATS_BSY) 749 return (ATA_FSM_RC_BUSY); 750 751 /* 752 * get the interrupt reason code 753 */ 754 intr_reason = ddi_get8(io_hdl1, ata_ctlp->ac_count); 755 756 /* 757 * encode the status and interrupt reason bits 758 * into an event code which is used to index the 759 * FSM tables 760 */ 761 event = ATAPI_EVENT(status, intr_reason); 762 763 /* 764 * determine the action for this event 765 */ 766 action = atapi_PioAction[state][event]; 767 768 /* 769 * determine the new state 770 */ 771 ata_drvp->ad_state = atapi_PioNextState[state][event]; 772 773 switch (action) { 774 default: 775 case A_UNK: 776 /* 777 * invalid state 778 */ 779 /* 780 * ??? this shouldn't happen. ??? 781 * if there's an active command on 782 * this device, the pkt timer should eventually clear the 783 * device. I might try sending a DEVICE-RESET here to speed 784 * up the error recovery except that DEVICE-RESET is kind of 785 * complicated to implement correctly because if I send a 786 * DEVICE-RESET to drive 1 it deselects itself. 787 */ 788 ADBG_WARN(("atapi_fsm_intr: Unsupported intr\n")); 789 break; 790 791 case A_NADA: 792 drv_usecwait(100); 793 break; 794 795 case A_CDB: 796 /* 797 * send out atapi pkt 798 */ 799 atapi_send_cdb(ata_ctlp, ata_pktp); 800 801 /* 802 * start the DMA engine if necessary and change 803 * the state variable to reflect not doing PIO 804 */ 805 if (ata_pktp->ap_pciide_dma) { 806 atapi_start_dma(ata_ctlp, ata_drvp, ata_pktp); 807 ata_drvp->ad_state = S_DMA; 808 } 809 break; 810 811 case A_IN: 812 if (!(ata_pktp->ap_flags & AP_READ)) { 813 /* 814 * maybe this was a spurious interrupt, just 815 * spin for a bit and see if the drive 816 * recovers 817 */ 818 atapi_fsm_error(ata_ctlp, state, event); 819 drv_usecwait(100); 820 break; 821 } 822 /* 823 * read in the data 824 */ 825 if (!ata_pktp->ap_pciide_dma) { 826 atapi_pio_data_in(ata_ctlp, ata_pktp); 827 } 828 break; 829 830 case A_OUT: 831 if (!(ata_pktp->ap_flags & AP_WRITE)) { 832 /* spin for a bit and see if the drive recovers */ 833 atapi_fsm_error(ata_ctlp, state, event); 834 drv_usecwait(100); 835 break; 836 } 837 /* 838 * send out data 839 */ 840 if (!ata_pktp->ap_pciide_dma) { 841 atapi_pio_data_out(ata_ctlp, ata_pktp); 842 } 843 break; 844 845 case A_IDLE: 846 /* 847 * The DRQ bit deasserted before or between the data 848 * transfer phases. 849 */ 850 if (!ata_drvp->ad_bogus_drq) { 851 ata_drvp->ad_bogus_drq = TRUE; 852 atapi_fsm_error(ata_ctlp, state, event); 853 } 854 drv_usecwait(100); 855 break; 856 857 case A_RE: 858 /* 859 * If we get here, a command has completed! 860 * 861 * check status of completed command 862 */ 863 atapi_status(ata_ctlp, ata_pktp, status, 864 (state == S_DMA) ? TRUE : FALSE); 865 866 return (ATA_FSM_RC_FINI); 867 868 case A_REX: 869 /* 870 * some NEC drives don't report the right interrupt 871 * reason code for the status phase 872 */ 873 if (!ata_drvp->ad_nec_bad_status) { 874 ata_drvp->ad_nec_bad_status = TRUE; 875 atapi_fsm_error(ata_ctlp, state, event); 876 drv_usecwait(100); 877 } 878 atapi_status(ata_ctlp, ata_pktp, status, 879 (state == S_DMA) ? TRUE : FALSE); 880 return (ATA_FSM_RC_FINI); 881 882 } 883 return (ATA_FSM_RC_OKAY); 884 } 885