1*507c3241Smlf /* 2*507c3241Smlf * CDDL HEADER START 3*507c3241Smlf * 4*507c3241Smlf * The contents of this file are subject to the terms of the 5*507c3241Smlf * Common Development and Distribution License (the "License"). 6*507c3241Smlf * You may not use this file except in compliance with the License. 7*507c3241Smlf * 8*507c3241Smlf * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*507c3241Smlf * or http://www.opensolaris.org/os/licensing. 10*507c3241Smlf * See the License for the specific language governing permissions 11*507c3241Smlf * and limitations under the License. 12*507c3241Smlf * 13*507c3241Smlf * When distributing Covered Code, include this CDDL HEADER in each 14*507c3241Smlf * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*507c3241Smlf * If applicable, add the following below this CDDL HEADER, with the 16*507c3241Smlf * fields enclosed by brackets "[]" replaced with your own identifying 17*507c3241Smlf * information: Portions Copyright [yyyy] [name of copyright owner] 18*507c3241Smlf * 19*507c3241Smlf * CDDL HEADER END 20*507c3241Smlf */ 21*507c3241Smlf 22*507c3241Smlf /* 23*507c3241Smlf * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24*507c3241Smlf * Use is subject to license terms. 25*507c3241Smlf */ 26*507c3241Smlf 27*507c3241Smlf #ifndef _PCIIDE_H 28*507c3241Smlf #define _PCIIDE_H 29*507c3241Smlf 30*507c3241Smlf #ifdef __cplusplus 31*507c3241Smlf extern "C" { 32*507c3241Smlf #endif 33*507c3241Smlf 34*507c3241Smlf 35*507c3241Smlf /* 36*507c3241Smlf * Bus Mastering devices have a PCI class-code of 0x010180 to 0x0101ff 37*507c3241Smlf */ 38*507c3241Smlf #define PCIIDE_BM_CAP_MASK 0x80 39*507c3241Smlf #define PCIIDE_BM_CLASS ((PCI_CLASS_MASS << 16) | (PCI_MASS_IDE << 8) | 0x80) 40*507c3241Smlf #define PCIIDE_BM_CLASS_MASK 0xffffff80 41*507c3241Smlf 42*507c3241Smlf 43*507c3241Smlf #define PCIIDE_BMICX_REG 0 /* Bus Master IDE Command Register */ 44*507c3241Smlf 45*507c3241Smlf #define PCIIDE_BMICX_SSBM 0x01 /* Start/Stop Bus Master */ 46*507c3241Smlf #define PCIIDE_BMICX_SSBM_E 0x01 /* 1=Start (Enable) */ 47*507c3241Smlf /* 0=Start (Disable) */ 48*507c3241Smlf 49*507c3241Smlf /* 50*507c3241Smlf * NOTE: "read" and "write" are the actions of the DMA 51*507c3241Smlf * engine on the PCI bus. Not the DMA engine's action on the ATA 52*507c3241Smlf * BUS. Therefore for a ATA READ command, program the DMA engine to 53*507c3241Smlf * "write to memory" mode (and vice versa). 54*507c3241Smlf */ 55*507c3241Smlf #define PCIIDE_BMICX_RWCON 0x08 /* Read/Write Control */ 56*507c3241Smlf #define PCIIDE_BMICX_RWCON_WRITE_TO_MEMORY 0x08 /* 1=Write (dev to host) */ 57*507c3241Smlf #define PCIIDE_BMICX_RWCON_READ_FROM_MEMORY 0x00 /* 0=Read (host to dev) */ 58*507c3241Smlf 59*507c3241Smlf /* preserve these bits during updates */ 60*507c3241Smlf #define PCIIDE_BMICX_MASK (~(PCIIDE_BMICX_SSBM | PCIIDE_BMICX_RWCON)) 61*507c3241Smlf 62*507c3241Smlf 63*507c3241Smlf 64*507c3241Smlf #define PCIIDE_BMISX_REG 2 /* Bus Master IDE Status Register */ 65*507c3241Smlf 66*507c3241Smlf #define PCIIDE_BMISX_BMIDEA 0x01 /* Bus Master IDE Active */ 67*507c3241Smlf #define PCIIDE_BMISX_IDERR 0x02 /* IDE DMA Error */ 68*507c3241Smlf #define PCIIDE_BMISX_IDEINTS 0x04 /* IDE Interrupt Status */ 69*507c3241Smlf #define PCIIDE_BMISX_DMA0CAP 0x20 /* Drive 0 DMA Capable */ 70*507c3241Smlf #define PCIIDE_BMISX_DMA1CAP 0x40 /* Drive 1 DMA Capable */ 71*507c3241Smlf #define PCIIDE_BMISX_SIMPLEX 0x80 /* Simplex only */ 72*507c3241Smlf 73*507c3241Smlf /* preserve these bits during updates */ 74*507c3241Smlf #define PCIIDE_BMISX_MASK 0xf8 75*507c3241Smlf 76*507c3241Smlf #define PCIIDE_BMIDTPX_REG 4 /* Bus Master IDE Desc. Table Ptr */ 77*507c3241Smlf #define PCIIDE_BMIDTPX_MASK 0x00000003 /* must be zeros */ 78*507c3241Smlf 79*507c3241Smlf 80*507c3241Smlf typedef struct PhysicalRegionDescriptorTableEntry { 81*507c3241Smlf uint_t p_address; /* physical address */ 82*507c3241Smlf uint_t p_count; /* byte count, EOT in high order bit */ 83*507c3241Smlf } prde_t; 84*507c3241Smlf 85*507c3241Smlf /* 86*507c3241Smlf * Some specs say the p_address must 32-bit aligned, and some claim 87*507c3241Smlf * 16-bit alignment. Use 32-bit alignment just to be safe. 88*507c3241Smlf */ 89*507c3241Smlf #ifdef __not_yet__ 90*507c3241Smlf #define PCIIDE_PRDE_ADDR_MASK ((uint_t)(sizeof (short) -1)) 91*507c3241Smlf #else 92*507c3241Smlf #define PCIIDE_PRDE_ADDR_MASK ((uint_t)(sizeof (int) -1)) 93*507c3241Smlf #endif 94*507c3241Smlf 95*507c3241Smlf #define PCIIDE_PRDE_CNT_MASK ((uint_t)0x0001) /* must be even */ 96*507c3241Smlf #define PCIIDE_PRDE_CNT_MAX ((uint_t)0x10000) /* 0 == 64k */ 97*507c3241Smlf #define PCIIDE_PRDE_EOT ((uint_t)0x80000000) 98*507c3241Smlf 99*507c3241Smlf #ifdef __cplusplus 100*507c3241Smlf } 101*507c3241Smlf #endif 102*507c3241Smlf 103*507c3241Smlf #endif /* _PCIIDE_H */ 104