1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _NB5000_H 28 #define _NB5000_H 29 30 #ifdef __cplusplus 31 extern "C" { 32 #endif 33 34 #include <sys/cpu_module.h> 35 36 #define NB_5000_MAX_MEM_CONTROLLERS 2 37 #define NB_MAX_DIMMS_PER_CHANNEL (nb_chipset == INTEL_NB_5100 ? 3 : \ 38 (nb_chipset == INTEL_NB_7300 ? 8 : 4)) 39 #define NB_MAX_CHANNELS_PER_BRANCH 2 40 #define NB_5100_RANKS_PER_CHANNEL 6 41 #define NB_MEM_BRANCH_SELECT \ 42 (nb_chipset == INTEL_NB_5400 || nb_chipset == INTEL_NB_5100 ? 2 : 3) 43 #define NB_MAX_MEM_BRANCH_SELECT 3 44 #define NB_MEM_RANK_SELECT (nb_chipset == INTEL_NB_7300 ? 7 : 5) 45 #define NB_MAX_MEM_RANK_SELECT 7 46 #define NB_RANKS_IN_SELECT 4 47 #define NB_PCI_DEV 10 48 49 #define NB_PCI_NFUNC 4 50 51 #define DOCMD_PEX_MASK 0x00 52 #define DOCMD_5400_PEX_MASK 0x000 53 #define DOCMD_PEX 0xf0 54 #define DOCMD_5400_PEX 0xff0 55 56 #define SPD_BUSY 0x1000 57 #define SPD_BUS_ERROR 0x2000 58 #define SPD_READ_DATA_VALID 0x8000 59 #define SPD_EEPROM_WRITE 0xa8000000 60 #define SPD_ADDR(slave, addr) ((((slave) & 7) << 24) | (((addr) & 0xff) << 16)) 61 62 #define MC_MIRROR 0x10000 63 #define MC_PATROL_SCRUB 0x80 64 #define MC_DEMAND_SCRUB 0x40 65 66 #define MCA_SCHDIMM 0x4000 67 68 #define TLOW_MAX 0x100000000ULL 69 70 #define MTR_PRESENT(mtr) \ 71 ((mtr) & (nb_chipset == INTEL_NB_5400 || nb_chipset == INTEL_NB_5100 ? \ 72 0x0400 : 0x0100)) 73 #define MTR_ETHROTTLE(mtr) \ 74 ((mtr) & (nb_chipset == INTEL_NB_5400 || nb_chipset == INTEL_NB_5100 ? \ 75 ? 0x0200 : 0x0080)) 76 #define MTR_WIDTH(mtr) \ 77 ((mtr) & (nb_chipset == INTEL_NB_5400 || nb_chipset == INTEL_NB_5100 ? \ 78 0x0100 : 0x0040) ? 8 : 4) 79 #define MTR_NUMBANK(mtr) \ 80 ((mtr) & (nb_chipset == INTEL_NB_5400 || nb_chipset == INTEL_NB_5100 ? \ 81 0x0040 : 0x0020) ? 8 : 4) 82 #define MTR_NUMRANK(mtr) (nb_chipset == INTEL_NB_5100 ? 1 : \ 83 (((mtr) & (nb_chipset == INTEL_NB_5400 ? 0x0020 : 0x0010)) ? 2 : 1)) 84 #define MTR_NUMROW(mtr) ((((mtr) >> 2) & 3) + 13) 85 #define MTR_NUMCOL(mtr) (((mtr) & 3) + 10) 86 87 #define MTR_DIMMSIZE(mtr) ((1ULL << (MTR_NUMCOL(mtr) + MTR_NUMROW(mtr))) \ 88 * MTR_NUMRANK(mtr) * MTR_NUMBANK(mtr) * MTR_WIDTH(mtr)) 89 #define DIMMSIZE(nrow, ncol, nrank, nbank, width) \ 90 ((1ULL << ((ncol) + (nrow))) * (nrank) * (nbank) * (width)) 91 #define MTR_DDR2_DIMMSIZE(mtr, nrank) \ 92 ((1ULL << (MTR_NUMCOL(mtr) + MTR_NUMROW(mtr))) \ 93 * (nrank) * MTR_NUMBANK(mtr) * MTR_WIDTH(mtr)) 94 95 /* FERR_GLOBAL and NERR_GLOBAL */ 96 #define GE_FERR_FSB3_FATAL 0x800000000ULL /* FSB3 Fatal Error */ 97 #define GE_FERR_FSB2_FATAL 0x400000000ULL /* FSB2 Fatal Error */ 98 #define GE_FERR_FSB3_NF 0x200000000ULL /* FSB3 Non-Fatal Error */ 99 #define GE_FERR_FSB2_NF 0x100000000ULL /* FSB2 Non-Fatal Error */ 100 101 #define GE_INT_FATAL 0x80000000 /* North Bridge Internal Error */ 102 #define GE_DMA_FATAL 0x40000000 /* DMA engine Fatal Error */ 103 #define GE_FSB1_FATAL 0x20000000 /* FSB1 Fatal Error */ 104 #define GE_FSB0_FATAL 0x10000000 /* FSB0 Fatal Error */ 105 #define GE_FERR_FBD_FATAL 0x08000000 /* FBD channel Fatal Error */ 106 #define GE_FERR_FBD3_FATAL 0x08000000 /* FBD3 channel Fatal Error */ 107 #define GE_FERR_FBD2_FATAL 0x04000000 /* FBD2 channel Fatal Error */ 108 #define GE_FERR_FBD1_FATAL 0x02000000 /* FBD1 channel Fatal Error */ 109 #define GE_FERR_FBD0_FATAL 0x01000000 /* FBD0 channel Fatal Error */ 110 #define GE_FERR_THERMAL_FATAL 0x04000000 /* Thermal Fatal Error */ 111 #define GE_PCIEX9_FATAL 0x02000000 /* PCI Express device 9 Fatal Error */ 112 #define GE_PCIEX8_FATAL 0x01000000 /* PCI Express device 8 Fatal Error */ 113 #define GE_PCIEX7_FATAL 0x00800000 /* PCI Express device 7 Fatal Error */ 114 #define GE_PCIEX6_FATAL 0x00400000 /* PCI Express device 6 Fatal Error */ 115 #define GE_PCIEX5_FATAL 0x00200000 /* PCI Express device 5 Fatal Error */ 116 #define GE_PCIEX4_FATAL 0x00100000 /* PCI Express device 4 Fatal Error */ 117 #define GE_PCIEX3_FATAL 0x00080000 /* PCI Express device 3 Fatal Error */ 118 #define GE_PCIEX2_FATAL 0x00040000 /* PCI Express device 2 Fatal Error */ 119 #define GE_PCIEX1_FATAL 0x00020000 /* PCI Express device 1 Fatal Error */ 120 #define GE_ESI_FATAL 0x00010000 /* ESI Fatal Error */ 121 #define GE_INT_NF 0x00008000 /* North Bridge Internal Error */ 122 #define GE_DMA_NF 0x00004000 /* DMA engine Non-Fatal Error */ 123 #define GE_FSB1_NF 0x00002000 /* FSB1 Non-Fatal Error */ 124 #define GE_FSB0_NF 0x00001000 /* FSB0 Non-Fatal Error */ 125 #define GE_FERR_FBD3_NF 0x00000800 /* FBD channel 3 Non-Fatal Error */ 126 #define GE_FERR_FBD2_NF 0x00000400 /* FBD channel 2 Non-Fatal Error */ 127 #define GE_FERR_FBD1_NF 0x00000200 /* FBD channel 1 Non-Fatal Error */ 128 #define GE_FERR_FBD0_NF 0x00000100 /* FBD channel 0 Non-Fatal Error */ 129 #define GE_FERR_FBD_NF 0x00000800 /* FBD channel Non-Fatal Error */ 130 #define GE_FERR_MEM1_NF 0x00000200 /* DDR channel 1 Non-Fatal Error */ 131 #define GE_FERR_MEM0_NF 0x00000100 /* DDR channel 0 Non-Fatal Error */ 132 #define GE_FERR_THERMAL_NF 0x00000400 /* Thermal Non-Fatal Error */ 133 #define GE_PCIEX9_NF 0x00000200 /* PCI Express dev 9 Non-Fatal Error */ 134 #define GE_PCIEX8_NF 0x00000100 /* PCI Express dev 8 Non-Fatal Error */ 135 #define GE_PCIEX7_NF 0x00000080 /* PCI Express dev 7 Non-Fatal Error */ 136 #define GE_PCIEX6_NF 0x00000040 /* PCI Express dev 6 Non-Fatal Error */ 137 #define GE_PCIEX5_NF 0x00000020 /* PCI Express dev 5 Non-Fatal Error */ 138 #define GE_PCIEX4_NF 0x00000010 /* PCI Express dev 4 Non-Fatal Error */ 139 #define GE_PCIEX3_NF 0x00000008 /* PCI Express dev 3 Non-Fatal Error */ 140 #define GE_PCIEX2_NF 0x00000004 /* PCI Express dev 2 Non-Fatal Error */ 141 #define GE_PCIEX1_NF 0x00000002 /* PCI Express dev 1 Non-Fatal Error */ 142 #define GE_ESI_NF 0x00000001 /* ESI Non-Fatal Error */ 143 144 #define GE_NERR_FSB2_FATAL 0x08000000 /* FSB2 Fatal Error */ 145 #define GE_NERR_FSB3_FATAL 0x04000000 /* FSB3 Fatal Error */ 146 #define GE_NERR_FBD_FATAL (nb_chipset == INTEL_NB_5100 ? 0 : 0x01000000) 147 /* FBD channel Fatal Error */ 148 #define GE_NERR_FSB2_NF 0x00000800 /* FSB2 Non-Fatal Error */ 149 #define GE_NERR_FSB3_NF 0x00000400 /* FSB3 Non-Fatal Error */ 150 #define GE_NERR_FBD_NF (nb_chipset == INTEL_NB_5100 ? 0 : 0x00000100) 151 /* FBD channel Non-Fatal Error */ 152 #define GE_NERR_MEM_NF (nb_chipset == INTEL_NB_5100 ? 0x00000100 : 0) 153 /* DDR channel0,1 Non-Fatal Error */ 154 #define ERR_FAT_FSB_F9 0x20 /* F9Msk FSB Protocol */ 155 #define ERR_FAT_FSB_F2 0x08 /* F2Msk Unsupported Bus Transaction */ 156 #define ERR_FAT_FSB_F1 0x01 /* F1Msk Request/Address Parity */ 157 158 #define ERR_NF_FSB_F7 0x04 /* F7Msk Detected MCERR */ 159 #define ERR_NF_FSB_F8 0x02 /* F8Msk B-INIT */ 160 #define ERR_NF_FSB_F6 0x01 /* F6Msk Data Parity */ 161 162 #define EMASK_FSB_F1 0x0001 /* F1Msk Request/Address Parity */ 163 #define EMASK_FSB_F2 0x0002 /* F2Msk Unsupported Bus Transaction */ 164 #define EMASK_FSB_F6 0x0020 /* F6Msk Data Parity */ 165 #define EMASK_FSB_F7 0x0040 /* F7Msk Detected MCERR */ 166 #define EMASK_FSB_F8 0x0080 /* F8Msk B-INIT */ 167 #define EMASK_FSB_F9 0x0100 /* F9Msk FSB Protocol */ 168 169 #define EMASK_FSB_FATAL (EMASK_FSB_F1 | EMASK_FSB_F2 | EMASK_FSB_F9) 170 #define EMASK_FSB_NF (EMASK_FSB_F6 | EMASK_FSB_F7 | EMASK_FSB_F8) 171 172 #define ERR_FBD_CH_SHIFT 28 /* channel index in fat_fbd and nf_fbd */ 173 174 #define ERR_FAT_FBD_M23 0x00400000 /* M23Err Non-Redundant Fast Reset */ 175 /* Timeout */ 176 #define ERR_FAT_FBD_M3 0x00000004 /* M3Err >Tmid thermal event with */ 177 /* intelligent throttling disabled */ 178 #define ERR_FAT_FBD_M2 0x00000002 /* M2Err memory or FBD configuration */ 179 /* CRC read error */ 180 #define ERR_FAT_FBD_M1 0x00000001 /* M1Err memory write error on */ 181 /* non-redundant retry or FBD */ 182 /* configuration write error on retry */ 183 #define ERR_FAT_FBD_MASK 0x007fffff 184 185 #define ERR_NF_FBD_M29 0x02000000 /* M29Err DIMM-Isolation Completed */ 186 #define ERR_NF_FBD_M28 0x01000000 /* M28Err DIMM-Spare Copy Completed */ 187 #define ERR_NF_FBD_M27 0x00800000 /* M27Err DIMM-Spare Copy Initiated */ 188 #define ERR_NF_FBD_M26 0x00400000 /* M26Err Redundant Fast Reset */ 189 /* Timeout */ 190 #define ERR_NF_FBD_M25 0x00200000 /* M25Err Memory write error on */ 191 #define ERR_NF_FBD_M24 0x00100000 /* M24Err refresh error */ 192 /* redundant retry */ 193 #define ERR_NF_FBD_M22 0x00040000 /* M22Err SPD protocol */ 194 #define ERR_NF_FBD_M21 0x00020000 /* M21Err FBD Northbound parity on */ 195 /* FBD sync status */ 196 #define ERR_NF_FBD_M20 0x00010000 /* M20Err Correctable patrol data ECC */ 197 #define ERR_NF_FBD_M19 0x00008000 /* M19Err Correctasble resilver or */ 198 /* spare-copy data ECC */ 199 #define ERR_NF_FBD_M18 0x00004000 /* M18Err Correctable Mirrored demand */ 200 /* data ECC */ 201 #define ERR_NF_FBD_M17 0x00002000 /* M17Err Correctable Non-mirrored */ 202 /* demand data ECC */ 203 #define ERR_NF_FBD_M16 0x00001000 /* M16Err channel failed over */ 204 #define ERR_NF_FBD_M15 0x00000800 /* M15Err Memory or FBD configuration */ 205 /* CRC read error */ 206 #define ERR_NF_FBD_M14 0x00000400 /* M14Err FBD configuration write */ 207 /* error on first attempt */ 208 #define ERR_NF_FBD_M13 0x00000200 /* M13Err Memory write error on first */ 209 /* attempt */ 210 #define ERR_NF_FBD_M12 0x00000100 /* M12Err Non-Aliased uncorrectable */ 211 /* patrol data ECC */ 212 #define ERR_NF_FBD_M11 0x00000080 /* M11Err Non-Aliased uncorrectable */ 213 /* resilver or spare copy data ECC */ 214 #define ERR_NF_FBD_M10 0x00000040 /* M10Err Non-Aliased uncorrectable */ 215 /* mirrored demand data ECC */ 216 #define ERR_NF_FBD_M9 0x00000020 /* M9Err Non-Aliased uncorrectable */ 217 /* non-mirrored demand data ECC */ 218 #define ERR_NF_FBD_M8 0x00000010 /* M8Err Aliased uncorrectable */ 219 /* patrol data ECC */ 220 #define ERR_NF_FBD_M7 0x00000008 /* M7Err Aliased uncorrectable */ 221 /* resilver or spare copy data ECC */ 222 #define ERR_NF_FBD_M6 0x00000004 /* M6Err Aliased uncorrectable */ 223 /* mirrored demand data ECC */ 224 #define ERR_NF_FBD_M5 0x00000002 /* M5Err Aliased uncorrectable */ 225 /* non-mirrored demand data ECC */ 226 #define ERR_NF_FBD_M4 0x00000001 /* M4Err uncorrectable data ECC on */ 227 /* replay */ 228 229 #define ERR_NF_FBD_MASK 0x01ffffff 230 #define ERR_NF_FBD_ECC_UE (ERR_NF_FBD_M12|ERR_NF_FBD_M11|ERR_NF_FBD_M10| \ 231 ERR_NF_FBD_M9|ERR_NF_FBD_M8|ERR_NF_FBD_M7|ERR_NF_FBD_M6|ERR_NF_FBD_M5| \ 232 ERR_NF_FBD_M4) 233 #define ERR_NF_FBD_MA (ERR_NF_FBD_M14) 234 #define ERR_NF_FBD_ECC_CE (ERR_NF_FBD_M20|ERR_NF_FBD_M19|ERR_NF_FBD_M18| \ 235 ERR_NF_FBD_M17|ERR_NF_FBD_M15|ERR_NF_FBD_M21) 236 #define ERR_NF_FBD_SPARE (ERR_NF_FBD_M28|ERR_NF_FBD_M27) 237 238 #define EMASK_FBD_M29 0x10000000 /* M29Err DIMM-Isolation Completed */ 239 #define EMASK_FBD_M28 0x08000000 /* M28Err DIMM-Spare Copy Completed */ 240 #define EMASK_FBD_M27 0x04000000 /* M27Err DIMM-Spare Copy Initiated */ 241 #define EMASK_FBD_M26 0x02000000 /* M26Err Redundant Fast Reset */ 242 /* Timeout */ 243 #define EMASK_FBD_M25 0x01000000 /* M25Err Memory write error on */ 244 /* redundant retry */ 245 #define EMASK_FBD_M24 0x00800000 /* M24Err refresh error */ 246 #define EMASK_FBD_M23 0x00400000 /* M23Err Non-Redundant Fast Reset */ 247 /* Timeout */ 248 #define EMASK_FBD_M22 0x00200000 /* M22Err SPD protocol */ 249 #define EMASK_FBD_M21 0x00100000 /* M21Err FBD Northbound parity on */ 250 /* FBD sync status */ 251 #define EMASK_FBD_M20 0x00080000 /* M20Err Correctable patrol data ECC */ 252 #define EMASK_FBD_M19 0x00040000 /* M19Err Correctasble resilver or */ 253 /* spare-copy data ECC */ 254 #define EMASK_FBD_M18 0x00020000 /* M18Err Correctable Mirrored demand */ 255 /* data ECC */ 256 #define EMASK_FBD_M17 0x00010000 /* M17Err Correctable Non-mirrored */ 257 /* demand data ECC */ 258 #define EMASK_FBD_M16 0x00008000 /* M16Err channel failed over */ 259 #define EMASK_FBD_M15 0x00004000 /* M15Err Memory or FBD configuration */ 260 /* CRC read error */ 261 #define EMASK_FBD_M14 0x00002000 /* M14Err FBD configuration write */ 262 /* error on first attempt */ 263 #define EMASK_FBD_M13 0x00001000 /* M13Err Memory write error on first */ 264 /* attempt */ 265 #define EMASK_FBD_M12 0x00000800 /* M12Err Non-Aliased uncorrectable */ 266 /* patrol data ECC */ 267 #define EMASK_FBD_M11 0x00000400 /* M11Err Non-Aliased uncorrectable */ 268 /* resilver or spare copy data ECC */ 269 #define EMASK_FBD_M10 0x00000200 /* M10Err Non-Aliased uncorrectable */ 270 /* mirrored demand data ECC */ 271 #define EMASK_FBD_M9 0x00000100 /* M9Err Non-Aliased uncorrectable */ 272 /* non-mirrored demand data ECC */ 273 #define EMASK_FBD_M8 0x00000080 /* M8Err Aliased uncorrectable */ 274 /* patrol data ECC */ 275 #define EMASK_FBD_M7 0x00000040 /* M7Err Aliased uncorrectable */ 276 /* resilver or spare copy data ECC */ 277 #define EMASK_FBD_M6 0x00000020 /* M6Err Aliased uncorrectable */ 278 /* mirrored demand data ECC */ 279 #define EMASK_FBD_M5 0x00000010 /* M5Err Aliased uncorrectable */ 280 /* non-mirrored demand data ECC */ 281 #define EMASK_FBD_M4 0x00000008 /* M4Err uncorrectable data ECC on */ 282 /* replay */ 283 #define EMASK_FBD_M3 0x00000004 /* M3Err >Tmid thermal event with */ 284 /* intelligent throttling disabled */ 285 #define EMASK_FBD_M2 0x00000002 /* M2Err memory or FBD configuration */ 286 /* CRC read error */ 287 #define EMASK_FBD_M1 0x00000001 /* M1Err memory write error on */ 288 /* non-redundant retry or FBD */ 289 /* configuration write error on retry */ 290 /* MCH 7300 errata 34 (reserved mask bits) */ 291 #define EMASK_5000_FBD_RES (EMASK_FBD_M24|EMASK_FBD_M16) 292 #define EMASK_FBD_RES (nb_chipset == INTEL_NB_5400 ? 0 : EMASK_5000_FBD_RES) 293 294 #define EMASK_FBD_FATAL (EMASK_FBD_M23|EMASK_FBD_M3|EMASK_FBD_M2|EMASK_FBD_M1) 295 #define EMASK_FBD_NF (EMASK_FBD_M28|EMASK_FBD_M27|EMASK_FBD_M26|EMASK_FBD_M25| \ 296 EMASK_FBD_M22|EMASK_FBD_M21|EMASK_FBD_M20|EMASK_FBD_M19|EMASK_FBD_M18| \ 297 EMASK_FBD_M17|EMASK_FBD_M15|EMASK_FBD_M14|EMASK_FBD_M13|EMASK_FBD_M12| \ 298 EMASK_FBD_M11|EMASK_FBD_M10|EMASK_FBD_M9|EMASK_FBD_M8|EMASK_FBD_M7| \ 299 EMASK_FBD_M6|EMASK_FBD_M5|EMASK_FBD_M4) 300 #define EMASK_5400_FBD_FATAL (EMASK_FBD_M23|EMASK_FBD_M2|EMASK_FBD_M1) 301 #define EMASK_5400_FBD_NF (EMASK_FBD_M29|EMASK_FBD_M28|EMASK_FBD_M27| \ 302 EMASK_FBD_M26|EMASK_FBD_M25|EMASK_FBD_M24|EMASK_FBD_M22|EMASK_FBD_M21| \ 303 EMASK_FBD_M20|EMASK_FBD_M19|EMASK_FBD_M18|EMASK_FBD_M17|EMASK_FBD_M16| \ 304 EMASK_FBD_M15|EMASK_FBD_M14|EMASK_FBD_M13|EMASK_FBD_M12| \ 305 EMASK_FBD_M11|EMASK_FBD_M10|EMASK_FBD_M9|EMASK_FBD_M8|EMASK_FBD_M7| \ 306 EMASK_FBD_M6|EMASK_FBD_M5|EMASK_FBD_M4) 307 308 /* FERR_NF_MEM: MC First non-fatal errors */ 309 #define ERR_MEM_CH_SHIFT 28 /* channel index in nf_mem */ 310 311 #define ERR_NF_MEM_M21 0x00200000 /* M21Err Spare Copy Completed */ 312 #define ERR_NF_MEM_M20 0x00100000 /* M20Err Spare Copy Initiated */ 313 #define ERR_NF_MEM_M18 0x00040000 /* M18Err SPD protocal */ 314 #define ERR_NF_MEM_M16 0x00010000 /* M16Err Correctable Patrol Data ECC */ 315 #define ERR_NF_MEM_M15 0x00008000 /* M15Err Correctable Spare-copy ECC */ 316 #define ERR_NF_MEM_M14 0x00004000 /* M14Err Correctable demand data ECC */ 317 #define ERR_NF_MEM_M12 0x00001000 /* M12Err non-aliased ue Patrol ECC */ 318 #define ERR_NF_MEM_M11 0x00000800 /* M11Err non-aliased ue Spare-copy */ 319 #define ERR_NF_MEM_M10 0x00000400 /* M10Err non-aliased ue demand data */ 320 #define ERR_NF_MEM_M6 0x00000040 /* M6Err aliased ue Patrol Data ECC */ 321 #define ERR_NF_MEM_M5 0x00000020 /* M5Err aliased ue Spare-copy ECC */ 322 #define ERR_NF_MEM_M4 0x00000010 /* M4Err aliased ue demand data ECC */ 323 #define ERR_NF_MEM_M1 0x00000002 /* M1Err ue data ECC on replay */ 324 325 #define ERR_NF_MEM_MASK 0x0003fffff 326 #define ERR_NF_MEM_ECC_UE (ERR_NF_MEM_M12|ERR_NF_MEM_M11|ERR_NF_MEM_M10| \ 327 ERR_NF_MEM_M6|ERR_NF_MEM_M5|ERR_NF_MEM_M4|ERR_NF_MEM_M1) 328 #define ERR_NF_MEM_ECC_CE (ERR_NF_MEM_M16|ERR_NF_MEM_M15|ERR_NF_MEM_M14) 329 #define ERR_NF_MEM_SPARE (ERR_NF_MEM_M21|ERR_NF_MEM_M20) 330 331 #define EMASK_MEM_M21 ERR_NF_MEM_M21 332 #define EMASK_MEM_M20 ERR_NF_MEM_M20 333 #define EMASK_MEM_M18 ERR_NF_MEM_M18 334 #define EMASK_MEM_M16 ERR_NF_MEM_M16 335 #define EMASK_MEM_M15 ERR_NF_MEM_M15 336 #define EMASK_MEM_M14 ERR_NF_MEM_M14 337 #define EMASK_MEM_M12 ERR_NF_MEM_M12 338 #define EMASK_MEM_M11 ERR_NF_MEM_M11 339 #define EMASK_MEM_M10 ERR_NF_MEM_M10 340 #define EMASK_MEM_M6 ERR_NF_MEM_M6 341 #define EMASK_MEM_M5 ERR_NF_MEM_M5 342 #define EMASK_MEM_M4 ERR_NF_MEM_M4 343 #define EMASK_MEM_M1 ERR_NF_MEM_M1 344 345 #define EMASK_MEM_NF (EMASK_FBD_M21|EMASK_FBD_M20|EMASK_FBD_M18|EMASK_FBD_M16| \ 346 EMASK_FBD_M15|EMASK_FBD_M14|EMASK_FBD_M12|EMASK_FBD_M11|EMASK_FBD_M10| \ 347 EMASK_MEM_M6|EMASK_MEM_M5|EMASK_MEM_M4|EMASK_MEM_M1) 348 349 #define ERR_INT_ALL (nb_chipset == INTEL_NB_5400 ? 0xffffffff : 0xff) 350 351 #define ERR_FAT_INT_B14 0x0400 /* B14Msk SF Scrub DBE */ 352 #define ERR_FAT_INT_B12 0x0100 /* B12Msk Parity Protected register */ 353 #define ERR_FAT_INT_B25 0x0080 /* B25Msk illegal HISMM/TSEG access */ 354 #define ERR_FAT_INT_B23 0x0040 /* B23Msk Vt Unaffiliated port error */ 355 #define ERR_FAT_INT_B21 0x0020 /* B21Msk illegal way */ 356 #define ERR_FAT_INT_B7 0x0010 /* B7Msk Multiple ECC error in any of */ 357 /* the ways during SF lookup */ 358 #define ERR_FAT_INT_B4 0x08 /* B4Msk Virtual pin port error */ 359 #define ERR_FAT_INT_B3 0x04 /* B3Msk Coherency violation error for EWB */ 360 #define ERR_FAT_INT_B2 0x02 /* B2Msk Multi-tag hit SF */ 361 #define ERR_FAT_INT_B1 0x01 /* B1Msk DM parity error */ 362 363 #define ERR_NF_INT_B27 0x4000 /* B27Msk Request received when in S1 */ 364 #define ERR_NF_INT_B24 0x2000 /* B24Msk DFXERR */ 365 #define ERR_NF_INT_B19 0x1000 /* B19Msk scrub SBE (SF) */ 366 #define ERR_NF_INT_B18 0x0800 /* B18Msk perfmon task completion */ 367 #define ERR_NF_INT_B17 0x0400 /* B17Msk JTAG/TAP error status */ 368 #define ERR_NF_INT_B16 0x0200 /* B16Msk SMBus error status */ 369 #define ERR_NF_INT_B22 0x0080 /* B22Msk Victim ROM parity */ 370 #define ERR_NF_INT_B20 0x0040 /* B20Msk Configuration write abort */ 371 #define ERR_NF_INT_B11 0x0020 /* B11Msk Victim Ram parity error */ 372 #define ERR_NF_INT_B10 0x0010 /* B10Msk DM Parity */ 373 #define ERR_NF_INT_B9 0x0008 /* B9Msk illeagl access */ 374 #define ERR_NF_INT_B8 0x0004 /* B8Msk SF Coherency Error for BIL */ 375 #define ERR_NF_INT_B6 0x0002 /* B6Msk Single ECC error on SF lookup */ 376 #define ERR_NF_INT_B5 0x0001 /* B5Msk Address Map error */ 377 378 #define NERR_NF_5400_INT_B26 0x0004 /* B26Msk Illeagl Access to */ 379 /* non-coherent address space */ 380 381 #define EMASK_INT_RES 0x02000000 /* Do not change */ 382 #define EMASK_INT_B25 0x01000000 /* B25Msk illegal HISMM/TSEG access */ 383 #define EMASK_INT_B23 0x00400000 /* B23Msk Vt Unaffiliated port error */ 384 #define EMASK_INT_B22 0x00200000 /* B22Msk Victim ROM parity */ 385 #define EMASK_INT_B21 0x00100000 /* B21Msk illegal way */ 386 #define EMASK_INT_B20 0x00080000 /* B20Msk Configuration write abort */ 387 #define EMASK_INT_B19 0x00040000 /* B19Msk Scrub SBE */ 388 #define EMASK_INT_B14 0x00002000 /* B14Msk Scrub DBE */ 389 #define EMASK_INT_B12 0x00000800 /* B12Msk Parity Protected */ 390 #define EMASK_INT_B11 0x00000400 /* B11Msk Victim Ram parity error */ 391 #define EMASK_INT_B10 0x00000200 /* B10Msk DM Parity */ 392 #define EMASK_INT_B9 0x00000100 /* B9Msk Illegal Accesss */ 393 394 #define EMASK_INT_B8 0x80 /* B8Msk SF Coherency Error for BIL */ 395 #define EMASK_INT_B7 0x40 /* B7Msk Multiple ECC error in any of */ 396 /* the ways during SF lookup */ 397 #define EMASK_INT_B6 0x20 /* B6Msk Single ECC error on SF lookup */ 398 #define EMASK_INT_B5 0x10 /* B5Msk Address Map error */ 399 #define EMASK_INT_B4 0x08 /* B4Msk Virtual pin port error */ 400 #define EMASK_INT_B3 0x04 /* B3Msk Coherency violation error for EWB */ 401 #define EMASK_INT_B2 0x02 /* B2Msk Multi-tag hit SF */ 402 #define EMASK_INT_B1 0x01 /* B1Msk DM parity error */ 403 404 /* MCH 5000 errata 2 */ 405 #define EMASK_INT_5000 EMASK_INT_B1 406 /* MCH 7300 errata 17 & 20 */ 407 #define EMASK_INT_7300 (EMASK_INT_B3|EMASK_INT_B1) 408 /* MCH 7300 errata 17,20 & 21 */ 409 #define EMASK_INT_7300_STEP_0 (EMASK_INT_B7|EMASK_INT_B3|EMASK_INT_B1) 410 #define EMASK_INT_5400 0 411 412 #define EMASK_INT_FATAL (EMASK_INT_B7|EMASK_INT_B4|EMASK_INT_B3|EMASK_INT_B2| \ 413 EMASK_INT_B1) 414 #define EMASK_INT_NF (EMASK_INT_B8|EMASK_INT_B6|EMASK_INT_B5) 415 #define GE_FBD_FATAL ((nb_chipset == INTEL_NB_5400) ? GE_FERR_FBD_FATAL : \ 416 (nb_chipset == INTEL_NB_5100) ? 0 : \ 417 (GE_FERR_FBD0_FATAL|GE_FERR_FBD1_FATAL|GE_FERR_FBD2_FATAL| \ 418 GE_FERR_FBD3_FATAL)) 419 #define GE_FBD_NF ((nb_chipset == INTEL_NB_5400) ? GE_FERR_FBD_NF : \ 420 (nb_chipset == INTEL_NB_5100) ? 0 : \ 421 (GE_FERR_FBD0_NF|GE_FERR_FBD1_NF|GE_FERR_FBD2_NF|GE_FERR_FBD3_NF)) 422 #define GE_MEM_NF ((nb_chipset == INTEL_NB_5100) ? \ 423 (GE_FERR_MEM0_NF|GE_FERR_MEM1_NF) : 0) 424 425 #define EMASK_UNCOR_PEX_IO18 0x00200000 /* ESI Reset timeout */ 426 #define EMASK_UNCOR_PEX_IO2 0x00100000 /* Received an unsupported */ 427 /* request */ 428 #define EMASK_UNCOR_PEX_IO9 0x00040000 /* Malformed TLP Status */ 429 #define EMASK_UNCOR_PEX_IO10 0x00020000 /* Received buffer overflow */ 430 #define EMASK_UNCOR_PEX_IO8 0x00010000 /* unexpected completion */ 431 #define EMASK_UNCOR_PEX_IO7 0x00008000 /* completion abort */ 432 #define EMASK_UNCOR_PEX_IO6 0x00004000 /* completion timeout */ 433 #define EMASK_UNCOR_PEX_IO5 0x00002000 /* flow control protocol */ 434 #define EMASK_UNCOR_PEX_IO4 0x00001000 /* poisoned TLP */ 435 #define EMASK_UNCOR_PEX_IO19 0x00000020 /* surprise link down */ 436 #define EMASK_UNCOR_PEX_IO0 0x00000010 /* data link protocol */ 437 #define EMASK_UNCOR_PEX_IO3 0x00000001 /* training error */ 438 439 #define EMASK_COR_PEX_IO20 0x00002000 /* Advisory Non Fatal */ 440 #define EMASK_COR_PEX_IO16 0x00001000 /* replay timer timeout */ 441 #define EMASK_COR_PEX_IO15 0x00000100 /* replay num pollover */ 442 #define EMASK_COR_PEX_IO14 0x00000080 /* bad DLLP */ 443 #define EMASK_COR_PEX_IO13 0x00000040 /* bad TLP */ 444 #define EMASK_COR_PEX_IO12 0x00000001 /* receiver error mask */ 445 446 #define EMASK_RP_PEX_IO1 0x00000004 /* fatal message detect */ 447 #define EMASK_RP_PEX_IO11 0x00000002 /* uncorrectable message */ 448 #define EMASK_RP_PEX_IO17 0x00000001 /* correctable message */ 449 450 #define EMASK_UNIT_PEX_IO33 0x00002000 /* Link autonomous BW change */ 451 #define EMASK_UNIT_PEX_IO32 0x00001000 /* Received CA Posted Req */ 452 #define EMASK_UNIT_PEX_IO31 0x00000800 /* Received UR Posted Req */ 453 #define EMASK_UNIT_PEX_IO30 0x00000400 /* VT-d internal HW */ 454 #define EMASK_UNIT_PEX_IO29 0x00000200 /* MSI address */ 455 #define EMASK_UNIT_PEX_IO28 0x00000100 /* Link BW change */ 456 #define EMASK_UNIT_PEX_IO27 0x00000080 /* stop & scream */ 457 #define EMASK_UNIT_PEX_IO26 0x00000040 /* Received CA response */ 458 #define EMASK_UNIT_PEX_IO25 0x00000020 /* Received UR response */ 459 #define EMASK_UNIT_PEX_IO24 0x00000010 /* Outbound poisoned data */ 460 #define EMASK_UNIT_PEX_IO23 0x00000008 /* VTd fault */ 461 #define EMASK_UNIT_PEX_IO22 0x00000004 /* internal header/ctl parity */ 462 #define EMASK_UNIT_PEX_IO18 0x00000002 /* ESI reset timeout */ 463 #define EMASK_UNIT_PEX_VPP 0x00000001 /* correctable message detect */ 464 465 #define PEX_5400_FAT_IO32 0x00800000 /* Received CA Posted Request */ 466 #define PEX_5400_FAT_IO31 0x00400000 /* Received UR Posted Request */ 467 #define PEX_5400_FAT_IO30 0x00200000 /* VT-d Internal HW */ 468 #define PEX_5400_FAT_IO29 0x00100000 /* MSI Address */ 469 #define PEX_5400_FAT_IO27 0x00040000 /* Stop & Scream */ 470 #define PEX_5400_FAT_IO26 0x00020000 /* Received CA Response */ 471 #define PEX_5400_FAT_IO25 0x00010000 /* Received UR Response */ 472 #define PEX_5400_FAT_IO24 0x00008000 /* Outbound poisoned TLP */ 473 #define PEX_5400_FAT_IO23 0x00004000 /* VT-d Fault */ 474 #define PEX_5400_FAT_IO22 0x00002000 /* Internal Header/Control */ 475 /* Parity */ 476 #define PEX_5400_FAT_IO18 0x00001000 /* ESI reset timeout */ 477 #define PEX_5400_FAT_IO1 0x00000400 /* received fatal error msg */ 478 #define PEX_5400_FAT_IO2 0x00000200 /* received unsupported req */ 479 #define PEX_5400_FAT_IO9 0x00000100 /* malformed TLP */ 480 #define PEX_5400_FAT_IO10 0x00000080 /* receiver buffer overflow */ 481 #define PEX_5400_FAT_IO8 0x00000040 /* unexpected completion */ 482 #define PEX_5400_FAT_IO7 0x00000020 /* completer abort */ 483 #define PEX_5400_FAT_IO6 0x00000010 /* completion timeout */ 484 #define PEX_5400_FAT_IO5 0x00000008 /* flow control protocol */ 485 #define PEX_5400_FAT_IO4 0x00000004 /* poisoned TLP */ 486 #define PEX_5400_FAT_IO19 0x00000002 /* surprise link down */ 487 #define PEX_5400_FAT_IO0 0x00000001 /* data link layer protocol */ 488 #define PEX_FAT_IO19 0x00001000 /* surprise link down */ 489 #define PEX_FAT_IO18 0x00000800 /* ESI reset timeout */ 490 #define PEX_FAT_IO9 0x00000400 /* malformed TLP */ 491 #define PEX_FAT_IO10 0x00000200 /* receiver buffer overflow */ 492 #define PEX_FAT_IO8 0x00000100 /* unexpected completion */ 493 #define PEX_FAT_IO7 0x00000080 /* completer abort */ 494 #define PEX_FAT_IO6 0x00000040 /* completion timeout */ 495 #define PEX_FAT_IO5 0x00000020 /* flow control protocol */ 496 #define PEX_FAT_IO4 0x00000010 /* poisoned TLP */ 497 #define PEX_FAT_IO3 0x00000008 /* training error */ 498 #define PEX_FAT_IO2 0x00000004 /* received unsupported req */ 499 #define PEX_FAT_IO1 0x00000002 /* received fatal error message */ 500 #define PEX_FAT_IO0 0x00000001 /* data link layer protocol */ 501 502 #define PEX_5400_NF_IO33 0x20000000 /* link autonomous bandwidth */ 503 /* change (correctable) */ 504 #define PEX_5400_NF_IO32 0x10000000 /* Received CA Posted Request */ 505 #define PEX_5400_NF_IO31 0x08000000 /* Received UR Posted Request */ 506 #define PEX_5400_NF_IO30 0x04000000 /* VT-d Internal HW */ 507 #define PEX_5400_NF_IO29 0x02000000 /* MSI Address */ 508 #define PEX_5400_NF_IO28 0x01000000 /* Link bandwidth change */ 509 #define PEX_5400_NF_IO27 0x00800000 /* Stop & Scream */ 510 #define PEX_5400_NF_IO26 0x00400000 /* Received CA Response */ 511 #define PEX_5400_NF_IO25 0x00200000 /* Received UR Response */ 512 #define PEX_5400_NF_IO24 0x00100000 /* Outbound poisoned TLP */ 513 #define PEX_5400_NF_IO23 0x00080000 /* VT-d Fault */ 514 #define PEX_5400_NF_IO11 0x00040000 /* received non fatal err msg */ 515 #define PEX_5400_NF_IO17 0x00020000 /* rec correctable error msg */ 516 #define PEX_5400_NF_IO2 0x00008000 /* Received unsupported req */ 517 #define PEX_5400_NF_IO9 0x00004000 /* Malformed TLP */ 518 #define PEX_5400_NF_IO10 0x00002000 /* Received buffer overflow */ 519 #define PEX_5400_NF_IO8 0x00001000 /* unexpected completion err */ 520 #define PEX_5400_NF_IO7 0x00000800 /* completion abort */ 521 #define PEX_5400_NF_IO6 0x00000400 /* completion timeout */ 522 #define PEX_5400_NF_IO5 0x00000200 /* flow control protocol */ 523 #define PEX_5400_NF_IO4 0x00000100 /* poisoned TLP */ 524 #define PEX_5400_NF_IO19 0x00000080 /* surprise link down */ 525 #define PEX_5400_NF_IO0 0x00000040 /* data link layer protocol */ 526 #define PEX_5400_NF_IO20 0x00000020 /* Advisory Non Fatel */ 527 #define PEX_5400_NF_IO16 0x00000010 /* replay timer timeout */ 528 #define PEX_5400_NF_IO15 0x00000008 /* replay num pollover */ 529 #define PEX_5400_NF_IO14 0x00000004 /* bad DLLP */ 530 #define PEX_5400_NF_IO13 0x00000002 /* bad TLP */ 531 #define PEX_5400_NF_IO12 0x00000001 /* receiver error mask */ 532 #define PEX_NF_IO19 0x00020000 /* surprise link down */ 533 #define PEX_NF_IO17 0x00010000 /* received correctable error message */ 534 #define PEX_NF_IO16 0x00008000 /* replay timer timeout */ 535 #define PEX_NF_IO15 0x00004000 /* replay num pollover */ 536 #define PEX_NF_IO14 0x00002000 /* bad DLLP */ 537 #define PEX_NF_IO13 0x00001000 /* bad TLP */ 538 #define PEX_NF_IO12 0x00000800 /* receiver error mask */ 539 #define PEX_NF_IO11 0x00000400 /* received non fatal error message */ 540 #define PEX_NF_IO10 0x00000200 /* Received buffer overflow */ 541 #define PEX_NF_IO9 0x00000100 /* Malformed TLP */ 542 #define PEX_NF_IO8 0x00000080 543 #define PEX_NF_IO7 0x00000040 544 #define PEX_NF_IO6 0x00000020 /* completion timeout */ 545 #define PEX_NF_IO5 0x00000010 /* flow control protocol */ 546 #define PEX_NF_IO4 0x00000008 /* poisoned TLP */ 547 #define PEX_NF_IO3 0x00000004 548 #define PEX_NF_IO2 0x00000002 549 #define PEX_NF_IO0 0x00000001 /* data link layer protocol */ 550 551 #define ERR_FAT_TH2 0x02 /* >tmid thermal event */ 552 #define ERR_FAT_TH1 0x01 /* Catastrophic on-die thermal event */ 553 554 #define ERR_NF_TH5 0x10 /* timeout on cooling update */ 555 #define ERR_NF_TH4 0x08 /* TSMAX update */ 556 #define ERR_NF_TH3 0x04 /* on-die throttling event */ 557 558 #define EMASK_TH5 0x0010 /* TH5Msk timeout on cooling update */ 559 #define EMASK_TH4 0x0008 /* TH4Msk TSMAX update */ 560 #define EMASK_TH3 0x0004 /* TH3Msk on-die throttling event */ 561 #define EMASK_TH2 0x0002 /* TH2Msk >tmid thermal event */ 562 #define EMASK_TH1 0x0001 /* TH1Msk Catastrophic on-die thermal event */ 563 564 #define GE_FERR_FSB(ferr) ( \ 565 ((ferr) & (GE_FSB0_FATAL|GE_FSB0_NF)) ? 0 : \ 566 ((ferr) & (GE_FSB1_FATAL|GE_FSB1_NF)) ? 1 : \ 567 (nb_chipset == INTEL_NB_7300) && \ 568 ((ferr) & (GE_FERR_FSB2_FATAL|GE_FERR_FSB2_NF)) ? 2 : \ 569 (nb_chipset == INTEL_NB_7300) && \ 570 ((ferr) & (GE_FERR_FSB3_FATAL|GE_FERR_FSB3_NF)) ? 3 : \ 571 -1) 572 573 #define GE_NERR_TO_FERR_FSB(nerr) \ 574 ((((nerr) & GE_NERR_FSB3_FATAL) ? GE_FERR_FSB3_FATAL : 0) | \ 575 (((nerr) & GE_NERR_FSB2_FATAL) ? GE_FERR_FSB2_FATAL : 0) | \ 576 (((nerr) & GE_FSB1_FATAL) ? GE_FSB1_FATAL : 0) | \ 577 (((nerr) & GE_FSB0_FATAL) ? GE_FSB0_FATAL : 0) | \ 578 (((nerr) & GE_NERR_FSB3_NF) ? GE_FERR_FSB3_NF : 0) | \ 579 (((nerr) & GE_NERR_FSB2_NF) ? GE_FERR_FSB2_NF : 0) | \ 580 (((nerr) & GE_FSB1_NF) ? GE_FSB1_NF : 0) | \ 581 (((nerr) & GE_FSB0_NF) ? GE_FSB0_NF : 0)) 582 583 #define GE_ERR_PEX(ferr) ( \ 584 ((ferr) & (GE_ESI_FATAL|GE_ESI_NF)) ? 0 : \ 585 ((nb_chipset == INTEL_NB_7300 || nb_chipset == INTEL_NB_5400) && \ 586 ((ferr) & (GE_PCIEX1_FATAL|GE_PCIEX1_NF))) ? 1 : \ 587 ((ferr) & (GE_PCIEX2_FATAL|GE_PCIEX2_NF)) ? 2 : \ 588 ((ferr) & (GE_PCIEX3_FATAL|GE_PCIEX3_NF)) ? 3 : \ 589 ((ferr) & (GE_PCIEX4_FATAL|GE_PCIEX4_NF)) ? 4 : \ 590 ((ferr) & (GE_PCIEX5_FATAL|GE_PCIEX5_NF)) ? 5 : \ 591 ((ferr) & (GE_PCIEX6_FATAL|GE_PCIEX6_NF)) ? 6 : \ 592 ((ferr) & (GE_PCIEX7_FATAL|GE_PCIEX7_NF)) ? 7 : \ 593 (nb_chipset == INTEL_NB_5400) && \ 594 ((ferr) & (GE_PCIEX8_FATAL|GE_PCIEX8_NF)) ? 8 : \ 595 ((ferr) & (GE_PCIEX9_FATAL|GE_PCIEX9_NF)) ? 9 : \ 596 -1) 597 598 #define GE_FERR_FATAL ((nb_chipset == INTEL_NB_7300) ? \ 599 (GE_INT_FATAL|GE_DMA_FATAL|GE_FERR_FSB3_FATAL|GE_FERR_FSB2_FATAL| \ 600 GE_FSB1_FATAL|GE_FSB0_FATAL|GE_FBD_FATAL|GE_PCIEX7_FATAL| \ 601 GE_PCIEX6_FATAL| GE_PCIEX5_FATAL|GE_PCIEX4_FATAL|GE_PCIEX3_FATAL| \ 602 GE_PCIEX2_FATAL| GE_ESI_FATAL) : \ 603 (GE_INT_FATAL|GE_DMA_FATAL|GE_FSB1_FATAL|GE_FSB0_FATAL|GE_FBD_FATAL| \ 604 GE_PCIEX7_FATAL|GE_PCIEX6_FATAL|GE_PCIEX5_FATAL|GE_PCIEX4_FATAL| \ 605 GE_PCIEX3_FATAL|GE_PCIEX2_FATAL|GE_ESI_FATAL)) 606 607 #define GE_NERR_FATAL ((nb_chipset == INTEL_NB_7300) ? \ 608 (GE_INT_FATAL|GE_DMA_FATAL|GE_NERR_FSB3_FATAL|GE_NERR_FSB2_FATAL| \ 609 GE_FSB1_FATAL|GE_FSB0_FATAL|GE_FBD_FATAL|GE_PCIEX7_FATAL| \ 610 GE_PCIEX6_FATAL|GE_PCIEX5_FATAL|GE_PCIEX4_FATAL|GE_PCIEX3_FATAL| \ 611 GE_PCIEX2_FATALGE_ESI_FATAL) : \ 612 (GE_INT_FATAL|GE_DMA_FATAL|GE_FSB1_FATAL|GE_FSB0_FATAL|GE_FBD_FATAL| \ 613 GE_PCIEX7_FATAL|GE_PCIEX6_FATAL|GE_PCIEX5_FATAL|GE_PCIEX4_FATAL| \ 614 GE_PCIEX3_FATAL|GE_PCIEX2_FATAL|GE_ESI_FATAL)) 615 616 #define GE_PCIEX_FATAL (GE_ESI_FATAL|GE_PCIEX1_FATAL|GE_PCIEX2_FATAL| \ 617 GE_PCIEX3_FATAL|GE_PCIEX4_FATAL|GE_PCIEX5_FATAL|GE_PCIEX6_FATAL| \ 618 GE_PCIEX7_FATAL) 619 #define GE_PCIEX_NF (GE_ESI_NF|GE_PCIEX1_NF|GE_PCIEX2_NF|GE_PCIEX3_NF| \ 620 GE_PCIEX4_NF|GE_PCIEX5_NF|GE_PCIEX6_NF|GE_PCIEX7_NF) 621 #define GE_FERR_FSB_FATAL ((nb_chipset == INTEL_NB_7300) ? \ 622 (GE_FSB0_FATAL|GE_FSB1_FATAL|GE_FERR_FSB2_FATAL|GE_FERR_FSB3_FATAL) : \ 623 (GE_FSB0_FATAL|GE_FSB1_FATAL)) 624 #define GE_NERR_FSB_FATAL ((nb_chipset == INTEL_NB_7300) ? \ 625 (GE_FSB0_FATAL|GE_FSB1_FATAL|GE_NERR_FSB2_FATAL|GE_NERR_FSB3_FATAL) : \ 626 (GE_FSB0_FATAL|GE_FSB1_FATAL)) 627 #define GE_FERR_FSB_NF ((nb_chipset == INTEL_NB_7300) ? \ 628 (GE_FSB0_NF|GE_FSB1_NF|GE_FERR_FSB2_NF|GE_FERR_FSB3_NF) : \ 629 (GE_FSB0_NF|GE_FSB1_NF)) 630 #define GE_NERR_FSB_NF ((nb_chipset == INTEL_NB_7300) ? \ 631 (GE_FSB0_NF|GE_FSB1_NF|GE_NERR_FSB2_NF|GE_NERR_FSB3_NF) : \ 632 (GE_FSB0_NF|GE_FSB1_NF)) 633 634 #define FERR_FBD_CHANNEL(reg) ((reg)>>28 & 3) 635 636 #define NB5000_STEPPING() nb_pci_getw(0, 0, 0, 8, 0) 637 638 #define FERR_GLOBAL_RD() ((nb_chipset == INTEL_NB_7300) ? \ 639 ((uint64_t)nb_pci_getl(0, 16, 2, \ 640 0x48, 0) << 32) | nb_pci_getl(0, 16, 2, \ 641 0x40, 0) : \ 642 (uint64_t)nb_pci_getl(0, 16, 2, 0x40, 0)) 643 #define NERR_GLOBAL_RD() nb_pci_getl(0, 16, 2, 0x44, 0) 644 #define FERR_FAT_FSB_RD(fsb, ip) ((nb_chipset == INTEL_NB_7300) ? \ 645 nb_pci_getb(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc0 : 0x40, ip) : \ 646 nb_pci_getb(0, 16, 0, fsb ? 0x480 : 0x180, ip)) 647 #define FERR_NF_FSB_RD(fsb, ip) ((nb_chipset == INTEL_NB_7300) ? \ 648 nb_pci_getb(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc1 : 0x41, ip) : \ 649 nb_pci_getb(0, 16, 0, fsb ? 0x481 : 0x181, ip)) 650 #define NERR_FAT_FSB_RD(fsb, ip) ((nb_chipset == INTEL_NB_7300) ? \ 651 nb_pci_getb(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc2 : 0x42, ip) : \ 652 nb_pci_getb(0, 16, 0, fsb ? 0x482 : 0x182, ip)) 653 #define NERR_NF_FSB_RD(fsb, ip) ((nb_chipset == INTEL_NB_7300) ? \ 654 nb_pci_getb(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc3 : 0x43, ip) : \ 655 nb_pci_getb(0, 16, 0, fsb ? 0x483 : 0x183, ip)) 656 657 #define NRECFSB_RD(fsb) ((nb_chipset == INTEL_NB_7300) ? \ 658 nb_pci_getl(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc4 : 0x44, 0) : \ 659 nb_pci_getl(0, 16, 0, fsb ? 0x484 : 0x184, 0)) 660 #define NRECFSB_WR(fsb) \ 661 if (nb_chipset == INTEL_NB_7300) { \ 662 nb_pci_putl(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc4 : 0x44, \ 663 0); \ 664 } else { \ 665 nb_pci_putl(0, 16, 0, fsb ? 0x484 : 0x184, 0); \ 666 } 667 #define RECFSB_RD(fsb) ((nb_chipset == INTEL_NB_7300) ? \ 668 nb_pci_getl(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc8 : 0x48, 0) : \ 669 nb_pci_getl(0, 16, 0, fsb ? 0x488 : 0x188, 0)) 670 #define RECFSB_WR(fsb) \ 671 if (nb_chipset == INTEL_NB_7300) { \ 672 nb_pci_putl(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc8 : 0x48, \ 673 0); \ 674 } else { \ 675 nb_pci_putl(0, 16, 0, fsb ? 0x488 : 0x188, 0); \ 676 } 677 #define NRECADDR_RD(fsb) ((nb_chipset == INTEL_NB_7300) ? \ 678 ((uint64_t)(nb_pci_getb(0, 17, (fsb & 2) ? 3 : 0, \ 679 (fsb & 1) ? 0xd0 : 0x50, 0)) << 32) | \ 680 nb_pci_getl(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xcc : 0x4c, 0) : \ 681 ((uint64_t)(nb_pci_getb(0, 16, 0, fsb ? 0x490 : 0x190, 0)) << 32) | \ 682 nb_pci_getl(0, 16, 0, fsb ? 0x48c : 0x18c, 0)) 683 #define NRECADDR_WR(fsb) \ 684 if (nb_chipset == INTEL_NB_7300) { \ 685 nb_pci_putb(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xd0 : 0x50, \ 686 0); \ 687 nb_pci_putl(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xcc : 0x4c, \ 688 0); \ 689 } else { \ 690 nb_pci_putb(0, 16, 0, fsb ? 0x490 : 0x190, 0); \ 691 nb_pci_putl(0, 16, 0, fsb ? 0x48c : 0x18c, 0); \ 692 } 693 #define EMASK_FSB_RD(fsb) ((nb_chipset == INTEL_NB_7300) ? \ 694 nb_pci_getw(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xd2 : 0x52, 0) : \ 695 nb_pci_getw(0, 16, 0, fsb ? 0x492 : 0x192, 0)) 696 #define ERR0_FSB_RD(fsb) ((nb_chipset == INTEL_NB_7300) ? \ 697 nb_pci_getw(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xd4 : 0x54, 0) : \ 698 nb_pci_getw(0, 16, 0, fsb ? 0x494 : 0x194, 0)) 699 #define ERR1_FSB_RD(fsb) ((nb_chipset == INTEL_NB_7300) ? \ 700 nb_pci_getw(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xd6 : 0x56, 0) : \ 701 nb_pci_getw(0, 16, 0, fsb ? 0x496 : 0x196, 0)) 702 #define ERR2_FSB_RD(fsb) ((nb_chipset == INTEL_NB_7300) ? \ 703 nb_pci_getw(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xd8 : 0x58, 0) : \ 704 nb_pci_getw(0, 16, 0, fsb ? 0x498 : 0x198, 0)) 705 #define MCERR_FSB_RD(fsb) ((nb_chipset == INTEL_NB_7300) ? \ 706 nb_pci_getw(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xda : 0x5a, 0) : \ 707 nb_pci_getw(0, 16, 0, fsb ? 0x49a : 0x19a, 0)) 708 709 #define FERR_GLOBAL_WR(val) \ 710 if (nb_chipset == INTEL_NB_7300) \ 711 { \ 712 nb_pci_putl(0, 16, 2, 0x48, (uint32_t)(val >> 32)); \ 713 nb_pci_putl(0, 16, 2, 0x40, (uint32_t)val); \ 714 } else { \ 715 nb_pci_putl(0, 16, 2, 0x40, (uint32_t)val); \ 716 } 717 #define NERR_GLOBAL_WR(val) nb_pci_putl(0, 16, 2, 0x44, val) 718 #define FERR_FAT_FSB_WR(fsb, val) ((nb_chipset == INTEL_NB_7300) ? \ 719 nb_pci_putb(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc0 : 0x40, val) : \ 720 nb_pci_putb(0, 16, 0, fsb ? 0x480 : 0x180, val)) 721 #define FERR_NF_FSB_WR(fsb, val) ((nb_chipset == INTEL_NB_7300) ? \ 722 nb_pci_putb(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc1 : 0x41, val) : \ 723 nb_pci_putb(0, 16, 0, fsb ? 0x481 : 0x181, val)) 724 #define NERR_FAT_FSB_WR(fsb, val) ((nb_chipset == INTEL_NB_7300) ? \ 725 nb_pci_putb(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc2 : 0x42, val) : \ 726 nb_pci_putb(0, 16, 0, fsb ? 0x482 : 0x182, val)) 727 #define NERR_NF_FSB_WR(fsb, val) ((nb_chipset == INTEL_NB_7300) ? \ 728 nb_pci_putb(0, 17, (fsb & 2) ? 3 : 0, (fsb & 1) ? 0xc3 : 0x43, val) : \ 729 nb_pci_putb(0, 16, 0, fsb ? 0x483 : 0x183, val)) 730 #define EMASK_FSB_WR(fsb, val) \ 731 { \ 732 if (nb_chipset == INTEL_NB_7300) \ 733 nb_pci_putw(0, 17, ((fsb) & 2) ? 3 : 0, \ 734 ((fsb) & 1) ? 0xd2 : 0x52, val); \ 735 else \ 736 nb_pci_putw(0, 16, 0, fsb ? 0x492 : 0x192, val); \ 737 } 738 #define ERR0_FSB_WR(fsb, val) \ 739 { \ 740 if (nb_chipset == INTEL_NB_7300) \ 741 nb_pci_putw(0, 17, (fsb & 2) ? 3 : 0, \ 742 (fsb & 1) ? 0xd4 : 0x54, val); \ 743 else \ 744 nb_pci_putw(0, 16, 0, fsb ? 0x494 : 0x194, val); \ 745 } 746 #define ERR1_FSB_WR(fsb, val) \ 747 { \ 748 if (nb_chipset == INTEL_NB_7300) \ 749 nb_pci_putw(0, 17, (fsb & 2) ? 3 : 0, \ 750 (fsb & 1) ? 0xd6 : 0x56, val); \ 751 else \ 752 nb_pci_putw(0, 16, 0, fsb ? 0x496 : 0x196, val); \ 753 } 754 #define ERR2_FSB_WR(fsb, val) \ 755 { \ 756 if (nb_chipset == INTEL_NB_7300) \ 757 nb_pci_putw(0, 17, (fsb & 2) ? 3 : 0, \ 758 (fsb & 1) ? 0xd8 : 0x58, val); \ 759 else \ 760 nb_pci_putw(0, 16, 0, fsb ? 0x498 : 0x198, val); \ 761 } 762 #define MCERR_FSB_WR(fsb, val) \ 763 { \ 764 if (nb_chipset == INTEL_NB_7300) \ 765 nb_pci_putw(0, 17, (fsb & 2) ? 3 : 0, \ 766 (fsb & 1) ? 0xda : 0x5a, val); \ 767 else \ 768 nb_pci_putw(0, 16, 0, fsb ? 0x49a : 0x19a, val); \ 769 } 770 771 #define NRECSF_RD() (nb_chipset == INTEL_NB_5000X || \ 772 nb_chipset == INTEL_NB_7300) ? ((uint64_t)( \ 773 nb_pci_getl(0, 16, 2, 0xb4, 0)) << 32) | \ 774 nb_pci_getl(0, 16, 2, 0xb0, 0) : 0LL 775 #define RECSF_RD() (nb_chipset == INTEL_NB_5000X || \ 776 nb_chipset == INTEL_NB_7300) ? ((uint64_t)( \ 777 nb_pci_getl(0, 16, 2, 0xbc, 0)) << 32) | \ 778 nb_pci_getl(0, 16, 2, 0xb8, 0) : 0LL 779 780 #define NRECSF_WR() if (nb_chipset == INTEL_NB_5000X || \ 781 nb_chipset == INTEL_NB_7300) { \ 782 nb_pci_putl(0, 16, 2, 0xbc, 0); \ 783 nb_pci_putl(0, 16, 2, 0xb0, 0); \ 784 } 785 #define RECSF_WR() if (nb_chipset == INTEL_NB_5000X || \ 786 nb_chipset == INTEL_NB_7300) { \ 787 nb_pci_putl(0, 16, 2, 0xbc, 0); \ 788 nb_pci_putl(0, 16, 2, 0xb8, 0); \ 789 } 790 791 #define FERR_FAT_INT_RD(ip) (((nb_chipset == INTEL_NB_5400) ? \ 792 ((uint16_t)nb_pci_getb(0, 16, 2, 0xc1, ip) << 8) : (uint16_t)0) | \ 793 nb_pci_getb(0, 16, 2, 0xc0, ip)) 794 #define FERR_NF_INT_RD(ip) ((nb_chipset == INTEL_NB_5400) ? \ 795 ((uint16_t)nb_pci_getb(0, 16, 2, 0xc3, ip) << 8) | \ 796 nb_pci_getb(0, 16, 2, 0xc2, ip) : \ 797 (uint16_t)nb_pci_getb(0, 16, 2, 0xc1, ip)) 798 #define NERR_FAT_INT_RD(ip) ((nb_chipset == INTEL_NB_5400) ? \ 799 ((uint16_t)nb_pci_getb(0, 16, 2, 0xc5, ip) << 8) | \ 800 nb_pci_getb(0, 16, 2, 0xc4, ip) : \ 801 (uint16_t)nb_pci_getb(0, 16, 2, 0xc2, ip)) 802 #define NERR_NF_INT_RD(ip) ((nb_chipset == INTEL_NB_5400) ? \ 803 ((uint16_t)nb_pci_getb(0, 16, 2, 0xc7, ip) << 8) | \ 804 nb_pci_getb(0, 16, 2, 0xc6, ip) : \ 805 (uint16_t)nb_pci_getb(0, 16, 2, 0xc3, ip)) 806 #define EMASK_INT_RD() ((nb_chipset == INTEL_NB_5400) ? \ 807 nb_pci_getl(0, 16, 2, 0xd0, 0) : nb_pci_getb(0, 16, 2, 0xcc, 0)) 808 #define ERR0_INT_RD() ((nb_chipset == INTEL_NB_5400) ? \ 809 nb_pci_getl(0, 16, 2, 0xd4, 0) : nb_pci_getb(0, 16, 2, 0xd0, 0)) 810 #define ERR1_INT_RD() ((nb_chipset == INTEL_NB_5400) ? \ 811 nb_pci_getl(0, 16, 2, 0xd8, 0) : nb_pci_getb(0, 16, 2, 0xd1, 0)) 812 #define ERR2_INT_RD() ((nb_chipset == INTEL_NB_5400) ? \ 813 nb_pci_getl(0, 16, 2, 0xdc, 0) : nb_pci_getb(0, 16, 2, 0xd2, 0)) 814 #define MCERR_INT_RD() ((nb_chipset == INTEL_NB_5400) ? \ 815 nb_pci_getl(0, 16, 2, 0xe0, 0) : nb_pci_getb(0, 16, 2, 0xd3, 0)) 816 817 #define FERR_FAT_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ 818 nb_pci_putb(0, 16, 2, 0xc0, \ 819 val & 0xff); \ 820 nb_pci_putb(0, 16, 2, 0xc1, val >> 8); \ 821 } else { \ 822 nb_pci_putb(0, 16, 2, 0xc0, val); \ 823 } 824 #define FERR_NF_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ 825 nb_pci_putb(0, 16, 2, 0xc2, \ 826 val & 0xff); \ 827 nb_pci_putb(0, 16, 2, 0xc3, val >> 8); \ 828 } else { \ 829 nb_pci_putb(0, 16, 2, 0xc1, val); \ 830 } 831 #define NERR_FAT_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ 832 nb_pci_putb(0, 16, 2, 0xc4, \ 833 val & 0xff); \ 834 nb_pci_putb(0, 16, 2, 0xc5, val >> 8); \ 835 } else { \ 836 nb_pci_putb(0, 16, 2, 0xc2, val); \ 837 } 838 #define NERR_NF_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ 839 nb_pci_putb(0, 16, 2, 0xc6, \ 840 val & 0xff); \ 841 nb_pci_putb(0, 16, 2, 0xc7, val >> 8); \ 842 } else { \ 843 nb_pci_putb(0, 16, 2, 0xc3, val); \ 844 } 845 #define EMASK_5000_INT_WR(val) nb_pci_putb(0, 16, 2, 0xcc, val) 846 #define EMASK_5400_INT_WR(val) nb_pci_putl(0, 16, 2, 0xd0, val) 847 #define EMASK_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ 848 EMASK_5400_INT_WR(val); \ 849 } else { \ 850 EMASK_5000_INT_WR(val); \ 851 } 852 #define ERR0_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ 853 nb_pci_putl(0, 16, 2, 0xd4, val); \ 854 } else { \ 855 nb_pci_putb(0, 16, 2, 0xd0, val); \ 856 } 857 #define ERR1_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ 858 nb_pci_putl(0, 16, 2, 0xd8, val); \ 859 } else { \ 860 nb_pci_putb(0, 16, 2, 0xd1, val); \ 861 } 862 #define ERR2_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ 863 nb_pci_putl(0, 16, 2, 0xdc, val); \ 864 } else { \ 865 nb_pci_putb(0, 16, 2, 0xd2, val); \ 866 } 867 #define MCERR_INT_WR(val) if (nb_chipset == INTEL_NB_5400) { \ 868 nb_pci_putl(0, 16, 2, 0xe0, val); \ 869 } else { \ 870 nb_pci_putb(0, 16, 2, 0xd3, val); \ 871 } 872 873 #define NRECINT_RD() nb_pci_getl(0, 16, 2, \ 874 nb_chipset == INTEL_NB_5400 ? 0xc8 : 0xc4, 0) 875 #define RECINT_RD() nb_pci_getl(0, 16, 2, \ 876 nb_chipset == INTEL_NB_5400 ? 0xcc : 0xc8, 0) 877 878 #define NRECINT_WR() nb_pci_putl(0, 16, 2, \ 879 nb_chipset == INTEL_NB_5400 ? 0xc8 : 0xc4, 0) 880 #define RECINT_WR() nb_pci_putl(0, 16, 2, \ 881 nb_chipset == INTEL_NB_5400 ? 0xcc : 0xc8, 0) 882 883 884 #define FERR_FAT_FBD_RD(ip) nb_pci_getl(0, 16, 1, 0x98, ip) 885 #define NERR_FAT_FBD_RD(ip) nb_pci_getl(0, 16, 1, 0x9c, ip) 886 #define FERR_NF_FBD_RD(ip) nb_pci_getl(0, 16, 1, 0xa0, ip) 887 #define NERR_NF_FBD_RD(ip) nb_pci_getl(0, 16, 1, 0xa4, ip) 888 #define EMASK_FBD_RD() nb_pci_getl(0, 16, 1, 0xa8, 0) 889 #define ERR0_FBD_RD() nb_pci_getl(0, 16, 1, 0xac, 0) 890 #define ERR1_FBD_RD() nb_pci_getl(0, 16, 1, 0xb0, 0) 891 #define ERR2_FBD_RD() nb_pci_getl(0, 16, 1, 0xb4, 0) 892 #define MCERR_FBD_RD() nb_pci_getl(0, 16, 1, 0xb8, 0) 893 894 #define FERR_FAT_FBD_WR(val) nb_pci_putl(0, 16, 1, 0x98, val) 895 #define NERR_FAT_FBD_WR(val) nb_pci_putl(0, 16, 1, 0x9c, val) 896 #define FERR_NF_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xa0, val) 897 #define NERR_NF_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xa4, val) 898 #define EMASK_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xa8, val) 899 #define ERR0_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xac, val) 900 #define ERR1_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xb0, val) 901 #define ERR2_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xb4, val) 902 #define MCERR_FBD_WR(val) nb_pci_putl(0, 16, 1, 0xb8, val) 903 904 #define NRECMEMA_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 905 nb_pci_getw(0, (branch) ? 22 : 21, 1, 0xbe, 0) : \ 906 nb_pci_getw(0, 16, 1, 0xbe, 0)) 907 #define NRECMEMB_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 908 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xc0, 0) : \ 909 nb_pci_getl(0, 16, 1, 0xc0, 0)) 910 #define NRECFGLOG_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 911 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0x74, 0) : \ 912 nb_pci_getl(0, 16, 1, 0xc4, 0)) 913 #define NRECFBDA_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 914 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xc4, 0) : \ 915 nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xc4 : 0xc8, 0)) 916 #define NRECFBDB_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 917 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xc8, 0) : \ 918 nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xc8 : 0xcc, 0)) 919 #define NRECFBDC_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 920 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xcc, 0) : \ 921 nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xcc : 0xd0, 0)) 922 #define NRECFBDD_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 923 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xd0, 0) : \ 924 nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xd0 : 0xd4, 0)) 925 #define NRECFBDE_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 926 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xd4, 0) : \ 927 nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xd4 : 0xd8, 0)) 928 #define NRECFBDF_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 929 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xd8, 0) : \ 930 nb_chipset == INTEL_NB_7300 ? nb_pci_getw(0, 16, 1, 0xd8, 0) : 0) 931 #define REDMEMB_RD() (nb_chipset == INTEL_NB_5400 ? \ 932 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0x7c, 0) : \ 933 nb_pci_getl(0, 16, 1, 0x7c, 0)) 934 #define RECMEMA_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 935 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xe0, 0) & 0xffffff : \ 936 nb_pci_getw(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xe0 : 0xe2, 0)) 937 #define RECMEMB_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 938 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xe4, 0) : \ 939 nb_pci_getl(0, 16, 1, 0xe4, 0)) 940 #define RECFGLOG_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 941 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0x78, 0) : \ 942 nb_chipset == INTEL_NB_7300 ? nb_pci_getl(0, 16, 1, 0x78, 0) : \ 943 nb_pci_getl(0, 16, 1, 0xe8, 0)) 944 #define RECFBDA_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 945 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xe8, 0) : \ 946 nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xe8 : 0xec, 0)) 947 #define RECFBDB_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 948 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xec, 0) : \ 949 nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xec : 0xf0, 0)) 950 #define RECFBDC_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 951 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xf0, 0) : \ 952 nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xf0 : 0xf4, 0)) 953 #define RECFBDD_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 954 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xf4, 0) : \ 955 nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xf4 : 0xf8, 0)) 956 #define RECFBDE_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 957 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xf8, 0) : \ 958 nb_pci_getl(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xf8 : 0xfc, 0)) 959 #define RECFBDF_RD(branch) (nb_chipset == INTEL_NB_5400 ? \ 960 nb_pci_getl(0, (branch) ? 22 : 21, 1, 0xfc, 0) : \ 961 nb_chipset == INTEL_NB_7300 ? nb_pci_getw(0, 16, 1, 0xfc, 0) : 0) 962 #define NRECMEMA_WR(branch) (nb_chipset == INTEL_NB_5400 ? \ 963 nb_pci_putw(0, (branch) ? 22 : 21, 1, 0xbe, 0) : \ 964 nb_pci_putw(0, 16, 1, 0xbe, 0)) 965 #define NRECMEMB_WR(branch) (nb_chipset == INTEL_NB_5400 ? \ 966 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xc0, 0) : \ 967 nb_pci_putl(0, 16, 1, 0xc0, 0)) 968 #define NRECFGLOG_WR(branch) \ 969 if (nb_chipset == INTEL_NB_5400) \ 970 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0x74, 0); \ 971 else if (nb_chipset == INTEL_NB_7300) \ 972 nb_pci_putl(0, 16, 1, 0x74, 0); \ 973 else \ 974 nb_pci_putl(0, 16, 1, 0xc4, 0) 975 #define NRECFBDA_WR(branch) \ 976 if (nb_chipset == INTEL_NB_5400) \ 977 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xc4, 0); \ 978 else if (nb_chipset == INTEL_NB_7300) \ 979 nb_pci_putl(0, 16, 1, 0xc4, 0); \ 980 else \ 981 nb_pci_putl(0, 16, 1, 0xc8, 0) 982 #define NRECFBDB_WR(branch) \ 983 if (nb_chipset == INTEL_NB_5400) \ 984 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xc8, 0); \ 985 else if (nb_chipset == INTEL_NB_7300) \ 986 nb_pci_putl(0, 16, 1, 0xc8, 0); \ 987 else \ 988 nb_pci_putl(0, 16, 1, 0xcc, 0) 989 #define NRECFBDC_WR(branch) \ 990 if (nb_chipset == INTEL_NB_5400) \ 991 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xcc, 0); \ 992 else if (nb_chipset == INTEL_NB_7300) \ 993 nb_pci_putl(0, 16, 1, 0xcc, 0); \ 994 else \ 995 nb_pci_putl(0, 16, 1, 0xd0, 0) 996 #define NRECFBDD_WR(branch) \ 997 if (nb_chipset == INTEL_NB_5400) \ 998 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xd0, 0); \ 999 else if (nb_chipset == INTEL_NB_7300) \ 1000 nb_pci_putl(0, 16, 1, 0xd0, 0); \ 1001 else \ 1002 nb_pci_putl(0, 16, 1, 0xd4, 0) 1003 #define NRECFBDE_WR(branch) \ 1004 if (nb_chipset == INTEL_NB_5400) \ 1005 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xd4, 0); \ 1006 else if (nb_chipset == INTEL_NB_7300) \ 1007 nb_pci_putl(0, 16, 1, 0xd4, 0); \ 1008 else \ 1009 nb_pci_putl(0, 16, 1, 0xd8, 0) 1010 #define NRECFBDF_WR(branch) \ 1011 if (nb_chipset == INTEL_NB_5400) \ 1012 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xd8, 0); \ 1013 else if (nb_chipset == INTEL_NB_7300) \ 1014 nb_pci_putw(0, 16, 1, 0xd8, 0); 1015 #define REDMEMB_WR(branch) \ 1016 if (nb_chipset == INTEL_NB_5400) \ 1017 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0x7c, 0); \ 1018 else \ 1019 nb_pci_putl(0, 16, 1, 0x7c, 0) 1020 #define RECMEMA_WR(branch) \ 1021 if (nb_chipset == INTEL_NB_5400) \ 1022 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xe0, 0); \ 1023 else \ 1024 nb_pci_putw(0, 16, 1, nb_chipset == INTEL_NB_7300 ? 0xe0 : \ 1025 0xe2, 0) 1026 #define RECMEMB_WR(branch) \ 1027 if (nb_chipset == INTEL_NB_5400) \ 1028 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xe4, 0); \ 1029 else \ 1030 nb_pci_putl(0, 16, 1, 0xe4, 0) 1031 #define RECFGLOG_WR(branch) \ 1032 if (nb_chipset == INTEL_NB_5400) \ 1033 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0x78, 0); \ 1034 else if (nb_chipset == INTEL_NB_7300) \ 1035 nb_pci_putl(0, 16, 1, 0x78, 0); \ 1036 else \ 1037 nb_pci_putl(0, 16, 1, 0xe8, 0) 1038 #define RECFBDA_WR(branch) \ 1039 if (nb_chipset == INTEL_NB_5400) \ 1040 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xe8, 0); \ 1041 else if (nb_chipset == INTEL_NB_7300) \ 1042 nb_pci_putl(0, 16, 1, 0xe8, 0); \ 1043 else \ 1044 nb_pci_putl(0, 16, 1, 0xec, 0) 1045 #define RECFBDB_WR(branch) \ 1046 if (nb_chipset == INTEL_NB_5400) \ 1047 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xec, 0); \ 1048 else if (nb_chipset == INTEL_NB_7300) \ 1049 nb_pci_putl(0, 16, 1, 0xec, 0); \ 1050 else \ 1051 nb_pci_putl(0, 16, 1, 0xf0, 0) 1052 #define RECFBDC_WR(branch) \ 1053 if (nb_chipset == INTEL_NB_5400) \ 1054 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xf0, 0); \ 1055 else if (nb_chipset == INTEL_NB_7300) \ 1056 nb_pci_putl(0, 16, 1, 0xf0, 0); \ 1057 else \ 1058 nb_pci_putl(0, 16, 1, 0xf4, 0) 1059 #define RECFBDD_WR(branch) \ 1060 if (nb_chipset == INTEL_NB_5400) \ 1061 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xf4, 0); \ 1062 else if (nb_chipset == INTEL_NB_7300) \ 1063 nb_pci_putl(0, 16, 1, 0xf4, 0); \ 1064 else \ 1065 nb_pci_putl(0, 16, 1, 0xf8, 0) 1066 #define RECFBDE_WR(branch) \ 1067 if (nb_chipset == INTEL_NB_5400) \ 1068 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xf8, 0); \ 1069 else if (nb_chipset == INTEL_NB_7300) \ 1070 nb_pci_putl(0, 16, 1, 0xf8, 0); \ 1071 else \ 1072 nb_pci_putl(0, 16, 1, 0xfc, 0) 1073 #define RECFBDF_WR(branch) \ 1074 if (nb_chipset == INTEL_NB_5400) \ 1075 nb_pci_putl(0, (branch) ? 22 : 21, 1, 0xfc, 0); \ 1076 else if (nb_chipset == INTEL_NB_7300) \ 1077 nb_pci_putw(0, 16, 1, 0xf8, 0); \ 1078 1079 #define FERR_NF_MEM_RD(ip) nb_pci_getl(0, 16, 1, 0xa0, ip) 1080 #define NERR_NF_MEM_RD(ip) nb_pci_getl(0, 16, 1, 0xa4, ip) 1081 #define EMASK_MEM_RD() nb_pci_getl(0, 16, 1, 0xa8, 0) 1082 #define ERR0_MEM_RD() nb_pci_getl(0, 16, 1, 0xac, 0) 1083 #define ERR1_MEM_RD() nb_pci_getl(0, 16, 1, 0xb0, 0) 1084 #define ERR2_MEM_RD() nb_pci_getl(0, 16, 1, 0xb4, 0) 1085 #define MCERR_MEM_RD() nb_pci_getl(0, 16, 1, 0xb8, 0) 1086 #define FERR_NF_MEM_WR(val) \ 1087 nb_pci_putl(0, 16, 1, 0xa0, (val)) 1088 #define NERR_NF_MEM_WR(val) \ 1089 nb_pci_putl(0, 16, 1, 0xa4, (val)) 1090 #define EMASK_MEM_WR(val) \ 1091 nb_pci_putl(0, 16, 1, 0xa8, (val)) 1092 #define ERR0_MEM_WR(val) \ 1093 nb_pci_putl(0, 16, 1, 0xac, (val)) 1094 #define ERR1_MEM_WR(val) \ 1095 nb_pci_putl(0, 16, 1, 0xb0, (val)) 1096 #define ERR2_MEM_WR(val) \ 1097 nb_pci_putl(0, 16, 1, 0xb4, (val)) 1098 #define MCERR_MEM_WR(val) \ 1099 nb_pci_putl(0, 16, 1, 0xb8, (val)) 1100 #define VALIDLOG_RD(branch) \ 1101 nb_pci_getl(0, (branch) ? 22 : 21, 0, 0x18c, 0) 1102 #define MEM_NRECMEMA_RD(branch) \ 1103 nb_pci_getl(0, (branch) ? 22 : 21, 0, 0x190, 0) 1104 #define MEM_NRECMEMB_RD(branch) \ 1105 nb_pci_getl(0, (branch) ? 22 : 21, 0, 0x194, 0) 1106 #define MEM_REDMEMA_RD(branch) \ 1107 nb_pci_getl(0, (branch) ? 22 : 21, 0, 0x198, 0) 1108 #define MEM_REDMEMB_RD(branch) \ 1109 nb_pci_getl(0, (branch) ? 22 : 21, 0, 0x19c, 0) 1110 #define MEM_RECMEMA_RD(branch) \ 1111 nb_pci_getl(0, (branch) ? 22 : 21, 0, 0x1a0, 0) 1112 #define MEM_RECMEMB_RD(branch) \ 1113 nb_pci_getl(0, (branch) ? 22 : 21, 0, 0x1a4, 0) 1114 #define MEM_CERRCNT_RD(branch) nb_pci_getl(0, 21, 0, 0x180, 0) 1115 #define MEM_CERRCNT_EXT_RD(branch) nb_pci_getw(0, 21, 0, 0x184, 0) 1116 #define MEM_NRECMEMA_WR(branch) \ 1117 nb_pci_putl(0, (branch) ? 22 : 21, 0, 0x190, 0) 1118 #define MEM_NRECMEMB_WR(branch) \ 1119 nb_pci_putl(0, (branch) ? 22 : 21, 0, 0x194, 0) 1120 #define MEM_REDMEMA_WR(branch) \ 1121 nb_pci_putl(0, (branch) ? 22 : 21, 0, 0x198, 0) 1122 #define MEM_REDMEMB_WR(branch) \ 1123 nb_pci_putl(0, (branch) ? 22 : 21, 0, 0x19c, 0) 1124 #define MEM_RECMEMA_WR(branch) \ 1125 nb_pci_putl(0, (branch) ? 22 : 21, 0, 0x1a0, 0) 1126 #define MEM_RECMEMB_WR(branch) \ 1127 nb_pci_putl(0, (branch) ? 22 : 21, 0, 0x1a4, 0) 1128 1129 #define MC_RD() nb_pci_getl(0, 16, 1, 0x40, 0) 1130 #define MC_WR(val) nb_pci_putl(0, 16, 1, 0x40, val) 1131 #define MCA_RD() nb_pci_getl(0, 16, 1, 0x58, 0) 1132 #define TOLM_RD() nb_pci_getw(0, 16, 1, 0x6c, 0) 1133 1134 #define MTR_5100_RD(channel, rank) ((rank) < 4 ? \ 1135 nb_pci_getw(0, (channel) == 0 ? 21 : 22, 0, 0x154 + ((rank) * 2), 0) : \ 1136 nb_pci_getw(0, (channel) == 0 ? 21 : 22, 0, 0x1b0 + (((rank) & 3) * 2),\ 1137 0)) 1138 1139 #define MTR_RD(branch, dimm) (nb_chipset == INTEL_NB_5100 ? \ 1140 MTR_5100_RD(branch, dimm) : \ 1141 nb_chipset == INTEL_NB_5400 ? \ 1142 nb_pci_getw(0, (branch) == 0 ? 21 : 22, 0, 0x80 + dimm * 2, 0) : \ 1143 ((branch) == 0) ? \ 1144 nb_pci_getw(0, 21, 0, \ 1145 dimm >= 4 ? 0x82 + (dimm & 3) * 4 : 0x80 + dimm * 4, 0) : \ 1146 (nb_number_memory_controllers == 2) ? \ 1147 nb_pci_getw(0, 22, 0, \ 1148 dimm >= 4 ? 0x82 + (dimm & 3) * 4 : 0x80 + dimm * 4, 0) : 0) 1149 #define MIR_RD(reg) nb_pci_getw(0, 16, 1, 0x80 + ((reg)*4), 0) 1150 1151 #define DMIR_RD(branch, reg) \ 1152 nb_chipset == INTEL_NB_5100 ? \ 1153 nb_pci_getl(0, ((branch) == 0) ? 21 : 22, 0, 0x15c + ((reg)*4), 0) : \ 1154 ((branch) == 0) ? nb_pci_getl(0, 21, 0, 0x90 + ((reg)*4), 0) : \ 1155 (nb_number_memory_controllers == 2) ? \ 1156 nb_pci_getl(0, 22, 0, 0x90 + ((reg)*4), 0) : 0 1157 1158 #define SPCPC_RD(branch) (nb_chipset == INTEL_NB_5000P || \ 1159 nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \ 1160 nb_chipset == INTEL_NB_5000Z ? \ 1161 (((branch) == 0) ? \ 1162 (uint32_t)nb_pci_getb(0, 21, 0, 0x40, 0) : \ 1163 (nb_number_memory_controllers == 2) ? \ 1164 (uint32_t)nb_pci_getb(0, 22, 0, 0x40, 0) : 0) : \ 1165 nb_pci_getl(0, ((branch) == 0) ? 21 : 22, 0, 0x40, 0)) 1166 1167 #define SPCPC_SPARE_ENABLE (nb_chipset == INTEL_NB_5000P || \ 1168 nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \ 1169 nb_chipset == INTEL_NB_5000Z ? 1 : 0x20) 1170 #define SPCPC_SPRANK(spcpc) (nb_chipset == INTEL_NB_5000P || \ 1171 nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \ 1172 nb_chipset == INTEL_NB_5000Z ? \ 1173 (((spcpc) >> 1) & 7) : ((spcpc) & 0xf)) 1174 1175 #define SPCPS_RD(branch) ((branch) == 0) ? \ 1176 nb_pci_getb(0, 21, 0, nb_chipset == INTEL_NB_5000P || \ 1177 nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \ 1178 nb_chipset == INTEL_NB_5000Z ? 0x41 : 0x43, 0) : \ 1179 (nb_number_memory_controllers == 2) ? \ 1180 nb_pci_getb(0, 22, 0, nb_chipset == INTEL_NB_5000P || \ 1181 nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \ 1182 nb_chipset == INTEL_NB_5000Z ? 0x41 : 0x43, 0) : 0 1183 1184 #define SPCPS_WR(branch) \ 1185 if ((branch) == 0) { \ 1186 nb_pci_putb(0, 21, 0, nb_chipset == INTEL_NB_5000P || \ 1187 nb_chipset == INTEL_NB_5000X || \ 1188 nb_chipset == INTEL_NB_5000V || \ 1189 nb_chipset == INTEL_NB_5000Z ? 0x41 : 0x43, 0); \ 1190 } else if (nb_number_memory_controllers == 2) { \ 1191 nb_pci_putb(0, 22, 0, nb_chipset == INTEL_NB_5000P || \ 1192 nb_chipset == INTEL_NB_5000X || \ 1193 nb_chipset == INTEL_NB_5000V || \ 1194 nb_chipset == INTEL_NB_5000Z ? 0x41 : 0x43, 0); \ 1195 } 1196 1197 #define SPCPS_SPARE_DEPLOYED (nb_chipset == INTEL_NB_5000P || \ 1198 nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \ 1199 nb_chipset == INTEL_NB_5000Z ? 0x11 : 0x60) 1200 #define SPCPS_FAILED_RANK(spcps) (nb_chipset == INTEL_NB_5000P || \ 1201 nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \ 1202 nb_chipset == INTEL_NB_5000Z ? (((spcps) >> 1) & 7) : ((spcps) & 0xf)) 1203 1204 #define UERRCNT_RD(branch) ((branch) == 0) ? \ 1205 nb_pci_getl(0, 21, 0, 0xa4, 0) : \ 1206 (nb_number_memory_controllers == 2) ? \ 1207 nb_pci_getl(0, 22, 0, 0xa4, 0) : 0 1208 #define CERRCNT_RD(branch) ((branch) == 0) ? \ 1209 nb_pci_getl(0, 21, 0, 0xa8, 0) : \ 1210 (nb_number_memory_controllers == 2) ? \ 1211 nb_pci_getl(0, 22, 0, 0xa8, 0) : 0 1212 #define CERRCNTA_RD(branch, channel) \ 1213 nb_pci_getl(0, branch == 0 ? 21 : 22, 0, \ 1214 (channel & 1) == 0 ? 0xe0 : 0xf0, 0) 1215 #define CERRCNTB_RD(branch, channel) \ 1216 nb_pci_getl(0, branch == 0 ? 21 : 22, 0, \ 1217 (channel & 1) == 0 ? 0xe4 : 0xf4, 0) 1218 #define CERRCNTC_RD(branch, channel) \ 1219 (nb_chipset == INTEL_NB_7300 ? \ 1220 nb_pci_getl(0, branch == 0 ? 21 : 22, 0, \ 1221 (channel & 1) == 0 ? 0xe8 : 0xf8, 0) : 0) 1222 #define CERRCNTD_RD(branch, channel) \ 1223 (nb_chipset == INTEL_NB_7300 ? \ 1224 nb_pci_getl(0, branch == 0 ? 21 : 22, 0, \ 1225 (channel & 1) == 0 ? 0xec : 0xfc, 0) : 0) 1226 #define BADRAMA_RD(branch) ((branch) == 0) ? \ 1227 nb_pci_getl(0, 21, 0, 0xac, 0) : \ 1228 (nb_number_memory_controllers == 2) ? \ 1229 nb_pci_getl(0, 22, 0, 0xac, 0) : 0 1230 #define BADRAMB_RD(branch) ((branch) == 0) ? \ 1231 nb_pci_getw(0, 21, 0, 0xb0, 0) : \ 1232 (nb_number_memory_controllers == 2) ? \ 1233 nb_pci_getw(0, 22, 0, 0xb0, 0) : 0 1234 #define BADCNT_RD(branch) ((branch) == 0) ? \ 1235 nb_pci_getl(0, 21, 0, 0xb4, 0) : \ 1236 (nb_number_memory_controllers == 2) ? \ 1237 nb_pci_getl(0, 22, 0, 0xb4, 0) : 0 1238 1239 #define UERRCNT_WR(branch, val) ((branch) == 0) ? \ 1240 nb_pci_putl(0, 21, 0, 0xa4, val) : \ 1241 (nb_number_memory_controllers == 2) ? \ 1242 nb_pci_putl(0, 22, 0, 0xa4, val) \ 1243 : 0 1244 #define CERRCNT_WR(branch, val) ((branch) == 0) ? \ 1245 nb_pci_putl(0, 21, 0, 0xa8, val) : \ 1246 (nb_number_memory_controllers == 2) ? \ 1247 nb_pci_putl(0, 22, 0, 0xa8, val) : 0 1248 #define BADRAMA_WR(branch, val) ((branch) == 0) ? \ 1249 nb_pci_putl(0, 21, 0, 0xac, val) : \ 1250 (nb_number_memory_controllers == 2) ? \ 1251 nb_pci_putl(0, 22, 0, 0xac, val) : 0 1252 #define BADRAMB_WR(branch, val) ((branch) == 0) ? \ 1253 nb_pci_putw(0, 21, 0, 0xb0, val) : \ 1254 (nb_number_memory_controllers == 2) ? \ 1255 nb_pci_putw(0, 22, 0, 0xb0) : 0 1256 #define BADCNT_WR(branch, val) ((branch) == 0) ? \ 1257 nb_pci_putl(0, 21, 0, 0xb4, val) : \ 1258 (nb_number_memory_controllers == 2) ? \ 1259 nb_pci_putl(0, 22, 0, 0xb4, val) : 0 1260 1261 #define SPD_RD(branch, channel) \ 1262 nb_chipset == INTEL_NB_5100 ? nb_pci_getw(0, 16, 1, 0x48, 0) : \ 1263 ((branch) == 0) ? \ 1264 nb_pci_getw(0, 21, 0, 0x74 + ((channel) * 2), 0) : \ 1265 (nb_number_memory_controllers == 2) ? \ 1266 nb_pci_getw(0, 22, 0, 0x74 + ((channel) * 2), 0) : 0 1267 #define SPDCMDRD(branch, channel) ((branch) == 0) ? \ 1268 nb_pci_getl(0, 21, 0, 0x78 + ((channel) * 4), 0) : \ 1269 (nb_number_memory_controllers == 2) ? \ 1270 nb_pci_getl(0, 22, 0, 0x78 + ((channel) * 4), 0) : 0 1271 1272 #define SPDCMD1_1_WR(val) nb_pci_putl(0, 21, 0, 0x7c, val) 1273 #define SPDCMD_WR(branch, channel, val) \ 1274 if (nb_chipset == INTEL_NB_5100) \ 1275 nb_pci_putl(0, 16, 1, 0x4c, val); \ 1276 else if ((branch) == 0) \ 1277 nb_pci_putl(0, 21, 0, 0x78 + ((channel) * 4), val); \ 1278 else if (nb_number_memory_controllers == 2) \ 1279 nb_pci_putl(0, 22, 0, 0x78 + ((channel) * 4), val) 1280 1281 #define UNCERRSTS_RD(pex) nb_pci_getl(0, pex, 0, 0x104, 0) 1282 #define UNCERRMSK_RD(pex) nb_pci_getl(0, pex, 0, 0x108, 0) 1283 #define PEX_FAT_FERR_ESI_RD() nb_pci_getl(0, 0, 0, 0x154, 0) 1284 #define PEX_FAT_NERR_ESI_RD() nb_pci_getl(0, 0, 0, 0x15c, 0) 1285 #define PEX_NF_FERR_ESI_RD() nb_pci_getl(0, 0, 0, 0x158, 0) 1286 #define PEX_NF_NERR_ESI_RD() nb_pci_getl(0, 0, 0, 0x160, 0) 1287 #define PEX_ERR_DOCMD_RD(pex) ((nb_chipset == INTEL_NB_5400) ? \ 1288 nb_pci_getw(0, pex, 0, 0x144, 0) : nb_pci_getl(0, pex, 0, 0x144, 0)) 1289 #define PEX_ERR_PIN_MASK_RD(pex) nb_pci_getw(0, pex, 0, 0x146, 0) 1290 #define EMASK_UNCOR_PEX_RD(pex) nb_pci_getl(0, pex, 0, 0x148, 0) 1291 #define EMASK_COR_PEX_RD(pex) nb_pci_getl(0, pex, 0, 0x14c, 0) 1292 #define EMASK_RP_PEX_RD(pex) nb_pci_getl(0, pex, 0, 0x150, 0) 1293 1294 #define UNCERRSTS_WR(pex, val) nb_pci_putl(0, pex, 0, 0x104, val) 1295 #define UNCERRMSK_WR(pex, val) nb_pci_putl(0, pex, 0, 0x108, val) 1296 #define PEX_FAT_FERR_ESI_WR(val) nb_pci_putl(0, 0, 0, 0x154, val) 1297 #define PEX_FAT_NERR_ESI_WR(val) nb_pci_putl(0, 0, 0, 0x15c, val) 1298 #define PEX_NF_FERR_ESI_WR(val) nb_pci_putl(0, 0, 0, 0x158, val) 1299 #define PEX_NF_NERR_ESI_WR(val) nb_pci_putl(0, 0, 0, 0x160, val) 1300 #define PEX_ERR_DOCMD_WR(pex, val) ((nb_chipset == INTEL_NB_5400) ? \ 1301 nb_pci_putw(0, pex, 0, 0x144, val) : nb_pci_putl(0, pex, 0, 0x144, val)) 1302 #define PEX_ERR_PIN_MASK_WR(pex, val) nb_pci_putw(0, pex, 0, 0x146, val) 1303 #define EMASK_UNCOR_PEX_WR(pex, val) nb_pci_putl(0, pex, 0, 0x148, val) 1304 #define EMASK_COR_PEX_WR(pex, val) nb_pci_putl(0, pex, 0, 0x14c, val) 1305 #define EMASK_RP_PEX_WR(pex, val) nb_pci_putl(0, pex, 0, 0x150, val) 1306 1307 #define PEX_FAT_FERR_RD(pex, ip) nb_pci_getl(0, pex, 0, 0x154, ip) 1308 #define PEX_FAT_NERR_RD(pex, ip) nb_pci_getl(0, pex, 0, 0x15c, ip) 1309 #define PEX_NF_FERR_RD(pex, ip) nb_pci_getl(0, pex, 0, 0x158, ip) 1310 #define PEX_NF_NERR_RD(pex, ip) nb_pci_getl(0, pex, 0, 0x160, ip) 1311 #define UNCERRSEV_RD(pex) nb_pci_getl(0, pex, 0, 0x10c, 0) 1312 #define CORERRSTS_RD(pex) nb_pci_getl(0, pex, 0, 0x110, 0) 1313 #define RPERRSTS_RD(pex) nb_pci_getl(0, pex, 0, 0x130, 0) 1314 #define RPERRSID_RD(pex) nb_pci_getl(0, pex, 0, 0x134, 0) 1315 #define AERRCAPCTRL_RD(pex) nb_pci_getl(0, pex, 0, 0x118, 0) 1316 #define PEXDEVSTS_RD(pex) nb_pci_getw(0, pex, 0, 0x76, 0) 1317 #define PEXROOTCTL_RD(pex) nb_pci_getw(0, pex, 0, 0x88, 0) 1318 1319 #define PEX_FAT_FERR_WR(pex, val) nb_pci_putl(0, pex, 0, 0x154, val) 1320 #define PEX_FAT_NERR_WR(pex, val) nb_pci_putl(0, pex, 0, 0x15c, val) 1321 #define PEX_NF_FERR_WR(pex, val) nb_pci_putl(0, pex, 0, 0x158, val) 1322 #define PEX_NF_NERR_WR(pex, val) nb_pci_putl(0, pex, 0, 0x160, val) 1323 #define CORERRSTS_WR(pex, val) nb_pci_putl(0, pex, 0, 0x110, val) 1324 #define UNCERRSEV_WR(pex, val) nb_pci_putl(0, pex, 0, 0x10c, val) 1325 #define RPERRSTS_WR(pex, val) nb_pci_putl(0, pex, 0, 0x130, val) 1326 #define PEXDEVSTS_WR(pex, val) nb_pci_putl(0, pex, 0, 0x76, val) 1327 #define PEXROOTCTL_WR(pex, val) nb_pci_putw(0, pex, 0, 0x88, val) 1328 1329 #define PCISTS_RD(ip) nb_pci_getw(0, 8, 0, 0x6, ip) 1330 #define PCIDEVSTS_RD() nb_pci_getw(0, 8, 0, 0x76, 0) 1331 #define PCISTS_WR(val) nb_pci_putw(0, 8, 0, 0x6, val) 1332 #define PCIDEVSTS_WR(val) nb_pci_putw(0, 8, 0, 0x76, val) 1333 1334 #define RANK_MASK (nb_chipset != INTEL_NB_7300 ? 7 : 0xf) 1335 #define CAS_MASK (nb_chipset == INTEL_NB_5000P || \ 1336 nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \ 1337 nb_chipset == INTEL_NB_5000Z ? 0xfff : 0x1fff) 1338 #define RAS_MASK (nb_chipset == INTEL_NB_5000P || \ 1339 nb_chipset == INTEL_NB_5000X || nb_chipset == INTEL_NB_5000V || \ 1340 nb_chipset == INTEL_NB_5000Z ? 0x7fff : 0xffff) 1341 #define BANK_MASK 7 1342 1343 #define DMIR_RANKS(dmir, rank0, rank1, rank2, rank3) \ 1344 if (nb_chipset == INTEL_NB_5000P || nb_chipset == INTEL_NB_5000X || \ 1345 nb_chipset == INTEL_NB_5000V || nb_chipset == INTEL_NB_5000Z || \ 1346 nb_chipset == INTEL_NB_5100) { \ 1347 rank0 = (dmir) & 3; \ 1348 rank1 = ((dmir) >> 3) & 3; \ 1349 rank2 = ((dmir) >> 6) & 3; \ 1350 rank3 = ((dmir) >> 9) & 3; \ 1351 } else { \ 1352 rank0 = (dmir) & 0xf; \ 1353 rank1 = ((dmir) >> 4) & 0xf; \ 1354 rank2 = ((dmir) >> 8) & 0xf; \ 1355 rank3 = ((dmir) >> 12) & 0xf; \ 1356 } 1357 1358 #define FERR_FAT_THR_RD(ip) nb_pci_getb(0, 16, 2, 0xf0, ip) 1359 #define FERR_NF_THR_RD(ip) nb_pci_getb(0, 16, 2, 0xf1, ip) 1360 #define NERR_FAT_THR_RD(ip) nb_pci_getb(0, 16, 2, 0xf2, ip) 1361 #define NERR_NF_THR_RD(ip) nb_pci_getb(0, 16, 2, 0xf3, ip) 1362 #define EMASK_THR_RD(ip) nb_pci_getw(0, 16, 2, 0xf6, ip) 1363 #define ERR0_THR_RD(ip) nb_pci_getw(0, 16, 2, 0xf8, ip) 1364 #define ERR1_THR_RD(ip) nb_pci_getw(0, 16, 2, 0xfa, ip) 1365 #define ERR2_THR_RD(ip) nb_pci_getw(0, 16, 2, 0xfc, ip) 1366 #define MCERR_THR_RD(ip) nb_pci_getw(0, 16, 2, 0xfe, ip) 1367 #define CTSTS_RD() nb_pci_getb(0, 16, 4, 0xee, 0) 1368 #define THRTSTS_RD() nb_pci_getw(0, 16, 3, 0x68, 0) 1369 1370 #define FERR_FAT_THR_WR(val) nb_pci_putb(0, 16, 2, 0xf0, val) 1371 #define FERR_NF_THR_WR(val) nb_pci_putb(0, 16, 2, 0xf1, val) 1372 #define NERR_FAT_THR_WR(val) nb_pci_putb(0, 16, 2, 0xf2, val) 1373 #define NERR_NF_THR_WR(val) nb_pci_putb(0, 16, 2, 0xf3, val) 1374 #define EMASK_THR_WR(val) nb_pci_putw(0, 16, 2, 0xf6, val) 1375 #define ERR0_THR_WR(val) nb_pci_putw(0, 16, 2, 0xf8, val) 1376 #define ERR1_THR_WR(val) nb_pci_putw(0, 16, 2, 0xfa, val) 1377 #define ERR2_THR_WR(val) nb_pci_putw(0, 16, 2, 0xfc, val) 1378 #define MCERR_THR_WR(val) nb_pci_putw(0, 16, 2, 0xfe, val) 1379 #define CTSTS_WR(val) nb_pci_putb(0, 16, 4, 0xee, val) 1380 #define THRTSTS_WR(val) nb_pci_putw(0, 16, 3, 0x68, val) 1381 1382 #define ERR_FAT_THR_F2 0x02 /* >tnid thermal event with intelligent */ 1383 /* throttling disabled */ 1384 #define ERR_FAT_THR_F1 0x01 /* catastrophic on-die thermal event */ 1385 1386 #define ERR_NF_THR_F5 0x10 /* deadman timeout on cooling update */ 1387 #define ERR_NF_THR_F4 0x08 /* TSMAX Updated */ 1388 #define ERR_NF_THR_F3 0x04 /* On-die throttling event */ 1389 1390 #define EMASK_THR_FATAL (ERR_FAT_THR_F2|ERR_FAT_THR_F1) 1391 #define EMASK_THR_NF (ERR_NF_THR_F5|ERR_NF_THR_F4|ERR_NF_THR_F3) 1392 1393 #define EMASK_THR_F5 0x0010 /* deadman timeout on cooling update */ 1394 #define EMASK_THR_F4 0x0008 /* TSMAX Updated */ 1395 #define EMASK_THR_F3 0x0004 /* On-die throttling event */ 1396 #define EMASK_THR_F2 0x0002 /* >tnid thermal event with intelligent */ 1397 /* throttling disabled */ 1398 #define EMASK_THR_F1 0x0001 /* catastrophic on-die thermal event */ 1399 1400 /* dimm type */ 1401 #define SPD_MEM_TYPE 2 1402 #define SPD_DDR2 8 1403 #define SPD_FBDIMM 9 1404 1405 #ifdef __cplusplus 1406 } 1407 #endif 1408 1409 #endif /* _NB5000_H */ 1410