1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2014, Neel Natu (neel@freebsd.org) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 /* 29 * This file and its contents are supplied under the terms of the 30 * Common Development and Distribution License ("CDDL"), version 1.0. 31 * You may only use this file in accordance with the terms of version 32 * 1.0 of the CDDL. 33 * 34 * A full copy of the text of the CDDL should have accompanied this 35 * source. A copy of the CDDL is also available via the Internet at 36 * http://www.illumos.org/license/CDDL. 37 * 38 * Copyright 2020 Oxide Computer Company 39 */ 40 41 #include <sys/cdefs.h> 42 __FBSDID("$FreeBSD$"); 43 44 #include <sys/param.h> 45 #include <sys/errno.h> 46 #include <sys/systm.h> 47 #include <sys/x86_archext.h> 48 #include <sys/privregs.h> 49 50 #include <machine/cpufunc.h> 51 #include <machine/specialreg.h> 52 #include <machine/vmm.h> 53 #include <sys/vmm_kernel.h> 54 55 #include "svm.h" 56 #include "vmcb.h" 57 #include "svm_softc.h" 58 #include "svm_msr.h" 59 60 #ifndef MSR_AMDK8_IPM 61 #define MSR_AMDK8_IPM 0xc0010055 62 #endif 63 64 enum { 65 IDX_MSR_LSTAR, 66 IDX_MSR_CSTAR, 67 IDX_MSR_STAR, 68 IDX_MSR_SF_MASK, 69 HOST_MSR_NUM /* must be the last enumeration */ 70 }; 71 CTASSERT(HOST_MSR_NUM == SVM_HOST_MSR_NUM); 72 73 void 74 svm_msr_guest_init(struct svm_softc *sc, int vcpu) 75 { 76 /* 77 * All the MSRs accessible to the guest are either saved/restored by 78 * hardware on every #VMEXIT/VMRUN (e.g., G_PAT) or are saved/restored 79 * by VMSAVE/VMLOAD (e.g., MSR_GSBASE). 80 * 81 * There are no guest MSRs that are saved/restored "by hand" so nothing 82 * more to do here. 83 */ 84 } 85 86 void 87 svm_msr_guest_enter(struct svm_softc *sc, int vcpu) 88 { 89 uint64_t *host_msrs = sc->host_msrs[vcpu]; 90 91 /* 92 * Save host MSRs (if any) and restore guest MSRs (if any). 93 */ 94 host_msrs[IDX_MSR_LSTAR] = rdmsr(MSR_LSTAR); 95 host_msrs[IDX_MSR_CSTAR] = rdmsr(MSR_CSTAR); 96 host_msrs[IDX_MSR_STAR] = rdmsr(MSR_STAR); 97 host_msrs[IDX_MSR_SF_MASK] = rdmsr(MSR_SF_MASK); 98 99 /* 100 * Set the frequency multiplier MSR to enable guest TSC scaling if 101 * needed. 102 */ 103 uint64_t mult = vm_get_freq_multiplier(sc->vm); 104 if (mult != VM_TSCM_NOSCALE) { 105 wrmsr(MSR_AMD_TSC_RATIO, mult); 106 } 107 } 108 109 void 110 svm_msr_guest_exit(struct svm_softc *sc, int vcpu) 111 { 112 uint64_t *host_msrs = sc->host_msrs[vcpu]; 113 114 /* 115 * Save guest MSRs (if any) and restore host MSRs. 116 */ 117 wrmsr(MSR_LSTAR, host_msrs[IDX_MSR_LSTAR]); 118 wrmsr(MSR_CSTAR, host_msrs[IDX_MSR_CSTAR]); 119 wrmsr(MSR_STAR, host_msrs[IDX_MSR_STAR]); 120 wrmsr(MSR_SF_MASK, host_msrs[IDX_MSR_SF_MASK]); 121 122 /* Reset frequency multiplier MSR */ 123 wrmsr(MSR_AMD_TSC_RATIO, AMD_TSCM_RESET_VAL); 124 125 /* MSR_KGSBASE will be restored on the way back to userspace */ 126 } 127 128 vm_msr_result_t 129 svm_rdmsr(struct svm_softc *sc, int vcpu, uint32_t num, uint64_t *result) 130 { 131 switch (num) { 132 case MSR_SYSCFG: 133 case MSR_AMDK8_IPM: 134 case MSR_EXTFEATURES: 135 *result = 0; 136 break; 137 case MSR_AMD_DE_CFG: 138 *result = 0; 139 /* 140 * Bit 1 of DE_CFG is defined by AMD to control whether the 141 * lfence instruction is serializing. Practically all CPUs 142 * supported by bhyve also contain this MSR, making it safe to 143 * expose unconditionally. 144 */ 145 if (is_x86_feature(x86_featureset, X86FSET_LFENCE_SER)) { 146 *result |= AMD_DE_CFG_LFENCE_DISPATCH; 147 } 148 break; 149 default: 150 return (VMR_UNHANLDED); 151 } 152 return (VMR_OK); 153 } 154 155 vm_msr_result_t 156 svm_wrmsr(struct svm_softc *sc, int vcpu, uint32_t num, uint64_t val) 157 { 158 switch (num) { 159 case MSR_SYSCFG: 160 /* Ignore writes */ 161 break; 162 case MSR_AMD_DE_CFG: 163 /* Ignore writes */ 164 break; 165 case MSR_AMDK8_IPM: 166 /* 167 * Ignore writes to the "Interrupt Pending Message" MSR. 168 */ 169 break; 170 case MSR_K8_UCODE_UPDATE: 171 /* 172 * Ignore writes to microcode update register. 173 */ 174 break; 175 case MSR_EXTFEATURES: 176 break; 177 default: 178 return (VMR_UNHANLDED); 179 } 180 181 return (VMR_OK); 182 } 183