1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2013 Neel Natu <neel@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 /* 31 * This file and its contents are supplied under the terms of the 32 * Common Development and Distribution License ("CDDL"), version 1.0. 33 * You may only use this file in accordance with the terms of version 34 * 1.0 of the CDDL. 35 * 36 * A full copy of the text of the CDDL should have accompanied this 37 * source. A copy of the CDDL is also available via the Internet at 38 * http://www.illumos.org/license/CDDL. 39 * 40 * Copyright 2020 Oxide Computer Company 41 */ 42 43 #ifndef _VLAPIC_PRIV_H_ 44 #define _VLAPIC_PRIV_H_ 45 46 #include <x86/apicreg.h> 47 48 /* 49 * APIC Register: Offset Description 50 */ 51 #define APIC_OFFSET_ID 0x20 /* Local APIC ID */ 52 #define APIC_OFFSET_VER 0x30 /* Local APIC Version */ 53 #define APIC_OFFSET_TPR 0x80 /* Task Priority Register */ 54 #define APIC_OFFSET_APR 0x90 /* Arbitration Priority */ 55 #define APIC_OFFSET_PPR 0xA0 /* Processor Priority Register */ 56 #define APIC_OFFSET_EOI 0xB0 /* EOI Register */ 57 #define APIC_OFFSET_RRR 0xC0 /* Remote read */ 58 #define APIC_OFFSET_LDR 0xD0 /* Logical Destination */ 59 #define APIC_OFFSET_DFR 0xE0 /* Destination Format Register */ 60 #define APIC_OFFSET_SVR 0xF0 /* Spurious Vector Register */ 61 #define APIC_OFFSET_ISR0 0x100 /* In Service Register */ 62 #define APIC_OFFSET_ISR1 0x110 63 #define APIC_OFFSET_ISR2 0x120 64 #define APIC_OFFSET_ISR3 0x130 65 #define APIC_OFFSET_ISR4 0x140 66 #define APIC_OFFSET_ISR5 0x150 67 #define APIC_OFFSET_ISR6 0x160 68 #define APIC_OFFSET_ISR7 0x170 69 #define APIC_OFFSET_TMR0 0x180 /* Trigger Mode Register */ 70 #define APIC_OFFSET_TMR1 0x190 71 #define APIC_OFFSET_TMR2 0x1A0 72 #define APIC_OFFSET_TMR3 0x1B0 73 #define APIC_OFFSET_TMR4 0x1C0 74 #define APIC_OFFSET_TMR5 0x1D0 75 #define APIC_OFFSET_TMR6 0x1E0 76 #define APIC_OFFSET_TMR7 0x1F0 77 #define APIC_OFFSET_IRR0 0x200 /* Interrupt Request Register */ 78 #define APIC_OFFSET_IRR1 0x210 79 #define APIC_OFFSET_IRR2 0x220 80 #define APIC_OFFSET_IRR3 0x230 81 #define APIC_OFFSET_IRR4 0x240 82 #define APIC_OFFSET_IRR5 0x250 83 #define APIC_OFFSET_IRR6 0x260 84 #define APIC_OFFSET_IRR7 0x270 85 #define APIC_OFFSET_ESR 0x280 /* Error Status Register */ 86 #define APIC_OFFSET_CMCI_LVT 0x2F0 /* Local Vector Table (CMCI) */ 87 #define APIC_OFFSET_ICR_LOW 0x300 /* Interrupt Command Register */ 88 #define APIC_OFFSET_ICR_HI 0x310 89 #define APIC_OFFSET_TIMER_LVT 0x320 /* Local Vector Table (Timer) */ 90 #define APIC_OFFSET_THERM_LVT 0x330 /* Local Vector Table (Thermal) */ 91 #define APIC_OFFSET_PERF_LVT 0x340 /* Local Vector Table (PMC) */ 92 #define APIC_OFFSET_LINT0_LVT 0x350 /* Local Vector Table (LINT0) */ 93 #define APIC_OFFSET_LINT1_LVT 0x360 /* Local Vector Table (LINT1) */ 94 #define APIC_OFFSET_ERROR_LVT 0x370 /* Local Vector Table (ERROR) */ 95 #define APIC_OFFSET_TIMER_ICR 0x380 /* Timer's Initial Count */ 96 #define APIC_OFFSET_TIMER_CCR 0x390 /* Timer's Current Count */ 97 #define APIC_OFFSET_TIMER_DCR 0x3E0 /* Timer's Divide Configuration */ 98 #define APIC_OFFSET_SELF_IPI 0x3F0 /* Self IPI register */ 99 100 #define VLAPIC_CTR0(vlapic, format) \ 101 VCPU_CTR0((vlapic)->vm, (vlapic)->vcpuid, format) 102 103 #define VLAPIC_CTR1(vlapic, format, p1) \ 104 VCPU_CTR1((vlapic)->vm, (vlapic)->vcpuid, format, p1) 105 106 #define VLAPIC_CTR2(vlapic, format, p1, p2) \ 107 VCPU_CTR2((vlapic)->vm, (vlapic)->vcpuid, format, p1, p2) 108 109 #define VLAPIC_CTR3(vlapic, format, p1, p2, p3) \ 110 VCPU_CTR3((vlapic)->vm, (vlapic)->vcpuid, format, p1, p2, p3) 111 112 #define VLAPIC_CTR_IRR(vlapic, msg) \ 113 do { \ 114 uint32_t *irrptr = &(vlapic)->apic_page->irr0; \ 115 irrptr[0] = irrptr[0]; /* silence compiler */ \ 116 VLAPIC_CTR1((vlapic), msg " irr0 0x%08x", irrptr[0 << 2]); \ 117 VLAPIC_CTR1((vlapic), msg " irr1 0x%08x", irrptr[1 << 2]); \ 118 VLAPIC_CTR1((vlapic), msg " irr2 0x%08x", irrptr[2 << 2]); \ 119 VLAPIC_CTR1((vlapic), msg " irr3 0x%08x", irrptr[3 << 2]); \ 120 VLAPIC_CTR1((vlapic), msg " irr4 0x%08x", irrptr[4 << 2]); \ 121 VLAPIC_CTR1((vlapic), msg " irr5 0x%08x", irrptr[5 << 2]); \ 122 VLAPIC_CTR1((vlapic), msg " irr6 0x%08x", irrptr[6 << 2]); \ 123 VLAPIC_CTR1((vlapic), msg " irr7 0x%08x", irrptr[7 << 2]); \ 124 } while (0) 125 126 #define VLAPIC_CTR_ISR(vlapic, msg) \ 127 do { \ 128 uint32_t *isrptr = &(vlapic)->apic_page->isr0; \ 129 isrptr[0] = isrptr[0]; /* silence compiler */ \ 130 VLAPIC_CTR1((vlapic), msg " isr0 0x%08x", isrptr[0 << 2]); \ 131 VLAPIC_CTR1((vlapic), msg " isr1 0x%08x", isrptr[1 << 2]); \ 132 VLAPIC_CTR1((vlapic), msg " isr2 0x%08x", isrptr[2 << 2]); \ 133 VLAPIC_CTR1((vlapic), msg " isr3 0x%08x", isrptr[3 << 2]); \ 134 VLAPIC_CTR1((vlapic), msg " isr4 0x%08x", isrptr[4 << 2]); \ 135 VLAPIC_CTR1((vlapic), msg " isr5 0x%08x", isrptr[5 << 2]); \ 136 VLAPIC_CTR1((vlapic), msg " isr6 0x%08x", isrptr[6 << 2]); \ 137 VLAPIC_CTR1((vlapic), msg " isr7 0x%08x", isrptr[7 << 2]); \ 138 } while (0) 139 140 /* 141 * 16 priority levels with at most one vector injected per level. 142 */ 143 #define ISRVEC_STK_SIZE (16 + 1) 144 145 #define VLAPIC_MAXLVT_INDEX APIC_LVT_CMCI 146 147 #define VLAPIC_TMR_CNT 8 148 149 #ifdef DEBUG 150 #define __ISRVEC_DEBUG 151 #endif 152 153 struct vlapic; 154 155 struct vlapic_ops { 156 vcpu_notify_t (*set_intr_ready)(struct vlapic *vlapic, int vector, 157 bool level); 158 void (*sync_state)(struct vlapic *vlapic); 159 void (*intr_accepted)(struct vlapic *vlapic, int vector); 160 void (*post_intr)(struct vlapic *vlapic, int hostcpu); 161 void (*enable_x2apic_mode)(struct vlapic *vlapic); 162 }; 163 164 struct vlapic { 165 struct vm *vm; 166 int vcpuid; 167 struct LAPIC *apic_page; 168 struct vlapic_ops ops; 169 170 uint32_t esr_pending; 171 172 struct callout callout; /* vlapic timer */ 173 hrtime_t timer_fire_when; 174 hrtime_t timer_period; 175 uint32_t timer_cur_freq; 176 177 kmutex_t timer_lock; 178 179 uint64_t msr_apicbase; 180 181 /* 182 * Copies of some registers in the virtual APIC page. We do this for 183 * a couple of different reasons: 184 * - to be able to detect what changed (e.g. svr_last) 185 * - to maintain a coherent snapshot of the register (e.g. lvt_last) 186 */ 187 uint32_t svr_last; 188 uint32_t lvt_last[VLAPIC_MAXLVT_INDEX + 1]; 189 190 #ifdef __ISRVEC_DEBUG 191 /* 192 * The 'isrvec_stk' is a stack of vectors injected by the local APIC. 193 * It is used as a debugging method to double-check the behavior of the 194 * emulation. Vectors are pushed to the stack when they are accepted 195 * for injection and popped from the stack when the processor performs 196 * an EOI. The vector on the top of the stack is used to verify the 197 * computed Processor Priority. 198 */ 199 uint8_t isrvec_stk[ISRVEC_STK_SIZE]; 200 int isrvec_stk_top; 201 #endif 202 }; 203 204 void vlapic_init(struct vlapic *vlapic); 205 void vlapic_cleanup(struct vlapic *vlapic); 206 207 #endif /* _VLAPIC_PRIV_H_ */ 208