17c478bd9Sstevel@tonic-gate /* 27c478bd9Sstevel@tonic-gate * CDDL HEADER START 37c478bd9Sstevel@tonic-gate * 47c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 500d0963fSdilpreet * Common Development and Distribution License (the "License"). 600d0963fSdilpreet * You may not use this file except in compliance with the License. 77c478bd9Sstevel@tonic-gate * 87c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 97c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 107c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 117c478bd9Sstevel@tonic-gate * and limitations under the License. 127c478bd9Sstevel@tonic-gate * 137c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 147c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 157c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 167c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 177c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 187c478bd9Sstevel@tonic-gate * 197c478bd9Sstevel@tonic-gate * CDDL HEADER END 207c478bd9Sstevel@tonic-gate */ 217c478bd9Sstevel@tonic-gate /* 22*39470729Skd93003 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 237c478bd9Sstevel@tonic-gate * Use is subject to license terms. 247c478bd9Sstevel@tonic-gate */ 257c478bd9Sstevel@tonic-gate 267c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 277c478bd9Sstevel@tonic-gate 287c478bd9Sstevel@tonic-gate /* 297c478bd9Sstevel@tonic-gate * Schizo specifics implementation: 307c478bd9Sstevel@tonic-gate * interrupt mapping register 317c478bd9Sstevel@tonic-gate * PBM configuration 327c478bd9Sstevel@tonic-gate * ECC and PBM error handling 337c478bd9Sstevel@tonic-gate * Iommu mapping handling 347c478bd9Sstevel@tonic-gate * Streaming Cache flushing 357c478bd9Sstevel@tonic-gate */ 367c478bd9Sstevel@tonic-gate 377c478bd9Sstevel@tonic-gate #include <sys/types.h> 387c478bd9Sstevel@tonic-gate #include <sys/kmem.h> 397c478bd9Sstevel@tonic-gate #include <sys/sysmacros.h> 407c478bd9Sstevel@tonic-gate #include <sys/async.h> 417c478bd9Sstevel@tonic-gate #include <sys/systm.h> 42b0fc0e77Sgovinda #include <sys/ivintr.h> 437c478bd9Sstevel@tonic-gate #include <sys/machsystm.h> /* lddphys() */ 447c478bd9Sstevel@tonic-gate #include <sys/machsystm.h> /* lddphys, intr_dist_add */ 457c478bd9Sstevel@tonic-gate #include <sys/iommutsb.h> 467c478bd9Sstevel@tonic-gate #include <sys/promif.h> /* prom_printf */ 477c478bd9Sstevel@tonic-gate #include <sys/map.h> 487c478bd9Sstevel@tonic-gate #include <sys/ddi.h> 497c478bd9Sstevel@tonic-gate #include <sys/sunddi.h> 507c478bd9Sstevel@tonic-gate #include <sys/sunndi.h> 517c478bd9Sstevel@tonic-gate #include <sys/spl.h> 527c478bd9Sstevel@tonic-gate #include <sys/fm/util.h> 537c478bd9Sstevel@tonic-gate #include <sys/ddi_impldefs.h> 547c478bd9Sstevel@tonic-gate #include <sys/fm/protocol.h> 557c478bd9Sstevel@tonic-gate #include <sys/fm/io/sun4upci.h> 567c478bd9Sstevel@tonic-gate #include <sys/fm/io/ddi.h> 577c478bd9Sstevel@tonic-gate #include <sys/fm/io/pci.h> 587c478bd9Sstevel@tonic-gate #include <sys/pci/pci_obj.h> 597c478bd9Sstevel@tonic-gate #include <sys/pci/pcisch.h> 607c478bd9Sstevel@tonic-gate #include <sys/pci/pcisch_asm.h> 617c478bd9Sstevel@tonic-gate #include <sys/x_call.h> /* XCALL_PIL */ 627c478bd9Sstevel@tonic-gate 637c478bd9Sstevel@tonic-gate /*LINTLIBRARY*/ 647c478bd9Sstevel@tonic-gate 657c478bd9Sstevel@tonic-gate extern uint8_t ldstub(uint8_t *); 667c478bd9Sstevel@tonic-gate 677c478bd9Sstevel@tonic-gate #define IOMMU_CTX_BITMAP_SIZE (1 << (12 - 3)) 687c478bd9Sstevel@tonic-gate static void iommu_ctx_free(iommu_t *); 697c478bd9Sstevel@tonic-gate static int iommu_tlb_scrub(iommu_t *, int); 707c478bd9Sstevel@tonic-gate static uint32_t pci_identity_init(pci_t *); 717c478bd9Sstevel@tonic-gate 727c478bd9Sstevel@tonic-gate static void pci_cb_clear_error(cb_t *, cb_errstate_t *); 737c478bd9Sstevel@tonic-gate static void pci_clear_error(pci_t *, pbm_errstate_t *); 747c478bd9Sstevel@tonic-gate static uint32_t pci_identity_init(pci_t *pci_p); 757c478bd9Sstevel@tonic-gate static int pci_intr_setup(pci_t *pci_p); 767c478bd9Sstevel@tonic-gate static void iommu_ereport_post(dev_info_t *, uint64_t, pbm_errstate_t *); 777c478bd9Sstevel@tonic-gate static void cb_ereport_post(dev_info_t *, uint64_t, cb_errstate_t *); 787c478bd9Sstevel@tonic-gate static void pcix_ereport_post(dev_info_t *, uint64_t, pbm_errstate_t *); 797c478bd9Sstevel@tonic-gate static void pci_format_ecc_addr(dev_info_t *dip, uint64_t *afar, 807c478bd9Sstevel@tonic-gate ecc_region_t region); 817c478bd9Sstevel@tonic-gate static void pci_pbm_errstate_get(pci_t *pci_p, pbm_errstate_t *pbm_err_p); 827c478bd9Sstevel@tonic-gate static void tm_vmem_free(ddi_dma_impl_t *mp, iommu_t *iommu_p, 837c478bd9Sstevel@tonic-gate dvma_addr_t dvma_pg, int npages); 847c478bd9Sstevel@tonic-gate 857c478bd9Sstevel@tonic-gate static int pcix_ma_behind_bridge(pbm_errstate_t *pbm_err_p); 867c478bd9Sstevel@tonic-gate 877c478bd9Sstevel@tonic-gate static pci_ksinfo_t *pci_name_kstat; 887c478bd9Sstevel@tonic-gate static pci_ksinfo_t *saf_name_kstat; 897c478bd9Sstevel@tonic-gate 907c478bd9Sstevel@tonic-gate extern void pcix_set_cmd_reg(dev_info_t *child, uint16_t value); 917c478bd9Sstevel@tonic-gate 927c478bd9Sstevel@tonic-gate /* called by pci_attach() DDI_ATTACH to initialize pci objects */ 937c478bd9Sstevel@tonic-gate int 947c478bd9Sstevel@tonic-gate pci_obj_setup(pci_t *pci_p) 957c478bd9Sstevel@tonic-gate { 967c478bd9Sstevel@tonic-gate pci_common_t *cmn_p; 977c478bd9Sstevel@tonic-gate uint32_t chip_id = pci_identity_init(pci_p); 987c478bd9Sstevel@tonic-gate uint32_t cmn_id = PCI_CMN_ID(ID_CHIP_TYPE(chip_id), pci_p->pci_id); 997c478bd9Sstevel@tonic-gate int ret; 1007c478bd9Sstevel@tonic-gate 1017c478bd9Sstevel@tonic-gate /* Perform allocations first to avoid delicate unwinding. */ 1027c478bd9Sstevel@tonic-gate if (pci_alloc_tsb(pci_p) != DDI_SUCCESS) 1037c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 1047c478bd9Sstevel@tonic-gate 1057c478bd9Sstevel@tonic-gate mutex_enter(&pci_global_mutex); 1067c478bd9Sstevel@tonic-gate cmn_p = get_pci_common_soft_state(cmn_id); 1077c478bd9Sstevel@tonic-gate if (cmn_p == NULL) { 1087c478bd9Sstevel@tonic-gate if (alloc_pci_common_soft_state(cmn_id) != DDI_SUCCESS) { 1097c478bd9Sstevel@tonic-gate mutex_exit(&pci_global_mutex); 1107c478bd9Sstevel@tonic-gate pci_free_tsb(pci_p); 1117c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 1127c478bd9Sstevel@tonic-gate } 1137c478bd9Sstevel@tonic-gate cmn_p = get_pci_common_soft_state(cmn_id); 1147c478bd9Sstevel@tonic-gate cmn_p->pci_common_id = cmn_id; 1157c478bd9Sstevel@tonic-gate cmn_p->pci_common_tsb_cookie = IOMMU_TSB_COOKIE_NONE; 1167c478bd9Sstevel@tonic-gate } 1177c478bd9Sstevel@tonic-gate 1187c478bd9Sstevel@tonic-gate ASSERT((pci_p->pci_side == 0) || (pci_p->pci_side == 1)); 1197c478bd9Sstevel@tonic-gate if (cmn_p->pci_p[pci_p->pci_side]) { 1207c478bd9Sstevel@tonic-gate /* second side attach */ 1217c478bd9Sstevel@tonic-gate pci_p->pci_side = PCI_OTHER_SIDE(pci_p->pci_side); 1227c478bd9Sstevel@tonic-gate ASSERT(cmn_p->pci_p[pci_p->pci_side] == NULL); 1237c478bd9Sstevel@tonic-gate } 1247c478bd9Sstevel@tonic-gate 1257c478bd9Sstevel@tonic-gate cmn_p->pci_p[pci_p->pci_side] = pci_p; 1267c478bd9Sstevel@tonic-gate pci_p->pci_common_p = cmn_p; 1277c478bd9Sstevel@tonic-gate 1287c478bd9Sstevel@tonic-gate if (cmn_p->pci_common_refcnt == 0) 1297c478bd9Sstevel@tonic-gate cmn_p->pci_chip_id = chip_id; 1307c478bd9Sstevel@tonic-gate 1317c478bd9Sstevel@tonic-gate ib_create(pci_p); 1327c478bd9Sstevel@tonic-gate 1337c478bd9Sstevel@tonic-gate /* 1347c478bd9Sstevel@tonic-gate * The initialization of cb internal interrupts depends on ib 1357c478bd9Sstevel@tonic-gate */ 1367c478bd9Sstevel@tonic-gate if (cmn_p->pci_common_refcnt == 0) { 1377c478bd9Sstevel@tonic-gate cb_create(pci_p); 1387c478bd9Sstevel@tonic-gate cmn_p->pci_common_cb_p = pci_p->pci_cb_p; 1397c478bd9Sstevel@tonic-gate } else 1407c478bd9Sstevel@tonic-gate pci_p->pci_cb_p = cmn_p->pci_common_cb_p; 1417c478bd9Sstevel@tonic-gate 1427c478bd9Sstevel@tonic-gate iommu_create(pci_p); 1437c478bd9Sstevel@tonic-gate 1447c478bd9Sstevel@tonic-gate if (cmn_p->pci_common_refcnt == 0) { 1457c478bd9Sstevel@tonic-gate ecc_create(pci_p); 1467c478bd9Sstevel@tonic-gate cmn_p->pci_common_ecc_p = pci_p->pci_ecc_p; 1477c478bd9Sstevel@tonic-gate } else 1487c478bd9Sstevel@tonic-gate pci_p->pci_ecc_p = cmn_p->pci_common_ecc_p; 1497c478bd9Sstevel@tonic-gate 1507c478bd9Sstevel@tonic-gate pbm_create(pci_p); 1517c478bd9Sstevel@tonic-gate sc_create(pci_p); 1527c478bd9Sstevel@tonic-gate 1537c478bd9Sstevel@tonic-gate pci_fm_create(pci_p); 1547c478bd9Sstevel@tonic-gate 1557c478bd9Sstevel@tonic-gate if ((ret = pci_intr_setup(pci_p)) != DDI_SUCCESS) 1567c478bd9Sstevel@tonic-gate goto done; 1577c478bd9Sstevel@tonic-gate 1587c478bd9Sstevel@tonic-gate pci_kstat_create(pci_p); 1597c478bd9Sstevel@tonic-gate 1607c478bd9Sstevel@tonic-gate cmn_p->pci_common_attachcnt++; 1617c478bd9Sstevel@tonic-gate cmn_p->pci_common_refcnt++; 1627c478bd9Sstevel@tonic-gate done: 1637c478bd9Sstevel@tonic-gate mutex_exit(&pci_global_mutex); 1647c478bd9Sstevel@tonic-gate if (ret != DDI_SUCCESS) 1657c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "pci_obj_setup failed %x", ret); 1667c478bd9Sstevel@tonic-gate return (ret); 1677c478bd9Sstevel@tonic-gate } 1687c478bd9Sstevel@tonic-gate 1697c478bd9Sstevel@tonic-gate /* called by pci_detach() DDI_DETACH to destroy pci objects */ 1707c478bd9Sstevel@tonic-gate void 1717c478bd9Sstevel@tonic-gate pci_obj_destroy(pci_t *pci_p) 1727c478bd9Sstevel@tonic-gate { 1737c478bd9Sstevel@tonic-gate pci_common_t *cmn_p; 1747c478bd9Sstevel@tonic-gate mutex_enter(&pci_global_mutex); 1757c478bd9Sstevel@tonic-gate 1767c478bd9Sstevel@tonic-gate cmn_p = pci_p->pci_common_p; 1777c478bd9Sstevel@tonic-gate cmn_p->pci_common_refcnt--; 1787c478bd9Sstevel@tonic-gate cmn_p->pci_common_attachcnt--; 1797c478bd9Sstevel@tonic-gate 1807c478bd9Sstevel@tonic-gate pci_kstat_destroy(pci_p); 1817c478bd9Sstevel@tonic-gate 1827c478bd9Sstevel@tonic-gate /* schizo non-shared objects */ 1837c478bd9Sstevel@tonic-gate pci_fm_destroy(pci_p); 1847c478bd9Sstevel@tonic-gate 1857c478bd9Sstevel@tonic-gate sc_destroy(pci_p); 1867c478bd9Sstevel@tonic-gate pbm_destroy(pci_p); 1877c478bd9Sstevel@tonic-gate iommu_destroy(pci_p); 1887c478bd9Sstevel@tonic-gate ib_destroy(pci_p); 1897c478bd9Sstevel@tonic-gate 1907c478bd9Sstevel@tonic-gate if (cmn_p->pci_common_refcnt != 0) { 1917c478bd9Sstevel@tonic-gate pci_intr_teardown(pci_p); 1927c478bd9Sstevel@tonic-gate cmn_p->pci_p[pci_p->pci_side] = NULL; 1937c478bd9Sstevel@tonic-gate mutex_exit(&pci_global_mutex); 1947c478bd9Sstevel@tonic-gate return; 1957c478bd9Sstevel@tonic-gate } 1967c478bd9Sstevel@tonic-gate 1977c478bd9Sstevel@tonic-gate /* schizo shared objects - uses cmn_p, must be destroyed before cmn */ 1987c478bd9Sstevel@tonic-gate ecc_destroy(pci_p); 1997c478bd9Sstevel@tonic-gate cb_destroy(pci_p); 2007c478bd9Sstevel@tonic-gate 2017c478bd9Sstevel@tonic-gate free_pci_common_soft_state(cmn_p->pci_common_id); 2027c478bd9Sstevel@tonic-gate pci_intr_teardown(pci_p); 2037c478bd9Sstevel@tonic-gate mutex_exit(&pci_global_mutex); 2047c478bd9Sstevel@tonic-gate } 2057c478bd9Sstevel@tonic-gate 2067c478bd9Sstevel@tonic-gate /* called by pci_attach() DDI_RESUME to (re)initialize pci objects */ 2077c478bd9Sstevel@tonic-gate void 2087c478bd9Sstevel@tonic-gate pci_obj_resume(pci_t *pci_p) 2097c478bd9Sstevel@tonic-gate { 2107c478bd9Sstevel@tonic-gate pci_common_t *cmn_p = pci_p->pci_common_p; 2117c478bd9Sstevel@tonic-gate 2127c478bd9Sstevel@tonic-gate mutex_enter(&pci_global_mutex); 2137c478bd9Sstevel@tonic-gate 2147c478bd9Sstevel@tonic-gate ib_configure(pci_p->pci_ib_p); 2157c478bd9Sstevel@tonic-gate iommu_configure(pci_p->pci_iommu_p); 2167c478bd9Sstevel@tonic-gate 2177c478bd9Sstevel@tonic-gate if (cmn_p->pci_common_attachcnt == 0) 2187c478bd9Sstevel@tonic-gate ecc_configure(pci_p); 2197c478bd9Sstevel@tonic-gate 2207c478bd9Sstevel@tonic-gate ib_resume(pci_p->pci_ib_p); 2217c478bd9Sstevel@tonic-gate 2227c478bd9Sstevel@tonic-gate pbm_configure(pci_p->pci_pbm_p); 2237c478bd9Sstevel@tonic-gate sc_configure(pci_p->pci_sc_p); 2247c478bd9Sstevel@tonic-gate 2257c478bd9Sstevel@tonic-gate if (cmn_p->pci_common_attachcnt == 0) 2267c478bd9Sstevel@tonic-gate cb_resume(pci_p->pci_cb_p); 2277c478bd9Sstevel@tonic-gate 2287c478bd9Sstevel@tonic-gate pbm_resume(pci_p->pci_pbm_p); 2297c478bd9Sstevel@tonic-gate 2307c478bd9Sstevel@tonic-gate cmn_p->pci_common_attachcnt++; 2317c478bd9Sstevel@tonic-gate mutex_exit(&pci_global_mutex); 2327c478bd9Sstevel@tonic-gate } 2337c478bd9Sstevel@tonic-gate 2347c478bd9Sstevel@tonic-gate /* called by pci_detach() DDI_SUSPEND to suspend pci objects */ 2357c478bd9Sstevel@tonic-gate void 2367c478bd9Sstevel@tonic-gate pci_obj_suspend(pci_t *pci_p) 2377c478bd9Sstevel@tonic-gate { 2387c478bd9Sstevel@tonic-gate mutex_enter(&pci_global_mutex); 2397c478bd9Sstevel@tonic-gate 2407c478bd9Sstevel@tonic-gate pbm_suspend(pci_p->pci_pbm_p); 2417c478bd9Sstevel@tonic-gate ib_suspend(pci_p->pci_ib_p); 2427c478bd9Sstevel@tonic-gate 2437c478bd9Sstevel@tonic-gate if (!--pci_p->pci_common_p->pci_common_attachcnt) 2447c478bd9Sstevel@tonic-gate cb_suspend(pci_p->pci_cb_p); 2457c478bd9Sstevel@tonic-gate 2467c478bd9Sstevel@tonic-gate mutex_exit(&pci_global_mutex); 2477c478bd9Sstevel@tonic-gate } 2487c478bd9Sstevel@tonic-gate 2497c478bd9Sstevel@tonic-gate /* 2507c478bd9Sstevel@tonic-gate * add an additional 0x35 or 0x36 ino interrupt on platforms don't have them 2517c478bd9Sstevel@tonic-gate * This routine has multiple places that assumes interrupt takes one cell 2527c478bd9Sstevel@tonic-gate * each and cell size is same as integer size. 2537c478bd9Sstevel@tonic-gate */ 2547c478bd9Sstevel@tonic-gate static int 2557c478bd9Sstevel@tonic-gate pci_intr_setup(pci_t *pci_p) 2567c478bd9Sstevel@tonic-gate { 2577c478bd9Sstevel@tonic-gate dev_info_t *dip = pci_p->pci_dip; 2587c478bd9Sstevel@tonic-gate pbm_t *pbm_p = pci_p->pci_pbm_p; 2597c478bd9Sstevel@tonic-gate cb_t *cb_p = pci_p->pci_cb_p; 260825808ceSdduvall uint32_t *intr_buf, *new_intr_buf; 261825808ceSdduvall int intr_len, intr_cnt, ret; 2627c478bd9Sstevel@tonic-gate 263a3282898Scth if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 2647c478bd9Sstevel@tonic-gate "interrupts", (caddr_t)&intr_buf, &intr_len) != DDI_SUCCESS) 2657c478bd9Sstevel@tonic-gate cmn_err(CE_PANIC, "%s%d: no interrupts property\n", 2667c478bd9Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip)); 2677c478bd9Sstevel@tonic-gate 2687c478bd9Sstevel@tonic-gate intr_cnt = BYTES_TO_1275_CELLS(intr_len); 2697c478bd9Sstevel@tonic-gate if (intr_cnt < CBNINTR_CDMA) /* CBNINTR_CDMA is 0 based */ 2707c478bd9Sstevel@tonic-gate cmn_err(CE_PANIC, "%s%d: <%d interrupts", ddi_driver_name(dip), 2717c478bd9Sstevel@tonic-gate ddi_get_instance(dip), CBNINTR_CDMA); 2727c478bd9Sstevel@tonic-gate 2737c478bd9Sstevel@tonic-gate if (intr_cnt == CBNINTR_CDMA) 2747c478bd9Sstevel@tonic-gate intr_cnt++; 2757c478bd9Sstevel@tonic-gate 2767c478bd9Sstevel@tonic-gate new_intr_buf = kmem_alloc(CELLS_1275_TO_BYTES(intr_cnt), KM_SLEEP); 2777c478bd9Sstevel@tonic-gate bcopy(intr_buf, new_intr_buf, intr_len); 2787c478bd9Sstevel@tonic-gate kmem_free(intr_buf, intr_len); 2797c478bd9Sstevel@tonic-gate 280825808ceSdduvall new_intr_buf[CBNINTR_CDMA] = PBM_CDMA_INO_BASE + pci_p->pci_side; 2817c478bd9Sstevel@tonic-gate pci_p->pci_inos = new_intr_buf; 2827c478bd9Sstevel@tonic-gate pci_p->pci_inos_len = CELLS_1275_TO_BYTES(intr_cnt); 2837c478bd9Sstevel@tonic-gate 2847c478bd9Sstevel@tonic-gate if (ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "interrupts", 2857c478bd9Sstevel@tonic-gate (int *)new_intr_buf, intr_cnt)) 2867c478bd9Sstevel@tonic-gate cmn_err(CE_PANIC, "%s%d: cannot update interrupts property\n", 2877c478bd9Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip)); 2887c478bd9Sstevel@tonic-gate 2897c478bd9Sstevel@tonic-gate if (pci_p->pci_common_p->pci_common_refcnt == 0) { 2907c478bd9Sstevel@tonic-gate cb_p->cb_no_of_inos = intr_cnt; 2917c478bd9Sstevel@tonic-gate if (ret = cb_register_intr(pci_p)) 2927c478bd9Sstevel@tonic-gate goto teardown; 2937c478bd9Sstevel@tonic-gate if (ret = ecc_register_intr(pci_p)) 2947c478bd9Sstevel@tonic-gate goto teardown; 2957c478bd9Sstevel@tonic-gate 2967c478bd9Sstevel@tonic-gate intr_dist_add(cb_intr_dist, cb_p); 2977c478bd9Sstevel@tonic-gate cb_enable_intr(pci_p); 2987c478bd9Sstevel@tonic-gate ecc_enable_intr(pci_p); 2997c478bd9Sstevel@tonic-gate } 3007c478bd9Sstevel@tonic-gate 3017c478bd9Sstevel@tonic-gate if (CHIP_TYPE(pci_p) != PCI_CHIP_SCHIZO) 3027c478bd9Sstevel@tonic-gate pbm_p->pbm_sync_ino = pci_p->pci_inos[CBNINTR_PBM]; 3037c478bd9Sstevel@tonic-gate if (ret = pbm_register_intr(pbm_p)) { 3047c478bd9Sstevel@tonic-gate if (pci_p->pci_common_p->pci_common_refcnt == 0) 3057c478bd9Sstevel@tonic-gate intr_dist_rem(cb_intr_dist, cb_p); 3067c478bd9Sstevel@tonic-gate goto teardown; 3077c478bd9Sstevel@tonic-gate } 3087c478bd9Sstevel@tonic-gate intr_dist_add(pbm_intr_dist, pbm_p); 3097c478bd9Sstevel@tonic-gate ib_intr_enable(pci_p, pci_p->pci_inos[CBNINTR_PBM]); 3107c478bd9Sstevel@tonic-gate ib_intr_enable(pci_p, pci_p->pci_inos[CBNINTR_CDMA]); 3117c478bd9Sstevel@tonic-gate 3127c478bd9Sstevel@tonic-gate intr_dist_add_weighted(ib_intr_dist_all, pci_p->pci_ib_p); 3137c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 3147c478bd9Sstevel@tonic-gate teardown: 3157c478bd9Sstevel@tonic-gate pci_intr_teardown(pci_p); 3167c478bd9Sstevel@tonic-gate return (ret); 3177c478bd9Sstevel@tonic-gate } 3187c478bd9Sstevel@tonic-gate 3197c478bd9Sstevel@tonic-gate uint64_t 3207c478bd9Sstevel@tonic-gate pci_sc_configure(pci_t *pci_p) 3217c478bd9Sstevel@tonic-gate { 3227c478bd9Sstevel@tonic-gate int instance; 3237c478bd9Sstevel@tonic-gate dev_info_t *dip = pci_p->pci_dip; 3247c478bd9Sstevel@tonic-gate 3257c478bd9Sstevel@tonic-gate instance = ddi_get_instance(dip); 3267c478bd9Sstevel@tonic-gate if ((pci_xmits_sc_max_prf & (1 << instance)) && 3277c478bd9Sstevel@tonic-gate (CHIP_TYPE(pci_p) == PCI_CHIP_XMITS)) 3287c478bd9Sstevel@tonic-gate return (XMITS_SC_MAX_PRF); 3297c478bd9Sstevel@tonic-gate else 3307c478bd9Sstevel@tonic-gate return (0); 3317c478bd9Sstevel@tonic-gate } 3327c478bd9Sstevel@tonic-gate 3337c478bd9Sstevel@tonic-gate static void 3347c478bd9Sstevel@tonic-gate pci_schizo_cdma_sync(pbm_t *pbm_p) 3357c478bd9Sstevel@tonic-gate { 3367c478bd9Sstevel@tonic-gate pci_t *pci_p = pbm_p->pbm_pci_p; 3377c478bd9Sstevel@tonic-gate hrtime_t start_time; 338825808ceSdduvall volatile uint64_t *clr_p = ib_clear_intr_reg_addr(pci_p->pci_ib_p, 339825808ceSdduvall pci_p->pci_inos[CBNINTR_CDMA]); 3407c478bd9Sstevel@tonic-gate uint32_t fail_cnt = pci_cdma_intr_count; 3417c478bd9Sstevel@tonic-gate 3427c478bd9Sstevel@tonic-gate mutex_enter(&pbm_p->pbm_sync_mutex); 343825808ceSdduvall #ifdef PBM_CDMA_DEBUG 344825808ceSdduvall pbm_p->pbm_cdma_req_cnt++; 345825808ceSdduvall #endif /* PBM_CDMA_DEBUG */ 3467c478bd9Sstevel@tonic-gate pbm_p->pbm_cdma_flag = PBM_CDMA_PEND; 3477c478bd9Sstevel@tonic-gate IB_INO_INTR_TRIG(clr_p); 3487c478bd9Sstevel@tonic-gate wait: 3497c478bd9Sstevel@tonic-gate start_time = gethrtime(); 350825808ceSdduvall while (pbm_p->pbm_cdma_flag != PBM_CDMA_DONE) { 3517c478bd9Sstevel@tonic-gate if (gethrtime() - start_time <= pci_cdma_intr_timeout) 3527c478bd9Sstevel@tonic-gate continue; 3537c478bd9Sstevel@tonic-gate if (--fail_cnt > 0) 3547c478bd9Sstevel@tonic-gate goto wait; 3557c478bd9Sstevel@tonic-gate if (pbm_p->pbm_cdma_flag == PBM_CDMA_DONE) 3567c478bd9Sstevel@tonic-gate break; 357825808ceSdduvall cmn_err(CE_PANIC, "%s (%s): consistent dma sync timeout", 358825808ceSdduvall pbm_p->pbm_nameinst_str, pbm_p->pbm_nameaddr_str); 3597c478bd9Sstevel@tonic-gate } 360825808ceSdduvall #ifdef PBM_CDMA_DEBUG 361825808ceSdduvall if (pbm_p->pbm_cdma_flag != PBM_CDMA_DONE) 362825808ceSdduvall pbm_p->pbm_cdma_to_cnt++; 363825808ceSdduvall else { 364825808ceSdduvall start_time = gethrtime() - start_time; 365825808ceSdduvall pbm_p->pbm_cdma_success_cnt++; 366825808ceSdduvall pbm_p->pbm_cdma_latency_sum += start_time; 367825808ceSdduvall if (start_time > pbm_p->pbm_cdma_latency_max) 368825808ceSdduvall pbm_p->pbm_cdma_latency_max = start_time; 369825808ceSdduvall } 370825808ceSdduvall #endif /* PBM_CDMA_DEBUG */ 3717c478bd9Sstevel@tonic-gate mutex_exit(&pbm_p->pbm_sync_mutex); 3727c478bd9Sstevel@tonic-gate } 3737c478bd9Sstevel@tonic-gate 3747c478bd9Sstevel@tonic-gate #if !defined(lint) 3757c478bd9Sstevel@tonic-gate #include <sys/cpuvar.h> 3767c478bd9Sstevel@tonic-gate #endif 3777c478bd9Sstevel@tonic-gate 3787c478bd9Sstevel@tonic-gate #define SYNC_HW_BUSY(pa, mask) (lddphysio(pa) & (mask)) 3797c478bd9Sstevel@tonic-gate 3807c478bd9Sstevel@tonic-gate /* 3817c478bd9Sstevel@tonic-gate * Consistent DMA Sync/Flush 3827c478bd9Sstevel@tonic-gate * 3837c478bd9Sstevel@tonic-gate * XMITS and Tomatillo use multi-threaded sync/flush register. 3847c478bd9Sstevel@tonic-gate * Called from interrupt wrapper: the associated ino is used to index 3857c478bd9Sstevel@tonic-gate * the distinctive register bit. 3867c478bd9Sstevel@tonic-gate * Called from pci_dma_sync(): the bit belongs to PBM is shared 3877c478bd9Sstevel@tonic-gate * for all calls from pci_dma_sync(). Xmits requires serialization 3887c478bd9Sstevel@tonic-gate * while Tomatillo does not. 3897c478bd9Sstevel@tonic-gate */ 3907c478bd9Sstevel@tonic-gate void 3917c478bd9Sstevel@tonic-gate pci_pbm_dma_sync(pbm_t *pbm_p, ib_ino_t ino) 3927c478bd9Sstevel@tonic-gate { 3937c478bd9Sstevel@tonic-gate pci_t *pci_p = pbm_p->pbm_pci_p; 3947c478bd9Sstevel@tonic-gate hrtime_t start_time; 3957c478bd9Sstevel@tonic-gate uint64_t ino_mask, sync_reg_pa; 3967c478bd9Sstevel@tonic-gate volatile uint64_t flag_val; 3977c478bd9Sstevel@tonic-gate uint32_t locked, chip_type = CHIP_TYPE(pci_p); 3987c478bd9Sstevel@tonic-gate int i; 3997c478bd9Sstevel@tonic-gate 4007c478bd9Sstevel@tonic-gate if (chip_type == PCI_CHIP_SCHIZO) { 4017c478bd9Sstevel@tonic-gate pci_schizo_cdma_sync(pbm_p); 4027c478bd9Sstevel@tonic-gate return; 4037c478bd9Sstevel@tonic-gate } 4047c478bd9Sstevel@tonic-gate 4057c478bd9Sstevel@tonic-gate sync_reg_pa = pbm_p->pbm_sync_reg_pa; 4067c478bd9Sstevel@tonic-gate 4077c478bd9Sstevel@tonic-gate locked = 0; 4087c478bd9Sstevel@tonic-gate if (((chip_type == PCI_CHIP_XMITS) && (ino == pbm_p->pbm_sync_ino)) || 4097c478bd9Sstevel@tonic-gate pci_sync_lock) { 4107c478bd9Sstevel@tonic-gate locked = 1; 4117c478bd9Sstevel@tonic-gate mutex_enter(&pbm_p->pbm_sync_mutex); 4127c478bd9Sstevel@tonic-gate } 4137c478bd9Sstevel@tonic-gate ino_mask = 1ull << ino; 4147c478bd9Sstevel@tonic-gate stdphysio(sync_reg_pa, ino_mask); 4157c478bd9Sstevel@tonic-gate 4167c478bd9Sstevel@tonic-gate for (i = 0; i < 5; i++) { 4177c478bd9Sstevel@tonic-gate if ((flag_val = SYNC_HW_BUSY(sync_reg_pa, ino_mask)) == 0) 4187c478bd9Sstevel@tonic-gate goto done; 4197c478bd9Sstevel@tonic-gate } 4207c478bd9Sstevel@tonic-gate 4217c478bd9Sstevel@tonic-gate start_time = gethrtime(); 4227c478bd9Sstevel@tonic-gate for (; (flag_val = SYNC_HW_BUSY(sync_reg_pa, ino_mask)) != 0; i++) { 4237c478bd9Sstevel@tonic-gate if (gethrtime() - start_time > pci_sync_buf_timeout) 4247c478bd9Sstevel@tonic-gate break; 4257c478bd9Sstevel@tonic-gate } 4267c478bd9Sstevel@tonic-gate 4277c478bd9Sstevel@tonic-gate if (flag_val && SYNC_HW_BUSY(sync_reg_pa, ino_mask) && !panicstr) 428f47a9c50Smathue cmn_err(CE_PANIC, "%s: pbm dma sync %lx,%lx timeout!", 4297c478bd9Sstevel@tonic-gate pbm_p->pbm_nameaddr_str, sync_reg_pa, flag_val); 4307c478bd9Sstevel@tonic-gate done: 4317c478bd9Sstevel@tonic-gate /* optional: stdphysio(sync_reg_pa - 8, ino_mask); */ 4327c478bd9Sstevel@tonic-gate if (locked) 4337c478bd9Sstevel@tonic-gate mutex_exit(&pbm_p->pbm_sync_mutex); 4347c478bd9Sstevel@tonic-gate 4357c478bd9Sstevel@tonic-gate if (tomatillo_store_store_wrka) { 4367c478bd9Sstevel@tonic-gate #if !defined(lint) 4377c478bd9Sstevel@tonic-gate kpreempt_disable(); 4387c478bd9Sstevel@tonic-gate #endif 4397c478bd9Sstevel@tonic-gate tomatillo_store_store_order(); 4407c478bd9Sstevel@tonic-gate #if !defined(lint) 4417c478bd9Sstevel@tonic-gate kpreempt_enable(); 4427c478bd9Sstevel@tonic-gate #endif 4437c478bd9Sstevel@tonic-gate } 4447c478bd9Sstevel@tonic-gate 4457c478bd9Sstevel@tonic-gate } 4467c478bd9Sstevel@tonic-gate 4477c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 4487c478bd9Sstevel@tonic-gate void 4497c478bd9Sstevel@tonic-gate pci_fix_ranges(pci_ranges_t *rng_p, int rng_entries) 4507c478bd9Sstevel@tonic-gate { 4517c478bd9Sstevel@tonic-gate } 4527c478bd9Sstevel@tonic-gate 4537c478bd9Sstevel@tonic-gate /* 4547c478bd9Sstevel@tonic-gate * map_pci_registers 4557c478bd9Sstevel@tonic-gate * 4567c478bd9Sstevel@tonic-gate * This function is called from the attach routine to map the registers 4577c478bd9Sstevel@tonic-gate * accessed by this driver. 4587c478bd9Sstevel@tonic-gate * 4597c478bd9Sstevel@tonic-gate * used by: pci_attach() 4607c478bd9Sstevel@tonic-gate * 4617c478bd9Sstevel@tonic-gate * return value: DDI_FAILURE on failure 4627c478bd9Sstevel@tonic-gate */ 4637c478bd9Sstevel@tonic-gate int 4647c478bd9Sstevel@tonic-gate map_pci_registers(pci_t *pci_p, dev_info_t *dip) 4657c478bd9Sstevel@tonic-gate { 4667c478bd9Sstevel@tonic-gate ddi_device_acc_attr_t attr; 4677c478bd9Sstevel@tonic-gate int len; 4687c478bd9Sstevel@tonic-gate 4697c478bd9Sstevel@tonic-gate attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 4707c478bd9Sstevel@tonic-gate attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 4717c478bd9Sstevel@tonic-gate 4727c478bd9Sstevel@tonic-gate attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 47300d0963fSdilpreet 4747c478bd9Sstevel@tonic-gate /* 4757c478bd9Sstevel@tonic-gate * Register set 0 is PCI CSR Base 4767c478bd9Sstevel@tonic-gate */ 4777c478bd9Sstevel@tonic-gate if (ddi_regs_map_setup(dip, 0, &pci_p->pci_address[0], 0, 0, 4787c478bd9Sstevel@tonic-gate &attr, &pci_p->pci_ac[0]) != DDI_SUCCESS) { 4797c478bd9Sstevel@tonic-gate len = 0; 4807c478bd9Sstevel@tonic-gate goto fail; 4817c478bd9Sstevel@tonic-gate } 4827c478bd9Sstevel@tonic-gate /* 4837c478bd9Sstevel@tonic-gate * Register set 1 is Schizo CSR Base 4847c478bd9Sstevel@tonic-gate */ 4857c478bd9Sstevel@tonic-gate if (ddi_regs_map_setup(dip, 1, &pci_p->pci_address[1], 0, 0, 4867c478bd9Sstevel@tonic-gate &attr, &pci_p->pci_ac[1]) != DDI_SUCCESS) { 4877c478bd9Sstevel@tonic-gate len = 1; 4887c478bd9Sstevel@tonic-gate goto fail; 4897c478bd9Sstevel@tonic-gate } 4907c478bd9Sstevel@tonic-gate 4917c478bd9Sstevel@tonic-gate /* 4927c478bd9Sstevel@tonic-gate * The third register set contains the bridge's configuration 4937c478bd9Sstevel@tonic-gate * header. This header is at the very beginning of the bridge's 4947c478bd9Sstevel@tonic-gate * configuration space. This space has litte-endian byte order. 4957c478bd9Sstevel@tonic-gate */ 4967c478bd9Sstevel@tonic-gate attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 4977c478bd9Sstevel@tonic-gate if (ddi_regs_map_setup(dip, 2, &pci_p->pci_address[2], 0, 4987c478bd9Sstevel@tonic-gate PCI_CONF_HDR_SIZE, &attr, &pci_p->pci_ac[2]) != DDI_SUCCESS) { 4997c478bd9Sstevel@tonic-gate len = 2; 5007c478bd9Sstevel@tonic-gate goto fail; 5017c478bd9Sstevel@tonic-gate } 5027c478bd9Sstevel@tonic-gate 503a3282898Scth if (ddi_getproplen(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 5047c478bd9Sstevel@tonic-gate "reg", &len) || (len / sizeof (pci_nexus_regspec_t) < 4)) 5057c478bd9Sstevel@tonic-gate goto done; 5067c478bd9Sstevel@tonic-gate 5077c478bd9Sstevel@tonic-gate /* 5087c478bd9Sstevel@tonic-gate * The optional fourth register bank points to the 5097c478bd9Sstevel@tonic-gate * interrupt concentrator registers. 5107c478bd9Sstevel@tonic-gate */ 5117c478bd9Sstevel@tonic-gate attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 5127c478bd9Sstevel@tonic-gate if (ddi_regs_map_setup(dip, 3, &pci_p->pci_address[3], 0, 5137c478bd9Sstevel@tonic-gate 0, &attr, &pci_p->pci_ac[3]) != DDI_SUCCESS) { 5147c478bd9Sstevel@tonic-gate len = 3; 5157c478bd9Sstevel@tonic-gate goto fail; 5167c478bd9Sstevel@tonic-gate } 5177c478bd9Sstevel@tonic-gate 5187c478bd9Sstevel@tonic-gate done: 5197c478bd9Sstevel@tonic-gate DEBUG4(DBG_ATTACH, dip, "address (%p,%p,%p,%p)\n", 5207c478bd9Sstevel@tonic-gate pci_p->pci_address[0], pci_p->pci_address[1], 5217c478bd9Sstevel@tonic-gate pci_p->pci_address[2], pci_p->pci_address[3]); 5227c478bd9Sstevel@tonic-gate 5237c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 5247c478bd9Sstevel@tonic-gate 5257c478bd9Sstevel@tonic-gate 5267c478bd9Sstevel@tonic-gate fail: 5277c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "%s%d: unable to map reg entry %d\n", 5287c478bd9Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip), len); 5297c478bd9Sstevel@tonic-gate for (; len--; ddi_regs_map_free(&pci_p->pci_ac[len])); 5307c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 5317c478bd9Sstevel@tonic-gate } 5327c478bd9Sstevel@tonic-gate 5337c478bd9Sstevel@tonic-gate /* 5347c478bd9Sstevel@tonic-gate * unmap_pci_registers: 5357c478bd9Sstevel@tonic-gate * 5367c478bd9Sstevel@tonic-gate * This routine unmap the registers mapped by map_pci_registers. 5377c478bd9Sstevel@tonic-gate * 5387c478bd9Sstevel@tonic-gate * used by: pci_detach() 5397c478bd9Sstevel@tonic-gate * 5407c478bd9Sstevel@tonic-gate * return value: none 5417c478bd9Sstevel@tonic-gate */ 5427c478bd9Sstevel@tonic-gate void 5437c478bd9Sstevel@tonic-gate unmap_pci_registers(pci_t *pci_p) 5447c478bd9Sstevel@tonic-gate { 5457c478bd9Sstevel@tonic-gate int i; 5467c478bd9Sstevel@tonic-gate 5477c478bd9Sstevel@tonic-gate for (i = 0; i < 4; i++) { 5487c478bd9Sstevel@tonic-gate if (pci_p->pci_ac[i]) 5497c478bd9Sstevel@tonic-gate ddi_regs_map_free(&pci_p->pci_ac[i]); 5507c478bd9Sstevel@tonic-gate } 5517c478bd9Sstevel@tonic-gate } 5527c478bd9Sstevel@tonic-gate 5537c478bd9Sstevel@tonic-gate uint64_t 5547c478bd9Sstevel@tonic-gate ib_get_map_reg(ib_mondo_t mondo, uint32_t cpu_id) 5557c478bd9Sstevel@tonic-gate { 5567c478bd9Sstevel@tonic-gate uint32_t agent_id; 5577c478bd9Sstevel@tonic-gate uint32_t node_id; 5587c478bd9Sstevel@tonic-gate 5597c478bd9Sstevel@tonic-gate /* ensure that cpu_id is only 10 bits. */ 5607c478bd9Sstevel@tonic-gate ASSERT((cpu_id & ~0x3ff) == 0); 5617c478bd9Sstevel@tonic-gate 5627c478bd9Sstevel@tonic-gate agent_id = cpu_id & 0x1f; 5637c478bd9Sstevel@tonic-gate node_id = (cpu_id >> 5) & 0x1f; 5647c478bd9Sstevel@tonic-gate 5657c478bd9Sstevel@tonic-gate return ((mondo) | (agent_id << COMMON_INTR_MAP_REG_TID_SHIFT) | 5667c478bd9Sstevel@tonic-gate (node_id << SCHIZO_INTR_MAP_REG_NID_SHIFT) | 5677c478bd9Sstevel@tonic-gate COMMON_INTR_MAP_REG_VALID); 5687c478bd9Sstevel@tonic-gate } 5697c478bd9Sstevel@tonic-gate 5707c478bd9Sstevel@tonic-gate uint32_t 5717c478bd9Sstevel@tonic-gate ib_map_reg_get_cpu(volatile uint64_t reg) 5727c478bd9Sstevel@tonic-gate { 5737c478bd9Sstevel@tonic-gate return (((reg & COMMON_INTR_MAP_REG_TID) >> 5747c478bd9Sstevel@tonic-gate COMMON_INTR_MAP_REG_TID_SHIFT) | 5757c478bd9Sstevel@tonic-gate ((reg & SCHIZO_INTR_MAP_REG_NID) >> 5767c478bd9Sstevel@tonic-gate (SCHIZO_INTR_MAP_REG_NID_SHIFT-5))); 5777c478bd9Sstevel@tonic-gate } 5787c478bd9Sstevel@tonic-gate 5797c478bd9Sstevel@tonic-gate uint64_t * 5807c478bd9Sstevel@tonic-gate ib_intr_map_reg_addr(ib_t *ib_p, ib_ino_t ino) 5817c478bd9Sstevel@tonic-gate { 5827c478bd9Sstevel@tonic-gate /* 5837c478bd9Sstevel@tonic-gate * Schizo maps all interrupts in one contiguous area. 5847c478bd9Sstevel@tonic-gate * (PCI_CSRBase + 0x00.1000 + INO * 8). 5857c478bd9Sstevel@tonic-gate */ 5867c478bd9Sstevel@tonic-gate return ((uint64_t *)(ib_p->ib_intr_map_regs) + (ino & 0x3f)); 5877c478bd9Sstevel@tonic-gate } 5887c478bd9Sstevel@tonic-gate 5897c478bd9Sstevel@tonic-gate uint64_t * 5907c478bd9Sstevel@tonic-gate ib_clear_intr_reg_addr(ib_t *ib_p, ib_ino_t ino) /* XXX - needs work */ 5917c478bd9Sstevel@tonic-gate { 5927c478bd9Sstevel@tonic-gate /* 5937c478bd9Sstevel@tonic-gate * Schizo maps clear intr. registers in contiguous area. 5947c478bd9Sstevel@tonic-gate * (PCI_CSRBase + 0x00.1400 + INO * 8). 5957c478bd9Sstevel@tonic-gate */ 5967c478bd9Sstevel@tonic-gate return ((uint64_t *)(ib_p->ib_slot_clear_intr_regs) + (ino & 0x3f)); 5977c478bd9Sstevel@tonic-gate } 5987c478bd9Sstevel@tonic-gate 5997c478bd9Sstevel@tonic-gate /* 6007c478bd9Sstevel@tonic-gate * schizo does not have mapping register per slot, so no sharing 6017c478bd9Sstevel@tonic-gate * is done. 6027c478bd9Sstevel@tonic-gate */ 6037c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 6047c478bd9Sstevel@tonic-gate void 6057c478bd9Sstevel@tonic-gate ib_ino_map_reg_share(ib_t *ib_p, ib_ino_t ino, ib_ino_info_t *ino_p) 6067c478bd9Sstevel@tonic-gate { 6077c478bd9Sstevel@tonic-gate } 6087c478bd9Sstevel@tonic-gate 6097c478bd9Sstevel@tonic-gate /* 6107c478bd9Sstevel@tonic-gate * return true if there are interrupts using this mapping register 6117c478bd9Sstevel@tonic-gate */ 6127c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 6137c478bd9Sstevel@tonic-gate int 6147c478bd9Sstevel@tonic-gate ib_ino_map_reg_unshare(ib_t *ib_p, ib_ino_t ino, ib_ino_info_t *ino_p) 6157c478bd9Sstevel@tonic-gate { 616b0fc0e77Sgovinda return (ino_p->ino_ipil_size); 6177c478bd9Sstevel@tonic-gate } 6187c478bd9Sstevel@tonic-gate 6197c478bd9Sstevel@tonic-gate void 6207c478bd9Sstevel@tonic-gate pci_pbm_intr_dist(pbm_t *pbm_p) 6217c478bd9Sstevel@tonic-gate { 6227c478bd9Sstevel@tonic-gate pci_t *pci_p = pbm_p->pbm_pci_p; 6237c478bd9Sstevel@tonic-gate ib_t *ib_p = pci_p->pci_ib_p; 6247c478bd9Sstevel@tonic-gate ib_ino_t ino = IB_MONDO_TO_INO(pci_p->pci_inos[CBNINTR_CDMA]); 6257c478bd9Sstevel@tonic-gate 6267c478bd9Sstevel@tonic-gate mutex_enter(&pbm_p->pbm_sync_mutex); 6277c478bd9Sstevel@tonic-gate ib_intr_dist_nintr(ib_p, ino, ib_intr_map_reg_addr(ib_p, ino)); 6287c478bd9Sstevel@tonic-gate mutex_exit(&pbm_p->pbm_sync_mutex); 6297c478bd9Sstevel@tonic-gate } 6307c478bd9Sstevel@tonic-gate 6317c478bd9Sstevel@tonic-gate uint32_t 6327c478bd9Sstevel@tonic-gate pci_xlate_intr(dev_info_t *dip, dev_info_t *rdip, ib_t *ib_p, uint32_t intr) 6337c478bd9Sstevel@tonic-gate { 6347c478bd9Sstevel@tonic-gate return (IB_INO_TO_MONDO(ib_p, intr)); 6357c478bd9Sstevel@tonic-gate } 6367c478bd9Sstevel@tonic-gate 6377c478bd9Sstevel@tonic-gate 6387c478bd9Sstevel@tonic-gate /* 6397c478bd9Sstevel@tonic-gate * Return the cpuid to to be used for an ino. We have no special cpu 6407c478bd9Sstevel@tonic-gate * assignment constraints for this nexus, so just call intr_dist_cpuid(). 6417c478bd9Sstevel@tonic-gate */ 6427c478bd9Sstevel@tonic-gate /* ARGSUSED */ 6437c478bd9Sstevel@tonic-gate uint32_t 6447c478bd9Sstevel@tonic-gate pci_intr_dist_cpuid(ib_t *ib_p, ib_ino_info_t *ino_p) 6457c478bd9Sstevel@tonic-gate { 6467c478bd9Sstevel@tonic-gate return (intr_dist_cpuid()); 6477c478bd9Sstevel@tonic-gate } 6487c478bd9Sstevel@tonic-gate 6497c478bd9Sstevel@tonic-gate void 6507c478bd9Sstevel@tonic-gate pci_cb_teardown(pci_t *pci_p) 6517c478bd9Sstevel@tonic-gate { 6527c478bd9Sstevel@tonic-gate cb_t *cb_p = pci_p->pci_cb_p; 6537c478bd9Sstevel@tonic-gate uint32_t mondo; 6547c478bd9Sstevel@tonic-gate 6557c478bd9Sstevel@tonic-gate if (!pci_buserr_interrupt) 6567c478bd9Sstevel@tonic-gate return; 6577c478bd9Sstevel@tonic-gate 6587c478bd9Sstevel@tonic-gate mondo = ((pci_p->pci_cb_p->cb_ign << PCI_INO_BITS) | 6597c478bd9Sstevel@tonic-gate pci_p->pci_inos[CBNINTR_BUS_ERROR]); 6607c478bd9Sstevel@tonic-gate mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 6617c478bd9Sstevel@tonic-gate 6627c478bd9Sstevel@tonic-gate cb_disable_nintr(cb_p, CBNINTR_BUS_ERROR, IB_INTR_WAIT); 663b0fc0e77Sgovinda VERIFY(rem_ivintr(mondo, pci_pil[CBNINTR_BUS_ERROR]) == 0); 6647c478bd9Sstevel@tonic-gate } 6657c478bd9Sstevel@tonic-gate 6667c478bd9Sstevel@tonic-gate int 6677c478bd9Sstevel@tonic-gate cb_register_intr(pci_t *pci_p) 6687c478bd9Sstevel@tonic-gate { 6697c478bd9Sstevel@tonic-gate uint32_t mondo; 6707c478bd9Sstevel@tonic-gate 6717c478bd9Sstevel@tonic-gate if (!pci_buserr_interrupt) 6727c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 6737c478bd9Sstevel@tonic-gate 6747c478bd9Sstevel@tonic-gate mondo = ((pci_p->pci_cb_p->cb_ign << PCI_INO_BITS) | 6757c478bd9Sstevel@tonic-gate pci_p->pci_inos[CBNINTR_BUS_ERROR]); 6767c478bd9Sstevel@tonic-gate mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 6777c478bd9Sstevel@tonic-gate 6787c478bd9Sstevel@tonic-gate VERIFY(add_ivintr(mondo, pci_pil[CBNINTR_BUS_ERROR], 679b0fc0e77Sgovinda (intrfunc)cb_buserr_intr, (caddr_t)pci_p->pci_cb_p, 680b0fc0e77Sgovinda NULL, NULL) == 0); 6817c478bd9Sstevel@tonic-gate 6827c478bd9Sstevel@tonic-gate return (PCI_ATTACH_RETCODE(PCI_CB_OBJ, PCI_OBJ_INTR_ADD, DDI_SUCCESS)); 6837c478bd9Sstevel@tonic-gate } 6847c478bd9Sstevel@tonic-gate 6857c478bd9Sstevel@tonic-gate void 6867c478bd9Sstevel@tonic-gate cb_enable_intr(pci_t *pci_p) 6877c478bd9Sstevel@tonic-gate { 6887c478bd9Sstevel@tonic-gate if (pci_buserr_interrupt) 6897c478bd9Sstevel@tonic-gate cb_enable_nintr(pci_p, CBNINTR_BUS_ERROR); 6907c478bd9Sstevel@tonic-gate } 6917c478bd9Sstevel@tonic-gate 6927c478bd9Sstevel@tonic-gate uint64_t 6937c478bd9Sstevel@tonic-gate cb_ino_to_map_pa(cb_t *cb_p, ib_ino_t ino) 6947c478bd9Sstevel@tonic-gate { 6957c478bd9Sstevel@tonic-gate return (cb_p->cb_map_pa + (ino << 3)); 6967c478bd9Sstevel@tonic-gate } 6977c478bd9Sstevel@tonic-gate 6987c478bd9Sstevel@tonic-gate uint64_t 6997c478bd9Sstevel@tonic-gate cb_ino_to_clr_pa(cb_t *cb_p, ib_ino_t ino) 7007c478bd9Sstevel@tonic-gate { 7017c478bd9Sstevel@tonic-gate return (cb_p->cb_clr_pa + (ino << 3)); 7027c478bd9Sstevel@tonic-gate } 7037c478bd9Sstevel@tonic-gate 7047c478bd9Sstevel@tonic-gate /* 7057c478bd9Sstevel@tonic-gate * Useful on psycho only. 7067c478bd9Sstevel@tonic-gate */ 7077c478bd9Sstevel@tonic-gate int 7087c478bd9Sstevel@tonic-gate cb_remove_xintr(pci_t *pci_p, dev_info_t *dip, dev_info_t *rdip, ib_ino_t ino, 7097c478bd9Sstevel@tonic-gate ib_mondo_t mondo) 7107c478bd9Sstevel@tonic-gate { 7117c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 7127c478bd9Sstevel@tonic-gate } 7137c478bd9Sstevel@tonic-gate 7147c478bd9Sstevel@tonic-gate void 7157c478bd9Sstevel@tonic-gate pbm_configure(pbm_t *pbm_p) 7167c478bd9Sstevel@tonic-gate { 7177c478bd9Sstevel@tonic-gate pci_t *pci_p = pbm_p->pbm_pci_p; 7187c478bd9Sstevel@tonic-gate dev_info_t *dip = pbm_p->pbm_pci_p->pci_dip; 7197c478bd9Sstevel@tonic-gate int instance = ddi_get_instance(dip); 7207c478bd9Sstevel@tonic-gate uint64_t l; 7217c478bd9Sstevel@tonic-gate uint64_t mask = 1ll << instance; 7227c478bd9Sstevel@tonic-gate ushort_t s = 0; 7237c478bd9Sstevel@tonic-gate 7247c478bd9Sstevel@tonic-gate l = *pbm_p->pbm_ctrl_reg; /* save control register state */ 7257c478bd9Sstevel@tonic-gate DEBUG1(DBG_ATTACH, dip, "pbm_configure: ctrl reg=%llx\n", l); 7267c478bd9Sstevel@tonic-gate 7277c478bd9Sstevel@tonic-gate /* 7287c478bd9Sstevel@tonic-gate * See if any SERR# signals are asserted. We'll clear them later. 7297c478bd9Sstevel@tonic-gate */ 7307c478bd9Sstevel@tonic-gate if (l & COMMON_PCI_CTRL_SERR) 7317c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "%s%d: SERR asserted on pci bus\n", 7327c478bd9Sstevel@tonic-gate ddi_driver_name(dip), instance); 7337c478bd9Sstevel@tonic-gate 7347c478bd9Sstevel@tonic-gate /* 7357c478bd9Sstevel@tonic-gate * Determine if PCI bus is running at 33 or 66 mhz. 7367c478bd9Sstevel@tonic-gate */ 7377c478bd9Sstevel@tonic-gate if (l & COMMON_PCI_CTRL_SPEED) 7387c478bd9Sstevel@tonic-gate pbm_p->pbm_speed = PBM_SPEED_66MHZ; 7397c478bd9Sstevel@tonic-gate else 7407c478bd9Sstevel@tonic-gate pbm_p->pbm_speed = PBM_SPEED_33MHZ; 7417c478bd9Sstevel@tonic-gate DEBUG1(DBG_ATTACH, dip, "pbm_configure: %d mhz\n", 7427c478bd9Sstevel@tonic-gate pbm_p->pbm_speed == PBM_SPEED_66MHZ ? 66 : 33); 7437c478bd9Sstevel@tonic-gate 7447c478bd9Sstevel@tonic-gate if (pci_set_dto_value & mask) { 7457c478bd9Sstevel@tonic-gate l &= ~(3ull << SCHIZO_PCI_CTRL_PTO_SHIFT); 7467c478bd9Sstevel@tonic-gate l |= pci_dto_value << SCHIZO_PCI_CTRL_PTO_SHIFT; 7477c478bd9Sstevel@tonic-gate } else if (PCI_CHIP_ID(pci_p) >= TOMATILLO_VER_21) { 7487c478bd9Sstevel@tonic-gate l |= (3ull << SCHIZO_PCI_CTRL_PTO_SHIFT); 7497c478bd9Sstevel@tonic-gate } 7507c478bd9Sstevel@tonic-gate 7517c478bd9Sstevel@tonic-gate /* 7527c478bd9Sstevel@tonic-gate * Enable error interrupts. 7537c478bd9Sstevel@tonic-gate */ 7547c478bd9Sstevel@tonic-gate if (pci_error_intr_enable & mask) 7557c478bd9Sstevel@tonic-gate l |= SCHIZO_PCI_CTRL_ERR_INT_EN; 7567c478bd9Sstevel@tonic-gate else 7577c478bd9Sstevel@tonic-gate l &= ~SCHIZO_PCI_CTRL_ERR_INT_EN; 7587c478bd9Sstevel@tonic-gate 7597c478bd9Sstevel@tonic-gate /* 7607c478bd9Sstevel@tonic-gate * Enable pci streaming byte errors and error interrupts. 7617c478bd9Sstevel@tonic-gate */ 7627c478bd9Sstevel@tonic-gate if (pci_sbh_error_intr_enable & mask) 7637c478bd9Sstevel@tonic-gate l |= SCHIZO_PCI_CTRL_SBH_INT_EN; 7647c478bd9Sstevel@tonic-gate else 7657c478bd9Sstevel@tonic-gate l &= ~SCHIZO_PCI_CTRL_SBH_INT_EN; 7667c478bd9Sstevel@tonic-gate 7677c478bd9Sstevel@tonic-gate /* 7687c478bd9Sstevel@tonic-gate * Enable pci discard timeout error interrupt. 7697c478bd9Sstevel@tonic-gate */ 7707c478bd9Sstevel@tonic-gate if (pci_mmu_error_intr_enable & mask) 7717c478bd9Sstevel@tonic-gate l |= SCHIZO_PCI_CTRL_MMU_INT_EN; 7727c478bd9Sstevel@tonic-gate else 7737c478bd9Sstevel@tonic-gate l &= ~SCHIZO_PCI_CTRL_MMU_INT_EN; 7747c478bd9Sstevel@tonic-gate 7757c478bd9Sstevel@tonic-gate /* 7767c478bd9Sstevel@tonic-gate * Enable PCI-X error interrupts. 7777c478bd9Sstevel@tonic-gate */ 7787c478bd9Sstevel@tonic-gate if (CHIP_TYPE(pci_p) == PCI_CHIP_XMITS) { 7797c478bd9Sstevel@tonic-gate 7807c478bd9Sstevel@tonic-gate if (xmits_error_intr_enable & mask) 7817c478bd9Sstevel@tonic-gate l |= XMITS_PCI_CTRL_X_ERRINT_EN; 7827c478bd9Sstevel@tonic-gate else 7837c478bd9Sstevel@tonic-gate l &= ~XMITS_PCI_CTRL_X_ERRINT_EN; 7847c478bd9Sstevel@tonic-gate /* 7857c478bd9Sstevel@tonic-gate * Panic if older XMITS hardware is found. 7867c478bd9Sstevel@tonic-gate */ 7877c478bd9Sstevel@tonic-gate if (*pbm_p->pbm_ctrl_reg & XMITS_PCI_CTRL_X_MODE) 7887c478bd9Sstevel@tonic-gate if (PCI_CHIP_ID(pci_p) <= XMITS_VER_10) 7897c478bd9Sstevel@tonic-gate cmn_err(CE_PANIC, "%s (%s): PCIX mode " 7907c478bd9Sstevel@tonic-gate "unsupported on XMITS version %d\n", 7917c478bd9Sstevel@tonic-gate pbm_p->pbm_nameinst_str, 7927c478bd9Sstevel@tonic-gate pbm_p->pbm_nameaddr_str, CHIP_VER(pci_p)); 7937c478bd9Sstevel@tonic-gate 7947c478bd9Sstevel@tonic-gate if (xmits_perr_recov_int_enable) { 7957c478bd9Sstevel@tonic-gate if (PCI_CHIP_ID(pci_p) >= XMITS_VER_30) { 7967c478bd9Sstevel@tonic-gate uint64_t pcix_err; 7977c478bd9Sstevel@tonic-gate /* 7987c478bd9Sstevel@tonic-gate * Enable interrupt on PERR 7997c478bd9Sstevel@tonic-gate */ 8007c478bd9Sstevel@tonic-gate pcix_err = *pbm_p->pbm_pcix_err_stat_reg; 8017c478bd9Sstevel@tonic-gate pcix_err |= XMITS_PCIX_STAT_PERR_RECOV_INT_EN; 8027c478bd9Sstevel@tonic-gate pcix_err &= ~XMITS_PCIX_STAT_SERR_ON_PERR; 8037c478bd9Sstevel@tonic-gate *pbm_p->pbm_pcix_err_stat_reg = pcix_err; 8047c478bd9Sstevel@tonic-gate } 8057c478bd9Sstevel@tonic-gate } 8067c478bd9Sstevel@tonic-gate 8077c478bd9Sstevel@tonic-gate /* 8087c478bd9Sstevel@tonic-gate * Enable parity error detection on internal memories 8097c478bd9Sstevel@tonic-gate */ 8107c478bd9Sstevel@tonic-gate *pbm_p->pbm_pci_ped_ctrl = 0x3fff; 8117c478bd9Sstevel@tonic-gate } 8127c478bd9Sstevel@tonic-gate 8137c478bd9Sstevel@tonic-gate /* 8147c478bd9Sstevel@tonic-gate * Enable/disable bus parking. 8157c478bd9Sstevel@tonic-gate */ 8167c478bd9Sstevel@tonic-gate if ((pci_bus_parking_enable & mask) && 8177c478bd9Sstevel@tonic-gate !ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 8187c478bd9Sstevel@tonic-gate "no-bus-parking")) 8197c478bd9Sstevel@tonic-gate l |= SCHIZO_PCI_CTRL_ARB_PARK; 8207c478bd9Sstevel@tonic-gate else 8217c478bd9Sstevel@tonic-gate l &= ~SCHIZO_PCI_CTRL_ARB_PARK; 8227c478bd9Sstevel@tonic-gate 8237c478bd9Sstevel@tonic-gate /* 8247c478bd9Sstevel@tonic-gate * Enable arbitration. 8257c478bd9Sstevel@tonic-gate */ 8267c478bd9Sstevel@tonic-gate l |= PCI_CHIP_ID(pci_p) == XMITS_VER_10 ? XMITS10_PCI_CTRL_ARB_EN_MASK : 8277c478bd9Sstevel@tonic-gate SCHIZO_PCI_CTRL_ARB_EN_MASK; 8287c478bd9Sstevel@tonic-gate 8297c478bd9Sstevel@tonic-gate /* 8307c478bd9Sstevel@tonic-gate * Make sure SERR is clear 8317c478bd9Sstevel@tonic-gate */ 8327c478bd9Sstevel@tonic-gate l |= COMMON_PCI_CTRL_SERR; 8337c478bd9Sstevel@tonic-gate 8347c478bd9Sstevel@tonic-gate 8357c478bd9Sstevel@tonic-gate /* 8367c478bd9Sstevel@tonic-gate * Enable DTO interrupt, if desired. 8377c478bd9Sstevel@tonic-gate */ 8387c478bd9Sstevel@tonic-gate 8397c478bd9Sstevel@tonic-gate if (PCI_CHIP_ID(pci_p) <= TOMATILLO_VER_20 || (pci_dto_intr_enable & 8407c478bd9Sstevel@tonic-gate mask)) 8417c478bd9Sstevel@tonic-gate l |= (TOMATILLO_PCI_CTRL_DTO_INT_EN); 8427c478bd9Sstevel@tonic-gate else 8437c478bd9Sstevel@tonic-gate l &= ~(TOMATILLO_PCI_CTRL_DTO_INT_EN); 8447c478bd9Sstevel@tonic-gate 8457c478bd9Sstevel@tonic-gate l |= TOMATILLO_PCI_CTRL_PEN_RD_MLTPL | 8467c478bd9Sstevel@tonic-gate TOMATILLO_PCI_CTRL_PEN_RD_ONE | 8477c478bd9Sstevel@tonic-gate TOMATILLO_PCI_CTRL_PEN_RD_LINE; 8487c478bd9Sstevel@tonic-gate 8497c478bd9Sstevel@tonic-gate /* 8507c478bd9Sstevel@tonic-gate * Now finally write the control register with the appropriate value. 8517c478bd9Sstevel@tonic-gate */ 8527c478bd9Sstevel@tonic-gate DEBUG1(DBG_ATTACH, dip, "pbm_configure: ctrl reg=%llx\n", l); 8537c478bd9Sstevel@tonic-gate *pbm_p->pbm_ctrl_reg = l; 8547c478bd9Sstevel@tonic-gate 8557c478bd9Sstevel@tonic-gate /* 8567c478bd9Sstevel@tonic-gate * Enable IO Prefetch on Tomatillo 8577c478bd9Sstevel@tonic-gate */ 8587c478bd9Sstevel@tonic-gate if (CHIP_TYPE(pci_p) == PCI_CHIP_TOMATILLO) { 8597c478bd9Sstevel@tonic-gate volatile uint64_t *ioc_csr_p = pbm_p->pbm_ctrl_reg + 8607c478bd9Sstevel@tonic-gate ((TOMATILLO_IOC_CSR_OFF - 8617c478bd9Sstevel@tonic-gate SCHIZO_PCI_CTRL_REG_OFFSET) >> 3); 8627c478bd9Sstevel@tonic-gate *ioc_csr_p = TOMATILLO_WRT_PEN | 8637c478bd9Sstevel@tonic-gate (1 << TOMATILLO_POFFSET_SHIFT) | 8647c478bd9Sstevel@tonic-gate TOMATILLO_C_PEN_RD_MLTPL | 8657c478bd9Sstevel@tonic-gate TOMATILLO_C_PEN_RD_ONE | 8667c478bd9Sstevel@tonic-gate TOMATILLO_C_PEN_RD_LINE; 8677c478bd9Sstevel@tonic-gate } 8687c478bd9Sstevel@tonic-gate 8697c478bd9Sstevel@tonic-gate /* 8707c478bd9Sstevel@tonic-gate * Allow DMA write parity errors to generate an interrupt. 8717c478bd9Sstevel@tonic-gate * This is implemented on Schizo 2.5 and greater and XMITS 3.0 8727c478bd9Sstevel@tonic-gate * and greater. Setting this on earlier versions of XMITS 3.0 8737c478bd9Sstevel@tonic-gate * has no affect. 8747c478bd9Sstevel@tonic-gate */ 8757c478bd9Sstevel@tonic-gate if (((CHIP_TYPE(pci_p) == PCI_CHIP_SCHIZO) && 8767c478bd9Sstevel@tonic-gate PCI_CHIP_ID(pci_p) >= SCHIZO_VER_25) || 8777c478bd9Sstevel@tonic-gate (CHIP_TYPE(pci_p) == PCI_CHIP_XMITS)) { 8787c478bd9Sstevel@tonic-gate volatile uint64_t *pbm_icd = pbm_p->pbm_ctrl_reg + 8797c478bd9Sstevel@tonic-gate ((SCHIZO_PERF_PCI_ICD_OFFSET - 8807c478bd9Sstevel@tonic-gate SCHIZO_PCI_CTRL_REG_OFFSET) >> 3); 8817c478bd9Sstevel@tonic-gate 8827c478bd9Sstevel@tonic-gate *pbm_icd |= SCHIZO_PERF_PCI_ICD_DMAW_PARITY_INT_ENABLE; 8837c478bd9Sstevel@tonic-gate } 8847c478bd9Sstevel@tonic-gate 8857c478bd9Sstevel@tonic-gate /* 8867c478bd9Sstevel@tonic-gate * Clear any PBM errors. 8877c478bd9Sstevel@tonic-gate */ 8887c478bd9Sstevel@tonic-gate l = (SCHIZO_PCI_AFSR_E_MASK << SCHIZO_PCI_AFSR_PE_SHIFT) | 8897c478bd9Sstevel@tonic-gate (SCHIZO_PCI_AFSR_E_MASK << SCHIZO_PCI_AFSR_SE_SHIFT); 8907c478bd9Sstevel@tonic-gate *pbm_p->pbm_async_flt_status_reg = l; 8917c478bd9Sstevel@tonic-gate 8927c478bd9Sstevel@tonic-gate /* 8937c478bd9Sstevel@tonic-gate * Allow the diag register to be set based upon variable that 8947c478bd9Sstevel@tonic-gate * can be configured via /etc/system. 8957c478bd9Sstevel@tonic-gate */ 8967c478bd9Sstevel@tonic-gate l = *pbm_p->pbm_diag_reg; 8977c478bd9Sstevel@tonic-gate DEBUG1(DBG_ATTACH, dip, "pbm_configure: PCI diag reg=%llx\n", l); 8987c478bd9Sstevel@tonic-gate 8997c478bd9Sstevel@tonic-gate /* 9007c478bd9Sstevel@tonic-gate * Enable/disable retry limit. 9017c478bd9Sstevel@tonic-gate */ 9027c478bd9Sstevel@tonic-gate if (pci_retry_disable & mask) 9037c478bd9Sstevel@tonic-gate l |= COMMON_PCI_DIAG_DIS_RETRY; 9047c478bd9Sstevel@tonic-gate else 9057c478bd9Sstevel@tonic-gate l &= ~COMMON_PCI_DIAG_DIS_RETRY; 9067c478bd9Sstevel@tonic-gate 9077c478bd9Sstevel@tonic-gate /* 9087c478bd9Sstevel@tonic-gate * Enable/disable DMA write/interrupt synchronization. 9097c478bd9Sstevel@tonic-gate */ 9107c478bd9Sstevel@tonic-gate if (pci_intsync_disable & mask) 9117c478bd9Sstevel@tonic-gate l |= COMMON_PCI_DIAG_DIS_INTSYNC; 9127c478bd9Sstevel@tonic-gate else 9137c478bd9Sstevel@tonic-gate l &= ~COMMON_PCI_DIAG_DIS_INTSYNC; 9147c478bd9Sstevel@tonic-gate 9157c478bd9Sstevel@tonic-gate /* 9167c478bd9Sstevel@tonic-gate * Enable/disable retry arbitration priority. 9177c478bd9Sstevel@tonic-gate */ 9187c478bd9Sstevel@tonic-gate if (pci_enable_retry_arb & mask) 9197c478bd9Sstevel@tonic-gate l &= ~SCHIZO_PCI_DIAG_DIS_RTRY_ARB; 9207c478bd9Sstevel@tonic-gate else 9217c478bd9Sstevel@tonic-gate l |= SCHIZO_PCI_DIAG_DIS_RTRY_ARB; 9227c478bd9Sstevel@tonic-gate 9237c478bd9Sstevel@tonic-gate DEBUG1(DBG_ATTACH, dip, "pbm_configure: PCI diag reg=%llx\n", l); 9247c478bd9Sstevel@tonic-gate *pbm_p->pbm_diag_reg = l; 9257c478bd9Sstevel@tonic-gate 9267c478bd9Sstevel@tonic-gate /* 9277c478bd9Sstevel@tonic-gate * Enable SERR# and parity reporting via command register. 9287c478bd9Sstevel@tonic-gate */ 9297c478bd9Sstevel@tonic-gate s = pci_perr_enable & mask ? PCI_COMM_PARITY_DETECT : 0; 9307c478bd9Sstevel@tonic-gate s |= pci_serr_enable & mask ? PCI_COMM_SERR_ENABLE : 0; 9317c478bd9Sstevel@tonic-gate 9327c478bd9Sstevel@tonic-gate DEBUG1(DBG_ATTACH, dip, "pbm_configure: conf command reg=%x\n", s); 9337c478bd9Sstevel@tonic-gate pbm_p->pbm_config_header->ch_command_reg = s; 9347c478bd9Sstevel@tonic-gate 9357c478bd9Sstevel@tonic-gate /* 9367c478bd9Sstevel@tonic-gate * Clear error bits in configuration status register. 9377c478bd9Sstevel@tonic-gate */ 9387c478bd9Sstevel@tonic-gate s = PCI_STAT_PERROR | PCI_STAT_S_PERROR | 9397c478bd9Sstevel@tonic-gate PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB | 9407c478bd9Sstevel@tonic-gate PCI_STAT_S_TARG_AB | PCI_STAT_S_PERROR; 9417c478bd9Sstevel@tonic-gate DEBUG1(DBG_ATTACH, dip, "pbm_configure: conf status reg=%x\n", s); 9427c478bd9Sstevel@tonic-gate pbm_p->pbm_config_header->ch_status_reg = s; 9437c478bd9Sstevel@tonic-gate 9447c478bd9Sstevel@tonic-gate /* 9457c478bd9Sstevel@tonic-gate * The current versions of the obp are suppose to set the latency 9467c478bd9Sstevel@tonic-gate * timer register but do not. Bug 1234181 is open against this 9477c478bd9Sstevel@tonic-gate * problem. Until this bug is fixed we check to see if the obp 9487c478bd9Sstevel@tonic-gate * has attempted to set the latency timer register by checking 9497c478bd9Sstevel@tonic-gate * for the existence of a "latency-timer" property. 9507c478bd9Sstevel@tonic-gate */ 9517c478bd9Sstevel@tonic-gate if (pci_set_latency_timer_register) { 9527c478bd9Sstevel@tonic-gate DEBUG1(DBG_ATTACH, dip, 9537c478bd9Sstevel@tonic-gate "pbm_configure: set schizo latency timer to %x\n", 9547c478bd9Sstevel@tonic-gate pci_latency_timer); 9557c478bd9Sstevel@tonic-gate pbm_p->pbm_config_header->ch_latency_timer_reg = 9567c478bd9Sstevel@tonic-gate pci_latency_timer; 9577c478bd9Sstevel@tonic-gate } 9587c478bd9Sstevel@tonic-gate 9597c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_ANY, dip, "latency-timer", 9607c478bd9Sstevel@tonic-gate (int)pbm_p->pbm_config_header->ch_latency_timer_reg); 961810a4a70Sdanice 962810a4a70Sdanice /* 963810a4a70Sdanice * Adjust xmits_upper_retry_counter if set in /etc/system 964810a4a70Sdanice * 965810a4a70Sdanice * NOTE: current implementation resets UPPR_RTRY counter for 966810a4a70Sdanice * _all_ XMITS' PBMs and does not support tuning per PBM. 967810a4a70Sdanice */ 968810a4a70Sdanice if (CHIP_TYPE(pci_p) == PCI_CHIP_XMITS) { 969810a4a70Sdanice uint_t xurc = xmits_upper_retry_counter & 970810a4a70Sdanice XMITS_UPPER_RETRY_MASK; 971810a4a70Sdanice 972810a4a70Sdanice if (xurc) { 973810a4a70Sdanice *pbm_p->pbm_upper_retry_counter_reg = (uint64_t)xurc; 974810a4a70Sdanice DEBUG1(DBG_ATTACH, dip, "pbm_configure: Setting XMITS" 975810a4a70Sdanice " uppr_rtry counter = 0x%lx\n", 976810a4a70Sdanice *pbm_p->pbm_upper_retry_counter_reg); 977810a4a70Sdanice } 978810a4a70Sdanice } 9797c478bd9Sstevel@tonic-gate } 9807c478bd9Sstevel@tonic-gate 9817c478bd9Sstevel@tonic-gate uint_t 9827c478bd9Sstevel@tonic-gate pbm_disable_pci_errors(pbm_t *pbm_p) 9837c478bd9Sstevel@tonic-gate { 9847c478bd9Sstevel@tonic-gate pci_t *pci_p = pbm_p->pbm_pci_p; 9857c478bd9Sstevel@tonic-gate ib_t *ib_p = pci_p->pci_ib_p; 9867c478bd9Sstevel@tonic-gate 9877c478bd9Sstevel@tonic-gate /* 9887c478bd9Sstevel@tonic-gate * Disable error and streaming byte hole interrupts via the 9897c478bd9Sstevel@tonic-gate * PBM control register. 9907c478bd9Sstevel@tonic-gate */ 9917c478bd9Sstevel@tonic-gate *pbm_p->pbm_ctrl_reg &= 9927c478bd9Sstevel@tonic-gate ~(SCHIZO_PCI_CTRL_ERR_INT_EN | SCHIZO_PCI_CTRL_SBH_INT_EN | 9937c478bd9Sstevel@tonic-gate SCHIZO_PCI_CTRL_MMU_INT_EN); 9947c478bd9Sstevel@tonic-gate 9957c478bd9Sstevel@tonic-gate /* 9967c478bd9Sstevel@tonic-gate * Disable error interrupts via the interrupt mapping register. 9977c478bd9Sstevel@tonic-gate */ 9987c478bd9Sstevel@tonic-gate ib_intr_disable(ib_p, pci_p->pci_inos[CBNINTR_PBM], IB_INTR_NOWAIT); 9997c478bd9Sstevel@tonic-gate return (BF_NONE); 10007c478bd9Sstevel@tonic-gate } 10017c478bd9Sstevel@tonic-gate 10027c478bd9Sstevel@tonic-gate /* 10037c478bd9Sstevel@tonic-gate * Layout of the dvma context bucket bitmap entry: 10047c478bd9Sstevel@tonic-gate * 10057c478bd9Sstevel@tonic-gate * 63 - 56 55 - 0 10067c478bd9Sstevel@tonic-gate * 8-bit lock 56-bit, each represent one context 10077c478bd9Sstevel@tonic-gate * DCB_LOCK_BITS DCB_BMAP_BITS 10087c478bd9Sstevel@tonic-gate */ 10097c478bd9Sstevel@tonic-gate #define DCB_LOCK_BITS 8 10107c478bd9Sstevel@tonic-gate #define DCB_BMAP_BITS (64 - DCB_LOCK_BITS) 10117c478bd9Sstevel@tonic-gate 10127c478bd9Sstevel@tonic-gate dvma_context_t 10137c478bd9Sstevel@tonic-gate pci_iommu_get_dvma_context(iommu_t *iommu_p, dvma_addr_t dvma_pg_index) 10147c478bd9Sstevel@tonic-gate { 10157c478bd9Sstevel@tonic-gate dvma_context_t ctx; 10167c478bd9Sstevel@tonic-gate int i = (dvma_pg_index >> 6) & 0x1f; /* 5 bit index within bucket */ 10177c478bd9Sstevel@tonic-gate uint64_t ctx_mask, test = 1ull << i; 10187c478bd9Sstevel@tonic-gate uint32_t bucket_no = dvma_pg_index & 0x3f; 10197c478bd9Sstevel@tonic-gate uint64_t *bucket_ptr = iommu_p->iommu_ctx_bitmap + bucket_no; 10207c478bd9Sstevel@tonic-gate 10217c478bd9Sstevel@tonic-gate uint32_t spl = ddi_enter_critical(); /* block interrupts */ 10227c478bd9Sstevel@tonic-gate if (ldstub((uint8_t *)bucket_ptr)) { /* try lock */ 10237c478bd9Sstevel@tonic-gate ddi_exit_critical(spl); /* unblock interrupt */ 10247c478bd9Sstevel@tonic-gate pci_iommu_ctx_lock_failure++; 10257c478bd9Sstevel@tonic-gate return (0); 10267c478bd9Sstevel@tonic-gate } 10277c478bd9Sstevel@tonic-gate 10287c478bd9Sstevel@tonic-gate /* clear lock bits */ 10297c478bd9Sstevel@tonic-gate ctx_mask = (*bucket_ptr << DCB_LOCK_BITS) >> DCB_LOCK_BITS; 10307c478bd9Sstevel@tonic-gate ASSERT(*bucket_ptr >> DCB_BMAP_BITS == 0xff); 10317c478bd9Sstevel@tonic-gate ASSERT(ctx_mask >> DCB_BMAP_BITS == 0); 10327c478bd9Sstevel@tonic-gate 10337c478bd9Sstevel@tonic-gate if (ctx_mask & test) /* quick check i bit */ 10347c478bd9Sstevel@tonic-gate for (i = 0, test = 1ull; test & ctx_mask; test <<= 1, i++); 10357c478bd9Sstevel@tonic-gate if (i < DCB_BMAP_BITS) 10367c478bd9Sstevel@tonic-gate ctx_mask |= test; 10377c478bd9Sstevel@tonic-gate *bucket_ptr = ctx_mask; /* unlock */ 10387c478bd9Sstevel@tonic-gate ddi_exit_critical(spl); /* unblock interrupts */ 10397c478bd9Sstevel@tonic-gate 10407c478bd9Sstevel@tonic-gate ctx = i < DCB_BMAP_BITS ? (bucket_no << 6) | i : 0; 10417c478bd9Sstevel@tonic-gate DEBUG3(DBG_DMA_MAP, iommu_p->iommu_pci_p->pci_dip, 10427c478bd9Sstevel@tonic-gate "get_dvma_context: ctx_mask=0x%x.%x ctx=0x%x\n", 10437c478bd9Sstevel@tonic-gate (uint32_t)(ctx_mask >> 32), (uint32_t)ctx_mask, ctx); 10447c478bd9Sstevel@tonic-gate return (ctx); 10457c478bd9Sstevel@tonic-gate } 10467c478bd9Sstevel@tonic-gate 10477c478bd9Sstevel@tonic-gate void 10487c478bd9Sstevel@tonic-gate pci_iommu_free_dvma_context(iommu_t *iommu_p, dvma_context_t ctx) 10497c478bd9Sstevel@tonic-gate { 10507c478bd9Sstevel@tonic-gate uint64_t ctx_mask; 10517c478bd9Sstevel@tonic-gate uint32_t spl, bucket_no = ctx >> 6; 10527c478bd9Sstevel@tonic-gate int bit_no = ctx & 0x3f; 10537c478bd9Sstevel@tonic-gate uint64_t *bucket_ptr = iommu_p->iommu_ctx_bitmap + bucket_no; 10547c478bd9Sstevel@tonic-gate 10557c478bd9Sstevel@tonic-gate DEBUG1(DBG_DMA_MAP, iommu_p->iommu_pci_p->pci_dip, 10567c478bd9Sstevel@tonic-gate "free_dvma_context: ctx=0x%x\n", ctx); 10577c478bd9Sstevel@tonic-gate 10587c478bd9Sstevel@tonic-gate spl = ddi_enter_critical(); /* block interrupts */ 10597c478bd9Sstevel@tonic-gate while (ldstub((uint8_t *)bucket_ptr)); /* spin lock */ 10607c478bd9Sstevel@tonic-gate ctx_mask = (*bucket_ptr << DCB_LOCK_BITS) >> DCB_LOCK_BITS; 10617c478bd9Sstevel@tonic-gate /* clear lock bits */ 10627c478bd9Sstevel@tonic-gate ASSERT(ctx_mask & (1ull << bit_no)); 10637c478bd9Sstevel@tonic-gate *bucket_ptr = ctx_mask ^ (1ull << bit_no); /* clear & unlock */ 10647c478bd9Sstevel@tonic-gate ddi_exit_critical(spl); /* unblock interrupt */ 10657c478bd9Sstevel@tonic-gate } 10667c478bd9Sstevel@tonic-gate 10677c478bd9Sstevel@tonic-gate int 10687c478bd9Sstevel@tonic-gate pci_sc_ctx_inv(dev_info_t *dip, sc_t *sc_p, ddi_dma_impl_t *mp) 10697c478bd9Sstevel@tonic-gate { 10707c478bd9Sstevel@tonic-gate dvma_context_t ctx = MP2CTX(mp); 10717c478bd9Sstevel@tonic-gate volatile uint64_t *reg_addr = sc_p->sc_ctx_match_reg + ctx; 10727c478bd9Sstevel@tonic-gate uint64_t matchreg; 10737c478bd9Sstevel@tonic-gate 10747c478bd9Sstevel@tonic-gate if (!*reg_addr) { 10757c478bd9Sstevel@tonic-gate DEBUG1(DBG_SC, dip, "ctx=%x no match\n", ctx); 10767c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 10777c478bd9Sstevel@tonic-gate } 10787c478bd9Sstevel@tonic-gate 10797c478bd9Sstevel@tonic-gate *sc_p->sc_ctx_invl_reg = ctx; /* 1st flush write */ 10807c478bd9Sstevel@tonic-gate matchreg = *reg_addr; /* re-fetch after 1st flush */ 10817c478bd9Sstevel@tonic-gate if (!matchreg) 10827c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 10837c478bd9Sstevel@tonic-gate 10847c478bd9Sstevel@tonic-gate matchreg = (matchreg << SC_ENT_SHIFT) >> SC_ENT_SHIFT; /* low 16-bit */ 10857c478bd9Sstevel@tonic-gate do { 10867c478bd9Sstevel@tonic-gate if (matchreg & 1) 10877c478bd9Sstevel@tonic-gate *sc_p->sc_ctx_invl_reg = ctx; 10887c478bd9Sstevel@tonic-gate matchreg >>= 1; 10897c478bd9Sstevel@tonic-gate } while (matchreg); 10907c478bd9Sstevel@tonic-gate 10917c478bd9Sstevel@tonic-gate if (pci_ctx_no_compat || !*reg_addr) /* compat: active ctx flush */ 10927c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 10937c478bd9Sstevel@tonic-gate 10947c478bd9Sstevel@tonic-gate pci_ctx_unsuccess_count++; 10957c478bd9Sstevel@tonic-gate if (pci_ctx_flush_warn) 10967c478bd9Sstevel@tonic-gate cmn_err(pci_ctx_flush_warn, "%s%d: ctx flush unsuccessful\n", 10977c478bd9Sstevel@tonic-gate NAMEINST(dip)); 10987c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 10997c478bd9Sstevel@tonic-gate } 11007c478bd9Sstevel@tonic-gate 11017c478bd9Sstevel@tonic-gate void 11027c478bd9Sstevel@tonic-gate pci_cb_setup(pci_t *pci_p) 11037c478bd9Sstevel@tonic-gate { 11047c478bd9Sstevel@tonic-gate dev_info_t *dip = pci_p->pci_dip; 11057c478bd9Sstevel@tonic-gate cb_t *cb_p = pci_p->pci_cb_p; 11067c478bd9Sstevel@tonic-gate uint64_t pa; 11077c478bd9Sstevel@tonic-gate uint32_t chip_id = PCI_CHIP_ID(pci_p); 11087c478bd9Sstevel@tonic-gate DEBUG1(DBG_ATTACH, dip, "cb_create: chip id %d\n", chip_id); 11097c478bd9Sstevel@tonic-gate 11107c478bd9Sstevel@tonic-gate if (CHIP_TYPE(pci_p) == PCI_CHIP_TOMATILLO) { 11117c478bd9Sstevel@tonic-gate if ((!tm_mtlb_gc_manual) && 11127c478bd9Sstevel@tonic-gate (PCI_CHIP_ID(pci_p) <= TOMATILLO_VER_24)) 11137c478bd9Sstevel@tonic-gate tm_mtlb_gc = 1; 11147c478bd9Sstevel@tonic-gate 11157c478bd9Sstevel@tonic-gate if (PCI_CHIP_ID(pci_p) <= TOMATILLO_VER_23) { 11167c478bd9Sstevel@tonic-gate tomatillo_store_store_wrka = 1; 11177c478bd9Sstevel@tonic-gate tomatillo_disallow_bypass = 1; 11187c478bd9Sstevel@tonic-gate if (pci_spurintr_msgs == PCI_SPURINTR_MSG_DEFAULT) 11197c478bd9Sstevel@tonic-gate pci_spurintr_msgs = 0; 11207c478bd9Sstevel@tonic-gate } 11217c478bd9Sstevel@tonic-gate } 11227c478bd9Sstevel@tonic-gate 11237c478bd9Sstevel@tonic-gate if (chip_id == TOMATILLO_VER_20 || chip_id == TOMATILLO_VER_21) 11247c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "Unsupported Tomatillo rev (%x)", chip_id); 11257c478bd9Sstevel@tonic-gate 11267c478bd9Sstevel@tonic-gate if (chip_id < SCHIZO_VER_23) 11277c478bd9Sstevel@tonic-gate pci_ctx_no_active_flush = 1; 11287c478bd9Sstevel@tonic-gate 11297c478bd9Sstevel@tonic-gate cb_p->cb_node_id = PCI_ID_TO_NODEID(pci_p->pci_id); 11307c478bd9Sstevel@tonic-gate cb_p->cb_ign = PCI_ID_TO_IGN(pci_p->pci_id); 11317c478bd9Sstevel@tonic-gate 11327c478bd9Sstevel@tonic-gate /* 11337c478bd9Sstevel@tonic-gate * schizo control status reg bank is on the 2nd "reg" property entry 11347c478bd9Sstevel@tonic-gate * interrupt mapping/clear/state regs are on the 1st "reg" entry. 11357c478bd9Sstevel@tonic-gate * 11367c478bd9Sstevel@tonic-gate * ALL internal interrupts except pbm interrupts are shared by both 11377c478bd9Sstevel@tonic-gate * sides, 1st-side-attached is used as *the* owner. 11387c478bd9Sstevel@tonic-gate */ 11397c478bd9Sstevel@tonic-gate pa = (uint64_t)hat_getpfnum(kas.a_hat, pci_p->pci_address[1]); 11407c478bd9Sstevel@tonic-gate cb_p->cb_base_pa = pa << MMU_PAGESHIFT; 11417c478bd9Sstevel@tonic-gate 11427c478bd9Sstevel@tonic-gate pa = pci_p->pci_address[3] ? 11437c478bd9Sstevel@tonic-gate (uint64_t)hat_getpfnum(kas.a_hat, pci_p->pci_address[3]) : 0; 11447c478bd9Sstevel@tonic-gate cb_p->cb_icbase_pa = (pa == PFN_INVALID) ? 0 : pa << MMU_PAGESHIFT; 11457c478bd9Sstevel@tonic-gate 11467c478bd9Sstevel@tonic-gate pa = (uint64_t)hat_getpfnum(kas.a_hat, pci_p->pci_address[0]) 11477c478bd9Sstevel@tonic-gate << MMU_PAGESHIFT; 11487c478bd9Sstevel@tonic-gate cb_p->cb_map_pa = pa + SCHIZO_IB_INTR_MAP_REG_OFFSET; 11497c478bd9Sstevel@tonic-gate cb_p->cb_clr_pa = pa + SCHIZO_IB_CLEAR_INTR_REG_OFFSET; 11507c478bd9Sstevel@tonic-gate cb_p->cb_obsta_pa = pa + COMMON_IB_OBIO_INTR_STATE_DIAG_REG; 11517c478bd9Sstevel@tonic-gate } 11527c478bd9Sstevel@tonic-gate 11537c478bd9Sstevel@tonic-gate void 11547c478bd9Sstevel@tonic-gate pci_ecc_setup(ecc_t *ecc_p) 11557c478bd9Sstevel@tonic-gate { 11567c478bd9Sstevel@tonic-gate ecc_p->ecc_ue.ecc_errpndg_mask = SCHIZO_ECC_UE_AFSR_ERRPNDG; 11577c478bd9Sstevel@tonic-gate ecc_p->ecc_ue.ecc_offset_mask = SCHIZO_ECC_UE_AFSR_QW_OFFSET; 11587c478bd9Sstevel@tonic-gate ecc_p->ecc_ue.ecc_offset_shift = SCHIZO_ECC_UE_AFSR_QW_OFFSET_SHIFT; 11597c478bd9Sstevel@tonic-gate ecc_p->ecc_ue.ecc_size_log2 = 4; 11607c478bd9Sstevel@tonic-gate 11617c478bd9Sstevel@tonic-gate ecc_p->ecc_ce.ecc_errpndg_mask = SCHIZO_ECC_CE_AFSR_ERRPNDG; 11627c478bd9Sstevel@tonic-gate ecc_p->ecc_ce.ecc_offset_mask = SCHIZO_ECC_CE_AFSR_QW_OFFSET; 11637c478bd9Sstevel@tonic-gate ecc_p->ecc_ce.ecc_offset_shift = SCHIZO_ECC_CE_AFSR_QW_OFFSET_SHIFT; 11647c478bd9Sstevel@tonic-gate ecc_p->ecc_ce.ecc_size_log2 = 4; 11657c478bd9Sstevel@tonic-gate } 11667c478bd9Sstevel@tonic-gate 11677c478bd9Sstevel@tonic-gate ushort_t 11687c478bd9Sstevel@tonic-gate pci_ecc_get_synd(uint64_t afsr) 11697c478bd9Sstevel@tonic-gate { 11707c478bd9Sstevel@tonic-gate return ((ushort_t)((afsr & SCHIZO_ECC_CE_AFSR_SYND) >> 11717c478bd9Sstevel@tonic-gate SCHIZO_ECC_CE_AFSR_SYND_SHIFT)); 11727c478bd9Sstevel@tonic-gate } 11737c478bd9Sstevel@tonic-gate 11747c478bd9Sstevel@tonic-gate /* 11757c478bd9Sstevel@tonic-gate * overwrite dvma end address (only on virtual-dma systems) 11767c478bd9Sstevel@tonic-gate * initialize tsb size 11777c478bd9Sstevel@tonic-gate * reset context bits 11787c478bd9Sstevel@tonic-gate * return: IOMMU CSR bank base address (VA) 11797c478bd9Sstevel@tonic-gate */ 11807c478bd9Sstevel@tonic-gate 11817c478bd9Sstevel@tonic-gate uintptr_t 11827c478bd9Sstevel@tonic-gate pci_iommu_setup(iommu_t *iommu_p) 11837c478bd9Sstevel@tonic-gate { 11847c478bd9Sstevel@tonic-gate pci_dvma_range_prop_t *dvma_prop; 11857c478bd9Sstevel@tonic-gate int dvma_prop_len; 11867c478bd9Sstevel@tonic-gate 11877c478bd9Sstevel@tonic-gate uintptr_t a; 11887c478bd9Sstevel@tonic-gate pci_t *pci_p = iommu_p->iommu_pci_p; 11897c478bd9Sstevel@tonic-gate dev_info_t *dip = pci_p->pci_dip; 11907c478bd9Sstevel@tonic-gate uint_t tsb_size = iommu_tsb_cookie_to_size(pci_p->pci_tsb_cookie); 119101a91d29Ssuha uint_t tsb_size_prop; 11927c478bd9Sstevel@tonic-gate 11937c478bd9Sstevel@tonic-gate /* 11947c478bd9Sstevel@tonic-gate * Initializations for Tomatillo's micro TLB bug. errata #82 11957c478bd9Sstevel@tonic-gate */ 11967c478bd9Sstevel@tonic-gate if (tm_mtlb_gc) { 11977c478bd9Sstevel@tonic-gate iommu_p->iommu_mtlb_nreq = 0; 11987c478bd9Sstevel@tonic-gate iommu_p->iommu_mtlb_npgs = 0; 11997c478bd9Sstevel@tonic-gate iommu_p->iommu_mtlb_maxpgs = tm_mtlb_maxpgs; 12007c478bd9Sstevel@tonic-gate iommu_p->iommu_mtlb_req_p = (dvma_unbind_req_t *) 12017c478bd9Sstevel@tonic-gate kmem_zalloc(sizeof (dvma_unbind_req_t) * 12027c478bd9Sstevel@tonic-gate (tm_mtlb_maxpgs + 1), KM_SLEEP); 12037c478bd9Sstevel@tonic-gate mutex_init(&iommu_p->iommu_mtlb_lock, NULL, MUTEX_DRIVER, NULL); 12047c478bd9Sstevel@tonic-gate } 12057c478bd9Sstevel@tonic-gate 12067c478bd9Sstevel@tonic-gate if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 12077c478bd9Sstevel@tonic-gate "virtual-dma", (caddr_t)&dvma_prop, &dvma_prop_len) != 12087c478bd9Sstevel@tonic-gate DDI_PROP_SUCCESS) 12097c478bd9Sstevel@tonic-gate goto tsb_done; 12107c478bd9Sstevel@tonic-gate 12117c478bd9Sstevel@tonic-gate if (dvma_prop_len != sizeof (pci_dvma_range_prop_t)) { 12127c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "%s%d: invalid virtual-dma property", 12137c478bd9Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip)); 12147c478bd9Sstevel@tonic-gate goto tsb_end; 12157c478bd9Sstevel@tonic-gate } 12167c478bd9Sstevel@tonic-gate iommu_p->iommu_dvma_end = dvma_prop->dvma_base + 12177c478bd9Sstevel@tonic-gate (dvma_prop->dvma_len - 1); 121801a91d29Ssuha tsb_size_prop = IOMMU_BTOP(dvma_prop->dvma_len) * sizeof (uint64_t); 121901a91d29Ssuha tsb_size = MIN(tsb_size_prop, tsb_size); 12207c478bd9Sstevel@tonic-gate tsb_end: 12217c478bd9Sstevel@tonic-gate kmem_free(dvma_prop, dvma_prop_len); 12227c478bd9Sstevel@tonic-gate tsb_done: 12237c478bd9Sstevel@tonic-gate iommu_p->iommu_tsb_size = iommu_tsb_size_encode(tsb_size); 12247c478bd9Sstevel@tonic-gate iommu_p->iommu_ctx_bitmap = 12257c478bd9Sstevel@tonic-gate kmem_zalloc(IOMMU_CTX_BITMAP_SIZE, KM_SLEEP); 12267c478bd9Sstevel@tonic-gate *iommu_p->iommu_ctx_bitmap = 1ull; /* reserve context 0 */ 12277c478bd9Sstevel@tonic-gate 12287c478bd9Sstevel@tonic-gate /* 12297c478bd9Sstevel@tonic-gate * Determine the virtual address of the register block 12307c478bd9Sstevel@tonic-gate * containing the iommu control registers and determine 12317c478bd9Sstevel@tonic-gate * the virtual address of schizo specific iommu registers. 12327c478bd9Sstevel@tonic-gate */ 12337c478bd9Sstevel@tonic-gate a = (uintptr_t)pci_p->pci_address[0]; 12347c478bd9Sstevel@tonic-gate iommu_p->iommu_flush_ctx_reg = 12357c478bd9Sstevel@tonic-gate (uint64_t *)(a + SCHIZO_IOMMU_FLUSH_CTX_REG_OFFSET); 12367c478bd9Sstevel@tonic-gate if (CHIP_TYPE(pci_p) == PCI_CHIP_TOMATILLO) 12377c478bd9Sstevel@tonic-gate iommu_p->iommu_tfar_reg = 12387c478bd9Sstevel@tonic-gate (uint64_t *)(a + TOMATILLO_IOMMU_ERR_TFAR_OFFSET); 12397c478bd9Sstevel@tonic-gate return (a); /* PCICSRBase */ 12407c478bd9Sstevel@tonic-gate } 12417c478bd9Sstevel@tonic-gate 12427c478bd9Sstevel@tonic-gate void 12437c478bd9Sstevel@tonic-gate pci_iommu_teardown(iommu_t *iommu_p) 12447c478bd9Sstevel@tonic-gate { 12457c478bd9Sstevel@tonic-gate if (pci_use_contexts) 12467c478bd9Sstevel@tonic-gate iommu_ctx_free(iommu_p); 12477c478bd9Sstevel@tonic-gate if (iommu_p->iommu_mtlb_req_p) { 12487c478bd9Sstevel@tonic-gate kmem_free(iommu_p->iommu_mtlb_req_p, 12497c478bd9Sstevel@tonic-gate sizeof (dvma_unbind_req_t) * (tm_mtlb_maxpgs + 1)); 12507c478bd9Sstevel@tonic-gate mutex_destroy(&iommu_p->iommu_mtlb_lock); 12517c478bd9Sstevel@tonic-gate iommu_p->iommu_mtlb_req_p = NULL; 12527c478bd9Sstevel@tonic-gate iommu_p->iommu_mtlb_nreq = 0; 12537c478bd9Sstevel@tonic-gate iommu_p->iommu_mtlb_npgs = iommu_p->iommu_mtlb_maxpgs = 0; 12547c478bd9Sstevel@tonic-gate } 12557c478bd9Sstevel@tonic-gate } 12567c478bd9Sstevel@tonic-gate 12577c478bd9Sstevel@tonic-gate uintptr_t 12587c478bd9Sstevel@tonic-gate get_pbm_reg_base(pci_t *pci_p) 12597c478bd9Sstevel@tonic-gate { 12607c478bd9Sstevel@tonic-gate return ((uintptr_t) 12617c478bd9Sstevel@tonic-gate (pci_p->pci_address[0] + SCHIZO_PCI_CTRL_REG_OFFSET)); 12627c478bd9Sstevel@tonic-gate } 12637c478bd9Sstevel@tonic-gate 12647c478bd9Sstevel@tonic-gate /* ARGSUSED */ 12657c478bd9Sstevel@tonic-gate static boolean_t 12667c478bd9Sstevel@tonic-gate pci_pbm_panic_callb(void *arg, int code) 12677c478bd9Sstevel@tonic-gate { 12687c478bd9Sstevel@tonic-gate pbm_t *pbm_p = (pbm_t *)arg; 12697c478bd9Sstevel@tonic-gate volatile uint64_t *ctrl_reg_p; 12707c478bd9Sstevel@tonic-gate 12717c478bd9Sstevel@tonic-gate if (pbm_p->pbm_quiesce_count > 0) { 12727c478bd9Sstevel@tonic-gate ctrl_reg_p = pbm_p->pbm_ctrl_reg; 12737c478bd9Sstevel@tonic-gate *ctrl_reg_p = pbm_p->pbm_saved_ctrl_reg; 12747c478bd9Sstevel@tonic-gate } 12757c478bd9Sstevel@tonic-gate 12767c478bd9Sstevel@tonic-gate return (B_TRUE); 12777c478bd9Sstevel@tonic-gate } 12787c478bd9Sstevel@tonic-gate 12797c478bd9Sstevel@tonic-gate static boolean_t 12807c478bd9Sstevel@tonic-gate pci_pbm_debug_callb(void *arg, int code) 12817c478bd9Sstevel@tonic-gate { 12827c478bd9Sstevel@tonic-gate pbm_t *pbm_p = (pbm_t *)arg; 12837c478bd9Sstevel@tonic-gate volatile uint64_t *ctrl_reg_p; 12847c478bd9Sstevel@tonic-gate uint64_t ctrl_reg; 12857c478bd9Sstevel@tonic-gate 12867c478bd9Sstevel@tonic-gate if (pbm_p->pbm_quiesce_count > 0) { 12877c478bd9Sstevel@tonic-gate ctrl_reg_p = pbm_p->pbm_ctrl_reg; 12887c478bd9Sstevel@tonic-gate if (code == 0) { 12897c478bd9Sstevel@tonic-gate *ctrl_reg_p = pbm_p->pbm_saved_ctrl_reg; 12907c478bd9Sstevel@tonic-gate } else { 12917c478bd9Sstevel@tonic-gate ctrl_reg = pbm_p->pbm_saved_ctrl_reg; 12927c478bd9Sstevel@tonic-gate ctrl_reg &= ~(SCHIZO_PCI_CTRL_ARB_EN_MASK | 12937c478bd9Sstevel@tonic-gate SCHIZO_PCI_CTRL_ARB_PARK); 12947c478bd9Sstevel@tonic-gate *ctrl_reg_p = ctrl_reg; 12957c478bd9Sstevel@tonic-gate } 12967c478bd9Sstevel@tonic-gate } 12977c478bd9Sstevel@tonic-gate 12987c478bd9Sstevel@tonic-gate return (B_TRUE); 12997c478bd9Sstevel@tonic-gate } 13007c478bd9Sstevel@tonic-gate 13017c478bd9Sstevel@tonic-gate void 13027c478bd9Sstevel@tonic-gate pci_pbm_setup(pbm_t *pbm_p) 13037c478bd9Sstevel@tonic-gate { 13047c478bd9Sstevel@tonic-gate pci_t *pci_p = pbm_p->pbm_pci_p; 13057c478bd9Sstevel@tonic-gate caddr_t a = pci_p->pci_address[0]; /* PBM block base VA */ 13067c478bd9Sstevel@tonic-gate uint64_t pa = va_to_pa(a); 13077c478bd9Sstevel@tonic-gate extern int segkmem_reloc; 13087c478bd9Sstevel@tonic-gate 13097c478bd9Sstevel@tonic-gate mutex_init(&pbm_p->pbm_sync_mutex, NULL, MUTEX_DRIVER, 13107c478bd9Sstevel@tonic-gate (void *)ipltospl(XCALL_PIL)); 13117c478bd9Sstevel@tonic-gate 13127c478bd9Sstevel@tonic-gate pbm_p->pbm_config_header = (config_header_t *)pci_p->pci_address[2]; 13137c478bd9Sstevel@tonic-gate pbm_p->pbm_ctrl_reg = (uint64_t *)(a + SCHIZO_PCI_CTRL_REG_OFFSET); 13147c478bd9Sstevel@tonic-gate pbm_p->pbm_diag_reg = (uint64_t *)(a + SCHIZO_PCI_DIAG_REG_OFFSET); 13157c478bd9Sstevel@tonic-gate pbm_p->pbm_async_flt_status_reg = 13167c478bd9Sstevel@tonic-gate (uint64_t *)(a + SCHIZO_PCI_ASYNC_FLT_STATUS_REG_OFFSET); 13177c478bd9Sstevel@tonic-gate pbm_p->pbm_async_flt_addr_reg = 13187c478bd9Sstevel@tonic-gate (uint64_t *)(a + SCHIZO_PCI_ASYNC_FLT_ADDR_REG_OFFSET); 13197c478bd9Sstevel@tonic-gate pbm_p->pbm_estar_reg = (uint64_t *)(a + SCHIZO_PCI_ESTAR_REG_OFFSET); 13207c478bd9Sstevel@tonic-gate pbm_p->pbm_pcix_err_stat_reg = (uint64_t *)(a + 13217c478bd9Sstevel@tonic-gate XMITS_PCI_X_ERROR_STATUS_REG_OFFSET); 13227c478bd9Sstevel@tonic-gate pbm_p->pbm_pci_ped_ctrl = (uint64_t *)(a + 13237c478bd9Sstevel@tonic-gate XMITS_PARITY_DETECT_REG_OFFSET); 13247c478bd9Sstevel@tonic-gate 13257c478bd9Sstevel@tonic-gate /* 13267c478bd9Sstevel@tonic-gate * Create a property to indicate that this node supports DVMA 13277c478bd9Sstevel@tonic-gate * page relocation. 13287c478bd9Sstevel@tonic-gate */ 13297c478bd9Sstevel@tonic-gate if (CHIP_TYPE(pci_p) != PCI_CHIP_TOMATILLO && segkmem_reloc != 0) { 13307c478bd9Sstevel@tonic-gate pci_dvma_remap_enabled = 1; 13317c478bd9Sstevel@tonic-gate (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, 13327c478bd9Sstevel@tonic-gate pci_p->pci_dip, "dvma-remap-supported"); 13337c478bd9Sstevel@tonic-gate } 13347c478bd9Sstevel@tonic-gate 13357c478bd9Sstevel@tonic-gate /* 13367c478bd9Sstevel@tonic-gate * Register a panic callback so we can unquiesce this bus 13377c478bd9Sstevel@tonic-gate * if it has been placed in the quiesced state. 13387c478bd9Sstevel@tonic-gate */ 13397c478bd9Sstevel@tonic-gate pbm_p->pbm_panic_cb_id = callb_add(pci_pbm_panic_callb, 13407c478bd9Sstevel@tonic-gate (void *)pbm_p, CB_CL_PANIC, "pci_panic"); 13417c478bd9Sstevel@tonic-gate pbm_p->pbm_debug_cb_id = callb_add(pci_pbm_panic_callb, 13427c478bd9Sstevel@tonic-gate (void *)pbm_p, CB_CL_ENTER_DEBUGGER, "pci_debug_enter"); 13437c478bd9Sstevel@tonic-gate 13447c478bd9Sstevel@tonic-gate if (CHIP_TYPE(pci_p) != PCI_CHIP_SCHIZO) 13457c478bd9Sstevel@tonic-gate goto non_schizo; 13467c478bd9Sstevel@tonic-gate 13477c478bd9Sstevel@tonic-gate if (PCI_CHIP_ID(pci_p) >= SCHIZO_VER_23) { 13487c478bd9Sstevel@tonic-gate 13497c478bd9Sstevel@tonic-gate pbm_p->pbm_sync_reg_pa = pa + SCHIZO_PBM_DMA_SYNC_REG_OFFSET; 13507c478bd9Sstevel@tonic-gate 13517c478bd9Sstevel@tonic-gate /* 13527c478bd9Sstevel@tonic-gate * This is a software workaround to fix schizo hardware bug. 13537c478bd9Sstevel@tonic-gate * Create a boolean property and its existence means consistent 13547c478bd9Sstevel@tonic-gate * dma sync should not be done while in prom. The usb polled 13557c478bd9Sstevel@tonic-gate * code (OHCI,EHCI) will check for this property and will not 13567c478bd9Sstevel@tonic-gate * do dma sync if this property exist. 13577c478bd9Sstevel@tonic-gate */ 13587c478bd9Sstevel@tonic-gate (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, 13597c478bd9Sstevel@tonic-gate pci_p->pci_dip, "no-prom-cdma-sync"); 13607c478bd9Sstevel@tonic-gate } 13617c478bd9Sstevel@tonic-gate return; 13627c478bd9Sstevel@tonic-gate non_schizo: 13637c478bd9Sstevel@tonic-gate if (CHIP_TYPE(pci_p) == PCI_CHIP_TOMATILLO) { 13647c478bd9Sstevel@tonic-gate pci_dvma_sync_before_unmap = 1; 13657c478bd9Sstevel@tonic-gate pa = pci_p->pci_cb_p->cb_icbase_pa; 13667c478bd9Sstevel@tonic-gate } 1367810a4a70Sdanice if (CHIP_TYPE(pci_p) == PCI_CHIP_XMITS) 1368810a4a70Sdanice pbm_p->pbm_upper_retry_counter_reg = 1369810a4a70Sdanice (uint64_t *)(a + XMITS_UPPER_RETRY_COUNTER_REG_OFFSET); 1370810a4a70Sdanice 13717c478bd9Sstevel@tonic-gate pbm_p->pbm_sync_reg_pa = pa + PBM_DMA_SYNC_PEND_REG_OFFSET; 13727c478bd9Sstevel@tonic-gate } 13737c478bd9Sstevel@tonic-gate 13747c478bd9Sstevel@tonic-gate void 13757c478bd9Sstevel@tonic-gate pci_pbm_teardown(pbm_t *pbm_p) 13767c478bd9Sstevel@tonic-gate { 13777c478bd9Sstevel@tonic-gate (void) callb_delete(pbm_p->pbm_panic_cb_id); 13787c478bd9Sstevel@tonic-gate (void) callb_delete(pbm_p->pbm_debug_cb_id); 13797c478bd9Sstevel@tonic-gate } 13807c478bd9Sstevel@tonic-gate 13817c478bd9Sstevel@tonic-gate uintptr_t 13827c478bd9Sstevel@tonic-gate pci_ib_setup(ib_t *ib_p) 13837c478bd9Sstevel@tonic-gate { 13847c478bd9Sstevel@tonic-gate /* 13857c478bd9Sstevel@tonic-gate * Determine virtual addresses of bridge specific registers, 13867c478bd9Sstevel@tonic-gate */ 13877c478bd9Sstevel@tonic-gate pci_t *pci_p = ib_p->ib_pci_p; 13887c478bd9Sstevel@tonic-gate uintptr_t a = (uintptr_t)pci_p->pci_address[0]; 13897c478bd9Sstevel@tonic-gate 13907c478bd9Sstevel@tonic-gate ib_p->ib_ign = PCI_ID_TO_IGN(pci_p->pci_id); 13917c478bd9Sstevel@tonic-gate ib_p->ib_max_ino = SCHIZO_MAX_INO; 13927c478bd9Sstevel@tonic-gate ib_p->ib_slot_intr_map_regs = a + SCHIZO_IB_SLOT_INTR_MAP_REG_OFFSET; 13937c478bd9Sstevel@tonic-gate ib_p->ib_intr_map_regs = a + SCHIZO_IB_INTR_MAP_REG_OFFSET; 13947c478bd9Sstevel@tonic-gate ib_p->ib_slot_clear_intr_regs = 13957c478bd9Sstevel@tonic-gate a + SCHIZO_IB_CLEAR_INTR_REG_OFFSET; 13967c478bd9Sstevel@tonic-gate return (a); 13977c478bd9Sstevel@tonic-gate } 13987c478bd9Sstevel@tonic-gate 13997c478bd9Sstevel@tonic-gate void 14007c478bd9Sstevel@tonic-gate pci_sc_setup(sc_t *sc_p) 14017c478bd9Sstevel@tonic-gate { 14027c478bd9Sstevel@tonic-gate pci_t *pci_p = sc_p->sc_pci_p; 14037c478bd9Sstevel@tonic-gate uintptr_t a; 14047c478bd9Sstevel@tonic-gate 14057c478bd9Sstevel@tonic-gate /* 14067c478bd9Sstevel@tonic-gate * Determine the virtual addresses of the stream cache 14077c478bd9Sstevel@tonic-gate * control/status and flush registers. 14087c478bd9Sstevel@tonic-gate */ 14097c478bd9Sstevel@tonic-gate a = (uintptr_t)pci_p->pci_address[0]; /* PCICSRBase */ 14107c478bd9Sstevel@tonic-gate sc_p->sc_ctrl_reg = (uint64_t *)(a + SCHIZO_SC_CTRL_REG_OFFSET); 14117c478bd9Sstevel@tonic-gate sc_p->sc_invl_reg = (uint64_t *)(a + SCHIZO_SC_INVL_REG_OFFSET); 14127c478bd9Sstevel@tonic-gate sc_p->sc_sync_reg = (uint64_t *)(a + SCHIZO_SC_SYNC_REG_OFFSET); 14137c478bd9Sstevel@tonic-gate sc_p->sc_ctx_invl_reg = (uint64_t *)(a + SCHIZO_SC_CTX_INVL_REG_OFFSET); 14147c478bd9Sstevel@tonic-gate sc_p->sc_ctx_match_reg = 14157c478bd9Sstevel@tonic-gate (uint64_t *)(a + SCHIZO_SC_CTX_MATCH_REG_OFFSET); 14167c478bd9Sstevel@tonic-gate 14177c478bd9Sstevel@tonic-gate /* 14187c478bd9Sstevel@tonic-gate * Determine the virtual addresses of the streaming cache 14197c478bd9Sstevel@tonic-gate * diagnostic access registers. 14207c478bd9Sstevel@tonic-gate */ 14217c478bd9Sstevel@tonic-gate sc_p->sc_data_diag_acc = (uint64_t *)(a + SCHIZO_SC_DATA_DIAG_OFFSET); 14227c478bd9Sstevel@tonic-gate sc_p->sc_tag_diag_acc = (uint64_t *)(a + SCHIZO_SC_TAG_DIAG_OFFSET); 14237c478bd9Sstevel@tonic-gate sc_p->sc_ltag_diag_acc = (uint64_t *)(a + SCHIZO_SC_LTAG_DIAG_OFFSET); 14247c478bd9Sstevel@tonic-gate } 14257c478bd9Sstevel@tonic-gate 14267c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 14277c478bd9Sstevel@tonic-gate int 14287c478bd9Sstevel@tonic-gate pci_get_numproxy(dev_info_t *dip) 14297c478bd9Sstevel@tonic-gate { 14307c478bd9Sstevel@tonic-gate /* 14317c478bd9Sstevel@tonic-gate * Schizo does not support interrupt proxies. 14327c478bd9Sstevel@tonic-gate */ 14337c478bd9Sstevel@tonic-gate return (0); 14347c478bd9Sstevel@tonic-gate } 14357c478bd9Sstevel@tonic-gate 14367c478bd9Sstevel@tonic-gate /* 14377c478bd9Sstevel@tonic-gate * pcisch error handling 101: 14387c478bd9Sstevel@tonic-gate * 14397c478bd9Sstevel@tonic-gate * The various functions below are responsible for error handling. Given 14407c478bd9Sstevel@tonic-gate * a particular error, they must gather the appropriate state, report all 14417c478bd9Sstevel@tonic-gate * errors with correct payload, and attempt recovery where ever possible. 14427c478bd9Sstevel@tonic-gate * 14437c478bd9Sstevel@tonic-gate * Recovery in the context of this driver is being able notify a leaf device 14447c478bd9Sstevel@tonic-gate * of the failed transaction. This leaf device may either be the master or 14457c478bd9Sstevel@tonic-gate * target for this transaction and may have already received an error 14467c478bd9Sstevel@tonic-gate * notification via a PCI interrupt. Notification is done via DMA and access 14477c478bd9Sstevel@tonic-gate * handles. If we capture an address for the transaction then we can map it 14487c478bd9Sstevel@tonic-gate * to a handle(if the leaf device is fma-compliant) and fault the handle as 14497c478bd9Sstevel@tonic-gate * well as call the device driver registered callback. 14507c478bd9Sstevel@tonic-gate * 14517c478bd9Sstevel@tonic-gate * The hardware can either interrupt or trap upon detection of an error, in 14527c478bd9Sstevel@tonic-gate * some rare cases it also causes a fatal reset. 14537c478bd9Sstevel@tonic-gate * 14547c478bd9Sstevel@tonic-gate * cb_buserr_intr() is responsible for handling control block 14557c478bd9Sstevel@tonic-gate * errors(errors which stem from the host bus side of the bridge). Since 14567c478bd9Sstevel@tonic-gate * we support multiple chips and host bus standards, cb_buserr_intr will 14577c478bd9Sstevel@tonic-gate * call a bus specific error handler to report and handle the detected 14587c478bd9Sstevel@tonic-gate * error. Since this error can either affect or orginate from either of the 14597c478bd9Sstevel@tonic-gate * two PCI busses which are connected to the bridge, we need to call 14607c478bd9Sstevel@tonic-gate * pci_pbm_err_handler() for each bus as well to report their errors. We 14617c478bd9Sstevel@tonic-gate * also need to gather possible errors which have been detected by their 14627c478bd9Sstevel@tonic-gate * compliant children(via ndi_fm_handler_dispatch()). 14637c478bd9Sstevel@tonic-gate * 14647c478bd9Sstevel@tonic-gate * pbm_error_intr() and ecc_intr() are responsible for PCI Block Module 14657c478bd9Sstevel@tonic-gate * errors(generic PCI + bridge specific) and ECC errors, respectively. They 14667c478bd9Sstevel@tonic-gate * are common between pcisch and pcipsy and therefore exist in pci_pbm.c and 14677c478bd9Sstevel@tonic-gate * pci_ecc.c. To support error handling certain chip specific handlers 14687c478bd9Sstevel@tonic-gate * must exist and they are defined below. 14697c478bd9Sstevel@tonic-gate * 14707c478bd9Sstevel@tonic-gate * cpu_deferred_error() and cpu_async_error(), handle the traps that may 14717c478bd9Sstevel@tonic-gate * have originated from IO space. They call into the registered IO callbacks 14727c478bd9Sstevel@tonic-gate * to report and handle errors that may have caused the trap. 14737c478bd9Sstevel@tonic-gate * 14747c478bd9Sstevel@tonic-gate * pci_pbm_err_handler() is called by pbm_error_intr() or pci_err_callback() 14757c478bd9Sstevel@tonic-gate * (generic fma callback for pcipsy/pcisch, pci_fm.c). pci_err_callback() is 14767c478bd9Sstevel@tonic-gate * called when the CPU has trapped because of a possible IO error(TO/BERR/UE). 14777c478bd9Sstevel@tonic-gate * It will call pci_pbm_err_handler() to report and handle all PCI/PBM/IOMMU 14787c478bd9Sstevel@tonic-gate * related errors which are detected by the chip. 14797c478bd9Sstevel@tonic-gate * 14807c478bd9Sstevel@tonic-gate * pci_pbm_err_handler() calls a generic interface pbm_afsr_report()(pci_pbm.c) 14817c478bd9Sstevel@tonic-gate * to report the pbm specific errors and attempt to map the failed address 14827c478bd9Sstevel@tonic-gate * (if captured) to a device instance. pbm_afsr_report() calls a chip specific 14837c478bd9Sstevel@tonic-gate * interface to interpret the afsr bits pci_pbm_classify()(pcisch.c/pcipsy.c). 14847c478bd9Sstevel@tonic-gate * pci_pbm_err_handler() also calls iommu_err_handler() to handle IOMMU related 14857c478bd9Sstevel@tonic-gate * errors. 14867c478bd9Sstevel@tonic-gate * 14877c478bd9Sstevel@tonic-gate * iommu_err_handler() can recover from most errors, as long as the requesting 14887c478bd9Sstevel@tonic-gate * device is notified and the iommu can be flushed. If an IOMMU error occurs 14897c478bd9Sstevel@tonic-gate * due to a UE then it will be passed on to the ecc_err_handler() for 14907c478bd9Sstevel@tonic-gate * subsequent handling. 14917c478bd9Sstevel@tonic-gate * 14927c478bd9Sstevel@tonic-gate * ecc_err_handler()(pci_ecc.c) also calls a chip specific interface to 14937c478bd9Sstevel@tonic-gate * interpret the afsr, pci_ecc_classify(). ecc_err_handler() also calls 14947c478bd9Sstevel@tonic-gate * pci_pbm_err_handler() to report any pbm errors detected. 14957c478bd9Sstevel@tonic-gate * 14967c478bd9Sstevel@tonic-gate * To make sure that the trap code and the interrupt code are not going 14977c478bd9Sstevel@tonic-gate * to step on each others toes we have a per chip pci_fm_mutex. This also 14987c478bd9Sstevel@tonic-gate * makes it necessary for us to be caution while we are at a high PIL, so 14997c478bd9Sstevel@tonic-gate * that we do not cause a subsequent trap that causes us to hang. 15007c478bd9Sstevel@tonic-gate * 15017c478bd9Sstevel@tonic-gate * The attempt to commonize code was meant to keep in line with the current 15027c478bd9Sstevel@tonic-gate * pci driver implementation and it was not meant to confuse. If you are 15037c478bd9Sstevel@tonic-gate * confused then don't worry, I was too. 15047c478bd9Sstevel@tonic-gate * 15057c478bd9Sstevel@tonic-gate */ 15067c478bd9Sstevel@tonic-gate static void 15077c478bd9Sstevel@tonic-gate pci_cb_errstate_get(cb_t *cb_p, cb_errstate_t *cb_err_p) 15087c478bd9Sstevel@tonic-gate { 15097c478bd9Sstevel@tonic-gate uint64_t pa = cb_p->cb_base_pa; 15107c478bd9Sstevel@tonic-gate int i; 15117c478bd9Sstevel@tonic-gate 15127c478bd9Sstevel@tonic-gate bzero(cb_err_p, sizeof (cb_errstate_t)); 15137c478bd9Sstevel@tonic-gate 15147c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&cb_p->cb_pci_cmn_p->pci_fm_mutex)); 15157c478bd9Sstevel@tonic-gate 15167c478bd9Sstevel@tonic-gate cb_err_p->cb_bridge_type = PCI_BRIDGE_TYPE(cb_p->cb_pci_cmn_p); 15177c478bd9Sstevel@tonic-gate 15187c478bd9Sstevel@tonic-gate cb_err_p->cb_csr = lddphysio(pa + SCHIZO_CB_CSR_OFFSET); 15197c478bd9Sstevel@tonic-gate cb_err_p->cb_err = lddphysio(pa + SCHIZO_CB_ERRCTRL_OFFSET); 15207c478bd9Sstevel@tonic-gate cb_err_p->cb_intr = lddphysio(pa + SCHIZO_CB_INTCTRL_OFFSET); 15217c478bd9Sstevel@tonic-gate cb_err_p->cb_elog = lddphysio(pa + SCHIZO_CB_ERRLOG_OFFSET); 15227c478bd9Sstevel@tonic-gate cb_err_p->cb_ecc = lddphysio(pa + SCHIZO_CB_ECCCTRL_OFFSET); 15237c478bd9Sstevel@tonic-gate cb_err_p->cb_ue_afsr = lddphysio(pa + SCHIZO_CB_UEAFSR_OFFSET); 15247c478bd9Sstevel@tonic-gate cb_err_p->cb_ue_afar = lddphysio(pa + SCHIZO_CB_UEAFAR_OFFSET); 15257c478bd9Sstevel@tonic-gate cb_err_p->cb_ce_afsr = lddphysio(pa + SCHIZO_CB_CEAFSR_OFFSET); 15267c478bd9Sstevel@tonic-gate cb_err_p->cb_ce_afar = lddphysio(pa + SCHIZO_CB_CEAFAR_OFFSET); 15277c478bd9Sstevel@tonic-gate 15287c478bd9Sstevel@tonic-gate if ((CB_CHIP_TYPE((cb_t *)cb_p)) == PCI_CHIP_XMITS) { 15297c478bd9Sstevel@tonic-gate cb_err_p->cb_first_elog = lddphysio(pa + 15307c478bd9Sstevel@tonic-gate XMITS_CB_FIRST_ERROR_LOG); 15317c478bd9Sstevel@tonic-gate cb_err_p->cb_first_eaddr = lddphysio(pa + 15327c478bd9Sstevel@tonic-gate XMITS_CB_FIRST_ERROR_ADDR); 15337c478bd9Sstevel@tonic-gate cb_err_p->cb_leaf_status = lddphysio(pa + 15347c478bd9Sstevel@tonic-gate XMITS_CB_FIRST_ERROR_ADDR); 15357c478bd9Sstevel@tonic-gate } 15367c478bd9Sstevel@tonic-gate 15377c478bd9Sstevel@tonic-gate /* Gather PBM state information for both sides of this chip */ 15387c478bd9Sstevel@tonic-gate for (i = 0; i < 2; i++) { 15397c478bd9Sstevel@tonic-gate if (cb_p->cb_pci_cmn_p->pci_p[i] == NULL) 15407c478bd9Sstevel@tonic-gate continue; 15417c478bd9Sstevel@tonic-gate pci_pbm_errstate_get(((cb_t *)cb_p)->cb_pci_cmn_p-> 15427c478bd9Sstevel@tonic-gate pci_p[i], &cb_err_p->cb_pbm[i]); 15437c478bd9Sstevel@tonic-gate } 15447c478bd9Sstevel@tonic-gate } 15457c478bd9Sstevel@tonic-gate 15467c478bd9Sstevel@tonic-gate static void 15477c478bd9Sstevel@tonic-gate pci_cb_clear_error(cb_t *cb_p, cb_errstate_t *cb_err_p) 15487c478bd9Sstevel@tonic-gate { 15497c478bd9Sstevel@tonic-gate uint64_t pa = ((cb_t *)cb_p)->cb_base_pa; 15507c478bd9Sstevel@tonic-gate 15517c478bd9Sstevel@tonic-gate stdphysio(pa + SCHIZO_CB_ERRLOG_OFFSET, cb_err_p->cb_elog); 15527c478bd9Sstevel@tonic-gate } 15537c478bd9Sstevel@tonic-gate 15547c478bd9Sstevel@tonic-gate static cb_fm_err_t safari_err_tbl[] = { 15557c478bd9Sstevel@tonic-gate SAFARI_BAD_CMD, SCHIZO_CB_ELOG_BAD_CMD, CB_FATAL, 15567c478bd9Sstevel@tonic-gate SAFARI_SSM_DIS, SCHIZO_CB_ELOG_SSM_DIS, CB_FATAL, 15577c478bd9Sstevel@tonic-gate SAFARI_BAD_CMD_PCIA, SCHIZO_CB_ELOG_BAD_CMD_PCIA, CB_FATAL, 15587c478bd9Sstevel@tonic-gate SAFARI_BAD_CMD_PCIB, SCHIZO_CB_ELOG_BAD_CMD_PCIB, CB_FATAL, 15597c478bd9Sstevel@tonic-gate SAFARI_PAR_ERR_INT_PCIB, XMITS_CB_ELOG_PAR_ERR_INT_PCIB, CB_FATAL, 15607c478bd9Sstevel@tonic-gate SAFARI_PAR_ERR_INT_PCIA, XMITS_CB_ELOG_PAR_ERR_INT_PCIA, CB_FATAL, 15617c478bd9Sstevel@tonic-gate SAFARI_PAR_ERR_INT_SAF, XMITS_CB_ELOG_PAR_ERR_INT_SAF, CB_FATAL, 15627c478bd9Sstevel@tonic-gate SAFARI_PLL_ERR_PCIB, XMITS_CB_ELOG_PLL_ERR_PCIB, CB_FATAL, 15637c478bd9Sstevel@tonic-gate SAFARI_PLL_ERR_PCIA, XMITS_CB_ELOG_PLL_ERR_PCIA, CB_FATAL, 15647c478bd9Sstevel@tonic-gate SAFARI_PLL_ERR_SAF, XMITS_CB_ELOG_PLL_ERR_SAF, CB_FATAL, 15657c478bd9Sstevel@tonic-gate SAFARI_SAF_CIQ_TO, SCHIZO_CB_ELOG_SAF_CIQ_TO, CB_FATAL, 15667c478bd9Sstevel@tonic-gate SAFARI_SAF_LPQ_TO, SCHIZO_CB_ELOG_SAF_LPQ_TO, CB_FATAL, 15677c478bd9Sstevel@tonic-gate SAFARI_SAF_SFPQ_TO, SCHIZO_CB_ELOG_SAF_SFPQ_TO, CB_FATAL, 15687c478bd9Sstevel@tonic-gate SAFARI_APERR, SCHIZO_CB_ELOG_ADDR_PAR_ERR, CB_FATAL, 15697c478bd9Sstevel@tonic-gate SAFARI_UNMAP_ERR, SCHIZO_CB_ELOG_UNMAP_ERR, CB_FATAL, 15707c478bd9Sstevel@tonic-gate SAFARI_BUS_ERR, SCHIZO_CB_ELOG_BUS_ERR, CB_FATAL, 15717c478bd9Sstevel@tonic-gate SAFARI_TO_ERR, SCHIZO_CB_ELOG_TO_ERR, CB_FATAL, 15727c478bd9Sstevel@tonic-gate SAFARI_DSTAT_ERR, SCHIZO_CB_ELOG_DSTAT_ERR, CB_FATAL, 15737c478bd9Sstevel@tonic-gate SAFARI_SAF_UFPQ_TO, SCHIZO_CB_ELOG_SAF_UFPQ_TO, CB_FATAL, 15747c478bd9Sstevel@tonic-gate SAFARI_CPU0_PAR_SINGLE, SCHIZO_CB_ELOG_CPU0_PAR_SINGLE, CB_FATAL, 15757c478bd9Sstevel@tonic-gate SAFARI_CPU0_PAR_BIDI, SCHIZO_CB_ELOG_CPU0_PAR_BIDI, CB_FATAL, 15767c478bd9Sstevel@tonic-gate SAFARI_CPU1_PAR_SINGLE, SCHIZO_CB_ELOG_CPU1_PAR_SINGLE, CB_FATAL, 15777c478bd9Sstevel@tonic-gate SAFARI_CPU1_PAR_BIDI, SCHIZO_CB_ELOG_CPU1_PAR_BIDI, CB_FATAL, 15787c478bd9Sstevel@tonic-gate NULL, NULL, NULL, 15797c478bd9Sstevel@tonic-gate }; 15807c478bd9Sstevel@tonic-gate 15817c478bd9Sstevel@tonic-gate /* 15827c478bd9Sstevel@tonic-gate * Function used to handle and log Safari bus errors. 15837c478bd9Sstevel@tonic-gate */ 15847c478bd9Sstevel@tonic-gate static int 15857c478bd9Sstevel@tonic-gate safari_err_handler(dev_info_t *dip, uint64_t fme_ena, 15867c478bd9Sstevel@tonic-gate cb_errstate_t *cb_err_p) 15877c478bd9Sstevel@tonic-gate { 15887c478bd9Sstevel@tonic-gate int i; 15897c478bd9Sstevel@tonic-gate int fatal = 0; 15907c478bd9Sstevel@tonic-gate pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 15917c478bd9Sstevel@tonic-gate pci_common_t *cmn_p = pci_p->pci_common_p; 15927c478bd9Sstevel@tonic-gate 15937c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&cmn_p->pci_fm_mutex)); 15947c478bd9Sstevel@tonic-gate 15957c478bd9Sstevel@tonic-gate for (i = 0; safari_err_tbl[i].cb_err_class != NULL; i++) { 15967c478bd9Sstevel@tonic-gate if (cb_err_p->cb_elog & safari_err_tbl[i].cb_reg_bit) { 15977c478bd9Sstevel@tonic-gate cb_err_p->cb_err_class = safari_err_tbl[i].cb_err_class; 15987c478bd9Sstevel@tonic-gate cb_ereport_post(dip, fme_ena, cb_err_p); 15997c478bd9Sstevel@tonic-gate fatal += safari_err_tbl[i].cb_fatal; 16007c478bd9Sstevel@tonic-gate } 16017c478bd9Sstevel@tonic-gate } 16027c478bd9Sstevel@tonic-gate 16037c478bd9Sstevel@tonic-gate if (fatal) 16047c478bd9Sstevel@tonic-gate return (DDI_FM_FATAL); 16057c478bd9Sstevel@tonic-gate return (DDI_FM_OK); 16067c478bd9Sstevel@tonic-gate 16077c478bd9Sstevel@tonic-gate } 16087c478bd9Sstevel@tonic-gate 16097c478bd9Sstevel@tonic-gate /* 16107c478bd9Sstevel@tonic-gate * Check pbm va log register for captured errant address, and fail handle 16117c478bd9Sstevel@tonic-gate * if in per device cache. 16127c478bd9Sstevel@tonic-gate * Called from jbus_err_handler. 16137c478bd9Sstevel@tonic-gate */ 16147c478bd9Sstevel@tonic-gate static int 16157c478bd9Sstevel@tonic-gate jbus_check_va_log(cb_t *cb_p, uint64_t fme_ena, 16167c478bd9Sstevel@tonic-gate cb_errstate_t *cb_err_p) 16177c478bd9Sstevel@tonic-gate { 16187c478bd9Sstevel@tonic-gate int i; 16197c478bd9Sstevel@tonic-gate int ret = DDI_FM_FATAL; 16207c478bd9Sstevel@tonic-gate pci_common_t *cmn_p = cb_p->cb_pci_cmn_p; 16217c478bd9Sstevel@tonic-gate 16227c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&cmn_p->pci_fm_mutex)); 16237c478bd9Sstevel@tonic-gate /* 16247c478bd9Sstevel@tonic-gate * Check VA log register for address associated with error, 16257c478bd9Sstevel@tonic-gate * if no address is registered then return failure 16267c478bd9Sstevel@tonic-gate */ 16277c478bd9Sstevel@tonic-gate for (i = 0; i < 2; i++) { 16287c478bd9Sstevel@tonic-gate 16297c478bd9Sstevel@tonic-gate if (cb_p->cb_pci_cmn_p->pci_p[i] == NULL) 16307c478bd9Sstevel@tonic-gate continue; 16317c478bd9Sstevel@tonic-gate /* 16327c478bd9Sstevel@tonic-gate * Look up and fault handle associated with 16337c478bd9Sstevel@tonic-gate * logged DMA address 16347c478bd9Sstevel@tonic-gate */ 16357c478bd9Sstevel@tonic-gate if (cb_err_p->cb_pbm[i].pbm_va_log) { 163600d0963fSdilpreet void *addr = (void *)&cb_err_p->cb_pbm[i].pbm_va_log; 163700d0963fSdilpreet ret = ndi_fmc_error(cb_p->cb_pci_cmn_p->pci_p[i]-> 163800d0963fSdilpreet pci_dip, NULL, DMA_HANDLE, fme_ena, 163900d0963fSdilpreet (void *)addr); 16407c478bd9Sstevel@tonic-gate if (ret == DDI_FM_NONFATAL) 16417c478bd9Sstevel@tonic-gate break; 16427c478bd9Sstevel@tonic-gate } 16437c478bd9Sstevel@tonic-gate } 16447c478bd9Sstevel@tonic-gate return (ret); 16457c478bd9Sstevel@tonic-gate } 16467c478bd9Sstevel@tonic-gate 16477c478bd9Sstevel@tonic-gate static cb_fm_err_t jbus_err_tbl[] = { 16487c478bd9Sstevel@tonic-gate JBUS_APERR, SCHIZO_CB_ELOG_ADDR_PAR_ERR, CB_FATAL, 16497c478bd9Sstevel@tonic-gate JBUS_PWR_DATA_PERR, TOMATILLO_CB_ELOG_WR_DATA_PAR_ERR, CB_FATAL, 16507c478bd9Sstevel@tonic-gate JBUS_DRD_DATA_PERR, TOMATILLO_CB_ELOG_RD_DATA_PAR_ERR, CB_NONFATAL, 16517c478bd9Sstevel@tonic-gate JBUS_CTL_PERR, TOMATILLO_CB_ELOG_CTL_PAR_ERR, CB_FATAL, 16527c478bd9Sstevel@tonic-gate JBUS_ILL_BYTE_EN, TOMATILLO_CB_ELOG_ILL_BYTE_EN, CB_FATAL, 16537c478bd9Sstevel@tonic-gate JBUS_ILL_COH_IN, TOMATILLO_CB_ELOG_ILL_COH_IN, CB_FATAL, 16547c478bd9Sstevel@tonic-gate JBUS_SNOOP_ERR_RD, TOMATILLO_CB_ELOG_SNOOP_ERR_RD, CB_FATAL, 16557c478bd9Sstevel@tonic-gate JBUS_SNOOP_ERR_RDS, TOMATILLO_CB_ELOG_SNOOP_ERR_RDS, CB_FATAL, 16567c478bd9Sstevel@tonic-gate JBUS_SNOOP_ERR_RDSA, TOMATILLO_CB_ELOG_SNOOP_ERR_RDSA, CB_FATAL, 16577c478bd9Sstevel@tonic-gate JBUS_SNOOP_ERR_OWN, TOMATILLO_CB_ELOG_SNOOP_ERR_OWN, CB_FATAL, 16587c478bd9Sstevel@tonic-gate JBUS_SNOOP_ERR_RDO, TOMATILLO_CB_ELOG_SNOOP_ERR_RDO, CB_FATAL, 16597c478bd9Sstevel@tonic-gate JBUS_SNOOP_ERR_PCI, TOMATILLO_CB_ELOG_SNOOP_ERR_PCI, CB_FATAL, 16607c478bd9Sstevel@tonic-gate JBUS_SNOOP_ERR_GR, TOMATILLO_CB_ELOG_SNOOP_ERR_GR, CB_FATAL, 16617c478bd9Sstevel@tonic-gate JBUS_SNOOP_ERR, TOMATILLO_CB_ELOG_SNOOP_ERR, CB_FATAL, 16627c478bd9Sstevel@tonic-gate JBUS_BAD_CMD, SCHIZO_CB_ELOG_BAD_CMD, CB_FATAL, 16637c478bd9Sstevel@tonic-gate JBUS_UNMAP_ERR, SCHIZO_CB_ELOG_UNMAP_ERR, CB_NONFATAL, 16647c478bd9Sstevel@tonic-gate JBUS_TO_EXP_ERR, TOMATILLO_CB_ELOG_TO_EXP_ERR, CB_NONFATAL, 16657c478bd9Sstevel@tonic-gate JBUS_TO_ERR, SCHIZO_CB_ELOG_TO_ERR, CB_NONFATAL, 16667c478bd9Sstevel@tonic-gate JBUS_BUS_ERR, SCHIZO_CB_ELOG_BUS_ERR, CB_NONFATAL, 16677c478bd9Sstevel@tonic-gate NULL, NULL, NULL, 16687c478bd9Sstevel@tonic-gate }; 16697c478bd9Sstevel@tonic-gate 16707c478bd9Sstevel@tonic-gate /* 16717c478bd9Sstevel@tonic-gate * Function used to handle and log Jbus errors. 16727c478bd9Sstevel@tonic-gate */ 16737c478bd9Sstevel@tonic-gate static int 16747c478bd9Sstevel@tonic-gate jbus_err_handler(dev_info_t *dip, uint64_t fme_ena, 16757c478bd9Sstevel@tonic-gate cb_errstate_t *cb_err_p) 16767c478bd9Sstevel@tonic-gate { 16777c478bd9Sstevel@tonic-gate int fatal = 0; 16787c478bd9Sstevel@tonic-gate int nonfatal = 0; 16797c478bd9Sstevel@tonic-gate int i; 16807c478bd9Sstevel@tonic-gate pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 16817c478bd9Sstevel@tonic-gate cb_t *cb_p = pci_p->pci_cb_p; 16827c478bd9Sstevel@tonic-gate 16837c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&pci_p->pci_common_p->pci_fm_mutex)); 16847c478bd9Sstevel@tonic-gate 16857c478bd9Sstevel@tonic-gate for (i = 0; jbus_err_tbl[i].cb_err_class != NULL; i++) { 16867c478bd9Sstevel@tonic-gate if (!(cb_err_p->cb_elog & jbus_err_tbl[i].cb_reg_bit)) 16877c478bd9Sstevel@tonic-gate continue; 16887c478bd9Sstevel@tonic-gate cb_err_p->cb_err_class = jbus_err_tbl[i].cb_err_class; 16897c478bd9Sstevel@tonic-gate if (jbus_err_tbl[i].cb_fatal) { 16907c478bd9Sstevel@tonic-gate fatal += jbus_err_tbl[i].cb_fatal; 16917c478bd9Sstevel@tonic-gate continue; 16927c478bd9Sstevel@tonic-gate } 16937c478bd9Sstevel@tonic-gate if (jbus_check_va_log(cb_p, fme_ena, cb_err_p) 16947c478bd9Sstevel@tonic-gate != DDI_FM_NONFATAL) { 16957c478bd9Sstevel@tonic-gate fatal++; 16967c478bd9Sstevel@tonic-gate } 16977c478bd9Sstevel@tonic-gate cb_ereport_post(dip, fme_ena, cb_err_p); 16987c478bd9Sstevel@tonic-gate } 16997c478bd9Sstevel@tonic-gate 17007c478bd9Sstevel@tonic-gate return (fatal ? DDI_FM_FATAL : (nonfatal ? DDI_FM_NONFATAL : 17017c478bd9Sstevel@tonic-gate DDI_FM_OK)); 17027c478bd9Sstevel@tonic-gate } 17037c478bd9Sstevel@tonic-gate 17047c478bd9Sstevel@tonic-gate /* 17057c478bd9Sstevel@tonic-gate * Control Block error interrupt handler. 17067c478bd9Sstevel@tonic-gate */ 17077c478bd9Sstevel@tonic-gate uint_t 17087c478bd9Sstevel@tonic-gate cb_buserr_intr(caddr_t a) 17097c478bd9Sstevel@tonic-gate { 17107c478bd9Sstevel@tonic-gate cb_t *cb_p = (cb_t *)a; 17117c478bd9Sstevel@tonic-gate pci_common_t *cmn_p = cb_p->cb_pci_cmn_p; 17127c478bd9Sstevel@tonic-gate pci_t *pci_p = cmn_p->pci_p[0]; 17137c478bd9Sstevel@tonic-gate cb_errstate_t cb_err; 17147c478bd9Sstevel@tonic-gate ddi_fm_error_t derr; 17157c478bd9Sstevel@tonic-gate int ret = DDI_FM_FATAL; 17167c478bd9Sstevel@tonic-gate int i; 17177c478bd9Sstevel@tonic-gate 17187c478bd9Sstevel@tonic-gate if (pci_p == NULL) 17197c478bd9Sstevel@tonic-gate pci_p = cmn_p->pci_p[1]; 17207c478bd9Sstevel@tonic-gate 17217c478bd9Sstevel@tonic-gate bzero(&derr, sizeof (ddi_fm_error_t)); 17227c478bd9Sstevel@tonic-gate derr.fme_version = DDI_FME_VERSION; 17237c478bd9Sstevel@tonic-gate derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 17247c478bd9Sstevel@tonic-gate 17257c478bd9Sstevel@tonic-gate mutex_enter(&cmn_p->pci_fm_mutex); 17267c478bd9Sstevel@tonic-gate 17277c478bd9Sstevel@tonic-gate pci_cb_errstate_get(cb_p, &cb_err); 17287c478bd9Sstevel@tonic-gate 17297c478bd9Sstevel@tonic-gate if (CB_CHIP_TYPE(cb_p) == PCI_CHIP_TOMATILLO) 17307c478bd9Sstevel@tonic-gate ret = jbus_err_handler(pci_p->pci_dip, derr.fme_ena, &cb_err); 17317c478bd9Sstevel@tonic-gate else if ((CB_CHIP_TYPE(cb_p) == PCI_CHIP_SCHIZO) || 17327c478bd9Sstevel@tonic-gate (CB_CHIP_TYPE(cb_p) == PCI_CHIP_XMITS)) 17337c478bd9Sstevel@tonic-gate ret = safari_err_handler(pci_p->pci_dip, derr.fme_ena, 17347c478bd9Sstevel@tonic-gate &cb_err); 17357c478bd9Sstevel@tonic-gate 17367c478bd9Sstevel@tonic-gate /* 17377c478bd9Sstevel@tonic-gate * Check for related errors in PBM and IOMMU. The IOMMU could cause 17387c478bd9Sstevel@tonic-gate * a timeout on the jbus due to an IOMMU miss, so we need to check and 17397c478bd9Sstevel@tonic-gate * log the IOMMU error registers. 17407c478bd9Sstevel@tonic-gate */ 17417c478bd9Sstevel@tonic-gate for (i = 0; i < 2; i++) { 17427c478bd9Sstevel@tonic-gate if (cmn_p->pci_p[i] == NULL) 17437c478bd9Sstevel@tonic-gate continue; 17447c478bd9Sstevel@tonic-gate if (pci_pbm_err_handler(cmn_p->pci_p[i]->pci_dip, &derr, 17457c478bd9Sstevel@tonic-gate (void *)cmn_p->pci_p[i], PCI_CB_CALL) == DDI_FM_FATAL) 17467c478bd9Sstevel@tonic-gate ret = DDI_FM_FATAL; 17477c478bd9Sstevel@tonic-gate } 17487c478bd9Sstevel@tonic-gate 17497c478bd9Sstevel@tonic-gate /* Cleanup and reset error bits */ 17507c478bd9Sstevel@tonic-gate (void) pci_cb_clear_error(cb_p, &cb_err); 17517c478bd9Sstevel@tonic-gate mutex_exit(&cmn_p->pci_fm_mutex); 17527c478bd9Sstevel@tonic-gate 17537c478bd9Sstevel@tonic-gate if (ret == DDI_FM_FATAL) { 17547c478bd9Sstevel@tonic-gate fm_panic("Fatal System Bus Error has occurred\n"); 17557c478bd9Sstevel@tonic-gate } 17567c478bd9Sstevel@tonic-gate 17577c478bd9Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 17587c478bd9Sstevel@tonic-gate } 17597c478bd9Sstevel@tonic-gate 17607c478bd9Sstevel@tonic-gate static ecc_fm_err_t ecc_err_tbl[] = { 1761*39470729Skd93003 PCI_ECC_PIO_UE, COMMON_ECC_AFSR_E_PIO, CBNINTR_UE, 17627c478bd9Sstevel@tonic-gate PBM_PRIMARY, SCHIZO_ECC_AFAR_PIOW_UPA64S, SCH_REG_UPA, 17637c478bd9Sstevel@tonic-gate ACC_HANDLE, 17647c478bd9Sstevel@tonic-gate 1765*39470729Skd93003 PCI_ECC_PIO_UE, COMMON_ECC_AFSR_E_PIO, CBNINTR_UE, 17667c478bd9Sstevel@tonic-gate PBM_PRIMARY, SCHIZO_ECC_AFAR_PIOW_PCIA_REG, SCH_REG_PCIA_REG, 17677c478bd9Sstevel@tonic-gate ACC_HANDLE, 17687c478bd9Sstevel@tonic-gate 1769*39470729Skd93003 PCI_ECC_PIO_UE, COMMON_ECC_AFSR_E_PIO, CBNINTR_UE, 17707c478bd9Sstevel@tonic-gate PBM_PRIMARY, SCHIZO_ECC_AFAR_PIOW_PCIA_MEM, SCH_REG_PCIA_MEM, 17717c478bd9Sstevel@tonic-gate ACC_HANDLE, 17727c478bd9Sstevel@tonic-gate 1773*39470729Skd93003 PCI_ECC_PIO_UE, COMMON_ECC_AFSR_E_PIO, CBNINTR_UE, 17747c478bd9Sstevel@tonic-gate PBM_PRIMARY, SCHIZO_ECC_AFAR_PIOW_PCIA_CFGIO, SCH_REG_PCIA_CFGIO, 17757c478bd9Sstevel@tonic-gate ACC_HANDLE, 17767c478bd9Sstevel@tonic-gate 1777*39470729Skd93003 PCI_ECC_PIO_UE, COMMON_ECC_AFSR_E_PIO, CBNINTR_UE, 17787c478bd9Sstevel@tonic-gate PBM_PRIMARY, SCHIZO_ECC_AFAR_PIOW_PCIB_REG, SCH_REG_PCIB_REG, 17797c478bd9Sstevel@tonic-gate ACC_HANDLE, 17807c478bd9Sstevel@tonic-gate 1781*39470729Skd93003 PCI_ECC_PIO_UE, COMMON_ECC_AFSR_E_PIO, CBNINTR_UE, 17827c478bd9Sstevel@tonic-gate PBM_PRIMARY, SCHIZO_ECC_AFAR_PIOW_PCIB_MEM, SCH_REG_PCIB_MEM, 17837c478bd9Sstevel@tonic-gate ACC_HANDLE, 17847c478bd9Sstevel@tonic-gate 1785*39470729Skd93003 PCI_ECC_PIO_UE, COMMON_ECC_AFSR_E_PIO, CBNINTR_UE, 17867c478bd9Sstevel@tonic-gate PBM_PRIMARY, SCHIZO_ECC_AFAR_PIOW_PCIB_CFGIO, SCH_REG_PCIB_CFGIO, 17877c478bd9Sstevel@tonic-gate ACC_HANDLE, 17887c478bd9Sstevel@tonic-gate 1789*39470729Skd93003 PCI_ECC_PIO_UE, COMMON_ECC_AFSR_E_PIO, CBNINTR_UE, 17907c478bd9Sstevel@tonic-gate PBM_PRIMARY, SCHIZO_ECC_AFAR_PIOW_SAFARI_REGS, SCH_REG_SAFARI_REGS, 17917c478bd9Sstevel@tonic-gate ACC_HANDLE, 17927c478bd9Sstevel@tonic-gate 1793*39470729Skd93003 PCI_ECC_SEC_PIO_UE, COMMON_ECC_AFSR_E_PIO, CBNINTR_UE, 17947c478bd9Sstevel@tonic-gate PBM_SECONDARY, NULL, NULL, ACC_HANDLE, 17957c478bd9Sstevel@tonic-gate 1796*39470729Skd93003 PCI_ECC_PIO_CE, COMMON_ECC_AFSR_E_PIO, CBNINTR_CE, 17977c478bd9Sstevel@tonic-gate PBM_PRIMARY, NULL, NULL, ACC_HANDLE, 17987c478bd9Sstevel@tonic-gate 1799*39470729Skd93003 PCI_ECC_SEC_PIO_CE, COMMON_ECC_AFSR_E_PIO, CBNINTR_CE, 18007c478bd9Sstevel@tonic-gate PBM_SECONDARY, NULL, NULL, ACC_HANDLE, 18017c478bd9Sstevel@tonic-gate 1802*39470729Skd93003 PCI_ECC_DRD_UE, COMMON_ECC_AFSR_E_DRD, CBNINTR_UE, 18037c478bd9Sstevel@tonic-gate PBM_PRIMARY, NULL, NULL, DMA_HANDLE, 18047c478bd9Sstevel@tonic-gate 1805*39470729Skd93003 PCI_ECC_SEC_DRD_UE, COMMON_ECC_AFSR_E_DRD, CBNINTR_UE, 18067c478bd9Sstevel@tonic-gate PBM_SECONDARY, NULL, NULL, DMA_HANDLE, 18077c478bd9Sstevel@tonic-gate 1808*39470729Skd93003 PCI_ECC_DRD_CE, COMMON_ECC_AFSR_E_DRD, CBNINTR_CE, 18097c478bd9Sstevel@tonic-gate PBM_PRIMARY, NULL, NULL, DMA_HANDLE, 18107c478bd9Sstevel@tonic-gate 1811*39470729Skd93003 PCI_ECC_SEC_DRD_CE, COMMON_ECC_AFSR_E_DRD, CBNINTR_CE, 18127c478bd9Sstevel@tonic-gate PBM_SECONDARY, NULL, NULL, DMA_HANDLE, 18137c478bd9Sstevel@tonic-gate 1814*39470729Skd93003 PCI_ECC_DWR_UE, COMMON_ECC_AFSR_E_DWR, CBNINTR_UE, 18157c478bd9Sstevel@tonic-gate PBM_PRIMARY, NULL, NULL, DMA_HANDLE, 18167c478bd9Sstevel@tonic-gate 1817*39470729Skd93003 PCI_ECC_SEC_DWR_UE, COMMON_ECC_AFSR_E_DWR, CBNINTR_UE, 18187c478bd9Sstevel@tonic-gate PBM_SECONDARY, NULL, NULL, DMA_HANDLE, 18197c478bd9Sstevel@tonic-gate 1820*39470729Skd93003 PCI_ECC_DWR_CE, COMMON_ECC_AFSR_E_DWR, CBNINTR_CE, 18217c478bd9Sstevel@tonic-gate PBM_PRIMARY, NULL, NULL, DMA_HANDLE, 18227c478bd9Sstevel@tonic-gate 1823*39470729Skd93003 PCI_ECC_SEC_DWR_CE, COMMON_ECC_AFSR_E_DWR, CBNINTR_CE, 18247c478bd9Sstevel@tonic-gate PBM_SECONDARY, NULL, NULL, DMA_HANDLE, 18257c478bd9Sstevel@tonic-gate 18267c478bd9Sstevel@tonic-gate NULL, NULL, NULL, NULL, NULL, NULL, 18277c478bd9Sstevel@tonic-gate }; 18287c478bd9Sstevel@tonic-gate 18297c478bd9Sstevel@tonic-gate /* 18307c478bd9Sstevel@tonic-gate * pci_ecc_classify, called by ecc_handler to classify ecc errors 18317c478bd9Sstevel@tonic-gate * and determine if we should panic or not. 18327c478bd9Sstevel@tonic-gate */ 18337c478bd9Sstevel@tonic-gate void 18347c478bd9Sstevel@tonic-gate pci_ecc_classify(uint64_t err, ecc_errstate_t *ecc_err_p) 18357c478bd9Sstevel@tonic-gate { 18367c478bd9Sstevel@tonic-gate struct async_flt *ecc_p = &ecc_err_p->ecc_aflt; 18377c478bd9Sstevel@tonic-gate uint64_t region, afar = ecc_p->flt_addr; 18387c478bd9Sstevel@tonic-gate int i, j, ret = 0; 18397c478bd9Sstevel@tonic-gate int flag, fatal = 0; 18407c478bd9Sstevel@tonic-gate pci_common_t *cmn_p = ecc_err_p->ecc_ii_p.ecc_p->ecc_pci_cmn_p; 18417c478bd9Sstevel@tonic-gate pci_t *pci_p = cmn_p->pci_p[0]; 18427c478bd9Sstevel@tonic-gate 18437c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&cmn_p->pci_fm_mutex)); 18447c478bd9Sstevel@tonic-gate 18457c478bd9Sstevel@tonic-gate ecc_err_p->ecc_bridge_type = PCI_BRIDGE_TYPE(cmn_p); 18467c478bd9Sstevel@tonic-gate 18477c478bd9Sstevel@tonic-gate if (pci_p == NULL) 18487c478bd9Sstevel@tonic-gate pci_p = cmn_p->pci_p[1]; 18497c478bd9Sstevel@tonic-gate 18507c478bd9Sstevel@tonic-gate ecc_err_p->ecc_ctrl = lddphysio(ecc_err_p->ecc_ii_p.ecc_p->ecc_csr_pa); 18517c478bd9Sstevel@tonic-gate ecc_err_p->ecc_err_addr = afar; 18527c478bd9Sstevel@tonic-gate region = afar & SCHIZO_ECC_AFAR_PIOW_MASK; 18537c478bd9Sstevel@tonic-gate 18547c478bd9Sstevel@tonic-gate for (i = 0; ecc_err_tbl[i].ecc_err_class != NULL; i++) { 18557c478bd9Sstevel@tonic-gate if (!(err & ecc_err_tbl[i].ecc_reg_bit) || 18567c478bd9Sstevel@tonic-gate (ecc_err_p->ecc_ii_p.ecc_type != 18577c478bd9Sstevel@tonic-gate ecc_err_tbl[i].ecc_type) || 18587c478bd9Sstevel@tonic-gate (ecc_err_p->ecc_pri != ecc_err_tbl[i].ecc_pri)) 18597c478bd9Sstevel@tonic-gate continue; 18607c478bd9Sstevel@tonic-gate 18617c478bd9Sstevel@tonic-gate ecc_p->flt_erpt_class = ecc_err_tbl[i].ecc_err_class; 18627c478bd9Sstevel@tonic-gate flag = ecc_err_tbl[i].ecc_flag; 18637c478bd9Sstevel@tonic-gate 18647c478bd9Sstevel@tonic-gate if (!ecc_err_tbl[i].ecc_pri || 18657c478bd9Sstevel@tonic-gate (ecc_err_tbl[i].ecc_type == CBNINTR_CE)) { 18667c478bd9Sstevel@tonic-gate fatal += (ecc_err_tbl[i].ecc_type == CBNINTR_UE) ? 18677c478bd9Sstevel@tonic-gate 1 : 0; 18687c478bd9Sstevel@tonic-gate break; 18697c478bd9Sstevel@tonic-gate } 18707c478bd9Sstevel@tonic-gate 18717c478bd9Sstevel@tonic-gate if (flag == ACC_HANDLE && 18727c478bd9Sstevel@tonic-gate (region & ecc_err_tbl[i].ecc_region_bits)) { 18737c478bd9Sstevel@tonic-gate ecc_err_p->ecc_region = ecc_err_tbl[i].ecc_region; 18747c478bd9Sstevel@tonic-gate pci_format_ecc_addr(pci_p->pci_dip, 18757c478bd9Sstevel@tonic-gate &ecc_err_p->ecc_err_addr, 18767c478bd9Sstevel@tonic-gate ecc_err_p->ecc_region); 18777c478bd9Sstevel@tonic-gate } 18787c478bd9Sstevel@tonic-gate 18797c478bd9Sstevel@tonic-gate /* 18807c478bd9Sstevel@tonic-gate * Lookup and fault errant handle 18817c478bd9Sstevel@tonic-gate */ 18827c478bd9Sstevel@tonic-gate for (j = 0; j < 2; ++j) { 18837c478bd9Sstevel@tonic-gate ret = DDI_FM_UNKNOWN; 18847c478bd9Sstevel@tonic-gate if (cmn_p->pci_p[j] == NULL) 18857c478bd9Sstevel@tonic-gate continue; 188600d0963fSdilpreet ret = ndi_fmc_error(cmn_p->pci_p[j]->pci_dip, NULL, 18877c478bd9Sstevel@tonic-gate flag, ecc_err_p->ecc_ena, 18887c478bd9Sstevel@tonic-gate (void *)&ecc_err_p->ecc_err_addr); 18897c478bd9Sstevel@tonic-gate if (ret == DDI_FM_NONFATAL) { 18907c478bd9Sstevel@tonic-gate fatal = 0; 18917c478bd9Sstevel@tonic-gate break; 18927c478bd9Sstevel@tonic-gate } else 18937c478bd9Sstevel@tonic-gate fatal++; 18947c478bd9Sstevel@tonic-gate } 18957c478bd9Sstevel@tonic-gate break; 18967c478bd9Sstevel@tonic-gate } 18977c478bd9Sstevel@tonic-gate 18987c478bd9Sstevel@tonic-gate if (fatal) 18997c478bd9Sstevel@tonic-gate ecc_p->flt_panic = 1; 19007c478bd9Sstevel@tonic-gate else if (flag != ACC_HANDLE) 19017c478bd9Sstevel@tonic-gate ecc_err_p->ecc_pg_ret = 1; 19027c478bd9Sstevel@tonic-gate } 19037c478bd9Sstevel@tonic-gate 19047c478bd9Sstevel@tonic-gate /* 19057c478bd9Sstevel@tonic-gate * Tables to define PCI-X Split Completion errors 19067c478bd9Sstevel@tonic-gate */ 19077c478bd9Sstevel@tonic-gate 19087c478bd9Sstevel@tonic-gate pcix_err_msg_rec_t pcix_completer_errs[] = { 19097c478bd9Sstevel@tonic-gate {PCIX_CPLT_OUT_OF_RANGE, "pcix", "oor" }, 19107c478bd9Sstevel@tonic-gate }; 19117c478bd9Sstevel@tonic-gate 19127c478bd9Sstevel@tonic-gate pcix_err_tbl_t pcix_split_errs_tbl[] = { 19137c478bd9Sstevel@tonic-gate {PCIX_CLASS_CPLT, 19147c478bd9Sstevel@tonic-gate sizeof (pcix_completer_errs)/sizeof (pcix_err_msg_rec_t), 19157c478bd9Sstevel@tonic-gate pcix_completer_errs }, 19167c478bd9Sstevel@tonic-gate }; 19177c478bd9Sstevel@tonic-gate 19187c478bd9Sstevel@tonic-gate /* 19197c478bd9Sstevel@tonic-gate * Tables for the PCI-X error status messages 19207c478bd9Sstevel@tonic-gate */ 19217c478bd9Sstevel@tonic-gate pcix_err_msg_rec_t pcix_stat_errs[] = { 19227c478bd9Sstevel@tonic-gate {XMITS_PCIX_STAT_SC_DSCRD, "pcix", "discard" }, 19237c478bd9Sstevel@tonic-gate {XMITS_PCIX_STAT_SC_TTO, "xmits.pbmx", "tato" }, 19247c478bd9Sstevel@tonic-gate {XMITS_PCIX_STAT_SMMU, "xmits.pbmx", "stmmu" }, 19257c478bd9Sstevel@tonic-gate {XMITS_PCIX_STAT_SDSTAT, "xmits.pbmx", "stdst" }, 19267c478bd9Sstevel@tonic-gate {XMITS_PCIX_STAT_CMMU, "xmits.pbmx", "cnmmu" }, 19277c478bd9Sstevel@tonic-gate {XMITS_PCIX_STAT_CDSTAT, "xmits.pbmx", "cndst" } 19287c478bd9Sstevel@tonic-gate }; 19297c478bd9Sstevel@tonic-gate 19307c478bd9Sstevel@tonic-gate pcix_err_tbl_t pcix_stat_errs_tbl = 19317c478bd9Sstevel@tonic-gate {PCIX_NO_CLASS, 19327c478bd9Sstevel@tonic-gate sizeof (pcix_stat_errs)/sizeof (pcix_err_msg_rec_t), 19337c478bd9Sstevel@tonic-gate pcix_stat_errs }; 19347c478bd9Sstevel@tonic-gate 19357c478bd9Sstevel@tonic-gate 19367c478bd9Sstevel@tonic-gate /* 19377c478bd9Sstevel@tonic-gate * walk thru a table of error messages, printing as appropriate 19387c478bd9Sstevel@tonic-gate * 19397c478bd9Sstevel@tonic-gate * t - the table of messages to parse 19407c478bd9Sstevel@tonic-gate * err - the error to match against 19417c478bd9Sstevel@tonic-gate * multi - flag, sometimes multiple error bits may be set/desired 19427c478bd9Sstevel@tonic-gate */ 19437c478bd9Sstevel@tonic-gate static int 19447c478bd9Sstevel@tonic-gate pcix_lookup_err_msgs(dev_info_t *dip, uint64_t ena, pcix_err_tbl_t t, 19457c478bd9Sstevel@tonic-gate pbm_errstate_t *pbm_err_p) 19467c478bd9Sstevel@tonic-gate { 19477c478bd9Sstevel@tonic-gate uint32_t err_bits = pbm_err_p->pbm_err & XMITS_PCIX_MSG_INDEX_MASK; 19487c478bd9Sstevel@tonic-gate int nerr = 0; 19497c478bd9Sstevel@tonic-gate int j; 19507c478bd9Sstevel@tonic-gate char buf[FM_MAX_CLASS]; 19517c478bd9Sstevel@tonic-gate 19527c478bd9Sstevel@tonic-gate for (j = 0; j < t.err_rec_num; j++) { 19537c478bd9Sstevel@tonic-gate uint32_t msg_key = t.err_msg_tbl[j].msg_key; 19547c478bd9Sstevel@tonic-gate if (pbm_err_p->pbm_multi ? !(err_bits & msg_key) : err_bits 19557c478bd9Sstevel@tonic-gate != msg_key) 19567c478bd9Sstevel@tonic-gate continue; 19577c478bd9Sstevel@tonic-gate 19587c478bd9Sstevel@tonic-gate (void) snprintf(buf, FM_MAX_CLASS, "%s.%s%s", 19597c478bd9Sstevel@tonic-gate t.err_msg_tbl[j].msg_class, 19607c478bd9Sstevel@tonic-gate pbm_err_p->pbm_pri ? "" : PCIX_SECONDARY, 19617c478bd9Sstevel@tonic-gate t.err_msg_tbl[j].msg_str); 19627c478bd9Sstevel@tonic-gate 19637c478bd9Sstevel@tonic-gate pbm_err_p->pbm_err_class = buf; 19647c478bd9Sstevel@tonic-gate pcix_ereport_post(dip, ena, pbm_err_p); 19657c478bd9Sstevel@tonic-gate nerr++; 19667c478bd9Sstevel@tonic-gate } 19677c478bd9Sstevel@tonic-gate return (nerr ? DDI_FM_FATAL : DDI_FM_OK); 19687c478bd9Sstevel@tonic-gate } 19697c478bd9Sstevel@tonic-gate 19707c478bd9Sstevel@tonic-gate /* 19717c478bd9Sstevel@tonic-gate * Decodes primary(bit 27-24) or secondary(bit 15-12) PCI-X split 19727c478bd9Sstevel@tonic-gate * completion error message class and index in PBM AFSR. 19737c478bd9Sstevel@tonic-gate */ 19747c478bd9Sstevel@tonic-gate static void 19757c478bd9Sstevel@tonic-gate pcix_log_split_err(dev_info_t *dip, uint64_t ena, pbm_errstate_t *pbm_err_p) 19767c478bd9Sstevel@tonic-gate { 19777c478bd9Sstevel@tonic-gate uint32_t class = pbm_err_p->pbm_err & XMITS_PCIX_MSG_CLASS_MASK; 19787c478bd9Sstevel@tonic-gate uint32_t num_classes = sizeof (pcix_split_errs_tbl) / 19797c478bd9Sstevel@tonic-gate sizeof (struct pcix_err_tbl); 19807c478bd9Sstevel@tonic-gate int i; 19817c478bd9Sstevel@tonic-gate 19827c478bd9Sstevel@tonic-gate for (i = 0; i < num_classes; i++) { 19837c478bd9Sstevel@tonic-gate if (class == pcix_split_errs_tbl[i].err_class) { 19847c478bd9Sstevel@tonic-gate pbm_err_p->pbm_multi = PCIX_SINGLE_ERR; 19857c478bd9Sstevel@tonic-gate (void) pcix_lookup_err_msgs(dip, ena, 19867c478bd9Sstevel@tonic-gate pcix_split_errs_tbl[i], pbm_err_p); 19877c478bd9Sstevel@tonic-gate break; 19887c478bd9Sstevel@tonic-gate } 19897c478bd9Sstevel@tonic-gate } 19907c478bd9Sstevel@tonic-gate } 19917c478bd9Sstevel@tonic-gate 19927c478bd9Sstevel@tonic-gate /* 19937c478bd9Sstevel@tonic-gate * Report PBM PCI-X Error Status Register if in PCI-X mode 19947c478bd9Sstevel@tonic-gate * 19957c478bd9Sstevel@tonic-gate * Once a PCI-X fault tree is constructed, the code below may need to 19967c478bd9Sstevel@tonic-gate * change. 19977c478bd9Sstevel@tonic-gate */ 19987c478bd9Sstevel@tonic-gate static int 19997c478bd9Sstevel@tonic-gate pcix_log_pbm(pci_t *pci_p, uint64_t ena, pbm_errstate_t *pbm_err_p) 20007c478bd9Sstevel@tonic-gate { 20017c478bd9Sstevel@tonic-gate int fatal = 0; 20027c478bd9Sstevel@tonic-gate int nonfatal = 0; 20037c478bd9Sstevel@tonic-gate uint32_t e; 20047c478bd9Sstevel@tonic-gate 20057c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&pci_p->pci_common_p->pci_fm_mutex)); 20067c478bd9Sstevel@tonic-gate 20077c478bd9Sstevel@tonic-gate DEBUG3(DBG_ERR_INTR, pci_p->pci_dip, "pcix_log_pbm: chip_type=%d " 20087c478bd9Sstevel@tonic-gate "ctr_stat=%lx afsr = 0x%lx", CHIP_TYPE(pci_p), 20097c478bd9Sstevel@tonic-gate pbm_err_p->pbm_ctl_stat, pbm_err_p->pbm_afsr); 20107c478bd9Sstevel@tonic-gate 20117c478bd9Sstevel@tonic-gate if (!(CHIP_TYPE(pci_p) == PCI_CHIP_XMITS) || 20127c478bd9Sstevel@tonic-gate !(pbm_err_p->pbm_ctl_stat & XMITS_PCI_CTRL_X_MODE)) 20137c478bd9Sstevel@tonic-gate return (DDI_FM_OK); 20147c478bd9Sstevel@tonic-gate 20157c478bd9Sstevel@tonic-gate if (pbm_err_p->pbm_afsr & XMITS_PCI_X_AFSR_P_SC_ERR) { 20167c478bd9Sstevel@tonic-gate pbm_err_p->pbm_err = PBM_AFSR_TO_PRISPLIT(pbm_err_p->pbm_afsr); 20177c478bd9Sstevel@tonic-gate pbm_err_p->pbm_pri = PBM_PRIMARY; 20187c478bd9Sstevel@tonic-gate pcix_log_split_err(pci_p->pci_dip, ena, pbm_err_p); 20197c478bd9Sstevel@tonic-gate nonfatal++; 20207c478bd9Sstevel@tonic-gate } 20217c478bd9Sstevel@tonic-gate if (pbm_err_p->pbm_afsr & XMITS_PCI_X_AFSR_S_SC_ERR) { 20227c478bd9Sstevel@tonic-gate pbm_err_p->pbm_err = PBM_AFSR_TO_PRISPLIT(pbm_err_p->pbm_afsr); 20237c478bd9Sstevel@tonic-gate pbm_err_p->pbm_pri = PBM_PRIMARY; 20247c478bd9Sstevel@tonic-gate pcix_log_split_err(pci_p->pci_dip, ena, pbm_err_p); 20257c478bd9Sstevel@tonic-gate nonfatal++; 20267c478bd9Sstevel@tonic-gate } 20277c478bd9Sstevel@tonic-gate 20287c478bd9Sstevel@tonic-gate e = PBM_PCIX_TO_PRIERR(pbm_err_p->pbm_pcix_stat); 20297c478bd9Sstevel@tonic-gate if (e) { 20307c478bd9Sstevel@tonic-gate pbm_err_p->pbm_pri = PBM_PRIMARY; 20317c478bd9Sstevel@tonic-gate pbm_err_p->pbm_err = e; 20327c478bd9Sstevel@tonic-gate pbm_err_p->pbm_multi = PCIX_MULTI_ERR; 20337c478bd9Sstevel@tonic-gate if (pcix_lookup_err_msgs(pci_p->pci_dip, ena, 20347c478bd9Sstevel@tonic-gate pcix_stat_errs_tbl, pbm_err_p) == DDI_FM_FATAL) 20357c478bd9Sstevel@tonic-gate fatal++; 20367c478bd9Sstevel@tonic-gate else 20377c478bd9Sstevel@tonic-gate nonfatal++; 20387c478bd9Sstevel@tonic-gate } 20397c478bd9Sstevel@tonic-gate 20407c478bd9Sstevel@tonic-gate e = PBM_PCIX_TO_SECERR(pbm_err_p->pbm_pcix_stat); 20417c478bd9Sstevel@tonic-gate if (e) { 20427c478bd9Sstevel@tonic-gate pbm_err_p->pbm_pri = PBM_SECONDARY; 20437c478bd9Sstevel@tonic-gate pbm_err_p->pbm_err = e; 20447c478bd9Sstevel@tonic-gate pbm_err_p->pbm_multi = PCIX_MULTI_ERR; 20457c478bd9Sstevel@tonic-gate if (pcix_lookup_err_msgs(pci_p->pci_dip, ena, 20467c478bd9Sstevel@tonic-gate pcix_stat_errs_tbl, pbm_err_p) == DDI_FM_FATAL) 20477c478bd9Sstevel@tonic-gate fatal++; 20487c478bd9Sstevel@tonic-gate else 20497c478bd9Sstevel@tonic-gate nonfatal++; 20507c478bd9Sstevel@tonic-gate } 20517c478bd9Sstevel@tonic-gate 20527c478bd9Sstevel@tonic-gate if (!fatal && !nonfatal) 20537c478bd9Sstevel@tonic-gate return (DDI_FM_OK); 20547c478bd9Sstevel@tonic-gate else if (fatal) 20557c478bd9Sstevel@tonic-gate return (DDI_FM_FATAL); 20567c478bd9Sstevel@tonic-gate return (DDI_FM_NONFATAL); 20577c478bd9Sstevel@tonic-gate } 20587c478bd9Sstevel@tonic-gate 20597c478bd9Sstevel@tonic-gate static pbm_fm_err_t pbm_err_tbl[] = { 20607c478bd9Sstevel@tonic-gate PCI_MA, SCHIZO_PCI_AFSR_E_MA, PBM_PRIMARY, 20617c478bd9Sstevel@tonic-gate FM_LOG_PCI, PCI_TARG_MA, 20627c478bd9Sstevel@tonic-gate 20637c478bd9Sstevel@tonic-gate PCI_SEC_MA, SCHIZO_PCI_AFSR_E_MA, PBM_SECONDARY, 20647c478bd9Sstevel@tonic-gate FM_LOG_PBM, NULL, 20657c478bd9Sstevel@tonic-gate 20667c478bd9Sstevel@tonic-gate PCI_REC_TA, SCHIZO_PCI_AFSR_E_TA, PBM_PRIMARY, 20677c478bd9Sstevel@tonic-gate FM_LOG_PCI, PCI_TARG_REC_TA, 20687c478bd9Sstevel@tonic-gate 20697c478bd9Sstevel@tonic-gate PCI_SEC_REC_TA, SCHIZO_PCI_AFSR_E_TA, PBM_SECONDARY, 20707c478bd9Sstevel@tonic-gate FM_LOG_PBM, NULL, 20717c478bd9Sstevel@tonic-gate 20727c478bd9Sstevel@tonic-gate PCI_PBM_RETRY, SCHIZO_PCI_AFSR_E_RTRY, PBM_PRIMARY, 20737c478bd9Sstevel@tonic-gate FM_LOG_PBM, PCI_PBM_TARG_RETRY, 20747c478bd9Sstevel@tonic-gate 20757c478bd9Sstevel@tonic-gate PCI_SEC_PBM_RETRY, SCHIZO_PCI_AFSR_E_RTRY, PBM_SECONDARY, 20767c478bd9Sstevel@tonic-gate FM_LOG_PBM, NULL, 20777c478bd9Sstevel@tonic-gate 20787c478bd9Sstevel@tonic-gate PCI_MDPE, SCHIZO_PCI_AFSR_E_PERR, PBM_PRIMARY, 20797c478bd9Sstevel@tonic-gate FM_LOG_PCI, PCI_TARG_MDPE, 20807c478bd9Sstevel@tonic-gate 20817c478bd9Sstevel@tonic-gate PCI_SEC_MDPE, SCHIZO_PCI_AFSR_E_PERR, PBM_SECONDARY, 20827c478bd9Sstevel@tonic-gate FM_LOG_PBM, NULL, 20837c478bd9Sstevel@tonic-gate 20847c478bd9Sstevel@tonic-gate PCI_PBM_TTO, SCHIZO_PCI_AFSR_E_TTO, PBM_PRIMARY, 20857c478bd9Sstevel@tonic-gate FM_LOG_PBM, PCI_PBM_TARG_TTO, 20867c478bd9Sstevel@tonic-gate 20877c478bd9Sstevel@tonic-gate PCI_SEC_PBM_TTO, SCHIZO_PCI_AFSR_E_TTO, PBM_SECONDARY, 20887c478bd9Sstevel@tonic-gate FM_LOG_PBM, NULL, 20897c478bd9Sstevel@tonic-gate 20907c478bd9Sstevel@tonic-gate PCI_SCH_BUS_UNUSABLE_ERR, SCHIZO_PCI_AFSR_E_UNUSABLE, PBM_PRIMARY, 20917c478bd9Sstevel@tonic-gate FM_LOG_PBM, NULL, 20927c478bd9Sstevel@tonic-gate 20937c478bd9Sstevel@tonic-gate PCI_SEC_SCH_BUS_UNUSABLE_ERR, SCHIZO_PCI_AFSR_E_UNUSABLE, PBM_SECONDARY, 20947c478bd9Sstevel@tonic-gate FM_LOG_PBM, NULL, 20957c478bd9Sstevel@tonic-gate 20967c478bd9Sstevel@tonic-gate NULL, NULL, NULL, 20977c478bd9Sstevel@tonic-gate NULL, NULL, 20987c478bd9Sstevel@tonic-gate }; 20997c478bd9Sstevel@tonic-gate 21007c478bd9Sstevel@tonic-gate 21017c478bd9Sstevel@tonic-gate /* 21027c478bd9Sstevel@tonic-gate * pci_pbm_classify, called by pbm_afsr_report to classify piow afsr. 21037c478bd9Sstevel@tonic-gate */ 21047c478bd9Sstevel@tonic-gate int 21057c478bd9Sstevel@tonic-gate pci_pbm_classify(pbm_errstate_t *pbm_err_p) 21067c478bd9Sstevel@tonic-gate { 21077c478bd9Sstevel@tonic-gate uint32_t err; 21087c478bd9Sstevel@tonic-gate int nerr = 0; 21097c478bd9Sstevel@tonic-gate int i; 21107c478bd9Sstevel@tonic-gate 21117c478bd9Sstevel@tonic-gate err = pbm_err_p->pbm_pri ? PBM_AFSR_TO_PRIERR(pbm_err_p->pbm_afsr): 21127c478bd9Sstevel@tonic-gate PBM_AFSR_TO_SECERR(pbm_err_p->pbm_afsr); 21137c478bd9Sstevel@tonic-gate 21147c478bd9Sstevel@tonic-gate for (i = 0; pbm_err_tbl[i].pbm_err_class != NULL; i++) { 21157c478bd9Sstevel@tonic-gate if ((err & pbm_err_tbl[i].pbm_reg_bit) && 21167c478bd9Sstevel@tonic-gate (pbm_err_p->pbm_pri == pbm_err_tbl[i].pbm_pri)) { 21177c478bd9Sstevel@tonic-gate if (pbm_err_tbl[i].pbm_flag == FM_LOG_PCI) 21187c478bd9Sstevel@tonic-gate pbm_err_p->pbm_pci.pci_err_class = 21197c478bd9Sstevel@tonic-gate pbm_err_tbl[i].pbm_err_class; 21207c478bd9Sstevel@tonic-gate else 21217c478bd9Sstevel@tonic-gate pbm_err_p->pbm_err_class = 21227c478bd9Sstevel@tonic-gate pbm_err_tbl[i].pbm_err_class; 21237c478bd9Sstevel@tonic-gate 21247c478bd9Sstevel@tonic-gate pbm_err_p->pbm_terr_class = 21257c478bd9Sstevel@tonic-gate pbm_err_tbl[i].pbm_terr_class; 21267c478bd9Sstevel@tonic-gate pbm_err_p->pbm_log = pbm_err_tbl[i].pbm_flag; 21277c478bd9Sstevel@tonic-gate nerr++; 21287c478bd9Sstevel@tonic-gate break; 21297c478bd9Sstevel@tonic-gate } 21307c478bd9Sstevel@tonic-gate } 21317c478bd9Sstevel@tonic-gate 21327c478bd9Sstevel@tonic-gate return (nerr); 21337c478bd9Sstevel@tonic-gate } 21347c478bd9Sstevel@tonic-gate 21357c478bd9Sstevel@tonic-gate /* 21367c478bd9Sstevel@tonic-gate * Function used to handle and log IOMMU errors. Called by pci_pbm_err_handler, 21377c478bd9Sstevel@tonic-gate * with pci_fm_mutex held. 21387c478bd9Sstevel@tonic-gate */ 21397c478bd9Sstevel@tonic-gate static int 21407c478bd9Sstevel@tonic-gate iommu_err_handler(dev_info_t *dip, uint64_t ena, pbm_errstate_t *pbm_err_p) 21417c478bd9Sstevel@tonic-gate { 21427c478bd9Sstevel@tonic-gate pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 21437c478bd9Sstevel@tonic-gate iommu_t *iommu_p = pci_p->pci_iommu_p; 21447c478bd9Sstevel@tonic-gate ecc_t *ecc_p = pci_p->pci_ecc_p; 21457c478bd9Sstevel@tonic-gate uint64_t stat; 21467c478bd9Sstevel@tonic-gate ushort_t ta_signalled; 21477c478bd9Sstevel@tonic-gate int err = 0; 21487c478bd9Sstevel@tonic-gate int fatal = 0; 21497c478bd9Sstevel@tonic-gate int nonfatal = 0; 21507c478bd9Sstevel@tonic-gate int ret; 21517c478bd9Sstevel@tonic-gate 21527c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&ecc_p->ecc_pci_cmn_p->pci_fm_mutex)); 21537c478bd9Sstevel@tonic-gate if (!((stat = *iommu_p->iommu_ctrl_reg) & TOMATILLO_IOMMU_ERR)) { 21547c478bd9Sstevel@tonic-gate pbm_err_p->pbm_err_class = PCI_SCH_MMU_ERR; 21557c478bd9Sstevel@tonic-gate iommu_ereport_post(dip, ena, pbm_err_p); 21567c478bd9Sstevel@tonic-gate return (DDI_FM_NONFATAL); 21577c478bd9Sstevel@tonic-gate } 21587c478bd9Sstevel@tonic-gate 21597c478bd9Sstevel@tonic-gate /* 21607c478bd9Sstevel@tonic-gate * Need to make sure a Target Abort was signalled to the device if 21617c478bd9Sstevel@tonic-gate * we have any hope of recovering. Tomatillo does not send a TA for 21627c478bd9Sstevel@tonic-gate * DMA Writes that result in a Translation Error, thus fooling the 21637c478bd9Sstevel@tonic-gate * device into believing everything is as it expects. Ignorance 21647c478bd9Sstevel@tonic-gate * is bliss, but knowledge is power. 21657c478bd9Sstevel@tonic-gate */ 21667c478bd9Sstevel@tonic-gate ta_signalled = pbm_err_p->pbm_pci.pci_cfg_stat & 21677c478bd9Sstevel@tonic-gate PCI_STAT_S_TARG_AB; 21687c478bd9Sstevel@tonic-gate 21697c478bd9Sstevel@tonic-gate if (stat & TOMATILLO_IOMMU_ERR_ILLTSBTBW) { 21707c478bd9Sstevel@tonic-gate pbm_err_p->pbm_err_class = PCI_TOM_MMU_BAD_TSBTBW; 21717c478bd9Sstevel@tonic-gate err = 1; 21727c478bd9Sstevel@tonic-gate iommu_ereport_post(dip, ena, pbm_err_p); 21737c478bd9Sstevel@tonic-gate if (!ta_signalled) 21747c478bd9Sstevel@tonic-gate fatal++; 21757c478bd9Sstevel@tonic-gate else 21767c478bd9Sstevel@tonic-gate nonfatal++; 21777c478bd9Sstevel@tonic-gate } 21787c478bd9Sstevel@tonic-gate 21797c478bd9Sstevel@tonic-gate if (stat & TOMATILLO_IOMMU_ERR_BAD_VA) { 21807c478bd9Sstevel@tonic-gate pbm_err_p->pbm_err_class = PCI_TOM_MMU_BAD_VA; 21817c478bd9Sstevel@tonic-gate err = 1; 21827c478bd9Sstevel@tonic-gate iommu_ereport_post(dip, ena, pbm_err_p); 21837c478bd9Sstevel@tonic-gate if (!ta_signalled) 21847c478bd9Sstevel@tonic-gate fatal++; 21857c478bd9Sstevel@tonic-gate else 21867c478bd9Sstevel@tonic-gate nonfatal++; 21877c478bd9Sstevel@tonic-gate } 21887c478bd9Sstevel@tonic-gate 21897c478bd9Sstevel@tonic-gate if (!err) { 21907c478bd9Sstevel@tonic-gate stat = ((stat & TOMATILLO_IOMMU_ERRSTS) >> 21917c478bd9Sstevel@tonic-gate TOMATILLO_IOMMU_ERRSTS_SHIFT); 21927c478bd9Sstevel@tonic-gate switch (stat) { 21937c478bd9Sstevel@tonic-gate case TOMATILLO_IOMMU_PROTECTION_ERR: 21947c478bd9Sstevel@tonic-gate pbm_err_p->pbm_err_class = PCI_TOM_MMU_PROT_ERR; 21957c478bd9Sstevel@tonic-gate iommu_ereport_post(dip, ena, pbm_err_p); 21967c478bd9Sstevel@tonic-gate fatal++; 21977c478bd9Sstevel@tonic-gate break; 21987c478bd9Sstevel@tonic-gate case TOMATILLO_IOMMU_INVALID_ERR: 21997c478bd9Sstevel@tonic-gate pbm_err_p->pbm_err_class = PCI_TOM_MMU_INVAL_ERR; 22007c478bd9Sstevel@tonic-gate /* 22017c478bd9Sstevel@tonic-gate * Fault the address in iommu_tfar 22027c478bd9Sstevel@tonic-gate * register to inform target driver of error 22037c478bd9Sstevel@tonic-gate */ 220400d0963fSdilpreet ret = ndi_fmc_error(pci_p->pci_dip, NULL, DMA_HANDLE, 22057c478bd9Sstevel@tonic-gate ena, (void *)&pbm_err_p->pbm_iommu.iommu_tfar); 22067c478bd9Sstevel@tonic-gate 220700d0963fSdilpreet if (ret != DDI_FM_NONFATAL) 22087c478bd9Sstevel@tonic-gate if (ta_signalled) 22097c478bd9Sstevel@tonic-gate nonfatal++; 22107c478bd9Sstevel@tonic-gate else 22117c478bd9Sstevel@tonic-gate fatal++; 22127c478bd9Sstevel@tonic-gate else 221300d0963fSdilpreet nonfatal++; 221400d0963fSdilpreet 22157c478bd9Sstevel@tonic-gate iommu_ereport_post(dip, ena, pbm_err_p); 22167c478bd9Sstevel@tonic-gate break; 22177c478bd9Sstevel@tonic-gate case TOMATILLO_IOMMU_TIMEOUT_ERR: 22187c478bd9Sstevel@tonic-gate pbm_err_p->pbm_err_class = PCI_TOM_MMU_TO_ERR; 22197c478bd9Sstevel@tonic-gate fatal++; 22207c478bd9Sstevel@tonic-gate iommu_ereport_post(dip, ena, pbm_err_p); 22217c478bd9Sstevel@tonic-gate break; 22227c478bd9Sstevel@tonic-gate case TOMATILLO_IOMMU_ECC_ERR: 22237c478bd9Sstevel@tonic-gate pbm_err_p->pbm_err_class = PCI_TOM_MMU_UE; 22247c478bd9Sstevel@tonic-gate iommu_ereport_post(dip, ena, pbm_err_p); 22257c478bd9Sstevel@tonic-gate break; 22267c478bd9Sstevel@tonic-gate } 22277c478bd9Sstevel@tonic-gate } 22287c478bd9Sstevel@tonic-gate 22297c478bd9Sstevel@tonic-gate if (fatal) 22307c478bd9Sstevel@tonic-gate return (DDI_FM_FATAL); 22317c478bd9Sstevel@tonic-gate else if (nonfatal) 22327c478bd9Sstevel@tonic-gate return (DDI_FM_NONFATAL); 22337c478bd9Sstevel@tonic-gate 22347c478bd9Sstevel@tonic-gate return (DDI_FM_OK); 22357c478bd9Sstevel@tonic-gate } 22367c478bd9Sstevel@tonic-gate 22377c478bd9Sstevel@tonic-gate int 22387c478bd9Sstevel@tonic-gate pci_check_error(pci_t *pci_p) 22397c478bd9Sstevel@tonic-gate { 22407c478bd9Sstevel@tonic-gate pbm_t *pbm_p = pci_p->pci_pbm_p; 22417c478bd9Sstevel@tonic-gate uint16_t pci_cfg_stat; 22427c478bd9Sstevel@tonic-gate uint64_t pbm_ctl_stat, pbm_afsr, pbm_pcix_stat; 22437c478bd9Sstevel@tonic-gate caddr_t a = pci_p->pci_address[0]; 22447c478bd9Sstevel@tonic-gate uint64_t *pbm_pcix_stat_reg; 22457c478bd9Sstevel@tonic-gate 22467c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&pci_p->pci_common_p->pci_fm_mutex)); 22477c478bd9Sstevel@tonic-gate 22487c478bd9Sstevel@tonic-gate pci_cfg_stat = pbm_p->pbm_config_header->ch_status_reg; 22497c478bd9Sstevel@tonic-gate pbm_ctl_stat = *pbm_p->pbm_ctrl_reg; 22507c478bd9Sstevel@tonic-gate pbm_afsr = *pbm_p->pbm_async_flt_status_reg; 22517c478bd9Sstevel@tonic-gate 22527c478bd9Sstevel@tonic-gate if ((pci_cfg_stat & (PCI_STAT_S_PERROR | PCI_STAT_S_TARG_AB | 22537c478bd9Sstevel@tonic-gate PCI_STAT_R_TARG_AB | PCI_STAT_R_MAST_AB | 22547c478bd9Sstevel@tonic-gate PCI_STAT_S_SYSERR | PCI_STAT_PERROR)) || 22557c478bd9Sstevel@tonic-gate (pbm_ctl_stat & (SCHIZO_PCI_CTRL_BUS_UNUSABLE | 22567c478bd9Sstevel@tonic-gate TOMATILLO_PCI_CTRL_PCI_DTO_ERR | 22577c478bd9Sstevel@tonic-gate SCHIZO_PCI_CTRL_PCI_TTO_ERR | 22587c478bd9Sstevel@tonic-gate SCHIZO_PCI_CTRL_PCI_RTRY_ERR | 22597c478bd9Sstevel@tonic-gate SCHIZO_PCI_CTRL_PCI_MMU_ERR | 22607c478bd9Sstevel@tonic-gate COMMON_PCI_CTRL_SBH_ERR | 22617c478bd9Sstevel@tonic-gate COMMON_PCI_CTRL_SERR)) || 22627c478bd9Sstevel@tonic-gate (PBM_AFSR_TO_PRIERR(pbm_afsr))) 22637c478bd9Sstevel@tonic-gate return (1); 22647c478bd9Sstevel@tonic-gate 22657c478bd9Sstevel@tonic-gate if ((CHIP_TYPE(pci_p) == PCI_CHIP_XMITS) && 22667c478bd9Sstevel@tonic-gate (pbm_ctl_stat & XMITS_PCI_CTRL_X_MODE)) { 22677c478bd9Sstevel@tonic-gate 22687c478bd9Sstevel@tonic-gate pbm_pcix_stat_reg = (uint64_t *)(a + 22697c478bd9Sstevel@tonic-gate XMITS_PCI_X_ERROR_STATUS_REG_OFFSET); 22707c478bd9Sstevel@tonic-gate 22717c478bd9Sstevel@tonic-gate pbm_pcix_stat = *pbm_pcix_stat_reg; 22727c478bd9Sstevel@tonic-gate 22737c478bd9Sstevel@tonic-gate if (PBM_PCIX_TO_PRIERR(pbm_pcix_stat)) 22747c478bd9Sstevel@tonic-gate return (1); 22757c478bd9Sstevel@tonic-gate 22767c478bd9Sstevel@tonic-gate if (pbm_pcix_stat & XMITS_PCIX_STAT_PERR_RECOV_INT) 22777c478bd9Sstevel@tonic-gate return (1); 22787c478bd9Sstevel@tonic-gate } 22797c478bd9Sstevel@tonic-gate 22807c478bd9Sstevel@tonic-gate return (0); 22817c478bd9Sstevel@tonic-gate 22827c478bd9Sstevel@tonic-gate } 22837c478bd9Sstevel@tonic-gate 22847c478bd9Sstevel@tonic-gate static pbm_fm_err_t pci_pbm_err_tbl[] = { 22857c478bd9Sstevel@tonic-gate PCI_PBM_RETRY, SCHIZO_PCI_CTRL_PCI_RTRY_ERR, 22867c478bd9Sstevel@tonic-gate NULL, PBM_NONFATAL, PCI_PBM_TARG_RETRY, 22877c478bd9Sstevel@tonic-gate 22887c478bd9Sstevel@tonic-gate PCI_PBM_TTO, SCHIZO_PCI_CTRL_PCI_TTO_ERR, 22897c478bd9Sstevel@tonic-gate NULL, PBM_NONFATAL, PCI_PBM_TARG_TTO, 22907c478bd9Sstevel@tonic-gate 22917c478bd9Sstevel@tonic-gate PCI_SCH_BUS_UNUSABLE_ERR, SCHIZO_PCI_CTRL_BUS_UNUSABLE, 22927c478bd9Sstevel@tonic-gate NULL, PBM_NONFATAL, NULL, 22937c478bd9Sstevel@tonic-gate 22947c478bd9Sstevel@tonic-gate NULL, NULL, 22957c478bd9Sstevel@tonic-gate NULL, NULL, NULL 22967c478bd9Sstevel@tonic-gate }; 22977c478bd9Sstevel@tonic-gate 22987c478bd9Sstevel@tonic-gate /* 22997c478bd9Sstevel@tonic-gate * Function used to log all PCI/PBM/IOMMU errors found in the system. 23007c478bd9Sstevel@tonic-gate * It is called by the pbm_error_intr as well as the pci_err_callback(trap 23017c478bd9Sstevel@tonic-gate * callback). To protect access we hold the pci_fm_mutex when calling 23027c478bd9Sstevel@tonic-gate * this function. 23037c478bd9Sstevel@tonic-gate */ 23047c478bd9Sstevel@tonic-gate int 23057c478bd9Sstevel@tonic-gate pci_pbm_err_handler(dev_info_t *dip, ddi_fm_error_t *derr, 23067c478bd9Sstevel@tonic-gate const void *impl_data, int caller) 23077c478bd9Sstevel@tonic-gate { 23087c478bd9Sstevel@tonic-gate int fatal = 0; 23097c478bd9Sstevel@tonic-gate int nonfatal = 0; 23107c478bd9Sstevel@tonic-gate int unknown = 0; 23117c478bd9Sstevel@tonic-gate uint32_t prierr, secerr; 23127c478bd9Sstevel@tonic-gate pbm_errstate_t pbm_err; 23137c478bd9Sstevel@tonic-gate char buf[FM_MAX_CLASS]; 23147c478bd9Sstevel@tonic-gate pci_t *pci_p = (pci_t *)impl_data; 23157c478bd9Sstevel@tonic-gate pbm_t *pbm_p = pci_p->pci_pbm_p; 23167c478bd9Sstevel@tonic-gate int i, ret = 0; 23177c478bd9Sstevel@tonic-gate 23187c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&pci_p->pci_common_p->pci_fm_mutex)); 23197c478bd9Sstevel@tonic-gate pci_pbm_errstate_get(pci_p, &pbm_err); 23207c478bd9Sstevel@tonic-gate 23217c478bd9Sstevel@tonic-gate derr->fme_ena = derr->fme_ena ? derr->fme_ena : 23227c478bd9Sstevel@tonic-gate fm_ena_generate(0, FM_ENA_FMT1); 23237c478bd9Sstevel@tonic-gate 23247c478bd9Sstevel@tonic-gate prierr = PBM_AFSR_TO_PRIERR(pbm_err.pbm_afsr); 23257c478bd9Sstevel@tonic-gate secerr = PBM_AFSR_TO_SECERR(pbm_err.pbm_afsr); 23267c478bd9Sstevel@tonic-gate 23277c478bd9Sstevel@tonic-gate if (derr->fme_flag == DDI_FM_ERR_EXPECTED) { 23287c478bd9Sstevel@tonic-gate if (caller == PCI_TRAP_CALL) { 23297c478bd9Sstevel@tonic-gate /* 23307c478bd9Sstevel@tonic-gate * For ddi_caut_get treat all events as nonfatal. 23317c478bd9Sstevel@tonic-gate * The trampoline will set err_ena = 0, err_status = 23327c478bd9Sstevel@tonic-gate * NONFATAL. We only really call this function so that 23337c478bd9Sstevel@tonic-gate * pci_clear_error() and ndi_fm_handler_dispatch() will 23347c478bd9Sstevel@tonic-gate * get called. 23357c478bd9Sstevel@tonic-gate */ 23367c478bd9Sstevel@tonic-gate derr->fme_status = DDI_FM_NONFATAL; 23377c478bd9Sstevel@tonic-gate nonfatal++; 23387c478bd9Sstevel@tonic-gate goto done; 23397c478bd9Sstevel@tonic-gate } else { 23407c478bd9Sstevel@tonic-gate /* 23417c478bd9Sstevel@tonic-gate * For ddi_caut_put treat all events as nonfatal. Here 23427c478bd9Sstevel@tonic-gate * we have the handle and can call ndi_fm_acc_err_set(). 23437c478bd9Sstevel@tonic-gate */ 23447c478bd9Sstevel@tonic-gate derr->fme_status = DDI_FM_NONFATAL; 23457c478bd9Sstevel@tonic-gate ndi_fm_acc_err_set(pbm_p->pbm_excl_handle, derr); 23467c478bd9Sstevel@tonic-gate nonfatal++; 23477c478bd9Sstevel@tonic-gate goto done; 23487c478bd9Sstevel@tonic-gate } 23497c478bd9Sstevel@tonic-gate } else if (derr->fme_flag == DDI_FM_ERR_PEEK) { 23507c478bd9Sstevel@tonic-gate /* 23517c478bd9Sstevel@tonic-gate * For ddi_peek treat all events as nonfatal. We only 23527c478bd9Sstevel@tonic-gate * really call this function so that pci_clear_error() 23537c478bd9Sstevel@tonic-gate * and ndi_fm_handler_dispatch() will get called. 23547c478bd9Sstevel@tonic-gate */ 23557c478bd9Sstevel@tonic-gate nonfatal++; 23567c478bd9Sstevel@tonic-gate goto done; 23577c478bd9Sstevel@tonic-gate } else if (derr->fme_flag == DDI_FM_ERR_POKE) { 23587c478bd9Sstevel@tonic-gate /* 23597c478bd9Sstevel@tonic-gate * For ddi_poke we can treat as nonfatal if the 23607c478bd9Sstevel@tonic-gate * following conditions are met : 23617c478bd9Sstevel@tonic-gate * 1. Make sure only primary error is MA/TA 23627c478bd9Sstevel@tonic-gate * 2. Make sure no secondary error bits set 23637c478bd9Sstevel@tonic-gate * 3. check pci config header stat reg to see MA/TA is 23647c478bd9Sstevel@tonic-gate * logged. We cannot verify only MA/TA is recorded 23657c478bd9Sstevel@tonic-gate * since it gets much more complicated when a 23667c478bd9Sstevel@tonic-gate * PCI-to-PCI bridge is present. 23677c478bd9Sstevel@tonic-gate */ 23687c478bd9Sstevel@tonic-gate if ((prierr == SCHIZO_PCI_AFSR_E_MA) && !secerr && 23697c478bd9Sstevel@tonic-gate (pbm_err.pbm_pci.pci_cfg_stat & PCI_STAT_R_MAST_AB)) { 23707c478bd9Sstevel@tonic-gate nonfatal++; 23717c478bd9Sstevel@tonic-gate goto done; 23727c478bd9Sstevel@tonic-gate } else if ((*pbm_p->pbm_ctrl_reg & XMITS_PCI_CTRL_X_MODE) && 23737c478bd9Sstevel@tonic-gate pcix_ma_behind_bridge(&pbm_err)) { 23747c478bd9Sstevel@tonic-gate /* 23757c478bd9Sstevel@tonic-gate * MAs behind a PCI-X bridge get sent back to 23767c478bd9Sstevel@tonic-gate * the host as a Split Completion Error Message. 23777c478bd9Sstevel@tonic-gate * We handle this the same as the above check. 23787c478bd9Sstevel@tonic-gate */ 23797c478bd9Sstevel@tonic-gate nonfatal++; 23807c478bd9Sstevel@tonic-gate goto done; 23817c478bd9Sstevel@tonic-gate } 23827c478bd9Sstevel@tonic-gate if ((prierr == SCHIZO_PCI_AFSR_E_TA) && !secerr && 23837c478bd9Sstevel@tonic-gate (pbm_err.pbm_pci.pci_cfg_stat & PCI_STAT_R_TARG_AB)) { 23847c478bd9Sstevel@tonic-gate nonfatal++; 23857c478bd9Sstevel@tonic-gate goto done; 23867c478bd9Sstevel@tonic-gate } 23877c478bd9Sstevel@tonic-gate } 23887c478bd9Sstevel@tonic-gate 23897c478bd9Sstevel@tonic-gate DEBUG2(DBG_ERR_INTR, dip, "pci_pbm_err_handler: prierr=0x%x " 23907c478bd9Sstevel@tonic-gate "secerr=0x%x", prierr, secerr); 23917c478bd9Sstevel@tonic-gate 23927c478bd9Sstevel@tonic-gate if (prierr || secerr) { 23937c478bd9Sstevel@tonic-gate ret = pbm_afsr_report(dip, derr->fme_ena, &pbm_err); 23947c478bd9Sstevel@tonic-gate if (ret == DDI_FM_FATAL) 23957c478bd9Sstevel@tonic-gate fatal++; 23967c478bd9Sstevel@tonic-gate else 23977c478bd9Sstevel@tonic-gate nonfatal++; 23987c478bd9Sstevel@tonic-gate } 23997c478bd9Sstevel@tonic-gate if ((ret = pcix_log_pbm(pci_p, derr->fme_ena, &pbm_err)) 24007c478bd9Sstevel@tonic-gate == DDI_FM_FATAL) 24017c478bd9Sstevel@tonic-gate fatal++; 24027c478bd9Sstevel@tonic-gate else if (ret == DDI_FM_NONFATAL) 24037c478bd9Sstevel@tonic-gate nonfatal++; 24047c478bd9Sstevel@tonic-gate 24057c478bd9Sstevel@tonic-gate if ((ret = pci_cfg_report(dip, derr, &pbm_err.pbm_pci, caller, prierr)) 24067c478bd9Sstevel@tonic-gate == DDI_FM_FATAL) 24077c478bd9Sstevel@tonic-gate fatal++; 24087c478bd9Sstevel@tonic-gate else if (ret == DDI_FM_NONFATAL) 24097c478bd9Sstevel@tonic-gate nonfatal++; 24107c478bd9Sstevel@tonic-gate 24117c478bd9Sstevel@tonic-gate for (i = 0; pci_pbm_err_tbl[i].pbm_err_class != NULL; i++) { 24127c478bd9Sstevel@tonic-gate if ((pbm_err.pbm_ctl_stat & pci_pbm_err_tbl[i].pbm_reg_bit) && 24137c478bd9Sstevel@tonic-gate !prierr) { 24147c478bd9Sstevel@tonic-gate pbm_err.pbm_err_class = 24157c478bd9Sstevel@tonic-gate pci_pbm_err_tbl[i].pbm_err_class; 24167c478bd9Sstevel@tonic-gate pbm_ereport_post(dip, derr->fme_ena, &pbm_err); 24177c478bd9Sstevel@tonic-gate if (pci_pbm_err_tbl[i].pbm_flag) 24187c478bd9Sstevel@tonic-gate fatal++; 24197c478bd9Sstevel@tonic-gate else 24207c478bd9Sstevel@tonic-gate nonfatal++; 24217c478bd9Sstevel@tonic-gate if (caller == PCI_TRAP_CALL && 242200d0963fSdilpreet pci_pbm_err_tbl[i].pbm_terr_class) 242300d0963fSdilpreet pci_target_enqueue(derr->fme_ena, 242400d0963fSdilpreet pci_pbm_err_tbl[i].pbm_terr_class, 242500d0963fSdilpreet pbm_err.pbm_bridge_type, 242600d0963fSdilpreet (uint64_t)derr->fme_bus_specific); 24277c478bd9Sstevel@tonic-gate } 24287c478bd9Sstevel@tonic-gate } 24297c478bd9Sstevel@tonic-gate 24307c478bd9Sstevel@tonic-gate if ((pbm_err.pbm_ctl_stat & COMMON_PCI_CTRL_SBH_ERR) && 24317c478bd9Sstevel@tonic-gate (CHIP_TYPE(pci_p) != PCI_CHIP_TOMATILLO)) { 24327c478bd9Sstevel@tonic-gate pbm_err.pbm_err_class = PCI_SCH_SBH; 24337c478bd9Sstevel@tonic-gate pbm_ereport_post(dip, derr->fme_ena, &pbm_err); 24347c478bd9Sstevel@tonic-gate if (pci_panic_on_sbh_errors) 24357c478bd9Sstevel@tonic-gate fatal++; 24367c478bd9Sstevel@tonic-gate else 24377c478bd9Sstevel@tonic-gate nonfatal++; 24387c478bd9Sstevel@tonic-gate } 24397c478bd9Sstevel@tonic-gate 24407c478bd9Sstevel@tonic-gate /* 24417c478bd9Sstevel@tonic-gate * PBM Received System Error - During any transaction, or 24427c478bd9Sstevel@tonic-gate * at any point on the bus, some device may detect a critical 24437c478bd9Sstevel@tonic-gate * error and signal a system error to the system. 24447c478bd9Sstevel@tonic-gate */ 24457c478bd9Sstevel@tonic-gate if (pbm_err.pbm_ctl_stat & COMMON_PCI_CTRL_SERR) { 24467c478bd9Sstevel@tonic-gate /* 24477c478bd9Sstevel@tonic-gate * may be expected (master abort from pci-pci bridge during 24487c478bd9Sstevel@tonic-gate * poke will generate SERR) 24497c478bd9Sstevel@tonic-gate */ 24507c478bd9Sstevel@tonic-gate if (derr->fme_flag != DDI_FM_ERR_POKE) { 24517c478bd9Sstevel@tonic-gate DEBUG1(DBG_ERR_INTR, dip, "pci_pbm_err_handler: " 24527c478bd9Sstevel@tonic-gate "ereport_post: %s", buf); 24537c478bd9Sstevel@tonic-gate (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", 24547c478bd9Sstevel@tonic-gate PCI_ERROR_SUBCLASS, PCI_REC_SERR); 24557c478bd9Sstevel@tonic-gate ddi_fm_ereport_post(dip, buf, derr->fme_ena, 24567c478bd9Sstevel@tonic-gate DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 24577c478bd9Sstevel@tonic-gate PCI_CONFIG_STATUS, DATA_TYPE_UINT16, 24587c478bd9Sstevel@tonic-gate pbm_err.pbm_pci.pci_cfg_stat, PCI_CONFIG_COMMAND, 24597c478bd9Sstevel@tonic-gate DATA_TYPE_UINT16, pbm_err.pbm_pci.pci_cfg_comm, 24607c478bd9Sstevel@tonic-gate PCI_PA, DATA_TYPE_UINT64, (uint64_t)0, NULL); 24617c478bd9Sstevel@tonic-gate } 246200d0963fSdilpreet unknown++; 24637c478bd9Sstevel@tonic-gate } 24647c478bd9Sstevel@tonic-gate 24657c478bd9Sstevel@tonic-gate /* 24667c478bd9Sstevel@tonic-gate * PCI Retry Timeout - Device fails to retry deferred 24677c478bd9Sstevel@tonic-gate * transaction within timeout. Only Tomatillo 24687c478bd9Sstevel@tonic-gate */ 24697c478bd9Sstevel@tonic-gate if (pbm_err.pbm_ctl_stat & TOMATILLO_PCI_CTRL_PCI_DTO_ERR) { 24707c478bd9Sstevel@tonic-gate if (pci_dto_fault_warn == CE_PANIC) 24717c478bd9Sstevel@tonic-gate fatal++; 24727c478bd9Sstevel@tonic-gate else 24737c478bd9Sstevel@tonic-gate nonfatal++; 24747c478bd9Sstevel@tonic-gate 24757c478bd9Sstevel@tonic-gate (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", 24767c478bd9Sstevel@tonic-gate PCI_ERROR_SUBCLASS, PCI_DTO); 24777c478bd9Sstevel@tonic-gate ddi_fm_ereport_post(dip, buf, derr->fme_ena, DDI_NOSLEEP, 24787c478bd9Sstevel@tonic-gate FM_VERSION, DATA_TYPE_UINT8, 0, 24797c478bd9Sstevel@tonic-gate PCI_CONFIG_STATUS, DATA_TYPE_UINT16, 24807c478bd9Sstevel@tonic-gate pbm_err.pbm_pci.pci_cfg_stat, 24817c478bd9Sstevel@tonic-gate PCI_CONFIG_COMMAND, DATA_TYPE_UINT16, 24827c478bd9Sstevel@tonic-gate pbm_err.pbm_pci.pci_cfg_comm, 24837c478bd9Sstevel@tonic-gate PCI_PA, DATA_TYPE_UINT64, (uint64_t)0, NULL); 24847c478bd9Sstevel@tonic-gate } 24857c478bd9Sstevel@tonic-gate 24867c478bd9Sstevel@tonic-gate /* 24877c478bd9Sstevel@tonic-gate * PBM Detected Data Parity Error - DPE detected during a DMA Write 24887c478bd9Sstevel@tonic-gate * or PIO Read. Later case is taken care of by cpu_deferred_error 24897c478bd9Sstevel@tonic-gate * and sent here to be logged. 24907c478bd9Sstevel@tonic-gate */ 24917c478bd9Sstevel@tonic-gate if ((pbm_err.pbm_pci.pci_cfg_stat & PCI_STAT_PERROR) && 24927c478bd9Sstevel@tonic-gate !(pbm_err.pbm_pci.pci_cfg_stat & PCI_STAT_S_SYSERR)) { 24937c478bd9Sstevel@tonic-gate /* 24947c478bd9Sstevel@tonic-gate * If we have an address then fault 24957c478bd9Sstevel@tonic-gate * it, if not probe for errant device 24967c478bd9Sstevel@tonic-gate */ 24977c478bd9Sstevel@tonic-gate ret = DDI_FM_FATAL; 24987c478bd9Sstevel@tonic-gate if (caller != PCI_TRAP_CALL) { 249900d0963fSdilpreet if (pbm_err.pbm_va_log) { 250000d0963fSdilpreet ret = ndi_fmc_error(dip, NULL, DMA_HANDLE, 250100d0963fSdilpreet derr->fme_ena, (void *)&pbm_err.pbm_va_log); 250200d0963fSdilpreet } 25037c478bd9Sstevel@tonic-gate if (ret == DDI_FM_NONFATAL) 25047c478bd9Sstevel@tonic-gate nonfatal++; 25057c478bd9Sstevel@tonic-gate else 25067c478bd9Sstevel@tonic-gate fatal++; 25077c478bd9Sstevel@tonic-gate } else 25087c478bd9Sstevel@tonic-gate nonfatal++; 25097c478bd9Sstevel@tonic-gate 25107c478bd9Sstevel@tonic-gate } 25117c478bd9Sstevel@tonic-gate 25127c478bd9Sstevel@tonic-gate /* PBM Detected IOMMU Error */ 25137c478bd9Sstevel@tonic-gate if (pbm_err.pbm_ctl_stat & SCHIZO_PCI_CTRL_PCI_MMU_ERR) { 25147c478bd9Sstevel@tonic-gate if (iommu_err_handler(dip, derr->fme_ena, &pbm_err) 25157c478bd9Sstevel@tonic-gate == DDI_FM_FATAL) 25167c478bd9Sstevel@tonic-gate fatal++; 25177c478bd9Sstevel@tonic-gate else 25187c478bd9Sstevel@tonic-gate nonfatal++; 25197c478bd9Sstevel@tonic-gate } 25207c478bd9Sstevel@tonic-gate 25217c478bd9Sstevel@tonic-gate done: 25227c478bd9Sstevel@tonic-gate ret = ndi_fm_handler_dispatch(dip, NULL, derr); 25237c478bd9Sstevel@tonic-gate if (ret == DDI_FM_FATAL) { 25247c478bd9Sstevel@tonic-gate fatal++; 25257c478bd9Sstevel@tonic-gate } else if (ret == DDI_FM_NONFATAL) { 25267c478bd9Sstevel@tonic-gate nonfatal++; 25277c478bd9Sstevel@tonic-gate } else if (ret == DDI_FM_UNKNOWN) { 25287c478bd9Sstevel@tonic-gate unknown++; 25297c478bd9Sstevel@tonic-gate } 25307c478bd9Sstevel@tonic-gate 25317c478bd9Sstevel@tonic-gate /* 25327c478bd9Sstevel@tonic-gate * RSERR not claimed as nonfatal by a child is considered fatal 25337c478bd9Sstevel@tonic-gate */ 253400d0963fSdilpreet if (unknown && !fatal && !nonfatal) 25357c478bd9Sstevel@tonic-gate fatal++; 25367c478bd9Sstevel@tonic-gate 25377c478bd9Sstevel@tonic-gate /* Cleanup and reset error bits */ 25387c478bd9Sstevel@tonic-gate pci_clear_error(pci_p, &pbm_err); 25397c478bd9Sstevel@tonic-gate 25407c478bd9Sstevel@tonic-gate return (fatal ? DDI_FM_FATAL : (nonfatal ? DDI_FM_NONFATAL : 25417c478bd9Sstevel@tonic-gate (unknown ? DDI_FM_UNKNOWN : DDI_FM_OK))); 25427c478bd9Sstevel@tonic-gate } 25437c478bd9Sstevel@tonic-gate 25447c478bd9Sstevel@tonic-gate /* 25457c478bd9Sstevel@tonic-gate * Function returns TRUE if a Primary error is Split Completion Error 25467c478bd9Sstevel@tonic-gate * that indicates a Master Abort occured behind a PCI-X bridge. 25477c478bd9Sstevel@tonic-gate * This function should only be called for busses running in PCI-X mode. 25487c478bd9Sstevel@tonic-gate */ 25497c478bd9Sstevel@tonic-gate static int 25507c478bd9Sstevel@tonic-gate pcix_ma_behind_bridge(pbm_errstate_t *pbm_err_p) 25517c478bd9Sstevel@tonic-gate { 25527c478bd9Sstevel@tonic-gate uint64_t msg; 25537c478bd9Sstevel@tonic-gate 25547c478bd9Sstevel@tonic-gate if (pbm_err_p->pbm_afsr & XMITS_PCI_X_AFSR_S_SC_ERR) 25557c478bd9Sstevel@tonic-gate return (0); 25567c478bd9Sstevel@tonic-gate 25577c478bd9Sstevel@tonic-gate if (pbm_err_p->pbm_afsr & XMITS_PCI_X_AFSR_P_SC_ERR) { 25587c478bd9Sstevel@tonic-gate msg = (pbm_err_p->pbm_afsr >> XMITS_PCI_X_P_MSG_SHIFT) & 25597c478bd9Sstevel@tonic-gate XMITS_PCIX_MSG_MASK; 25607c478bd9Sstevel@tonic-gate if (msg & PCIX_CLASS_BRIDGE) 25617c478bd9Sstevel@tonic-gate if (msg & PCIX_BRIDGE_MASTER_ABORT) { 25627c478bd9Sstevel@tonic-gate return (1); 25637c478bd9Sstevel@tonic-gate } 25647c478bd9Sstevel@tonic-gate } 25657c478bd9Sstevel@tonic-gate 25667c478bd9Sstevel@tonic-gate return (0); 25677c478bd9Sstevel@tonic-gate } 25687c478bd9Sstevel@tonic-gate 25697c478bd9Sstevel@tonic-gate /* 25707c478bd9Sstevel@tonic-gate * Function used to gather PBM/PCI/IOMMU error state for the 25717c478bd9Sstevel@tonic-gate * pci_pbm_err_handler and the cb_buserr_intr. This function must be 25727c478bd9Sstevel@tonic-gate * called while pci_fm_mutex is held. 25737c478bd9Sstevel@tonic-gate */ 25747c478bd9Sstevel@tonic-gate static void 25757c478bd9Sstevel@tonic-gate pci_pbm_errstate_get(pci_t *pci_p, pbm_errstate_t *pbm_err_p) 25767c478bd9Sstevel@tonic-gate { 25777c478bd9Sstevel@tonic-gate pbm_t *pbm_p = pci_p->pci_pbm_p; 25787c478bd9Sstevel@tonic-gate iommu_t *iommu_p = pci_p->pci_iommu_p; 25797c478bd9Sstevel@tonic-gate caddr_t a = pci_p->pci_address[0]; 25807c478bd9Sstevel@tonic-gate uint64_t *pbm_pcix_stat_reg; 25817c478bd9Sstevel@tonic-gate 25827c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&pci_p->pci_common_p->pci_fm_mutex)); 25837c478bd9Sstevel@tonic-gate bzero(pbm_err_p, sizeof (pbm_errstate_t)); 25847c478bd9Sstevel@tonic-gate 25857c478bd9Sstevel@tonic-gate /* 25867c478bd9Sstevel@tonic-gate * Capture all pbm error state for later logging 25877c478bd9Sstevel@tonic-gate */ 25887c478bd9Sstevel@tonic-gate pbm_err_p->pbm_bridge_type = PCI_BRIDGE_TYPE(pci_p->pci_common_p); 25897c478bd9Sstevel@tonic-gate 25907c478bd9Sstevel@tonic-gate pbm_err_p->pbm_pci.pci_cfg_stat = 25917c478bd9Sstevel@tonic-gate pbm_p->pbm_config_header->ch_status_reg; 25927c478bd9Sstevel@tonic-gate pbm_err_p->pbm_ctl_stat = *pbm_p->pbm_ctrl_reg; 25937c478bd9Sstevel@tonic-gate pbm_err_p->pbm_afsr = *pbm_p->pbm_async_flt_status_reg; 25947c478bd9Sstevel@tonic-gate pbm_err_p->pbm_afar = *pbm_p->pbm_async_flt_addr_reg; 25957c478bd9Sstevel@tonic-gate pbm_err_p->pbm_iommu.iommu_stat = *iommu_p->iommu_ctrl_reg; 25967c478bd9Sstevel@tonic-gate pbm_err_p->pbm_pci.pci_cfg_comm = 25977c478bd9Sstevel@tonic-gate pbm_p->pbm_config_header->ch_command_reg; 25987c478bd9Sstevel@tonic-gate pbm_err_p->pbm_pci.pci_pa = *pbm_p->pbm_async_flt_addr_reg; 25997c478bd9Sstevel@tonic-gate 26007c478bd9Sstevel@tonic-gate /* 26017c478bd9Sstevel@tonic-gate * Record errant slot for Xmits and Schizo 26027c478bd9Sstevel@tonic-gate * Not stored in Tomatillo 26037c478bd9Sstevel@tonic-gate */ 26047c478bd9Sstevel@tonic-gate if (CHIP_TYPE(pci_p) == PCI_CHIP_XMITS || 26057c478bd9Sstevel@tonic-gate CHIP_TYPE(pci_p) == PCI_CHIP_SCHIZO) { 26067c478bd9Sstevel@tonic-gate pbm_err_p->pbm_err_sl = (pbm_err_p->pbm_ctl_stat & 26077c478bd9Sstevel@tonic-gate SCHIZO_PCI_CTRL_ERR_SLOT) >> 26087c478bd9Sstevel@tonic-gate SCHIZO_PCI_CTRL_ERR_SLOT_SHIFT; 26097c478bd9Sstevel@tonic-gate 26107c478bd9Sstevel@tonic-gate /* 26117c478bd9Sstevel@tonic-gate * The bit 51 on XMITS rev1.0 is same as 26127c478bd9Sstevel@tonic-gate * SCHIZO_PCI_CTRL_ERR_SLOT_LOCK on schizo2.3. But 26137c478bd9Sstevel@tonic-gate * this bit needs to be cleared to be able to latch 26147c478bd9Sstevel@tonic-gate * the slot info on next fault. 26157c478bd9Sstevel@tonic-gate * But in XMITS Rev2.0, this bit indicates a DMA Write 26167c478bd9Sstevel@tonic-gate * Parity error. 26177c478bd9Sstevel@tonic-gate */ 26187c478bd9Sstevel@tonic-gate if (pbm_err_p->pbm_ctl_stat & XMITS_PCI_CTRL_DMA_WR_PERR) { 26197c478bd9Sstevel@tonic-gate if ((PCI_CHIP_ID(pci_p) == XMITS_VER_10) || 26207c478bd9Sstevel@tonic-gate (PCI_CHIP_ID(pci_p) <= SCHIZO_VER_23)) { 26217c478bd9Sstevel@tonic-gate /* 26227c478bd9Sstevel@tonic-gate * top 32 bits are W1C and we just want to 26237c478bd9Sstevel@tonic-gate * clear SLOT_LOCK. Leave bottom 32 bits 26247c478bd9Sstevel@tonic-gate * unchanged 26257c478bd9Sstevel@tonic-gate */ 26267c478bd9Sstevel@tonic-gate *pbm_p->pbm_ctrl_reg = 26277c478bd9Sstevel@tonic-gate pbm_err_p->pbm_ctl_stat & 26287c478bd9Sstevel@tonic-gate (SCHIZO_PCI_CTRL_ERR_SLOT_LOCK | 26297c478bd9Sstevel@tonic-gate 0xffffffff); 26307c478bd9Sstevel@tonic-gate pbm_err_p->pbm_ctl_stat = 26317c478bd9Sstevel@tonic-gate *pbm_p->pbm_ctrl_reg; 26327c478bd9Sstevel@tonic-gate } 26337c478bd9Sstevel@tonic-gate } 26347c478bd9Sstevel@tonic-gate } 26357c478bd9Sstevel@tonic-gate 26367c478bd9Sstevel@tonic-gate /* 26377c478bd9Sstevel@tonic-gate * Tomatillo specific registers 26387c478bd9Sstevel@tonic-gate */ 26397c478bd9Sstevel@tonic-gate if (CHIP_TYPE(pci_p) == PCI_CHIP_TOMATILLO) { 2640f47a9c50Smathue pbm_err_p->pbm_va_log = (uint64_t)va_to_pa( 2641f47a9c50Smathue (void *)(uintptr_t)*(a + TOMATILLO_TGT_ERR_VALOG_OFFSET)); 26427c478bd9Sstevel@tonic-gate pbm_err_p->pbm_iommu.iommu_tfar = *iommu_p->iommu_tfar_reg; 26437c478bd9Sstevel@tonic-gate } 26447c478bd9Sstevel@tonic-gate 26457c478bd9Sstevel@tonic-gate /* 26467c478bd9Sstevel@tonic-gate * Xmits PCI-X register 26477c478bd9Sstevel@tonic-gate */ 26487c478bd9Sstevel@tonic-gate if ((CHIP_TYPE(pci_p) == PCI_CHIP_XMITS) && 26497c478bd9Sstevel@tonic-gate (pbm_err_p->pbm_ctl_stat & XMITS_PCI_CTRL_X_MODE)) { 26507c478bd9Sstevel@tonic-gate 26517c478bd9Sstevel@tonic-gate pbm_pcix_stat_reg = (uint64_t *)(a + 26527c478bd9Sstevel@tonic-gate XMITS_PCI_X_ERROR_STATUS_REG_OFFSET); 26537c478bd9Sstevel@tonic-gate 26547c478bd9Sstevel@tonic-gate pbm_err_p->pbm_pcix_stat = *pbm_pcix_stat_reg; 26557c478bd9Sstevel@tonic-gate pbm_err_p->pbm_pcix_pfar = pbm_err_p->pbm_pcix_stat & 26567c478bd9Sstevel@tonic-gate XMITS_PCI_X_STATUS_PFAR_MASK; 26577c478bd9Sstevel@tonic-gate } 26587c478bd9Sstevel@tonic-gate } 26597c478bd9Sstevel@tonic-gate 26607c478bd9Sstevel@tonic-gate /* 26617c478bd9Sstevel@tonic-gate * Function used to clear PBM/PCI/IOMMU error state after error handling 26627c478bd9Sstevel@tonic-gate * is complete. Only clearing error bits which have been logged. Called by 26637c478bd9Sstevel@tonic-gate * pci_pbm_err_handler and pci_bus_exit. 26647c478bd9Sstevel@tonic-gate */ 26657c478bd9Sstevel@tonic-gate static void 26667c478bd9Sstevel@tonic-gate pci_clear_error(pci_t *pci_p, pbm_errstate_t *pbm_err_p) 26677c478bd9Sstevel@tonic-gate { 26687c478bd9Sstevel@tonic-gate pbm_t *pbm_p = pci_p->pci_pbm_p; 26697c478bd9Sstevel@tonic-gate iommu_t *iommu_p = pci_p->pci_iommu_p; 26707c478bd9Sstevel@tonic-gate 26717c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&pbm_p->pbm_pci_p->pci_common_p->pci_fm_mutex)); 26727c478bd9Sstevel@tonic-gate 26737c478bd9Sstevel@tonic-gate if (*pbm_p->pbm_ctrl_reg & SCHIZO_PCI_CTRL_PCI_MMU_ERR) { 26747c478bd9Sstevel@tonic-gate iommu_tlb_scrub(pci_p->pci_iommu_p, 1); 26757c478bd9Sstevel@tonic-gate } 26767c478bd9Sstevel@tonic-gate pbm_p->pbm_config_header->ch_status_reg = 26777c478bd9Sstevel@tonic-gate pbm_err_p->pbm_pci.pci_cfg_stat; 26787c478bd9Sstevel@tonic-gate *pbm_p->pbm_ctrl_reg = pbm_err_p->pbm_ctl_stat; 26797c478bd9Sstevel@tonic-gate *pbm_p->pbm_async_flt_status_reg = pbm_err_p->pbm_afsr; 26807c478bd9Sstevel@tonic-gate *iommu_p->iommu_ctrl_reg = pbm_err_p->pbm_iommu.iommu_stat; 26817c478bd9Sstevel@tonic-gate } 26827c478bd9Sstevel@tonic-gate 26837c478bd9Sstevel@tonic-gate void 26847c478bd9Sstevel@tonic-gate pbm_clear_error(pbm_t *pbm_p) 26857c478bd9Sstevel@tonic-gate { 26867c478bd9Sstevel@tonic-gate uint64_t pbm_afsr, pbm_ctl_stat; 26877c478bd9Sstevel@tonic-gate 26887c478bd9Sstevel@tonic-gate /* 26897c478bd9Sstevel@tonic-gate * for poke() support - called from POKE_FLUSH. Spin waiting 26907c478bd9Sstevel@tonic-gate * for MA, TA or SERR to be cleared by a pbm_error_intr(). 26917c478bd9Sstevel@tonic-gate * We have to wait for SERR too in case the device is beyond 26927c478bd9Sstevel@tonic-gate * a pci-pci bridge. 26937c478bd9Sstevel@tonic-gate */ 26947c478bd9Sstevel@tonic-gate pbm_ctl_stat = *pbm_p->pbm_ctrl_reg; 26957c478bd9Sstevel@tonic-gate pbm_afsr = *pbm_p->pbm_async_flt_status_reg; 26967c478bd9Sstevel@tonic-gate while (((pbm_afsr >> SCHIZO_PCI_AFSR_PE_SHIFT) & 26977c478bd9Sstevel@tonic-gate (SCHIZO_PCI_AFSR_E_MA | SCHIZO_PCI_AFSR_E_TA)) || 26987c478bd9Sstevel@tonic-gate (pbm_ctl_stat & COMMON_PCI_CTRL_SERR)) { 26997c478bd9Sstevel@tonic-gate pbm_ctl_stat = *pbm_p->pbm_ctrl_reg; 27007c478bd9Sstevel@tonic-gate pbm_afsr = *pbm_p->pbm_async_flt_status_reg; 27017c478bd9Sstevel@tonic-gate } 27027c478bd9Sstevel@tonic-gate } 27037c478bd9Sstevel@tonic-gate 27047c478bd9Sstevel@tonic-gate /* 27057c478bd9Sstevel@tonic-gate * Function used to convert the 32 bit captured PCI error address 27067c478bd9Sstevel@tonic-gate * to the full Safari or Jbus address. This is so we can look this address 27077c478bd9Sstevel@tonic-gate * up in our handle caches. 27087c478bd9Sstevel@tonic-gate */ 27097c478bd9Sstevel@tonic-gate void 27107c478bd9Sstevel@tonic-gate pci_format_addr(dev_info_t *dip, uint64_t *afar, uint64_t afsr) 27117c478bd9Sstevel@tonic-gate { 27127c478bd9Sstevel@tonic-gate pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 27137c478bd9Sstevel@tonic-gate pci_ranges_t *io_range, *mem_range; 27147c478bd9Sstevel@tonic-gate uint64_t err_pa = 0; 27157c478bd9Sstevel@tonic-gate 27167c478bd9Sstevel@tonic-gate if (afsr & SCHIZO_PCI_AFSR_CONF_SPACE) { 27177c478bd9Sstevel@tonic-gate err_pa |= pci_p->pci_ranges->parent_high; 27187c478bd9Sstevel@tonic-gate err_pa = err_pa << 32; 27197c478bd9Sstevel@tonic-gate err_pa |= pci_p->pci_ranges->parent_low; 27207c478bd9Sstevel@tonic-gate } else if (afsr & SCHIZO_PCI_AFSR_IO_SPACE) { 27217c478bd9Sstevel@tonic-gate io_range = pci_p->pci_ranges + 1; 27227c478bd9Sstevel@tonic-gate err_pa |= io_range->parent_high; 27237c478bd9Sstevel@tonic-gate err_pa = err_pa << 32; 27247c478bd9Sstevel@tonic-gate err_pa |= io_range->parent_low; 27257c478bd9Sstevel@tonic-gate } else if (afsr & SCHIZO_PCI_AFSR_MEM_SPACE) { 27267c478bd9Sstevel@tonic-gate mem_range = pci_p->pci_ranges + 2; 27277c478bd9Sstevel@tonic-gate err_pa |= mem_range->parent_high; 27287c478bd9Sstevel@tonic-gate err_pa = err_pa << 32; 27297c478bd9Sstevel@tonic-gate err_pa |= mem_range->parent_low; 27307c478bd9Sstevel@tonic-gate } 27317c478bd9Sstevel@tonic-gate *afar |= err_pa; 27327c478bd9Sstevel@tonic-gate } 27337c478bd9Sstevel@tonic-gate 27347c478bd9Sstevel@tonic-gate static ecc_format_t ecc_format_tbl[] = { 27357c478bd9Sstevel@tonic-gate SCH_REG_UPA, NULL, NULL, 27367c478bd9Sstevel@tonic-gate SCH_REG_PCIA_REG, SCHIZO_PCI_AFSR_CONF_SPACE, PCI_SIDEA, 27377c478bd9Sstevel@tonic-gate SCH_REG_PCIA_MEM, SCHIZO_PCI_AFSR_MEM_SPACE, PCI_SIDEA, 27387c478bd9Sstevel@tonic-gate SCH_REG_PCIA_CFGIO, SCHIZO_PCI_AFSR_IO_SPACE, PCI_SIDEA, 27397c478bd9Sstevel@tonic-gate SCH_REG_PCIB_REG, SCHIZO_PCI_AFSR_CONF_SPACE, PCI_SIDEB, 27407c478bd9Sstevel@tonic-gate SCH_REG_PCIB_MEM, SCHIZO_PCI_AFSR_MEM_SPACE, PCI_SIDEB, 27417c478bd9Sstevel@tonic-gate SCH_REG_PCIB_CFGIO, SCHIZO_PCI_AFSR_IO_SPACE, PCI_SIDEB, 27427c478bd9Sstevel@tonic-gate SCH_REG_SAFARI_REGS, NULL, NULL, 27437c478bd9Sstevel@tonic-gate NULL, NULL, NULL, 27447c478bd9Sstevel@tonic-gate }; 27457c478bd9Sstevel@tonic-gate 27467c478bd9Sstevel@tonic-gate /* 27477c478bd9Sstevel@tonic-gate * Function used to convert the 32 bit PIO address captured for a 27487c478bd9Sstevel@tonic-gate * Safari Bus UE(during PIO Rd/Wr) to a full Safari Bus Address. 27497c478bd9Sstevel@tonic-gate */ 27507c478bd9Sstevel@tonic-gate static void 27517c478bd9Sstevel@tonic-gate pci_format_ecc_addr(dev_info_t *dip, uint64_t *afar, ecc_region_t region) 27527c478bd9Sstevel@tonic-gate { 27537c478bd9Sstevel@tonic-gate pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 27547c478bd9Sstevel@tonic-gate pci_common_t *cmn_p = pci_p->pci_common_p; 27557c478bd9Sstevel@tonic-gate cb_t *cb_p = pci_p->pci_cb_p; 27567c478bd9Sstevel@tonic-gate int i, pci_side = 0; 27577c478bd9Sstevel@tonic-gate int swap = 0; 27587c478bd9Sstevel@tonic-gate uint64_t pa = cb_p->cb_base_pa; 27597c478bd9Sstevel@tonic-gate uint64_t flag, schizo_base, pci_csr_base; 27607c478bd9Sstevel@tonic-gate 27617c478bd9Sstevel@tonic-gate if (pci_p == NULL) 27627c478bd9Sstevel@tonic-gate return; 27637c478bd9Sstevel@tonic-gate 27647c478bd9Sstevel@tonic-gate pci_csr_base = va_to_pa(pci_p->pci_address[0]); 27657c478bd9Sstevel@tonic-gate 27667c478bd9Sstevel@tonic-gate /* 27677c478bd9Sstevel@tonic-gate * Using the csr_base address to determine which side 27687c478bd9Sstevel@tonic-gate * we are on. 27697c478bd9Sstevel@tonic-gate */ 27707c478bd9Sstevel@tonic-gate if (pci_csr_base & PCI_SIDE_ADDR_MASK) 27717c478bd9Sstevel@tonic-gate pci_side = 1; 27727c478bd9Sstevel@tonic-gate else 27737c478bd9Sstevel@tonic-gate pci_side = 0; 27747c478bd9Sstevel@tonic-gate 27757c478bd9Sstevel@tonic-gate schizo_base = pa - PBM_CTRL_OFFSET; 27767c478bd9Sstevel@tonic-gate 27777c478bd9Sstevel@tonic-gate for (i = 0; ecc_format_tbl[i].ecc_region != NULL; i++) { 27787c478bd9Sstevel@tonic-gate if (region == ecc_format_tbl[i].ecc_region) { 27797c478bd9Sstevel@tonic-gate flag = ecc_format_tbl[i].ecc_space; 27807c478bd9Sstevel@tonic-gate if (ecc_format_tbl[i].ecc_side != pci_side) 27817c478bd9Sstevel@tonic-gate swap = 1; 27827c478bd9Sstevel@tonic-gate if (region == SCH_REG_SAFARI_REGS) 27837c478bd9Sstevel@tonic-gate *afar |= schizo_base; 27847c478bd9Sstevel@tonic-gate break; 27857c478bd9Sstevel@tonic-gate } 27867c478bd9Sstevel@tonic-gate } 27877c478bd9Sstevel@tonic-gate 27887c478bd9Sstevel@tonic-gate if (swap) { 27897c478bd9Sstevel@tonic-gate pci_p = cmn_p->pci_p[PCI_OTHER_SIDE(pci_p->pci_side)]; 27907c478bd9Sstevel@tonic-gate 27917c478bd9Sstevel@tonic-gate if (pci_p == NULL) 27927c478bd9Sstevel@tonic-gate return; 27937c478bd9Sstevel@tonic-gate } 27947c478bd9Sstevel@tonic-gate pci_format_addr(pci_p->pci_dip, afar, flag); 27957c478bd9Sstevel@tonic-gate } 27967c478bd9Sstevel@tonic-gate 27977c478bd9Sstevel@tonic-gate /* 27987c478bd9Sstevel@tonic-gate * Function used to post control block specific ereports. 27997c478bd9Sstevel@tonic-gate */ 28007c478bd9Sstevel@tonic-gate static void 28017c478bd9Sstevel@tonic-gate cb_ereport_post(dev_info_t *dip, uint64_t ena, cb_errstate_t *cb_err) 28027c478bd9Sstevel@tonic-gate { 28037c478bd9Sstevel@tonic-gate pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 28047c478bd9Sstevel@tonic-gate char buf[FM_MAX_CLASS], dev_path[MAXPATHLEN], *ptr; 28057c478bd9Sstevel@tonic-gate struct i_ddi_fmhdl *fmhdl = DEVI(dip)->devi_fmhdl; 28067c478bd9Sstevel@tonic-gate nvlist_t *ereport, *detector; 28077c478bd9Sstevel@tonic-gate errorq_elem_t *eqep; 28087c478bd9Sstevel@tonic-gate nv_alloc_t *nva; 28097c478bd9Sstevel@tonic-gate 28107c478bd9Sstevel@tonic-gate DEBUG1(DBG_ATTACH, dip, "cb_ereport_post: elog 0x%lx", 28117c478bd9Sstevel@tonic-gate cb_err->cb_elog); 28127c478bd9Sstevel@tonic-gate 28137c478bd9Sstevel@tonic-gate /* 28147c478bd9Sstevel@tonic-gate * We do not use ddi_fm_ereport_post because we need to set a 28157c478bd9Sstevel@tonic-gate * special detector here. Since we do not have a device path for 28167c478bd9Sstevel@tonic-gate * the bridge chip we use what we think it should be to aid in 28177c478bd9Sstevel@tonic-gate * diagnosis. 28187c478bd9Sstevel@tonic-gate */ 28197c478bd9Sstevel@tonic-gate (void) snprintf(buf, FM_MAX_CLASS, "%s.%s.%s", DDI_IO_CLASS, 28207c478bd9Sstevel@tonic-gate cb_err->cb_bridge_type, cb_err->cb_err_class); 28217c478bd9Sstevel@tonic-gate 28227c478bd9Sstevel@tonic-gate ena = ena ? ena : fm_ena_generate(0, FM_ENA_FMT1); 28237c478bd9Sstevel@tonic-gate 28247c478bd9Sstevel@tonic-gate eqep = errorq_reserve(fmhdl->fh_errorq); 28257c478bd9Sstevel@tonic-gate if (eqep == NULL) 28267c478bd9Sstevel@tonic-gate return; 28277c478bd9Sstevel@tonic-gate 28287c478bd9Sstevel@tonic-gate ereport = errorq_elem_nvl(fmhdl->fh_errorq, eqep); 28297c478bd9Sstevel@tonic-gate nva = errorq_elem_nva(fmhdl->fh_errorq, eqep); 28307c478bd9Sstevel@tonic-gate detector = fm_nvlist_create(nva); 28317c478bd9Sstevel@tonic-gate 28327c478bd9Sstevel@tonic-gate ASSERT(ereport); 28337c478bd9Sstevel@tonic-gate ASSERT(nva); 28347c478bd9Sstevel@tonic-gate ASSERT(detector); 28357c478bd9Sstevel@tonic-gate 28367c478bd9Sstevel@tonic-gate ddi_pathname(dip, dev_path); 28377c478bd9Sstevel@tonic-gate ptr = strrchr(dev_path, (int)','); 28387c478bd9Sstevel@tonic-gate 28397c478bd9Sstevel@tonic-gate if (ptr) 28407c478bd9Sstevel@tonic-gate *ptr = '\0'; 28417c478bd9Sstevel@tonic-gate 28427c478bd9Sstevel@tonic-gate fm_fmri_dev_set(detector, FM_DEV_SCHEME_VERSION, NULL, dev_path, NULL); 28437c478bd9Sstevel@tonic-gate 28447c478bd9Sstevel@tonic-gate DEBUG1(DBG_ERR_INTR, dip, "cb_ereport_post: ereport_set: %s", buf); 28457c478bd9Sstevel@tonic-gate 28467c478bd9Sstevel@tonic-gate if (CHIP_TYPE(pci_p) == PCI_CHIP_SCHIZO || 28477c478bd9Sstevel@tonic-gate CHIP_TYPE(pci_p) == PCI_CHIP_XMITS) { 28487c478bd9Sstevel@tonic-gate fm_ereport_set(ereport, FM_EREPORT_VERSION, buf, ena, detector, 28497c478bd9Sstevel@tonic-gate SAFARI_CSR, DATA_TYPE_UINT64, cb_err->cb_csr, 28507c478bd9Sstevel@tonic-gate SAFARI_ERR, DATA_TYPE_UINT64, cb_err->cb_err, 28517c478bd9Sstevel@tonic-gate SAFARI_INTR, DATA_TYPE_UINT64, cb_err->cb_intr, 28527c478bd9Sstevel@tonic-gate SAFARI_ELOG, DATA_TYPE_UINT64, cb_err->cb_elog, 28537c478bd9Sstevel@tonic-gate SAFARI_PCR, DATA_TYPE_UINT64, cb_err->cb_pcr, 28547c478bd9Sstevel@tonic-gate NULL); 28557c478bd9Sstevel@tonic-gate } else if (CHIP_TYPE(pci_p) == PCI_CHIP_TOMATILLO) { 28567c478bd9Sstevel@tonic-gate fm_ereport_set(ereport, FM_EREPORT_VERSION, buf, ena, detector, 28577c478bd9Sstevel@tonic-gate JBUS_CSR, DATA_TYPE_UINT64, cb_err->cb_csr, 28587c478bd9Sstevel@tonic-gate JBUS_ERR, DATA_TYPE_UINT64, cb_err->cb_err, 28597c478bd9Sstevel@tonic-gate JBUS_INTR, DATA_TYPE_UINT64, cb_err->cb_intr, 28607c478bd9Sstevel@tonic-gate JBUS_ELOG, DATA_TYPE_UINT64, cb_err->cb_elog, 28617c478bd9Sstevel@tonic-gate JBUS_PCR, DATA_TYPE_UINT64, cb_err->cb_pcr, 28627c478bd9Sstevel@tonic-gate NULL); 28637c478bd9Sstevel@tonic-gate } 28647c478bd9Sstevel@tonic-gate errorq_commit(fmhdl->fh_errorq, eqep, ERRORQ_ASYNC); 28657c478bd9Sstevel@tonic-gate } 28667c478bd9Sstevel@tonic-gate 28677c478bd9Sstevel@tonic-gate /* 28687c478bd9Sstevel@tonic-gate * Function used to post IOMMU specific ereports. 28697c478bd9Sstevel@tonic-gate */ 28707c478bd9Sstevel@tonic-gate static void 28717c478bd9Sstevel@tonic-gate iommu_ereport_post(dev_info_t *dip, uint64_t ena, pbm_errstate_t *pbm_err) 28727c478bd9Sstevel@tonic-gate { 28737c478bd9Sstevel@tonic-gate char buf[FM_MAX_CLASS]; 28747c478bd9Sstevel@tonic-gate 28757c478bd9Sstevel@tonic-gate (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", 28767c478bd9Sstevel@tonic-gate pbm_err->pbm_bridge_type, pbm_err->pbm_err_class); 28777c478bd9Sstevel@tonic-gate 28787c478bd9Sstevel@tonic-gate ena = ena ? ena : fm_ena_generate(0, FM_ENA_FMT1); 28797c478bd9Sstevel@tonic-gate 28807c478bd9Sstevel@tonic-gate DEBUG1(DBG_ERR_INTR, dip, "iommu_ereport_post: ereport_set: %s", buf); 28817c478bd9Sstevel@tonic-gate 28827c478bd9Sstevel@tonic-gate ddi_fm_ereport_post(dip, buf, ena, DDI_NOSLEEP, 28837c478bd9Sstevel@tonic-gate FM_VERSION, DATA_TYPE_UINT8, 0, 28847c478bd9Sstevel@tonic-gate PCI_CONFIG_STATUS, DATA_TYPE_UINT16, pbm_err->pbm_pci.pci_cfg_stat, 28857c478bd9Sstevel@tonic-gate PCI_CONFIG_COMMAND, DATA_TYPE_UINT16, pbm_err->pbm_pci.pci_cfg_comm, 28867c478bd9Sstevel@tonic-gate PCI_PBM_CSR, DATA_TYPE_UINT64, pbm_err->pbm_ctl_stat, 28877c478bd9Sstevel@tonic-gate PCI_PBM_IOMMU_CTRL, DATA_TYPE_UINT64, pbm_err->pbm_iommu.iommu_stat, 28887c478bd9Sstevel@tonic-gate PCI_PBM_IOMMU_TFAR, DATA_TYPE_UINT64, pbm_err->pbm_iommu.iommu_tfar, 28897c478bd9Sstevel@tonic-gate PCI_PBM_SLOT, DATA_TYPE_UINT64, pbm_err->pbm_err_sl, 28907c478bd9Sstevel@tonic-gate PCI_PBM_VALOG, DATA_TYPE_UINT64, pbm_err->pbm_va_log, 28917c478bd9Sstevel@tonic-gate NULL); 28927c478bd9Sstevel@tonic-gate } 28937c478bd9Sstevel@tonic-gate 28947c478bd9Sstevel@tonic-gate /* 28957c478bd9Sstevel@tonic-gate * Function used to post PCI-X generic ereports. 28967c478bd9Sstevel@tonic-gate * This function needs to be fixed once the Fault Boundary Analysis 28977c478bd9Sstevel@tonic-gate * for PCI-X is conducted. The payload should be made more generic. 28987c478bd9Sstevel@tonic-gate */ 28997c478bd9Sstevel@tonic-gate static void 29007c478bd9Sstevel@tonic-gate pcix_ereport_post(dev_info_t *dip, uint64_t ena, pbm_errstate_t *pbm_err) 29017c478bd9Sstevel@tonic-gate { 29027c478bd9Sstevel@tonic-gate char buf[FM_MAX_CLASS]; 29037c478bd9Sstevel@tonic-gate 290400d0963fSdilpreet (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", 290500d0963fSdilpreet pbm_err->pbm_bridge_type, pbm_err->pbm_err_class); 290600d0963fSdilpreet 29077c478bd9Sstevel@tonic-gate ena = ena ? ena : fm_ena_generate(0, FM_ENA_FMT1); 29087c478bd9Sstevel@tonic-gate 29097c478bd9Sstevel@tonic-gate DEBUG1(DBG_ERR_INTR, dip, "pcix_ereport_post: ereport_post: %s", buf); 29107c478bd9Sstevel@tonic-gate 291100d0963fSdilpreet ddi_fm_ereport_post(dip, buf, ena, DDI_NOSLEEP, 29127c478bd9Sstevel@tonic-gate FM_VERSION, DATA_TYPE_UINT8, 0, 29137c478bd9Sstevel@tonic-gate PCI_CONFIG_STATUS, DATA_TYPE_UINT16, pbm_err->pbm_pci.pci_cfg_stat, 29147c478bd9Sstevel@tonic-gate PCI_CONFIG_COMMAND, DATA_TYPE_UINT16, pbm_err->pbm_pci.pci_cfg_comm, 29157c478bd9Sstevel@tonic-gate PCI_PBM_CSR, DATA_TYPE_UINT64, pbm_err->pbm_ctl_stat, 29167c478bd9Sstevel@tonic-gate PCI_PBM_AFSR, DATA_TYPE_UINT64, pbm_err->pbm_afsr, 29177c478bd9Sstevel@tonic-gate PCI_PBM_AFAR, DATA_TYPE_UINT64, pbm_err->pbm_afar, 29187c478bd9Sstevel@tonic-gate PCI_PBM_SLOT, DATA_TYPE_UINT64, pbm_err->pbm_err_sl, 29197c478bd9Sstevel@tonic-gate PCIX_STAT, DATA_TYPE_UINT64, pbm_err->pbm_pcix_stat, 29207c478bd9Sstevel@tonic-gate PCIX_PFAR, DATA_TYPE_UINT32, pbm_err->pbm_pcix_pfar, 29217c478bd9Sstevel@tonic-gate NULL); 29227c478bd9Sstevel@tonic-gate } 29237c478bd9Sstevel@tonic-gate 29247c478bd9Sstevel@tonic-gate static void 29257c478bd9Sstevel@tonic-gate iommu_ctx_free(iommu_t *iommu_p) 29267c478bd9Sstevel@tonic-gate { 29277c478bd9Sstevel@tonic-gate kmem_free(iommu_p->iommu_ctx_bitmap, IOMMU_CTX_BITMAP_SIZE); 29287c478bd9Sstevel@tonic-gate } 29297c478bd9Sstevel@tonic-gate 29307c478bd9Sstevel@tonic-gate /* 29317c478bd9Sstevel@tonic-gate * iommu_tlb_scrub(): 29327c478bd9Sstevel@tonic-gate * Exam TLB entries through TLB diagnostic registers and look for errors. 29337c478bd9Sstevel@tonic-gate * scrub = 1 : cleanup all error bits in tlb, called in FAULT_RESET case 29347c478bd9Sstevel@tonic-gate * scrub = 0 : log all error conditions to console, FAULT_LOG case 29357c478bd9Sstevel@tonic-gate * In both cases, it returns number of errors found in tlb entries. 29367c478bd9Sstevel@tonic-gate */ 29377c478bd9Sstevel@tonic-gate static int 29387c478bd9Sstevel@tonic-gate iommu_tlb_scrub(iommu_t *iommu_p, int scrub) 29397c478bd9Sstevel@tonic-gate { 29407c478bd9Sstevel@tonic-gate int i, nerr = 0; 29417c478bd9Sstevel@tonic-gate dev_info_t *dip = iommu_p->iommu_pci_p->pci_dip; 29427c478bd9Sstevel@tonic-gate char *neg = "not "; 29437c478bd9Sstevel@tonic-gate 29447c478bd9Sstevel@tonic-gate uint64_t base = (uint64_t)iommu_p->iommu_ctrl_reg - 29457c478bd9Sstevel@tonic-gate COMMON_IOMMU_CTRL_REG_OFFSET; 29467c478bd9Sstevel@tonic-gate 29477c478bd9Sstevel@tonic-gate volatile uint64_t *tlb_tag = (volatile uint64_t *) 29487c478bd9Sstevel@tonic-gate (base + COMMON_IOMMU_TLB_TAG_DIAG_ACC_OFFSET); 29497c478bd9Sstevel@tonic-gate volatile uint64_t *tlb_data = (volatile uint64_t *) 29507c478bd9Sstevel@tonic-gate (base + COMMON_IOMMU_TLB_DATA_DIAG_ACC_OFFSET); 29517c478bd9Sstevel@tonic-gate for (i = 0; i < IOMMU_TLB_ENTRIES; i++) { 29527c478bd9Sstevel@tonic-gate uint64_t tag = tlb_tag[i]; 29537c478bd9Sstevel@tonic-gate uint64_t data = tlb_data[i]; 29547c478bd9Sstevel@tonic-gate uint32_t errstat; 29557c478bd9Sstevel@tonic-gate iopfn_t pfn; 29567c478bd9Sstevel@tonic-gate 29577c478bd9Sstevel@tonic-gate if (!(tag & TLBTAG_ERR_BIT)) 29587c478bd9Sstevel@tonic-gate continue; 29597c478bd9Sstevel@tonic-gate 29607c478bd9Sstevel@tonic-gate pfn = (iopfn_t)(data & TLBDATA_MEMPA_BITS); 29617c478bd9Sstevel@tonic-gate errstat = (uint32_t) 29627c478bd9Sstevel@tonic-gate ((tag & TLBTAG_ERRSTAT_BITS) >> TLBTAG_ERRSTAT_SHIFT); 29637c478bd9Sstevel@tonic-gate if (errstat == TLBTAG_ERRSTAT_INVALID) { 29647c478bd9Sstevel@tonic-gate if (scrub) 29657c478bd9Sstevel@tonic-gate tlb_tag[i] = tlb_data[i] = 0ull; 29667c478bd9Sstevel@tonic-gate } else 29677c478bd9Sstevel@tonic-gate nerr++; 29687c478bd9Sstevel@tonic-gate 29697c478bd9Sstevel@tonic-gate if (scrub) 29707c478bd9Sstevel@tonic-gate continue; 29717c478bd9Sstevel@tonic-gate 29727c478bd9Sstevel@tonic-gate cmn_err(CE_CONT, "%s%d: Error %x on IOMMU TLB entry %x:\n" 2973f47a9c50Smathue "\tContext=%lx %sWritable %sStreamable\n" 2974f47a9c50Smathue "\tPCI Page Size=%sk Address in page %lx\n", 29757c478bd9Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip), errstat, i, 29767c478bd9Sstevel@tonic-gate (tag & TLBTAG_CONTEXT_BITS) >> TLBTAG_CONTEXT_SHIFT, 29777c478bd9Sstevel@tonic-gate (tag & TLBTAG_WRITABLE_BIT) ? "" : neg, 29787c478bd9Sstevel@tonic-gate (tag & TLBTAG_STREAM_BIT) ? "" : neg, 29797c478bd9Sstevel@tonic-gate (tag & TLBTAG_PGSIZE_BIT) ? "64" : "8", 29807c478bd9Sstevel@tonic-gate (tag & TLBTAG_PCIVPN_BITS) << 13); 2981f47a9c50Smathue cmn_err(CE_CONT, "Memory: %sValid %sCacheable Page Frame=%lx\n", 29827c478bd9Sstevel@tonic-gate (data & TLBDATA_VALID_BIT) ? "" : neg, 29837c478bd9Sstevel@tonic-gate (data & TLBDATA_CACHE_BIT) ? "" : neg, pfn); 29847c478bd9Sstevel@tonic-gate } 29857c478bd9Sstevel@tonic-gate return (nerr); 29867c478bd9Sstevel@tonic-gate } 29877c478bd9Sstevel@tonic-gate 29887c478bd9Sstevel@tonic-gate /* 29897c478bd9Sstevel@tonic-gate * pci_iommu_disp: calculates the displacement needed in tomatillo's 29907c478bd9Sstevel@tonic-gate * iommu control register and modifies the control value template 29917c478bd9Sstevel@tonic-gate * from caller. It also clears any error status bit that are new 29927c478bd9Sstevel@tonic-gate * in tomatillo. 29937c478bd9Sstevel@tonic-gate * return value: an 8-bit mask to enable corresponding 512 MB segments 29947c478bd9Sstevel@tonic-gate * suitable for tomatillo's target address register. 29957c478bd9Sstevel@tonic-gate * 0x00: no programming is needed, use existing value from prom 29967c478bd9Sstevel@tonic-gate * 0x60: use segment 5 and 6 to form a 1GB dvma range 29977c478bd9Sstevel@tonic-gate */ 29987c478bd9Sstevel@tonic-gate static uint64_t 29997c478bd9Sstevel@tonic-gate pci_iommu_disp(iommu_t *iommu_p, uint64_t *ctl_p) 30007c478bd9Sstevel@tonic-gate { 30017c478bd9Sstevel@tonic-gate uint64_t ctl_old; 30027c478bd9Sstevel@tonic-gate if (CHIP_TYPE(iommu_p->iommu_pci_p) != PCI_CHIP_TOMATILLO) 30037c478bd9Sstevel@tonic-gate return (0); 30047c478bd9Sstevel@tonic-gate 30057c478bd9Sstevel@tonic-gate ctl_old = *iommu_p->iommu_ctrl_reg; 30067c478bd9Sstevel@tonic-gate /* iommu ctrl reg error bits are W1C */ 30077c478bd9Sstevel@tonic-gate if (ctl_old >> TOMATIILO_IOMMU_ERR_REG_SHIFT) { 3008f47a9c50Smathue cmn_err(CE_WARN, "Tomatillo iommu err: %lx", ctl_old); 30097c478bd9Sstevel@tonic-gate *ctl_p |= (ctl_old >> TOMATIILO_IOMMU_ERR_REG_SHIFT) 30107c478bd9Sstevel@tonic-gate << TOMATIILO_IOMMU_ERR_REG_SHIFT; 30117c478bd9Sstevel@tonic-gate } 30127c478bd9Sstevel@tonic-gate 30137c478bd9Sstevel@tonic-gate if (iommu_p->iommu_tsb_size != TOMATILLO_IOMMU_TSB_MAX) 30147c478bd9Sstevel@tonic-gate return (0); 30157c478bd9Sstevel@tonic-gate 30167c478bd9Sstevel@tonic-gate /* Tomatillo 2.0 and later, and 1GB DVMA range */ 30177c478bd9Sstevel@tonic-gate *ctl_p |= 1 << TOMATILLO_IOMMU_SEG_DISP_SHIFT; 30187c478bd9Sstevel@tonic-gate return (3 << (iommu_p->iommu_dvma_base >> (32 - 3))); 30197c478bd9Sstevel@tonic-gate } 30207c478bd9Sstevel@tonic-gate 30217c478bd9Sstevel@tonic-gate void 30227c478bd9Sstevel@tonic-gate pci_iommu_config(iommu_t *iommu_p, uint64_t iommu_ctl, uint64_t cfgpa) 30237c478bd9Sstevel@tonic-gate { 30247c478bd9Sstevel@tonic-gate uintptr_t pbm_regbase = get_pbm_reg_base(iommu_p->iommu_pci_p); 30257c478bd9Sstevel@tonic-gate volatile uint64_t *pbm_csr_p = (volatile uint64_t *)pbm_regbase; 30267c478bd9Sstevel@tonic-gate volatile uint64_t *tgt_space_p = (volatile uint64_t *)(pbm_regbase | 30277c478bd9Sstevel@tonic-gate (TOMATILLO_TGT_ADDR_SPACE_OFFSET - SCHIZO_PCI_CTRL_REG_OFFSET)); 30287c478bd9Sstevel@tonic-gate volatile uint64_t pbm_ctl = *pbm_csr_p; 30297c478bd9Sstevel@tonic-gate 30307c478bd9Sstevel@tonic-gate volatile uint64_t *iommu_ctl_p = iommu_p->iommu_ctrl_reg; 30317c478bd9Sstevel@tonic-gate volatile uint64_t tsb_bar_val = iommu_p->iommu_tsb_paddr; 30327c478bd9Sstevel@tonic-gate volatile uint64_t *tsb_bar_p = iommu_p->iommu_tsb_base_addr_reg; 30337c478bd9Sstevel@tonic-gate uint64_t mask = pci_iommu_disp(iommu_p, &iommu_ctl); 30347c478bd9Sstevel@tonic-gate 30357c478bd9Sstevel@tonic-gate DEBUG2(DBG_ATTACH, iommu_p->iommu_pci_p->pci_dip, 30367c478bd9Sstevel@tonic-gate "\npci_iommu_config: pbm_csr_p=%llx pbm_ctl=%llx", 30377c478bd9Sstevel@tonic-gate pbm_csr_p, pbm_ctl); 30387c478bd9Sstevel@tonic-gate DEBUG2(DBG_ATTACH|DBG_CONT, iommu_p->iommu_pci_p->pci_dip, 30397c478bd9Sstevel@tonic-gate "\n\tiommu_ctl_p=%llx iommu_ctl=%llx", 30407c478bd9Sstevel@tonic-gate iommu_ctl_p, iommu_ctl); 30417c478bd9Sstevel@tonic-gate DEBUG4(DBG_ATTACH|DBG_CONT, iommu_p->iommu_pci_p->pci_dip, 30427c478bd9Sstevel@tonic-gate "\n\tcfgpa=%llx tgt_space_p=%llx mask=%x tsb=%llx\n", 30437c478bd9Sstevel@tonic-gate cfgpa, tgt_space_p, mask, tsb_bar_val); 30447c478bd9Sstevel@tonic-gate 30457c478bd9Sstevel@tonic-gate if (!cfgpa) 30467c478bd9Sstevel@tonic-gate goto reprog; 30477c478bd9Sstevel@tonic-gate 30487c478bd9Sstevel@tonic-gate /* disable PBM arbiters - turn off bits 0-7 */ 30497c478bd9Sstevel@tonic-gate *pbm_csr_p = (pbm_ctl >> 8) << 8; 30507c478bd9Sstevel@tonic-gate 30517c478bd9Sstevel@tonic-gate /* 30527c478bd9Sstevel@tonic-gate * For non-XMITS, flush any previous writes. This is only 30537c478bd9Sstevel@tonic-gate * necessary for host bridges that may have a USB keywboard 30547c478bd9Sstevel@tonic-gate * attached. XMITS does not. 30557c478bd9Sstevel@tonic-gate */ 30567c478bd9Sstevel@tonic-gate if (!(CHIP_TYPE(iommu_p->iommu_pci_p) == PCI_CHIP_XMITS)) 30577c478bd9Sstevel@tonic-gate (void) ldphysio(cfgpa); 30587c478bd9Sstevel@tonic-gate 30597c478bd9Sstevel@tonic-gate reprog: 30607c478bd9Sstevel@tonic-gate if (mask) 30617c478bd9Sstevel@tonic-gate *tgt_space_p = mask; 30627c478bd9Sstevel@tonic-gate 30637c478bd9Sstevel@tonic-gate *tsb_bar_p = tsb_bar_val; 30647c478bd9Sstevel@tonic-gate *iommu_ctl_p = iommu_ctl; 30657c478bd9Sstevel@tonic-gate 30667c478bd9Sstevel@tonic-gate *pbm_csr_p = pbm_ctl; /* re-enable bus arbitration */ 30677c478bd9Sstevel@tonic-gate pbm_ctl = *pbm_csr_p; /* flush all prev writes */ 30687c478bd9Sstevel@tonic-gate } 30697c478bd9Sstevel@tonic-gate 30707c478bd9Sstevel@tonic-gate 30717c478bd9Sstevel@tonic-gate int 30727c478bd9Sstevel@tonic-gate pci_get_portid(dev_info_t *dip) 30737c478bd9Sstevel@tonic-gate { 30747c478bd9Sstevel@tonic-gate return (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 30757c478bd9Sstevel@tonic-gate "portid", -1)); 30767c478bd9Sstevel@tonic-gate } 30777c478bd9Sstevel@tonic-gate 30787c478bd9Sstevel@tonic-gate /* 30797c478bd9Sstevel@tonic-gate * Schizo Safari Performance Events. 30807c478bd9Sstevel@tonic-gate */ 30817c478bd9Sstevel@tonic-gate pci_kev_mask_t 30827c478bd9Sstevel@tonic-gate schizo_saf_events[] = { 30837c478bd9Sstevel@tonic-gate {"saf_bus_cycles", 0x1}, {"saf_pause_asserted_cycles", 0x2}, 30847c478bd9Sstevel@tonic-gate {"saf_frn_coherent_cmds", 0x3}, {"saf_frn_coherent_hits", 0x4}, 30857c478bd9Sstevel@tonic-gate {"saf_my_coherent_cmds", 0x5}, {"saf_my_coherent_hits", 0x6}, 30867c478bd9Sstevel@tonic-gate {"saf_frn_io_cmds", 0x7}, {"saf_frn_io_hits", 0x8}, 30877c478bd9Sstevel@tonic-gate {"merge_buffer", 0x9}, {"interrupts", 0xa}, 30887c478bd9Sstevel@tonic-gate {"csr_pios", 0xc}, {"upa_pios", 0xd}, 30897c478bd9Sstevel@tonic-gate {"pcia_pios", 0xe}, {"pcib_pios", 0xf}, 30907c478bd9Sstevel@tonic-gate {"saf_pause_seen_cycles", 0x11}, {"dvma_reads", 0x12}, 30917c478bd9Sstevel@tonic-gate {"dvma_writes", 0x13}, {"saf_orq_full_cycles", 0x14}, 30927c478bd9Sstevel@tonic-gate {"saf_data_in_cycles", 0x15}, {"saf_data_out_cycles", 0x16}, 30937c478bd9Sstevel@tonic-gate {"clear_pic", 0x1f} 30947c478bd9Sstevel@tonic-gate }; 30957c478bd9Sstevel@tonic-gate 30967c478bd9Sstevel@tonic-gate 30977c478bd9Sstevel@tonic-gate /* 30987c478bd9Sstevel@tonic-gate * Schizo PCI Performance Events. 30997c478bd9Sstevel@tonic-gate */ 31007c478bd9Sstevel@tonic-gate pci_kev_mask_t 31017c478bd9Sstevel@tonic-gate schizo_pci_events[] = { 31027c478bd9Sstevel@tonic-gate {"dvma_stream_rd", 0x0}, {"dvma_stream_wr", 0x1}, 31037c478bd9Sstevel@tonic-gate {"dvma_const_rd", 0x2}, {"dvma_const_wr", 0x3}, 31047c478bd9Sstevel@tonic-gate {"dvma_stream_buf_mis", 0x4}, {"dvma_cycles", 0x5}, 31057c478bd9Sstevel@tonic-gate {"dvma_wd_xfr", 0x6}, {"pio_cycles", 0x7}, 31067c478bd9Sstevel@tonic-gate {"dvma_tlb_misses", 0x10}, {"interrupts", 0x11}, 31077c478bd9Sstevel@tonic-gate {"saf_inter_nack", 0x12}, {"pio_reads", 0x13}, 31087c478bd9Sstevel@tonic-gate {"pio_writes", 0x14}, {"dvma_rd_buf_timeout", 0x15}, 31097c478bd9Sstevel@tonic-gate {"dvma_rd_rtry_stc", 0x16}, {"dvma_wr_rtry_stc", 0x17}, 31107c478bd9Sstevel@tonic-gate {"dvma_rd_rtry_nonstc", 0x18}, {"dvma_wr_rtry_nonstc", 0x19}, 31117c478bd9Sstevel@tonic-gate {"E*_slow_transitions", 0x1a}, {"E*_slow_cycles_per_64", 0x1b}, 31127c478bd9Sstevel@tonic-gate {"clear_pic", 0x1f} 31137c478bd9Sstevel@tonic-gate }; 31147c478bd9Sstevel@tonic-gate 31157c478bd9Sstevel@tonic-gate 31167c478bd9Sstevel@tonic-gate /* 31177c478bd9Sstevel@tonic-gate * Create the picN kstats for the pci 31187c478bd9Sstevel@tonic-gate * and safari events. 31197c478bd9Sstevel@tonic-gate */ 31207c478bd9Sstevel@tonic-gate void 31217c478bd9Sstevel@tonic-gate pci_kstat_init() 31227c478bd9Sstevel@tonic-gate { 31237c478bd9Sstevel@tonic-gate pci_name_kstat = (pci_ksinfo_t *)kmem_alloc(sizeof (pci_ksinfo_t), 31247c478bd9Sstevel@tonic-gate KM_NOSLEEP); 31257c478bd9Sstevel@tonic-gate 31267c478bd9Sstevel@tonic-gate if (pci_name_kstat == NULL) { 31277c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "pcisch : no space for kstat\n"); 31287c478bd9Sstevel@tonic-gate } else { 31297c478bd9Sstevel@tonic-gate pci_name_kstat->pic_no_evs = 31307c478bd9Sstevel@tonic-gate sizeof (schizo_pci_events) / sizeof (pci_kev_mask_t); 31317c478bd9Sstevel@tonic-gate pci_name_kstat->pic_shift[0] = SCHIZO_SHIFT_PIC0; 31327c478bd9Sstevel@tonic-gate pci_name_kstat->pic_shift[1] = SCHIZO_SHIFT_PIC1; 31337c478bd9Sstevel@tonic-gate pci_create_name_kstat("pcis", 31347c478bd9Sstevel@tonic-gate pci_name_kstat, schizo_pci_events); 31357c478bd9Sstevel@tonic-gate } 31367c478bd9Sstevel@tonic-gate 31377c478bd9Sstevel@tonic-gate saf_name_kstat = (pci_ksinfo_t *)kmem_alloc(sizeof (pci_ksinfo_t), 31387c478bd9Sstevel@tonic-gate KM_NOSLEEP); 31397c478bd9Sstevel@tonic-gate if (saf_name_kstat == NULL) { 31407c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "pcisch : no space for kstat\n"); 31417c478bd9Sstevel@tonic-gate } else { 31427c478bd9Sstevel@tonic-gate saf_name_kstat->pic_no_evs = 31437c478bd9Sstevel@tonic-gate sizeof (schizo_saf_events) / sizeof (pci_kev_mask_t); 31447c478bd9Sstevel@tonic-gate saf_name_kstat->pic_shift[0] = SCHIZO_SHIFT_PIC0; 31457c478bd9Sstevel@tonic-gate saf_name_kstat->pic_shift[1] = SCHIZO_SHIFT_PIC1; 31467c478bd9Sstevel@tonic-gate pci_create_name_kstat("saf", saf_name_kstat, schizo_saf_events); 31477c478bd9Sstevel@tonic-gate } 31487c478bd9Sstevel@tonic-gate } 31497c478bd9Sstevel@tonic-gate 31507c478bd9Sstevel@tonic-gate void 31517c478bd9Sstevel@tonic-gate pci_kstat_fini() 31527c478bd9Sstevel@tonic-gate { 31537c478bd9Sstevel@tonic-gate if (pci_name_kstat != NULL) { 31547c478bd9Sstevel@tonic-gate pci_delete_name_kstat(pci_name_kstat); 31557c478bd9Sstevel@tonic-gate kmem_free(pci_name_kstat, sizeof (pci_ksinfo_t)); 31567c478bd9Sstevel@tonic-gate pci_name_kstat = NULL; 31577c478bd9Sstevel@tonic-gate } 31587c478bd9Sstevel@tonic-gate 31597c478bd9Sstevel@tonic-gate if (saf_name_kstat != NULL) { 31607c478bd9Sstevel@tonic-gate pci_delete_name_kstat(saf_name_kstat); 31617c478bd9Sstevel@tonic-gate kmem_free(saf_name_kstat, sizeof (pci_ksinfo_t)); 31627c478bd9Sstevel@tonic-gate saf_name_kstat = NULL; 31637c478bd9Sstevel@tonic-gate } 31647c478bd9Sstevel@tonic-gate } 31657c478bd9Sstevel@tonic-gate 31667c478bd9Sstevel@tonic-gate /* 31677c478bd9Sstevel@tonic-gate * Create 'counters' kstat for pci events. 31687c478bd9Sstevel@tonic-gate */ 31697c478bd9Sstevel@tonic-gate void 31707c478bd9Sstevel@tonic-gate pci_add_pci_kstat(pci_t *pci_p) 31717c478bd9Sstevel@tonic-gate { 31727c478bd9Sstevel@tonic-gate pci_cntr_addr_t *cntr_addr_p = &pci_p->pci_ks_addr; 31737c478bd9Sstevel@tonic-gate uintptr_t regbase = (uintptr_t)pci_p->pci_address[0]; 31747c478bd9Sstevel@tonic-gate 31757c478bd9Sstevel@tonic-gate cntr_addr_p->pcr_addr = (uint64_t *) 31767c478bd9Sstevel@tonic-gate (regbase + SCHIZO_PERF_PCI_PCR_OFFSET); 31777c478bd9Sstevel@tonic-gate cntr_addr_p->pic_addr = (uint64_t *) 31787c478bd9Sstevel@tonic-gate (regbase + SCHIZO_PERF_PCI_PIC_OFFSET); 31797c478bd9Sstevel@tonic-gate 31807c478bd9Sstevel@tonic-gate pci_p->pci_ksp = pci_create_cntr_kstat(pci_p, "pcis", 31817c478bd9Sstevel@tonic-gate NUM_OF_PICS, pci_cntr_kstat_update, cntr_addr_p); 31827c478bd9Sstevel@tonic-gate 31837c478bd9Sstevel@tonic-gate if (pci_p->pci_ksp == NULL) { 31847c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "pcisch : cannot create counter kstat"); 31857c478bd9Sstevel@tonic-gate } 31867c478bd9Sstevel@tonic-gate } 31877c478bd9Sstevel@tonic-gate 31887c478bd9Sstevel@tonic-gate void 31897c478bd9Sstevel@tonic-gate pci_rem_pci_kstat(pci_t *pci_p) 31907c478bd9Sstevel@tonic-gate { 31917c478bd9Sstevel@tonic-gate if (pci_p->pci_ksp != NULL) 31927c478bd9Sstevel@tonic-gate kstat_delete(pci_p->pci_ksp); 31937c478bd9Sstevel@tonic-gate pci_p->pci_ksp = NULL; 31947c478bd9Sstevel@tonic-gate } 31957c478bd9Sstevel@tonic-gate 31967c478bd9Sstevel@tonic-gate void 31977c478bd9Sstevel@tonic-gate pci_add_upstream_kstat(pci_t *pci_p) 31987c478bd9Sstevel@tonic-gate { 31997c478bd9Sstevel@tonic-gate pci_common_t *cmn_p = pci_p->pci_common_p; 32007c478bd9Sstevel@tonic-gate pci_cntr_pa_t *cntr_pa_p = &cmn_p->pci_cmn_uks_pa; 32017c478bd9Sstevel@tonic-gate uint64_t regbase = va_to_pa(pci_p->pci_address[1]); 32027c478bd9Sstevel@tonic-gate 32037c478bd9Sstevel@tonic-gate cntr_pa_p->pcr_pa = 32047c478bd9Sstevel@tonic-gate regbase + SCHIZO_PERF_SAF_PCR_OFFSET; 32057c478bd9Sstevel@tonic-gate cntr_pa_p->pic_pa = 32067c478bd9Sstevel@tonic-gate regbase + SCHIZO_PERF_SAF_PIC_OFFSET; 32077c478bd9Sstevel@tonic-gate 32087c478bd9Sstevel@tonic-gate cmn_p->pci_common_uksp = pci_create_cntr_kstat(pci_p, "saf", 32097c478bd9Sstevel@tonic-gate NUM_OF_PICS, pci_cntr_kstat_pa_update, cntr_pa_p); 32107c478bd9Sstevel@tonic-gate } 32117c478bd9Sstevel@tonic-gate 32127c478bd9Sstevel@tonic-gate /* 32137c478bd9Sstevel@tonic-gate * Extract the drivers binding name to identify which chip 32147c478bd9Sstevel@tonic-gate * we're binding to. Whenever a new bus bridge is created, the driver alias 32157c478bd9Sstevel@tonic-gate * entry should be added here to identify the device if needed. If a device 32167c478bd9Sstevel@tonic-gate * isn't added, the identity defaults to PCI_CHIP_UNIDENTIFIED. 32177c478bd9Sstevel@tonic-gate */ 32187c478bd9Sstevel@tonic-gate static uint32_t 32197c478bd9Sstevel@tonic-gate pci_identity_init(pci_t *pci_p) 32207c478bd9Sstevel@tonic-gate { 32217c478bd9Sstevel@tonic-gate dev_info_t *dip = pci_p->pci_dip; 32227c478bd9Sstevel@tonic-gate char *name = ddi_binding_name(dip); 32237c478bd9Sstevel@tonic-gate uint32_t ver = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 32247c478bd9Sstevel@tonic-gate "version#", 0); 32257c478bd9Sstevel@tonic-gate 32267c478bd9Sstevel@tonic-gate if (strcmp(name, "pci108e,a801") == 0) 32277c478bd9Sstevel@tonic-gate return (CHIP_ID(PCI_CHIP_TOMATILLO, ver, 0x00)); 32287c478bd9Sstevel@tonic-gate 32297c478bd9Sstevel@tonic-gate if (strcmp(name, "pci108e,8001") == 0) 32307c478bd9Sstevel@tonic-gate return (CHIP_ID(PCI_CHIP_SCHIZO, ver, 0x00)); 32317c478bd9Sstevel@tonic-gate 32327c478bd9Sstevel@tonic-gate if (strcmp(name, "pci108e,8002") == 0) { 32337c478bd9Sstevel@tonic-gate uint32_t mod_rev = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 32347c478bd9Sstevel@tonic-gate DDI_PROP_DONTPASS, "module-revision#", 0); 32357c478bd9Sstevel@tonic-gate return (CHIP_ID(PCI_CHIP_XMITS, ver, mod_rev)); 32367c478bd9Sstevel@tonic-gate } 32377c478bd9Sstevel@tonic-gate 32387c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "%s%d: Unknown PCI Host bridge %s %x\n", 32397c478bd9Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip), name, ver); 32407c478bd9Sstevel@tonic-gate 32417c478bd9Sstevel@tonic-gate return (PCI_CHIP_UNIDENTIFIED); 32427c478bd9Sstevel@tonic-gate } 32437c478bd9Sstevel@tonic-gate 32447c478bd9Sstevel@tonic-gate /* 32457c478bd9Sstevel@tonic-gate * Setup a physical pointer to one leaf config space area. This 32467c478bd9Sstevel@tonic-gate * is used in several places in order to do a dummy read which 32477c478bd9Sstevel@tonic-gate * guarantees the nexus (and not a bus master) has gained control 32487c478bd9Sstevel@tonic-gate * of the bus. 32497c478bd9Sstevel@tonic-gate */ 32507c478bd9Sstevel@tonic-gate static void 32517c478bd9Sstevel@tonic-gate pci_setup_cfgpa(pci_t *pci_p) 32527c478bd9Sstevel@tonic-gate { 32537c478bd9Sstevel@tonic-gate dev_info_t *dip = pci_p->pci_dip; 32547c478bd9Sstevel@tonic-gate dev_info_t *cdip; 32557c478bd9Sstevel@tonic-gate pbm_t *pbm_p = pci_p->pci_pbm_p; 32567c478bd9Sstevel@tonic-gate uint64_t cfgpa = pci_get_cfg_pabase(pci_p); 32577c478bd9Sstevel@tonic-gate uint32_t *reg_p; 32587c478bd9Sstevel@tonic-gate int reg_len; 32597c478bd9Sstevel@tonic-gate 32607c478bd9Sstevel@tonic-gate for (cdip = ddi_get_child(dip); cdip != NULL; 32617c478bd9Sstevel@tonic-gate cdip = ddi_get_next_sibling(cdip)) { 3262a3282898Scth if (ddi_getlongprop(DDI_DEV_T_ANY, cdip, DDI_PROP_DONTPASS, 32637c478bd9Sstevel@tonic-gate "reg", (caddr_t)®_p, ®_len) != DDI_PROP_SUCCESS) 32647c478bd9Sstevel@tonic-gate continue; 32657c478bd9Sstevel@tonic-gate cfgpa += (*reg_p) & (PCI_CONF_ADDR_MASK ^ PCI_REG_REG_M); 32667c478bd9Sstevel@tonic-gate kmem_free(reg_p, reg_len); 32677c478bd9Sstevel@tonic-gate break; 32687c478bd9Sstevel@tonic-gate } 32697c478bd9Sstevel@tonic-gate pbm_p->pbm_anychild_cfgpa = cfgpa; 32707c478bd9Sstevel@tonic-gate } 32717c478bd9Sstevel@tonic-gate 32727c478bd9Sstevel@tonic-gate void 32737c478bd9Sstevel@tonic-gate pci_post_init_child(pci_t *pci_p, dev_info_t *child) 32747c478bd9Sstevel@tonic-gate { 32757c478bd9Sstevel@tonic-gate volatile uint64_t *ctrl_reg_p; 32767c478bd9Sstevel@tonic-gate pbm_t *pbm_p = pci_p->pci_pbm_p; 32777c478bd9Sstevel@tonic-gate 32787c478bd9Sstevel@tonic-gate pci_setup_cfgpa(pci_p); 32797c478bd9Sstevel@tonic-gate 32807c478bd9Sstevel@tonic-gate /* 32817c478bd9Sstevel@tonic-gate * This is a hack for skyhawk/casinni combination to address 32827c478bd9Sstevel@tonic-gate * hardware problems between the request and grant signals which 32837c478bd9Sstevel@tonic-gate * causes a bus hang. One workaround, which is applied here, 32847c478bd9Sstevel@tonic-gate * is to disable bus parking if the child contains the property 32857c478bd9Sstevel@tonic-gate * pci-req-removal. Note that if the bus is quiesced we must mask 32867c478bd9Sstevel@tonic-gate * off the parking bit in the saved control registers, since the 32877c478bd9Sstevel@tonic-gate * quiesce operation temporarily turns off PCI bus parking. 32887c478bd9Sstevel@tonic-gate */ 32897c478bd9Sstevel@tonic-gate if (ddi_prop_exists(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, 32907c478bd9Sstevel@tonic-gate "pci-req-removal") == 1) { 32917c478bd9Sstevel@tonic-gate 32927c478bd9Sstevel@tonic-gate if (pbm_p->pbm_quiesce_count > 0) { 32937c478bd9Sstevel@tonic-gate pbm_p->pbm_saved_ctrl_reg &= ~SCHIZO_PCI_CTRL_ARB_PARK; 32947c478bd9Sstevel@tonic-gate } else { 32957c478bd9Sstevel@tonic-gate ctrl_reg_p = pbm_p->pbm_ctrl_reg; 32967c478bd9Sstevel@tonic-gate *ctrl_reg_p &= ~SCHIZO_PCI_CTRL_ARB_PARK; 32977c478bd9Sstevel@tonic-gate } 32987c478bd9Sstevel@tonic-gate } 32997c478bd9Sstevel@tonic-gate 33007c478bd9Sstevel@tonic-gate if (CHIP_TYPE(pci_p) == PCI_CHIP_XMITS) { 33017c478bd9Sstevel@tonic-gate if (*pbm_p->pbm_ctrl_reg & XMITS_PCI_CTRL_X_MODE) { 33027c478bd9Sstevel@tonic-gate int value; 33037c478bd9Sstevel@tonic-gate 33047c478bd9Sstevel@tonic-gate /* 33057c478bd9Sstevel@tonic-gate * Due to a XMITS bug, we need to set the outstanding 33067c478bd9Sstevel@tonic-gate * split transactions to 1 for all PCI-X functions 33077c478bd9Sstevel@tonic-gate * behind the leaf. 33087c478bd9Sstevel@tonic-gate */ 33097c478bd9Sstevel@tonic-gate value = (xmits_max_transactions << 4) | 33107c478bd9Sstevel@tonic-gate (xmits_max_read_bytes << 2); 33117c478bd9Sstevel@tonic-gate 33127c478bd9Sstevel@tonic-gate DEBUG1(DBG_INIT_CLD, child, "Turning on XMITS NCPQ " 33137c478bd9Sstevel@tonic-gate "Workaround: value = %x\n", value); 33147c478bd9Sstevel@tonic-gate 33157c478bd9Sstevel@tonic-gate pcix_set_cmd_reg(child, value); 33167c478bd9Sstevel@tonic-gate 33177c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, 33187c478bd9Sstevel@tonic-gate child, "pcix-update-cmd-reg", value); 33197c478bd9Sstevel@tonic-gate } 332057026b47Sdanice 332157026b47Sdanice if (PCI_CHIP_ID(pci_p) >= XMITS_VER_30) { 332257026b47Sdanice uint64_t *pbm_pcix_diag_reg = 332357026b47Sdanice (uint64_t *)(pci_p->pci_address[0] + 332457026b47Sdanice XMITS_PCI_X_DIAG_REG_OFFSET); 332557026b47Sdanice uint64_t bugcntl = (*pbm_pcix_diag_reg >> 332657026b47Sdanice XMITS_PCI_X_DIAG_BUGCNTL_SHIFT) & 332757026b47Sdanice XMITS_PCI_X_DIAG_BUGCNTL_MASK; 332857026b47Sdanice uint64_t tunable = (*pbm_p->pbm_ctrl_reg & 332957026b47Sdanice XMITS_PCI_CTRL_X_MODE ? 333057026b47Sdanice xmits_pcix_diag_bugcntl_pcix : 333157026b47Sdanice xmits_pcix_diag_bugcntl_pci) 333257026b47Sdanice & XMITS_PCI_X_DIAG_BUGCNTL_MASK; 333357026b47Sdanice 333457026b47Sdanice DEBUG4(DBG_INIT_CLD, pci_p->pci_dip, "%s: XMITS " 333557026b47Sdanice "pcix diag bugcntl=0x%lx, tunable=0x%lx, mode=%s\n", 333657026b47Sdanice ddi_driver_name(child), bugcntl, tunable, 333757026b47Sdanice ((*pbm_p->pbm_ctrl_reg & XMITS_PCI_CTRL_X_MODE)? 333857026b47Sdanice "PCI-X":"PCI")); 333957026b47Sdanice 334057026b47Sdanice DEBUG2(DBG_INIT_CLD, pci_p->pci_dip, "%s: XMITS " 334157026b47Sdanice "pcix diag reg=0x%lx (CUR)\n", 334257026b47Sdanice ddi_driver_name(child), *pbm_pcix_diag_reg); 334357026b47Sdanice 334457026b47Sdanice /* 334557026b47Sdanice * Due to a XMITS 3.x hw bug, we need to 334657026b47Sdanice * read PBM's xmits pci ctrl status register to 334757026b47Sdanice * determine mode (PCI or PCI-X) and then update 334857026b47Sdanice * PBM's pcix diag register with new BUG_FIX_CNTL 334957026b47Sdanice * bits (47:32) _if_ different from tunable's mode 335057026b47Sdanice * based value. This update is performed only once 335157026b47Sdanice * during the PBM's first child init. 335257026b47Sdanice * 335357026b47Sdanice * Per instructions from xmits hw engineering, 335457026b47Sdanice * non-BUG_FIX_CNTL bits should not be preserved 335557026b47Sdanice * when updating the pcix diag register. Such bits 335657026b47Sdanice * should be written as 0s. 335757026b47Sdanice */ 335857026b47Sdanice 335957026b47Sdanice if (bugcntl != tunable) { 336057026b47Sdanice *pbm_pcix_diag_reg = tunable << 336157026b47Sdanice XMITS_PCI_X_DIAG_BUGCNTL_SHIFT; 336257026b47Sdanice 336357026b47Sdanice DEBUG2(DBG_INIT_CLD, pci_p->pci_dip, "%s: XMITS" 336457026b47Sdanice " pcix diag reg=0x%lx (NEW)\n", 336557026b47Sdanice ddi_driver_name(child), *pbm_pcix_diag_reg); 336657026b47Sdanice } 336757026b47Sdanice } 33687c478bd9Sstevel@tonic-gate } 33697c478bd9Sstevel@tonic-gate } 33707c478bd9Sstevel@tonic-gate 33717c478bd9Sstevel@tonic-gate void 33727c478bd9Sstevel@tonic-gate pci_post_uninit_child(pci_t *pci_p) 33737c478bd9Sstevel@tonic-gate { 33747c478bd9Sstevel@tonic-gate pci_setup_cfgpa(pci_p); 33757c478bd9Sstevel@tonic-gate } 33767c478bd9Sstevel@tonic-gate 33777c478bd9Sstevel@tonic-gate static int 33787c478bd9Sstevel@tonic-gate pci_tom_nbintr_op(pci_t *pci_p, uint32_t inum, intrfunc f, caddr_t arg, 33797c478bd9Sstevel@tonic-gate int flag) 33807c478bd9Sstevel@tonic-gate { 33817c478bd9Sstevel@tonic-gate uint32_t ino = pci_p->pci_inos[inum]; 33827c478bd9Sstevel@tonic-gate uint32_t mondo = IB_INO_TO_NBMONDO(pci_p->pci_ib_p, ino); 33837c478bd9Sstevel@tonic-gate int ret = DDI_SUCCESS; 33847c478bd9Sstevel@tonic-gate 33857c478bd9Sstevel@tonic-gate mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); /* no op on tom */ 33867c478bd9Sstevel@tonic-gate 33877c478bd9Sstevel@tonic-gate switch (flag) { 33887c478bd9Sstevel@tonic-gate case PCI_OBJ_INTR_ADD: 3389b0fc0e77Sgovinda VERIFY(add_ivintr(mondo, pci_pil[inum], f, 3390b0fc0e77Sgovinda arg, NULL, NULL) == 0); 33917c478bd9Sstevel@tonic-gate break; 33927c478bd9Sstevel@tonic-gate case PCI_OBJ_INTR_REMOVE: 3393b0fc0e77Sgovinda VERIFY(rem_ivintr(mondo, pci_pil[inum]) == 0); 33947c478bd9Sstevel@tonic-gate break; 33957c478bd9Sstevel@tonic-gate default: 33967c478bd9Sstevel@tonic-gate ret = DDI_FAILURE; 33977c478bd9Sstevel@tonic-gate break; 33987c478bd9Sstevel@tonic-gate } 33997c478bd9Sstevel@tonic-gate 34007c478bd9Sstevel@tonic-gate return (ret); 34017c478bd9Sstevel@tonic-gate } 34027c478bd9Sstevel@tonic-gate 34037c478bd9Sstevel@tonic-gate int 34047c478bd9Sstevel@tonic-gate pci_ecc_add_intr(pci_t *pci_p, int inum, ecc_intr_info_t *eii_p) 34057c478bd9Sstevel@tonic-gate { 34067c478bd9Sstevel@tonic-gate uint32_t mondo; 34077c478bd9Sstevel@tonic-gate int r; 34087c478bd9Sstevel@tonic-gate 34097c478bd9Sstevel@tonic-gate mondo = ((pci_p->pci_cb_p->cb_ign << PCI_INO_BITS) | 34107c478bd9Sstevel@tonic-gate pci_p->pci_inos[inum]); 34117c478bd9Sstevel@tonic-gate mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 34127c478bd9Sstevel@tonic-gate 3413b0fc0e77Sgovinda VERIFY(add_ivintr(mondo, pci_pil[inum], (intrfunc)ecc_intr, 3414b0fc0e77Sgovinda (caddr_t)eii_p, NULL, NULL) == 0); 34157c478bd9Sstevel@tonic-gate 34167c478bd9Sstevel@tonic-gate if (CHIP_TYPE(pci_p) != PCI_CHIP_TOMATILLO) 34177c478bd9Sstevel@tonic-gate return (PCI_ATTACH_RETCODE(PCI_ECC_OBJ, PCI_OBJ_INTR_ADD, 34187c478bd9Sstevel@tonic-gate DDI_SUCCESS)); 34197c478bd9Sstevel@tonic-gate 3420b0fc0e77Sgovinda r = pci_tom_nbintr_op(pci_p, inum, (intrfunc)ecc_intr, 34217c478bd9Sstevel@tonic-gate (caddr_t)eii_p, PCI_OBJ_INTR_ADD); 34227c478bd9Sstevel@tonic-gate return (PCI_ATTACH_RETCODE(PCI_ECC_OBJ, PCI_OBJ_INTR_ADD, r)); 34237c478bd9Sstevel@tonic-gate } 34247c478bd9Sstevel@tonic-gate 34257c478bd9Sstevel@tonic-gate void 34267c478bd9Sstevel@tonic-gate pci_ecc_rem_intr(pci_t *pci_p, int inum, ecc_intr_info_t *eii_p) 34277c478bd9Sstevel@tonic-gate { 34287c478bd9Sstevel@tonic-gate uint32_t mondo; 34297c478bd9Sstevel@tonic-gate 34307c478bd9Sstevel@tonic-gate mondo = ((pci_p->pci_cb_p->cb_ign << PCI_INO_BITS) | 34317c478bd9Sstevel@tonic-gate pci_p->pci_inos[inum]); 34327c478bd9Sstevel@tonic-gate mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 34337c478bd9Sstevel@tonic-gate 3434b0fc0e77Sgovinda VERIFY(rem_ivintr(mondo, pci_pil[inum]) == 0); 34357c478bd9Sstevel@tonic-gate 34367c478bd9Sstevel@tonic-gate if (CHIP_TYPE(pci_p) == PCI_CHIP_TOMATILLO) 3437b0fc0e77Sgovinda pci_tom_nbintr_op(pci_p, inum, (intrfunc)ecc_intr, 34387c478bd9Sstevel@tonic-gate (caddr_t)eii_p, PCI_OBJ_INTR_REMOVE); 34397c478bd9Sstevel@tonic-gate } 34407c478bd9Sstevel@tonic-gate 34417c478bd9Sstevel@tonic-gate static uint_t 34427c478bd9Sstevel@tonic-gate pci_pbm_cdma_intr(caddr_t a) 34437c478bd9Sstevel@tonic-gate { 34447c478bd9Sstevel@tonic-gate pbm_t *pbm_p = (pbm_t *)a; 34457c478bd9Sstevel@tonic-gate pbm_p->pbm_cdma_flag = PBM_CDMA_DONE; 3446825808ceSdduvall #ifdef PBM_CDMA_DEBUG 3447825808ceSdduvall pbm_p->pbm_cdma_intr_cnt++; 3448825808ceSdduvall #endif /* PBM_CDMA_DEBUG */ 34497c478bd9Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 34507c478bd9Sstevel@tonic-gate } 34517c478bd9Sstevel@tonic-gate 34527c478bd9Sstevel@tonic-gate int 34537c478bd9Sstevel@tonic-gate pci_pbm_add_intr(pci_t *pci_p) 34547c478bd9Sstevel@tonic-gate { 34557c478bd9Sstevel@tonic-gate uint32_t mondo; 34567c478bd9Sstevel@tonic-gate 34577c478bd9Sstevel@tonic-gate mondo = IB_INO_TO_MONDO(pci_p->pci_ib_p, pci_p->pci_inos[CBNINTR_CDMA]); 34587c478bd9Sstevel@tonic-gate mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 34597c478bd9Sstevel@tonic-gate 34607c478bd9Sstevel@tonic-gate VERIFY(add_ivintr(mondo, pci_pil[CBNINTR_CDMA], 3461b0fc0e77Sgovinda (intrfunc)pci_pbm_cdma_intr, (caddr_t)pci_p->pci_pbm_p, 3462b0fc0e77Sgovinda NULL, NULL) == 0); 34637c478bd9Sstevel@tonic-gate 34647c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 34657c478bd9Sstevel@tonic-gate } 34667c478bd9Sstevel@tonic-gate 34677c478bd9Sstevel@tonic-gate void 34687c478bd9Sstevel@tonic-gate pci_pbm_rem_intr(pci_t *pci_p) 34697c478bd9Sstevel@tonic-gate { 34707c478bd9Sstevel@tonic-gate ib_t *ib_p = pci_p->pci_ib_p; 34717c478bd9Sstevel@tonic-gate uint32_t mondo; 34727c478bd9Sstevel@tonic-gate 34737c478bd9Sstevel@tonic-gate mondo = IB_INO_TO_MONDO(pci_p->pci_ib_p, pci_p->pci_inos[CBNINTR_CDMA]); 34747c478bd9Sstevel@tonic-gate mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 34757c478bd9Sstevel@tonic-gate 34767c478bd9Sstevel@tonic-gate ib_intr_disable(ib_p, pci_p->pci_inos[CBNINTR_CDMA], IB_INTR_NOWAIT); 3477b0fc0e77Sgovinda VERIFY(rem_ivintr(mondo, pci_pil[CBNINTR_CDMA]) == 0); 34787c478bd9Sstevel@tonic-gate } 34797c478bd9Sstevel@tonic-gate 34807c478bd9Sstevel@tonic-gate void 34817c478bd9Sstevel@tonic-gate pci_pbm_suspend(pci_t *pci_p) 34827c478bd9Sstevel@tonic-gate { 34837c478bd9Sstevel@tonic-gate pbm_t *pbm_p = pci_p->pci_pbm_p; 34847c478bd9Sstevel@tonic-gate ib_ino_t ino = pci_p->pci_inos[CBNINTR_CDMA]; 34857c478bd9Sstevel@tonic-gate 34867c478bd9Sstevel@tonic-gate /* Save CDMA interrupt state */ 34877c478bd9Sstevel@tonic-gate pbm_p->pbm_cdma_imr_save = *ib_intr_map_reg_addr(pci_p->pci_ib_p, ino); 34887c478bd9Sstevel@tonic-gate } 34897c478bd9Sstevel@tonic-gate 34907c478bd9Sstevel@tonic-gate void 34917c478bd9Sstevel@tonic-gate pci_pbm_resume(pci_t *pci_p) 34927c478bd9Sstevel@tonic-gate { 34937c478bd9Sstevel@tonic-gate pbm_t *pbm_p = pci_p->pci_pbm_p; 34947c478bd9Sstevel@tonic-gate ib_ino_t ino = pci_p->pci_inos[CBNINTR_CDMA]; 34957c478bd9Sstevel@tonic-gate 34967c478bd9Sstevel@tonic-gate /* Restore CDMA interrupt state */ 34977c478bd9Sstevel@tonic-gate *ib_intr_map_reg_addr(pci_p->pci_ib_p, ino) = pbm_p->pbm_cdma_imr_save; 34987c478bd9Sstevel@tonic-gate } 34997c478bd9Sstevel@tonic-gate 35007c478bd9Sstevel@tonic-gate /* 35017c478bd9Sstevel@tonic-gate * pci_bus_quiesce 35027c478bd9Sstevel@tonic-gate * 35037c478bd9Sstevel@tonic-gate * This function is called as the corresponding control ops routine 35047c478bd9Sstevel@tonic-gate * to a DDI_CTLOPS_QUIESCE command. Its mission is to halt all DMA 35057c478bd9Sstevel@tonic-gate * activity on the bus by disabling arbitration/parking. 35067c478bd9Sstevel@tonic-gate */ 35077c478bd9Sstevel@tonic-gate int 35087c478bd9Sstevel@tonic-gate pci_bus_quiesce(pci_t *pci_p, dev_info_t *dip, void *result) 35097c478bd9Sstevel@tonic-gate { 35107c478bd9Sstevel@tonic-gate volatile uint64_t *ctrl_reg_p; 35117c478bd9Sstevel@tonic-gate volatile uint64_t ctrl_reg; 35127c478bd9Sstevel@tonic-gate pbm_t *pbm_p; 35137c478bd9Sstevel@tonic-gate 35147c478bd9Sstevel@tonic-gate pbm_p = pci_p->pci_pbm_p; 35157c478bd9Sstevel@tonic-gate ctrl_reg_p = pbm_p->pbm_ctrl_reg; 35167c478bd9Sstevel@tonic-gate 35177c478bd9Sstevel@tonic-gate if (pbm_p->pbm_quiesce_count++ == 0) { 35187c478bd9Sstevel@tonic-gate 35197c478bd9Sstevel@tonic-gate DEBUG0(DBG_PWR, dip, "quiescing bus\n"); 35207c478bd9Sstevel@tonic-gate 35217c478bd9Sstevel@tonic-gate ctrl_reg = *ctrl_reg_p; 35227c478bd9Sstevel@tonic-gate pbm_p->pbm_saved_ctrl_reg = ctrl_reg; 35237c478bd9Sstevel@tonic-gate ctrl_reg &= ~(SCHIZO_PCI_CTRL_ARB_EN_MASK | 35247c478bd9Sstevel@tonic-gate SCHIZO_PCI_CTRL_ARB_PARK); 35257c478bd9Sstevel@tonic-gate *ctrl_reg_p = ctrl_reg; 35267c478bd9Sstevel@tonic-gate #ifdef DEBUG 35277c478bd9Sstevel@tonic-gate ctrl_reg = *ctrl_reg_p; 35287c478bd9Sstevel@tonic-gate if ((ctrl_reg & (SCHIZO_PCI_CTRL_ARB_EN_MASK | 35297c478bd9Sstevel@tonic-gate SCHIZO_PCI_CTRL_ARB_PARK)) != 0) 3530f47a9c50Smathue panic("ctrl_reg didn't quiesce: 0x%lx\n", ctrl_reg); 35317c478bd9Sstevel@tonic-gate #endif 35327c478bd9Sstevel@tonic-gate if (pbm_p->pbm_anychild_cfgpa) 35337c478bd9Sstevel@tonic-gate (void) ldphysio(pbm_p->pbm_anychild_cfgpa); 35347c478bd9Sstevel@tonic-gate } 35357c478bd9Sstevel@tonic-gate 35367c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 35377c478bd9Sstevel@tonic-gate } 35387c478bd9Sstevel@tonic-gate 35397c478bd9Sstevel@tonic-gate /* 35407c478bd9Sstevel@tonic-gate * pci_bus_unquiesce 35417c478bd9Sstevel@tonic-gate * 35427c478bd9Sstevel@tonic-gate * This function is called as the corresponding control ops routine 35437c478bd9Sstevel@tonic-gate * to a DDI_CTLOPS_UNQUIESCE command. Its mission is to resume paused 35447c478bd9Sstevel@tonic-gate * DMA activity on the bus by re-enabling arbitration (and maybe parking). 35457c478bd9Sstevel@tonic-gate */ 35467c478bd9Sstevel@tonic-gate int 35477c478bd9Sstevel@tonic-gate pci_bus_unquiesce(pci_t *pci_p, dev_info_t *dip, void *result) 35487c478bd9Sstevel@tonic-gate { 35497c478bd9Sstevel@tonic-gate volatile uint64_t *ctrl_reg_p; 35507c478bd9Sstevel@tonic-gate pbm_t *pbm_p; 35517c478bd9Sstevel@tonic-gate #ifdef DEBUG 35527c478bd9Sstevel@tonic-gate volatile uint64_t ctrl_reg; 35537c478bd9Sstevel@tonic-gate #endif 35547c478bd9Sstevel@tonic-gate 35557c478bd9Sstevel@tonic-gate pbm_p = pci_p->pci_pbm_p; 35567c478bd9Sstevel@tonic-gate ctrl_reg_p = pbm_p->pbm_ctrl_reg; 35577c478bd9Sstevel@tonic-gate 35587c478bd9Sstevel@tonic-gate ASSERT(pbm_p->pbm_quiesce_count > 0); 35597c478bd9Sstevel@tonic-gate if (--pbm_p->pbm_quiesce_count == 0) { 35607c478bd9Sstevel@tonic-gate *ctrl_reg_p = pbm_p->pbm_saved_ctrl_reg; 35617c478bd9Sstevel@tonic-gate #ifdef DEBUG 35627c478bd9Sstevel@tonic-gate ctrl_reg = *ctrl_reg_p; 35637c478bd9Sstevel@tonic-gate if ((ctrl_reg & (SCHIZO_PCI_CTRL_ARB_EN_MASK | 35647c478bd9Sstevel@tonic-gate SCHIZO_PCI_CTRL_ARB_PARK)) == 0) 3565f47a9c50Smathue panic("ctrl_reg didn't unquiesce: 0x%lx\n", ctrl_reg); 35667c478bd9Sstevel@tonic-gate #endif 35677c478bd9Sstevel@tonic-gate } 35687c478bd9Sstevel@tonic-gate 35697c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 35707c478bd9Sstevel@tonic-gate } 35717c478bd9Sstevel@tonic-gate 3572d0662dbfSelowe int 3573d0662dbfSelowe pci_reloc_getkey(void) 3574d0662dbfSelowe { 3575d0662dbfSelowe return (0x200); 3576d0662dbfSelowe } 3577d0662dbfSelowe 35787c478bd9Sstevel@tonic-gate static void 35797c478bd9Sstevel@tonic-gate tm_vmem_free(ddi_dma_impl_t *mp, iommu_t *iommu_p, dvma_addr_t dvma_pg, 35807c478bd9Sstevel@tonic-gate int npages) 35817c478bd9Sstevel@tonic-gate { 35827c478bd9Sstevel@tonic-gate uint32_t dur_max, dur_base; 35837c478bd9Sstevel@tonic-gate dvma_unbind_req_t *req_p, *req_max_p; 35847c478bd9Sstevel@tonic-gate dvma_unbind_req_t *req_base_p = iommu_p->iommu_mtlb_req_p; 35857c478bd9Sstevel@tonic-gate uint32_t tlb_vpn[IOMMU_TLB_ENTRIES]; 35867c478bd9Sstevel@tonic-gate caddr_t reg_base; 35877c478bd9Sstevel@tonic-gate volatile uint64_t *tag_p; 35887c478bd9Sstevel@tonic-gate int i, preserv_count = 0; 35897c478bd9Sstevel@tonic-gate 35907c478bd9Sstevel@tonic-gate mutex_enter(&iommu_p->iommu_mtlb_lock); 35917c478bd9Sstevel@tonic-gate 35927c478bd9Sstevel@tonic-gate iommu_p->iommu_mtlb_npgs += npages; 35937c478bd9Sstevel@tonic-gate req_max_p = req_base_p + iommu_p->iommu_mtlb_nreq++; 35947c478bd9Sstevel@tonic-gate req_max_p->dur_npg = npages; 35957c478bd9Sstevel@tonic-gate req_max_p->dur_base = dvma_pg; 35967c478bd9Sstevel@tonic-gate req_max_p->dur_flags = mp->dmai_flags & DMAI_FLAGS_VMEMCACHE; 35977c478bd9Sstevel@tonic-gate 35987c478bd9Sstevel@tonic-gate 35997c478bd9Sstevel@tonic-gate if (iommu_p->iommu_mtlb_npgs <= iommu_p->iommu_mtlb_maxpgs) 36007c478bd9Sstevel@tonic-gate goto done; 36017c478bd9Sstevel@tonic-gate 36027c478bd9Sstevel@tonic-gate /* read TLB */ 36037c478bd9Sstevel@tonic-gate reg_base = iommu_p->iommu_pci_p->pci_address[0]; 36047c478bd9Sstevel@tonic-gate tag_p = (volatile uint64_t *) 36057c478bd9Sstevel@tonic-gate (reg_base + COMMON_IOMMU_TLB_TAG_DIAG_ACC_OFFSET); 36067c478bd9Sstevel@tonic-gate 36077c478bd9Sstevel@tonic-gate for (i = 0; i < IOMMU_TLB_ENTRIES; i++) 36087c478bd9Sstevel@tonic-gate tlb_vpn[i] = tag_p[i] & SCHIZO_VPN_MASK; 36097c478bd9Sstevel@tonic-gate 36107c478bd9Sstevel@tonic-gate /* for each request search the TLB for a matching address */ 36117c478bd9Sstevel@tonic-gate for (req_p = req_base_p; req_p <= req_max_p; req_p++) { 36127c478bd9Sstevel@tonic-gate dur_base = req_p->dur_base; 36137c478bd9Sstevel@tonic-gate dur_max = req_p->dur_base + req_p->dur_npg; 36147c478bd9Sstevel@tonic-gate 36157c478bd9Sstevel@tonic-gate for (i = 0; i < IOMMU_TLB_ENTRIES; i++) { 36167c478bd9Sstevel@tonic-gate uint_t vpn = tlb_vpn[i]; 36177c478bd9Sstevel@tonic-gate if (vpn >= dur_base && vpn < dur_max) 36187c478bd9Sstevel@tonic-gate break; 36197c478bd9Sstevel@tonic-gate } 36207c478bd9Sstevel@tonic-gate if (i >= IOMMU_TLB_ENTRIES) { 36217c478bd9Sstevel@tonic-gate pci_vmem_do_free(iommu_p, 36227c478bd9Sstevel@tonic-gate (void *)IOMMU_PTOB(req_p->dur_base), 36237c478bd9Sstevel@tonic-gate req_p->dur_npg, req_p->dur_flags); 36247c478bd9Sstevel@tonic-gate iommu_p->iommu_mtlb_npgs -= req_p->dur_npg; 36257c478bd9Sstevel@tonic-gate continue; 36267c478bd9Sstevel@tonic-gate } 36277c478bd9Sstevel@tonic-gate /* if an empty slot exists */ 36287c478bd9Sstevel@tonic-gate if ((req_p - req_base_p) != preserv_count) 36297c478bd9Sstevel@tonic-gate *(req_base_p + preserv_count) = *req_p; 36307c478bd9Sstevel@tonic-gate preserv_count++; 36317c478bd9Sstevel@tonic-gate } 36327c478bd9Sstevel@tonic-gate 36337c478bd9Sstevel@tonic-gate iommu_p->iommu_mtlb_nreq = preserv_count; 36347c478bd9Sstevel@tonic-gate done: 36357c478bd9Sstevel@tonic-gate mutex_exit(&iommu_p->iommu_mtlb_lock); 36367c478bd9Sstevel@tonic-gate } 36377c478bd9Sstevel@tonic-gate 36387c478bd9Sstevel@tonic-gate void 36397c478bd9Sstevel@tonic-gate pci_vmem_free(iommu_t *iommu_p, ddi_dma_impl_t *mp, void *dvma_addr, 36407c478bd9Sstevel@tonic-gate size_t npages) 36417c478bd9Sstevel@tonic-gate { 36427c478bd9Sstevel@tonic-gate if (tm_mtlb_gc) 36437c478bd9Sstevel@tonic-gate tm_vmem_free(mp, iommu_p, 36447c478bd9Sstevel@tonic-gate (dvma_addr_t)IOMMU_BTOP((dvma_addr_t)dvma_addr), npages); 36457c478bd9Sstevel@tonic-gate else 36467c478bd9Sstevel@tonic-gate pci_vmem_do_free(iommu_p, dvma_addr, npages, 36477c478bd9Sstevel@tonic-gate (mp->dmai_flags & DMAI_FLAGS_VMEMCACHE)); 36487c478bd9Sstevel@tonic-gate } 364949f91442Ssuha 365049f91442Ssuha /* 365149f91442Ssuha * pci_iommu_bypass_end_configure 365249f91442Ssuha * 365349f91442Ssuha * Support for 42-bit bus width to SAFARI and JBUS in DVMA and 365449f91442Ssuha * iommu bypass transfers: 365549f91442Ssuha */ 365649f91442Ssuha 365749f91442Ssuha dma_bypass_addr_t 365849f91442Ssuha pci_iommu_bypass_end_configure(void) 365949f91442Ssuha { 366049f91442Ssuha 366149f91442Ssuha return ((dma_bypass_addr_t)SAFARI_JBUS_IOMMU_BYPASS_END); 366249f91442Ssuha } 3663