1*7c478bd9Sstevel@tonic-gate /* 2*7c478bd9Sstevel@tonic-gate * CDDL HEADER START 3*7c478bd9Sstevel@tonic-gate * 4*7c478bd9Sstevel@tonic-gate * The contents of this file are subject to the terms of the 5*7c478bd9Sstevel@tonic-gate * Common Development and Distribution License, Version 1.0 only 6*7c478bd9Sstevel@tonic-gate * (the "License"). You may not use this file except in compliance 7*7c478bd9Sstevel@tonic-gate * with the License. 8*7c478bd9Sstevel@tonic-gate * 9*7c478bd9Sstevel@tonic-gate * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10*7c478bd9Sstevel@tonic-gate * or http://www.opensolaris.org/os/licensing. 11*7c478bd9Sstevel@tonic-gate * See the License for the specific language governing permissions 12*7c478bd9Sstevel@tonic-gate * and limitations under the License. 13*7c478bd9Sstevel@tonic-gate * 14*7c478bd9Sstevel@tonic-gate * When distributing Covered Code, include this CDDL HEADER in each 15*7c478bd9Sstevel@tonic-gate * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16*7c478bd9Sstevel@tonic-gate * If applicable, add the following below this CDDL HEADER, with the 17*7c478bd9Sstevel@tonic-gate * fields enclosed by brackets "[]" replaced with your own identifying 18*7c478bd9Sstevel@tonic-gate * information: Portions Copyright [yyyy] [name of copyright owner] 19*7c478bd9Sstevel@tonic-gate * 20*7c478bd9Sstevel@tonic-gate * CDDL HEADER END 21*7c478bd9Sstevel@tonic-gate */ 22*7c478bd9Sstevel@tonic-gate /* 23*7c478bd9Sstevel@tonic-gate * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24*7c478bd9Sstevel@tonic-gate * Use is subject to license terms. 25*7c478bd9Sstevel@tonic-gate */ 26*7c478bd9Sstevel@tonic-gate 27*7c478bd9Sstevel@tonic-gate #pragma ident "%Z%%M% %I% %E% SMI" 28*7c478bd9Sstevel@tonic-gate 29*7c478bd9Sstevel@tonic-gate /* 30*7c478bd9Sstevel@tonic-gate * Schizo specifics implementation: 31*7c478bd9Sstevel@tonic-gate * interrupt mapping register 32*7c478bd9Sstevel@tonic-gate * PBM configuration 33*7c478bd9Sstevel@tonic-gate * ECC and PBM error handling 34*7c478bd9Sstevel@tonic-gate * Iommu mapping handling 35*7c478bd9Sstevel@tonic-gate * Streaming Cache flushing 36*7c478bd9Sstevel@tonic-gate */ 37*7c478bd9Sstevel@tonic-gate 38*7c478bd9Sstevel@tonic-gate #include <sys/types.h> 39*7c478bd9Sstevel@tonic-gate #include <sys/kmem.h> 40*7c478bd9Sstevel@tonic-gate #include <sys/sysmacros.h> 41*7c478bd9Sstevel@tonic-gate #include <sys/async.h> 42*7c478bd9Sstevel@tonic-gate #include <sys/ivintr.h> 43*7c478bd9Sstevel@tonic-gate #include <sys/systm.h> 44*7c478bd9Sstevel@tonic-gate #include <sys/intr.h> 45*7c478bd9Sstevel@tonic-gate #include <sys/machsystm.h> /* lddphys() */ 46*7c478bd9Sstevel@tonic-gate #include <sys/machsystm.h> /* lddphys, intr_dist_add */ 47*7c478bd9Sstevel@tonic-gate #include <sys/iommutsb.h> 48*7c478bd9Sstevel@tonic-gate #include <sys/promif.h> /* prom_printf */ 49*7c478bd9Sstevel@tonic-gate #include <sys/map.h> 50*7c478bd9Sstevel@tonic-gate #include <sys/ddi.h> 51*7c478bd9Sstevel@tonic-gate #include <sys/sunddi.h> 52*7c478bd9Sstevel@tonic-gate #include <sys/sunndi.h> 53*7c478bd9Sstevel@tonic-gate #include <sys/spl.h> 54*7c478bd9Sstevel@tonic-gate #include <sys/fm/util.h> 55*7c478bd9Sstevel@tonic-gate #include <sys/ddi_impldefs.h> 56*7c478bd9Sstevel@tonic-gate #include <sys/fm/protocol.h> 57*7c478bd9Sstevel@tonic-gate #include <sys/fm/io/sun4upci.h> 58*7c478bd9Sstevel@tonic-gate #include <sys/fm/io/ddi.h> 59*7c478bd9Sstevel@tonic-gate #include <sys/fm/io/pci.h> 60*7c478bd9Sstevel@tonic-gate #include <sys/pci/pci_obj.h> 61*7c478bd9Sstevel@tonic-gate #include <sys/pci/pcisch.h> 62*7c478bd9Sstevel@tonic-gate #include <sys/pci/pcisch_asm.h> 63*7c478bd9Sstevel@tonic-gate #include <sys/x_call.h> /* XCALL_PIL */ 64*7c478bd9Sstevel@tonic-gate 65*7c478bd9Sstevel@tonic-gate /*LINTLIBRARY*/ 66*7c478bd9Sstevel@tonic-gate 67*7c478bd9Sstevel@tonic-gate extern uint8_t ldstub(uint8_t *); 68*7c478bd9Sstevel@tonic-gate 69*7c478bd9Sstevel@tonic-gate #define IOMMU_CTX_BITMAP_SIZE (1 << (12 - 3)) 70*7c478bd9Sstevel@tonic-gate static void iommu_ctx_free(iommu_t *); 71*7c478bd9Sstevel@tonic-gate static int iommu_tlb_scrub(iommu_t *, int); 72*7c478bd9Sstevel@tonic-gate static uint32_t pci_identity_init(pci_t *); 73*7c478bd9Sstevel@tonic-gate 74*7c478bd9Sstevel@tonic-gate static void pci_cb_clear_error(cb_t *, cb_errstate_t *); 75*7c478bd9Sstevel@tonic-gate static void pci_clear_error(pci_t *, pbm_errstate_t *); 76*7c478bd9Sstevel@tonic-gate static uint32_t pci_identity_init(pci_t *pci_p); 77*7c478bd9Sstevel@tonic-gate static int pci_intr_setup(pci_t *pci_p); 78*7c478bd9Sstevel@tonic-gate static void iommu_ereport_post(dev_info_t *, uint64_t, pbm_errstate_t *); 79*7c478bd9Sstevel@tonic-gate static void cb_ereport_post(dev_info_t *, uint64_t, cb_errstate_t *); 80*7c478bd9Sstevel@tonic-gate static void pcix_ereport_post(dev_info_t *, uint64_t, pbm_errstate_t *); 81*7c478bd9Sstevel@tonic-gate static void pci_format_ecc_addr(dev_info_t *dip, uint64_t *afar, 82*7c478bd9Sstevel@tonic-gate ecc_region_t region); 83*7c478bd9Sstevel@tonic-gate static void pci_pbm_errstate_get(pci_t *pci_p, pbm_errstate_t *pbm_err_p); 84*7c478bd9Sstevel@tonic-gate static void tm_vmem_free(ddi_dma_impl_t *mp, iommu_t *iommu_p, 85*7c478bd9Sstevel@tonic-gate dvma_addr_t dvma_pg, int npages); 86*7c478bd9Sstevel@tonic-gate 87*7c478bd9Sstevel@tonic-gate static int pcix_ma_behind_bridge(pbm_errstate_t *pbm_err_p); 88*7c478bd9Sstevel@tonic-gate 89*7c478bd9Sstevel@tonic-gate static pci_ksinfo_t *pci_name_kstat; 90*7c478bd9Sstevel@tonic-gate static pci_ksinfo_t *saf_name_kstat; 91*7c478bd9Sstevel@tonic-gate 92*7c478bd9Sstevel@tonic-gate extern void pcix_set_cmd_reg(dev_info_t *child, uint16_t value); 93*7c478bd9Sstevel@tonic-gate 94*7c478bd9Sstevel@tonic-gate /* called by pci_attach() DDI_ATTACH to initialize pci objects */ 95*7c478bd9Sstevel@tonic-gate int 96*7c478bd9Sstevel@tonic-gate pci_obj_setup(pci_t *pci_p) 97*7c478bd9Sstevel@tonic-gate { 98*7c478bd9Sstevel@tonic-gate pci_common_t *cmn_p; 99*7c478bd9Sstevel@tonic-gate uint32_t chip_id = pci_identity_init(pci_p); 100*7c478bd9Sstevel@tonic-gate uint32_t cmn_id = PCI_CMN_ID(ID_CHIP_TYPE(chip_id), pci_p->pci_id); 101*7c478bd9Sstevel@tonic-gate int ret; 102*7c478bd9Sstevel@tonic-gate 103*7c478bd9Sstevel@tonic-gate /* Perform allocations first to avoid delicate unwinding. */ 104*7c478bd9Sstevel@tonic-gate if (pci_alloc_tsb(pci_p) != DDI_SUCCESS) 105*7c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 106*7c478bd9Sstevel@tonic-gate 107*7c478bd9Sstevel@tonic-gate mutex_enter(&pci_global_mutex); 108*7c478bd9Sstevel@tonic-gate cmn_p = get_pci_common_soft_state(cmn_id); 109*7c478bd9Sstevel@tonic-gate if (cmn_p == NULL) { 110*7c478bd9Sstevel@tonic-gate if (alloc_pci_common_soft_state(cmn_id) != DDI_SUCCESS) { 111*7c478bd9Sstevel@tonic-gate mutex_exit(&pci_global_mutex); 112*7c478bd9Sstevel@tonic-gate pci_free_tsb(pci_p); 113*7c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 114*7c478bd9Sstevel@tonic-gate } 115*7c478bd9Sstevel@tonic-gate cmn_p = get_pci_common_soft_state(cmn_id); 116*7c478bd9Sstevel@tonic-gate cmn_p->pci_common_id = cmn_id; 117*7c478bd9Sstevel@tonic-gate cmn_p->pci_common_tsb_cookie = IOMMU_TSB_COOKIE_NONE; 118*7c478bd9Sstevel@tonic-gate } 119*7c478bd9Sstevel@tonic-gate 120*7c478bd9Sstevel@tonic-gate ASSERT((pci_p->pci_side == 0) || (pci_p->pci_side == 1)); 121*7c478bd9Sstevel@tonic-gate if (cmn_p->pci_p[pci_p->pci_side]) { 122*7c478bd9Sstevel@tonic-gate /* second side attach */ 123*7c478bd9Sstevel@tonic-gate pci_p->pci_side = PCI_OTHER_SIDE(pci_p->pci_side); 124*7c478bd9Sstevel@tonic-gate ASSERT(cmn_p->pci_p[pci_p->pci_side] == NULL); 125*7c478bd9Sstevel@tonic-gate } 126*7c478bd9Sstevel@tonic-gate 127*7c478bd9Sstevel@tonic-gate cmn_p->pci_p[pci_p->pci_side] = pci_p; 128*7c478bd9Sstevel@tonic-gate pci_p->pci_common_p = cmn_p; 129*7c478bd9Sstevel@tonic-gate 130*7c478bd9Sstevel@tonic-gate if (cmn_p->pci_common_refcnt == 0) 131*7c478bd9Sstevel@tonic-gate cmn_p->pci_chip_id = chip_id; 132*7c478bd9Sstevel@tonic-gate 133*7c478bd9Sstevel@tonic-gate ib_create(pci_p); 134*7c478bd9Sstevel@tonic-gate 135*7c478bd9Sstevel@tonic-gate /* 136*7c478bd9Sstevel@tonic-gate * The initialization of cb internal interrupts depends on ib 137*7c478bd9Sstevel@tonic-gate */ 138*7c478bd9Sstevel@tonic-gate if (cmn_p->pci_common_refcnt == 0) { 139*7c478bd9Sstevel@tonic-gate cb_create(pci_p); 140*7c478bd9Sstevel@tonic-gate cmn_p->pci_common_cb_p = pci_p->pci_cb_p; 141*7c478bd9Sstevel@tonic-gate } else 142*7c478bd9Sstevel@tonic-gate pci_p->pci_cb_p = cmn_p->pci_common_cb_p; 143*7c478bd9Sstevel@tonic-gate 144*7c478bd9Sstevel@tonic-gate iommu_create(pci_p); 145*7c478bd9Sstevel@tonic-gate 146*7c478bd9Sstevel@tonic-gate if (cmn_p->pci_common_refcnt == 0) { 147*7c478bd9Sstevel@tonic-gate ecc_create(pci_p); 148*7c478bd9Sstevel@tonic-gate cmn_p->pci_common_ecc_p = pci_p->pci_ecc_p; 149*7c478bd9Sstevel@tonic-gate } else 150*7c478bd9Sstevel@tonic-gate pci_p->pci_ecc_p = cmn_p->pci_common_ecc_p; 151*7c478bd9Sstevel@tonic-gate 152*7c478bd9Sstevel@tonic-gate pbm_create(pci_p); 153*7c478bd9Sstevel@tonic-gate sc_create(pci_p); 154*7c478bd9Sstevel@tonic-gate 155*7c478bd9Sstevel@tonic-gate pci_fm_create(pci_p); 156*7c478bd9Sstevel@tonic-gate 157*7c478bd9Sstevel@tonic-gate if ((ret = pci_intr_setup(pci_p)) != DDI_SUCCESS) 158*7c478bd9Sstevel@tonic-gate goto done; 159*7c478bd9Sstevel@tonic-gate 160*7c478bd9Sstevel@tonic-gate pci_kstat_create(pci_p); 161*7c478bd9Sstevel@tonic-gate 162*7c478bd9Sstevel@tonic-gate cmn_p->pci_common_attachcnt++; 163*7c478bd9Sstevel@tonic-gate cmn_p->pci_common_refcnt++; 164*7c478bd9Sstevel@tonic-gate done: 165*7c478bd9Sstevel@tonic-gate mutex_exit(&pci_global_mutex); 166*7c478bd9Sstevel@tonic-gate if (ret != DDI_SUCCESS) 167*7c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "pci_obj_setup failed %x", ret); 168*7c478bd9Sstevel@tonic-gate return (ret); 169*7c478bd9Sstevel@tonic-gate } 170*7c478bd9Sstevel@tonic-gate 171*7c478bd9Sstevel@tonic-gate /* called by pci_detach() DDI_DETACH to destroy pci objects */ 172*7c478bd9Sstevel@tonic-gate void 173*7c478bd9Sstevel@tonic-gate pci_obj_destroy(pci_t *pci_p) 174*7c478bd9Sstevel@tonic-gate { 175*7c478bd9Sstevel@tonic-gate pci_common_t *cmn_p; 176*7c478bd9Sstevel@tonic-gate mutex_enter(&pci_global_mutex); 177*7c478bd9Sstevel@tonic-gate 178*7c478bd9Sstevel@tonic-gate cmn_p = pci_p->pci_common_p; 179*7c478bd9Sstevel@tonic-gate cmn_p->pci_common_refcnt--; 180*7c478bd9Sstevel@tonic-gate cmn_p->pci_common_attachcnt--; 181*7c478bd9Sstevel@tonic-gate 182*7c478bd9Sstevel@tonic-gate pci_kstat_destroy(pci_p); 183*7c478bd9Sstevel@tonic-gate 184*7c478bd9Sstevel@tonic-gate /* schizo non-shared objects */ 185*7c478bd9Sstevel@tonic-gate pci_fm_destroy(pci_p); 186*7c478bd9Sstevel@tonic-gate 187*7c478bd9Sstevel@tonic-gate sc_destroy(pci_p); 188*7c478bd9Sstevel@tonic-gate pbm_destroy(pci_p); 189*7c478bd9Sstevel@tonic-gate iommu_destroy(pci_p); 190*7c478bd9Sstevel@tonic-gate ib_destroy(pci_p); 191*7c478bd9Sstevel@tonic-gate 192*7c478bd9Sstevel@tonic-gate if (cmn_p->pci_common_refcnt != 0) { 193*7c478bd9Sstevel@tonic-gate pci_intr_teardown(pci_p); 194*7c478bd9Sstevel@tonic-gate cmn_p->pci_p[pci_p->pci_side] = NULL; 195*7c478bd9Sstevel@tonic-gate mutex_exit(&pci_global_mutex); 196*7c478bd9Sstevel@tonic-gate return; 197*7c478bd9Sstevel@tonic-gate } 198*7c478bd9Sstevel@tonic-gate 199*7c478bd9Sstevel@tonic-gate /* schizo shared objects - uses cmn_p, must be destroyed before cmn */ 200*7c478bd9Sstevel@tonic-gate ecc_destroy(pci_p); 201*7c478bd9Sstevel@tonic-gate cb_destroy(pci_p); 202*7c478bd9Sstevel@tonic-gate 203*7c478bd9Sstevel@tonic-gate free_pci_common_soft_state(cmn_p->pci_common_id); 204*7c478bd9Sstevel@tonic-gate pci_intr_teardown(pci_p); 205*7c478bd9Sstevel@tonic-gate mutex_exit(&pci_global_mutex); 206*7c478bd9Sstevel@tonic-gate } 207*7c478bd9Sstevel@tonic-gate 208*7c478bd9Sstevel@tonic-gate /* called by pci_attach() DDI_RESUME to (re)initialize pci objects */ 209*7c478bd9Sstevel@tonic-gate void 210*7c478bd9Sstevel@tonic-gate pci_obj_resume(pci_t *pci_p) 211*7c478bd9Sstevel@tonic-gate { 212*7c478bd9Sstevel@tonic-gate pci_common_t *cmn_p = pci_p->pci_common_p; 213*7c478bd9Sstevel@tonic-gate 214*7c478bd9Sstevel@tonic-gate mutex_enter(&pci_global_mutex); 215*7c478bd9Sstevel@tonic-gate 216*7c478bd9Sstevel@tonic-gate ib_configure(pci_p->pci_ib_p); 217*7c478bd9Sstevel@tonic-gate iommu_configure(pci_p->pci_iommu_p); 218*7c478bd9Sstevel@tonic-gate 219*7c478bd9Sstevel@tonic-gate if (cmn_p->pci_common_attachcnt == 0) 220*7c478bd9Sstevel@tonic-gate ecc_configure(pci_p); 221*7c478bd9Sstevel@tonic-gate 222*7c478bd9Sstevel@tonic-gate ib_resume(pci_p->pci_ib_p); 223*7c478bd9Sstevel@tonic-gate 224*7c478bd9Sstevel@tonic-gate pbm_configure(pci_p->pci_pbm_p); 225*7c478bd9Sstevel@tonic-gate sc_configure(pci_p->pci_sc_p); 226*7c478bd9Sstevel@tonic-gate 227*7c478bd9Sstevel@tonic-gate if (cmn_p->pci_common_attachcnt == 0) 228*7c478bd9Sstevel@tonic-gate cb_resume(pci_p->pci_cb_p); 229*7c478bd9Sstevel@tonic-gate 230*7c478bd9Sstevel@tonic-gate pbm_resume(pci_p->pci_pbm_p); 231*7c478bd9Sstevel@tonic-gate 232*7c478bd9Sstevel@tonic-gate cmn_p->pci_common_attachcnt++; 233*7c478bd9Sstevel@tonic-gate mutex_exit(&pci_global_mutex); 234*7c478bd9Sstevel@tonic-gate } 235*7c478bd9Sstevel@tonic-gate 236*7c478bd9Sstevel@tonic-gate /* called by pci_detach() DDI_SUSPEND to suspend pci objects */ 237*7c478bd9Sstevel@tonic-gate void 238*7c478bd9Sstevel@tonic-gate pci_obj_suspend(pci_t *pci_p) 239*7c478bd9Sstevel@tonic-gate { 240*7c478bd9Sstevel@tonic-gate mutex_enter(&pci_global_mutex); 241*7c478bd9Sstevel@tonic-gate 242*7c478bd9Sstevel@tonic-gate pbm_suspend(pci_p->pci_pbm_p); 243*7c478bd9Sstevel@tonic-gate ib_suspend(pci_p->pci_ib_p); 244*7c478bd9Sstevel@tonic-gate 245*7c478bd9Sstevel@tonic-gate if (!--pci_p->pci_common_p->pci_common_attachcnt) 246*7c478bd9Sstevel@tonic-gate cb_suspend(pci_p->pci_cb_p); 247*7c478bd9Sstevel@tonic-gate 248*7c478bd9Sstevel@tonic-gate mutex_exit(&pci_global_mutex); 249*7c478bd9Sstevel@tonic-gate } 250*7c478bd9Sstevel@tonic-gate 251*7c478bd9Sstevel@tonic-gate /* 252*7c478bd9Sstevel@tonic-gate * add an additional 0x35 or 0x36 ino interrupt on platforms don't have them 253*7c478bd9Sstevel@tonic-gate * This routine has multiple places that assumes interrupt takes one cell 254*7c478bd9Sstevel@tonic-gate * each and cell size is same as integer size. 255*7c478bd9Sstevel@tonic-gate */ 256*7c478bd9Sstevel@tonic-gate static int 257*7c478bd9Sstevel@tonic-gate pci_intr_setup(pci_t *pci_p) 258*7c478bd9Sstevel@tonic-gate { 259*7c478bd9Sstevel@tonic-gate dev_info_t *dip = pci_p->pci_dip; 260*7c478bd9Sstevel@tonic-gate pbm_t *pbm_p = pci_p->pci_pbm_p; 261*7c478bd9Sstevel@tonic-gate cb_t *cb_p = pci_p->pci_cb_p; 262*7c478bd9Sstevel@tonic-gate uint32_t *intr_buf, *new_intr_buf; 263*7c478bd9Sstevel@tonic-gate int intr_len, intr_cnt, ret; 264*7c478bd9Sstevel@tonic-gate 265*7c478bd9Sstevel@tonic-gate if (ddi_getlongprop(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 266*7c478bd9Sstevel@tonic-gate "interrupts", (caddr_t)&intr_buf, &intr_len) != DDI_SUCCESS) 267*7c478bd9Sstevel@tonic-gate cmn_err(CE_PANIC, "%s%d: no interrupts property\n", 268*7c478bd9Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip)); 269*7c478bd9Sstevel@tonic-gate 270*7c478bd9Sstevel@tonic-gate intr_cnt = BYTES_TO_1275_CELLS(intr_len); 271*7c478bd9Sstevel@tonic-gate if (intr_cnt < CBNINTR_CDMA) /* CBNINTR_CDMA is 0 based */ 272*7c478bd9Sstevel@tonic-gate cmn_err(CE_PANIC, "%s%d: <%d interrupts", ddi_driver_name(dip), 273*7c478bd9Sstevel@tonic-gate ddi_get_instance(dip), CBNINTR_CDMA); 274*7c478bd9Sstevel@tonic-gate 275*7c478bd9Sstevel@tonic-gate if (intr_cnt == CBNINTR_CDMA) 276*7c478bd9Sstevel@tonic-gate intr_cnt++; 277*7c478bd9Sstevel@tonic-gate 278*7c478bd9Sstevel@tonic-gate new_intr_buf = kmem_alloc(CELLS_1275_TO_BYTES(intr_cnt), KM_SLEEP); 279*7c478bd9Sstevel@tonic-gate bcopy(intr_buf, new_intr_buf, intr_len); 280*7c478bd9Sstevel@tonic-gate kmem_free(intr_buf, intr_len); 281*7c478bd9Sstevel@tonic-gate 282*7c478bd9Sstevel@tonic-gate new_intr_buf[CBNINTR_CDMA] = PBM_CDMA_INO_BASE + pci_p->pci_side; 283*7c478bd9Sstevel@tonic-gate pci_p->pci_inos = new_intr_buf; 284*7c478bd9Sstevel@tonic-gate pci_p->pci_inos_len = CELLS_1275_TO_BYTES(intr_cnt); 285*7c478bd9Sstevel@tonic-gate 286*7c478bd9Sstevel@tonic-gate if (ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "interrupts", 287*7c478bd9Sstevel@tonic-gate (int *)new_intr_buf, intr_cnt)) 288*7c478bd9Sstevel@tonic-gate cmn_err(CE_PANIC, "%s%d: cannot update interrupts property\n", 289*7c478bd9Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip)); 290*7c478bd9Sstevel@tonic-gate 291*7c478bd9Sstevel@tonic-gate if (pci_p->pci_common_p->pci_common_refcnt == 0) { 292*7c478bd9Sstevel@tonic-gate cb_p->cb_no_of_inos = intr_cnt; 293*7c478bd9Sstevel@tonic-gate if (ret = cb_register_intr(pci_p)) 294*7c478bd9Sstevel@tonic-gate goto teardown; 295*7c478bd9Sstevel@tonic-gate if (ret = ecc_register_intr(pci_p)) 296*7c478bd9Sstevel@tonic-gate goto teardown; 297*7c478bd9Sstevel@tonic-gate 298*7c478bd9Sstevel@tonic-gate intr_dist_add(cb_intr_dist, cb_p); 299*7c478bd9Sstevel@tonic-gate cb_enable_intr(pci_p); 300*7c478bd9Sstevel@tonic-gate ecc_enable_intr(pci_p); 301*7c478bd9Sstevel@tonic-gate } 302*7c478bd9Sstevel@tonic-gate 303*7c478bd9Sstevel@tonic-gate if (CHIP_TYPE(pci_p) != PCI_CHIP_SCHIZO) 304*7c478bd9Sstevel@tonic-gate pbm_p->pbm_sync_ino = pci_p->pci_inos[CBNINTR_PBM]; 305*7c478bd9Sstevel@tonic-gate if (ret = pbm_register_intr(pbm_p)) { 306*7c478bd9Sstevel@tonic-gate if (pci_p->pci_common_p->pci_common_refcnt == 0) 307*7c478bd9Sstevel@tonic-gate intr_dist_rem(cb_intr_dist, cb_p); 308*7c478bd9Sstevel@tonic-gate goto teardown; 309*7c478bd9Sstevel@tonic-gate } 310*7c478bd9Sstevel@tonic-gate intr_dist_add(pbm_intr_dist, pbm_p); 311*7c478bd9Sstevel@tonic-gate ib_intr_enable(pci_p, pci_p->pci_inos[CBNINTR_PBM]); 312*7c478bd9Sstevel@tonic-gate ib_intr_enable(pci_p, pci_p->pci_inos[CBNINTR_CDMA]); 313*7c478bd9Sstevel@tonic-gate 314*7c478bd9Sstevel@tonic-gate intr_dist_add_weighted(ib_intr_dist_all, pci_p->pci_ib_p); 315*7c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 316*7c478bd9Sstevel@tonic-gate teardown: 317*7c478bd9Sstevel@tonic-gate pci_intr_teardown(pci_p); 318*7c478bd9Sstevel@tonic-gate return (ret); 319*7c478bd9Sstevel@tonic-gate } 320*7c478bd9Sstevel@tonic-gate 321*7c478bd9Sstevel@tonic-gate uint64_t 322*7c478bd9Sstevel@tonic-gate pci_sc_configure(pci_t *pci_p) 323*7c478bd9Sstevel@tonic-gate { 324*7c478bd9Sstevel@tonic-gate int instance; 325*7c478bd9Sstevel@tonic-gate dev_info_t *dip = pci_p->pci_dip; 326*7c478bd9Sstevel@tonic-gate 327*7c478bd9Sstevel@tonic-gate instance = ddi_get_instance(dip); 328*7c478bd9Sstevel@tonic-gate if ((pci_xmits_sc_max_prf & (1 << instance)) && 329*7c478bd9Sstevel@tonic-gate (CHIP_TYPE(pci_p) == PCI_CHIP_XMITS)) 330*7c478bd9Sstevel@tonic-gate return (XMITS_SC_MAX_PRF); 331*7c478bd9Sstevel@tonic-gate else 332*7c478bd9Sstevel@tonic-gate return (0); 333*7c478bd9Sstevel@tonic-gate } 334*7c478bd9Sstevel@tonic-gate 335*7c478bd9Sstevel@tonic-gate static void 336*7c478bd9Sstevel@tonic-gate pci_schizo_cdma_sync(pbm_t *pbm_p) 337*7c478bd9Sstevel@tonic-gate { 338*7c478bd9Sstevel@tonic-gate pci_t *pci_p = pbm_p->pbm_pci_p; 339*7c478bd9Sstevel@tonic-gate hrtime_t start_time; 340*7c478bd9Sstevel@tonic-gate volatile uint64_t *clr_p = ib_clear_intr_reg_addr(pci_p->pci_ib_p, 341*7c478bd9Sstevel@tonic-gate pci_p->pci_inos[CBNINTR_CDMA]); 342*7c478bd9Sstevel@tonic-gate uint32_t fail_cnt = pci_cdma_intr_count; 343*7c478bd9Sstevel@tonic-gate 344*7c478bd9Sstevel@tonic-gate mutex_enter(&pbm_p->pbm_sync_mutex); 345*7c478bd9Sstevel@tonic-gate #ifdef PBM_CDMA_DEBUG 346*7c478bd9Sstevel@tonic-gate pbm_p->pbm_cdma_req_cnt++; 347*7c478bd9Sstevel@tonic-gate #endif /* PBM_CDMA_DEBUG */ 348*7c478bd9Sstevel@tonic-gate pbm_p->pbm_cdma_flag = PBM_CDMA_PEND; 349*7c478bd9Sstevel@tonic-gate IB_INO_INTR_TRIG(clr_p); 350*7c478bd9Sstevel@tonic-gate wait: 351*7c478bd9Sstevel@tonic-gate start_time = gethrtime(); 352*7c478bd9Sstevel@tonic-gate while (pbm_p->pbm_cdma_flag != PBM_CDMA_DONE) { 353*7c478bd9Sstevel@tonic-gate if (gethrtime() - start_time <= pci_cdma_intr_timeout) 354*7c478bd9Sstevel@tonic-gate continue; 355*7c478bd9Sstevel@tonic-gate if (--fail_cnt > 0) 356*7c478bd9Sstevel@tonic-gate goto wait; 357*7c478bd9Sstevel@tonic-gate if (pbm_p->pbm_cdma_flag == PBM_CDMA_DONE) 358*7c478bd9Sstevel@tonic-gate break; 359*7c478bd9Sstevel@tonic-gate cmn_err(CE_PANIC, "%s (%s): consistent dma sync timeout", 360*7c478bd9Sstevel@tonic-gate pbm_p->pbm_nameinst_str, pbm_p->pbm_nameaddr_str); 361*7c478bd9Sstevel@tonic-gate } 362*7c478bd9Sstevel@tonic-gate #ifdef PBM_CDMA_DEBUG 363*7c478bd9Sstevel@tonic-gate if (pbm_p->pbm_cdma_flag != PBM_CDMA_DONE) 364*7c478bd9Sstevel@tonic-gate pbm_p->pbm_cdma_to_cnt++; 365*7c478bd9Sstevel@tonic-gate else { 366*7c478bd9Sstevel@tonic-gate start_time = gethrtime() - start_time; 367*7c478bd9Sstevel@tonic-gate pbm_p->pbm_cdma_success_cnt++; 368*7c478bd9Sstevel@tonic-gate pbm_p->pbm_cdma_latency_sum += start_time; 369*7c478bd9Sstevel@tonic-gate if (start_time > pbm_p->pbm_cdma_latency_max) 370*7c478bd9Sstevel@tonic-gate pbm_p->pbm_cdma_latency_max = start_time; 371*7c478bd9Sstevel@tonic-gate } 372*7c478bd9Sstevel@tonic-gate #endif /* PBM_CDMA_DEBUG */ 373*7c478bd9Sstevel@tonic-gate mutex_exit(&pbm_p->pbm_sync_mutex); 374*7c478bd9Sstevel@tonic-gate } 375*7c478bd9Sstevel@tonic-gate 376*7c478bd9Sstevel@tonic-gate #if !defined(lint) 377*7c478bd9Sstevel@tonic-gate #include <sys/cpuvar.h> 378*7c478bd9Sstevel@tonic-gate #endif 379*7c478bd9Sstevel@tonic-gate 380*7c478bd9Sstevel@tonic-gate #define SYNC_HW_BUSY(pa, mask) (lddphysio(pa) & (mask)) 381*7c478bd9Sstevel@tonic-gate 382*7c478bd9Sstevel@tonic-gate /* 383*7c478bd9Sstevel@tonic-gate * Consistent DMA Sync/Flush 384*7c478bd9Sstevel@tonic-gate * 385*7c478bd9Sstevel@tonic-gate * XMITS and Tomatillo use multi-threaded sync/flush register. 386*7c478bd9Sstevel@tonic-gate * Called from interrupt wrapper: the associated ino is used to index 387*7c478bd9Sstevel@tonic-gate * the distinctive register bit. 388*7c478bd9Sstevel@tonic-gate * Called from pci_dma_sync(): the bit belongs to PBM is shared 389*7c478bd9Sstevel@tonic-gate * for all calls from pci_dma_sync(). Xmits requires serialization 390*7c478bd9Sstevel@tonic-gate * while Tomatillo does not. 391*7c478bd9Sstevel@tonic-gate */ 392*7c478bd9Sstevel@tonic-gate void 393*7c478bd9Sstevel@tonic-gate pci_pbm_dma_sync(pbm_t *pbm_p, ib_ino_t ino) 394*7c478bd9Sstevel@tonic-gate { 395*7c478bd9Sstevel@tonic-gate pci_t *pci_p = pbm_p->pbm_pci_p; 396*7c478bd9Sstevel@tonic-gate hrtime_t start_time; 397*7c478bd9Sstevel@tonic-gate uint64_t ino_mask, sync_reg_pa; 398*7c478bd9Sstevel@tonic-gate volatile uint64_t flag_val; 399*7c478bd9Sstevel@tonic-gate uint32_t locked, chip_type = CHIP_TYPE(pci_p); 400*7c478bd9Sstevel@tonic-gate int i; 401*7c478bd9Sstevel@tonic-gate 402*7c478bd9Sstevel@tonic-gate if (chip_type == PCI_CHIP_SCHIZO) { 403*7c478bd9Sstevel@tonic-gate pci_schizo_cdma_sync(pbm_p); 404*7c478bd9Sstevel@tonic-gate return; 405*7c478bd9Sstevel@tonic-gate } 406*7c478bd9Sstevel@tonic-gate 407*7c478bd9Sstevel@tonic-gate sync_reg_pa = pbm_p->pbm_sync_reg_pa; 408*7c478bd9Sstevel@tonic-gate 409*7c478bd9Sstevel@tonic-gate locked = 0; 410*7c478bd9Sstevel@tonic-gate if (((chip_type == PCI_CHIP_XMITS) && (ino == pbm_p->pbm_sync_ino)) || 411*7c478bd9Sstevel@tonic-gate pci_sync_lock) { 412*7c478bd9Sstevel@tonic-gate locked = 1; 413*7c478bd9Sstevel@tonic-gate mutex_enter(&pbm_p->pbm_sync_mutex); 414*7c478bd9Sstevel@tonic-gate } 415*7c478bd9Sstevel@tonic-gate ino_mask = 1ull << ino; 416*7c478bd9Sstevel@tonic-gate stdphysio(sync_reg_pa, ino_mask); 417*7c478bd9Sstevel@tonic-gate 418*7c478bd9Sstevel@tonic-gate for (i = 0; i < 5; i++) { 419*7c478bd9Sstevel@tonic-gate if ((flag_val = SYNC_HW_BUSY(sync_reg_pa, ino_mask)) == 0) 420*7c478bd9Sstevel@tonic-gate goto done; 421*7c478bd9Sstevel@tonic-gate } 422*7c478bd9Sstevel@tonic-gate 423*7c478bd9Sstevel@tonic-gate start_time = gethrtime(); 424*7c478bd9Sstevel@tonic-gate for (; (flag_val = SYNC_HW_BUSY(sync_reg_pa, ino_mask)) != 0; i++) { 425*7c478bd9Sstevel@tonic-gate if (gethrtime() - start_time > pci_sync_buf_timeout) 426*7c478bd9Sstevel@tonic-gate break; 427*7c478bd9Sstevel@tonic-gate } 428*7c478bd9Sstevel@tonic-gate 429*7c478bd9Sstevel@tonic-gate if (flag_val && SYNC_HW_BUSY(sync_reg_pa, ino_mask) && !panicstr) 430*7c478bd9Sstevel@tonic-gate cmn_err(CE_PANIC, "%s: pbm dma sync %llx,%llx timeout!", 431*7c478bd9Sstevel@tonic-gate pbm_p->pbm_nameaddr_str, sync_reg_pa, flag_val); 432*7c478bd9Sstevel@tonic-gate done: 433*7c478bd9Sstevel@tonic-gate /* optional: stdphysio(sync_reg_pa - 8, ino_mask); */ 434*7c478bd9Sstevel@tonic-gate if (locked) 435*7c478bd9Sstevel@tonic-gate mutex_exit(&pbm_p->pbm_sync_mutex); 436*7c478bd9Sstevel@tonic-gate 437*7c478bd9Sstevel@tonic-gate if (tomatillo_store_store_wrka) { 438*7c478bd9Sstevel@tonic-gate #if !defined(lint) 439*7c478bd9Sstevel@tonic-gate kpreempt_disable(); 440*7c478bd9Sstevel@tonic-gate #endif 441*7c478bd9Sstevel@tonic-gate tomatillo_store_store_order(); 442*7c478bd9Sstevel@tonic-gate #if !defined(lint) 443*7c478bd9Sstevel@tonic-gate kpreempt_enable(); 444*7c478bd9Sstevel@tonic-gate #endif 445*7c478bd9Sstevel@tonic-gate } 446*7c478bd9Sstevel@tonic-gate 447*7c478bd9Sstevel@tonic-gate } 448*7c478bd9Sstevel@tonic-gate 449*7c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 450*7c478bd9Sstevel@tonic-gate void 451*7c478bd9Sstevel@tonic-gate pci_fix_ranges(pci_ranges_t *rng_p, int rng_entries) 452*7c478bd9Sstevel@tonic-gate { 453*7c478bd9Sstevel@tonic-gate } 454*7c478bd9Sstevel@tonic-gate 455*7c478bd9Sstevel@tonic-gate /* 456*7c478bd9Sstevel@tonic-gate * map_pci_registers 457*7c478bd9Sstevel@tonic-gate * 458*7c478bd9Sstevel@tonic-gate * This function is called from the attach routine to map the registers 459*7c478bd9Sstevel@tonic-gate * accessed by this driver. 460*7c478bd9Sstevel@tonic-gate * 461*7c478bd9Sstevel@tonic-gate * used by: pci_attach() 462*7c478bd9Sstevel@tonic-gate * 463*7c478bd9Sstevel@tonic-gate * return value: DDI_FAILURE on failure 464*7c478bd9Sstevel@tonic-gate */ 465*7c478bd9Sstevel@tonic-gate int 466*7c478bd9Sstevel@tonic-gate map_pci_registers(pci_t *pci_p, dev_info_t *dip) 467*7c478bd9Sstevel@tonic-gate { 468*7c478bd9Sstevel@tonic-gate ddi_device_acc_attr_t attr; 469*7c478bd9Sstevel@tonic-gate int len; 470*7c478bd9Sstevel@tonic-gate 471*7c478bd9Sstevel@tonic-gate attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 472*7c478bd9Sstevel@tonic-gate attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 473*7c478bd9Sstevel@tonic-gate 474*7c478bd9Sstevel@tonic-gate attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 475*7c478bd9Sstevel@tonic-gate /* 476*7c478bd9Sstevel@tonic-gate * Register set 0 is PCI CSR Base 477*7c478bd9Sstevel@tonic-gate */ 478*7c478bd9Sstevel@tonic-gate if (ddi_regs_map_setup(dip, 0, &pci_p->pci_address[0], 0, 0, 479*7c478bd9Sstevel@tonic-gate &attr, &pci_p->pci_ac[0]) != DDI_SUCCESS) { 480*7c478bd9Sstevel@tonic-gate len = 0; 481*7c478bd9Sstevel@tonic-gate goto fail; 482*7c478bd9Sstevel@tonic-gate } 483*7c478bd9Sstevel@tonic-gate /* 484*7c478bd9Sstevel@tonic-gate * Register set 1 is Schizo CSR Base 485*7c478bd9Sstevel@tonic-gate */ 486*7c478bd9Sstevel@tonic-gate if (ddi_regs_map_setup(dip, 1, &pci_p->pci_address[1], 0, 0, 487*7c478bd9Sstevel@tonic-gate &attr, &pci_p->pci_ac[1]) != DDI_SUCCESS) { 488*7c478bd9Sstevel@tonic-gate len = 1; 489*7c478bd9Sstevel@tonic-gate goto fail; 490*7c478bd9Sstevel@tonic-gate } 491*7c478bd9Sstevel@tonic-gate 492*7c478bd9Sstevel@tonic-gate /* 493*7c478bd9Sstevel@tonic-gate * The third register set contains the bridge's configuration 494*7c478bd9Sstevel@tonic-gate * header. This header is at the very beginning of the bridge's 495*7c478bd9Sstevel@tonic-gate * configuration space. This space has litte-endian byte order. 496*7c478bd9Sstevel@tonic-gate */ 497*7c478bd9Sstevel@tonic-gate attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 498*7c478bd9Sstevel@tonic-gate if (ddi_regs_map_setup(dip, 2, &pci_p->pci_address[2], 0, 499*7c478bd9Sstevel@tonic-gate PCI_CONF_HDR_SIZE, &attr, &pci_p->pci_ac[2]) != DDI_SUCCESS) { 500*7c478bd9Sstevel@tonic-gate len = 2; 501*7c478bd9Sstevel@tonic-gate goto fail; 502*7c478bd9Sstevel@tonic-gate } 503*7c478bd9Sstevel@tonic-gate 504*7c478bd9Sstevel@tonic-gate if (ddi_getproplen(DDI_DEV_T_NONE, dip, DDI_PROP_DONTPASS, 505*7c478bd9Sstevel@tonic-gate "reg", &len) || (len / sizeof (pci_nexus_regspec_t) < 4)) 506*7c478bd9Sstevel@tonic-gate goto done; 507*7c478bd9Sstevel@tonic-gate 508*7c478bd9Sstevel@tonic-gate /* 509*7c478bd9Sstevel@tonic-gate * The optional fourth register bank points to the 510*7c478bd9Sstevel@tonic-gate * interrupt concentrator registers. 511*7c478bd9Sstevel@tonic-gate */ 512*7c478bd9Sstevel@tonic-gate attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 513*7c478bd9Sstevel@tonic-gate if (ddi_regs_map_setup(dip, 3, &pci_p->pci_address[3], 0, 514*7c478bd9Sstevel@tonic-gate 0, &attr, &pci_p->pci_ac[3]) != DDI_SUCCESS) { 515*7c478bd9Sstevel@tonic-gate len = 3; 516*7c478bd9Sstevel@tonic-gate goto fail; 517*7c478bd9Sstevel@tonic-gate } 518*7c478bd9Sstevel@tonic-gate 519*7c478bd9Sstevel@tonic-gate done: 520*7c478bd9Sstevel@tonic-gate DEBUG4(DBG_ATTACH, dip, "address (%p,%p,%p,%p)\n", 521*7c478bd9Sstevel@tonic-gate pci_p->pci_address[0], pci_p->pci_address[1], 522*7c478bd9Sstevel@tonic-gate pci_p->pci_address[2], pci_p->pci_address[3]); 523*7c478bd9Sstevel@tonic-gate 524*7c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 525*7c478bd9Sstevel@tonic-gate 526*7c478bd9Sstevel@tonic-gate 527*7c478bd9Sstevel@tonic-gate fail: 528*7c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "%s%d: unable to map reg entry %d\n", 529*7c478bd9Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip), len); 530*7c478bd9Sstevel@tonic-gate for (; len--; ddi_regs_map_free(&pci_p->pci_ac[len])); 531*7c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 532*7c478bd9Sstevel@tonic-gate } 533*7c478bd9Sstevel@tonic-gate 534*7c478bd9Sstevel@tonic-gate /* 535*7c478bd9Sstevel@tonic-gate * unmap_pci_registers: 536*7c478bd9Sstevel@tonic-gate * 537*7c478bd9Sstevel@tonic-gate * This routine unmap the registers mapped by map_pci_registers. 538*7c478bd9Sstevel@tonic-gate * 539*7c478bd9Sstevel@tonic-gate * used by: pci_detach() 540*7c478bd9Sstevel@tonic-gate * 541*7c478bd9Sstevel@tonic-gate * return value: none 542*7c478bd9Sstevel@tonic-gate */ 543*7c478bd9Sstevel@tonic-gate void 544*7c478bd9Sstevel@tonic-gate unmap_pci_registers(pci_t *pci_p) 545*7c478bd9Sstevel@tonic-gate { 546*7c478bd9Sstevel@tonic-gate int i; 547*7c478bd9Sstevel@tonic-gate 548*7c478bd9Sstevel@tonic-gate for (i = 0; i < 4; i++) { 549*7c478bd9Sstevel@tonic-gate if (pci_p->pci_ac[i]) 550*7c478bd9Sstevel@tonic-gate ddi_regs_map_free(&pci_p->pci_ac[i]); 551*7c478bd9Sstevel@tonic-gate } 552*7c478bd9Sstevel@tonic-gate } 553*7c478bd9Sstevel@tonic-gate 554*7c478bd9Sstevel@tonic-gate uint64_t 555*7c478bd9Sstevel@tonic-gate ib_get_map_reg(ib_mondo_t mondo, uint32_t cpu_id) 556*7c478bd9Sstevel@tonic-gate { 557*7c478bd9Sstevel@tonic-gate uint32_t agent_id; 558*7c478bd9Sstevel@tonic-gate uint32_t node_id; 559*7c478bd9Sstevel@tonic-gate 560*7c478bd9Sstevel@tonic-gate /* ensure that cpu_id is only 10 bits. */ 561*7c478bd9Sstevel@tonic-gate ASSERT((cpu_id & ~0x3ff) == 0); 562*7c478bd9Sstevel@tonic-gate 563*7c478bd9Sstevel@tonic-gate agent_id = cpu_id & 0x1f; 564*7c478bd9Sstevel@tonic-gate node_id = (cpu_id >> 5) & 0x1f; 565*7c478bd9Sstevel@tonic-gate 566*7c478bd9Sstevel@tonic-gate return ((mondo) | (agent_id << COMMON_INTR_MAP_REG_TID_SHIFT) | 567*7c478bd9Sstevel@tonic-gate (node_id << SCHIZO_INTR_MAP_REG_NID_SHIFT) | 568*7c478bd9Sstevel@tonic-gate COMMON_INTR_MAP_REG_VALID); 569*7c478bd9Sstevel@tonic-gate } 570*7c478bd9Sstevel@tonic-gate 571*7c478bd9Sstevel@tonic-gate uint32_t 572*7c478bd9Sstevel@tonic-gate ib_map_reg_get_cpu(volatile uint64_t reg) 573*7c478bd9Sstevel@tonic-gate { 574*7c478bd9Sstevel@tonic-gate return (((reg & COMMON_INTR_MAP_REG_TID) >> 575*7c478bd9Sstevel@tonic-gate COMMON_INTR_MAP_REG_TID_SHIFT) | 576*7c478bd9Sstevel@tonic-gate ((reg & SCHIZO_INTR_MAP_REG_NID) >> 577*7c478bd9Sstevel@tonic-gate (SCHIZO_INTR_MAP_REG_NID_SHIFT-5))); 578*7c478bd9Sstevel@tonic-gate } 579*7c478bd9Sstevel@tonic-gate 580*7c478bd9Sstevel@tonic-gate uint64_t * 581*7c478bd9Sstevel@tonic-gate ib_intr_map_reg_addr(ib_t *ib_p, ib_ino_t ino) 582*7c478bd9Sstevel@tonic-gate { 583*7c478bd9Sstevel@tonic-gate /* 584*7c478bd9Sstevel@tonic-gate * Schizo maps all interrupts in one contiguous area. 585*7c478bd9Sstevel@tonic-gate * (PCI_CSRBase + 0x00.1000 + INO * 8). 586*7c478bd9Sstevel@tonic-gate */ 587*7c478bd9Sstevel@tonic-gate return ((uint64_t *)(ib_p->ib_intr_map_regs) + (ino & 0x3f)); 588*7c478bd9Sstevel@tonic-gate } 589*7c478bd9Sstevel@tonic-gate 590*7c478bd9Sstevel@tonic-gate uint64_t * 591*7c478bd9Sstevel@tonic-gate ib_clear_intr_reg_addr(ib_t *ib_p, ib_ino_t ino) /* XXX - needs work */ 592*7c478bd9Sstevel@tonic-gate { 593*7c478bd9Sstevel@tonic-gate /* 594*7c478bd9Sstevel@tonic-gate * Schizo maps clear intr. registers in contiguous area. 595*7c478bd9Sstevel@tonic-gate * (PCI_CSRBase + 0x00.1400 + INO * 8). 596*7c478bd9Sstevel@tonic-gate */ 597*7c478bd9Sstevel@tonic-gate return ((uint64_t *)(ib_p->ib_slot_clear_intr_regs) + (ino & 0x3f)); 598*7c478bd9Sstevel@tonic-gate } 599*7c478bd9Sstevel@tonic-gate 600*7c478bd9Sstevel@tonic-gate /* 601*7c478bd9Sstevel@tonic-gate * schizo does not have mapping register per slot, so no sharing 602*7c478bd9Sstevel@tonic-gate * is done. 603*7c478bd9Sstevel@tonic-gate */ 604*7c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 605*7c478bd9Sstevel@tonic-gate void 606*7c478bd9Sstevel@tonic-gate ib_ino_map_reg_share(ib_t *ib_p, ib_ino_t ino, ib_ino_info_t *ino_p) 607*7c478bd9Sstevel@tonic-gate { 608*7c478bd9Sstevel@tonic-gate } 609*7c478bd9Sstevel@tonic-gate 610*7c478bd9Sstevel@tonic-gate /* 611*7c478bd9Sstevel@tonic-gate * return true if there are interrupts using this mapping register 612*7c478bd9Sstevel@tonic-gate */ 613*7c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 614*7c478bd9Sstevel@tonic-gate int 615*7c478bd9Sstevel@tonic-gate ib_ino_map_reg_unshare(ib_t *ib_p, ib_ino_t ino, ib_ino_info_t *ino_p) 616*7c478bd9Sstevel@tonic-gate { 617*7c478bd9Sstevel@tonic-gate return (ino_p->ino_ih_size); 618*7c478bd9Sstevel@tonic-gate } 619*7c478bd9Sstevel@tonic-gate 620*7c478bd9Sstevel@tonic-gate void 621*7c478bd9Sstevel@tonic-gate pci_pbm_intr_dist(pbm_t *pbm_p) 622*7c478bd9Sstevel@tonic-gate { 623*7c478bd9Sstevel@tonic-gate pci_t *pci_p = pbm_p->pbm_pci_p; 624*7c478bd9Sstevel@tonic-gate ib_t *ib_p = pci_p->pci_ib_p; 625*7c478bd9Sstevel@tonic-gate ib_ino_t ino = IB_MONDO_TO_INO(pci_p->pci_inos[CBNINTR_CDMA]); 626*7c478bd9Sstevel@tonic-gate 627*7c478bd9Sstevel@tonic-gate mutex_enter(&pbm_p->pbm_sync_mutex); 628*7c478bd9Sstevel@tonic-gate ib_intr_dist_nintr(ib_p, ino, ib_intr_map_reg_addr(ib_p, ino)); 629*7c478bd9Sstevel@tonic-gate mutex_exit(&pbm_p->pbm_sync_mutex); 630*7c478bd9Sstevel@tonic-gate } 631*7c478bd9Sstevel@tonic-gate 632*7c478bd9Sstevel@tonic-gate uint32_t 633*7c478bd9Sstevel@tonic-gate pci_xlate_intr(dev_info_t *dip, dev_info_t *rdip, ib_t *ib_p, uint32_t intr) 634*7c478bd9Sstevel@tonic-gate { 635*7c478bd9Sstevel@tonic-gate return (IB_INO_TO_MONDO(ib_p, intr)); 636*7c478bd9Sstevel@tonic-gate } 637*7c478bd9Sstevel@tonic-gate 638*7c478bd9Sstevel@tonic-gate 639*7c478bd9Sstevel@tonic-gate /* 640*7c478bd9Sstevel@tonic-gate * Return the cpuid to to be used for an ino. We have no special cpu 641*7c478bd9Sstevel@tonic-gate * assignment constraints for this nexus, so just call intr_dist_cpuid(). 642*7c478bd9Sstevel@tonic-gate */ 643*7c478bd9Sstevel@tonic-gate /* ARGSUSED */ 644*7c478bd9Sstevel@tonic-gate uint32_t 645*7c478bd9Sstevel@tonic-gate pci_intr_dist_cpuid(ib_t *ib_p, ib_ino_info_t *ino_p) 646*7c478bd9Sstevel@tonic-gate { 647*7c478bd9Sstevel@tonic-gate return (intr_dist_cpuid()); 648*7c478bd9Sstevel@tonic-gate } 649*7c478bd9Sstevel@tonic-gate 650*7c478bd9Sstevel@tonic-gate void 651*7c478bd9Sstevel@tonic-gate pci_cb_teardown(pci_t *pci_p) 652*7c478bd9Sstevel@tonic-gate { 653*7c478bd9Sstevel@tonic-gate cb_t *cb_p = pci_p->pci_cb_p; 654*7c478bd9Sstevel@tonic-gate uint32_t mondo; 655*7c478bd9Sstevel@tonic-gate 656*7c478bd9Sstevel@tonic-gate if (!pci_buserr_interrupt) 657*7c478bd9Sstevel@tonic-gate return; 658*7c478bd9Sstevel@tonic-gate 659*7c478bd9Sstevel@tonic-gate mondo = ((pci_p->pci_cb_p->cb_ign << PCI_INO_BITS) | 660*7c478bd9Sstevel@tonic-gate pci_p->pci_inos[CBNINTR_BUS_ERROR]); 661*7c478bd9Sstevel@tonic-gate mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 662*7c478bd9Sstevel@tonic-gate 663*7c478bd9Sstevel@tonic-gate cb_disable_nintr(cb_p, CBNINTR_BUS_ERROR, IB_INTR_WAIT); 664*7c478bd9Sstevel@tonic-gate rem_ivintr(mondo, NULL); 665*7c478bd9Sstevel@tonic-gate } 666*7c478bd9Sstevel@tonic-gate 667*7c478bd9Sstevel@tonic-gate int 668*7c478bd9Sstevel@tonic-gate cb_register_intr(pci_t *pci_p) 669*7c478bd9Sstevel@tonic-gate { 670*7c478bd9Sstevel@tonic-gate uint32_t mondo; 671*7c478bd9Sstevel@tonic-gate 672*7c478bd9Sstevel@tonic-gate if (!pci_buserr_interrupt) 673*7c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 674*7c478bd9Sstevel@tonic-gate 675*7c478bd9Sstevel@tonic-gate mondo = ((pci_p->pci_cb_p->cb_ign << PCI_INO_BITS) | 676*7c478bd9Sstevel@tonic-gate pci_p->pci_inos[CBNINTR_BUS_ERROR]); 677*7c478bd9Sstevel@tonic-gate mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 678*7c478bd9Sstevel@tonic-gate 679*7c478bd9Sstevel@tonic-gate VERIFY(add_ivintr(mondo, pci_pil[CBNINTR_BUS_ERROR], 680*7c478bd9Sstevel@tonic-gate cb_buserr_intr, (caddr_t)pci_p->pci_cb_p, NULL) == 0); 681*7c478bd9Sstevel@tonic-gate 682*7c478bd9Sstevel@tonic-gate return (PCI_ATTACH_RETCODE(PCI_CB_OBJ, PCI_OBJ_INTR_ADD, DDI_SUCCESS)); 683*7c478bd9Sstevel@tonic-gate } 684*7c478bd9Sstevel@tonic-gate 685*7c478bd9Sstevel@tonic-gate void 686*7c478bd9Sstevel@tonic-gate cb_enable_intr(pci_t *pci_p) 687*7c478bd9Sstevel@tonic-gate { 688*7c478bd9Sstevel@tonic-gate if (pci_buserr_interrupt) 689*7c478bd9Sstevel@tonic-gate cb_enable_nintr(pci_p, CBNINTR_BUS_ERROR); 690*7c478bd9Sstevel@tonic-gate } 691*7c478bd9Sstevel@tonic-gate 692*7c478bd9Sstevel@tonic-gate uint64_t 693*7c478bd9Sstevel@tonic-gate cb_ino_to_map_pa(cb_t *cb_p, ib_ino_t ino) 694*7c478bd9Sstevel@tonic-gate { 695*7c478bd9Sstevel@tonic-gate return (cb_p->cb_map_pa + (ino << 3)); 696*7c478bd9Sstevel@tonic-gate } 697*7c478bd9Sstevel@tonic-gate 698*7c478bd9Sstevel@tonic-gate uint64_t 699*7c478bd9Sstevel@tonic-gate cb_ino_to_clr_pa(cb_t *cb_p, ib_ino_t ino) 700*7c478bd9Sstevel@tonic-gate { 701*7c478bd9Sstevel@tonic-gate return (cb_p->cb_clr_pa + (ino << 3)); 702*7c478bd9Sstevel@tonic-gate } 703*7c478bd9Sstevel@tonic-gate 704*7c478bd9Sstevel@tonic-gate /* 705*7c478bd9Sstevel@tonic-gate * Useful on psycho only. 706*7c478bd9Sstevel@tonic-gate */ 707*7c478bd9Sstevel@tonic-gate int 708*7c478bd9Sstevel@tonic-gate cb_remove_xintr(pci_t *pci_p, dev_info_t *dip, dev_info_t *rdip, ib_ino_t ino, 709*7c478bd9Sstevel@tonic-gate ib_mondo_t mondo) 710*7c478bd9Sstevel@tonic-gate { 711*7c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 712*7c478bd9Sstevel@tonic-gate } 713*7c478bd9Sstevel@tonic-gate 714*7c478bd9Sstevel@tonic-gate void 715*7c478bd9Sstevel@tonic-gate pbm_configure(pbm_t *pbm_p) 716*7c478bd9Sstevel@tonic-gate { 717*7c478bd9Sstevel@tonic-gate pci_t *pci_p = pbm_p->pbm_pci_p; 718*7c478bd9Sstevel@tonic-gate dev_info_t *dip = pbm_p->pbm_pci_p->pci_dip; 719*7c478bd9Sstevel@tonic-gate int instance = ddi_get_instance(dip); 720*7c478bd9Sstevel@tonic-gate uint64_t l; 721*7c478bd9Sstevel@tonic-gate uint64_t mask = 1ll << instance; 722*7c478bd9Sstevel@tonic-gate ushort_t s = 0; 723*7c478bd9Sstevel@tonic-gate 724*7c478bd9Sstevel@tonic-gate l = *pbm_p->pbm_ctrl_reg; /* save control register state */ 725*7c478bd9Sstevel@tonic-gate DEBUG1(DBG_ATTACH, dip, "pbm_configure: ctrl reg=%llx\n", l); 726*7c478bd9Sstevel@tonic-gate 727*7c478bd9Sstevel@tonic-gate /* 728*7c478bd9Sstevel@tonic-gate * See if any SERR# signals are asserted. We'll clear them later. 729*7c478bd9Sstevel@tonic-gate */ 730*7c478bd9Sstevel@tonic-gate if (l & COMMON_PCI_CTRL_SERR) 731*7c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "%s%d: SERR asserted on pci bus\n", 732*7c478bd9Sstevel@tonic-gate ddi_driver_name(dip), instance); 733*7c478bd9Sstevel@tonic-gate 734*7c478bd9Sstevel@tonic-gate /* 735*7c478bd9Sstevel@tonic-gate * Determine if PCI bus is running at 33 or 66 mhz. 736*7c478bd9Sstevel@tonic-gate */ 737*7c478bd9Sstevel@tonic-gate if (l & COMMON_PCI_CTRL_SPEED) 738*7c478bd9Sstevel@tonic-gate pbm_p->pbm_speed = PBM_SPEED_66MHZ; 739*7c478bd9Sstevel@tonic-gate else 740*7c478bd9Sstevel@tonic-gate pbm_p->pbm_speed = PBM_SPEED_33MHZ; 741*7c478bd9Sstevel@tonic-gate DEBUG1(DBG_ATTACH, dip, "pbm_configure: %d mhz\n", 742*7c478bd9Sstevel@tonic-gate pbm_p->pbm_speed == PBM_SPEED_66MHZ ? 66 : 33); 743*7c478bd9Sstevel@tonic-gate 744*7c478bd9Sstevel@tonic-gate if (pci_set_dto_value & mask) { 745*7c478bd9Sstevel@tonic-gate l &= ~(3ull << SCHIZO_PCI_CTRL_PTO_SHIFT); 746*7c478bd9Sstevel@tonic-gate l |= pci_dto_value << SCHIZO_PCI_CTRL_PTO_SHIFT; 747*7c478bd9Sstevel@tonic-gate } else if (PCI_CHIP_ID(pci_p) >= TOMATILLO_VER_21) { 748*7c478bd9Sstevel@tonic-gate l |= (3ull << SCHIZO_PCI_CTRL_PTO_SHIFT); 749*7c478bd9Sstevel@tonic-gate } 750*7c478bd9Sstevel@tonic-gate 751*7c478bd9Sstevel@tonic-gate /* 752*7c478bd9Sstevel@tonic-gate * Enable error interrupts. 753*7c478bd9Sstevel@tonic-gate */ 754*7c478bd9Sstevel@tonic-gate if (pci_error_intr_enable & mask) 755*7c478bd9Sstevel@tonic-gate l |= SCHIZO_PCI_CTRL_ERR_INT_EN; 756*7c478bd9Sstevel@tonic-gate else 757*7c478bd9Sstevel@tonic-gate l &= ~SCHIZO_PCI_CTRL_ERR_INT_EN; 758*7c478bd9Sstevel@tonic-gate 759*7c478bd9Sstevel@tonic-gate /* 760*7c478bd9Sstevel@tonic-gate * Enable pci streaming byte errors and error interrupts. 761*7c478bd9Sstevel@tonic-gate */ 762*7c478bd9Sstevel@tonic-gate if (pci_sbh_error_intr_enable & mask) 763*7c478bd9Sstevel@tonic-gate l |= SCHIZO_PCI_CTRL_SBH_INT_EN; 764*7c478bd9Sstevel@tonic-gate else 765*7c478bd9Sstevel@tonic-gate l &= ~SCHIZO_PCI_CTRL_SBH_INT_EN; 766*7c478bd9Sstevel@tonic-gate 767*7c478bd9Sstevel@tonic-gate /* 768*7c478bd9Sstevel@tonic-gate * Enable pci discard timeout error interrupt. 769*7c478bd9Sstevel@tonic-gate */ 770*7c478bd9Sstevel@tonic-gate if (pci_mmu_error_intr_enable & mask) 771*7c478bd9Sstevel@tonic-gate l |= SCHIZO_PCI_CTRL_MMU_INT_EN; 772*7c478bd9Sstevel@tonic-gate else 773*7c478bd9Sstevel@tonic-gate l &= ~SCHIZO_PCI_CTRL_MMU_INT_EN; 774*7c478bd9Sstevel@tonic-gate 775*7c478bd9Sstevel@tonic-gate /* 776*7c478bd9Sstevel@tonic-gate * Enable PCI-X error interrupts. 777*7c478bd9Sstevel@tonic-gate */ 778*7c478bd9Sstevel@tonic-gate if (CHIP_TYPE(pci_p) == PCI_CHIP_XMITS) { 779*7c478bd9Sstevel@tonic-gate 780*7c478bd9Sstevel@tonic-gate if (xmits_error_intr_enable & mask) 781*7c478bd9Sstevel@tonic-gate l |= XMITS_PCI_CTRL_X_ERRINT_EN; 782*7c478bd9Sstevel@tonic-gate else 783*7c478bd9Sstevel@tonic-gate l &= ~XMITS_PCI_CTRL_X_ERRINT_EN; 784*7c478bd9Sstevel@tonic-gate /* 785*7c478bd9Sstevel@tonic-gate * Panic if older XMITS hardware is found. 786*7c478bd9Sstevel@tonic-gate */ 787*7c478bd9Sstevel@tonic-gate if (*pbm_p->pbm_ctrl_reg & XMITS_PCI_CTRL_X_MODE) 788*7c478bd9Sstevel@tonic-gate if (PCI_CHIP_ID(pci_p) <= XMITS_VER_10) 789*7c478bd9Sstevel@tonic-gate cmn_err(CE_PANIC, "%s (%s): PCIX mode " 790*7c478bd9Sstevel@tonic-gate "unsupported on XMITS version %d\n", 791*7c478bd9Sstevel@tonic-gate pbm_p->pbm_nameinst_str, 792*7c478bd9Sstevel@tonic-gate pbm_p->pbm_nameaddr_str, CHIP_VER(pci_p)); 793*7c478bd9Sstevel@tonic-gate 794*7c478bd9Sstevel@tonic-gate if (xmits_perr_recov_int_enable) { 795*7c478bd9Sstevel@tonic-gate if (PCI_CHIP_ID(pci_p) >= XMITS_VER_30) { 796*7c478bd9Sstevel@tonic-gate uint64_t pcix_err; 797*7c478bd9Sstevel@tonic-gate /* 798*7c478bd9Sstevel@tonic-gate * Enable interrupt on PERR 799*7c478bd9Sstevel@tonic-gate */ 800*7c478bd9Sstevel@tonic-gate pcix_err = *pbm_p->pbm_pcix_err_stat_reg; 801*7c478bd9Sstevel@tonic-gate pcix_err |= XMITS_PCIX_STAT_PERR_RECOV_INT_EN; 802*7c478bd9Sstevel@tonic-gate pcix_err &= ~XMITS_PCIX_STAT_SERR_ON_PERR; 803*7c478bd9Sstevel@tonic-gate *pbm_p->pbm_pcix_err_stat_reg = pcix_err; 804*7c478bd9Sstevel@tonic-gate } 805*7c478bd9Sstevel@tonic-gate } 806*7c478bd9Sstevel@tonic-gate 807*7c478bd9Sstevel@tonic-gate /* 808*7c478bd9Sstevel@tonic-gate * Enable parity error detection on internal memories 809*7c478bd9Sstevel@tonic-gate */ 810*7c478bd9Sstevel@tonic-gate *pbm_p->pbm_pci_ped_ctrl = 0x3fff; 811*7c478bd9Sstevel@tonic-gate } 812*7c478bd9Sstevel@tonic-gate 813*7c478bd9Sstevel@tonic-gate /* 814*7c478bd9Sstevel@tonic-gate * Enable/disable bus parking. 815*7c478bd9Sstevel@tonic-gate */ 816*7c478bd9Sstevel@tonic-gate if ((pci_bus_parking_enable & mask) && 817*7c478bd9Sstevel@tonic-gate !ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 818*7c478bd9Sstevel@tonic-gate "no-bus-parking")) 819*7c478bd9Sstevel@tonic-gate l |= SCHIZO_PCI_CTRL_ARB_PARK; 820*7c478bd9Sstevel@tonic-gate else 821*7c478bd9Sstevel@tonic-gate l &= ~SCHIZO_PCI_CTRL_ARB_PARK; 822*7c478bd9Sstevel@tonic-gate 823*7c478bd9Sstevel@tonic-gate /* 824*7c478bd9Sstevel@tonic-gate * Enable arbitration. 825*7c478bd9Sstevel@tonic-gate */ 826*7c478bd9Sstevel@tonic-gate l |= PCI_CHIP_ID(pci_p) == XMITS_VER_10 ? XMITS10_PCI_CTRL_ARB_EN_MASK : 827*7c478bd9Sstevel@tonic-gate SCHIZO_PCI_CTRL_ARB_EN_MASK; 828*7c478bd9Sstevel@tonic-gate 829*7c478bd9Sstevel@tonic-gate /* 830*7c478bd9Sstevel@tonic-gate * Make sure SERR is clear 831*7c478bd9Sstevel@tonic-gate */ 832*7c478bd9Sstevel@tonic-gate l |= COMMON_PCI_CTRL_SERR; 833*7c478bd9Sstevel@tonic-gate 834*7c478bd9Sstevel@tonic-gate 835*7c478bd9Sstevel@tonic-gate /* 836*7c478bd9Sstevel@tonic-gate * Enable DTO interrupt, if desired. 837*7c478bd9Sstevel@tonic-gate */ 838*7c478bd9Sstevel@tonic-gate 839*7c478bd9Sstevel@tonic-gate if (PCI_CHIP_ID(pci_p) <= TOMATILLO_VER_20 || (pci_dto_intr_enable & 840*7c478bd9Sstevel@tonic-gate mask)) 841*7c478bd9Sstevel@tonic-gate l |= (TOMATILLO_PCI_CTRL_DTO_INT_EN); 842*7c478bd9Sstevel@tonic-gate else 843*7c478bd9Sstevel@tonic-gate l &= ~(TOMATILLO_PCI_CTRL_DTO_INT_EN); 844*7c478bd9Sstevel@tonic-gate 845*7c478bd9Sstevel@tonic-gate l |= TOMATILLO_PCI_CTRL_PEN_RD_MLTPL | 846*7c478bd9Sstevel@tonic-gate TOMATILLO_PCI_CTRL_PEN_RD_ONE | 847*7c478bd9Sstevel@tonic-gate TOMATILLO_PCI_CTRL_PEN_RD_LINE; 848*7c478bd9Sstevel@tonic-gate 849*7c478bd9Sstevel@tonic-gate /* 850*7c478bd9Sstevel@tonic-gate * Now finally write the control register with the appropriate value. 851*7c478bd9Sstevel@tonic-gate */ 852*7c478bd9Sstevel@tonic-gate DEBUG1(DBG_ATTACH, dip, "pbm_configure: ctrl reg=%llx\n", l); 853*7c478bd9Sstevel@tonic-gate *pbm_p->pbm_ctrl_reg = l; 854*7c478bd9Sstevel@tonic-gate 855*7c478bd9Sstevel@tonic-gate /* 856*7c478bd9Sstevel@tonic-gate * Enable IO Prefetch on Tomatillo 857*7c478bd9Sstevel@tonic-gate */ 858*7c478bd9Sstevel@tonic-gate if (CHIP_TYPE(pci_p) == PCI_CHIP_TOMATILLO) { 859*7c478bd9Sstevel@tonic-gate volatile uint64_t *ioc_csr_p = pbm_p->pbm_ctrl_reg + 860*7c478bd9Sstevel@tonic-gate ((TOMATILLO_IOC_CSR_OFF - 861*7c478bd9Sstevel@tonic-gate SCHIZO_PCI_CTRL_REG_OFFSET) >> 3); 862*7c478bd9Sstevel@tonic-gate *ioc_csr_p = TOMATILLO_WRT_PEN | 863*7c478bd9Sstevel@tonic-gate (1 << TOMATILLO_POFFSET_SHIFT) | 864*7c478bd9Sstevel@tonic-gate TOMATILLO_C_PEN_RD_MLTPL | 865*7c478bd9Sstevel@tonic-gate TOMATILLO_C_PEN_RD_ONE | 866*7c478bd9Sstevel@tonic-gate TOMATILLO_C_PEN_RD_LINE; 867*7c478bd9Sstevel@tonic-gate } 868*7c478bd9Sstevel@tonic-gate 869*7c478bd9Sstevel@tonic-gate /* 870*7c478bd9Sstevel@tonic-gate * Allow DMA write parity errors to generate an interrupt. 871*7c478bd9Sstevel@tonic-gate * This is implemented on Schizo 2.5 and greater and XMITS 3.0 872*7c478bd9Sstevel@tonic-gate * and greater. Setting this on earlier versions of XMITS 3.0 873*7c478bd9Sstevel@tonic-gate * has no affect. 874*7c478bd9Sstevel@tonic-gate */ 875*7c478bd9Sstevel@tonic-gate if (((CHIP_TYPE(pci_p) == PCI_CHIP_SCHIZO) && 876*7c478bd9Sstevel@tonic-gate PCI_CHIP_ID(pci_p) >= SCHIZO_VER_25) || 877*7c478bd9Sstevel@tonic-gate (CHIP_TYPE(pci_p) == PCI_CHIP_XMITS)) { 878*7c478bd9Sstevel@tonic-gate volatile uint64_t *pbm_icd = pbm_p->pbm_ctrl_reg + 879*7c478bd9Sstevel@tonic-gate ((SCHIZO_PERF_PCI_ICD_OFFSET - 880*7c478bd9Sstevel@tonic-gate SCHIZO_PCI_CTRL_REG_OFFSET) >> 3); 881*7c478bd9Sstevel@tonic-gate 882*7c478bd9Sstevel@tonic-gate *pbm_icd |= SCHIZO_PERF_PCI_ICD_DMAW_PARITY_INT_ENABLE; 883*7c478bd9Sstevel@tonic-gate } 884*7c478bd9Sstevel@tonic-gate 885*7c478bd9Sstevel@tonic-gate /* 886*7c478bd9Sstevel@tonic-gate * Clear any PBM errors. 887*7c478bd9Sstevel@tonic-gate */ 888*7c478bd9Sstevel@tonic-gate l = (SCHIZO_PCI_AFSR_E_MASK << SCHIZO_PCI_AFSR_PE_SHIFT) | 889*7c478bd9Sstevel@tonic-gate (SCHIZO_PCI_AFSR_E_MASK << SCHIZO_PCI_AFSR_SE_SHIFT); 890*7c478bd9Sstevel@tonic-gate *pbm_p->pbm_async_flt_status_reg = l; 891*7c478bd9Sstevel@tonic-gate 892*7c478bd9Sstevel@tonic-gate /* 893*7c478bd9Sstevel@tonic-gate * Allow the diag register to be set based upon variable that 894*7c478bd9Sstevel@tonic-gate * can be configured via /etc/system. 895*7c478bd9Sstevel@tonic-gate */ 896*7c478bd9Sstevel@tonic-gate l = *pbm_p->pbm_diag_reg; 897*7c478bd9Sstevel@tonic-gate DEBUG1(DBG_ATTACH, dip, "pbm_configure: PCI diag reg=%llx\n", l); 898*7c478bd9Sstevel@tonic-gate 899*7c478bd9Sstevel@tonic-gate /* 900*7c478bd9Sstevel@tonic-gate * Enable/disable retry limit. 901*7c478bd9Sstevel@tonic-gate */ 902*7c478bd9Sstevel@tonic-gate if (pci_retry_disable & mask) 903*7c478bd9Sstevel@tonic-gate l |= COMMON_PCI_DIAG_DIS_RETRY; 904*7c478bd9Sstevel@tonic-gate else 905*7c478bd9Sstevel@tonic-gate l &= ~COMMON_PCI_DIAG_DIS_RETRY; 906*7c478bd9Sstevel@tonic-gate 907*7c478bd9Sstevel@tonic-gate /* 908*7c478bd9Sstevel@tonic-gate * Enable/disable DMA write/interrupt synchronization. 909*7c478bd9Sstevel@tonic-gate */ 910*7c478bd9Sstevel@tonic-gate if (pci_intsync_disable & mask) 911*7c478bd9Sstevel@tonic-gate l |= COMMON_PCI_DIAG_DIS_INTSYNC; 912*7c478bd9Sstevel@tonic-gate else 913*7c478bd9Sstevel@tonic-gate l &= ~COMMON_PCI_DIAG_DIS_INTSYNC; 914*7c478bd9Sstevel@tonic-gate 915*7c478bd9Sstevel@tonic-gate /* 916*7c478bd9Sstevel@tonic-gate * Enable/disable retry arbitration priority. 917*7c478bd9Sstevel@tonic-gate */ 918*7c478bd9Sstevel@tonic-gate if (pci_enable_retry_arb & mask) 919*7c478bd9Sstevel@tonic-gate l &= ~SCHIZO_PCI_DIAG_DIS_RTRY_ARB; 920*7c478bd9Sstevel@tonic-gate else 921*7c478bd9Sstevel@tonic-gate l |= SCHIZO_PCI_DIAG_DIS_RTRY_ARB; 922*7c478bd9Sstevel@tonic-gate 923*7c478bd9Sstevel@tonic-gate DEBUG1(DBG_ATTACH, dip, "pbm_configure: PCI diag reg=%llx\n", l); 924*7c478bd9Sstevel@tonic-gate *pbm_p->pbm_diag_reg = l; 925*7c478bd9Sstevel@tonic-gate 926*7c478bd9Sstevel@tonic-gate /* 927*7c478bd9Sstevel@tonic-gate * Enable SERR# and parity reporting via command register. 928*7c478bd9Sstevel@tonic-gate */ 929*7c478bd9Sstevel@tonic-gate s = pci_perr_enable & mask ? PCI_COMM_PARITY_DETECT : 0; 930*7c478bd9Sstevel@tonic-gate s |= pci_serr_enable & mask ? PCI_COMM_SERR_ENABLE : 0; 931*7c478bd9Sstevel@tonic-gate 932*7c478bd9Sstevel@tonic-gate DEBUG1(DBG_ATTACH, dip, "pbm_configure: conf command reg=%x\n", s); 933*7c478bd9Sstevel@tonic-gate pbm_p->pbm_config_header->ch_command_reg = s; 934*7c478bd9Sstevel@tonic-gate 935*7c478bd9Sstevel@tonic-gate /* 936*7c478bd9Sstevel@tonic-gate * Clear error bits in configuration status register. 937*7c478bd9Sstevel@tonic-gate */ 938*7c478bd9Sstevel@tonic-gate s = PCI_STAT_PERROR | PCI_STAT_S_PERROR | 939*7c478bd9Sstevel@tonic-gate PCI_STAT_R_MAST_AB | PCI_STAT_R_TARG_AB | 940*7c478bd9Sstevel@tonic-gate PCI_STAT_S_TARG_AB | PCI_STAT_S_PERROR; 941*7c478bd9Sstevel@tonic-gate DEBUG1(DBG_ATTACH, dip, "pbm_configure: conf status reg=%x\n", s); 942*7c478bd9Sstevel@tonic-gate pbm_p->pbm_config_header->ch_status_reg = s; 943*7c478bd9Sstevel@tonic-gate 944*7c478bd9Sstevel@tonic-gate /* 945*7c478bd9Sstevel@tonic-gate * The current versions of the obp are suppose to set the latency 946*7c478bd9Sstevel@tonic-gate * timer register but do not. Bug 1234181 is open against this 947*7c478bd9Sstevel@tonic-gate * problem. Until this bug is fixed we check to see if the obp 948*7c478bd9Sstevel@tonic-gate * has attempted to set the latency timer register by checking 949*7c478bd9Sstevel@tonic-gate * for the existence of a "latency-timer" property. 950*7c478bd9Sstevel@tonic-gate */ 951*7c478bd9Sstevel@tonic-gate if (pci_set_latency_timer_register) { 952*7c478bd9Sstevel@tonic-gate DEBUG1(DBG_ATTACH, dip, 953*7c478bd9Sstevel@tonic-gate "pbm_configure: set schizo latency timer to %x\n", 954*7c478bd9Sstevel@tonic-gate pci_latency_timer); 955*7c478bd9Sstevel@tonic-gate pbm_p->pbm_config_header->ch_latency_timer_reg = 956*7c478bd9Sstevel@tonic-gate pci_latency_timer; 957*7c478bd9Sstevel@tonic-gate } 958*7c478bd9Sstevel@tonic-gate 959*7c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_ANY, dip, "latency-timer", 960*7c478bd9Sstevel@tonic-gate (int)pbm_p->pbm_config_header->ch_latency_timer_reg); 961*7c478bd9Sstevel@tonic-gate } 962*7c478bd9Sstevel@tonic-gate 963*7c478bd9Sstevel@tonic-gate uint_t 964*7c478bd9Sstevel@tonic-gate pbm_disable_pci_errors(pbm_t *pbm_p) 965*7c478bd9Sstevel@tonic-gate { 966*7c478bd9Sstevel@tonic-gate pci_t *pci_p = pbm_p->pbm_pci_p; 967*7c478bd9Sstevel@tonic-gate ib_t *ib_p = pci_p->pci_ib_p; 968*7c478bd9Sstevel@tonic-gate 969*7c478bd9Sstevel@tonic-gate /* 970*7c478bd9Sstevel@tonic-gate * Disable error and streaming byte hole interrupts via the 971*7c478bd9Sstevel@tonic-gate * PBM control register. 972*7c478bd9Sstevel@tonic-gate */ 973*7c478bd9Sstevel@tonic-gate *pbm_p->pbm_ctrl_reg &= 974*7c478bd9Sstevel@tonic-gate ~(SCHIZO_PCI_CTRL_ERR_INT_EN | SCHIZO_PCI_CTRL_SBH_INT_EN | 975*7c478bd9Sstevel@tonic-gate SCHIZO_PCI_CTRL_MMU_INT_EN); 976*7c478bd9Sstevel@tonic-gate 977*7c478bd9Sstevel@tonic-gate /* 978*7c478bd9Sstevel@tonic-gate * Disable error interrupts via the interrupt mapping register. 979*7c478bd9Sstevel@tonic-gate */ 980*7c478bd9Sstevel@tonic-gate ib_intr_disable(ib_p, pci_p->pci_inos[CBNINTR_PBM], IB_INTR_NOWAIT); 981*7c478bd9Sstevel@tonic-gate return (BF_NONE); 982*7c478bd9Sstevel@tonic-gate } 983*7c478bd9Sstevel@tonic-gate 984*7c478bd9Sstevel@tonic-gate /* 985*7c478bd9Sstevel@tonic-gate * Layout of the dvma context bucket bitmap entry: 986*7c478bd9Sstevel@tonic-gate * 987*7c478bd9Sstevel@tonic-gate * 63 - 56 55 - 0 988*7c478bd9Sstevel@tonic-gate * 8-bit lock 56-bit, each represent one context 989*7c478bd9Sstevel@tonic-gate * DCB_LOCK_BITS DCB_BMAP_BITS 990*7c478bd9Sstevel@tonic-gate */ 991*7c478bd9Sstevel@tonic-gate #define DCB_LOCK_BITS 8 992*7c478bd9Sstevel@tonic-gate #define DCB_BMAP_BITS (64 - DCB_LOCK_BITS) 993*7c478bd9Sstevel@tonic-gate 994*7c478bd9Sstevel@tonic-gate dvma_context_t 995*7c478bd9Sstevel@tonic-gate pci_iommu_get_dvma_context(iommu_t *iommu_p, dvma_addr_t dvma_pg_index) 996*7c478bd9Sstevel@tonic-gate { 997*7c478bd9Sstevel@tonic-gate dvma_context_t ctx; 998*7c478bd9Sstevel@tonic-gate int i = (dvma_pg_index >> 6) & 0x1f; /* 5 bit index within bucket */ 999*7c478bd9Sstevel@tonic-gate uint64_t ctx_mask, test = 1ull << i; 1000*7c478bd9Sstevel@tonic-gate uint32_t bucket_no = dvma_pg_index & 0x3f; 1001*7c478bd9Sstevel@tonic-gate uint64_t *bucket_ptr = iommu_p->iommu_ctx_bitmap + bucket_no; 1002*7c478bd9Sstevel@tonic-gate 1003*7c478bd9Sstevel@tonic-gate uint32_t spl = ddi_enter_critical(); /* block interrupts */ 1004*7c478bd9Sstevel@tonic-gate if (ldstub((uint8_t *)bucket_ptr)) { /* try lock */ 1005*7c478bd9Sstevel@tonic-gate ddi_exit_critical(spl); /* unblock interrupt */ 1006*7c478bd9Sstevel@tonic-gate pci_iommu_ctx_lock_failure++; 1007*7c478bd9Sstevel@tonic-gate return (0); 1008*7c478bd9Sstevel@tonic-gate } 1009*7c478bd9Sstevel@tonic-gate 1010*7c478bd9Sstevel@tonic-gate /* clear lock bits */ 1011*7c478bd9Sstevel@tonic-gate ctx_mask = (*bucket_ptr << DCB_LOCK_BITS) >> DCB_LOCK_BITS; 1012*7c478bd9Sstevel@tonic-gate ASSERT(*bucket_ptr >> DCB_BMAP_BITS == 0xff); 1013*7c478bd9Sstevel@tonic-gate ASSERT(ctx_mask >> DCB_BMAP_BITS == 0); 1014*7c478bd9Sstevel@tonic-gate 1015*7c478bd9Sstevel@tonic-gate if (ctx_mask & test) /* quick check i bit */ 1016*7c478bd9Sstevel@tonic-gate for (i = 0, test = 1ull; test & ctx_mask; test <<= 1, i++); 1017*7c478bd9Sstevel@tonic-gate if (i < DCB_BMAP_BITS) 1018*7c478bd9Sstevel@tonic-gate ctx_mask |= test; 1019*7c478bd9Sstevel@tonic-gate *bucket_ptr = ctx_mask; /* unlock */ 1020*7c478bd9Sstevel@tonic-gate ddi_exit_critical(spl); /* unblock interrupts */ 1021*7c478bd9Sstevel@tonic-gate 1022*7c478bd9Sstevel@tonic-gate ctx = i < DCB_BMAP_BITS ? (bucket_no << 6) | i : 0; 1023*7c478bd9Sstevel@tonic-gate DEBUG3(DBG_DMA_MAP, iommu_p->iommu_pci_p->pci_dip, 1024*7c478bd9Sstevel@tonic-gate "get_dvma_context: ctx_mask=0x%x.%x ctx=0x%x\n", 1025*7c478bd9Sstevel@tonic-gate (uint32_t)(ctx_mask >> 32), (uint32_t)ctx_mask, ctx); 1026*7c478bd9Sstevel@tonic-gate return (ctx); 1027*7c478bd9Sstevel@tonic-gate } 1028*7c478bd9Sstevel@tonic-gate 1029*7c478bd9Sstevel@tonic-gate void 1030*7c478bd9Sstevel@tonic-gate pci_iommu_free_dvma_context(iommu_t *iommu_p, dvma_context_t ctx) 1031*7c478bd9Sstevel@tonic-gate { 1032*7c478bd9Sstevel@tonic-gate uint64_t ctx_mask; 1033*7c478bd9Sstevel@tonic-gate uint32_t spl, bucket_no = ctx >> 6; 1034*7c478bd9Sstevel@tonic-gate int bit_no = ctx & 0x3f; 1035*7c478bd9Sstevel@tonic-gate uint64_t *bucket_ptr = iommu_p->iommu_ctx_bitmap + bucket_no; 1036*7c478bd9Sstevel@tonic-gate 1037*7c478bd9Sstevel@tonic-gate DEBUG1(DBG_DMA_MAP, iommu_p->iommu_pci_p->pci_dip, 1038*7c478bd9Sstevel@tonic-gate "free_dvma_context: ctx=0x%x\n", ctx); 1039*7c478bd9Sstevel@tonic-gate 1040*7c478bd9Sstevel@tonic-gate spl = ddi_enter_critical(); /* block interrupts */ 1041*7c478bd9Sstevel@tonic-gate while (ldstub((uint8_t *)bucket_ptr)); /* spin lock */ 1042*7c478bd9Sstevel@tonic-gate ctx_mask = (*bucket_ptr << DCB_LOCK_BITS) >> DCB_LOCK_BITS; 1043*7c478bd9Sstevel@tonic-gate /* clear lock bits */ 1044*7c478bd9Sstevel@tonic-gate ASSERT(ctx_mask & (1ull << bit_no)); 1045*7c478bd9Sstevel@tonic-gate *bucket_ptr = ctx_mask ^ (1ull << bit_no); /* clear & unlock */ 1046*7c478bd9Sstevel@tonic-gate ddi_exit_critical(spl); /* unblock interrupt */ 1047*7c478bd9Sstevel@tonic-gate } 1048*7c478bd9Sstevel@tonic-gate 1049*7c478bd9Sstevel@tonic-gate int 1050*7c478bd9Sstevel@tonic-gate pci_sc_ctx_inv(dev_info_t *dip, sc_t *sc_p, ddi_dma_impl_t *mp) 1051*7c478bd9Sstevel@tonic-gate { 1052*7c478bd9Sstevel@tonic-gate dvma_context_t ctx = MP2CTX(mp); 1053*7c478bd9Sstevel@tonic-gate volatile uint64_t *reg_addr = sc_p->sc_ctx_match_reg + ctx; 1054*7c478bd9Sstevel@tonic-gate uint64_t matchreg; 1055*7c478bd9Sstevel@tonic-gate 1056*7c478bd9Sstevel@tonic-gate if (!*reg_addr) { 1057*7c478bd9Sstevel@tonic-gate DEBUG1(DBG_SC, dip, "ctx=%x no match\n", ctx); 1058*7c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 1059*7c478bd9Sstevel@tonic-gate } 1060*7c478bd9Sstevel@tonic-gate 1061*7c478bd9Sstevel@tonic-gate *sc_p->sc_ctx_invl_reg = ctx; /* 1st flush write */ 1062*7c478bd9Sstevel@tonic-gate matchreg = *reg_addr; /* re-fetch after 1st flush */ 1063*7c478bd9Sstevel@tonic-gate if (!matchreg) 1064*7c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 1065*7c478bd9Sstevel@tonic-gate 1066*7c478bd9Sstevel@tonic-gate matchreg = (matchreg << SC_ENT_SHIFT) >> SC_ENT_SHIFT; /* low 16-bit */ 1067*7c478bd9Sstevel@tonic-gate do { 1068*7c478bd9Sstevel@tonic-gate if (matchreg & 1) 1069*7c478bd9Sstevel@tonic-gate *sc_p->sc_ctx_invl_reg = ctx; 1070*7c478bd9Sstevel@tonic-gate matchreg >>= 1; 1071*7c478bd9Sstevel@tonic-gate } while (matchreg); 1072*7c478bd9Sstevel@tonic-gate 1073*7c478bd9Sstevel@tonic-gate if (pci_ctx_no_compat || !*reg_addr) /* compat: active ctx flush */ 1074*7c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 1075*7c478bd9Sstevel@tonic-gate 1076*7c478bd9Sstevel@tonic-gate pci_ctx_unsuccess_count++; 1077*7c478bd9Sstevel@tonic-gate if (pci_ctx_flush_warn) 1078*7c478bd9Sstevel@tonic-gate cmn_err(pci_ctx_flush_warn, "%s%d: ctx flush unsuccessful\n", 1079*7c478bd9Sstevel@tonic-gate NAMEINST(dip)); 1080*7c478bd9Sstevel@tonic-gate return (DDI_FAILURE); 1081*7c478bd9Sstevel@tonic-gate } 1082*7c478bd9Sstevel@tonic-gate 1083*7c478bd9Sstevel@tonic-gate void 1084*7c478bd9Sstevel@tonic-gate pci_cb_setup(pci_t *pci_p) 1085*7c478bd9Sstevel@tonic-gate { 1086*7c478bd9Sstevel@tonic-gate dev_info_t *dip = pci_p->pci_dip; 1087*7c478bd9Sstevel@tonic-gate cb_t *cb_p = pci_p->pci_cb_p; 1088*7c478bd9Sstevel@tonic-gate uint64_t pa; 1089*7c478bd9Sstevel@tonic-gate uint32_t chip_id = PCI_CHIP_ID(pci_p); 1090*7c478bd9Sstevel@tonic-gate DEBUG1(DBG_ATTACH, dip, "cb_create: chip id %d\n", chip_id); 1091*7c478bd9Sstevel@tonic-gate 1092*7c478bd9Sstevel@tonic-gate if (CHIP_TYPE(pci_p) == PCI_CHIP_TOMATILLO) { 1093*7c478bd9Sstevel@tonic-gate if ((!tm_mtlb_gc_manual) && 1094*7c478bd9Sstevel@tonic-gate (PCI_CHIP_ID(pci_p) <= TOMATILLO_VER_24)) 1095*7c478bd9Sstevel@tonic-gate tm_mtlb_gc = 1; 1096*7c478bd9Sstevel@tonic-gate 1097*7c478bd9Sstevel@tonic-gate if (PCI_CHIP_ID(pci_p) <= TOMATILLO_VER_23) { 1098*7c478bd9Sstevel@tonic-gate extern int ignore_invalid_vecintr; 1099*7c478bd9Sstevel@tonic-gate ignore_invalid_vecintr = 1; 1100*7c478bd9Sstevel@tonic-gate tomatillo_store_store_wrka = 1; 1101*7c478bd9Sstevel@tonic-gate tomatillo_disallow_bypass = 1; 1102*7c478bd9Sstevel@tonic-gate if (pci_spurintr_msgs == PCI_SPURINTR_MSG_DEFAULT) 1103*7c478bd9Sstevel@tonic-gate pci_spurintr_msgs = 0; 1104*7c478bd9Sstevel@tonic-gate } 1105*7c478bd9Sstevel@tonic-gate } 1106*7c478bd9Sstevel@tonic-gate 1107*7c478bd9Sstevel@tonic-gate if (chip_id == TOMATILLO_VER_20 || chip_id == TOMATILLO_VER_21) 1108*7c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "Unsupported Tomatillo rev (%x)", chip_id); 1109*7c478bd9Sstevel@tonic-gate 1110*7c478bd9Sstevel@tonic-gate if (chip_id < SCHIZO_VER_23) 1111*7c478bd9Sstevel@tonic-gate pci_ctx_no_active_flush = 1; 1112*7c478bd9Sstevel@tonic-gate 1113*7c478bd9Sstevel@tonic-gate cb_p->cb_node_id = PCI_ID_TO_NODEID(pci_p->pci_id); 1114*7c478bd9Sstevel@tonic-gate cb_p->cb_ign = PCI_ID_TO_IGN(pci_p->pci_id); 1115*7c478bd9Sstevel@tonic-gate 1116*7c478bd9Sstevel@tonic-gate /* 1117*7c478bd9Sstevel@tonic-gate * schizo control status reg bank is on the 2nd "reg" property entry 1118*7c478bd9Sstevel@tonic-gate * interrupt mapping/clear/state regs are on the 1st "reg" entry. 1119*7c478bd9Sstevel@tonic-gate * 1120*7c478bd9Sstevel@tonic-gate * ALL internal interrupts except pbm interrupts are shared by both 1121*7c478bd9Sstevel@tonic-gate * sides, 1st-side-attached is used as *the* owner. 1122*7c478bd9Sstevel@tonic-gate */ 1123*7c478bd9Sstevel@tonic-gate pa = (uint64_t)hat_getpfnum(kas.a_hat, pci_p->pci_address[1]); 1124*7c478bd9Sstevel@tonic-gate cb_p->cb_base_pa = pa << MMU_PAGESHIFT; 1125*7c478bd9Sstevel@tonic-gate 1126*7c478bd9Sstevel@tonic-gate pa = pci_p->pci_address[3] ? 1127*7c478bd9Sstevel@tonic-gate (uint64_t)hat_getpfnum(kas.a_hat, pci_p->pci_address[3]) : 0; 1128*7c478bd9Sstevel@tonic-gate cb_p->cb_icbase_pa = (pa == PFN_INVALID) ? 0 : pa << MMU_PAGESHIFT; 1129*7c478bd9Sstevel@tonic-gate 1130*7c478bd9Sstevel@tonic-gate pa = (uint64_t)hat_getpfnum(kas.a_hat, pci_p->pci_address[0]) 1131*7c478bd9Sstevel@tonic-gate << MMU_PAGESHIFT; 1132*7c478bd9Sstevel@tonic-gate cb_p->cb_map_pa = pa + SCHIZO_IB_INTR_MAP_REG_OFFSET; 1133*7c478bd9Sstevel@tonic-gate cb_p->cb_clr_pa = pa + SCHIZO_IB_CLEAR_INTR_REG_OFFSET; 1134*7c478bd9Sstevel@tonic-gate cb_p->cb_obsta_pa = pa + COMMON_IB_OBIO_INTR_STATE_DIAG_REG; 1135*7c478bd9Sstevel@tonic-gate } 1136*7c478bd9Sstevel@tonic-gate 1137*7c478bd9Sstevel@tonic-gate void 1138*7c478bd9Sstevel@tonic-gate pci_ecc_setup(ecc_t *ecc_p) 1139*7c478bd9Sstevel@tonic-gate { 1140*7c478bd9Sstevel@tonic-gate ecc_p->ecc_ue.ecc_errpndg_mask = SCHIZO_ECC_UE_AFSR_ERRPNDG; 1141*7c478bd9Sstevel@tonic-gate ecc_p->ecc_ue.ecc_offset_mask = SCHIZO_ECC_UE_AFSR_QW_OFFSET; 1142*7c478bd9Sstevel@tonic-gate ecc_p->ecc_ue.ecc_offset_shift = SCHIZO_ECC_UE_AFSR_QW_OFFSET_SHIFT; 1143*7c478bd9Sstevel@tonic-gate ecc_p->ecc_ue.ecc_size_log2 = 4; 1144*7c478bd9Sstevel@tonic-gate 1145*7c478bd9Sstevel@tonic-gate ecc_p->ecc_ce.ecc_errpndg_mask = SCHIZO_ECC_CE_AFSR_ERRPNDG; 1146*7c478bd9Sstevel@tonic-gate ecc_p->ecc_ce.ecc_offset_mask = SCHIZO_ECC_CE_AFSR_QW_OFFSET; 1147*7c478bd9Sstevel@tonic-gate ecc_p->ecc_ce.ecc_offset_shift = SCHIZO_ECC_CE_AFSR_QW_OFFSET_SHIFT; 1148*7c478bd9Sstevel@tonic-gate ecc_p->ecc_ce.ecc_size_log2 = 4; 1149*7c478bd9Sstevel@tonic-gate } 1150*7c478bd9Sstevel@tonic-gate 1151*7c478bd9Sstevel@tonic-gate ushort_t 1152*7c478bd9Sstevel@tonic-gate pci_ecc_get_synd(uint64_t afsr) 1153*7c478bd9Sstevel@tonic-gate { 1154*7c478bd9Sstevel@tonic-gate return ((ushort_t)((afsr & SCHIZO_ECC_CE_AFSR_SYND) >> 1155*7c478bd9Sstevel@tonic-gate SCHIZO_ECC_CE_AFSR_SYND_SHIFT)); 1156*7c478bd9Sstevel@tonic-gate } 1157*7c478bd9Sstevel@tonic-gate 1158*7c478bd9Sstevel@tonic-gate /* 1159*7c478bd9Sstevel@tonic-gate * overwrite dvma end address (only on virtual-dma systems) 1160*7c478bd9Sstevel@tonic-gate * initialize tsb size 1161*7c478bd9Sstevel@tonic-gate * reset context bits 1162*7c478bd9Sstevel@tonic-gate * return: IOMMU CSR bank base address (VA) 1163*7c478bd9Sstevel@tonic-gate */ 1164*7c478bd9Sstevel@tonic-gate 1165*7c478bd9Sstevel@tonic-gate uintptr_t 1166*7c478bd9Sstevel@tonic-gate pci_iommu_setup(iommu_t *iommu_p) 1167*7c478bd9Sstevel@tonic-gate { 1168*7c478bd9Sstevel@tonic-gate pci_dvma_range_prop_t *dvma_prop; 1169*7c478bd9Sstevel@tonic-gate int dvma_prop_len; 1170*7c478bd9Sstevel@tonic-gate 1171*7c478bd9Sstevel@tonic-gate uintptr_t a; 1172*7c478bd9Sstevel@tonic-gate pci_t *pci_p = iommu_p->iommu_pci_p; 1173*7c478bd9Sstevel@tonic-gate dev_info_t *dip = pci_p->pci_dip; 1174*7c478bd9Sstevel@tonic-gate uint_t tsb_size = iommu_tsb_cookie_to_size(pci_p->pci_tsb_cookie); 1175*7c478bd9Sstevel@tonic-gate 1176*7c478bd9Sstevel@tonic-gate /* 1177*7c478bd9Sstevel@tonic-gate * Initializations for Tomatillo's micro TLB bug. errata #82 1178*7c478bd9Sstevel@tonic-gate */ 1179*7c478bd9Sstevel@tonic-gate if (tm_mtlb_gc) { 1180*7c478bd9Sstevel@tonic-gate iommu_p->iommu_mtlb_nreq = 0; 1181*7c478bd9Sstevel@tonic-gate iommu_p->iommu_mtlb_npgs = 0; 1182*7c478bd9Sstevel@tonic-gate iommu_p->iommu_mtlb_maxpgs = tm_mtlb_maxpgs; 1183*7c478bd9Sstevel@tonic-gate iommu_p->iommu_mtlb_req_p = (dvma_unbind_req_t *) 1184*7c478bd9Sstevel@tonic-gate kmem_zalloc(sizeof (dvma_unbind_req_t) * 1185*7c478bd9Sstevel@tonic-gate (tm_mtlb_maxpgs + 1), KM_SLEEP); 1186*7c478bd9Sstevel@tonic-gate mutex_init(&iommu_p->iommu_mtlb_lock, NULL, MUTEX_DRIVER, NULL); 1187*7c478bd9Sstevel@tonic-gate } 1188*7c478bd9Sstevel@tonic-gate 1189*7c478bd9Sstevel@tonic-gate if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1190*7c478bd9Sstevel@tonic-gate "virtual-dma", (caddr_t)&dvma_prop, &dvma_prop_len) != 1191*7c478bd9Sstevel@tonic-gate DDI_PROP_SUCCESS) 1192*7c478bd9Sstevel@tonic-gate goto tsb_done; 1193*7c478bd9Sstevel@tonic-gate 1194*7c478bd9Sstevel@tonic-gate if (dvma_prop_len != sizeof (pci_dvma_range_prop_t)) { 1195*7c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "%s%d: invalid virtual-dma property", 1196*7c478bd9Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip)); 1197*7c478bd9Sstevel@tonic-gate goto tsb_end; 1198*7c478bd9Sstevel@tonic-gate } 1199*7c478bd9Sstevel@tonic-gate iommu_p->iommu_dvma_end = dvma_prop->dvma_base + 1200*7c478bd9Sstevel@tonic-gate (dvma_prop->dvma_len - 1); 1201*7c478bd9Sstevel@tonic-gate tsb_end: 1202*7c478bd9Sstevel@tonic-gate kmem_free(dvma_prop, dvma_prop_len); 1203*7c478bd9Sstevel@tonic-gate tsb_done: 1204*7c478bd9Sstevel@tonic-gate iommu_p->iommu_tsb_size = iommu_tsb_size_encode(tsb_size); 1205*7c478bd9Sstevel@tonic-gate iommu_p->iommu_ctx_bitmap = 1206*7c478bd9Sstevel@tonic-gate kmem_zalloc(IOMMU_CTX_BITMAP_SIZE, KM_SLEEP); 1207*7c478bd9Sstevel@tonic-gate *iommu_p->iommu_ctx_bitmap = 1ull; /* reserve context 0 */ 1208*7c478bd9Sstevel@tonic-gate 1209*7c478bd9Sstevel@tonic-gate /* 1210*7c478bd9Sstevel@tonic-gate * Determine the virtual address of the register block 1211*7c478bd9Sstevel@tonic-gate * containing the iommu control registers and determine 1212*7c478bd9Sstevel@tonic-gate * the virtual address of schizo specific iommu registers. 1213*7c478bd9Sstevel@tonic-gate */ 1214*7c478bd9Sstevel@tonic-gate a = (uintptr_t)pci_p->pci_address[0]; 1215*7c478bd9Sstevel@tonic-gate iommu_p->iommu_flush_ctx_reg = 1216*7c478bd9Sstevel@tonic-gate (uint64_t *)(a + SCHIZO_IOMMU_FLUSH_CTX_REG_OFFSET); 1217*7c478bd9Sstevel@tonic-gate if (CHIP_TYPE(pci_p) == PCI_CHIP_TOMATILLO) 1218*7c478bd9Sstevel@tonic-gate iommu_p->iommu_tfar_reg = 1219*7c478bd9Sstevel@tonic-gate (uint64_t *)(a + TOMATILLO_IOMMU_ERR_TFAR_OFFSET); 1220*7c478bd9Sstevel@tonic-gate return (a); /* PCICSRBase */ 1221*7c478bd9Sstevel@tonic-gate } 1222*7c478bd9Sstevel@tonic-gate 1223*7c478bd9Sstevel@tonic-gate void 1224*7c478bd9Sstevel@tonic-gate pci_iommu_teardown(iommu_t *iommu_p) 1225*7c478bd9Sstevel@tonic-gate { 1226*7c478bd9Sstevel@tonic-gate if (pci_use_contexts) 1227*7c478bd9Sstevel@tonic-gate iommu_ctx_free(iommu_p); 1228*7c478bd9Sstevel@tonic-gate if (iommu_p->iommu_mtlb_req_p) { 1229*7c478bd9Sstevel@tonic-gate kmem_free(iommu_p->iommu_mtlb_req_p, 1230*7c478bd9Sstevel@tonic-gate sizeof (dvma_unbind_req_t) * (tm_mtlb_maxpgs + 1)); 1231*7c478bd9Sstevel@tonic-gate mutex_destroy(&iommu_p->iommu_mtlb_lock); 1232*7c478bd9Sstevel@tonic-gate iommu_p->iommu_mtlb_req_p = NULL; 1233*7c478bd9Sstevel@tonic-gate iommu_p->iommu_mtlb_nreq = 0; 1234*7c478bd9Sstevel@tonic-gate iommu_p->iommu_mtlb_npgs = iommu_p->iommu_mtlb_maxpgs = 0; 1235*7c478bd9Sstevel@tonic-gate } 1236*7c478bd9Sstevel@tonic-gate } 1237*7c478bd9Sstevel@tonic-gate 1238*7c478bd9Sstevel@tonic-gate uintptr_t 1239*7c478bd9Sstevel@tonic-gate get_pbm_reg_base(pci_t *pci_p) 1240*7c478bd9Sstevel@tonic-gate { 1241*7c478bd9Sstevel@tonic-gate return ((uintptr_t) 1242*7c478bd9Sstevel@tonic-gate (pci_p->pci_address[0] + SCHIZO_PCI_CTRL_REG_OFFSET)); 1243*7c478bd9Sstevel@tonic-gate } 1244*7c478bd9Sstevel@tonic-gate 1245*7c478bd9Sstevel@tonic-gate /* ARGSUSED */ 1246*7c478bd9Sstevel@tonic-gate static boolean_t 1247*7c478bd9Sstevel@tonic-gate pci_pbm_panic_callb(void *arg, int code) 1248*7c478bd9Sstevel@tonic-gate { 1249*7c478bd9Sstevel@tonic-gate pbm_t *pbm_p = (pbm_t *)arg; 1250*7c478bd9Sstevel@tonic-gate volatile uint64_t *ctrl_reg_p; 1251*7c478bd9Sstevel@tonic-gate 1252*7c478bd9Sstevel@tonic-gate if (pbm_p->pbm_quiesce_count > 0) { 1253*7c478bd9Sstevel@tonic-gate ctrl_reg_p = pbm_p->pbm_ctrl_reg; 1254*7c478bd9Sstevel@tonic-gate *ctrl_reg_p = pbm_p->pbm_saved_ctrl_reg; 1255*7c478bd9Sstevel@tonic-gate } 1256*7c478bd9Sstevel@tonic-gate 1257*7c478bd9Sstevel@tonic-gate return (B_TRUE); 1258*7c478bd9Sstevel@tonic-gate } 1259*7c478bd9Sstevel@tonic-gate 1260*7c478bd9Sstevel@tonic-gate static boolean_t 1261*7c478bd9Sstevel@tonic-gate pci_pbm_debug_callb(void *arg, int code) 1262*7c478bd9Sstevel@tonic-gate { 1263*7c478bd9Sstevel@tonic-gate pbm_t *pbm_p = (pbm_t *)arg; 1264*7c478bd9Sstevel@tonic-gate volatile uint64_t *ctrl_reg_p; 1265*7c478bd9Sstevel@tonic-gate uint64_t ctrl_reg; 1266*7c478bd9Sstevel@tonic-gate 1267*7c478bd9Sstevel@tonic-gate if (pbm_p->pbm_quiesce_count > 0) { 1268*7c478bd9Sstevel@tonic-gate ctrl_reg_p = pbm_p->pbm_ctrl_reg; 1269*7c478bd9Sstevel@tonic-gate if (code == 0) { 1270*7c478bd9Sstevel@tonic-gate *ctrl_reg_p = pbm_p->pbm_saved_ctrl_reg; 1271*7c478bd9Sstevel@tonic-gate } else { 1272*7c478bd9Sstevel@tonic-gate ctrl_reg = pbm_p->pbm_saved_ctrl_reg; 1273*7c478bd9Sstevel@tonic-gate ctrl_reg &= ~(SCHIZO_PCI_CTRL_ARB_EN_MASK | 1274*7c478bd9Sstevel@tonic-gate SCHIZO_PCI_CTRL_ARB_PARK); 1275*7c478bd9Sstevel@tonic-gate *ctrl_reg_p = ctrl_reg; 1276*7c478bd9Sstevel@tonic-gate } 1277*7c478bd9Sstevel@tonic-gate } 1278*7c478bd9Sstevel@tonic-gate 1279*7c478bd9Sstevel@tonic-gate return (B_TRUE); 1280*7c478bd9Sstevel@tonic-gate } 1281*7c478bd9Sstevel@tonic-gate 1282*7c478bd9Sstevel@tonic-gate void 1283*7c478bd9Sstevel@tonic-gate pci_pbm_setup(pbm_t *pbm_p) 1284*7c478bd9Sstevel@tonic-gate { 1285*7c478bd9Sstevel@tonic-gate pci_t *pci_p = pbm_p->pbm_pci_p; 1286*7c478bd9Sstevel@tonic-gate caddr_t a = pci_p->pci_address[0]; /* PBM block base VA */ 1287*7c478bd9Sstevel@tonic-gate uint64_t pa = va_to_pa(a); 1288*7c478bd9Sstevel@tonic-gate extern int segkmem_reloc; 1289*7c478bd9Sstevel@tonic-gate 1290*7c478bd9Sstevel@tonic-gate mutex_init(&pbm_p->pbm_sync_mutex, NULL, MUTEX_DRIVER, 1291*7c478bd9Sstevel@tonic-gate (void *)ipltospl(XCALL_PIL)); 1292*7c478bd9Sstevel@tonic-gate 1293*7c478bd9Sstevel@tonic-gate pbm_p->pbm_config_header = (config_header_t *)pci_p->pci_address[2]; 1294*7c478bd9Sstevel@tonic-gate pbm_p->pbm_ctrl_reg = (uint64_t *)(a + SCHIZO_PCI_CTRL_REG_OFFSET); 1295*7c478bd9Sstevel@tonic-gate pbm_p->pbm_diag_reg = (uint64_t *)(a + SCHIZO_PCI_DIAG_REG_OFFSET); 1296*7c478bd9Sstevel@tonic-gate pbm_p->pbm_async_flt_status_reg = 1297*7c478bd9Sstevel@tonic-gate (uint64_t *)(a + SCHIZO_PCI_ASYNC_FLT_STATUS_REG_OFFSET); 1298*7c478bd9Sstevel@tonic-gate pbm_p->pbm_async_flt_addr_reg = 1299*7c478bd9Sstevel@tonic-gate (uint64_t *)(a + SCHIZO_PCI_ASYNC_FLT_ADDR_REG_OFFSET); 1300*7c478bd9Sstevel@tonic-gate pbm_p->pbm_estar_reg = (uint64_t *)(a + SCHIZO_PCI_ESTAR_REG_OFFSET); 1301*7c478bd9Sstevel@tonic-gate pbm_p->pbm_pcix_err_stat_reg = (uint64_t *)(a + 1302*7c478bd9Sstevel@tonic-gate XMITS_PCI_X_ERROR_STATUS_REG_OFFSET); 1303*7c478bd9Sstevel@tonic-gate pbm_p->pbm_pci_ped_ctrl = (uint64_t *)(a + 1304*7c478bd9Sstevel@tonic-gate XMITS_PARITY_DETECT_REG_OFFSET); 1305*7c478bd9Sstevel@tonic-gate 1306*7c478bd9Sstevel@tonic-gate /* 1307*7c478bd9Sstevel@tonic-gate * Create a property to indicate that this node supports DVMA 1308*7c478bd9Sstevel@tonic-gate * page relocation. 1309*7c478bd9Sstevel@tonic-gate */ 1310*7c478bd9Sstevel@tonic-gate if (CHIP_TYPE(pci_p) != PCI_CHIP_TOMATILLO && segkmem_reloc != 0) { 1311*7c478bd9Sstevel@tonic-gate pci_dvma_remap_enabled = 1; 1312*7c478bd9Sstevel@tonic-gate (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, 1313*7c478bd9Sstevel@tonic-gate pci_p->pci_dip, "dvma-remap-supported"); 1314*7c478bd9Sstevel@tonic-gate } 1315*7c478bd9Sstevel@tonic-gate 1316*7c478bd9Sstevel@tonic-gate /* 1317*7c478bd9Sstevel@tonic-gate * Register a panic callback so we can unquiesce this bus 1318*7c478bd9Sstevel@tonic-gate * if it has been placed in the quiesced state. 1319*7c478bd9Sstevel@tonic-gate */ 1320*7c478bd9Sstevel@tonic-gate pbm_p->pbm_panic_cb_id = callb_add(pci_pbm_panic_callb, 1321*7c478bd9Sstevel@tonic-gate (void *)pbm_p, CB_CL_PANIC, "pci_panic"); 1322*7c478bd9Sstevel@tonic-gate pbm_p->pbm_debug_cb_id = callb_add(pci_pbm_panic_callb, 1323*7c478bd9Sstevel@tonic-gate (void *)pbm_p, CB_CL_ENTER_DEBUGGER, "pci_debug_enter"); 1324*7c478bd9Sstevel@tonic-gate 1325*7c478bd9Sstevel@tonic-gate if (CHIP_TYPE(pci_p) != PCI_CHIP_SCHIZO) 1326*7c478bd9Sstevel@tonic-gate goto non_schizo; 1327*7c478bd9Sstevel@tonic-gate 1328*7c478bd9Sstevel@tonic-gate if (PCI_CHIP_ID(pci_p) >= SCHIZO_VER_23) { 1329*7c478bd9Sstevel@tonic-gate 1330*7c478bd9Sstevel@tonic-gate pbm_p->pbm_sync_reg_pa = pa + SCHIZO_PBM_DMA_SYNC_REG_OFFSET; 1331*7c478bd9Sstevel@tonic-gate 1332*7c478bd9Sstevel@tonic-gate /* 1333*7c478bd9Sstevel@tonic-gate * This is a software workaround to fix schizo hardware bug. 1334*7c478bd9Sstevel@tonic-gate * Create a boolean property and its existence means consistent 1335*7c478bd9Sstevel@tonic-gate * dma sync should not be done while in prom. The usb polled 1336*7c478bd9Sstevel@tonic-gate * code (OHCI,EHCI) will check for this property and will not 1337*7c478bd9Sstevel@tonic-gate * do dma sync if this property exist. 1338*7c478bd9Sstevel@tonic-gate */ 1339*7c478bd9Sstevel@tonic-gate (void) ndi_prop_create_boolean(DDI_DEV_T_NONE, 1340*7c478bd9Sstevel@tonic-gate pci_p->pci_dip, "no-prom-cdma-sync"); 1341*7c478bd9Sstevel@tonic-gate } 1342*7c478bd9Sstevel@tonic-gate return; 1343*7c478bd9Sstevel@tonic-gate non_schizo: 1344*7c478bd9Sstevel@tonic-gate if (CHIP_TYPE(pci_p) == PCI_CHIP_TOMATILLO) { 1345*7c478bd9Sstevel@tonic-gate pci_dvma_sync_before_unmap = 1; 1346*7c478bd9Sstevel@tonic-gate pa = pci_p->pci_cb_p->cb_icbase_pa; 1347*7c478bd9Sstevel@tonic-gate } 1348*7c478bd9Sstevel@tonic-gate pbm_p->pbm_sync_reg_pa = pa + PBM_DMA_SYNC_PEND_REG_OFFSET; 1349*7c478bd9Sstevel@tonic-gate } 1350*7c478bd9Sstevel@tonic-gate 1351*7c478bd9Sstevel@tonic-gate void 1352*7c478bd9Sstevel@tonic-gate pci_pbm_teardown(pbm_t *pbm_p) 1353*7c478bd9Sstevel@tonic-gate { 1354*7c478bd9Sstevel@tonic-gate (void) callb_delete(pbm_p->pbm_panic_cb_id); 1355*7c478bd9Sstevel@tonic-gate (void) callb_delete(pbm_p->pbm_debug_cb_id); 1356*7c478bd9Sstevel@tonic-gate } 1357*7c478bd9Sstevel@tonic-gate 1358*7c478bd9Sstevel@tonic-gate uintptr_t 1359*7c478bd9Sstevel@tonic-gate pci_ib_setup(ib_t *ib_p) 1360*7c478bd9Sstevel@tonic-gate { 1361*7c478bd9Sstevel@tonic-gate /* 1362*7c478bd9Sstevel@tonic-gate * Determine virtual addresses of bridge specific registers, 1363*7c478bd9Sstevel@tonic-gate */ 1364*7c478bd9Sstevel@tonic-gate pci_t *pci_p = ib_p->ib_pci_p; 1365*7c478bd9Sstevel@tonic-gate uintptr_t a = (uintptr_t)pci_p->pci_address[0]; 1366*7c478bd9Sstevel@tonic-gate 1367*7c478bd9Sstevel@tonic-gate ib_p->ib_ign = PCI_ID_TO_IGN(pci_p->pci_id); 1368*7c478bd9Sstevel@tonic-gate ib_p->ib_max_ino = SCHIZO_MAX_INO; 1369*7c478bd9Sstevel@tonic-gate ib_p->ib_slot_intr_map_regs = a + SCHIZO_IB_SLOT_INTR_MAP_REG_OFFSET; 1370*7c478bd9Sstevel@tonic-gate ib_p->ib_intr_map_regs = a + SCHIZO_IB_INTR_MAP_REG_OFFSET; 1371*7c478bd9Sstevel@tonic-gate ib_p->ib_slot_clear_intr_regs = 1372*7c478bd9Sstevel@tonic-gate a + SCHIZO_IB_CLEAR_INTR_REG_OFFSET; 1373*7c478bd9Sstevel@tonic-gate return (a); 1374*7c478bd9Sstevel@tonic-gate } 1375*7c478bd9Sstevel@tonic-gate 1376*7c478bd9Sstevel@tonic-gate void 1377*7c478bd9Sstevel@tonic-gate pci_sc_setup(sc_t *sc_p) 1378*7c478bd9Sstevel@tonic-gate { 1379*7c478bd9Sstevel@tonic-gate pci_t *pci_p = sc_p->sc_pci_p; 1380*7c478bd9Sstevel@tonic-gate uintptr_t a; 1381*7c478bd9Sstevel@tonic-gate 1382*7c478bd9Sstevel@tonic-gate /* 1383*7c478bd9Sstevel@tonic-gate * Determine the virtual addresses of the stream cache 1384*7c478bd9Sstevel@tonic-gate * control/status and flush registers. 1385*7c478bd9Sstevel@tonic-gate */ 1386*7c478bd9Sstevel@tonic-gate a = (uintptr_t)pci_p->pci_address[0]; /* PCICSRBase */ 1387*7c478bd9Sstevel@tonic-gate sc_p->sc_ctrl_reg = (uint64_t *)(a + SCHIZO_SC_CTRL_REG_OFFSET); 1388*7c478bd9Sstevel@tonic-gate sc_p->sc_invl_reg = (uint64_t *)(a + SCHIZO_SC_INVL_REG_OFFSET); 1389*7c478bd9Sstevel@tonic-gate sc_p->sc_sync_reg = (uint64_t *)(a + SCHIZO_SC_SYNC_REG_OFFSET); 1390*7c478bd9Sstevel@tonic-gate sc_p->sc_ctx_invl_reg = (uint64_t *)(a + SCHIZO_SC_CTX_INVL_REG_OFFSET); 1391*7c478bd9Sstevel@tonic-gate sc_p->sc_ctx_match_reg = 1392*7c478bd9Sstevel@tonic-gate (uint64_t *)(a + SCHIZO_SC_CTX_MATCH_REG_OFFSET); 1393*7c478bd9Sstevel@tonic-gate 1394*7c478bd9Sstevel@tonic-gate /* 1395*7c478bd9Sstevel@tonic-gate * Determine the virtual addresses of the streaming cache 1396*7c478bd9Sstevel@tonic-gate * diagnostic access registers. 1397*7c478bd9Sstevel@tonic-gate */ 1398*7c478bd9Sstevel@tonic-gate sc_p->sc_data_diag_acc = (uint64_t *)(a + SCHIZO_SC_DATA_DIAG_OFFSET); 1399*7c478bd9Sstevel@tonic-gate sc_p->sc_tag_diag_acc = (uint64_t *)(a + SCHIZO_SC_TAG_DIAG_OFFSET); 1400*7c478bd9Sstevel@tonic-gate sc_p->sc_ltag_diag_acc = (uint64_t *)(a + SCHIZO_SC_LTAG_DIAG_OFFSET); 1401*7c478bd9Sstevel@tonic-gate } 1402*7c478bd9Sstevel@tonic-gate 1403*7c478bd9Sstevel@tonic-gate /*ARGSUSED*/ 1404*7c478bd9Sstevel@tonic-gate int 1405*7c478bd9Sstevel@tonic-gate pci_get_numproxy(dev_info_t *dip) 1406*7c478bd9Sstevel@tonic-gate { 1407*7c478bd9Sstevel@tonic-gate /* 1408*7c478bd9Sstevel@tonic-gate * Schizo does not support interrupt proxies. 1409*7c478bd9Sstevel@tonic-gate */ 1410*7c478bd9Sstevel@tonic-gate return (0); 1411*7c478bd9Sstevel@tonic-gate } 1412*7c478bd9Sstevel@tonic-gate 1413*7c478bd9Sstevel@tonic-gate /* 1414*7c478bd9Sstevel@tonic-gate * pcisch error handling 101: 1415*7c478bd9Sstevel@tonic-gate * 1416*7c478bd9Sstevel@tonic-gate * The various functions below are responsible for error handling. Given 1417*7c478bd9Sstevel@tonic-gate * a particular error, they must gather the appropriate state, report all 1418*7c478bd9Sstevel@tonic-gate * errors with correct payload, and attempt recovery where ever possible. 1419*7c478bd9Sstevel@tonic-gate * 1420*7c478bd9Sstevel@tonic-gate * Recovery in the context of this driver is being able notify a leaf device 1421*7c478bd9Sstevel@tonic-gate * of the failed transaction. This leaf device may either be the master or 1422*7c478bd9Sstevel@tonic-gate * target for this transaction and may have already received an error 1423*7c478bd9Sstevel@tonic-gate * notification via a PCI interrupt. Notification is done via DMA and access 1424*7c478bd9Sstevel@tonic-gate * handles. If we capture an address for the transaction then we can map it 1425*7c478bd9Sstevel@tonic-gate * to a handle(if the leaf device is fma-compliant) and fault the handle as 1426*7c478bd9Sstevel@tonic-gate * well as call the device driver registered callback. 1427*7c478bd9Sstevel@tonic-gate * 1428*7c478bd9Sstevel@tonic-gate * The hardware can either interrupt or trap upon detection of an error, in 1429*7c478bd9Sstevel@tonic-gate * some rare cases it also causes a fatal reset. 1430*7c478bd9Sstevel@tonic-gate * 1431*7c478bd9Sstevel@tonic-gate * cb_buserr_intr() is responsible for handling control block 1432*7c478bd9Sstevel@tonic-gate * errors(errors which stem from the host bus side of the bridge). Since 1433*7c478bd9Sstevel@tonic-gate * we support multiple chips and host bus standards, cb_buserr_intr will 1434*7c478bd9Sstevel@tonic-gate * call a bus specific error handler to report and handle the detected 1435*7c478bd9Sstevel@tonic-gate * error. Since this error can either affect or orginate from either of the 1436*7c478bd9Sstevel@tonic-gate * two PCI busses which are connected to the bridge, we need to call 1437*7c478bd9Sstevel@tonic-gate * pci_pbm_err_handler() for each bus as well to report their errors. We 1438*7c478bd9Sstevel@tonic-gate * also need to gather possible errors which have been detected by their 1439*7c478bd9Sstevel@tonic-gate * compliant children(via ndi_fm_handler_dispatch()). 1440*7c478bd9Sstevel@tonic-gate * 1441*7c478bd9Sstevel@tonic-gate * pbm_error_intr() and ecc_intr() are responsible for PCI Block Module 1442*7c478bd9Sstevel@tonic-gate * errors(generic PCI + bridge specific) and ECC errors, respectively. They 1443*7c478bd9Sstevel@tonic-gate * are common between pcisch and pcipsy and therefore exist in pci_pbm.c and 1444*7c478bd9Sstevel@tonic-gate * pci_ecc.c. To support error handling certain chip specific handlers 1445*7c478bd9Sstevel@tonic-gate * must exist and they are defined below. 1446*7c478bd9Sstevel@tonic-gate * 1447*7c478bd9Sstevel@tonic-gate * cpu_deferred_error() and cpu_async_error(), handle the traps that may 1448*7c478bd9Sstevel@tonic-gate * have originated from IO space. They call into the registered IO callbacks 1449*7c478bd9Sstevel@tonic-gate * to report and handle errors that may have caused the trap. 1450*7c478bd9Sstevel@tonic-gate * 1451*7c478bd9Sstevel@tonic-gate * pci_pbm_err_handler() is called by pbm_error_intr() or pci_err_callback() 1452*7c478bd9Sstevel@tonic-gate * (generic fma callback for pcipsy/pcisch, pci_fm.c). pci_err_callback() is 1453*7c478bd9Sstevel@tonic-gate * called when the CPU has trapped because of a possible IO error(TO/BERR/UE). 1454*7c478bd9Sstevel@tonic-gate * It will call pci_pbm_err_handler() to report and handle all PCI/PBM/IOMMU 1455*7c478bd9Sstevel@tonic-gate * related errors which are detected by the chip. 1456*7c478bd9Sstevel@tonic-gate * 1457*7c478bd9Sstevel@tonic-gate * pci_pbm_err_handler() calls a generic interface pbm_afsr_report()(pci_pbm.c) 1458*7c478bd9Sstevel@tonic-gate * to report the pbm specific errors and attempt to map the failed address 1459*7c478bd9Sstevel@tonic-gate * (if captured) to a device instance. pbm_afsr_report() calls a chip specific 1460*7c478bd9Sstevel@tonic-gate * interface to interpret the afsr bits pci_pbm_classify()(pcisch.c/pcipsy.c). 1461*7c478bd9Sstevel@tonic-gate * pci_pbm_err_handler() also calls iommu_err_handler() to handle IOMMU related 1462*7c478bd9Sstevel@tonic-gate * errors. 1463*7c478bd9Sstevel@tonic-gate * 1464*7c478bd9Sstevel@tonic-gate * iommu_err_handler() can recover from most errors, as long as the requesting 1465*7c478bd9Sstevel@tonic-gate * device is notified and the iommu can be flushed. If an IOMMU error occurs 1466*7c478bd9Sstevel@tonic-gate * due to a UE then it will be passed on to the ecc_err_handler() for 1467*7c478bd9Sstevel@tonic-gate * subsequent handling. 1468*7c478bd9Sstevel@tonic-gate * 1469*7c478bd9Sstevel@tonic-gate * ecc_err_handler()(pci_ecc.c) also calls a chip specific interface to 1470*7c478bd9Sstevel@tonic-gate * interpret the afsr, pci_ecc_classify(). ecc_err_handler() also calls 1471*7c478bd9Sstevel@tonic-gate * pci_pbm_err_handler() to report any pbm errors detected. 1472*7c478bd9Sstevel@tonic-gate * 1473*7c478bd9Sstevel@tonic-gate * To make sure that the trap code and the interrupt code are not going 1474*7c478bd9Sstevel@tonic-gate * to step on each others toes we have a per chip pci_fm_mutex. This also 1475*7c478bd9Sstevel@tonic-gate * makes it necessary for us to be caution while we are at a high PIL, so 1476*7c478bd9Sstevel@tonic-gate * that we do not cause a subsequent trap that causes us to hang. 1477*7c478bd9Sstevel@tonic-gate * 1478*7c478bd9Sstevel@tonic-gate * The attempt to commonize code was meant to keep in line with the current 1479*7c478bd9Sstevel@tonic-gate * pci driver implementation and it was not meant to confuse. If you are 1480*7c478bd9Sstevel@tonic-gate * confused then don't worry, I was too. 1481*7c478bd9Sstevel@tonic-gate * 1482*7c478bd9Sstevel@tonic-gate */ 1483*7c478bd9Sstevel@tonic-gate static void 1484*7c478bd9Sstevel@tonic-gate pci_cb_errstate_get(cb_t *cb_p, cb_errstate_t *cb_err_p) 1485*7c478bd9Sstevel@tonic-gate { 1486*7c478bd9Sstevel@tonic-gate uint64_t pa = cb_p->cb_base_pa; 1487*7c478bd9Sstevel@tonic-gate int i; 1488*7c478bd9Sstevel@tonic-gate 1489*7c478bd9Sstevel@tonic-gate bzero(cb_err_p, sizeof (cb_errstate_t)); 1490*7c478bd9Sstevel@tonic-gate 1491*7c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&cb_p->cb_pci_cmn_p->pci_fm_mutex)); 1492*7c478bd9Sstevel@tonic-gate 1493*7c478bd9Sstevel@tonic-gate cb_err_p->cb_bridge_type = PCI_BRIDGE_TYPE(cb_p->cb_pci_cmn_p); 1494*7c478bd9Sstevel@tonic-gate 1495*7c478bd9Sstevel@tonic-gate cb_err_p->cb_csr = lddphysio(pa + SCHIZO_CB_CSR_OFFSET); 1496*7c478bd9Sstevel@tonic-gate cb_err_p->cb_err = lddphysio(pa + SCHIZO_CB_ERRCTRL_OFFSET); 1497*7c478bd9Sstevel@tonic-gate cb_err_p->cb_intr = lddphysio(pa + SCHIZO_CB_INTCTRL_OFFSET); 1498*7c478bd9Sstevel@tonic-gate cb_err_p->cb_elog = lddphysio(pa + SCHIZO_CB_ERRLOG_OFFSET); 1499*7c478bd9Sstevel@tonic-gate cb_err_p->cb_ecc = lddphysio(pa + SCHIZO_CB_ECCCTRL_OFFSET); 1500*7c478bd9Sstevel@tonic-gate cb_err_p->cb_ue_afsr = lddphysio(pa + SCHIZO_CB_UEAFSR_OFFSET); 1501*7c478bd9Sstevel@tonic-gate cb_err_p->cb_ue_afar = lddphysio(pa + SCHIZO_CB_UEAFAR_OFFSET); 1502*7c478bd9Sstevel@tonic-gate cb_err_p->cb_ce_afsr = lddphysio(pa + SCHIZO_CB_CEAFSR_OFFSET); 1503*7c478bd9Sstevel@tonic-gate cb_err_p->cb_ce_afar = lddphysio(pa + SCHIZO_CB_CEAFAR_OFFSET); 1504*7c478bd9Sstevel@tonic-gate 1505*7c478bd9Sstevel@tonic-gate if ((CB_CHIP_TYPE((cb_t *)cb_p)) == PCI_CHIP_XMITS) { 1506*7c478bd9Sstevel@tonic-gate cb_err_p->cb_first_elog = lddphysio(pa + 1507*7c478bd9Sstevel@tonic-gate XMITS_CB_FIRST_ERROR_LOG); 1508*7c478bd9Sstevel@tonic-gate cb_err_p->cb_first_eaddr = lddphysio(pa + 1509*7c478bd9Sstevel@tonic-gate XMITS_CB_FIRST_ERROR_ADDR); 1510*7c478bd9Sstevel@tonic-gate cb_err_p->cb_leaf_status = lddphysio(pa + 1511*7c478bd9Sstevel@tonic-gate XMITS_CB_FIRST_ERROR_ADDR); 1512*7c478bd9Sstevel@tonic-gate } 1513*7c478bd9Sstevel@tonic-gate 1514*7c478bd9Sstevel@tonic-gate /* Gather PBM state information for both sides of this chip */ 1515*7c478bd9Sstevel@tonic-gate for (i = 0; i < 2; i++) { 1516*7c478bd9Sstevel@tonic-gate if (cb_p->cb_pci_cmn_p->pci_p[i] == NULL) 1517*7c478bd9Sstevel@tonic-gate continue; 1518*7c478bd9Sstevel@tonic-gate pci_pbm_errstate_get(((cb_t *)cb_p)->cb_pci_cmn_p-> 1519*7c478bd9Sstevel@tonic-gate pci_p[i], &cb_err_p->cb_pbm[i]); 1520*7c478bd9Sstevel@tonic-gate } 1521*7c478bd9Sstevel@tonic-gate } 1522*7c478bd9Sstevel@tonic-gate 1523*7c478bd9Sstevel@tonic-gate static void 1524*7c478bd9Sstevel@tonic-gate pci_cb_clear_error(cb_t *cb_p, cb_errstate_t *cb_err_p) 1525*7c478bd9Sstevel@tonic-gate { 1526*7c478bd9Sstevel@tonic-gate uint64_t pa = ((cb_t *)cb_p)->cb_base_pa; 1527*7c478bd9Sstevel@tonic-gate 1528*7c478bd9Sstevel@tonic-gate stdphysio(pa + SCHIZO_CB_ERRLOG_OFFSET, cb_err_p->cb_elog); 1529*7c478bd9Sstevel@tonic-gate } 1530*7c478bd9Sstevel@tonic-gate 1531*7c478bd9Sstevel@tonic-gate static cb_fm_err_t safari_err_tbl[] = { 1532*7c478bd9Sstevel@tonic-gate SAFARI_BAD_CMD, SCHIZO_CB_ELOG_BAD_CMD, CB_FATAL, 1533*7c478bd9Sstevel@tonic-gate SAFARI_SSM_DIS, SCHIZO_CB_ELOG_SSM_DIS, CB_FATAL, 1534*7c478bd9Sstevel@tonic-gate SAFARI_BAD_CMD_PCIA, SCHIZO_CB_ELOG_BAD_CMD_PCIA, CB_FATAL, 1535*7c478bd9Sstevel@tonic-gate SAFARI_BAD_CMD_PCIB, SCHIZO_CB_ELOG_BAD_CMD_PCIB, CB_FATAL, 1536*7c478bd9Sstevel@tonic-gate SAFARI_PAR_ERR_INT_PCIB, XMITS_CB_ELOG_PAR_ERR_INT_PCIB, CB_FATAL, 1537*7c478bd9Sstevel@tonic-gate SAFARI_PAR_ERR_INT_PCIA, XMITS_CB_ELOG_PAR_ERR_INT_PCIA, CB_FATAL, 1538*7c478bd9Sstevel@tonic-gate SAFARI_PAR_ERR_INT_SAF, XMITS_CB_ELOG_PAR_ERR_INT_SAF, CB_FATAL, 1539*7c478bd9Sstevel@tonic-gate SAFARI_PLL_ERR_PCIB, XMITS_CB_ELOG_PLL_ERR_PCIB, CB_FATAL, 1540*7c478bd9Sstevel@tonic-gate SAFARI_PLL_ERR_PCIA, XMITS_CB_ELOG_PLL_ERR_PCIA, CB_FATAL, 1541*7c478bd9Sstevel@tonic-gate SAFARI_PLL_ERR_SAF, XMITS_CB_ELOG_PLL_ERR_SAF, CB_FATAL, 1542*7c478bd9Sstevel@tonic-gate SAFARI_SAF_CIQ_TO, SCHIZO_CB_ELOG_SAF_CIQ_TO, CB_FATAL, 1543*7c478bd9Sstevel@tonic-gate SAFARI_SAF_LPQ_TO, SCHIZO_CB_ELOG_SAF_LPQ_TO, CB_FATAL, 1544*7c478bd9Sstevel@tonic-gate SAFARI_SAF_SFPQ_TO, SCHIZO_CB_ELOG_SAF_SFPQ_TO, CB_FATAL, 1545*7c478bd9Sstevel@tonic-gate SAFARI_APERR, SCHIZO_CB_ELOG_ADDR_PAR_ERR, CB_FATAL, 1546*7c478bd9Sstevel@tonic-gate SAFARI_UNMAP_ERR, SCHIZO_CB_ELOG_UNMAP_ERR, CB_FATAL, 1547*7c478bd9Sstevel@tonic-gate SAFARI_BUS_ERR, SCHIZO_CB_ELOG_BUS_ERR, CB_FATAL, 1548*7c478bd9Sstevel@tonic-gate SAFARI_TO_ERR, SCHIZO_CB_ELOG_TO_ERR, CB_FATAL, 1549*7c478bd9Sstevel@tonic-gate SAFARI_DSTAT_ERR, SCHIZO_CB_ELOG_DSTAT_ERR, CB_FATAL, 1550*7c478bd9Sstevel@tonic-gate SAFARI_SAF_UFPQ_TO, SCHIZO_CB_ELOG_SAF_UFPQ_TO, CB_FATAL, 1551*7c478bd9Sstevel@tonic-gate SAFARI_CPU0_PAR_SINGLE, SCHIZO_CB_ELOG_CPU0_PAR_SINGLE, CB_FATAL, 1552*7c478bd9Sstevel@tonic-gate SAFARI_CPU0_PAR_BIDI, SCHIZO_CB_ELOG_CPU0_PAR_BIDI, CB_FATAL, 1553*7c478bd9Sstevel@tonic-gate SAFARI_CPU1_PAR_SINGLE, SCHIZO_CB_ELOG_CPU1_PAR_SINGLE, CB_FATAL, 1554*7c478bd9Sstevel@tonic-gate SAFARI_CPU1_PAR_BIDI, SCHIZO_CB_ELOG_CPU1_PAR_BIDI, CB_FATAL, 1555*7c478bd9Sstevel@tonic-gate NULL, NULL, NULL, 1556*7c478bd9Sstevel@tonic-gate }; 1557*7c478bd9Sstevel@tonic-gate 1558*7c478bd9Sstevel@tonic-gate /* 1559*7c478bd9Sstevel@tonic-gate * Function used to handle and log Safari bus errors. 1560*7c478bd9Sstevel@tonic-gate */ 1561*7c478bd9Sstevel@tonic-gate static int 1562*7c478bd9Sstevel@tonic-gate safari_err_handler(dev_info_t *dip, uint64_t fme_ena, 1563*7c478bd9Sstevel@tonic-gate cb_errstate_t *cb_err_p) 1564*7c478bd9Sstevel@tonic-gate { 1565*7c478bd9Sstevel@tonic-gate int i; 1566*7c478bd9Sstevel@tonic-gate int fatal = 0; 1567*7c478bd9Sstevel@tonic-gate pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 1568*7c478bd9Sstevel@tonic-gate pci_common_t *cmn_p = pci_p->pci_common_p; 1569*7c478bd9Sstevel@tonic-gate 1570*7c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&cmn_p->pci_fm_mutex)); 1571*7c478bd9Sstevel@tonic-gate 1572*7c478bd9Sstevel@tonic-gate for (i = 0; safari_err_tbl[i].cb_err_class != NULL; i++) { 1573*7c478bd9Sstevel@tonic-gate if (cb_err_p->cb_elog & safari_err_tbl[i].cb_reg_bit) { 1574*7c478bd9Sstevel@tonic-gate cb_err_p->cb_err_class = safari_err_tbl[i].cb_err_class; 1575*7c478bd9Sstevel@tonic-gate cb_ereport_post(dip, fme_ena, cb_err_p); 1576*7c478bd9Sstevel@tonic-gate fatal += safari_err_tbl[i].cb_fatal; 1577*7c478bd9Sstevel@tonic-gate } 1578*7c478bd9Sstevel@tonic-gate } 1579*7c478bd9Sstevel@tonic-gate 1580*7c478bd9Sstevel@tonic-gate if (fatal) 1581*7c478bd9Sstevel@tonic-gate return (DDI_FM_FATAL); 1582*7c478bd9Sstevel@tonic-gate return (DDI_FM_OK); 1583*7c478bd9Sstevel@tonic-gate 1584*7c478bd9Sstevel@tonic-gate } 1585*7c478bd9Sstevel@tonic-gate 1586*7c478bd9Sstevel@tonic-gate /* 1587*7c478bd9Sstevel@tonic-gate * Check pbm va log register for captured errant address, and fail handle 1588*7c478bd9Sstevel@tonic-gate * if in per device cache. 1589*7c478bd9Sstevel@tonic-gate * Called from jbus_err_handler. 1590*7c478bd9Sstevel@tonic-gate */ 1591*7c478bd9Sstevel@tonic-gate static int 1592*7c478bd9Sstevel@tonic-gate jbus_check_va_log(cb_t *cb_p, uint64_t fme_ena, 1593*7c478bd9Sstevel@tonic-gate cb_errstate_t *cb_err_p) 1594*7c478bd9Sstevel@tonic-gate { 1595*7c478bd9Sstevel@tonic-gate int i; 1596*7c478bd9Sstevel@tonic-gate int ret = DDI_FM_FATAL; 1597*7c478bd9Sstevel@tonic-gate pci_common_t *cmn_p = cb_p->cb_pci_cmn_p; 1598*7c478bd9Sstevel@tonic-gate 1599*7c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&cmn_p->pci_fm_mutex)); 1600*7c478bd9Sstevel@tonic-gate /* 1601*7c478bd9Sstevel@tonic-gate * Check VA log register for address associated with error, 1602*7c478bd9Sstevel@tonic-gate * if no address is registered then return failure 1603*7c478bd9Sstevel@tonic-gate */ 1604*7c478bd9Sstevel@tonic-gate for (i = 0; i < 2; i++) { 1605*7c478bd9Sstevel@tonic-gate 1606*7c478bd9Sstevel@tonic-gate if (cb_p->cb_pci_cmn_p->pci_p[i] == NULL) 1607*7c478bd9Sstevel@tonic-gate continue; 1608*7c478bd9Sstevel@tonic-gate /* 1609*7c478bd9Sstevel@tonic-gate * Look up and fault handle associated with 1610*7c478bd9Sstevel@tonic-gate * logged DMA address 1611*7c478bd9Sstevel@tonic-gate */ 1612*7c478bd9Sstevel@tonic-gate if (cb_err_p->cb_pbm[i].pbm_va_log) { 1613*7c478bd9Sstevel@tonic-gate ret = pci_handle_lookup(cb_p->cb_pci_cmn_p->pci_p[i]-> 1614*7c478bd9Sstevel@tonic-gate pci_dip, DMA_HANDLE, fme_ena, 1615*7c478bd9Sstevel@tonic-gate (void *)&cb_err_p->cb_pbm[i]. 1616*7c478bd9Sstevel@tonic-gate pbm_va_log); 1617*7c478bd9Sstevel@tonic-gate if (ret == DDI_FM_NONFATAL) 1618*7c478bd9Sstevel@tonic-gate break; 1619*7c478bd9Sstevel@tonic-gate } 1620*7c478bd9Sstevel@tonic-gate } 1621*7c478bd9Sstevel@tonic-gate return (ret); 1622*7c478bd9Sstevel@tonic-gate } 1623*7c478bd9Sstevel@tonic-gate 1624*7c478bd9Sstevel@tonic-gate static cb_fm_err_t jbus_err_tbl[] = { 1625*7c478bd9Sstevel@tonic-gate JBUS_APERR, SCHIZO_CB_ELOG_ADDR_PAR_ERR, CB_FATAL, 1626*7c478bd9Sstevel@tonic-gate JBUS_PWR_DATA_PERR, TOMATILLO_CB_ELOG_WR_DATA_PAR_ERR, CB_FATAL, 1627*7c478bd9Sstevel@tonic-gate JBUS_DRD_DATA_PERR, TOMATILLO_CB_ELOG_RD_DATA_PAR_ERR, CB_NONFATAL, 1628*7c478bd9Sstevel@tonic-gate JBUS_CTL_PERR, TOMATILLO_CB_ELOG_CTL_PAR_ERR, CB_FATAL, 1629*7c478bd9Sstevel@tonic-gate JBUS_ILL_BYTE_EN, TOMATILLO_CB_ELOG_ILL_BYTE_EN, CB_FATAL, 1630*7c478bd9Sstevel@tonic-gate JBUS_ILL_COH_IN, TOMATILLO_CB_ELOG_ILL_COH_IN, CB_FATAL, 1631*7c478bd9Sstevel@tonic-gate JBUS_SNOOP_ERR_RD, TOMATILLO_CB_ELOG_SNOOP_ERR_RD, CB_FATAL, 1632*7c478bd9Sstevel@tonic-gate JBUS_SNOOP_ERR_RDS, TOMATILLO_CB_ELOG_SNOOP_ERR_RDS, CB_FATAL, 1633*7c478bd9Sstevel@tonic-gate JBUS_SNOOP_ERR_RDSA, TOMATILLO_CB_ELOG_SNOOP_ERR_RDSA, CB_FATAL, 1634*7c478bd9Sstevel@tonic-gate JBUS_SNOOP_ERR_OWN, TOMATILLO_CB_ELOG_SNOOP_ERR_OWN, CB_FATAL, 1635*7c478bd9Sstevel@tonic-gate JBUS_SNOOP_ERR_RDO, TOMATILLO_CB_ELOG_SNOOP_ERR_RDO, CB_FATAL, 1636*7c478bd9Sstevel@tonic-gate JBUS_SNOOP_ERR_PCI, TOMATILLO_CB_ELOG_SNOOP_ERR_PCI, CB_FATAL, 1637*7c478bd9Sstevel@tonic-gate JBUS_SNOOP_ERR_GR, TOMATILLO_CB_ELOG_SNOOP_ERR_GR, CB_FATAL, 1638*7c478bd9Sstevel@tonic-gate JBUS_SNOOP_ERR, TOMATILLO_CB_ELOG_SNOOP_ERR, CB_FATAL, 1639*7c478bd9Sstevel@tonic-gate JBUS_BAD_CMD, SCHIZO_CB_ELOG_BAD_CMD, CB_FATAL, 1640*7c478bd9Sstevel@tonic-gate JBUS_UNMAP_ERR, SCHIZO_CB_ELOG_UNMAP_ERR, CB_NONFATAL, 1641*7c478bd9Sstevel@tonic-gate JBUS_TO_EXP_ERR, TOMATILLO_CB_ELOG_TO_EXP_ERR, CB_NONFATAL, 1642*7c478bd9Sstevel@tonic-gate JBUS_TO_ERR, SCHIZO_CB_ELOG_TO_ERR, CB_NONFATAL, 1643*7c478bd9Sstevel@tonic-gate JBUS_BUS_ERR, SCHIZO_CB_ELOG_BUS_ERR, CB_NONFATAL, 1644*7c478bd9Sstevel@tonic-gate NULL, NULL, NULL, 1645*7c478bd9Sstevel@tonic-gate }; 1646*7c478bd9Sstevel@tonic-gate 1647*7c478bd9Sstevel@tonic-gate /* 1648*7c478bd9Sstevel@tonic-gate * Function used to handle and log Jbus errors. 1649*7c478bd9Sstevel@tonic-gate */ 1650*7c478bd9Sstevel@tonic-gate static int 1651*7c478bd9Sstevel@tonic-gate jbus_err_handler(dev_info_t *dip, uint64_t fme_ena, 1652*7c478bd9Sstevel@tonic-gate cb_errstate_t *cb_err_p) 1653*7c478bd9Sstevel@tonic-gate { 1654*7c478bd9Sstevel@tonic-gate int fatal = 0; 1655*7c478bd9Sstevel@tonic-gate int nonfatal = 0; 1656*7c478bd9Sstevel@tonic-gate int i; 1657*7c478bd9Sstevel@tonic-gate pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 1658*7c478bd9Sstevel@tonic-gate cb_t *cb_p = pci_p->pci_cb_p; 1659*7c478bd9Sstevel@tonic-gate 1660*7c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&pci_p->pci_common_p->pci_fm_mutex)); 1661*7c478bd9Sstevel@tonic-gate 1662*7c478bd9Sstevel@tonic-gate for (i = 0; jbus_err_tbl[i].cb_err_class != NULL; i++) { 1663*7c478bd9Sstevel@tonic-gate if (!(cb_err_p->cb_elog & jbus_err_tbl[i].cb_reg_bit)) 1664*7c478bd9Sstevel@tonic-gate continue; 1665*7c478bd9Sstevel@tonic-gate cb_err_p->cb_err_class = jbus_err_tbl[i].cb_err_class; 1666*7c478bd9Sstevel@tonic-gate if (jbus_err_tbl[i].cb_fatal) { 1667*7c478bd9Sstevel@tonic-gate fatal += jbus_err_tbl[i].cb_fatal; 1668*7c478bd9Sstevel@tonic-gate continue; 1669*7c478bd9Sstevel@tonic-gate } 1670*7c478bd9Sstevel@tonic-gate if (jbus_check_va_log(cb_p, fme_ena, cb_err_p) 1671*7c478bd9Sstevel@tonic-gate != DDI_FM_NONFATAL) { 1672*7c478bd9Sstevel@tonic-gate fatal++; 1673*7c478bd9Sstevel@tonic-gate } 1674*7c478bd9Sstevel@tonic-gate cb_ereport_post(dip, fme_ena, cb_err_p); 1675*7c478bd9Sstevel@tonic-gate } 1676*7c478bd9Sstevel@tonic-gate 1677*7c478bd9Sstevel@tonic-gate return (fatal ? DDI_FM_FATAL : (nonfatal ? DDI_FM_NONFATAL : 1678*7c478bd9Sstevel@tonic-gate DDI_FM_OK)); 1679*7c478bd9Sstevel@tonic-gate } 1680*7c478bd9Sstevel@tonic-gate 1681*7c478bd9Sstevel@tonic-gate /* 1682*7c478bd9Sstevel@tonic-gate * Control Block error interrupt handler. 1683*7c478bd9Sstevel@tonic-gate */ 1684*7c478bd9Sstevel@tonic-gate uint_t 1685*7c478bd9Sstevel@tonic-gate cb_buserr_intr(caddr_t a) 1686*7c478bd9Sstevel@tonic-gate { 1687*7c478bd9Sstevel@tonic-gate cb_t *cb_p = (cb_t *)a; 1688*7c478bd9Sstevel@tonic-gate pci_common_t *cmn_p = cb_p->cb_pci_cmn_p; 1689*7c478bd9Sstevel@tonic-gate pci_t *pci_p = cmn_p->pci_p[0]; 1690*7c478bd9Sstevel@tonic-gate cb_errstate_t cb_err; 1691*7c478bd9Sstevel@tonic-gate ddi_fm_error_t derr; 1692*7c478bd9Sstevel@tonic-gate int ret = DDI_FM_FATAL; 1693*7c478bd9Sstevel@tonic-gate int i; 1694*7c478bd9Sstevel@tonic-gate 1695*7c478bd9Sstevel@tonic-gate if (pci_p == NULL) 1696*7c478bd9Sstevel@tonic-gate pci_p = cmn_p->pci_p[1]; 1697*7c478bd9Sstevel@tonic-gate 1698*7c478bd9Sstevel@tonic-gate bzero(&derr, sizeof (ddi_fm_error_t)); 1699*7c478bd9Sstevel@tonic-gate derr.fme_version = DDI_FME_VERSION; 1700*7c478bd9Sstevel@tonic-gate derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 1701*7c478bd9Sstevel@tonic-gate 1702*7c478bd9Sstevel@tonic-gate mutex_enter(&cmn_p->pci_fm_mutex); 1703*7c478bd9Sstevel@tonic-gate 1704*7c478bd9Sstevel@tonic-gate pci_cb_errstate_get(cb_p, &cb_err); 1705*7c478bd9Sstevel@tonic-gate 1706*7c478bd9Sstevel@tonic-gate if (CB_CHIP_TYPE(cb_p) == PCI_CHIP_TOMATILLO) 1707*7c478bd9Sstevel@tonic-gate ret = jbus_err_handler(pci_p->pci_dip, derr.fme_ena, &cb_err); 1708*7c478bd9Sstevel@tonic-gate else if ((CB_CHIP_TYPE(cb_p) == PCI_CHIP_SCHIZO) || 1709*7c478bd9Sstevel@tonic-gate (CB_CHIP_TYPE(cb_p) == PCI_CHIP_XMITS)) 1710*7c478bd9Sstevel@tonic-gate ret = safari_err_handler(pci_p->pci_dip, derr.fme_ena, 1711*7c478bd9Sstevel@tonic-gate &cb_err); 1712*7c478bd9Sstevel@tonic-gate 1713*7c478bd9Sstevel@tonic-gate /* 1714*7c478bd9Sstevel@tonic-gate * Check for related errors in PBM and IOMMU. The IOMMU could cause 1715*7c478bd9Sstevel@tonic-gate * a timeout on the jbus due to an IOMMU miss, so we need to check and 1716*7c478bd9Sstevel@tonic-gate * log the IOMMU error registers. 1717*7c478bd9Sstevel@tonic-gate */ 1718*7c478bd9Sstevel@tonic-gate for (i = 0; i < 2; i++) { 1719*7c478bd9Sstevel@tonic-gate if (cmn_p->pci_p[i] == NULL) 1720*7c478bd9Sstevel@tonic-gate continue; 1721*7c478bd9Sstevel@tonic-gate if (pci_pbm_err_handler(cmn_p->pci_p[i]->pci_dip, &derr, 1722*7c478bd9Sstevel@tonic-gate (void *)cmn_p->pci_p[i], PCI_CB_CALL) == DDI_FM_FATAL) 1723*7c478bd9Sstevel@tonic-gate ret = DDI_FM_FATAL; 1724*7c478bd9Sstevel@tonic-gate } 1725*7c478bd9Sstevel@tonic-gate 1726*7c478bd9Sstevel@tonic-gate /* Cleanup and reset error bits */ 1727*7c478bd9Sstevel@tonic-gate (void) pci_cb_clear_error(cb_p, &cb_err); 1728*7c478bd9Sstevel@tonic-gate mutex_exit(&cmn_p->pci_fm_mutex); 1729*7c478bd9Sstevel@tonic-gate 1730*7c478bd9Sstevel@tonic-gate if (ret == DDI_FM_FATAL) { 1731*7c478bd9Sstevel@tonic-gate fm_panic("Fatal System Bus Error has occurred\n"); 1732*7c478bd9Sstevel@tonic-gate } 1733*7c478bd9Sstevel@tonic-gate 1734*7c478bd9Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 1735*7c478bd9Sstevel@tonic-gate } 1736*7c478bd9Sstevel@tonic-gate 1737*7c478bd9Sstevel@tonic-gate static ecc_fm_err_t ecc_err_tbl[] = { 1738*7c478bd9Sstevel@tonic-gate PCI_ECC_PIO_UE, COMMON_ECC_UE_AFSR_E_PIO, CBNINTR_UE, 1739*7c478bd9Sstevel@tonic-gate PBM_PRIMARY, SCHIZO_ECC_AFAR_PIOW_UPA64S, SCH_REG_UPA, 1740*7c478bd9Sstevel@tonic-gate ACC_HANDLE, 1741*7c478bd9Sstevel@tonic-gate 1742*7c478bd9Sstevel@tonic-gate PCI_ECC_PIO_UE, COMMON_ECC_UE_AFSR_E_PIO, CBNINTR_UE, 1743*7c478bd9Sstevel@tonic-gate PBM_PRIMARY, SCHIZO_ECC_AFAR_PIOW_PCIA_REG, SCH_REG_PCIA_REG, 1744*7c478bd9Sstevel@tonic-gate ACC_HANDLE, 1745*7c478bd9Sstevel@tonic-gate 1746*7c478bd9Sstevel@tonic-gate PCI_ECC_PIO_UE, COMMON_ECC_UE_AFSR_E_PIO, CBNINTR_UE, 1747*7c478bd9Sstevel@tonic-gate PBM_PRIMARY, SCHIZO_ECC_AFAR_PIOW_PCIA_MEM, SCH_REG_PCIA_MEM, 1748*7c478bd9Sstevel@tonic-gate ACC_HANDLE, 1749*7c478bd9Sstevel@tonic-gate 1750*7c478bd9Sstevel@tonic-gate PCI_ECC_PIO_UE, COMMON_ECC_UE_AFSR_E_PIO, CBNINTR_UE, 1751*7c478bd9Sstevel@tonic-gate PBM_PRIMARY, SCHIZO_ECC_AFAR_PIOW_PCIA_CFGIO, SCH_REG_PCIA_CFGIO, 1752*7c478bd9Sstevel@tonic-gate ACC_HANDLE, 1753*7c478bd9Sstevel@tonic-gate 1754*7c478bd9Sstevel@tonic-gate PCI_ECC_PIO_UE, COMMON_ECC_UE_AFSR_E_PIO, CBNINTR_UE, 1755*7c478bd9Sstevel@tonic-gate PBM_PRIMARY, SCHIZO_ECC_AFAR_PIOW_PCIB_REG, SCH_REG_PCIB_REG, 1756*7c478bd9Sstevel@tonic-gate ACC_HANDLE, 1757*7c478bd9Sstevel@tonic-gate 1758*7c478bd9Sstevel@tonic-gate PCI_ECC_PIO_UE, COMMON_ECC_UE_AFSR_E_PIO, CBNINTR_UE, 1759*7c478bd9Sstevel@tonic-gate PBM_PRIMARY, SCHIZO_ECC_AFAR_PIOW_PCIB_MEM, SCH_REG_PCIB_MEM, 1760*7c478bd9Sstevel@tonic-gate ACC_HANDLE, 1761*7c478bd9Sstevel@tonic-gate 1762*7c478bd9Sstevel@tonic-gate PCI_ECC_PIO_UE, COMMON_ECC_UE_AFSR_E_PIO, CBNINTR_UE, 1763*7c478bd9Sstevel@tonic-gate PBM_PRIMARY, SCHIZO_ECC_AFAR_PIOW_PCIB_CFGIO, SCH_REG_PCIB_CFGIO, 1764*7c478bd9Sstevel@tonic-gate ACC_HANDLE, 1765*7c478bd9Sstevel@tonic-gate 1766*7c478bd9Sstevel@tonic-gate PCI_ECC_PIO_UE, COMMON_ECC_UE_AFSR_E_PIO, CBNINTR_UE, 1767*7c478bd9Sstevel@tonic-gate PBM_PRIMARY, SCHIZO_ECC_AFAR_PIOW_SAFARI_REGS, SCH_REG_SAFARI_REGS, 1768*7c478bd9Sstevel@tonic-gate ACC_HANDLE, 1769*7c478bd9Sstevel@tonic-gate 1770*7c478bd9Sstevel@tonic-gate PCI_ECC_SEC_PIO_UE, COMMON_ECC_UE_AFSR_E_PIO, CBNINTR_UE, 1771*7c478bd9Sstevel@tonic-gate PBM_SECONDARY, NULL, NULL, ACC_HANDLE, 1772*7c478bd9Sstevel@tonic-gate 1773*7c478bd9Sstevel@tonic-gate PCI_ECC_PIO_CE, COMMON_ECC_UE_AFSR_E_PIO, CBNINTR_CE, 1774*7c478bd9Sstevel@tonic-gate PBM_PRIMARY, NULL, NULL, ACC_HANDLE, 1775*7c478bd9Sstevel@tonic-gate 1776*7c478bd9Sstevel@tonic-gate PCI_ECC_SEC_PIO_CE, COMMON_ECC_UE_AFSR_E_PIO, CBNINTR_CE, 1777*7c478bd9Sstevel@tonic-gate PBM_SECONDARY, NULL, NULL, ACC_HANDLE, 1778*7c478bd9Sstevel@tonic-gate 1779*7c478bd9Sstevel@tonic-gate PCI_ECC_DRD_UE, COMMON_ECC_UE_AFSR_E_DRD, CBNINTR_UE, 1780*7c478bd9Sstevel@tonic-gate PBM_PRIMARY, NULL, NULL, DMA_HANDLE, 1781*7c478bd9Sstevel@tonic-gate 1782*7c478bd9Sstevel@tonic-gate PCI_ECC_SEC_DRD_UE, COMMON_ECC_UE_AFSR_E_DRD, CBNINTR_UE, 1783*7c478bd9Sstevel@tonic-gate PBM_SECONDARY, NULL, NULL, DMA_HANDLE, 1784*7c478bd9Sstevel@tonic-gate 1785*7c478bd9Sstevel@tonic-gate PCI_ECC_DRD_CE, COMMON_ECC_UE_AFSR_E_DRD, CBNINTR_CE, 1786*7c478bd9Sstevel@tonic-gate PBM_PRIMARY, NULL, NULL, DMA_HANDLE, 1787*7c478bd9Sstevel@tonic-gate 1788*7c478bd9Sstevel@tonic-gate PCI_ECC_SEC_DRD_CE, COMMON_ECC_UE_AFSR_E_DRD, CBNINTR_CE, 1789*7c478bd9Sstevel@tonic-gate PBM_SECONDARY, NULL, NULL, DMA_HANDLE, 1790*7c478bd9Sstevel@tonic-gate 1791*7c478bd9Sstevel@tonic-gate PCI_ECC_DWR_UE, COMMON_ECC_UE_AFSR_E_DWR, CBNINTR_UE, 1792*7c478bd9Sstevel@tonic-gate PBM_PRIMARY, NULL, NULL, DMA_HANDLE, 1793*7c478bd9Sstevel@tonic-gate 1794*7c478bd9Sstevel@tonic-gate PCI_ECC_SEC_DWR_UE, COMMON_ECC_UE_AFSR_E_DWR, CBNINTR_UE, 1795*7c478bd9Sstevel@tonic-gate PBM_SECONDARY, NULL, NULL, DMA_HANDLE, 1796*7c478bd9Sstevel@tonic-gate 1797*7c478bd9Sstevel@tonic-gate PCI_ECC_DWR_CE, COMMON_ECC_UE_AFSR_E_DWR, CBNINTR_CE, 1798*7c478bd9Sstevel@tonic-gate PBM_PRIMARY, NULL, NULL, DMA_HANDLE, 1799*7c478bd9Sstevel@tonic-gate 1800*7c478bd9Sstevel@tonic-gate PCI_ECC_SEC_DWR_CE, COMMON_ECC_UE_AFSR_E_DWR, CBNINTR_CE, 1801*7c478bd9Sstevel@tonic-gate PBM_SECONDARY, NULL, NULL, DMA_HANDLE, 1802*7c478bd9Sstevel@tonic-gate 1803*7c478bd9Sstevel@tonic-gate NULL, NULL, NULL, NULL, NULL, NULL, 1804*7c478bd9Sstevel@tonic-gate }; 1805*7c478bd9Sstevel@tonic-gate 1806*7c478bd9Sstevel@tonic-gate /* 1807*7c478bd9Sstevel@tonic-gate * pci_ecc_classify, called by ecc_handler to classify ecc errors 1808*7c478bd9Sstevel@tonic-gate * and determine if we should panic or not. 1809*7c478bd9Sstevel@tonic-gate */ 1810*7c478bd9Sstevel@tonic-gate void 1811*7c478bd9Sstevel@tonic-gate pci_ecc_classify(uint64_t err, ecc_errstate_t *ecc_err_p) 1812*7c478bd9Sstevel@tonic-gate { 1813*7c478bd9Sstevel@tonic-gate struct async_flt *ecc_p = &ecc_err_p->ecc_aflt; 1814*7c478bd9Sstevel@tonic-gate uint64_t region, afar = ecc_p->flt_addr; 1815*7c478bd9Sstevel@tonic-gate int i, j, ret = 0; 1816*7c478bd9Sstevel@tonic-gate int flag, fatal = 0; 1817*7c478bd9Sstevel@tonic-gate pci_common_t *cmn_p = ecc_err_p->ecc_ii_p.ecc_p->ecc_pci_cmn_p; 1818*7c478bd9Sstevel@tonic-gate pci_t *pci_p = cmn_p->pci_p[0]; 1819*7c478bd9Sstevel@tonic-gate 1820*7c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&cmn_p->pci_fm_mutex)); 1821*7c478bd9Sstevel@tonic-gate 1822*7c478bd9Sstevel@tonic-gate ecc_err_p->ecc_bridge_type = PCI_BRIDGE_TYPE(cmn_p); 1823*7c478bd9Sstevel@tonic-gate 1824*7c478bd9Sstevel@tonic-gate if (pci_p == NULL) 1825*7c478bd9Sstevel@tonic-gate pci_p = cmn_p->pci_p[1]; 1826*7c478bd9Sstevel@tonic-gate 1827*7c478bd9Sstevel@tonic-gate ecc_err_p->ecc_ctrl = lddphysio(ecc_err_p->ecc_ii_p.ecc_p->ecc_csr_pa); 1828*7c478bd9Sstevel@tonic-gate ecc_err_p->ecc_err_addr = afar; 1829*7c478bd9Sstevel@tonic-gate region = afar & SCHIZO_ECC_AFAR_PIOW_MASK; 1830*7c478bd9Sstevel@tonic-gate 1831*7c478bd9Sstevel@tonic-gate for (i = 0; ecc_err_tbl[i].ecc_err_class != NULL; i++) { 1832*7c478bd9Sstevel@tonic-gate if (!(err & ecc_err_tbl[i].ecc_reg_bit) || 1833*7c478bd9Sstevel@tonic-gate (ecc_err_p->ecc_ii_p.ecc_type != 1834*7c478bd9Sstevel@tonic-gate ecc_err_tbl[i].ecc_type) || 1835*7c478bd9Sstevel@tonic-gate (ecc_err_p->ecc_pri != ecc_err_tbl[i].ecc_pri)) 1836*7c478bd9Sstevel@tonic-gate continue; 1837*7c478bd9Sstevel@tonic-gate 1838*7c478bd9Sstevel@tonic-gate ecc_p->flt_erpt_class = ecc_err_tbl[i].ecc_err_class; 1839*7c478bd9Sstevel@tonic-gate flag = ecc_err_tbl[i].ecc_flag; 1840*7c478bd9Sstevel@tonic-gate 1841*7c478bd9Sstevel@tonic-gate if (!ecc_err_tbl[i].ecc_pri || 1842*7c478bd9Sstevel@tonic-gate (ecc_err_tbl[i].ecc_type == CBNINTR_CE)) { 1843*7c478bd9Sstevel@tonic-gate fatal += (ecc_err_tbl[i].ecc_type == CBNINTR_UE) ? 1844*7c478bd9Sstevel@tonic-gate 1 : 0; 1845*7c478bd9Sstevel@tonic-gate break; 1846*7c478bd9Sstevel@tonic-gate } 1847*7c478bd9Sstevel@tonic-gate 1848*7c478bd9Sstevel@tonic-gate if (flag == ACC_HANDLE && 1849*7c478bd9Sstevel@tonic-gate (region & ecc_err_tbl[i].ecc_region_bits)) { 1850*7c478bd9Sstevel@tonic-gate ecc_err_p->ecc_region = ecc_err_tbl[i].ecc_region; 1851*7c478bd9Sstevel@tonic-gate pci_format_ecc_addr(pci_p->pci_dip, 1852*7c478bd9Sstevel@tonic-gate &ecc_err_p->ecc_err_addr, 1853*7c478bd9Sstevel@tonic-gate ecc_err_p->ecc_region); 1854*7c478bd9Sstevel@tonic-gate } 1855*7c478bd9Sstevel@tonic-gate 1856*7c478bd9Sstevel@tonic-gate /* 1857*7c478bd9Sstevel@tonic-gate * Lookup and fault errant handle 1858*7c478bd9Sstevel@tonic-gate */ 1859*7c478bd9Sstevel@tonic-gate for (j = 0; j < 2; ++j) { 1860*7c478bd9Sstevel@tonic-gate ret = DDI_FM_UNKNOWN; 1861*7c478bd9Sstevel@tonic-gate if (cmn_p->pci_p[j] == NULL) 1862*7c478bd9Sstevel@tonic-gate continue; 1863*7c478bd9Sstevel@tonic-gate ret = pci_handle_lookup(cmn_p->pci_p[j]->pci_dip, 1864*7c478bd9Sstevel@tonic-gate flag, ecc_err_p->ecc_ena, 1865*7c478bd9Sstevel@tonic-gate (void *)&ecc_err_p->ecc_err_addr); 1866*7c478bd9Sstevel@tonic-gate if (ret == DDI_FM_NONFATAL) { 1867*7c478bd9Sstevel@tonic-gate fatal = 0; 1868*7c478bd9Sstevel@tonic-gate break; 1869*7c478bd9Sstevel@tonic-gate } else 1870*7c478bd9Sstevel@tonic-gate fatal++; 1871*7c478bd9Sstevel@tonic-gate } 1872*7c478bd9Sstevel@tonic-gate break; 1873*7c478bd9Sstevel@tonic-gate } 1874*7c478bd9Sstevel@tonic-gate 1875*7c478bd9Sstevel@tonic-gate if (fatal) 1876*7c478bd9Sstevel@tonic-gate ecc_p->flt_panic = 1; 1877*7c478bd9Sstevel@tonic-gate else if (flag != ACC_HANDLE) 1878*7c478bd9Sstevel@tonic-gate ecc_err_p->ecc_pg_ret = 1; 1879*7c478bd9Sstevel@tonic-gate } 1880*7c478bd9Sstevel@tonic-gate 1881*7c478bd9Sstevel@tonic-gate /* 1882*7c478bd9Sstevel@tonic-gate * Tables to define PCI-X Split Completion errors 1883*7c478bd9Sstevel@tonic-gate */ 1884*7c478bd9Sstevel@tonic-gate 1885*7c478bd9Sstevel@tonic-gate pcix_err_msg_rec_t pcix_completer_errs[] = { 1886*7c478bd9Sstevel@tonic-gate {PCIX_CPLT_OUT_OF_RANGE, "pcix", "oor" }, 1887*7c478bd9Sstevel@tonic-gate }; 1888*7c478bd9Sstevel@tonic-gate 1889*7c478bd9Sstevel@tonic-gate pcix_err_tbl_t pcix_split_errs_tbl[] = { 1890*7c478bd9Sstevel@tonic-gate {PCIX_CLASS_CPLT, 1891*7c478bd9Sstevel@tonic-gate sizeof (pcix_completer_errs)/sizeof (pcix_err_msg_rec_t), 1892*7c478bd9Sstevel@tonic-gate pcix_completer_errs }, 1893*7c478bd9Sstevel@tonic-gate }; 1894*7c478bd9Sstevel@tonic-gate 1895*7c478bd9Sstevel@tonic-gate /* 1896*7c478bd9Sstevel@tonic-gate * Tables for the PCI-X error status messages 1897*7c478bd9Sstevel@tonic-gate */ 1898*7c478bd9Sstevel@tonic-gate pcix_err_msg_rec_t pcix_stat_errs[] = { 1899*7c478bd9Sstevel@tonic-gate {XMITS_PCIX_STAT_SC_DSCRD, "pcix", "discard" }, 1900*7c478bd9Sstevel@tonic-gate {XMITS_PCIX_STAT_SC_TTO, "xmits.pbmx", "tato" }, 1901*7c478bd9Sstevel@tonic-gate {XMITS_PCIX_STAT_SMMU, "xmits.pbmx", "stmmu" }, 1902*7c478bd9Sstevel@tonic-gate {XMITS_PCIX_STAT_SDSTAT, "xmits.pbmx", "stdst" }, 1903*7c478bd9Sstevel@tonic-gate {XMITS_PCIX_STAT_CMMU, "xmits.pbmx", "cnmmu" }, 1904*7c478bd9Sstevel@tonic-gate {XMITS_PCIX_STAT_CDSTAT, "xmits.pbmx", "cndst" } 1905*7c478bd9Sstevel@tonic-gate }; 1906*7c478bd9Sstevel@tonic-gate 1907*7c478bd9Sstevel@tonic-gate pcix_err_tbl_t pcix_stat_errs_tbl = 1908*7c478bd9Sstevel@tonic-gate {PCIX_NO_CLASS, 1909*7c478bd9Sstevel@tonic-gate sizeof (pcix_stat_errs)/sizeof (pcix_err_msg_rec_t), 1910*7c478bd9Sstevel@tonic-gate pcix_stat_errs }; 1911*7c478bd9Sstevel@tonic-gate 1912*7c478bd9Sstevel@tonic-gate 1913*7c478bd9Sstevel@tonic-gate /* 1914*7c478bd9Sstevel@tonic-gate * walk thru a table of error messages, printing as appropriate 1915*7c478bd9Sstevel@tonic-gate * 1916*7c478bd9Sstevel@tonic-gate * t - the table of messages to parse 1917*7c478bd9Sstevel@tonic-gate * err - the error to match against 1918*7c478bd9Sstevel@tonic-gate * multi - flag, sometimes multiple error bits may be set/desired 1919*7c478bd9Sstevel@tonic-gate */ 1920*7c478bd9Sstevel@tonic-gate static int 1921*7c478bd9Sstevel@tonic-gate pcix_lookup_err_msgs(dev_info_t *dip, uint64_t ena, pcix_err_tbl_t t, 1922*7c478bd9Sstevel@tonic-gate pbm_errstate_t *pbm_err_p) 1923*7c478bd9Sstevel@tonic-gate { 1924*7c478bd9Sstevel@tonic-gate uint32_t err_bits = pbm_err_p->pbm_err & XMITS_PCIX_MSG_INDEX_MASK; 1925*7c478bd9Sstevel@tonic-gate int nerr = 0; 1926*7c478bd9Sstevel@tonic-gate int j; 1927*7c478bd9Sstevel@tonic-gate char buf[FM_MAX_CLASS]; 1928*7c478bd9Sstevel@tonic-gate 1929*7c478bd9Sstevel@tonic-gate for (j = 0; j < t.err_rec_num; j++) { 1930*7c478bd9Sstevel@tonic-gate uint32_t msg_key = t.err_msg_tbl[j].msg_key; 1931*7c478bd9Sstevel@tonic-gate if (pbm_err_p->pbm_multi ? !(err_bits & msg_key) : err_bits 1932*7c478bd9Sstevel@tonic-gate != msg_key) 1933*7c478bd9Sstevel@tonic-gate continue; 1934*7c478bd9Sstevel@tonic-gate 1935*7c478bd9Sstevel@tonic-gate (void) snprintf(buf, FM_MAX_CLASS, "%s.%s%s", 1936*7c478bd9Sstevel@tonic-gate t.err_msg_tbl[j].msg_class, 1937*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_pri ? "" : PCIX_SECONDARY, 1938*7c478bd9Sstevel@tonic-gate t.err_msg_tbl[j].msg_str); 1939*7c478bd9Sstevel@tonic-gate 1940*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_err_class = buf; 1941*7c478bd9Sstevel@tonic-gate pcix_ereport_post(dip, ena, pbm_err_p); 1942*7c478bd9Sstevel@tonic-gate nerr++; 1943*7c478bd9Sstevel@tonic-gate } 1944*7c478bd9Sstevel@tonic-gate return (nerr ? DDI_FM_FATAL : DDI_FM_OK); 1945*7c478bd9Sstevel@tonic-gate } 1946*7c478bd9Sstevel@tonic-gate 1947*7c478bd9Sstevel@tonic-gate /* 1948*7c478bd9Sstevel@tonic-gate * Decodes primary(bit 27-24) or secondary(bit 15-12) PCI-X split 1949*7c478bd9Sstevel@tonic-gate * completion error message class and index in PBM AFSR. 1950*7c478bd9Sstevel@tonic-gate */ 1951*7c478bd9Sstevel@tonic-gate static void 1952*7c478bd9Sstevel@tonic-gate pcix_log_split_err(dev_info_t *dip, uint64_t ena, pbm_errstate_t *pbm_err_p) 1953*7c478bd9Sstevel@tonic-gate { 1954*7c478bd9Sstevel@tonic-gate uint32_t class = pbm_err_p->pbm_err & XMITS_PCIX_MSG_CLASS_MASK; 1955*7c478bd9Sstevel@tonic-gate uint32_t num_classes = sizeof (pcix_split_errs_tbl) / 1956*7c478bd9Sstevel@tonic-gate sizeof (struct pcix_err_tbl); 1957*7c478bd9Sstevel@tonic-gate int i; 1958*7c478bd9Sstevel@tonic-gate 1959*7c478bd9Sstevel@tonic-gate for (i = 0; i < num_classes; i++) { 1960*7c478bd9Sstevel@tonic-gate if (class == pcix_split_errs_tbl[i].err_class) { 1961*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_multi = PCIX_SINGLE_ERR; 1962*7c478bd9Sstevel@tonic-gate (void) pcix_lookup_err_msgs(dip, ena, 1963*7c478bd9Sstevel@tonic-gate pcix_split_errs_tbl[i], pbm_err_p); 1964*7c478bd9Sstevel@tonic-gate break; 1965*7c478bd9Sstevel@tonic-gate } 1966*7c478bd9Sstevel@tonic-gate } 1967*7c478bd9Sstevel@tonic-gate } 1968*7c478bd9Sstevel@tonic-gate 1969*7c478bd9Sstevel@tonic-gate /* 1970*7c478bd9Sstevel@tonic-gate * Report PBM PCI-X Error Status Register if in PCI-X mode 1971*7c478bd9Sstevel@tonic-gate * 1972*7c478bd9Sstevel@tonic-gate * Once a PCI-X fault tree is constructed, the code below may need to 1973*7c478bd9Sstevel@tonic-gate * change. 1974*7c478bd9Sstevel@tonic-gate */ 1975*7c478bd9Sstevel@tonic-gate static int 1976*7c478bd9Sstevel@tonic-gate pcix_log_pbm(pci_t *pci_p, uint64_t ena, pbm_errstate_t *pbm_err_p) 1977*7c478bd9Sstevel@tonic-gate { 1978*7c478bd9Sstevel@tonic-gate int fatal = 0; 1979*7c478bd9Sstevel@tonic-gate int nonfatal = 0; 1980*7c478bd9Sstevel@tonic-gate uint32_t e; 1981*7c478bd9Sstevel@tonic-gate 1982*7c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&pci_p->pci_common_p->pci_fm_mutex)); 1983*7c478bd9Sstevel@tonic-gate 1984*7c478bd9Sstevel@tonic-gate DEBUG3(DBG_ERR_INTR, pci_p->pci_dip, "pcix_log_pbm: chip_type=%d " 1985*7c478bd9Sstevel@tonic-gate "ctr_stat=%lx afsr = 0x%lx", CHIP_TYPE(pci_p), 1986*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_ctl_stat, pbm_err_p->pbm_afsr); 1987*7c478bd9Sstevel@tonic-gate 1988*7c478bd9Sstevel@tonic-gate if (!(CHIP_TYPE(pci_p) == PCI_CHIP_XMITS) || 1989*7c478bd9Sstevel@tonic-gate !(pbm_err_p->pbm_ctl_stat & XMITS_PCI_CTRL_X_MODE)) 1990*7c478bd9Sstevel@tonic-gate return (DDI_FM_OK); 1991*7c478bd9Sstevel@tonic-gate 1992*7c478bd9Sstevel@tonic-gate if (pbm_err_p->pbm_afsr & XMITS_PCI_X_AFSR_P_SC_ERR) { 1993*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_err = PBM_AFSR_TO_PRISPLIT(pbm_err_p->pbm_afsr); 1994*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_pri = PBM_PRIMARY; 1995*7c478bd9Sstevel@tonic-gate pcix_log_split_err(pci_p->pci_dip, ena, pbm_err_p); 1996*7c478bd9Sstevel@tonic-gate nonfatal++; 1997*7c478bd9Sstevel@tonic-gate } 1998*7c478bd9Sstevel@tonic-gate if (pbm_err_p->pbm_afsr & XMITS_PCI_X_AFSR_S_SC_ERR) { 1999*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_err = PBM_AFSR_TO_PRISPLIT(pbm_err_p->pbm_afsr); 2000*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_pri = PBM_PRIMARY; 2001*7c478bd9Sstevel@tonic-gate pcix_log_split_err(pci_p->pci_dip, ena, pbm_err_p); 2002*7c478bd9Sstevel@tonic-gate nonfatal++; 2003*7c478bd9Sstevel@tonic-gate } 2004*7c478bd9Sstevel@tonic-gate 2005*7c478bd9Sstevel@tonic-gate e = PBM_PCIX_TO_PRIERR(pbm_err_p->pbm_pcix_stat); 2006*7c478bd9Sstevel@tonic-gate if (e) { 2007*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_pri = PBM_PRIMARY; 2008*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_err = e; 2009*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_multi = PCIX_MULTI_ERR; 2010*7c478bd9Sstevel@tonic-gate if (pcix_lookup_err_msgs(pci_p->pci_dip, ena, 2011*7c478bd9Sstevel@tonic-gate pcix_stat_errs_tbl, pbm_err_p) == DDI_FM_FATAL) 2012*7c478bd9Sstevel@tonic-gate fatal++; 2013*7c478bd9Sstevel@tonic-gate else 2014*7c478bd9Sstevel@tonic-gate nonfatal++; 2015*7c478bd9Sstevel@tonic-gate } 2016*7c478bd9Sstevel@tonic-gate 2017*7c478bd9Sstevel@tonic-gate e = PBM_PCIX_TO_SECERR(pbm_err_p->pbm_pcix_stat); 2018*7c478bd9Sstevel@tonic-gate if (e) { 2019*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_pri = PBM_SECONDARY; 2020*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_err = e; 2021*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_multi = PCIX_MULTI_ERR; 2022*7c478bd9Sstevel@tonic-gate if (pcix_lookup_err_msgs(pci_p->pci_dip, ena, 2023*7c478bd9Sstevel@tonic-gate pcix_stat_errs_tbl, pbm_err_p) == DDI_FM_FATAL) 2024*7c478bd9Sstevel@tonic-gate fatal++; 2025*7c478bd9Sstevel@tonic-gate else 2026*7c478bd9Sstevel@tonic-gate nonfatal++; 2027*7c478bd9Sstevel@tonic-gate } 2028*7c478bd9Sstevel@tonic-gate 2029*7c478bd9Sstevel@tonic-gate if (!fatal && !nonfatal) 2030*7c478bd9Sstevel@tonic-gate return (DDI_FM_OK); 2031*7c478bd9Sstevel@tonic-gate else if (fatal) 2032*7c478bd9Sstevel@tonic-gate return (DDI_FM_FATAL); 2033*7c478bd9Sstevel@tonic-gate return (DDI_FM_NONFATAL); 2034*7c478bd9Sstevel@tonic-gate } 2035*7c478bd9Sstevel@tonic-gate 2036*7c478bd9Sstevel@tonic-gate static pbm_fm_err_t pbm_err_tbl[] = { 2037*7c478bd9Sstevel@tonic-gate PCI_MA, SCHIZO_PCI_AFSR_E_MA, PBM_PRIMARY, 2038*7c478bd9Sstevel@tonic-gate FM_LOG_PCI, PCI_TARG_MA, 2039*7c478bd9Sstevel@tonic-gate 2040*7c478bd9Sstevel@tonic-gate PCI_SEC_MA, SCHIZO_PCI_AFSR_E_MA, PBM_SECONDARY, 2041*7c478bd9Sstevel@tonic-gate FM_LOG_PBM, NULL, 2042*7c478bd9Sstevel@tonic-gate 2043*7c478bd9Sstevel@tonic-gate PCI_REC_TA, SCHIZO_PCI_AFSR_E_TA, PBM_PRIMARY, 2044*7c478bd9Sstevel@tonic-gate FM_LOG_PCI, PCI_TARG_REC_TA, 2045*7c478bd9Sstevel@tonic-gate 2046*7c478bd9Sstevel@tonic-gate PCI_SEC_REC_TA, SCHIZO_PCI_AFSR_E_TA, PBM_SECONDARY, 2047*7c478bd9Sstevel@tonic-gate FM_LOG_PBM, NULL, 2048*7c478bd9Sstevel@tonic-gate 2049*7c478bd9Sstevel@tonic-gate PCI_PBM_RETRY, SCHIZO_PCI_AFSR_E_RTRY, PBM_PRIMARY, 2050*7c478bd9Sstevel@tonic-gate FM_LOG_PBM, PCI_PBM_TARG_RETRY, 2051*7c478bd9Sstevel@tonic-gate 2052*7c478bd9Sstevel@tonic-gate PCI_SEC_PBM_RETRY, SCHIZO_PCI_AFSR_E_RTRY, PBM_SECONDARY, 2053*7c478bd9Sstevel@tonic-gate FM_LOG_PBM, NULL, 2054*7c478bd9Sstevel@tonic-gate 2055*7c478bd9Sstevel@tonic-gate PCI_MDPE, SCHIZO_PCI_AFSR_E_PERR, PBM_PRIMARY, 2056*7c478bd9Sstevel@tonic-gate FM_LOG_PCI, PCI_TARG_MDPE, 2057*7c478bd9Sstevel@tonic-gate 2058*7c478bd9Sstevel@tonic-gate PCI_SEC_MDPE, SCHIZO_PCI_AFSR_E_PERR, PBM_SECONDARY, 2059*7c478bd9Sstevel@tonic-gate FM_LOG_PBM, NULL, 2060*7c478bd9Sstevel@tonic-gate 2061*7c478bd9Sstevel@tonic-gate PCI_PBM_TTO, SCHIZO_PCI_AFSR_E_TTO, PBM_PRIMARY, 2062*7c478bd9Sstevel@tonic-gate FM_LOG_PBM, PCI_PBM_TARG_TTO, 2063*7c478bd9Sstevel@tonic-gate 2064*7c478bd9Sstevel@tonic-gate PCI_SEC_PBM_TTO, SCHIZO_PCI_AFSR_E_TTO, PBM_SECONDARY, 2065*7c478bd9Sstevel@tonic-gate FM_LOG_PBM, NULL, 2066*7c478bd9Sstevel@tonic-gate 2067*7c478bd9Sstevel@tonic-gate PCI_SCH_BUS_UNUSABLE_ERR, SCHIZO_PCI_AFSR_E_UNUSABLE, PBM_PRIMARY, 2068*7c478bd9Sstevel@tonic-gate FM_LOG_PBM, NULL, 2069*7c478bd9Sstevel@tonic-gate 2070*7c478bd9Sstevel@tonic-gate PCI_SEC_SCH_BUS_UNUSABLE_ERR, SCHIZO_PCI_AFSR_E_UNUSABLE, PBM_SECONDARY, 2071*7c478bd9Sstevel@tonic-gate FM_LOG_PBM, NULL, 2072*7c478bd9Sstevel@tonic-gate 2073*7c478bd9Sstevel@tonic-gate NULL, NULL, NULL, 2074*7c478bd9Sstevel@tonic-gate NULL, NULL, 2075*7c478bd9Sstevel@tonic-gate }; 2076*7c478bd9Sstevel@tonic-gate 2077*7c478bd9Sstevel@tonic-gate 2078*7c478bd9Sstevel@tonic-gate /* 2079*7c478bd9Sstevel@tonic-gate * pci_pbm_classify, called by pbm_afsr_report to classify piow afsr. 2080*7c478bd9Sstevel@tonic-gate */ 2081*7c478bd9Sstevel@tonic-gate int 2082*7c478bd9Sstevel@tonic-gate pci_pbm_classify(pbm_errstate_t *pbm_err_p) 2083*7c478bd9Sstevel@tonic-gate { 2084*7c478bd9Sstevel@tonic-gate uint32_t err; 2085*7c478bd9Sstevel@tonic-gate int nerr = 0; 2086*7c478bd9Sstevel@tonic-gate int i; 2087*7c478bd9Sstevel@tonic-gate 2088*7c478bd9Sstevel@tonic-gate err = pbm_err_p->pbm_pri ? PBM_AFSR_TO_PRIERR(pbm_err_p->pbm_afsr): 2089*7c478bd9Sstevel@tonic-gate PBM_AFSR_TO_SECERR(pbm_err_p->pbm_afsr); 2090*7c478bd9Sstevel@tonic-gate 2091*7c478bd9Sstevel@tonic-gate for (i = 0; pbm_err_tbl[i].pbm_err_class != NULL; i++) { 2092*7c478bd9Sstevel@tonic-gate if ((err & pbm_err_tbl[i].pbm_reg_bit) && 2093*7c478bd9Sstevel@tonic-gate (pbm_err_p->pbm_pri == pbm_err_tbl[i].pbm_pri)) { 2094*7c478bd9Sstevel@tonic-gate if (pbm_err_tbl[i].pbm_flag == FM_LOG_PCI) 2095*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_pci.pci_err_class = 2096*7c478bd9Sstevel@tonic-gate pbm_err_tbl[i].pbm_err_class; 2097*7c478bd9Sstevel@tonic-gate else 2098*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_err_class = 2099*7c478bd9Sstevel@tonic-gate pbm_err_tbl[i].pbm_err_class; 2100*7c478bd9Sstevel@tonic-gate 2101*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_terr_class = 2102*7c478bd9Sstevel@tonic-gate pbm_err_tbl[i].pbm_terr_class; 2103*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_log = pbm_err_tbl[i].pbm_flag; 2104*7c478bd9Sstevel@tonic-gate nerr++; 2105*7c478bd9Sstevel@tonic-gate break; 2106*7c478bd9Sstevel@tonic-gate } 2107*7c478bd9Sstevel@tonic-gate } 2108*7c478bd9Sstevel@tonic-gate 2109*7c478bd9Sstevel@tonic-gate return (nerr); 2110*7c478bd9Sstevel@tonic-gate } 2111*7c478bd9Sstevel@tonic-gate 2112*7c478bd9Sstevel@tonic-gate /* 2113*7c478bd9Sstevel@tonic-gate * Function used to handle and log IOMMU errors. Called by pci_pbm_err_handler, 2114*7c478bd9Sstevel@tonic-gate * with pci_fm_mutex held. 2115*7c478bd9Sstevel@tonic-gate */ 2116*7c478bd9Sstevel@tonic-gate static int 2117*7c478bd9Sstevel@tonic-gate iommu_err_handler(dev_info_t *dip, uint64_t ena, pbm_errstate_t *pbm_err_p) 2118*7c478bd9Sstevel@tonic-gate { 2119*7c478bd9Sstevel@tonic-gate pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 2120*7c478bd9Sstevel@tonic-gate iommu_t *iommu_p = pci_p->pci_iommu_p; 2121*7c478bd9Sstevel@tonic-gate ecc_t *ecc_p = pci_p->pci_ecc_p; 2122*7c478bd9Sstevel@tonic-gate uint64_t stat; 2123*7c478bd9Sstevel@tonic-gate ushort_t ta_signalled; 2124*7c478bd9Sstevel@tonic-gate int err = 0; 2125*7c478bd9Sstevel@tonic-gate int fatal = 0; 2126*7c478bd9Sstevel@tonic-gate int nonfatal = 0; 2127*7c478bd9Sstevel@tonic-gate int ret; 2128*7c478bd9Sstevel@tonic-gate 2129*7c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&ecc_p->ecc_pci_cmn_p->pci_fm_mutex)); 2130*7c478bd9Sstevel@tonic-gate if (!((stat = *iommu_p->iommu_ctrl_reg) & TOMATILLO_IOMMU_ERR)) { 2131*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_err_class = PCI_SCH_MMU_ERR; 2132*7c478bd9Sstevel@tonic-gate iommu_ereport_post(dip, ena, pbm_err_p); 2133*7c478bd9Sstevel@tonic-gate return (DDI_FM_NONFATAL); 2134*7c478bd9Sstevel@tonic-gate } 2135*7c478bd9Sstevel@tonic-gate 2136*7c478bd9Sstevel@tonic-gate /* 2137*7c478bd9Sstevel@tonic-gate * Need to make sure a Target Abort was signalled to the device if 2138*7c478bd9Sstevel@tonic-gate * we have any hope of recovering. Tomatillo does not send a TA for 2139*7c478bd9Sstevel@tonic-gate * DMA Writes that result in a Translation Error, thus fooling the 2140*7c478bd9Sstevel@tonic-gate * device into believing everything is as it expects. Ignorance 2141*7c478bd9Sstevel@tonic-gate * is bliss, but knowledge is power. 2142*7c478bd9Sstevel@tonic-gate */ 2143*7c478bd9Sstevel@tonic-gate ta_signalled = pbm_err_p->pbm_pci.pci_cfg_stat & 2144*7c478bd9Sstevel@tonic-gate PCI_STAT_S_TARG_AB; 2145*7c478bd9Sstevel@tonic-gate 2146*7c478bd9Sstevel@tonic-gate if (stat & TOMATILLO_IOMMU_ERR_ILLTSBTBW) { 2147*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_err_class = PCI_TOM_MMU_BAD_TSBTBW; 2148*7c478bd9Sstevel@tonic-gate err = 1; 2149*7c478bd9Sstevel@tonic-gate iommu_ereport_post(dip, ena, pbm_err_p); 2150*7c478bd9Sstevel@tonic-gate if (!ta_signalled) 2151*7c478bd9Sstevel@tonic-gate fatal++; 2152*7c478bd9Sstevel@tonic-gate else 2153*7c478bd9Sstevel@tonic-gate nonfatal++; 2154*7c478bd9Sstevel@tonic-gate } 2155*7c478bd9Sstevel@tonic-gate 2156*7c478bd9Sstevel@tonic-gate if (stat & TOMATILLO_IOMMU_ERR_BAD_VA) { 2157*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_err_class = PCI_TOM_MMU_BAD_VA; 2158*7c478bd9Sstevel@tonic-gate err = 1; 2159*7c478bd9Sstevel@tonic-gate iommu_ereport_post(dip, ena, pbm_err_p); 2160*7c478bd9Sstevel@tonic-gate if (!ta_signalled) 2161*7c478bd9Sstevel@tonic-gate fatal++; 2162*7c478bd9Sstevel@tonic-gate else 2163*7c478bd9Sstevel@tonic-gate nonfatal++; 2164*7c478bd9Sstevel@tonic-gate } 2165*7c478bd9Sstevel@tonic-gate 2166*7c478bd9Sstevel@tonic-gate if (!err) { 2167*7c478bd9Sstevel@tonic-gate stat = ((stat & TOMATILLO_IOMMU_ERRSTS) >> 2168*7c478bd9Sstevel@tonic-gate TOMATILLO_IOMMU_ERRSTS_SHIFT); 2169*7c478bd9Sstevel@tonic-gate switch (stat) { 2170*7c478bd9Sstevel@tonic-gate case TOMATILLO_IOMMU_PROTECTION_ERR: 2171*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_err_class = PCI_TOM_MMU_PROT_ERR; 2172*7c478bd9Sstevel@tonic-gate iommu_ereport_post(dip, ena, pbm_err_p); 2173*7c478bd9Sstevel@tonic-gate fatal++; 2174*7c478bd9Sstevel@tonic-gate break; 2175*7c478bd9Sstevel@tonic-gate case TOMATILLO_IOMMU_INVALID_ERR: 2176*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_err_class = PCI_TOM_MMU_INVAL_ERR; 2177*7c478bd9Sstevel@tonic-gate /* 2178*7c478bd9Sstevel@tonic-gate * Fault the address in iommu_tfar 2179*7c478bd9Sstevel@tonic-gate * register to inform target driver of error 2180*7c478bd9Sstevel@tonic-gate */ 2181*7c478bd9Sstevel@tonic-gate ret = pci_handle_lookup(pci_p->pci_dip, DMA_HANDLE, 2182*7c478bd9Sstevel@tonic-gate ena, (void *)&pbm_err_p->pbm_iommu.iommu_tfar); 2183*7c478bd9Sstevel@tonic-gate 2184*7c478bd9Sstevel@tonic-gate if (ret == DDI_FM_NONFATAL) 2185*7c478bd9Sstevel@tonic-gate if (ta_signalled) 2186*7c478bd9Sstevel@tonic-gate nonfatal++; 2187*7c478bd9Sstevel@tonic-gate else 2188*7c478bd9Sstevel@tonic-gate fatal++; 2189*7c478bd9Sstevel@tonic-gate else 2190*7c478bd9Sstevel@tonic-gate fatal++; 2191*7c478bd9Sstevel@tonic-gate iommu_ereport_post(dip, ena, pbm_err_p); 2192*7c478bd9Sstevel@tonic-gate break; 2193*7c478bd9Sstevel@tonic-gate case TOMATILLO_IOMMU_TIMEOUT_ERR: 2194*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_err_class = PCI_TOM_MMU_TO_ERR; 2195*7c478bd9Sstevel@tonic-gate fatal++; 2196*7c478bd9Sstevel@tonic-gate iommu_ereport_post(dip, ena, pbm_err_p); 2197*7c478bd9Sstevel@tonic-gate break; 2198*7c478bd9Sstevel@tonic-gate case TOMATILLO_IOMMU_ECC_ERR: 2199*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_err_class = PCI_TOM_MMU_UE; 2200*7c478bd9Sstevel@tonic-gate iommu_ereport_post(dip, ena, pbm_err_p); 2201*7c478bd9Sstevel@tonic-gate break; 2202*7c478bd9Sstevel@tonic-gate } 2203*7c478bd9Sstevel@tonic-gate } 2204*7c478bd9Sstevel@tonic-gate 2205*7c478bd9Sstevel@tonic-gate if (fatal) 2206*7c478bd9Sstevel@tonic-gate return (DDI_FM_FATAL); 2207*7c478bd9Sstevel@tonic-gate else if (nonfatal) 2208*7c478bd9Sstevel@tonic-gate return (DDI_FM_NONFATAL); 2209*7c478bd9Sstevel@tonic-gate 2210*7c478bd9Sstevel@tonic-gate return (DDI_FM_OK); 2211*7c478bd9Sstevel@tonic-gate } 2212*7c478bd9Sstevel@tonic-gate 2213*7c478bd9Sstevel@tonic-gate int 2214*7c478bd9Sstevel@tonic-gate pci_check_error(pci_t *pci_p) 2215*7c478bd9Sstevel@tonic-gate { 2216*7c478bd9Sstevel@tonic-gate pbm_t *pbm_p = pci_p->pci_pbm_p; 2217*7c478bd9Sstevel@tonic-gate uint16_t pci_cfg_stat; 2218*7c478bd9Sstevel@tonic-gate uint64_t pbm_ctl_stat, pbm_afsr, pbm_pcix_stat; 2219*7c478bd9Sstevel@tonic-gate caddr_t a = pci_p->pci_address[0]; 2220*7c478bd9Sstevel@tonic-gate uint64_t *pbm_pcix_stat_reg; 2221*7c478bd9Sstevel@tonic-gate 2222*7c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&pci_p->pci_common_p->pci_fm_mutex)); 2223*7c478bd9Sstevel@tonic-gate 2224*7c478bd9Sstevel@tonic-gate pci_cfg_stat = pbm_p->pbm_config_header->ch_status_reg; 2225*7c478bd9Sstevel@tonic-gate pbm_ctl_stat = *pbm_p->pbm_ctrl_reg; 2226*7c478bd9Sstevel@tonic-gate pbm_afsr = *pbm_p->pbm_async_flt_status_reg; 2227*7c478bd9Sstevel@tonic-gate 2228*7c478bd9Sstevel@tonic-gate if ((pci_cfg_stat & (PCI_STAT_S_PERROR | PCI_STAT_S_TARG_AB | 2229*7c478bd9Sstevel@tonic-gate PCI_STAT_R_TARG_AB | PCI_STAT_R_MAST_AB | 2230*7c478bd9Sstevel@tonic-gate PCI_STAT_S_SYSERR | PCI_STAT_PERROR)) || 2231*7c478bd9Sstevel@tonic-gate (pbm_ctl_stat & (SCHIZO_PCI_CTRL_BUS_UNUSABLE | 2232*7c478bd9Sstevel@tonic-gate TOMATILLO_PCI_CTRL_PCI_DTO_ERR | 2233*7c478bd9Sstevel@tonic-gate SCHIZO_PCI_CTRL_PCI_TTO_ERR | 2234*7c478bd9Sstevel@tonic-gate SCHIZO_PCI_CTRL_PCI_RTRY_ERR | 2235*7c478bd9Sstevel@tonic-gate SCHIZO_PCI_CTRL_PCI_MMU_ERR | 2236*7c478bd9Sstevel@tonic-gate COMMON_PCI_CTRL_SBH_ERR | 2237*7c478bd9Sstevel@tonic-gate COMMON_PCI_CTRL_SERR)) || 2238*7c478bd9Sstevel@tonic-gate (PBM_AFSR_TO_PRIERR(pbm_afsr))) 2239*7c478bd9Sstevel@tonic-gate return (1); 2240*7c478bd9Sstevel@tonic-gate 2241*7c478bd9Sstevel@tonic-gate if ((CHIP_TYPE(pci_p) == PCI_CHIP_XMITS) && 2242*7c478bd9Sstevel@tonic-gate (pbm_ctl_stat & XMITS_PCI_CTRL_X_MODE)) { 2243*7c478bd9Sstevel@tonic-gate 2244*7c478bd9Sstevel@tonic-gate pbm_pcix_stat_reg = (uint64_t *)(a + 2245*7c478bd9Sstevel@tonic-gate XMITS_PCI_X_ERROR_STATUS_REG_OFFSET); 2246*7c478bd9Sstevel@tonic-gate 2247*7c478bd9Sstevel@tonic-gate pbm_pcix_stat = *pbm_pcix_stat_reg; 2248*7c478bd9Sstevel@tonic-gate 2249*7c478bd9Sstevel@tonic-gate if (PBM_PCIX_TO_PRIERR(pbm_pcix_stat)) 2250*7c478bd9Sstevel@tonic-gate return (1); 2251*7c478bd9Sstevel@tonic-gate 2252*7c478bd9Sstevel@tonic-gate if (pbm_pcix_stat & XMITS_PCIX_STAT_PERR_RECOV_INT) 2253*7c478bd9Sstevel@tonic-gate return (1); 2254*7c478bd9Sstevel@tonic-gate } 2255*7c478bd9Sstevel@tonic-gate 2256*7c478bd9Sstevel@tonic-gate return (0); 2257*7c478bd9Sstevel@tonic-gate 2258*7c478bd9Sstevel@tonic-gate } 2259*7c478bd9Sstevel@tonic-gate 2260*7c478bd9Sstevel@tonic-gate static pbm_fm_err_t pci_pbm_err_tbl[] = { 2261*7c478bd9Sstevel@tonic-gate PCI_PBM_RETRY, SCHIZO_PCI_CTRL_PCI_RTRY_ERR, 2262*7c478bd9Sstevel@tonic-gate NULL, PBM_NONFATAL, PCI_PBM_TARG_RETRY, 2263*7c478bd9Sstevel@tonic-gate 2264*7c478bd9Sstevel@tonic-gate PCI_PBM_TTO, SCHIZO_PCI_CTRL_PCI_TTO_ERR, 2265*7c478bd9Sstevel@tonic-gate NULL, PBM_NONFATAL, PCI_PBM_TARG_TTO, 2266*7c478bd9Sstevel@tonic-gate 2267*7c478bd9Sstevel@tonic-gate PCI_SCH_BUS_UNUSABLE_ERR, SCHIZO_PCI_CTRL_BUS_UNUSABLE, 2268*7c478bd9Sstevel@tonic-gate NULL, PBM_NONFATAL, NULL, 2269*7c478bd9Sstevel@tonic-gate 2270*7c478bd9Sstevel@tonic-gate NULL, NULL, 2271*7c478bd9Sstevel@tonic-gate NULL, NULL, NULL 2272*7c478bd9Sstevel@tonic-gate }; 2273*7c478bd9Sstevel@tonic-gate 2274*7c478bd9Sstevel@tonic-gate /* 2275*7c478bd9Sstevel@tonic-gate * Function used to log all PCI/PBM/IOMMU errors found in the system. 2276*7c478bd9Sstevel@tonic-gate * It is called by the pbm_error_intr as well as the pci_err_callback(trap 2277*7c478bd9Sstevel@tonic-gate * callback). To protect access we hold the pci_fm_mutex when calling 2278*7c478bd9Sstevel@tonic-gate * this function. 2279*7c478bd9Sstevel@tonic-gate */ 2280*7c478bd9Sstevel@tonic-gate int 2281*7c478bd9Sstevel@tonic-gate pci_pbm_err_handler(dev_info_t *dip, ddi_fm_error_t *derr, 2282*7c478bd9Sstevel@tonic-gate const void *impl_data, int caller) 2283*7c478bd9Sstevel@tonic-gate { 2284*7c478bd9Sstevel@tonic-gate int fatal = 0; 2285*7c478bd9Sstevel@tonic-gate int nonfatal = 0; 2286*7c478bd9Sstevel@tonic-gate int unknown = 0; 2287*7c478bd9Sstevel@tonic-gate int rserr = 0; 2288*7c478bd9Sstevel@tonic-gate uint32_t prierr, secerr; 2289*7c478bd9Sstevel@tonic-gate pbm_errstate_t pbm_err; 2290*7c478bd9Sstevel@tonic-gate char buf[FM_MAX_CLASS]; 2291*7c478bd9Sstevel@tonic-gate pci_t *pci_p = (pci_t *)impl_data; 2292*7c478bd9Sstevel@tonic-gate pbm_t *pbm_p = pci_p->pci_pbm_p; 2293*7c478bd9Sstevel@tonic-gate pci_target_err_t tgt_err; 2294*7c478bd9Sstevel@tonic-gate int i, ret = 0; 2295*7c478bd9Sstevel@tonic-gate 2296*7c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&pci_p->pci_common_p->pci_fm_mutex)); 2297*7c478bd9Sstevel@tonic-gate pci_pbm_errstate_get(pci_p, &pbm_err); 2298*7c478bd9Sstevel@tonic-gate 2299*7c478bd9Sstevel@tonic-gate derr->fme_ena = derr->fme_ena ? derr->fme_ena : 2300*7c478bd9Sstevel@tonic-gate fm_ena_generate(0, FM_ENA_FMT1); 2301*7c478bd9Sstevel@tonic-gate 2302*7c478bd9Sstevel@tonic-gate prierr = PBM_AFSR_TO_PRIERR(pbm_err.pbm_afsr); 2303*7c478bd9Sstevel@tonic-gate secerr = PBM_AFSR_TO_SECERR(pbm_err.pbm_afsr); 2304*7c478bd9Sstevel@tonic-gate 2305*7c478bd9Sstevel@tonic-gate if (derr->fme_flag == DDI_FM_ERR_EXPECTED) { 2306*7c478bd9Sstevel@tonic-gate if (caller == PCI_TRAP_CALL) { 2307*7c478bd9Sstevel@tonic-gate /* 2308*7c478bd9Sstevel@tonic-gate * For ddi_caut_get treat all events as nonfatal. 2309*7c478bd9Sstevel@tonic-gate * The trampoline will set err_ena = 0, err_status = 2310*7c478bd9Sstevel@tonic-gate * NONFATAL. We only really call this function so that 2311*7c478bd9Sstevel@tonic-gate * pci_clear_error() and ndi_fm_handler_dispatch() will 2312*7c478bd9Sstevel@tonic-gate * get called. 2313*7c478bd9Sstevel@tonic-gate */ 2314*7c478bd9Sstevel@tonic-gate derr->fme_status = DDI_FM_NONFATAL; 2315*7c478bd9Sstevel@tonic-gate nonfatal++; 2316*7c478bd9Sstevel@tonic-gate goto done; 2317*7c478bd9Sstevel@tonic-gate } else { 2318*7c478bd9Sstevel@tonic-gate /* 2319*7c478bd9Sstevel@tonic-gate * For ddi_caut_put treat all events as nonfatal. Here 2320*7c478bd9Sstevel@tonic-gate * we have the handle and can call ndi_fm_acc_err_set(). 2321*7c478bd9Sstevel@tonic-gate */ 2322*7c478bd9Sstevel@tonic-gate derr->fme_status = DDI_FM_NONFATAL; 2323*7c478bd9Sstevel@tonic-gate ndi_fm_acc_err_set(pbm_p->pbm_excl_handle, derr); 2324*7c478bd9Sstevel@tonic-gate nonfatal++; 2325*7c478bd9Sstevel@tonic-gate goto done; 2326*7c478bd9Sstevel@tonic-gate } 2327*7c478bd9Sstevel@tonic-gate } else if (derr->fme_flag == DDI_FM_ERR_PEEK) { 2328*7c478bd9Sstevel@tonic-gate /* 2329*7c478bd9Sstevel@tonic-gate * For ddi_peek treat all events as nonfatal. We only 2330*7c478bd9Sstevel@tonic-gate * really call this function so that pci_clear_error() 2331*7c478bd9Sstevel@tonic-gate * and ndi_fm_handler_dispatch() will get called. 2332*7c478bd9Sstevel@tonic-gate */ 2333*7c478bd9Sstevel@tonic-gate nonfatal++; 2334*7c478bd9Sstevel@tonic-gate goto done; 2335*7c478bd9Sstevel@tonic-gate } else if (derr->fme_flag == DDI_FM_ERR_POKE) { 2336*7c478bd9Sstevel@tonic-gate /* 2337*7c478bd9Sstevel@tonic-gate * For ddi_poke we can treat as nonfatal if the 2338*7c478bd9Sstevel@tonic-gate * following conditions are met : 2339*7c478bd9Sstevel@tonic-gate * 1. Make sure only primary error is MA/TA 2340*7c478bd9Sstevel@tonic-gate * 2. Make sure no secondary error bits set 2341*7c478bd9Sstevel@tonic-gate * 3. check pci config header stat reg to see MA/TA is 2342*7c478bd9Sstevel@tonic-gate * logged. We cannot verify only MA/TA is recorded 2343*7c478bd9Sstevel@tonic-gate * since it gets much more complicated when a 2344*7c478bd9Sstevel@tonic-gate * PCI-to-PCI bridge is present. 2345*7c478bd9Sstevel@tonic-gate */ 2346*7c478bd9Sstevel@tonic-gate if ((prierr == SCHIZO_PCI_AFSR_E_MA) && !secerr && 2347*7c478bd9Sstevel@tonic-gate (pbm_err.pbm_pci.pci_cfg_stat & PCI_STAT_R_MAST_AB)) { 2348*7c478bd9Sstevel@tonic-gate nonfatal++; 2349*7c478bd9Sstevel@tonic-gate goto done; 2350*7c478bd9Sstevel@tonic-gate } else if ((*pbm_p->pbm_ctrl_reg & XMITS_PCI_CTRL_X_MODE) && 2351*7c478bd9Sstevel@tonic-gate pcix_ma_behind_bridge(&pbm_err)) { 2352*7c478bd9Sstevel@tonic-gate /* 2353*7c478bd9Sstevel@tonic-gate * MAs behind a PCI-X bridge get sent back to 2354*7c478bd9Sstevel@tonic-gate * the host as a Split Completion Error Message. 2355*7c478bd9Sstevel@tonic-gate * We handle this the same as the above check. 2356*7c478bd9Sstevel@tonic-gate */ 2357*7c478bd9Sstevel@tonic-gate nonfatal++; 2358*7c478bd9Sstevel@tonic-gate goto done; 2359*7c478bd9Sstevel@tonic-gate } 2360*7c478bd9Sstevel@tonic-gate if ((prierr == SCHIZO_PCI_AFSR_E_TA) && !secerr && 2361*7c478bd9Sstevel@tonic-gate (pbm_err.pbm_pci.pci_cfg_stat & PCI_STAT_R_TARG_AB)) { 2362*7c478bd9Sstevel@tonic-gate nonfatal++; 2363*7c478bd9Sstevel@tonic-gate goto done; 2364*7c478bd9Sstevel@tonic-gate } 2365*7c478bd9Sstevel@tonic-gate } 2366*7c478bd9Sstevel@tonic-gate 2367*7c478bd9Sstevel@tonic-gate DEBUG2(DBG_ERR_INTR, dip, "pci_pbm_err_handler: prierr=0x%x " 2368*7c478bd9Sstevel@tonic-gate "secerr=0x%x", prierr, secerr); 2369*7c478bd9Sstevel@tonic-gate 2370*7c478bd9Sstevel@tonic-gate if (prierr || secerr) { 2371*7c478bd9Sstevel@tonic-gate ret = pbm_afsr_report(dip, derr->fme_ena, &pbm_err); 2372*7c478bd9Sstevel@tonic-gate if (ret == DDI_FM_FATAL) 2373*7c478bd9Sstevel@tonic-gate fatal++; 2374*7c478bd9Sstevel@tonic-gate else 2375*7c478bd9Sstevel@tonic-gate nonfatal++; 2376*7c478bd9Sstevel@tonic-gate } 2377*7c478bd9Sstevel@tonic-gate if ((ret = pcix_log_pbm(pci_p, derr->fme_ena, &pbm_err)) 2378*7c478bd9Sstevel@tonic-gate == DDI_FM_FATAL) 2379*7c478bd9Sstevel@tonic-gate fatal++; 2380*7c478bd9Sstevel@tonic-gate else if (ret == DDI_FM_NONFATAL) 2381*7c478bd9Sstevel@tonic-gate nonfatal++; 2382*7c478bd9Sstevel@tonic-gate 2383*7c478bd9Sstevel@tonic-gate if ((ret = pci_cfg_report(dip, derr, &pbm_err.pbm_pci, caller, prierr)) 2384*7c478bd9Sstevel@tonic-gate == DDI_FM_FATAL) 2385*7c478bd9Sstevel@tonic-gate fatal++; 2386*7c478bd9Sstevel@tonic-gate else if (ret == DDI_FM_NONFATAL) 2387*7c478bd9Sstevel@tonic-gate nonfatal++; 2388*7c478bd9Sstevel@tonic-gate 2389*7c478bd9Sstevel@tonic-gate for (i = 0; pci_pbm_err_tbl[i].pbm_err_class != NULL; i++) { 2390*7c478bd9Sstevel@tonic-gate if ((pbm_err.pbm_ctl_stat & pci_pbm_err_tbl[i].pbm_reg_bit) && 2391*7c478bd9Sstevel@tonic-gate !prierr) { 2392*7c478bd9Sstevel@tonic-gate pbm_err.pbm_err_class = 2393*7c478bd9Sstevel@tonic-gate pci_pbm_err_tbl[i].pbm_err_class; 2394*7c478bd9Sstevel@tonic-gate pbm_ereport_post(dip, derr->fme_ena, &pbm_err); 2395*7c478bd9Sstevel@tonic-gate if (pci_pbm_err_tbl[i].pbm_flag) 2396*7c478bd9Sstevel@tonic-gate fatal++; 2397*7c478bd9Sstevel@tonic-gate else 2398*7c478bd9Sstevel@tonic-gate nonfatal++; 2399*7c478bd9Sstevel@tonic-gate if (caller == PCI_TRAP_CALL && 2400*7c478bd9Sstevel@tonic-gate pci_pbm_err_tbl[i].pbm_terr_class) { 2401*7c478bd9Sstevel@tonic-gate tgt_err.tgt_err_ena = derr->fme_ena; 2402*7c478bd9Sstevel@tonic-gate tgt_err.tgt_err_class = 2403*7c478bd9Sstevel@tonic-gate pci_pbm_err_tbl[i].pbm_terr_class; 2404*7c478bd9Sstevel@tonic-gate tgt_err.tgt_bridge_type = 2405*7c478bd9Sstevel@tonic-gate pbm_err.pbm_bridge_type; 2406*7c478bd9Sstevel@tonic-gate tgt_err.tgt_err_addr = 2407*7c478bd9Sstevel@tonic-gate (uint64_t)derr->fme_bus_specific; 2408*7c478bd9Sstevel@tonic-gate errorq_dispatch(pci_target_queue, 2409*7c478bd9Sstevel@tonic-gate (void *)&tgt_err, sizeof (pci_target_err_t), 2410*7c478bd9Sstevel@tonic-gate ERRORQ_ASYNC); 2411*7c478bd9Sstevel@tonic-gate } 2412*7c478bd9Sstevel@tonic-gate } 2413*7c478bd9Sstevel@tonic-gate } 2414*7c478bd9Sstevel@tonic-gate 2415*7c478bd9Sstevel@tonic-gate if ((pbm_err.pbm_ctl_stat & COMMON_PCI_CTRL_SBH_ERR) && 2416*7c478bd9Sstevel@tonic-gate (CHIP_TYPE(pci_p) != PCI_CHIP_TOMATILLO)) { 2417*7c478bd9Sstevel@tonic-gate pbm_err.pbm_err_class = PCI_SCH_SBH; 2418*7c478bd9Sstevel@tonic-gate pbm_ereport_post(dip, derr->fme_ena, &pbm_err); 2419*7c478bd9Sstevel@tonic-gate if (pci_panic_on_sbh_errors) 2420*7c478bd9Sstevel@tonic-gate fatal++; 2421*7c478bd9Sstevel@tonic-gate else 2422*7c478bd9Sstevel@tonic-gate nonfatal++; 2423*7c478bd9Sstevel@tonic-gate } 2424*7c478bd9Sstevel@tonic-gate 2425*7c478bd9Sstevel@tonic-gate /* 2426*7c478bd9Sstevel@tonic-gate * PBM Received System Error - During any transaction, or 2427*7c478bd9Sstevel@tonic-gate * at any point on the bus, some device may detect a critical 2428*7c478bd9Sstevel@tonic-gate * error and signal a system error to the system. 2429*7c478bd9Sstevel@tonic-gate */ 2430*7c478bd9Sstevel@tonic-gate if (pbm_err.pbm_ctl_stat & COMMON_PCI_CTRL_SERR) { 2431*7c478bd9Sstevel@tonic-gate /* 2432*7c478bd9Sstevel@tonic-gate * may be expected (master abort from pci-pci bridge during 2433*7c478bd9Sstevel@tonic-gate * poke will generate SERR) 2434*7c478bd9Sstevel@tonic-gate */ 2435*7c478bd9Sstevel@tonic-gate if (derr->fme_flag != DDI_FM_ERR_POKE) { 2436*7c478bd9Sstevel@tonic-gate DEBUG1(DBG_ERR_INTR, dip, "pci_pbm_err_handler: " 2437*7c478bd9Sstevel@tonic-gate "ereport_post: %s", buf); 2438*7c478bd9Sstevel@tonic-gate (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", 2439*7c478bd9Sstevel@tonic-gate PCI_ERROR_SUBCLASS, PCI_REC_SERR); 2440*7c478bd9Sstevel@tonic-gate ddi_fm_ereport_post(dip, buf, derr->fme_ena, 2441*7c478bd9Sstevel@tonic-gate DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2442*7c478bd9Sstevel@tonic-gate PCI_CONFIG_STATUS, DATA_TYPE_UINT16, 2443*7c478bd9Sstevel@tonic-gate pbm_err.pbm_pci.pci_cfg_stat, PCI_CONFIG_COMMAND, 2444*7c478bd9Sstevel@tonic-gate DATA_TYPE_UINT16, pbm_err.pbm_pci.pci_cfg_comm, 2445*7c478bd9Sstevel@tonic-gate PCI_PA, DATA_TYPE_UINT64, (uint64_t)0, NULL); 2446*7c478bd9Sstevel@tonic-gate } 2447*7c478bd9Sstevel@tonic-gate rserr++; 2448*7c478bd9Sstevel@tonic-gate } 2449*7c478bd9Sstevel@tonic-gate 2450*7c478bd9Sstevel@tonic-gate /* 2451*7c478bd9Sstevel@tonic-gate * PCI Retry Timeout - Device fails to retry deferred 2452*7c478bd9Sstevel@tonic-gate * transaction within timeout. Only Tomatillo 2453*7c478bd9Sstevel@tonic-gate */ 2454*7c478bd9Sstevel@tonic-gate if (pbm_err.pbm_ctl_stat & TOMATILLO_PCI_CTRL_PCI_DTO_ERR) { 2455*7c478bd9Sstevel@tonic-gate if (pci_dto_fault_warn == CE_PANIC) 2456*7c478bd9Sstevel@tonic-gate fatal++; 2457*7c478bd9Sstevel@tonic-gate else 2458*7c478bd9Sstevel@tonic-gate nonfatal++; 2459*7c478bd9Sstevel@tonic-gate 2460*7c478bd9Sstevel@tonic-gate (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", 2461*7c478bd9Sstevel@tonic-gate PCI_ERROR_SUBCLASS, PCI_DTO); 2462*7c478bd9Sstevel@tonic-gate ddi_fm_ereport_post(dip, buf, derr->fme_ena, DDI_NOSLEEP, 2463*7c478bd9Sstevel@tonic-gate FM_VERSION, DATA_TYPE_UINT8, 0, 2464*7c478bd9Sstevel@tonic-gate PCI_CONFIG_STATUS, DATA_TYPE_UINT16, 2465*7c478bd9Sstevel@tonic-gate pbm_err.pbm_pci.pci_cfg_stat, 2466*7c478bd9Sstevel@tonic-gate PCI_CONFIG_COMMAND, DATA_TYPE_UINT16, 2467*7c478bd9Sstevel@tonic-gate pbm_err.pbm_pci.pci_cfg_comm, 2468*7c478bd9Sstevel@tonic-gate PCI_PA, DATA_TYPE_UINT64, (uint64_t)0, NULL); 2469*7c478bd9Sstevel@tonic-gate } 2470*7c478bd9Sstevel@tonic-gate 2471*7c478bd9Sstevel@tonic-gate /* 2472*7c478bd9Sstevel@tonic-gate * PBM Detected Data Parity Error - DPE detected during a DMA Write 2473*7c478bd9Sstevel@tonic-gate * or PIO Read. Later case is taken care of by cpu_deferred_error 2474*7c478bd9Sstevel@tonic-gate * and sent here to be logged. 2475*7c478bd9Sstevel@tonic-gate */ 2476*7c478bd9Sstevel@tonic-gate if ((pbm_err.pbm_pci.pci_cfg_stat & PCI_STAT_PERROR) && 2477*7c478bd9Sstevel@tonic-gate !(pbm_err.pbm_pci.pci_cfg_stat & PCI_STAT_S_SYSERR)) { 2478*7c478bd9Sstevel@tonic-gate /* 2479*7c478bd9Sstevel@tonic-gate * If we have an address then fault 2480*7c478bd9Sstevel@tonic-gate * it, if not probe for errant device 2481*7c478bd9Sstevel@tonic-gate */ 2482*7c478bd9Sstevel@tonic-gate ret = DDI_FM_FATAL; 2483*7c478bd9Sstevel@tonic-gate if (caller != PCI_TRAP_CALL) { 2484*7c478bd9Sstevel@tonic-gate if (pbm_err.pbm_va_log) 2485*7c478bd9Sstevel@tonic-gate ret = pci_handle_lookup(dip, DMA_HANDLE, 2486*7c478bd9Sstevel@tonic-gate derr->fme_ena, 2487*7c478bd9Sstevel@tonic-gate (void *)&pbm_err.pbm_va_log); 2488*7c478bd9Sstevel@tonic-gate if (ret == DDI_FM_NONFATAL) 2489*7c478bd9Sstevel@tonic-gate nonfatal++; 2490*7c478bd9Sstevel@tonic-gate else 2491*7c478bd9Sstevel@tonic-gate fatal++; 2492*7c478bd9Sstevel@tonic-gate } else 2493*7c478bd9Sstevel@tonic-gate nonfatal++; 2494*7c478bd9Sstevel@tonic-gate 2495*7c478bd9Sstevel@tonic-gate } 2496*7c478bd9Sstevel@tonic-gate 2497*7c478bd9Sstevel@tonic-gate /* PBM Detected IOMMU Error */ 2498*7c478bd9Sstevel@tonic-gate if (pbm_err.pbm_ctl_stat & SCHIZO_PCI_CTRL_PCI_MMU_ERR) { 2499*7c478bd9Sstevel@tonic-gate if (iommu_err_handler(dip, derr->fme_ena, &pbm_err) 2500*7c478bd9Sstevel@tonic-gate == DDI_FM_FATAL) 2501*7c478bd9Sstevel@tonic-gate fatal++; 2502*7c478bd9Sstevel@tonic-gate else 2503*7c478bd9Sstevel@tonic-gate nonfatal++; 2504*7c478bd9Sstevel@tonic-gate } 2505*7c478bd9Sstevel@tonic-gate 2506*7c478bd9Sstevel@tonic-gate done: 2507*7c478bd9Sstevel@tonic-gate ret = ndi_fm_handler_dispatch(dip, NULL, derr); 2508*7c478bd9Sstevel@tonic-gate if (ret == DDI_FM_FATAL) { 2509*7c478bd9Sstevel@tonic-gate fatal++; 2510*7c478bd9Sstevel@tonic-gate } else if (ret == DDI_FM_NONFATAL) { 2511*7c478bd9Sstevel@tonic-gate nonfatal++; 2512*7c478bd9Sstevel@tonic-gate } else if (ret == DDI_FM_UNKNOWN) { 2513*7c478bd9Sstevel@tonic-gate unknown++; 2514*7c478bd9Sstevel@tonic-gate } 2515*7c478bd9Sstevel@tonic-gate 2516*7c478bd9Sstevel@tonic-gate /* 2517*7c478bd9Sstevel@tonic-gate * RSERR not claimed as nonfatal by a child is considered fatal 2518*7c478bd9Sstevel@tonic-gate */ 2519*7c478bd9Sstevel@tonic-gate if (rserr && ret != DDI_FM_NONFATAL) 2520*7c478bd9Sstevel@tonic-gate fatal++; 2521*7c478bd9Sstevel@tonic-gate 2522*7c478bd9Sstevel@tonic-gate /* Cleanup and reset error bits */ 2523*7c478bd9Sstevel@tonic-gate pci_clear_error(pci_p, &pbm_err); 2524*7c478bd9Sstevel@tonic-gate 2525*7c478bd9Sstevel@tonic-gate return (fatal ? DDI_FM_FATAL : (nonfatal ? DDI_FM_NONFATAL : 2526*7c478bd9Sstevel@tonic-gate (unknown ? DDI_FM_UNKNOWN : DDI_FM_OK))); 2527*7c478bd9Sstevel@tonic-gate } 2528*7c478bd9Sstevel@tonic-gate 2529*7c478bd9Sstevel@tonic-gate /* 2530*7c478bd9Sstevel@tonic-gate * Function returns TRUE if a Primary error is Split Completion Error 2531*7c478bd9Sstevel@tonic-gate * that indicates a Master Abort occured behind a PCI-X bridge. 2532*7c478bd9Sstevel@tonic-gate * This function should only be called for busses running in PCI-X mode. 2533*7c478bd9Sstevel@tonic-gate */ 2534*7c478bd9Sstevel@tonic-gate static int 2535*7c478bd9Sstevel@tonic-gate pcix_ma_behind_bridge(pbm_errstate_t *pbm_err_p) 2536*7c478bd9Sstevel@tonic-gate { 2537*7c478bd9Sstevel@tonic-gate uint64_t msg; 2538*7c478bd9Sstevel@tonic-gate 2539*7c478bd9Sstevel@tonic-gate if (pbm_err_p->pbm_afsr & XMITS_PCI_X_AFSR_S_SC_ERR) 2540*7c478bd9Sstevel@tonic-gate return (0); 2541*7c478bd9Sstevel@tonic-gate 2542*7c478bd9Sstevel@tonic-gate if (pbm_err_p->pbm_afsr & XMITS_PCI_X_AFSR_P_SC_ERR) { 2543*7c478bd9Sstevel@tonic-gate msg = (pbm_err_p->pbm_afsr >> XMITS_PCI_X_P_MSG_SHIFT) & 2544*7c478bd9Sstevel@tonic-gate XMITS_PCIX_MSG_MASK; 2545*7c478bd9Sstevel@tonic-gate if (msg & PCIX_CLASS_BRIDGE) 2546*7c478bd9Sstevel@tonic-gate if (msg & PCIX_BRIDGE_MASTER_ABORT) { 2547*7c478bd9Sstevel@tonic-gate return (1); 2548*7c478bd9Sstevel@tonic-gate } 2549*7c478bd9Sstevel@tonic-gate } 2550*7c478bd9Sstevel@tonic-gate 2551*7c478bd9Sstevel@tonic-gate return (0); 2552*7c478bd9Sstevel@tonic-gate } 2553*7c478bd9Sstevel@tonic-gate 2554*7c478bd9Sstevel@tonic-gate /* 2555*7c478bd9Sstevel@tonic-gate * Function used to gather PBM/PCI/IOMMU error state for the 2556*7c478bd9Sstevel@tonic-gate * pci_pbm_err_handler and the cb_buserr_intr. This function must be 2557*7c478bd9Sstevel@tonic-gate * called while pci_fm_mutex is held. 2558*7c478bd9Sstevel@tonic-gate */ 2559*7c478bd9Sstevel@tonic-gate static void 2560*7c478bd9Sstevel@tonic-gate pci_pbm_errstate_get(pci_t *pci_p, pbm_errstate_t *pbm_err_p) 2561*7c478bd9Sstevel@tonic-gate { 2562*7c478bd9Sstevel@tonic-gate pbm_t *pbm_p = pci_p->pci_pbm_p; 2563*7c478bd9Sstevel@tonic-gate iommu_t *iommu_p = pci_p->pci_iommu_p; 2564*7c478bd9Sstevel@tonic-gate caddr_t a = pci_p->pci_address[0]; 2565*7c478bd9Sstevel@tonic-gate uint64_t *pbm_pcix_stat_reg; 2566*7c478bd9Sstevel@tonic-gate 2567*7c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&pci_p->pci_common_p->pci_fm_mutex)); 2568*7c478bd9Sstevel@tonic-gate bzero(pbm_err_p, sizeof (pbm_errstate_t)); 2569*7c478bd9Sstevel@tonic-gate 2570*7c478bd9Sstevel@tonic-gate /* 2571*7c478bd9Sstevel@tonic-gate * Capture all pbm error state for later logging 2572*7c478bd9Sstevel@tonic-gate */ 2573*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_bridge_type = PCI_BRIDGE_TYPE(pci_p->pci_common_p); 2574*7c478bd9Sstevel@tonic-gate 2575*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_pci.pci_cfg_stat = 2576*7c478bd9Sstevel@tonic-gate pbm_p->pbm_config_header->ch_status_reg; 2577*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_ctl_stat = *pbm_p->pbm_ctrl_reg; 2578*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_afsr = *pbm_p->pbm_async_flt_status_reg; 2579*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_afar = *pbm_p->pbm_async_flt_addr_reg; 2580*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_iommu.iommu_stat = *iommu_p->iommu_ctrl_reg; 2581*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_pci.pci_cfg_comm = 2582*7c478bd9Sstevel@tonic-gate pbm_p->pbm_config_header->ch_command_reg; 2583*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_pci.pci_pa = *pbm_p->pbm_async_flt_addr_reg; 2584*7c478bd9Sstevel@tonic-gate 2585*7c478bd9Sstevel@tonic-gate /* 2586*7c478bd9Sstevel@tonic-gate * Record errant slot for Xmits and Schizo 2587*7c478bd9Sstevel@tonic-gate * Not stored in Tomatillo 2588*7c478bd9Sstevel@tonic-gate */ 2589*7c478bd9Sstevel@tonic-gate if (CHIP_TYPE(pci_p) == PCI_CHIP_XMITS || 2590*7c478bd9Sstevel@tonic-gate CHIP_TYPE(pci_p) == PCI_CHIP_SCHIZO) { 2591*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_err_sl = (pbm_err_p->pbm_ctl_stat & 2592*7c478bd9Sstevel@tonic-gate SCHIZO_PCI_CTRL_ERR_SLOT) >> 2593*7c478bd9Sstevel@tonic-gate SCHIZO_PCI_CTRL_ERR_SLOT_SHIFT; 2594*7c478bd9Sstevel@tonic-gate 2595*7c478bd9Sstevel@tonic-gate /* 2596*7c478bd9Sstevel@tonic-gate * The bit 51 on XMITS rev1.0 is same as 2597*7c478bd9Sstevel@tonic-gate * SCHIZO_PCI_CTRL_ERR_SLOT_LOCK on schizo2.3. But 2598*7c478bd9Sstevel@tonic-gate * this bit needs to be cleared to be able to latch 2599*7c478bd9Sstevel@tonic-gate * the slot info on next fault. 2600*7c478bd9Sstevel@tonic-gate * But in XMITS Rev2.0, this bit indicates a DMA Write 2601*7c478bd9Sstevel@tonic-gate * Parity error. 2602*7c478bd9Sstevel@tonic-gate */ 2603*7c478bd9Sstevel@tonic-gate if (pbm_err_p->pbm_ctl_stat & XMITS_PCI_CTRL_DMA_WR_PERR) { 2604*7c478bd9Sstevel@tonic-gate if ((PCI_CHIP_ID(pci_p) == XMITS_VER_10) || 2605*7c478bd9Sstevel@tonic-gate (PCI_CHIP_ID(pci_p) <= SCHIZO_VER_23)) { 2606*7c478bd9Sstevel@tonic-gate /* 2607*7c478bd9Sstevel@tonic-gate * top 32 bits are W1C and we just want to 2608*7c478bd9Sstevel@tonic-gate * clear SLOT_LOCK. Leave bottom 32 bits 2609*7c478bd9Sstevel@tonic-gate * unchanged 2610*7c478bd9Sstevel@tonic-gate */ 2611*7c478bd9Sstevel@tonic-gate *pbm_p->pbm_ctrl_reg = 2612*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_ctl_stat & 2613*7c478bd9Sstevel@tonic-gate (SCHIZO_PCI_CTRL_ERR_SLOT_LOCK | 2614*7c478bd9Sstevel@tonic-gate 0xffffffff); 2615*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_ctl_stat = 2616*7c478bd9Sstevel@tonic-gate *pbm_p->pbm_ctrl_reg; 2617*7c478bd9Sstevel@tonic-gate } 2618*7c478bd9Sstevel@tonic-gate } 2619*7c478bd9Sstevel@tonic-gate } 2620*7c478bd9Sstevel@tonic-gate 2621*7c478bd9Sstevel@tonic-gate /* 2622*7c478bd9Sstevel@tonic-gate * Tomatillo specific registers 2623*7c478bd9Sstevel@tonic-gate */ 2624*7c478bd9Sstevel@tonic-gate if (CHIP_TYPE(pci_p) == PCI_CHIP_TOMATILLO) { 2625*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_va_log = (uint64_t)va_to_pa((void *)*(a + 2626*7c478bd9Sstevel@tonic-gate TOMATILLO_TGT_ERR_VALOG_OFFSET)); 2627*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_iommu.iommu_tfar = *iommu_p->iommu_tfar_reg; 2628*7c478bd9Sstevel@tonic-gate } 2629*7c478bd9Sstevel@tonic-gate 2630*7c478bd9Sstevel@tonic-gate /* 2631*7c478bd9Sstevel@tonic-gate * Xmits PCI-X register 2632*7c478bd9Sstevel@tonic-gate */ 2633*7c478bd9Sstevel@tonic-gate if ((CHIP_TYPE(pci_p) == PCI_CHIP_XMITS) && 2634*7c478bd9Sstevel@tonic-gate (pbm_err_p->pbm_ctl_stat & XMITS_PCI_CTRL_X_MODE)) { 2635*7c478bd9Sstevel@tonic-gate 2636*7c478bd9Sstevel@tonic-gate pbm_pcix_stat_reg = (uint64_t *)(a + 2637*7c478bd9Sstevel@tonic-gate XMITS_PCI_X_ERROR_STATUS_REG_OFFSET); 2638*7c478bd9Sstevel@tonic-gate 2639*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_pcix_stat = *pbm_pcix_stat_reg; 2640*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_pcix_pfar = pbm_err_p->pbm_pcix_stat & 2641*7c478bd9Sstevel@tonic-gate XMITS_PCI_X_STATUS_PFAR_MASK; 2642*7c478bd9Sstevel@tonic-gate } 2643*7c478bd9Sstevel@tonic-gate } 2644*7c478bd9Sstevel@tonic-gate 2645*7c478bd9Sstevel@tonic-gate /* 2646*7c478bd9Sstevel@tonic-gate * Function used to clear PBM/PCI/IOMMU error state after error handling 2647*7c478bd9Sstevel@tonic-gate * is complete. Only clearing error bits which have been logged. Called by 2648*7c478bd9Sstevel@tonic-gate * pci_pbm_err_handler and pci_bus_exit. 2649*7c478bd9Sstevel@tonic-gate */ 2650*7c478bd9Sstevel@tonic-gate static void 2651*7c478bd9Sstevel@tonic-gate pci_clear_error(pci_t *pci_p, pbm_errstate_t *pbm_err_p) 2652*7c478bd9Sstevel@tonic-gate { 2653*7c478bd9Sstevel@tonic-gate pbm_t *pbm_p = pci_p->pci_pbm_p; 2654*7c478bd9Sstevel@tonic-gate iommu_t *iommu_p = pci_p->pci_iommu_p; 2655*7c478bd9Sstevel@tonic-gate 2656*7c478bd9Sstevel@tonic-gate ASSERT(MUTEX_HELD(&pbm_p->pbm_pci_p->pci_common_p->pci_fm_mutex)); 2657*7c478bd9Sstevel@tonic-gate 2658*7c478bd9Sstevel@tonic-gate if (*pbm_p->pbm_ctrl_reg & SCHIZO_PCI_CTRL_PCI_MMU_ERR) { 2659*7c478bd9Sstevel@tonic-gate iommu_tlb_scrub(pci_p->pci_iommu_p, 1); 2660*7c478bd9Sstevel@tonic-gate } 2661*7c478bd9Sstevel@tonic-gate pbm_p->pbm_config_header->ch_status_reg = 2662*7c478bd9Sstevel@tonic-gate pbm_err_p->pbm_pci.pci_cfg_stat; 2663*7c478bd9Sstevel@tonic-gate *pbm_p->pbm_ctrl_reg = pbm_err_p->pbm_ctl_stat; 2664*7c478bd9Sstevel@tonic-gate *pbm_p->pbm_async_flt_status_reg = pbm_err_p->pbm_afsr; 2665*7c478bd9Sstevel@tonic-gate *iommu_p->iommu_ctrl_reg = pbm_err_p->pbm_iommu.iommu_stat; 2666*7c478bd9Sstevel@tonic-gate } 2667*7c478bd9Sstevel@tonic-gate 2668*7c478bd9Sstevel@tonic-gate void 2669*7c478bd9Sstevel@tonic-gate pbm_clear_error(pbm_t *pbm_p) 2670*7c478bd9Sstevel@tonic-gate { 2671*7c478bd9Sstevel@tonic-gate uint64_t pbm_afsr, pbm_ctl_stat; 2672*7c478bd9Sstevel@tonic-gate 2673*7c478bd9Sstevel@tonic-gate /* 2674*7c478bd9Sstevel@tonic-gate * for poke() support - called from POKE_FLUSH. Spin waiting 2675*7c478bd9Sstevel@tonic-gate * for MA, TA or SERR to be cleared by a pbm_error_intr(). 2676*7c478bd9Sstevel@tonic-gate * We have to wait for SERR too in case the device is beyond 2677*7c478bd9Sstevel@tonic-gate * a pci-pci bridge. 2678*7c478bd9Sstevel@tonic-gate */ 2679*7c478bd9Sstevel@tonic-gate pbm_ctl_stat = *pbm_p->pbm_ctrl_reg; 2680*7c478bd9Sstevel@tonic-gate pbm_afsr = *pbm_p->pbm_async_flt_status_reg; 2681*7c478bd9Sstevel@tonic-gate while (((pbm_afsr >> SCHIZO_PCI_AFSR_PE_SHIFT) & 2682*7c478bd9Sstevel@tonic-gate (SCHIZO_PCI_AFSR_E_MA | SCHIZO_PCI_AFSR_E_TA)) || 2683*7c478bd9Sstevel@tonic-gate (pbm_ctl_stat & COMMON_PCI_CTRL_SERR)) { 2684*7c478bd9Sstevel@tonic-gate pbm_ctl_stat = *pbm_p->pbm_ctrl_reg; 2685*7c478bd9Sstevel@tonic-gate pbm_afsr = *pbm_p->pbm_async_flt_status_reg; 2686*7c478bd9Sstevel@tonic-gate } 2687*7c478bd9Sstevel@tonic-gate } 2688*7c478bd9Sstevel@tonic-gate 2689*7c478bd9Sstevel@tonic-gate /* 2690*7c478bd9Sstevel@tonic-gate * Function used to convert the 32 bit captured PCI error address 2691*7c478bd9Sstevel@tonic-gate * to the full Safari or Jbus address. This is so we can look this address 2692*7c478bd9Sstevel@tonic-gate * up in our handle caches. 2693*7c478bd9Sstevel@tonic-gate */ 2694*7c478bd9Sstevel@tonic-gate void 2695*7c478bd9Sstevel@tonic-gate pci_format_addr(dev_info_t *dip, uint64_t *afar, uint64_t afsr) 2696*7c478bd9Sstevel@tonic-gate { 2697*7c478bd9Sstevel@tonic-gate pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 2698*7c478bd9Sstevel@tonic-gate pci_ranges_t *io_range, *mem_range; 2699*7c478bd9Sstevel@tonic-gate uint64_t err_pa = 0; 2700*7c478bd9Sstevel@tonic-gate 2701*7c478bd9Sstevel@tonic-gate if (afsr & SCHIZO_PCI_AFSR_CONF_SPACE) { 2702*7c478bd9Sstevel@tonic-gate err_pa |= pci_p->pci_ranges->parent_high; 2703*7c478bd9Sstevel@tonic-gate err_pa = err_pa << 32; 2704*7c478bd9Sstevel@tonic-gate err_pa |= pci_p->pci_ranges->parent_low; 2705*7c478bd9Sstevel@tonic-gate } else if (afsr & SCHIZO_PCI_AFSR_IO_SPACE) { 2706*7c478bd9Sstevel@tonic-gate io_range = pci_p->pci_ranges + 1; 2707*7c478bd9Sstevel@tonic-gate err_pa |= io_range->parent_high; 2708*7c478bd9Sstevel@tonic-gate err_pa = err_pa << 32; 2709*7c478bd9Sstevel@tonic-gate err_pa |= io_range->parent_low; 2710*7c478bd9Sstevel@tonic-gate } else if (afsr & SCHIZO_PCI_AFSR_MEM_SPACE) { 2711*7c478bd9Sstevel@tonic-gate mem_range = pci_p->pci_ranges + 2; 2712*7c478bd9Sstevel@tonic-gate err_pa |= mem_range->parent_high; 2713*7c478bd9Sstevel@tonic-gate err_pa = err_pa << 32; 2714*7c478bd9Sstevel@tonic-gate err_pa |= mem_range->parent_low; 2715*7c478bd9Sstevel@tonic-gate } 2716*7c478bd9Sstevel@tonic-gate *afar |= err_pa; 2717*7c478bd9Sstevel@tonic-gate } 2718*7c478bd9Sstevel@tonic-gate 2719*7c478bd9Sstevel@tonic-gate static ecc_format_t ecc_format_tbl[] = { 2720*7c478bd9Sstevel@tonic-gate SCH_REG_UPA, NULL, NULL, 2721*7c478bd9Sstevel@tonic-gate SCH_REG_PCIA_REG, SCHIZO_PCI_AFSR_CONF_SPACE, PCI_SIDEA, 2722*7c478bd9Sstevel@tonic-gate SCH_REG_PCIA_MEM, SCHIZO_PCI_AFSR_MEM_SPACE, PCI_SIDEA, 2723*7c478bd9Sstevel@tonic-gate SCH_REG_PCIA_CFGIO, SCHIZO_PCI_AFSR_IO_SPACE, PCI_SIDEA, 2724*7c478bd9Sstevel@tonic-gate SCH_REG_PCIB_REG, SCHIZO_PCI_AFSR_CONF_SPACE, PCI_SIDEB, 2725*7c478bd9Sstevel@tonic-gate SCH_REG_PCIB_MEM, SCHIZO_PCI_AFSR_MEM_SPACE, PCI_SIDEB, 2726*7c478bd9Sstevel@tonic-gate SCH_REG_PCIB_CFGIO, SCHIZO_PCI_AFSR_IO_SPACE, PCI_SIDEB, 2727*7c478bd9Sstevel@tonic-gate SCH_REG_SAFARI_REGS, NULL, NULL, 2728*7c478bd9Sstevel@tonic-gate NULL, NULL, NULL, 2729*7c478bd9Sstevel@tonic-gate }; 2730*7c478bd9Sstevel@tonic-gate 2731*7c478bd9Sstevel@tonic-gate /* 2732*7c478bd9Sstevel@tonic-gate * Function used to convert the 32 bit PIO address captured for a 2733*7c478bd9Sstevel@tonic-gate * Safari Bus UE(during PIO Rd/Wr) to a full Safari Bus Address. 2734*7c478bd9Sstevel@tonic-gate */ 2735*7c478bd9Sstevel@tonic-gate static void 2736*7c478bd9Sstevel@tonic-gate pci_format_ecc_addr(dev_info_t *dip, uint64_t *afar, ecc_region_t region) 2737*7c478bd9Sstevel@tonic-gate { 2738*7c478bd9Sstevel@tonic-gate pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 2739*7c478bd9Sstevel@tonic-gate pci_common_t *cmn_p = pci_p->pci_common_p; 2740*7c478bd9Sstevel@tonic-gate cb_t *cb_p = pci_p->pci_cb_p; 2741*7c478bd9Sstevel@tonic-gate int i, pci_side = 0; 2742*7c478bd9Sstevel@tonic-gate int swap = 0; 2743*7c478bd9Sstevel@tonic-gate uint64_t pa = cb_p->cb_base_pa; 2744*7c478bd9Sstevel@tonic-gate uint64_t flag, schizo_base, pci_csr_base; 2745*7c478bd9Sstevel@tonic-gate 2746*7c478bd9Sstevel@tonic-gate if (pci_p == NULL) 2747*7c478bd9Sstevel@tonic-gate return; 2748*7c478bd9Sstevel@tonic-gate 2749*7c478bd9Sstevel@tonic-gate pci_csr_base = va_to_pa(pci_p->pci_address[0]); 2750*7c478bd9Sstevel@tonic-gate 2751*7c478bd9Sstevel@tonic-gate /* 2752*7c478bd9Sstevel@tonic-gate * Using the csr_base address to determine which side 2753*7c478bd9Sstevel@tonic-gate * we are on. 2754*7c478bd9Sstevel@tonic-gate */ 2755*7c478bd9Sstevel@tonic-gate if (pci_csr_base & PCI_SIDE_ADDR_MASK) 2756*7c478bd9Sstevel@tonic-gate pci_side = 1; 2757*7c478bd9Sstevel@tonic-gate else 2758*7c478bd9Sstevel@tonic-gate pci_side = 0; 2759*7c478bd9Sstevel@tonic-gate 2760*7c478bd9Sstevel@tonic-gate schizo_base = pa - PBM_CTRL_OFFSET; 2761*7c478bd9Sstevel@tonic-gate 2762*7c478bd9Sstevel@tonic-gate for (i = 0; ecc_format_tbl[i].ecc_region != NULL; i++) { 2763*7c478bd9Sstevel@tonic-gate if (region == ecc_format_tbl[i].ecc_region) { 2764*7c478bd9Sstevel@tonic-gate flag = ecc_format_tbl[i].ecc_space; 2765*7c478bd9Sstevel@tonic-gate if (ecc_format_tbl[i].ecc_side != pci_side) 2766*7c478bd9Sstevel@tonic-gate swap = 1; 2767*7c478bd9Sstevel@tonic-gate if (region == SCH_REG_SAFARI_REGS) 2768*7c478bd9Sstevel@tonic-gate *afar |= schizo_base; 2769*7c478bd9Sstevel@tonic-gate break; 2770*7c478bd9Sstevel@tonic-gate } 2771*7c478bd9Sstevel@tonic-gate } 2772*7c478bd9Sstevel@tonic-gate 2773*7c478bd9Sstevel@tonic-gate if (swap) { 2774*7c478bd9Sstevel@tonic-gate pci_p = cmn_p->pci_p[PCI_OTHER_SIDE(pci_p->pci_side)]; 2775*7c478bd9Sstevel@tonic-gate 2776*7c478bd9Sstevel@tonic-gate if (pci_p == NULL) 2777*7c478bd9Sstevel@tonic-gate return; 2778*7c478bd9Sstevel@tonic-gate } 2779*7c478bd9Sstevel@tonic-gate pci_format_addr(pci_p->pci_dip, afar, flag); 2780*7c478bd9Sstevel@tonic-gate } 2781*7c478bd9Sstevel@tonic-gate 2782*7c478bd9Sstevel@tonic-gate /* 2783*7c478bd9Sstevel@tonic-gate * Function used to post control block specific ereports. 2784*7c478bd9Sstevel@tonic-gate */ 2785*7c478bd9Sstevel@tonic-gate static void 2786*7c478bd9Sstevel@tonic-gate cb_ereport_post(dev_info_t *dip, uint64_t ena, cb_errstate_t *cb_err) 2787*7c478bd9Sstevel@tonic-gate { 2788*7c478bd9Sstevel@tonic-gate pci_t *pci_p = get_pci_soft_state(ddi_get_instance(dip)); 2789*7c478bd9Sstevel@tonic-gate char buf[FM_MAX_CLASS], dev_path[MAXPATHLEN], *ptr; 2790*7c478bd9Sstevel@tonic-gate struct i_ddi_fmhdl *fmhdl = DEVI(dip)->devi_fmhdl; 2791*7c478bd9Sstevel@tonic-gate nvlist_t *ereport, *detector; 2792*7c478bd9Sstevel@tonic-gate errorq_elem_t *eqep; 2793*7c478bd9Sstevel@tonic-gate nv_alloc_t *nva; 2794*7c478bd9Sstevel@tonic-gate 2795*7c478bd9Sstevel@tonic-gate DEBUG1(DBG_ATTACH, dip, "cb_ereport_post: elog 0x%lx", 2796*7c478bd9Sstevel@tonic-gate cb_err->cb_elog); 2797*7c478bd9Sstevel@tonic-gate 2798*7c478bd9Sstevel@tonic-gate /* 2799*7c478bd9Sstevel@tonic-gate * We do not use ddi_fm_ereport_post because we need to set a 2800*7c478bd9Sstevel@tonic-gate * special detector here. Since we do not have a device path for 2801*7c478bd9Sstevel@tonic-gate * the bridge chip we use what we think it should be to aid in 2802*7c478bd9Sstevel@tonic-gate * diagnosis. 2803*7c478bd9Sstevel@tonic-gate */ 2804*7c478bd9Sstevel@tonic-gate (void) snprintf(buf, FM_MAX_CLASS, "%s.%s.%s", DDI_IO_CLASS, 2805*7c478bd9Sstevel@tonic-gate cb_err->cb_bridge_type, cb_err->cb_err_class); 2806*7c478bd9Sstevel@tonic-gate 2807*7c478bd9Sstevel@tonic-gate ena = ena ? ena : fm_ena_generate(0, FM_ENA_FMT1); 2808*7c478bd9Sstevel@tonic-gate 2809*7c478bd9Sstevel@tonic-gate eqep = errorq_reserve(fmhdl->fh_errorq); 2810*7c478bd9Sstevel@tonic-gate if (eqep == NULL) 2811*7c478bd9Sstevel@tonic-gate return; 2812*7c478bd9Sstevel@tonic-gate 2813*7c478bd9Sstevel@tonic-gate ereport = errorq_elem_nvl(fmhdl->fh_errorq, eqep); 2814*7c478bd9Sstevel@tonic-gate nva = errorq_elem_nva(fmhdl->fh_errorq, eqep); 2815*7c478bd9Sstevel@tonic-gate detector = fm_nvlist_create(nva); 2816*7c478bd9Sstevel@tonic-gate 2817*7c478bd9Sstevel@tonic-gate ASSERT(ereport); 2818*7c478bd9Sstevel@tonic-gate ASSERT(nva); 2819*7c478bd9Sstevel@tonic-gate ASSERT(detector); 2820*7c478bd9Sstevel@tonic-gate 2821*7c478bd9Sstevel@tonic-gate ddi_pathname(dip, dev_path); 2822*7c478bd9Sstevel@tonic-gate ptr = strrchr(dev_path, (int)','); 2823*7c478bd9Sstevel@tonic-gate 2824*7c478bd9Sstevel@tonic-gate if (ptr) 2825*7c478bd9Sstevel@tonic-gate *ptr = '\0'; 2826*7c478bd9Sstevel@tonic-gate 2827*7c478bd9Sstevel@tonic-gate fm_fmri_dev_set(detector, FM_DEV_SCHEME_VERSION, NULL, dev_path, NULL); 2828*7c478bd9Sstevel@tonic-gate 2829*7c478bd9Sstevel@tonic-gate DEBUG1(DBG_ERR_INTR, dip, "cb_ereport_post: ereport_set: %s", buf); 2830*7c478bd9Sstevel@tonic-gate 2831*7c478bd9Sstevel@tonic-gate if (CHIP_TYPE(pci_p) == PCI_CHIP_SCHIZO || 2832*7c478bd9Sstevel@tonic-gate CHIP_TYPE(pci_p) == PCI_CHIP_XMITS) { 2833*7c478bd9Sstevel@tonic-gate fm_ereport_set(ereport, FM_EREPORT_VERSION, buf, ena, detector, 2834*7c478bd9Sstevel@tonic-gate SAFARI_CSR, DATA_TYPE_UINT64, cb_err->cb_csr, 2835*7c478bd9Sstevel@tonic-gate SAFARI_ERR, DATA_TYPE_UINT64, cb_err->cb_err, 2836*7c478bd9Sstevel@tonic-gate SAFARI_INTR, DATA_TYPE_UINT64, cb_err->cb_intr, 2837*7c478bd9Sstevel@tonic-gate SAFARI_ELOG, DATA_TYPE_UINT64, cb_err->cb_elog, 2838*7c478bd9Sstevel@tonic-gate SAFARI_PCR, DATA_TYPE_UINT64, cb_err->cb_pcr, 2839*7c478bd9Sstevel@tonic-gate NULL); 2840*7c478bd9Sstevel@tonic-gate } else if (CHIP_TYPE(pci_p) == PCI_CHIP_TOMATILLO) { 2841*7c478bd9Sstevel@tonic-gate fm_ereport_set(ereport, FM_EREPORT_VERSION, buf, ena, detector, 2842*7c478bd9Sstevel@tonic-gate JBUS_CSR, DATA_TYPE_UINT64, cb_err->cb_csr, 2843*7c478bd9Sstevel@tonic-gate JBUS_ERR, DATA_TYPE_UINT64, cb_err->cb_err, 2844*7c478bd9Sstevel@tonic-gate JBUS_INTR, DATA_TYPE_UINT64, cb_err->cb_intr, 2845*7c478bd9Sstevel@tonic-gate JBUS_ELOG, DATA_TYPE_UINT64, cb_err->cb_elog, 2846*7c478bd9Sstevel@tonic-gate JBUS_PCR, DATA_TYPE_UINT64, cb_err->cb_pcr, 2847*7c478bd9Sstevel@tonic-gate NULL); 2848*7c478bd9Sstevel@tonic-gate } 2849*7c478bd9Sstevel@tonic-gate errorq_commit(fmhdl->fh_errorq, eqep, ERRORQ_ASYNC); 2850*7c478bd9Sstevel@tonic-gate } 2851*7c478bd9Sstevel@tonic-gate 2852*7c478bd9Sstevel@tonic-gate /* 2853*7c478bd9Sstevel@tonic-gate * Function used to post IOMMU specific ereports. 2854*7c478bd9Sstevel@tonic-gate */ 2855*7c478bd9Sstevel@tonic-gate static void 2856*7c478bd9Sstevel@tonic-gate iommu_ereport_post(dev_info_t *dip, uint64_t ena, pbm_errstate_t *pbm_err) 2857*7c478bd9Sstevel@tonic-gate { 2858*7c478bd9Sstevel@tonic-gate char buf[FM_MAX_CLASS]; 2859*7c478bd9Sstevel@tonic-gate 2860*7c478bd9Sstevel@tonic-gate (void) snprintf(buf, FM_MAX_CLASS, "%s.%s", 2861*7c478bd9Sstevel@tonic-gate pbm_err->pbm_bridge_type, pbm_err->pbm_err_class); 2862*7c478bd9Sstevel@tonic-gate 2863*7c478bd9Sstevel@tonic-gate ena = ena ? ena : fm_ena_generate(0, FM_ENA_FMT1); 2864*7c478bd9Sstevel@tonic-gate 2865*7c478bd9Sstevel@tonic-gate DEBUG1(DBG_ERR_INTR, dip, "iommu_ereport_post: ereport_set: %s", buf); 2866*7c478bd9Sstevel@tonic-gate 2867*7c478bd9Sstevel@tonic-gate ddi_fm_ereport_post(dip, buf, ena, DDI_NOSLEEP, 2868*7c478bd9Sstevel@tonic-gate FM_VERSION, DATA_TYPE_UINT8, 0, 2869*7c478bd9Sstevel@tonic-gate PCI_CONFIG_STATUS, DATA_TYPE_UINT16, pbm_err->pbm_pci.pci_cfg_stat, 2870*7c478bd9Sstevel@tonic-gate PCI_CONFIG_COMMAND, DATA_TYPE_UINT16, pbm_err->pbm_pci.pci_cfg_comm, 2871*7c478bd9Sstevel@tonic-gate PCI_PBM_CSR, DATA_TYPE_UINT64, pbm_err->pbm_ctl_stat, 2872*7c478bd9Sstevel@tonic-gate PCI_PBM_IOMMU_CTRL, DATA_TYPE_UINT64, pbm_err->pbm_iommu.iommu_stat, 2873*7c478bd9Sstevel@tonic-gate PCI_PBM_IOMMU_TFAR, DATA_TYPE_UINT64, pbm_err->pbm_iommu.iommu_tfar, 2874*7c478bd9Sstevel@tonic-gate PCI_PBM_SLOT, DATA_TYPE_UINT64, pbm_err->pbm_err_sl, 2875*7c478bd9Sstevel@tonic-gate PCI_PBM_VALOG, DATA_TYPE_UINT64, pbm_err->pbm_va_log, 2876*7c478bd9Sstevel@tonic-gate NULL); 2877*7c478bd9Sstevel@tonic-gate } 2878*7c478bd9Sstevel@tonic-gate 2879*7c478bd9Sstevel@tonic-gate /* 2880*7c478bd9Sstevel@tonic-gate * Function used to post PCI-X generic ereports. 2881*7c478bd9Sstevel@tonic-gate * This function needs to be fixed once the Fault Boundary Analysis 2882*7c478bd9Sstevel@tonic-gate * for PCI-X is conducted. The payload should be made more generic. 2883*7c478bd9Sstevel@tonic-gate */ 2884*7c478bd9Sstevel@tonic-gate static void 2885*7c478bd9Sstevel@tonic-gate pcix_ereport_post(dev_info_t *dip, uint64_t ena, pbm_errstate_t *pbm_err) 2886*7c478bd9Sstevel@tonic-gate { 2887*7c478bd9Sstevel@tonic-gate char buf[FM_MAX_CLASS]; 2888*7c478bd9Sstevel@tonic-gate 2889*7c478bd9Sstevel@tonic-gate ena = ena ? ena : fm_ena_generate(0, FM_ENA_FMT1); 2890*7c478bd9Sstevel@tonic-gate 2891*7c478bd9Sstevel@tonic-gate DEBUG1(DBG_ERR_INTR, dip, "pcix_ereport_post: ereport_post: %s", buf); 2892*7c478bd9Sstevel@tonic-gate 2893*7c478bd9Sstevel@tonic-gate ddi_fm_ereport_post(dip, pbm_err->pbm_err_class, ena, DDI_NOSLEEP, 2894*7c478bd9Sstevel@tonic-gate FM_VERSION, DATA_TYPE_UINT8, 0, 2895*7c478bd9Sstevel@tonic-gate PCI_CONFIG_STATUS, DATA_TYPE_UINT16, pbm_err->pbm_pci.pci_cfg_stat, 2896*7c478bd9Sstevel@tonic-gate PCI_CONFIG_COMMAND, DATA_TYPE_UINT16, pbm_err->pbm_pci.pci_cfg_comm, 2897*7c478bd9Sstevel@tonic-gate PCI_PBM_CSR, DATA_TYPE_UINT64, pbm_err->pbm_ctl_stat, 2898*7c478bd9Sstevel@tonic-gate PCI_PBM_AFSR, DATA_TYPE_UINT64, pbm_err->pbm_afsr, 2899*7c478bd9Sstevel@tonic-gate PCI_PBM_AFAR, DATA_TYPE_UINT64, pbm_err->pbm_afar, 2900*7c478bd9Sstevel@tonic-gate PCI_PBM_SLOT, DATA_TYPE_UINT64, pbm_err->pbm_err_sl, 2901*7c478bd9Sstevel@tonic-gate PCIX_STAT, DATA_TYPE_UINT64, pbm_err->pbm_pcix_stat, 2902*7c478bd9Sstevel@tonic-gate PCIX_PFAR, DATA_TYPE_UINT32, pbm_err->pbm_pcix_pfar, 2903*7c478bd9Sstevel@tonic-gate NULL); 2904*7c478bd9Sstevel@tonic-gate } 2905*7c478bd9Sstevel@tonic-gate 2906*7c478bd9Sstevel@tonic-gate static void 2907*7c478bd9Sstevel@tonic-gate iommu_ctx_free(iommu_t *iommu_p) 2908*7c478bd9Sstevel@tonic-gate { 2909*7c478bd9Sstevel@tonic-gate kmem_free(iommu_p->iommu_ctx_bitmap, IOMMU_CTX_BITMAP_SIZE); 2910*7c478bd9Sstevel@tonic-gate } 2911*7c478bd9Sstevel@tonic-gate 2912*7c478bd9Sstevel@tonic-gate /* 2913*7c478bd9Sstevel@tonic-gate * iommu_tlb_scrub(): 2914*7c478bd9Sstevel@tonic-gate * Exam TLB entries through TLB diagnostic registers and look for errors. 2915*7c478bd9Sstevel@tonic-gate * scrub = 1 : cleanup all error bits in tlb, called in FAULT_RESET case 2916*7c478bd9Sstevel@tonic-gate * scrub = 0 : log all error conditions to console, FAULT_LOG case 2917*7c478bd9Sstevel@tonic-gate * In both cases, it returns number of errors found in tlb entries. 2918*7c478bd9Sstevel@tonic-gate */ 2919*7c478bd9Sstevel@tonic-gate static int 2920*7c478bd9Sstevel@tonic-gate iommu_tlb_scrub(iommu_t *iommu_p, int scrub) 2921*7c478bd9Sstevel@tonic-gate { 2922*7c478bd9Sstevel@tonic-gate int i, nerr = 0; 2923*7c478bd9Sstevel@tonic-gate dev_info_t *dip = iommu_p->iommu_pci_p->pci_dip; 2924*7c478bd9Sstevel@tonic-gate char *neg = "not "; 2925*7c478bd9Sstevel@tonic-gate 2926*7c478bd9Sstevel@tonic-gate uint64_t base = (uint64_t)iommu_p->iommu_ctrl_reg - 2927*7c478bd9Sstevel@tonic-gate COMMON_IOMMU_CTRL_REG_OFFSET; 2928*7c478bd9Sstevel@tonic-gate 2929*7c478bd9Sstevel@tonic-gate volatile uint64_t *tlb_tag = (volatile uint64_t *) 2930*7c478bd9Sstevel@tonic-gate (base + COMMON_IOMMU_TLB_TAG_DIAG_ACC_OFFSET); 2931*7c478bd9Sstevel@tonic-gate volatile uint64_t *tlb_data = (volatile uint64_t *) 2932*7c478bd9Sstevel@tonic-gate (base + COMMON_IOMMU_TLB_DATA_DIAG_ACC_OFFSET); 2933*7c478bd9Sstevel@tonic-gate for (i = 0; i < IOMMU_TLB_ENTRIES; i++) { 2934*7c478bd9Sstevel@tonic-gate uint64_t tag = tlb_tag[i]; 2935*7c478bd9Sstevel@tonic-gate uint64_t data = tlb_data[i]; 2936*7c478bd9Sstevel@tonic-gate uint32_t errstat; 2937*7c478bd9Sstevel@tonic-gate iopfn_t pfn; 2938*7c478bd9Sstevel@tonic-gate 2939*7c478bd9Sstevel@tonic-gate if (!(tag & TLBTAG_ERR_BIT)) 2940*7c478bd9Sstevel@tonic-gate continue; 2941*7c478bd9Sstevel@tonic-gate 2942*7c478bd9Sstevel@tonic-gate pfn = (iopfn_t)(data & TLBDATA_MEMPA_BITS); 2943*7c478bd9Sstevel@tonic-gate errstat = (uint32_t) 2944*7c478bd9Sstevel@tonic-gate ((tag & TLBTAG_ERRSTAT_BITS) >> TLBTAG_ERRSTAT_SHIFT); 2945*7c478bd9Sstevel@tonic-gate if (errstat == TLBTAG_ERRSTAT_INVALID) { 2946*7c478bd9Sstevel@tonic-gate if (scrub) 2947*7c478bd9Sstevel@tonic-gate tlb_tag[i] = tlb_data[i] = 0ull; 2948*7c478bd9Sstevel@tonic-gate } else 2949*7c478bd9Sstevel@tonic-gate nerr++; 2950*7c478bd9Sstevel@tonic-gate 2951*7c478bd9Sstevel@tonic-gate if (scrub) 2952*7c478bd9Sstevel@tonic-gate continue; 2953*7c478bd9Sstevel@tonic-gate 2954*7c478bd9Sstevel@tonic-gate cmn_err(CE_CONT, "%s%d: Error %x on IOMMU TLB entry %x:\n" 2955*7c478bd9Sstevel@tonic-gate "\tContext=%x %sWritable %sStreamable\n" 2956*7c478bd9Sstevel@tonic-gate "\tPCI Page Size=%sk Address in page %x\n", 2957*7c478bd9Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip), errstat, i, 2958*7c478bd9Sstevel@tonic-gate (tag & TLBTAG_CONTEXT_BITS) >> TLBTAG_CONTEXT_SHIFT, 2959*7c478bd9Sstevel@tonic-gate (tag & TLBTAG_WRITABLE_BIT) ? "" : neg, 2960*7c478bd9Sstevel@tonic-gate (tag & TLBTAG_STREAM_BIT) ? "" : neg, 2961*7c478bd9Sstevel@tonic-gate (tag & TLBTAG_PGSIZE_BIT) ? "64" : "8", 2962*7c478bd9Sstevel@tonic-gate (tag & TLBTAG_PCIVPN_BITS) << 13); 2963*7c478bd9Sstevel@tonic-gate cmn_err(CE_CONT, "Memory: %sValid %sCacheable Page Frame=%x\n", 2964*7c478bd9Sstevel@tonic-gate (data & TLBDATA_VALID_BIT) ? "" : neg, 2965*7c478bd9Sstevel@tonic-gate (data & TLBDATA_CACHE_BIT) ? "" : neg, pfn); 2966*7c478bd9Sstevel@tonic-gate } 2967*7c478bd9Sstevel@tonic-gate return (nerr); 2968*7c478bd9Sstevel@tonic-gate } 2969*7c478bd9Sstevel@tonic-gate 2970*7c478bd9Sstevel@tonic-gate /* 2971*7c478bd9Sstevel@tonic-gate * pci_iommu_disp: calculates the displacement needed in tomatillo's 2972*7c478bd9Sstevel@tonic-gate * iommu control register and modifies the control value template 2973*7c478bd9Sstevel@tonic-gate * from caller. It also clears any error status bit that are new 2974*7c478bd9Sstevel@tonic-gate * in tomatillo. 2975*7c478bd9Sstevel@tonic-gate * return value: an 8-bit mask to enable corresponding 512 MB segments 2976*7c478bd9Sstevel@tonic-gate * suitable for tomatillo's target address register. 2977*7c478bd9Sstevel@tonic-gate * 0x00: no programming is needed, use existing value from prom 2978*7c478bd9Sstevel@tonic-gate * 0x60: use segment 5 and 6 to form a 1GB dvma range 2979*7c478bd9Sstevel@tonic-gate */ 2980*7c478bd9Sstevel@tonic-gate static uint64_t 2981*7c478bd9Sstevel@tonic-gate pci_iommu_disp(iommu_t *iommu_p, uint64_t *ctl_p) 2982*7c478bd9Sstevel@tonic-gate { 2983*7c478bd9Sstevel@tonic-gate uint64_t ctl_old; 2984*7c478bd9Sstevel@tonic-gate if (CHIP_TYPE(iommu_p->iommu_pci_p) != PCI_CHIP_TOMATILLO) 2985*7c478bd9Sstevel@tonic-gate return (0); 2986*7c478bd9Sstevel@tonic-gate 2987*7c478bd9Sstevel@tonic-gate ctl_old = *iommu_p->iommu_ctrl_reg; 2988*7c478bd9Sstevel@tonic-gate /* iommu ctrl reg error bits are W1C */ 2989*7c478bd9Sstevel@tonic-gate if (ctl_old >> TOMATIILO_IOMMU_ERR_REG_SHIFT) { 2990*7c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "Tomatillo iommu err: %x", ctl_old); 2991*7c478bd9Sstevel@tonic-gate *ctl_p |= (ctl_old >> TOMATIILO_IOMMU_ERR_REG_SHIFT) 2992*7c478bd9Sstevel@tonic-gate << TOMATIILO_IOMMU_ERR_REG_SHIFT; 2993*7c478bd9Sstevel@tonic-gate } 2994*7c478bd9Sstevel@tonic-gate 2995*7c478bd9Sstevel@tonic-gate if (iommu_p->iommu_tsb_size != TOMATILLO_IOMMU_TSB_MAX) 2996*7c478bd9Sstevel@tonic-gate return (0); 2997*7c478bd9Sstevel@tonic-gate 2998*7c478bd9Sstevel@tonic-gate /* Tomatillo 2.0 and later, and 1GB DVMA range */ 2999*7c478bd9Sstevel@tonic-gate *ctl_p |= 1 << TOMATILLO_IOMMU_SEG_DISP_SHIFT; 3000*7c478bd9Sstevel@tonic-gate return (3 << (iommu_p->iommu_dvma_base >> (32 - 3))); 3001*7c478bd9Sstevel@tonic-gate } 3002*7c478bd9Sstevel@tonic-gate 3003*7c478bd9Sstevel@tonic-gate void 3004*7c478bd9Sstevel@tonic-gate pci_iommu_config(iommu_t *iommu_p, uint64_t iommu_ctl, uint64_t cfgpa) 3005*7c478bd9Sstevel@tonic-gate { 3006*7c478bd9Sstevel@tonic-gate uintptr_t pbm_regbase = get_pbm_reg_base(iommu_p->iommu_pci_p); 3007*7c478bd9Sstevel@tonic-gate volatile uint64_t *pbm_csr_p = (volatile uint64_t *)pbm_regbase; 3008*7c478bd9Sstevel@tonic-gate volatile uint64_t *tgt_space_p = (volatile uint64_t *)(pbm_regbase | 3009*7c478bd9Sstevel@tonic-gate (TOMATILLO_TGT_ADDR_SPACE_OFFSET - SCHIZO_PCI_CTRL_REG_OFFSET)); 3010*7c478bd9Sstevel@tonic-gate volatile uint64_t pbm_ctl = *pbm_csr_p; 3011*7c478bd9Sstevel@tonic-gate 3012*7c478bd9Sstevel@tonic-gate volatile uint64_t *iommu_ctl_p = iommu_p->iommu_ctrl_reg; 3013*7c478bd9Sstevel@tonic-gate volatile uint64_t tsb_bar_val = iommu_p->iommu_tsb_paddr; 3014*7c478bd9Sstevel@tonic-gate volatile uint64_t *tsb_bar_p = iommu_p->iommu_tsb_base_addr_reg; 3015*7c478bd9Sstevel@tonic-gate uint64_t mask = pci_iommu_disp(iommu_p, &iommu_ctl); 3016*7c478bd9Sstevel@tonic-gate 3017*7c478bd9Sstevel@tonic-gate DEBUG2(DBG_ATTACH, iommu_p->iommu_pci_p->pci_dip, 3018*7c478bd9Sstevel@tonic-gate "\npci_iommu_config: pbm_csr_p=%llx pbm_ctl=%llx", 3019*7c478bd9Sstevel@tonic-gate pbm_csr_p, pbm_ctl); 3020*7c478bd9Sstevel@tonic-gate DEBUG2(DBG_ATTACH|DBG_CONT, iommu_p->iommu_pci_p->pci_dip, 3021*7c478bd9Sstevel@tonic-gate "\n\tiommu_ctl_p=%llx iommu_ctl=%llx", 3022*7c478bd9Sstevel@tonic-gate iommu_ctl_p, iommu_ctl); 3023*7c478bd9Sstevel@tonic-gate DEBUG4(DBG_ATTACH|DBG_CONT, iommu_p->iommu_pci_p->pci_dip, 3024*7c478bd9Sstevel@tonic-gate "\n\tcfgpa=%llx tgt_space_p=%llx mask=%x tsb=%llx\n", 3025*7c478bd9Sstevel@tonic-gate cfgpa, tgt_space_p, mask, tsb_bar_val); 3026*7c478bd9Sstevel@tonic-gate 3027*7c478bd9Sstevel@tonic-gate if (!cfgpa) 3028*7c478bd9Sstevel@tonic-gate goto reprog; 3029*7c478bd9Sstevel@tonic-gate 3030*7c478bd9Sstevel@tonic-gate /* disable PBM arbiters - turn off bits 0-7 */ 3031*7c478bd9Sstevel@tonic-gate *pbm_csr_p = (pbm_ctl >> 8) << 8; 3032*7c478bd9Sstevel@tonic-gate 3033*7c478bd9Sstevel@tonic-gate /* 3034*7c478bd9Sstevel@tonic-gate * For non-XMITS, flush any previous writes. This is only 3035*7c478bd9Sstevel@tonic-gate * necessary for host bridges that may have a USB keywboard 3036*7c478bd9Sstevel@tonic-gate * attached. XMITS does not. 3037*7c478bd9Sstevel@tonic-gate */ 3038*7c478bd9Sstevel@tonic-gate if (!(CHIP_TYPE(iommu_p->iommu_pci_p) == PCI_CHIP_XMITS)) 3039*7c478bd9Sstevel@tonic-gate (void) ldphysio(cfgpa); 3040*7c478bd9Sstevel@tonic-gate 3041*7c478bd9Sstevel@tonic-gate reprog: 3042*7c478bd9Sstevel@tonic-gate if (mask) 3043*7c478bd9Sstevel@tonic-gate *tgt_space_p = mask; 3044*7c478bd9Sstevel@tonic-gate 3045*7c478bd9Sstevel@tonic-gate *tsb_bar_p = tsb_bar_val; 3046*7c478bd9Sstevel@tonic-gate *iommu_ctl_p = iommu_ctl; 3047*7c478bd9Sstevel@tonic-gate 3048*7c478bd9Sstevel@tonic-gate *pbm_csr_p = pbm_ctl; /* re-enable bus arbitration */ 3049*7c478bd9Sstevel@tonic-gate pbm_ctl = *pbm_csr_p; /* flush all prev writes */ 3050*7c478bd9Sstevel@tonic-gate } 3051*7c478bd9Sstevel@tonic-gate 3052*7c478bd9Sstevel@tonic-gate 3053*7c478bd9Sstevel@tonic-gate int 3054*7c478bd9Sstevel@tonic-gate pci_get_portid(dev_info_t *dip) 3055*7c478bd9Sstevel@tonic-gate { 3056*7c478bd9Sstevel@tonic-gate return (ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 3057*7c478bd9Sstevel@tonic-gate "portid", -1)); 3058*7c478bd9Sstevel@tonic-gate } 3059*7c478bd9Sstevel@tonic-gate 3060*7c478bd9Sstevel@tonic-gate /* 3061*7c478bd9Sstevel@tonic-gate * Schizo Safari Performance Events. 3062*7c478bd9Sstevel@tonic-gate */ 3063*7c478bd9Sstevel@tonic-gate pci_kev_mask_t 3064*7c478bd9Sstevel@tonic-gate schizo_saf_events[] = { 3065*7c478bd9Sstevel@tonic-gate {"saf_bus_cycles", 0x1}, {"saf_pause_asserted_cycles", 0x2}, 3066*7c478bd9Sstevel@tonic-gate {"saf_frn_coherent_cmds", 0x3}, {"saf_frn_coherent_hits", 0x4}, 3067*7c478bd9Sstevel@tonic-gate {"saf_my_coherent_cmds", 0x5}, {"saf_my_coherent_hits", 0x6}, 3068*7c478bd9Sstevel@tonic-gate {"saf_frn_io_cmds", 0x7}, {"saf_frn_io_hits", 0x8}, 3069*7c478bd9Sstevel@tonic-gate {"merge_buffer", 0x9}, {"interrupts", 0xa}, 3070*7c478bd9Sstevel@tonic-gate {"csr_pios", 0xc}, {"upa_pios", 0xd}, 3071*7c478bd9Sstevel@tonic-gate {"pcia_pios", 0xe}, {"pcib_pios", 0xf}, 3072*7c478bd9Sstevel@tonic-gate {"saf_pause_seen_cycles", 0x11}, {"dvma_reads", 0x12}, 3073*7c478bd9Sstevel@tonic-gate {"dvma_writes", 0x13}, {"saf_orq_full_cycles", 0x14}, 3074*7c478bd9Sstevel@tonic-gate {"saf_data_in_cycles", 0x15}, {"saf_data_out_cycles", 0x16}, 3075*7c478bd9Sstevel@tonic-gate {"clear_pic", 0x1f} 3076*7c478bd9Sstevel@tonic-gate }; 3077*7c478bd9Sstevel@tonic-gate 3078*7c478bd9Sstevel@tonic-gate 3079*7c478bd9Sstevel@tonic-gate /* 3080*7c478bd9Sstevel@tonic-gate * Schizo PCI Performance Events. 3081*7c478bd9Sstevel@tonic-gate */ 3082*7c478bd9Sstevel@tonic-gate pci_kev_mask_t 3083*7c478bd9Sstevel@tonic-gate schizo_pci_events[] = { 3084*7c478bd9Sstevel@tonic-gate {"dvma_stream_rd", 0x0}, {"dvma_stream_wr", 0x1}, 3085*7c478bd9Sstevel@tonic-gate {"dvma_const_rd", 0x2}, {"dvma_const_wr", 0x3}, 3086*7c478bd9Sstevel@tonic-gate {"dvma_stream_buf_mis", 0x4}, {"dvma_cycles", 0x5}, 3087*7c478bd9Sstevel@tonic-gate {"dvma_wd_xfr", 0x6}, {"pio_cycles", 0x7}, 3088*7c478bd9Sstevel@tonic-gate {"dvma_tlb_misses", 0x10}, {"interrupts", 0x11}, 3089*7c478bd9Sstevel@tonic-gate {"saf_inter_nack", 0x12}, {"pio_reads", 0x13}, 3090*7c478bd9Sstevel@tonic-gate {"pio_writes", 0x14}, {"dvma_rd_buf_timeout", 0x15}, 3091*7c478bd9Sstevel@tonic-gate {"dvma_rd_rtry_stc", 0x16}, {"dvma_wr_rtry_stc", 0x17}, 3092*7c478bd9Sstevel@tonic-gate {"dvma_rd_rtry_nonstc", 0x18}, {"dvma_wr_rtry_nonstc", 0x19}, 3093*7c478bd9Sstevel@tonic-gate {"E*_slow_transitions", 0x1a}, {"E*_slow_cycles_per_64", 0x1b}, 3094*7c478bd9Sstevel@tonic-gate {"clear_pic", 0x1f} 3095*7c478bd9Sstevel@tonic-gate }; 3096*7c478bd9Sstevel@tonic-gate 3097*7c478bd9Sstevel@tonic-gate 3098*7c478bd9Sstevel@tonic-gate /* 3099*7c478bd9Sstevel@tonic-gate * Create the picN kstats for the pci 3100*7c478bd9Sstevel@tonic-gate * and safari events. 3101*7c478bd9Sstevel@tonic-gate */ 3102*7c478bd9Sstevel@tonic-gate void 3103*7c478bd9Sstevel@tonic-gate pci_kstat_init() 3104*7c478bd9Sstevel@tonic-gate { 3105*7c478bd9Sstevel@tonic-gate pci_name_kstat = (pci_ksinfo_t *)kmem_alloc(sizeof (pci_ksinfo_t), 3106*7c478bd9Sstevel@tonic-gate KM_NOSLEEP); 3107*7c478bd9Sstevel@tonic-gate 3108*7c478bd9Sstevel@tonic-gate if (pci_name_kstat == NULL) { 3109*7c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "pcisch : no space for kstat\n"); 3110*7c478bd9Sstevel@tonic-gate } else { 3111*7c478bd9Sstevel@tonic-gate pci_name_kstat->pic_no_evs = 3112*7c478bd9Sstevel@tonic-gate sizeof (schizo_pci_events) / sizeof (pci_kev_mask_t); 3113*7c478bd9Sstevel@tonic-gate pci_name_kstat->pic_shift[0] = SCHIZO_SHIFT_PIC0; 3114*7c478bd9Sstevel@tonic-gate pci_name_kstat->pic_shift[1] = SCHIZO_SHIFT_PIC1; 3115*7c478bd9Sstevel@tonic-gate pci_create_name_kstat("pcis", 3116*7c478bd9Sstevel@tonic-gate pci_name_kstat, schizo_pci_events); 3117*7c478bd9Sstevel@tonic-gate } 3118*7c478bd9Sstevel@tonic-gate 3119*7c478bd9Sstevel@tonic-gate saf_name_kstat = (pci_ksinfo_t *)kmem_alloc(sizeof (pci_ksinfo_t), 3120*7c478bd9Sstevel@tonic-gate KM_NOSLEEP); 3121*7c478bd9Sstevel@tonic-gate if (saf_name_kstat == NULL) { 3122*7c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "pcisch : no space for kstat\n"); 3123*7c478bd9Sstevel@tonic-gate } else { 3124*7c478bd9Sstevel@tonic-gate saf_name_kstat->pic_no_evs = 3125*7c478bd9Sstevel@tonic-gate sizeof (schizo_saf_events) / sizeof (pci_kev_mask_t); 3126*7c478bd9Sstevel@tonic-gate saf_name_kstat->pic_shift[0] = SCHIZO_SHIFT_PIC0; 3127*7c478bd9Sstevel@tonic-gate saf_name_kstat->pic_shift[1] = SCHIZO_SHIFT_PIC1; 3128*7c478bd9Sstevel@tonic-gate pci_create_name_kstat("saf", saf_name_kstat, schizo_saf_events); 3129*7c478bd9Sstevel@tonic-gate } 3130*7c478bd9Sstevel@tonic-gate } 3131*7c478bd9Sstevel@tonic-gate 3132*7c478bd9Sstevel@tonic-gate void 3133*7c478bd9Sstevel@tonic-gate pci_kstat_fini() 3134*7c478bd9Sstevel@tonic-gate { 3135*7c478bd9Sstevel@tonic-gate if (pci_name_kstat != NULL) { 3136*7c478bd9Sstevel@tonic-gate pci_delete_name_kstat(pci_name_kstat); 3137*7c478bd9Sstevel@tonic-gate kmem_free(pci_name_kstat, sizeof (pci_ksinfo_t)); 3138*7c478bd9Sstevel@tonic-gate pci_name_kstat = NULL; 3139*7c478bd9Sstevel@tonic-gate } 3140*7c478bd9Sstevel@tonic-gate 3141*7c478bd9Sstevel@tonic-gate if (saf_name_kstat != NULL) { 3142*7c478bd9Sstevel@tonic-gate pci_delete_name_kstat(saf_name_kstat); 3143*7c478bd9Sstevel@tonic-gate kmem_free(saf_name_kstat, sizeof (pci_ksinfo_t)); 3144*7c478bd9Sstevel@tonic-gate saf_name_kstat = NULL; 3145*7c478bd9Sstevel@tonic-gate } 3146*7c478bd9Sstevel@tonic-gate } 3147*7c478bd9Sstevel@tonic-gate 3148*7c478bd9Sstevel@tonic-gate /* 3149*7c478bd9Sstevel@tonic-gate * Create 'counters' kstat for pci events. 3150*7c478bd9Sstevel@tonic-gate */ 3151*7c478bd9Sstevel@tonic-gate void 3152*7c478bd9Sstevel@tonic-gate pci_add_pci_kstat(pci_t *pci_p) 3153*7c478bd9Sstevel@tonic-gate { 3154*7c478bd9Sstevel@tonic-gate pci_cntr_addr_t *cntr_addr_p = &pci_p->pci_ks_addr; 3155*7c478bd9Sstevel@tonic-gate uintptr_t regbase = (uintptr_t)pci_p->pci_address[0]; 3156*7c478bd9Sstevel@tonic-gate 3157*7c478bd9Sstevel@tonic-gate cntr_addr_p->pcr_addr = (uint64_t *) 3158*7c478bd9Sstevel@tonic-gate (regbase + SCHIZO_PERF_PCI_PCR_OFFSET); 3159*7c478bd9Sstevel@tonic-gate cntr_addr_p->pic_addr = (uint64_t *) 3160*7c478bd9Sstevel@tonic-gate (regbase + SCHIZO_PERF_PCI_PIC_OFFSET); 3161*7c478bd9Sstevel@tonic-gate 3162*7c478bd9Sstevel@tonic-gate pci_p->pci_ksp = pci_create_cntr_kstat(pci_p, "pcis", 3163*7c478bd9Sstevel@tonic-gate NUM_OF_PICS, pci_cntr_kstat_update, cntr_addr_p); 3164*7c478bd9Sstevel@tonic-gate 3165*7c478bd9Sstevel@tonic-gate if (pci_p->pci_ksp == NULL) { 3166*7c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "pcisch : cannot create counter kstat"); 3167*7c478bd9Sstevel@tonic-gate } 3168*7c478bd9Sstevel@tonic-gate } 3169*7c478bd9Sstevel@tonic-gate 3170*7c478bd9Sstevel@tonic-gate void 3171*7c478bd9Sstevel@tonic-gate pci_rem_pci_kstat(pci_t *pci_p) 3172*7c478bd9Sstevel@tonic-gate { 3173*7c478bd9Sstevel@tonic-gate if (pci_p->pci_ksp != NULL) 3174*7c478bd9Sstevel@tonic-gate kstat_delete(pci_p->pci_ksp); 3175*7c478bd9Sstevel@tonic-gate pci_p->pci_ksp = NULL; 3176*7c478bd9Sstevel@tonic-gate } 3177*7c478bd9Sstevel@tonic-gate 3178*7c478bd9Sstevel@tonic-gate void 3179*7c478bd9Sstevel@tonic-gate pci_add_upstream_kstat(pci_t *pci_p) 3180*7c478bd9Sstevel@tonic-gate { 3181*7c478bd9Sstevel@tonic-gate pci_common_t *cmn_p = pci_p->pci_common_p; 3182*7c478bd9Sstevel@tonic-gate pci_cntr_pa_t *cntr_pa_p = &cmn_p->pci_cmn_uks_pa; 3183*7c478bd9Sstevel@tonic-gate uint64_t regbase = va_to_pa(pci_p->pci_address[1]); 3184*7c478bd9Sstevel@tonic-gate 3185*7c478bd9Sstevel@tonic-gate cntr_pa_p->pcr_pa = 3186*7c478bd9Sstevel@tonic-gate regbase + SCHIZO_PERF_SAF_PCR_OFFSET; 3187*7c478bd9Sstevel@tonic-gate cntr_pa_p->pic_pa = 3188*7c478bd9Sstevel@tonic-gate regbase + SCHIZO_PERF_SAF_PIC_OFFSET; 3189*7c478bd9Sstevel@tonic-gate 3190*7c478bd9Sstevel@tonic-gate cmn_p->pci_common_uksp = pci_create_cntr_kstat(pci_p, "saf", 3191*7c478bd9Sstevel@tonic-gate NUM_OF_PICS, pci_cntr_kstat_pa_update, cntr_pa_p); 3192*7c478bd9Sstevel@tonic-gate } 3193*7c478bd9Sstevel@tonic-gate 3194*7c478bd9Sstevel@tonic-gate /* 3195*7c478bd9Sstevel@tonic-gate * Extract the drivers binding name to identify which chip 3196*7c478bd9Sstevel@tonic-gate * we're binding to. Whenever a new bus bridge is created, the driver alias 3197*7c478bd9Sstevel@tonic-gate * entry should be added here to identify the device if needed. If a device 3198*7c478bd9Sstevel@tonic-gate * isn't added, the identity defaults to PCI_CHIP_UNIDENTIFIED. 3199*7c478bd9Sstevel@tonic-gate */ 3200*7c478bd9Sstevel@tonic-gate static uint32_t 3201*7c478bd9Sstevel@tonic-gate pci_identity_init(pci_t *pci_p) 3202*7c478bd9Sstevel@tonic-gate { 3203*7c478bd9Sstevel@tonic-gate dev_info_t *dip = pci_p->pci_dip; 3204*7c478bd9Sstevel@tonic-gate char *name = ddi_binding_name(dip); 3205*7c478bd9Sstevel@tonic-gate uint32_t ver = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 3206*7c478bd9Sstevel@tonic-gate "version#", 0); 3207*7c478bd9Sstevel@tonic-gate 3208*7c478bd9Sstevel@tonic-gate if (strcmp(name, "pci108e,a801") == 0) 3209*7c478bd9Sstevel@tonic-gate return (CHIP_ID(PCI_CHIP_TOMATILLO, ver, 0x00)); 3210*7c478bd9Sstevel@tonic-gate 3211*7c478bd9Sstevel@tonic-gate if (strcmp(name, "pci108e,8001") == 0) 3212*7c478bd9Sstevel@tonic-gate return (CHIP_ID(PCI_CHIP_SCHIZO, ver, 0x00)); 3213*7c478bd9Sstevel@tonic-gate 3214*7c478bd9Sstevel@tonic-gate if (strcmp(name, "pci108e,8002") == 0) { 3215*7c478bd9Sstevel@tonic-gate uint32_t mod_rev = ddi_prop_get_int(DDI_DEV_T_ANY, dip, 3216*7c478bd9Sstevel@tonic-gate DDI_PROP_DONTPASS, "module-revision#", 0); 3217*7c478bd9Sstevel@tonic-gate return (CHIP_ID(PCI_CHIP_XMITS, ver, mod_rev)); 3218*7c478bd9Sstevel@tonic-gate } 3219*7c478bd9Sstevel@tonic-gate 3220*7c478bd9Sstevel@tonic-gate cmn_err(CE_WARN, "%s%d: Unknown PCI Host bridge %s %x\n", 3221*7c478bd9Sstevel@tonic-gate ddi_driver_name(dip), ddi_get_instance(dip), name, ver); 3222*7c478bd9Sstevel@tonic-gate 3223*7c478bd9Sstevel@tonic-gate return (PCI_CHIP_UNIDENTIFIED); 3224*7c478bd9Sstevel@tonic-gate } 3225*7c478bd9Sstevel@tonic-gate 3226*7c478bd9Sstevel@tonic-gate /* 3227*7c478bd9Sstevel@tonic-gate * Setup a physical pointer to one leaf config space area. This 3228*7c478bd9Sstevel@tonic-gate * is used in several places in order to do a dummy read which 3229*7c478bd9Sstevel@tonic-gate * guarantees the nexus (and not a bus master) has gained control 3230*7c478bd9Sstevel@tonic-gate * of the bus. 3231*7c478bd9Sstevel@tonic-gate */ 3232*7c478bd9Sstevel@tonic-gate static void 3233*7c478bd9Sstevel@tonic-gate pci_setup_cfgpa(pci_t *pci_p) 3234*7c478bd9Sstevel@tonic-gate { 3235*7c478bd9Sstevel@tonic-gate dev_info_t *dip = pci_p->pci_dip; 3236*7c478bd9Sstevel@tonic-gate dev_info_t *cdip; 3237*7c478bd9Sstevel@tonic-gate pbm_t *pbm_p = pci_p->pci_pbm_p; 3238*7c478bd9Sstevel@tonic-gate uint64_t cfgpa = pci_get_cfg_pabase(pci_p); 3239*7c478bd9Sstevel@tonic-gate uint32_t *reg_p; 3240*7c478bd9Sstevel@tonic-gate int reg_len; 3241*7c478bd9Sstevel@tonic-gate 3242*7c478bd9Sstevel@tonic-gate for (cdip = ddi_get_child(dip); cdip != NULL; 3243*7c478bd9Sstevel@tonic-gate cdip = ddi_get_next_sibling(cdip)) { 3244*7c478bd9Sstevel@tonic-gate if (ddi_getlongprop(DDI_DEV_T_NONE, cdip, DDI_PROP_DONTPASS, 3245*7c478bd9Sstevel@tonic-gate "reg", (caddr_t)®_p, ®_len) != DDI_PROP_SUCCESS) 3246*7c478bd9Sstevel@tonic-gate continue; 3247*7c478bd9Sstevel@tonic-gate cfgpa += (*reg_p) & (PCI_CONF_ADDR_MASK ^ PCI_REG_REG_M); 3248*7c478bd9Sstevel@tonic-gate kmem_free(reg_p, reg_len); 3249*7c478bd9Sstevel@tonic-gate break; 3250*7c478bd9Sstevel@tonic-gate } 3251*7c478bd9Sstevel@tonic-gate pbm_p->pbm_anychild_cfgpa = cfgpa; 3252*7c478bd9Sstevel@tonic-gate } 3253*7c478bd9Sstevel@tonic-gate 3254*7c478bd9Sstevel@tonic-gate void 3255*7c478bd9Sstevel@tonic-gate pci_post_init_child(pci_t *pci_p, dev_info_t *child) 3256*7c478bd9Sstevel@tonic-gate { 3257*7c478bd9Sstevel@tonic-gate volatile uint64_t *ctrl_reg_p; 3258*7c478bd9Sstevel@tonic-gate pbm_t *pbm_p = pci_p->pci_pbm_p; 3259*7c478bd9Sstevel@tonic-gate 3260*7c478bd9Sstevel@tonic-gate pci_setup_cfgpa(pci_p); 3261*7c478bd9Sstevel@tonic-gate 3262*7c478bd9Sstevel@tonic-gate /* 3263*7c478bd9Sstevel@tonic-gate * This is a hack for skyhawk/casinni combination to address 3264*7c478bd9Sstevel@tonic-gate * hardware problems between the request and grant signals which 3265*7c478bd9Sstevel@tonic-gate * causes a bus hang. One workaround, which is applied here, 3266*7c478bd9Sstevel@tonic-gate * is to disable bus parking if the child contains the property 3267*7c478bd9Sstevel@tonic-gate * pci-req-removal. Note that if the bus is quiesced we must mask 3268*7c478bd9Sstevel@tonic-gate * off the parking bit in the saved control registers, since the 3269*7c478bd9Sstevel@tonic-gate * quiesce operation temporarily turns off PCI bus parking. 3270*7c478bd9Sstevel@tonic-gate */ 3271*7c478bd9Sstevel@tonic-gate if (ddi_prop_exists(DDI_DEV_T_ANY, child, DDI_PROP_DONTPASS, 3272*7c478bd9Sstevel@tonic-gate "pci-req-removal") == 1) { 3273*7c478bd9Sstevel@tonic-gate 3274*7c478bd9Sstevel@tonic-gate if (pbm_p->pbm_quiesce_count > 0) { 3275*7c478bd9Sstevel@tonic-gate pbm_p->pbm_saved_ctrl_reg &= ~SCHIZO_PCI_CTRL_ARB_PARK; 3276*7c478bd9Sstevel@tonic-gate } else { 3277*7c478bd9Sstevel@tonic-gate ctrl_reg_p = pbm_p->pbm_ctrl_reg; 3278*7c478bd9Sstevel@tonic-gate *ctrl_reg_p &= ~SCHIZO_PCI_CTRL_ARB_PARK; 3279*7c478bd9Sstevel@tonic-gate } 3280*7c478bd9Sstevel@tonic-gate } 3281*7c478bd9Sstevel@tonic-gate 3282*7c478bd9Sstevel@tonic-gate if (CHIP_TYPE(pci_p) == PCI_CHIP_XMITS) { 3283*7c478bd9Sstevel@tonic-gate if (*pbm_p->pbm_ctrl_reg & XMITS_PCI_CTRL_X_MODE) { 3284*7c478bd9Sstevel@tonic-gate int value; 3285*7c478bd9Sstevel@tonic-gate 3286*7c478bd9Sstevel@tonic-gate /* 3287*7c478bd9Sstevel@tonic-gate * Due to a XMITS bug, we need to set the outstanding 3288*7c478bd9Sstevel@tonic-gate * split transactions to 1 for all PCI-X functions 3289*7c478bd9Sstevel@tonic-gate * behind the leaf. 3290*7c478bd9Sstevel@tonic-gate */ 3291*7c478bd9Sstevel@tonic-gate value = (xmits_max_transactions << 4) | 3292*7c478bd9Sstevel@tonic-gate (xmits_max_read_bytes << 2); 3293*7c478bd9Sstevel@tonic-gate 3294*7c478bd9Sstevel@tonic-gate DEBUG1(DBG_INIT_CLD, child, "Turning on XMITS NCPQ " 3295*7c478bd9Sstevel@tonic-gate "Workaround: value = %x\n", value); 3296*7c478bd9Sstevel@tonic-gate 3297*7c478bd9Sstevel@tonic-gate pcix_set_cmd_reg(child, value); 3298*7c478bd9Sstevel@tonic-gate 3299*7c478bd9Sstevel@tonic-gate (void) ndi_prop_update_int(DDI_DEV_T_NONE, 3300*7c478bd9Sstevel@tonic-gate child, "pcix-update-cmd-reg", value); 3301*7c478bd9Sstevel@tonic-gate } 3302*7c478bd9Sstevel@tonic-gate } 3303*7c478bd9Sstevel@tonic-gate } 3304*7c478bd9Sstevel@tonic-gate 3305*7c478bd9Sstevel@tonic-gate void 3306*7c478bd9Sstevel@tonic-gate pci_post_uninit_child(pci_t *pci_p) 3307*7c478bd9Sstevel@tonic-gate { 3308*7c478bd9Sstevel@tonic-gate pci_setup_cfgpa(pci_p); 3309*7c478bd9Sstevel@tonic-gate } 3310*7c478bd9Sstevel@tonic-gate 3311*7c478bd9Sstevel@tonic-gate static int 3312*7c478bd9Sstevel@tonic-gate pci_tom_nbintr_op(pci_t *pci_p, uint32_t inum, intrfunc f, caddr_t arg, 3313*7c478bd9Sstevel@tonic-gate int flag) 3314*7c478bd9Sstevel@tonic-gate { 3315*7c478bd9Sstevel@tonic-gate uint32_t ino = pci_p->pci_inos[inum]; 3316*7c478bd9Sstevel@tonic-gate uint32_t mondo = IB_INO_TO_NBMONDO(pci_p->pci_ib_p, ino); 3317*7c478bd9Sstevel@tonic-gate int ret = DDI_SUCCESS; 3318*7c478bd9Sstevel@tonic-gate 3319*7c478bd9Sstevel@tonic-gate mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); /* no op on tom */ 3320*7c478bd9Sstevel@tonic-gate 3321*7c478bd9Sstevel@tonic-gate switch (flag) { 3322*7c478bd9Sstevel@tonic-gate case PCI_OBJ_INTR_ADD: 3323*7c478bd9Sstevel@tonic-gate VERIFY(add_ivintr(mondo, pci_pil[inum], f, arg, NULL) == 0); 3324*7c478bd9Sstevel@tonic-gate break; 3325*7c478bd9Sstevel@tonic-gate case PCI_OBJ_INTR_REMOVE: 3326*7c478bd9Sstevel@tonic-gate rem_ivintr(mondo, NULL); 3327*7c478bd9Sstevel@tonic-gate break; 3328*7c478bd9Sstevel@tonic-gate default: 3329*7c478bd9Sstevel@tonic-gate ret = DDI_FAILURE; 3330*7c478bd9Sstevel@tonic-gate break; 3331*7c478bd9Sstevel@tonic-gate } 3332*7c478bd9Sstevel@tonic-gate 3333*7c478bd9Sstevel@tonic-gate return (ret); 3334*7c478bd9Sstevel@tonic-gate } 3335*7c478bd9Sstevel@tonic-gate 3336*7c478bd9Sstevel@tonic-gate int 3337*7c478bd9Sstevel@tonic-gate pci_ecc_add_intr(pci_t *pci_p, int inum, ecc_intr_info_t *eii_p) 3338*7c478bd9Sstevel@tonic-gate { 3339*7c478bd9Sstevel@tonic-gate uint32_t mondo; 3340*7c478bd9Sstevel@tonic-gate int r; 3341*7c478bd9Sstevel@tonic-gate 3342*7c478bd9Sstevel@tonic-gate mondo = ((pci_p->pci_cb_p->cb_ign << PCI_INO_BITS) | 3343*7c478bd9Sstevel@tonic-gate pci_p->pci_inos[inum]); 3344*7c478bd9Sstevel@tonic-gate mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 3345*7c478bd9Sstevel@tonic-gate 3346*7c478bd9Sstevel@tonic-gate VERIFY(add_ivintr(mondo, pci_pil[inum], ecc_intr, 3347*7c478bd9Sstevel@tonic-gate (caddr_t)eii_p, NULL) == 0); 3348*7c478bd9Sstevel@tonic-gate 3349*7c478bd9Sstevel@tonic-gate if (CHIP_TYPE(pci_p) != PCI_CHIP_TOMATILLO) 3350*7c478bd9Sstevel@tonic-gate return (PCI_ATTACH_RETCODE(PCI_ECC_OBJ, PCI_OBJ_INTR_ADD, 3351*7c478bd9Sstevel@tonic-gate DDI_SUCCESS)); 3352*7c478bd9Sstevel@tonic-gate 3353*7c478bd9Sstevel@tonic-gate r = pci_tom_nbintr_op(pci_p, inum, ecc_intr, 3354*7c478bd9Sstevel@tonic-gate (caddr_t)eii_p, PCI_OBJ_INTR_ADD); 3355*7c478bd9Sstevel@tonic-gate return (PCI_ATTACH_RETCODE(PCI_ECC_OBJ, PCI_OBJ_INTR_ADD, r)); 3356*7c478bd9Sstevel@tonic-gate } 3357*7c478bd9Sstevel@tonic-gate 3358*7c478bd9Sstevel@tonic-gate void 3359*7c478bd9Sstevel@tonic-gate pci_ecc_rem_intr(pci_t *pci_p, int inum, ecc_intr_info_t *eii_p) 3360*7c478bd9Sstevel@tonic-gate { 3361*7c478bd9Sstevel@tonic-gate uint32_t mondo; 3362*7c478bd9Sstevel@tonic-gate 3363*7c478bd9Sstevel@tonic-gate mondo = ((pci_p->pci_cb_p->cb_ign << PCI_INO_BITS) | 3364*7c478bd9Sstevel@tonic-gate pci_p->pci_inos[inum]); 3365*7c478bd9Sstevel@tonic-gate mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 3366*7c478bd9Sstevel@tonic-gate 3367*7c478bd9Sstevel@tonic-gate rem_ivintr(mondo, NULL); 3368*7c478bd9Sstevel@tonic-gate 3369*7c478bd9Sstevel@tonic-gate if (CHIP_TYPE(pci_p) == PCI_CHIP_TOMATILLO) 3370*7c478bd9Sstevel@tonic-gate pci_tom_nbintr_op(pci_p, inum, ecc_intr, 3371*7c478bd9Sstevel@tonic-gate (caddr_t)eii_p, PCI_OBJ_INTR_REMOVE); 3372*7c478bd9Sstevel@tonic-gate } 3373*7c478bd9Sstevel@tonic-gate 3374*7c478bd9Sstevel@tonic-gate static uint_t 3375*7c478bd9Sstevel@tonic-gate pci_pbm_cdma_intr(caddr_t a) 3376*7c478bd9Sstevel@tonic-gate { 3377*7c478bd9Sstevel@tonic-gate pbm_t *pbm_p = (pbm_t *)a; 3378*7c478bd9Sstevel@tonic-gate pbm_p->pbm_cdma_flag = PBM_CDMA_DONE; 3379*7c478bd9Sstevel@tonic-gate #ifdef PBM_CDMA_DEBUG 3380*7c478bd9Sstevel@tonic-gate pbm_p->pbm_cdma_intr_cnt++; 3381*7c478bd9Sstevel@tonic-gate #endif /* PBM_CDMA_DEBUG */ 3382*7c478bd9Sstevel@tonic-gate return (DDI_INTR_CLAIMED); 3383*7c478bd9Sstevel@tonic-gate } 3384*7c478bd9Sstevel@tonic-gate 3385*7c478bd9Sstevel@tonic-gate int 3386*7c478bd9Sstevel@tonic-gate pci_pbm_add_intr(pci_t *pci_p) 3387*7c478bd9Sstevel@tonic-gate { 3388*7c478bd9Sstevel@tonic-gate uint32_t mondo; 3389*7c478bd9Sstevel@tonic-gate 3390*7c478bd9Sstevel@tonic-gate mondo = IB_INO_TO_MONDO(pci_p->pci_ib_p, pci_p->pci_inos[CBNINTR_CDMA]); 3391*7c478bd9Sstevel@tonic-gate mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 3392*7c478bd9Sstevel@tonic-gate 3393*7c478bd9Sstevel@tonic-gate VERIFY(add_ivintr(mondo, pci_pil[CBNINTR_CDMA], 3394*7c478bd9Sstevel@tonic-gate pci_pbm_cdma_intr, (caddr_t)pci_p->pci_pbm_p, NULL) == 0); 3395*7c478bd9Sstevel@tonic-gate 3396*7c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 3397*7c478bd9Sstevel@tonic-gate } 3398*7c478bd9Sstevel@tonic-gate 3399*7c478bd9Sstevel@tonic-gate void 3400*7c478bd9Sstevel@tonic-gate pci_pbm_rem_intr(pci_t *pci_p) 3401*7c478bd9Sstevel@tonic-gate { 3402*7c478bd9Sstevel@tonic-gate ib_t *ib_p = pci_p->pci_ib_p; 3403*7c478bd9Sstevel@tonic-gate uint32_t mondo; 3404*7c478bd9Sstevel@tonic-gate 3405*7c478bd9Sstevel@tonic-gate mondo = IB_INO_TO_MONDO(pci_p->pci_ib_p, pci_p->pci_inos[CBNINTR_CDMA]); 3406*7c478bd9Sstevel@tonic-gate mondo = CB_MONDO_TO_XMONDO(pci_p->pci_cb_p, mondo); 3407*7c478bd9Sstevel@tonic-gate 3408*7c478bd9Sstevel@tonic-gate ib_intr_disable(ib_p, pci_p->pci_inos[CBNINTR_CDMA], IB_INTR_NOWAIT); 3409*7c478bd9Sstevel@tonic-gate rem_ivintr(mondo, NULL); 3410*7c478bd9Sstevel@tonic-gate } 3411*7c478bd9Sstevel@tonic-gate 3412*7c478bd9Sstevel@tonic-gate void 3413*7c478bd9Sstevel@tonic-gate pci_pbm_suspend(pci_t *pci_p) 3414*7c478bd9Sstevel@tonic-gate { 3415*7c478bd9Sstevel@tonic-gate pbm_t *pbm_p = pci_p->pci_pbm_p; 3416*7c478bd9Sstevel@tonic-gate ib_ino_t ino = pci_p->pci_inos[CBNINTR_CDMA]; 3417*7c478bd9Sstevel@tonic-gate 3418*7c478bd9Sstevel@tonic-gate /* Save CDMA interrupt state */ 3419*7c478bd9Sstevel@tonic-gate pbm_p->pbm_cdma_imr_save = *ib_intr_map_reg_addr(pci_p->pci_ib_p, ino); 3420*7c478bd9Sstevel@tonic-gate } 3421*7c478bd9Sstevel@tonic-gate 3422*7c478bd9Sstevel@tonic-gate void 3423*7c478bd9Sstevel@tonic-gate pci_pbm_resume(pci_t *pci_p) 3424*7c478bd9Sstevel@tonic-gate { 3425*7c478bd9Sstevel@tonic-gate pbm_t *pbm_p = pci_p->pci_pbm_p; 3426*7c478bd9Sstevel@tonic-gate ib_ino_t ino = pci_p->pci_inos[CBNINTR_CDMA]; 3427*7c478bd9Sstevel@tonic-gate 3428*7c478bd9Sstevel@tonic-gate /* Restore CDMA interrupt state */ 3429*7c478bd9Sstevel@tonic-gate *ib_intr_map_reg_addr(pci_p->pci_ib_p, ino) = pbm_p->pbm_cdma_imr_save; 3430*7c478bd9Sstevel@tonic-gate } 3431*7c478bd9Sstevel@tonic-gate 3432*7c478bd9Sstevel@tonic-gate /* 3433*7c478bd9Sstevel@tonic-gate * pci_bus_quiesce 3434*7c478bd9Sstevel@tonic-gate * 3435*7c478bd9Sstevel@tonic-gate * This function is called as the corresponding control ops routine 3436*7c478bd9Sstevel@tonic-gate * to a DDI_CTLOPS_QUIESCE command. Its mission is to halt all DMA 3437*7c478bd9Sstevel@tonic-gate * activity on the bus by disabling arbitration/parking. 3438*7c478bd9Sstevel@tonic-gate */ 3439*7c478bd9Sstevel@tonic-gate int 3440*7c478bd9Sstevel@tonic-gate pci_bus_quiesce(pci_t *pci_p, dev_info_t *dip, void *result) 3441*7c478bd9Sstevel@tonic-gate { 3442*7c478bd9Sstevel@tonic-gate volatile uint64_t *ctrl_reg_p; 3443*7c478bd9Sstevel@tonic-gate volatile uint64_t ctrl_reg; 3444*7c478bd9Sstevel@tonic-gate pbm_t *pbm_p; 3445*7c478bd9Sstevel@tonic-gate 3446*7c478bd9Sstevel@tonic-gate pbm_p = pci_p->pci_pbm_p; 3447*7c478bd9Sstevel@tonic-gate ctrl_reg_p = pbm_p->pbm_ctrl_reg; 3448*7c478bd9Sstevel@tonic-gate 3449*7c478bd9Sstevel@tonic-gate if (pbm_p->pbm_quiesce_count++ == 0) { 3450*7c478bd9Sstevel@tonic-gate 3451*7c478bd9Sstevel@tonic-gate DEBUG0(DBG_PWR, dip, "quiescing bus\n"); 3452*7c478bd9Sstevel@tonic-gate 3453*7c478bd9Sstevel@tonic-gate ctrl_reg = *ctrl_reg_p; 3454*7c478bd9Sstevel@tonic-gate pbm_p->pbm_saved_ctrl_reg = ctrl_reg; 3455*7c478bd9Sstevel@tonic-gate ctrl_reg &= ~(SCHIZO_PCI_CTRL_ARB_EN_MASK | 3456*7c478bd9Sstevel@tonic-gate SCHIZO_PCI_CTRL_ARB_PARK); 3457*7c478bd9Sstevel@tonic-gate *ctrl_reg_p = ctrl_reg; 3458*7c478bd9Sstevel@tonic-gate #ifdef DEBUG 3459*7c478bd9Sstevel@tonic-gate ctrl_reg = *ctrl_reg_p; 3460*7c478bd9Sstevel@tonic-gate if ((ctrl_reg & (SCHIZO_PCI_CTRL_ARB_EN_MASK | 3461*7c478bd9Sstevel@tonic-gate SCHIZO_PCI_CTRL_ARB_PARK)) != 0) 3462*7c478bd9Sstevel@tonic-gate panic("ctrl_reg didn't quiesce: 0x%x\n", ctrl_reg); 3463*7c478bd9Sstevel@tonic-gate #endif 3464*7c478bd9Sstevel@tonic-gate if (pbm_p->pbm_anychild_cfgpa) 3465*7c478bd9Sstevel@tonic-gate (void) ldphysio(pbm_p->pbm_anychild_cfgpa); 3466*7c478bd9Sstevel@tonic-gate } 3467*7c478bd9Sstevel@tonic-gate 3468*7c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 3469*7c478bd9Sstevel@tonic-gate } 3470*7c478bd9Sstevel@tonic-gate 3471*7c478bd9Sstevel@tonic-gate /* 3472*7c478bd9Sstevel@tonic-gate * pci_bus_unquiesce 3473*7c478bd9Sstevel@tonic-gate * 3474*7c478bd9Sstevel@tonic-gate * This function is called as the corresponding control ops routine 3475*7c478bd9Sstevel@tonic-gate * to a DDI_CTLOPS_UNQUIESCE command. Its mission is to resume paused 3476*7c478bd9Sstevel@tonic-gate * DMA activity on the bus by re-enabling arbitration (and maybe parking). 3477*7c478bd9Sstevel@tonic-gate */ 3478*7c478bd9Sstevel@tonic-gate int 3479*7c478bd9Sstevel@tonic-gate pci_bus_unquiesce(pci_t *pci_p, dev_info_t *dip, void *result) 3480*7c478bd9Sstevel@tonic-gate { 3481*7c478bd9Sstevel@tonic-gate volatile uint64_t *ctrl_reg_p; 3482*7c478bd9Sstevel@tonic-gate pbm_t *pbm_p; 3483*7c478bd9Sstevel@tonic-gate #ifdef DEBUG 3484*7c478bd9Sstevel@tonic-gate volatile uint64_t ctrl_reg; 3485*7c478bd9Sstevel@tonic-gate #endif 3486*7c478bd9Sstevel@tonic-gate 3487*7c478bd9Sstevel@tonic-gate pbm_p = pci_p->pci_pbm_p; 3488*7c478bd9Sstevel@tonic-gate ctrl_reg_p = pbm_p->pbm_ctrl_reg; 3489*7c478bd9Sstevel@tonic-gate 3490*7c478bd9Sstevel@tonic-gate ASSERT(pbm_p->pbm_quiesce_count > 0); 3491*7c478bd9Sstevel@tonic-gate if (--pbm_p->pbm_quiesce_count == 0) { 3492*7c478bd9Sstevel@tonic-gate *ctrl_reg_p = pbm_p->pbm_saved_ctrl_reg; 3493*7c478bd9Sstevel@tonic-gate #ifdef DEBUG 3494*7c478bd9Sstevel@tonic-gate ctrl_reg = *ctrl_reg_p; 3495*7c478bd9Sstevel@tonic-gate if ((ctrl_reg & (SCHIZO_PCI_CTRL_ARB_EN_MASK | 3496*7c478bd9Sstevel@tonic-gate SCHIZO_PCI_CTRL_ARB_PARK)) == 0) 3497*7c478bd9Sstevel@tonic-gate panic("ctrl_reg didn't unquiesce: 0x%x\n", ctrl_reg); 3498*7c478bd9Sstevel@tonic-gate #endif 3499*7c478bd9Sstevel@tonic-gate } 3500*7c478bd9Sstevel@tonic-gate 3501*7c478bd9Sstevel@tonic-gate return (DDI_SUCCESS); 3502*7c478bd9Sstevel@tonic-gate } 3503*7c478bd9Sstevel@tonic-gate 3504*7c478bd9Sstevel@tonic-gate static void 3505*7c478bd9Sstevel@tonic-gate tm_vmem_free(ddi_dma_impl_t *mp, iommu_t *iommu_p, dvma_addr_t dvma_pg, 3506*7c478bd9Sstevel@tonic-gate int npages) 3507*7c478bd9Sstevel@tonic-gate { 3508*7c478bd9Sstevel@tonic-gate uint32_t dur_max, dur_base; 3509*7c478bd9Sstevel@tonic-gate dvma_unbind_req_t *req_p, *req_max_p; 3510*7c478bd9Sstevel@tonic-gate dvma_unbind_req_t *req_base_p = iommu_p->iommu_mtlb_req_p; 3511*7c478bd9Sstevel@tonic-gate uint32_t tlb_vpn[IOMMU_TLB_ENTRIES]; 3512*7c478bd9Sstevel@tonic-gate caddr_t reg_base; 3513*7c478bd9Sstevel@tonic-gate volatile uint64_t *tag_p; 3514*7c478bd9Sstevel@tonic-gate int i, preserv_count = 0; 3515*7c478bd9Sstevel@tonic-gate 3516*7c478bd9Sstevel@tonic-gate mutex_enter(&iommu_p->iommu_mtlb_lock); 3517*7c478bd9Sstevel@tonic-gate 3518*7c478bd9Sstevel@tonic-gate iommu_p->iommu_mtlb_npgs += npages; 3519*7c478bd9Sstevel@tonic-gate req_max_p = req_base_p + iommu_p->iommu_mtlb_nreq++; 3520*7c478bd9Sstevel@tonic-gate req_max_p->dur_npg = npages; 3521*7c478bd9Sstevel@tonic-gate req_max_p->dur_base = dvma_pg; 3522*7c478bd9Sstevel@tonic-gate req_max_p->dur_flags = mp->dmai_flags & DMAI_FLAGS_VMEMCACHE; 3523*7c478bd9Sstevel@tonic-gate 3524*7c478bd9Sstevel@tonic-gate 3525*7c478bd9Sstevel@tonic-gate if (iommu_p->iommu_mtlb_npgs <= iommu_p->iommu_mtlb_maxpgs) 3526*7c478bd9Sstevel@tonic-gate goto done; 3527*7c478bd9Sstevel@tonic-gate 3528*7c478bd9Sstevel@tonic-gate /* read TLB */ 3529*7c478bd9Sstevel@tonic-gate reg_base = iommu_p->iommu_pci_p->pci_address[0]; 3530*7c478bd9Sstevel@tonic-gate tag_p = (volatile uint64_t *) 3531*7c478bd9Sstevel@tonic-gate (reg_base + COMMON_IOMMU_TLB_TAG_DIAG_ACC_OFFSET); 3532*7c478bd9Sstevel@tonic-gate 3533*7c478bd9Sstevel@tonic-gate for (i = 0; i < IOMMU_TLB_ENTRIES; i++) 3534*7c478bd9Sstevel@tonic-gate tlb_vpn[i] = tag_p[i] & SCHIZO_VPN_MASK; 3535*7c478bd9Sstevel@tonic-gate 3536*7c478bd9Sstevel@tonic-gate /* for each request search the TLB for a matching address */ 3537*7c478bd9Sstevel@tonic-gate for (req_p = req_base_p; req_p <= req_max_p; req_p++) { 3538*7c478bd9Sstevel@tonic-gate dur_base = req_p->dur_base; 3539*7c478bd9Sstevel@tonic-gate dur_max = req_p->dur_base + req_p->dur_npg; 3540*7c478bd9Sstevel@tonic-gate 3541*7c478bd9Sstevel@tonic-gate for (i = 0; i < IOMMU_TLB_ENTRIES; i++) { 3542*7c478bd9Sstevel@tonic-gate uint_t vpn = tlb_vpn[i]; 3543*7c478bd9Sstevel@tonic-gate if (vpn >= dur_base && vpn < dur_max) 3544*7c478bd9Sstevel@tonic-gate break; 3545*7c478bd9Sstevel@tonic-gate } 3546*7c478bd9Sstevel@tonic-gate if (i >= IOMMU_TLB_ENTRIES) { 3547*7c478bd9Sstevel@tonic-gate pci_vmem_do_free(iommu_p, 3548*7c478bd9Sstevel@tonic-gate (void *)IOMMU_PTOB(req_p->dur_base), 3549*7c478bd9Sstevel@tonic-gate req_p->dur_npg, req_p->dur_flags); 3550*7c478bd9Sstevel@tonic-gate iommu_p->iommu_mtlb_npgs -= req_p->dur_npg; 3551*7c478bd9Sstevel@tonic-gate continue; 3552*7c478bd9Sstevel@tonic-gate } 3553*7c478bd9Sstevel@tonic-gate /* if an empty slot exists */ 3554*7c478bd9Sstevel@tonic-gate if ((req_p - req_base_p) != preserv_count) 3555*7c478bd9Sstevel@tonic-gate *(req_base_p + preserv_count) = *req_p; 3556*7c478bd9Sstevel@tonic-gate preserv_count++; 3557*7c478bd9Sstevel@tonic-gate } 3558*7c478bd9Sstevel@tonic-gate 3559*7c478bd9Sstevel@tonic-gate iommu_p->iommu_mtlb_nreq = preserv_count; 3560*7c478bd9Sstevel@tonic-gate done: 3561*7c478bd9Sstevel@tonic-gate mutex_exit(&iommu_p->iommu_mtlb_lock); 3562*7c478bd9Sstevel@tonic-gate } 3563*7c478bd9Sstevel@tonic-gate 3564*7c478bd9Sstevel@tonic-gate void 3565*7c478bd9Sstevel@tonic-gate pci_vmem_free(iommu_t *iommu_p, ddi_dma_impl_t *mp, void *dvma_addr, 3566*7c478bd9Sstevel@tonic-gate size_t npages) 3567*7c478bd9Sstevel@tonic-gate { 3568*7c478bd9Sstevel@tonic-gate if (tm_mtlb_gc) 3569*7c478bd9Sstevel@tonic-gate tm_vmem_free(mp, iommu_p, 3570*7c478bd9Sstevel@tonic-gate (dvma_addr_t)IOMMU_BTOP((dvma_addr_t)dvma_addr), npages); 3571*7c478bd9Sstevel@tonic-gate else 3572*7c478bd9Sstevel@tonic-gate pci_vmem_do_free(iommu_p, dvma_addr, npages, 3573*7c478bd9Sstevel@tonic-gate (mp->dmai_flags & DMAI_FLAGS_VMEMCACHE)); 3574*7c478bd9Sstevel@tonic-gate } 3575