1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 /* 26 * All Rights Reserved, Copyright (c) FUJITSU LIMITED 2006 27 */ 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #include <sys/types.h> 32 #include <sys/sysmacros.h> 33 #include <sys/conf.h> 34 #include <sys/modctl.h> 35 #include <sys/stat.h> 36 #include <sys/async.h> 37 #include <sys/machcpuvar.h> 38 #include <sys/machsystm.h> 39 #include <sys/promif.h> 40 #include <sys/ksynch.h> 41 #include <sys/ddi.h> 42 #include <sys/sunddi.h> 43 #include <sys/ddifm.h> 44 #include <sys/fm/protocol.h> 45 #include <sys/fm/util.h> 46 #include <sys/kmem.h> 47 #include <sys/fm/io/opl_mc_fm.h> 48 #include <sys/memlist.h> 49 #include <sys/param.h> 50 #include <sys/disp.h> 51 #include <sys/ontrap.h> 52 #include <vm/page.h> 53 #include <sys/mc-opl.h> 54 #include <sys/opl.h> 55 #include <sys/opl_dimm.h> 56 #include <sys/scfd/scfostoescf.h> 57 58 /* 59 * Function prototypes 60 */ 61 static int mc_open(dev_t *, int, int, cred_t *); 62 static int mc_close(dev_t, int, int, cred_t *); 63 static int mc_ioctl(dev_t, int, intptr_t, int, cred_t *, int *); 64 static int mc_attach(dev_info_t *, ddi_attach_cmd_t); 65 static int mc_detach(dev_info_t *, ddi_detach_cmd_t); 66 67 static int mc_poll_init(void); 68 static void mc_poll_fini(void); 69 static int mc_board_add(mc_opl_t *mcp); 70 static int mc_board_del(mc_opl_t *mcp); 71 static int mc_suspend(mc_opl_t *mcp, uint32_t flag); 72 static int mc_resume(mc_opl_t *mcp, uint32_t flag); 73 int opl_mc_suspend(void); 74 int opl_mc_resume(void); 75 76 static void insert_mcp(mc_opl_t *mcp); 77 static void delete_mcp(mc_opl_t *mcp); 78 79 static int pa_to_maddr(mc_opl_t *mcp, uint64_t pa, mc_addr_t *maddr); 80 81 static int mc_valid_pa(mc_opl_t *mcp, uint64_t pa); 82 83 int mc_get_mem_unum(int, uint64_t, char *, int, int *); 84 int mc_get_mem_addr(char *unum, char *sid, uint64_t offset, uint64_t *paddr); 85 int mc_get_mem_offset(uint64_t paddr, uint64_t *offp); 86 int mc_get_mem_sid(char *unum, char *buf, int buflen, int *lenp); 87 int mc_get_mem_sid_dimm(mc_opl_t *mcp, char *dname, char *buf, 88 int buflen, int *lenp); 89 mc_dimm_info_t *mc_get_dimm_list(mc_opl_t *mcp); 90 mc_dimm_info_t *mc_prepare_dimmlist(board_dimm_info_t *bd_dimmp); 91 int mc_set_mem_sid(mc_opl_t *mcp, char *buf, int buflen, int lsb, int bank, 92 uint32_t mf_type, uint32_t d_slot); 93 static void mc_free_dimm_list(mc_dimm_info_t *d); 94 static void mc_get_mlist(mc_opl_t *); 95 static void mc_polling(void); 96 static int mc_opl_get_physical_board(int); 97 98 #ifdef DEBUG 99 static int mc_ioctl_debug(dev_t, int, intptr_t, int, cred_t *, int *); 100 void mc_dump_dimm(char *buf, int dnamesz, int serialsz, int partnumsz); 101 void mc_dump_dimm_info(board_dimm_info_t *bd_dimmp); 102 #endif 103 104 #pragma weak opl_get_physical_board 105 extern int opl_get_physical_board(int); 106 extern int plat_max_boards(void); 107 108 /* 109 * Configuration data structures 110 */ 111 static struct cb_ops mc_cb_ops = { 112 mc_open, /* open */ 113 mc_close, /* close */ 114 nulldev, /* strategy */ 115 nulldev, /* print */ 116 nodev, /* dump */ 117 nulldev, /* read */ 118 nulldev, /* write */ 119 mc_ioctl, /* ioctl */ 120 nodev, /* devmap */ 121 nodev, /* mmap */ 122 nodev, /* segmap */ 123 nochpoll, /* poll */ 124 ddi_prop_op, /* cb_prop_op */ 125 0, /* streamtab */ 126 D_MP | D_NEW | D_HOTPLUG, /* Driver compatibility flag */ 127 CB_REV, /* rev */ 128 nodev, /* cb_aread */ 129 nodev /* cb_awrite */ 130 }; 131 132 static struct dev_ops mc_ops = { 133 DEVO_REV, /* rev */ 134 0, /* refcnt */ 135 ddi_getinfo_1to1, /* getinfo */ 136 nulldev, /* identify */ 137 nulldev, /* probe */ 138 mc_attach, /* attach */ 139 mc_detach, /* detach */ 140 nulldev, /* reset */ 141 &mc_cb_ops, /* cb_ops */ 142 (struct bus_ops *)0, /* bus_ops */ 143 nulldev /* power */ 144 }; 145 146 /* 147 * Driver globals 148 */ 149 150 static enum { 151 MODEL_FF1 = 0, 152 MODEL_FF2 = 1, 153 MODEL_DC = 2 154 } plat_model = MODEL_DC; /* The default behaviour is DC */ 155 156 static struct plat_model_names { 157 const char *unit_name; 158 const char *mem_name; 159 } model_names[] = { 160 { "MBU_A", "MEMB" }, 161 { "MBU_B", "MEMB" }, 162 { "CMU", "" } 163 }; 164 165 /* 166 * The DIMM Names for DC platform. 167 * The index into this table is made up of (bank, dslot), 168 * Where dslot occupies bits 0-1 and bank occupies 2-4. 169 */ 170 static char *mc_dc_dimm_unum_table[OPL_MAX_DIMMS] = { 171 /* --------CMUnn----------- */ 172 /* --CS0-----|--CS1------ */ 173 /* -H-|--L-- | -H- | -L-- */ 174 "03A", "02A", "03B", "02B", /* MAC 0 bank 0 */ 175 "13A", "12A", "13B", "12B", /* MAC 0 bank 1 */ 176 "23A", "22A", "23B", "22B", /* MAC 1 bank 2 */ 177 "33A", "32A", "33B", "32B", /* MAC 1 bank 3 */ 178 "01A", "00A", "01B", "00B", /* MAC 2 bank 4 */ 179 "11A", "10A", "11B", "10B", /* MAC 2 bank 5 */ 180 "21A", "20A", "21B", "20B", /* MAC 3 bank 6 */ 181 "31A", "30A", "31B", "30B" /* MAC 3 bank 7 */ 182 }; 183 184 /* 185 * The DIMM Names for FF1/FF2 platforms. 186 * The index into this table is made up of (board, bank, dslot), 187 * Where dslot occupies bits 0-1, bank occupies 2-4 and 188 * board occupies the bit 5. 189 */ 190 static char *mc_ff_dimm_unum_table[2 * OPL_MAX_DIMMS] = { 191 /* --------CMU0---------- */ 192 /* --CS0-----|--CS1------ */ 193 /* -H-|--L-- | -H- | -L-- */ 194 "03A", "02A", "03B", "02B", /* MAC 0 bank 0 */ 195 "01A", "00A", "01B", "00B", /* MAC 0 bank 1 */ 196 "13A", "12A", "13B", "12B", /* MAC 1 bank 2 */ 197 "11A", "10A", "11B", "10B", /* MAC 1 bank 3 */ 198 "23A", "20A", "23B", "20B", /* MAC 2 bank 4 */ 199 "21A", "20A", "21B", "20B", /* MAC 2 bank 5 */ 200 "33A", "32A", "33B", "32B", /* MAC 3 bank 6 */ 201 "31A", "30A", "31B", "30B", /* MAC 3 bank 7 */ 202 /* --------CMU1---------- */ 203 /* --CS0-----|--CS1------ */ 204 /* -H-|--L-- | -H- | -L-- */ 205 "43A", "42A", "43B", "42B", /* MAC 0 bank 0 */ 206 "41A", "40A", "41B", "40B", /* MAC 0 bank 1 */ 207 "53A", "52A", "53B", "50B", /* MAC 1 bank 2 */ 208 "51A", "50A", "51B", "50B", /* MAC 1 bank 3 */ 209 "63A", "62A", "63B", "62B", /* MAC 2 bank 4 */ 210 "61A", "60A", "61B", "60B", /* MAC 2 bank 5 */ 211 "73A", "72A", "73B", "72B", /* MAC 3 bank 6 */ 212 "71A", "70A", "71B", "70B" /* MAC 3 bank 7 */ 213 }; 214 215 #define BD_BK_SLOT_TO_INDEX(bd, bk, s) \ 216 (((bd & 0x01) << 5) | ((bk & 0x07) << 2) | (s & 0x03)) 217 218 #define INDEX_TO_BANK(i) (((i) & 0x1C) >> 2) 219 #define INDEX_TO_SLOT(i) ((i) & 0x03) 220 221 /* Isolation unit size is 64 MB */ 222 #define MC_ISOLATION_BSIZE (64 * 1024 * 1024) 223 224 #define MC_MAX_SPEEDS 7 225 226 /* make this a structure */ 227 228 typedef struct { 229 uint32_t mc_speeds; 230 uint32_t mc_period; 231 } mc_scan_speed_t; 232 233 #define MC_CNTL_SPEED_SHIFT 26 234 235 static mc_scan_speed_t mc_scan_speeds[MC_MAX_SPEEDS] = { 236 {0x6 << MC_CNTL_SPEED_SHIFT, 0}, 237 {0x5 << MC_CNTL_SPEED_SHIFT, 32}, 238 {0x4 << MC_CNTL_SPEED_SHIFT, 64}, 239 {0x3 << MC_CNTL_SPEED_SHIFT, 128}, 240 {0x2 << MC_CNTL_SPEED_SHIFT, 256}, 241 {0x1 << MC_CNTL_SPEED_SHIFT, 512}, 242 {0x0 << MC_CNTL_SPEED_SHIFT, 1024} 243 }; 244 245 static uint32_t mc_max_speed = (0x6 << 26); 246 247 /* we have to measure these delays */ 248 249 int mc_isolation_bsize = MC_ISOLATION_BSIZE; 250 int mc_patrol_interval_sec = MC_PATROL_INTERVAL_SEC; 251 int mc_max_scf_retry = 16; 252 int mc_max_scf_logs = 64; 253 int mc_max_errlog_processed = BANKNUM_PER_SB*2; 254 int mc_scan_period = 12 * 60 * 60; /* 12 hours period */ 255 int mc_max_rewrite_loop = 100; 256 int mc_rewrite_delay = 10; 257 /* 258 * it takes SCF about 300 m.s. to process a requst. We can bail out 259 * if it is busy. It does not pay to wait for it too long. 260 */ 261 int mc_max_scf_loop = 2; 262 int mc_scf_delay = 100; 263 int mc_pce_dropped = 0; 264 int mc_poll_priority = MINCLSYSPRI; 265 266 267 /* 268 * Mutex heierachy in mc-opl 269 * If both mcmutex and mc_lock must be held, 270 * mcmutex must be acquired first, and then mc_lock. 271 */ 272 273 static kmutex_t mcmutex; 274 mc_opl_t *mc_instances[OPL_MAX_BOARDS]; 275 276 static kmutex_t mc_polling_lock; 277 static kcondvar_t mc_polling_cv; 278 static kcondvar_t mc_poll_exit_cv; 279 static int mc_poll_cmd = 0; 280 static int mc_pollthr_running = 0; 281 int mc_timeout_period = 0; /* this is in m.s. */ 282 void *mc_statep; 283 284 #ifdef DEBUG 285 int oplmc_debug = 0; 286 #endif 287 288 static int mc_debug_show_all = 0; 289 290 extern struct mod_ops mod_driverops; 291 292 static struct modldrv modldrv = { 293 &mod_driverops, /* module type, this one is a driver */ 294 "OPL Memory-controller %I%", /* module name */ 295 &mc_ops, /* driver ops */ 296 }; 297 298 static struct modlinkage modlinkage = { 299 MODREV_1, /* rev */ 300 (void *)&modldrv, 301 NULL 302 }; 303 304 #pragma weak opl_get_mem_unum 305 #pragma weak opl_get_mem_sid 306 #pragma weak opl_get_mem_offset 307 #pragma weak opl_get_mem_addr 308 309 extern int (*opl_get_mem_unum)(int, uint64_t, char *, int, int *); 310 extern int (*opl_get_mem_sid)(char *unum, char *buf, int buflen, int *lenp); 311 extern int (*opl_get_mem_offset)(uint64_t paddr, uint64_t *offp); 312 extern int (*opl_get_mem_addr)(char *unum, char *sid, uint64_t offset, 313 uint64_t *paddr); 314 315 316 /* 317 * pseudo-mc node portid format 318 * 319 * [10] = 0 320 * [9] = 1 321 * [8] = LSB_ID[4] = 0 322 * [7:4] = LSB_ID[3:0] 323 * [3:0] = 0 324 * 325 */ 326 327 /* 328 * These are the module initialization routines. 329 */ 330 int 331 _init(void) 332 { 333 int error; 334 int plen; 335 char model[20]; 336 pnode_t node; 337 338 339 if ((error = ddi_soft_state_init(&mc_statep, 340 sizeof (mc_opl_t), 1)) != 0) 341 return (error); 342 343 if ((error = mc_poll_init()) != 0) { 344 ddi_soft_state_fini(&mc_statep); 345 return (error); 346 } 347 348 mutex_init(&mcmutex, NULL, MUTEX_DRIVER, NULL); 349 if (&opl_get_mem_unum) 350 opl_get_mem_unum = mc_get_mem_unum; 351 if (&opl_get_mem_sid) 352 opl_get_mem_sid = mc_get_mem_sid; 353 if (&opl_get_mem_offset) 354 opl_get_mem_offset = mc_get_mem_offset; 355 if (&opl_get_mem_addr) 356 opl_get_mem_addr = mc_get_mem_addr; 357 358 node = prom_rootnode(); 359 plen = prom_getproplen(node, "model"); 360 361 if (plen > 0 && plen < sizeof (model)) { 362 (void) prom_getprop(node, "model", model); 363 model[plen] = '\0'; 364 if (strcmp(model, "FF1") == 0) 365 plat_model = MODEL_FF1; 366 else if (strcmp(model, "FF2") == 0) 367 plat_model = MODEL_FF2; 368 else if (strncmp(model, "DC", 2) == 0) 369 plat_model = MODEL_DC; 370 } 371 372 error = mod_install(&modlinkage); 373 if (error != 0) { 374 if (&opl_get_mem_unum) 375 opl_get_mem_unum = NULL; 376 if (&opl_get_mem_sid) 377 opl_get_mem_sid = NULL; 378 if (&opl_get_mem_offset) 379 opl_get_mem_offset = NULL; 380 if (&opl_get_mem_addr) 381 opl_get_mem_addr = NULL; 382 mutex_destroy(&mcmutex); 383 mc_poll_fini(); 384 ddi_soft_state_fini(&mc_statep); 385 } 386 return (error); 387 } 388 389 int 390 _fini(void) 391 { 392 int error; 393 394 if ((error = mod_remove(&modlinkage)) != 0) 395 return (error); 396 397 if (&opl_get_mem_unum) 398 opl_get_mem_unum = NULL; 399 if (&opl_get_mem_sid) 400 opl_get_mem_sid = NULL; 401 if (&opl_get_mem_offset) 402 opl_get_mem_offset = NULL; 403 if (&opl_get_mem_addr) 404 opl_get_mem_addr = NULL; 405 406 mutex_destroy(&mcmutex); 407 mc_poll_fini(); 408 ddi_soft_state_fini(&mc_statep); 409 410 return (0); 411 } 412 413 int 414 _info(struct modinfo *modinfop) 415 { 416 return (mod_info(&modlinkage, modinfop)); 417 } 418 419 static void 420 mc_polling_thread() 421 { 422 mutex_enter(&mc_polling_lock); 423 mc_pollthr_running = 1; 424 while (!(mc_poll_cmd & MC_POLL_EXIT)) { 425 mc_polling(); 426 cv_timedwait(&mc_polling_cv, &mc_polling_lock, 427 ddi_get_lbolt() + mc_timeout_period); 428 } 429 mc_pollthr_running = 0; 430 431 /* 432 * signal if any one is waiting for this thread to exit. 433 */ 434 cv_signal(&mc_poll_exit_cv); 435 mutex_exit(&mc_polling_lock); 436 thread_exit(); 437 /* NOTREACHED */ 438 } 439 440 static int 441 mc_poll_init() 442 { 443 mutex_init(&mc_polling_lock, NULL, MUTEX_DRIVER, NULL); 444 cv_init(&mc_polling_cv, NULL, CV_DRIVER, NULL); 445 cv_init(&mc_poll_exit_cv, NULL, CV_DRIVER, NULL); 446 return (0); 447 } 448 449 static void 450 mc_poll_fini() 451 { 452 mutex_enter(&mc_polling_lock); 453 if (mc_pollthr_running) { 454 mc_poll_cmd = MC_POLL_EXIT; 455 cv_signal(&mc_polling_cv); 456 while (mc_pollthr_running) { 457 cv_wait(&mc_poll_exit_cv, &mc_polling_lock); 458 } 459 } 460 mutex_exit(&mc_polling_lock); 461 mutex_destroy(&mc_polling_lock); 462 cv_destroy(&mc_polling_cv); 463 cv_destroy(&mc_poll_exit_cv); 464 } 465 466 static int 467 mc_attach(dev_info_t *devi, ddi_attach_cmd_t cmd) 468 { 469 mc_opl_t *mcp; 470 int instance; 471 int rv; 472 473 /* get the instance of this devi */ 474 instance = ddi_get_instance(devi); 475 476 switch (cmd) { 477 case DDI_ATTACH: 478 break; 479 case DDI_RESUME: 480 mcp = ddi_get_soft_state(mc_statep, instance); 481 rv = mc_resume(mcp, MC_DRIVER_SUSPENDED); 482 return (rv); 483 default: 484 return (DDI_FAILURE); 485 } 486 487 if (ddi_soft_state_zalloc(mc_statep, instance) != DDI_SUCCESS) 488 return (DDI_FAILURE); 489 490 if ((mcp = ddi_get_soft_state(mc_statep, instance)) == NULL) { 491 goto bad; 492 } 493 494 if (mc_timeout_period == 0) { 495 mc_patrol_interval_sec = (int)ddi_getprop(DDI_DEV_T_ANY, devi, 496 DDI_PROP_DONTPASS, "mc-timeout-interval-sec", 497 mc_patrol_interval_sec); 498 mc_timeout_period = drv_usectohz( 499 1000000 * mc_patrol_interval_sec / OPL_MAX_BOARDS); 500 } 501 502 /* set informations in mc state */ 503 mcp->mc_dip = devi; 504 505 if (mc_board_add(mcp)) 506 goto bad; 507 508 insert_mcp(mcp); 509 510 /* 511 * Start the polling thread if it is not running already. 512 */ 513 mutex_enter(&mc_polling_lock); 514 if (!mc_pollthr_running) { 515 (void) thread_create(NULL, 0, (void (*)())mc_polling_thread, 516 NULL, 0, &p0, TS_RUN, mc_poll_priority); 517 } 518 mutex_exit(&mc_polling_lock); 519 ddi_report_dev(devi); 520 521 return (DDI_SUCCESS); 522 523 bad: 524 ddi_soft_state_free(mc_statep, instance); 525 return (DDI_FAILURE); 526 } 527 528 /* ARGSUSED */ 529 static int 530 mc_detach(dev_info_t *devi, ddi_detach_cmd_t cmd) 531 { 532 int rv; 533 int instance; 534 mc_opl_t *mcp; 535 536 /* get the instance of this devi */ 537 instance = ddi_get_instance(devi); 538 if ((mcp = ddi_get_soft_state(mc_statep, instance)) == NULL) { 539 return (DDI_FAILURE); 540 } 541 542 switch (cmd) { 543 case DDI_SUSPEND: 544 rv = mc_suspend(mcp, MC_DRIVER_SUSPENDED); 545 return (rv); 546 case DDI_DETACH: 547 break; 548 default: 549 return (DDI_FAILURE); 550 } 551 552 delete_mcp(mcp); 553 if (mc_board_del(mcp) != DDI_SUCCESS) { 554 return (DDI_FAILURE); 555 } 556 557 /* free up the soft state */ 558 ddi_soft_state_free(mc_statep, instance); 559 560 return (DDI_SUCCESS); 561 } 562 563 /* ARGSUSED */ 564 static int 565 mc_open(dev_t *devp, int flag, int otyp, cred_t *credp) 566 { 567 return (0); 568 } 569 570 /* ARGSUSED */ 571 static int 572 mc_close(dev_t devp, int flag, int otyp, cred_t *credp) 573 { 574 return (0); 575 } 576 577 /* ARGSUSED */ 578 static int 579 mc_ioctl(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp, 580 int *rvalp) 581 { 582 #ifdef DEBUG 583 return (mc_ioctl_debug(dev, cmd, arg, mode, credp, rvalp)); 584 #else 585 return (ENXIO); 586 #endif 587 } 588 589 /* 590 * PA validity check: 591 * This function return 1 if the PA is valid, otherwise 592 * return 0. 593 */ 594 595 /* ARGSUSED */ 596 static int 597 pa_is_valid(mc_opl_t *mcp, uint64_t addr) 598 { 599 /* 600 * Check if the addr is on the board. 601 */ 602 if ((addr < mcp->mc_start_address) || 603 (mcp->mc_start_address + mcp->mc_size <= addr)) 604 return (0); 605 606 if (mcp->mlist == NULL) 607 mc_get_mlist(mcp); 608 609 if (mcp->mlist && address_in_memlist(mcp->mlist, addr, 0)) { 610 return (1); 611 } 612 return (0); 613 } 614 615 /* 616 * mac-pa translation routines. 617 * 618 * Input: mc driver state, (LSB#, Bank#, DIMM address) 619 * Output: physical address 620 * 621 * Valid - return value: 0 622 * Invalid - return value: -1 623 */ 624 static int 625 mcaddr_to_pa(mc_opl_t *mcp, mc_addr_t *maddr, uint64_t *pa) 626 { 627 int i; 628 uint64_t pa_offset = 0; 629 int cs = (maddr->ma_dimm_addr >> CS_SHIFT) & 1; 630 int bank = maddr->ma_bank; 631 mc_addr_t maddr1; 632 int bank0, bank1; 633 634 MC_LOG("mcaddr /LSB%d/B%d/%x\n", maddr->ma_bd, bank, 635 maddr->ma_dimm_addr); 636 637 /* loc validity check */ 638 ASSERT(maddr->ma_bd >= 0 && OPL_BOARD_MAX > maddr->ma_bd); 639 ASSERT(bank >= 0 && OPL_BANK_MAX > bank); 640 641 /* Do translation */ 642 for (i = 0; i < PA_BITS_FOR_MAC; i++) { 643 int pa_bit = 0; 644 int mc_bit = mcp->mc_trans_table[cs][i]; 645 if (mc_bit < MC_ADDRESS_BITS) { 646 pa_bit = (maddr->ma_dimm_addr >> mc_bit) & 1; 647 } else if (mc_bit == MP_NONE) { 648 pa_bit = 0; 649 } else if (mc_bit == MP_BANK_0) { 650 pa_bit = bank & 1; 651 } else if (mc_bit == MP_BANK_1) { 652 pa_bit = (bank >> 1) & 1; 653 } else if (mc_bit == MP_BANK_2) { 654 pa_bit = (bank >> 2) & 1; 655 } 656 pa_offset |= ((uint64_t)pa_bit) << i; 657 } 658 *pa = mcp->mc_start_address + pa_offset; 659 MC_LOG("pa = %lx\n", *pa); 660 661 if (pa_to_maddr(mcp, *pa, &maddr1) == -1) { 662 cmn_err(CE_WARN, "mcaddr_to_pa: /LSB%d/B%d/%x failed to " 663 "convert PA %lx\n", maddr->ma_bd, bank, 664 maddr->ma_dimm_addr, *pa); 665 return (-1); 666 } 667 668 /* 669 * In mirror mode, PA is always translated to the even bank. 670 */ 671 if (IS_MIRROR(mcp, maddr->ma_bank)) { 672 bank0 = maddr->ma_bank & ~(1); 673 bank1 = maddr1.ma_bank & ~(1); 674 } else { 675 bank0 = maddr->ma_bank; 676 bank1 = maddr1.ma_bank; 677 } 678 /* 679 * there is no need to check ma_bd because it is generated from 680 * mcp. They are the same. 681 */ 682 if ((bank0 == bank1) && 683 (maddr->ma_dimm_addr == maddr1.ma_dimm_addr)) { 684 return (0); 685 } else { 686 cmn_err(CE_WARN, "Translation error source /LSB%d/B%d/%x, " 687 "PA %lx, target /LSB%d/B%d/%x\n", 688 maddr->ma_bd, bank, maddr->ma_dimm_addr, 689 *pa, maddr1.ma_bd, maddr1.ma_bank, 690 maddr1.ma_dimm_addr); 691 return (-1); 692 } 693 } 694 695 /* 696 * PA to CS (used by pa_to_maddr). 697 */ 698 static int 699 pa_to_cs(mc_opl_t *mcp, uint64_t pa_offset) 700 { 701 int i; 702 int cs = 0; 703 704 for (i = 0; i < PA_BITS_FOR_MAC; i++) { 705 /* MAC address bit<29> is arranged on the same PA bit */ 706 /* on both table. So we may use any table. */ 707 if (mcp->mc_trans_table[0][i] == CS_SHIFT) { 708 cs = (pa_offset >> i) & 1; 709 break; 710 } 711 } 712 return (cs); 713 } 714 715 /* 716 * PA to DIMM (used by pa_to_maddr). 717 */ 718 /* ARGSUSED */ 719 static uint32_t 720 pa_to_dimm(mc_opl_t *mcp, uint64_t pa_offset) 721 { 722 int i; 723 int cs = pa_to_cs(mcp, pa_offset); 724 uint32_t dimm_addr = 0; 725 726 for (i = 0; i < PA_BITS_FOR_MAC; i++) { 727 int pa_bit_value = (pa_offset >> i) & 1; 728 int mc_bit = mcp->mc_trans_table[cs][i]; 729 if (mc_bit < MC_ADDRESS_BITS) { 730 dimm_addr |= pa_bit_value << mc_bit; 731 } 732 } 733 return (dimm_addr); 734 } 735 736 /* 737 * PA to Bank (used by pa_to_maddr). 738 */ 739 static int 740 pa_to_bank(mc_opl_t *mcp, uint64_t pa_offset) 741 { 742 int i; 743 int cs = pa_to_cs(mcp, pa_offset); 744 int bankno = mcp->mc_trans_table[cs][INDEX_OF_BANK_SUPPLEMENT_BIT]; 745 746 747 for (i = 0; i < PA_BITS_FOR_MAC; i++) { 748 int pa_bit_value = (pa_offset >> i) & 1; 749 int mc_bit = mcp->mc_trans_table[cs][i]; 750 switch (mc_bit) { 751 case MP_BANK_0: 752 bankno |= pa_bit_value; 753 break; 754 case MP_BANK_1: 755 bankno |= pa_bit_value << 1; 756 break; 757 case MP_BANK_2: 758 bankno |= pa_bit_value << 2; 759 break; 760 } 761 } 762 763 return (bankno); 764 } 765 766 /* 767 * PA to MAC address translation 768 * 769 * Input: MAC driver state, physicall adress 770 * Output: LSB#, Bank id, mac address 771 * 772 * Valid - return value: 0 773 * Invalid - return value: -1 774 */ 775 776 int 777 pa_to_maddr(mc_opl_t *mcp, uint64_t pa, mc_addr_t *maddr) 778 { 779 uint64_t pa_offset; 780 781 /* PA validity check */ 782 if (!pa_is_valid(mcp, pa)) 783 return (-1); 784 785 786 /* Do translation */ 787 pa_offset = pa - mcp->mc_start_address; 788 789 maddr->ma_bd = mcp->mc_board_num; 790 maddr->ma_bank = pa_to_bank(mcp, pa_offset); 791 maddr->ma_dimm_addr = pa_to_dimm(mcp, pa_offset); 792 MC_LOG("pa %lx -> mcaddr /LSB%d/B%d/%x\n", 793 pa_offset, maddr->ma_bd, maddr->ma_bank, maddr->ma_dimm_addr); 794 return (0); 795 } 796 797 /* 798 * UNUM format for DC is "/CMUnn/MEMxyZ", where 799 * nn = 00..03 for DC1 and 00..07 for DC2 and 00..15 for DC3. 800 * x = MAC 0..3 801 * y = 0..3 (slot info). 802 * Z = 'A' or 'B' 803 * 804 * UNUM format for FF1 is "/MBU_A/MEMBx/MEMyZ", where 805 * x = 0..3 (MEMB number) 806 * y = 0..3 (slot info). 807 * Z = 'A' or 'B' 808 * 809 * UNUM format for FF2 is "/MBU_B/MEMBx/MEMyZ" 810 * x = 0..7 (MEMB number) 811 * y = 0..3 (slot info). 812 * Z = 'A' or 'B' 813 */ 814 int 815 mc_set_mem_unum(char *buf, int buflen, int lsb, int bank, 816 uint32_t mf_type, uint32_t d_slot) 817 { 818 char *dimmnm; 819 char memb_num; 820 int sb; 821 int i; 822 823 if ((sb = mc_opl_get_physical_board(lsb)) < 0) 824 return (ENODEV); 825 826 if (plat_model == MODEL_DC) { 827 if (mf_type == FLT_TYPE_PERMANENT_CE) { 828 i = BD_BK_SLOT_TO_INDEX(0, bank, d_slot); 829 dimmnm = mc_dc_dimm_unum_table[i]; 830 snprintf(buf, buflen, "/%s%02d/MEM%s", 831 model_names[plat_model].unit_name, sb, dimmnm); 832 } else { 833 i = BD_BK_SLOT_TO_INDEX(0, bank, 0); 834 snprintf(buf, buflen, "/%s%02d/MEM%s MEM%s MEM%s MEM%s", 835 model_names[plat_model].unit_name, sb, 836 mc_dc_dimm_unum_table[i], 837 mc_dc_dimm_unum_table[i + 1], 838 mc_dc_dimm_unum_table[i + 2], 839 mc_dc_dimm_unum_table[i + 3]); 840 } 841 } else { 842 i = BD_BK_SLOT_TO_INDEX(sb, bank, d_slot); 843 if (mf_type == FLT_TYPE_PERMANENT_CE) { 844 dimmnm = mc_ff_dimm_unum_table[i]; 845 memb_num = dimmnm[0]; 846 snprintf(buf, buflen, "/%s/%s%c/MEM%s", 847 model_names[plat_model].unit_name, 848 model_names[plat_model].mem_name, 849 memb_num, &dimmnm[1]); 850 } else { 851 i = BD_BK_SLOT_TO_INDEX(sb, bank, 0); 852 memb_num = mc_ff_dimm_unum_table[i][0], 853 snprintf(buf, buflen, 854 "/%s/%s%c/MEM%s MEM%s MEM%s MEM%s", 855 model_names[plat_model].unit_name, 856 model_names[plat_model].mem_name, memb_num, 857 &mc_ff_dimm_unum_table[i][1], 858 &mc_ff_dimm_unum_table[i + 1][1], 859 &mc_ff_dimm_unum_table[i + 2][1], 860 &mc_ff_dimm_unum_table[i + 3][1]); 861 } 862 } 863 return (0); 864 } 865 866 static void 867 mc_ereport_post(mc_aflt_t *mc_aflt) 868 { 869 char buf[FM_MAX_CLASS]; 870 char device_path[MAXPATHLEN]; 871 char sid[MAXPATHLEN]; 872 nv_alloc_t *nva = NULL; 873 nvlist_t *ereport, *detector, *resource; 874 errorq_elem_t *eqep; 875 int nflts; 876 mc_flt_stat_t *flt_stat; 877 int i, n; 878 int blen = MAXPATHLEN; 879 char *p, *s = NULL; 880 uint32_t values[2], synd[2], dslot[2]; 881 uint64_t offset = (uint64_t)-1; 882 int ret = -1; 883 884 if (panicstr) { 885 eqep = errorq_reserve(ereport_errorq); 886 if (eqep == NULL) 887 return; 888 ereport = errorq_elem_nvl(ereport_errorq, eqep); 889 nva = errorq_elem_nva(ereport_errorq, eqep); 890 } else { 891 ereport = fm_nvlist_create(nva); 892 } 893 894 /* 895 * Create the scheme "dev" FMRI. 896 */ 897 detector = fm_nvlist_create(nva); 898 resource = fm_nvlist_create(nva); 899 900 nflts = mc_aflt->mflt_nflts; 901 902 ASSERT(nflts >= 1 && nflts <= 2); 903 904 flt_stat = mc_aflt->mflt_stat[0]; 905 (void) ddi_pathname(mc_aflt->mflt_mcp->mc_dip, device_path); 906 (void) fm_fmri_dev_set(detector, FM_DEV_SCHEME_VERSION, NULL, 907 device_path, NULL); 908 909 /* 910 * Encode all the common data into the ereport. 911 */ 912 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s-%s", 913 MC_OPL_ERROR_CLASS, 914 mc_aflt->mflt_is_ptrl ? MC_OPL_PTRL_SUBCLASS : 915 MC_OPL_MI_SUBCLASS, 916 mc_aflt->mflt_erpt_class); 917 918 MC_LOG("mc_ereport_post: ereport %s\n", buf); 919 920 921 fm_ereport_set(ereport, FM_EREPORT_VERSION, buf, 922 fm_ena_generate(mc_aflt->mflt_id, FM_ENA_FMT1), 923 detector, NULL); 924 925 /* 926 * Set payload. 927 */ 928 fm_payload_set(ereport, MC_OPL_BOARD, DATA_TYPE_UINT32, 929 flt_stat->mf_flt_maddr.ma_bd, NULL); 930 931 fm_payload_set(ereport, MC_OPL_PA, DATA_TYPE_UINT64, 932 flt_stat->mf_flt_paddr, NULL); 933 934 if (flt_stat->mf_type == FLT_TYPE_PERMANENT_CE) { 935 fm_payload_set(ereport, MC_OPL_FLT_TYPE, 936 DATA_TYPE_UINT8, ECC_STICKY, NULL); 937 } 938 939 for (i = 0; i < nflts; i++) 940 values[i] = mc_aflt->mflt_stat[i]->mf_flt_maddr.ma_bank; 941 942 fm_payload_set(ereport, MC_OPL_BANK, DATA_TYPE_UINT32_ARRAY, 943 nflts, values, NULL); 944 945 for (i = 0; i < nflts; i++) 946 values[i] = mc_aflt->mflt_stat[i]->mf_cntl; 947 948 fm_payload_set(ereport, MC_OPL_STATUS, DATA_TYPE_UINT32_ARRAY, 949 nflts, values, NULL); 950 951 for (i = 0; i < nflts; i++) 952 values[i] = mc_aflt->mflt_stat[i]->mf_err_add; 953 954 /* offset is set only for PCE */ 955 if (mc_aflt->mflt_stat[0]->mf_type == FLT_TYPE_PERMANENT_CE) { 956 offset = values[0]; 957 958 } 959 fm_payload_set(ereport, MC_OPL_ERR_ADD, DATA_TYPE_UINT32_ARRAY, 960 nflts, values, NULL); 961 962 for (i = 0; i < nflts; i++) 963 values[i] = mc_aflt->mflt_stat[i]->mf_err_log; 964 965 fm_payload_set(ereport, MC_OPL_ERR_LOG, DATA_TYPE_UINT32_ARRAY, 966 nflts, values, NULL); 967 968 for (i = 0; i < nflts; i++) { 969 flt_stat = mc_aflt->mflt_stat[i]; 970 if (flt_stat->mf_errlog_valid) { 971 synd[i] = flt_stat->mf_synd; 972 dslot[i] = flt_stat->mf_dimm_slot; 973 values[i] = flt_stat->mf_dram_place; 974 } else { 975 synd[i] = 0; 976 dslot[i] = 0; 977 values[i] = 0; 978 } 979 } 980 981 fm_payload_set(ereport, MC_OPL_ERR_SYND, 982 DATA_TYPE_UINT32_ARRAY, nflts, synd, NULL); 983 984 fm_payload_set(ereport, MC_OPL_ERR_DIMMSLOT, 985 DATA_TYPE_UINT32_ARRAY, nflts, dslot, NULL); 986 987 fm_payload_set(ereport, MC_OPL_ERR_DRAM, 988 DATA_TYPE_UINT32_ARRAY, nflts, values, NULL); 989 990 device_path[0] = 0; 991 p = &device_path[0]; 992 sid[0] = 0; 993 s = &sid[0]; 994 ret = 0; 995 996 for (i = 0; i < nflts; i++) { 997 int bank; 998 999 flt_stat = mc_aflt->mflt_stat[i]; 1000 bank = flt_stat->mf_flt_maddr.ma_bank; 1001 ret = mc_set_mem_unum(p + strlen(p), blen, 1002 flt_stat->mf_flt_maddr.ma_bd, bank, flt_stat->mf_type, 1003 flt_stat->mf_dimm_slot); 1004 1005 if (ret != 0) { 1006 cmn_err(CE_WARN, 1007 "mc_ereport_post: Failed to determine the unum " 1008 "for board=%d bank=%d type=0x%x slot=0x%x", 1009 flt_stat->mf_flt_maddr.ma_bd, bank, 1010 flt_stat->mf_type, flt_stat->mf_dimm_slot); 1011 continue; 1012 } 1013 n = strlen(device_path); 1014 blen = MAXPATHLEN - n; 1015 p = &device_path[n]; 1016 if (i < (nflts - 1)) { 1017 snprintf(p, blen, " "); 1018 blen--; 1019 p++; 1020 } 1021 1022 if (ret == 0) { 1023 ret = mc_set_mem_sid(mc_aflt->mflt_mcp, s + strlen(s), 1024 blen, flt_stat->mf_flt_maddr.ma_bd, bank, 1025 flt_stat->mf_type, flt_stat->mf_dimm_slot); 1026 1027 } 1028 } 1029 1030 (void) fm_fmri_mem_set(resource, FM_MEM_SCHEME_VERSION, 1031 NULL, device_path, (ret == 0) ? sid : NULL, 1032 (ret == 0) ? offset : (uint64_t)-1); 1033 1034 fm_payload_set(ereport, MC_OPL_RESOURCE, DATA_TYPE_NVLIST, 1035 resource, NULL); 1036 1037 if (panicstr) { 1038 errorq_commit(ereport_errorq, eqep, ERRORQ_SYNC); 1039 } else { 1040 (void) fm_ereport_post(ereport, EVCH_TRYHARD); 1041 fm_nvlist_destroy(ereport, FM_NVA_FREE); 1042 fm_nvlist_destroy(detector, FM_NVA_FREE); 1043 fm_nvlist_destroy(resource, FM_NVA_FREE); 1044 } 1045 } 1046 1047 1048 static void 1049 mc_err_drain(mc_aflt_t *mc_aflt) 1050 { 1051 int rv; 1052 page_t *pp; 1053 uint64_t errors; 1054 uint64_t pa = (uint64_t)(-1); 1055 int i; 1056 1057 MC_LOG("mc_err_drain: %s\n", 1058 mc_aflt->mflt_erpt_class); 1059 /* 1060 * we come here only when we have: 1061 * In mirror mode: CMPE, MUE, SUE 1062 * In normal mode: UE, Permanent CE 1063 */ 1064 for (i = 0; i < mc_aflt->mflt_nflts; i++) { 1065 rv = mcaddr_to_pa(mc_aflt->mflt_mcp, 1066 &(mc_aflt->mflt_stat[i]->mf_flt_maddr), &pa); 1067 if (rv == 0) 1068 mc_aflt->mflt_stat[i]->mf_flt_paddr = pa; 1069 else 1070 mc_aflt->mflt_stat[i]->mf_flt_paddr = (uint64_t)-1; 1071 } 1072 1073 if (mc_aflt->mflt_stat[0]->mf_type != FLT_TYPE_PERMANENT_CE) { 1074 MC_LOG("mc_err_drain:pa = %lx\n", pa); 1075 pp = page_numtopp_nolock(pa >> PAGESHIFT); 1076 1077 if (pp) { 1078 /* 1079 * Don't keep retiring and make ereports 1080 * on bad pages in PTRL case 1081 */ 1082 MC_LOG("mc_err_drain:pp = %p\n", pp); 1083 if (mc_aflt->mflt_is_ptrl) { 1084 errors = 0; 1085 if (page_retire_check(pa, &errors) == 0) { 1086 MC_LOG("Page retired\n"); 1087 return; 1088 } 1089 if (errors & mc_aflt->mflt_pr) { 1090 MC_LOG("errors %lx, mflt_pr %x\n", 1091 errors, mc_aflt->mflt_pr); 1092 return; 1093 } 1094 } 1095 MC_LOG("offline page %p error %x\n", pp, 1096 mc_aflt->mflt_pr); 1097 (void) page_retire(pa, mc_aflt->mflt_pr); 1098 } 1099 } 1100 1101 for (i = 0; i < mc_aflt->mflt_nflts; i++) { 1102 mc_aflt_t mc_aflt0; 1103 if (mc_aflt->mflt_stat[i]->mf_flt_paddr != (uint64_t)-1) { 1104 mc_aflt0 = *mc_aflt; 1105 mc_aflt0.mflt_nflts = 1; 1106 mc_aflt0.mflt_stat[0] = mc_aflt->mflt_stat[i]; 1107 mc_ereport_post(&mc_aflt0); 1108 } 1109 } 1110 } 1111 1112 /* 1113 * The restart address is actually defined in unit of PA[37:6] 1114 * the mac patrol will convert that to dimm offset. If the 1115 * address is not in the bank, it will continue to search for 1116 * the next PA that is within the bank. 1117 * 1118 * Also the mac patrol scans the dimms based on PA, not 1119 * dimm offset. 1120 */ 1121 static int 1122 restart_patrol(mc_opl_t *mcp, int bank, mc_addr_info_t *maddr_info) 1123 { 1124 page_t *pp; 1125 uint64_t pa; 1126 int rv; 1127 int loop_count = 0; 1128 1129 if (maddr_info == NULL || (maddr_info->mi_valid == 0)) { 1130 MAC_PTRL_START(mcp, bank); 1131 return (0); 1132 } 1133 1134 rv = mcaddr_to_pa(mcp, &maddr_info->mi_maddr, &pa); 1135 if (rv != 0) { 1136 MC_LOG("cannot convert mcaddr to pa. use auto restart\n"); 1137 MAC_PTRL_START(mcp, bank); 1138 return (0); 1139 } 1140 1141 /* 1142 * pa is the last address scanned by the mac patrol 1143 * we calculate the next restart address as follows: 1144 * first we always advance it by 64 byte. Then begin the loop. 1145 * loop { 1146 * if it is not in phys_install, we advance to next 64 MB boundary 1147 * if it is not backed by a page structure, done 1148 * if the page is bad, advance to the next page boundary. 1149 * else done 1150 * if the new address exceeds the board, wrap around. 1151 * } <stop if we come back to the same page> 1152 */ 1153 1154 if (pa < mcp->mc_start_address || pa >= (mcp->mc_start_address 1155 + mcp->mc_size)) { 1156 /* pa is not on this board, just retry */ 1157 cmn_err(CE_WARN, "restart_patrol: invalid address %lx " 1158 "on board %d\n", pa, mcp->mc_board_num); 1159 MAC_PTRL_START(mcp, bank); 1160 return (0); 1161 } 1162 1163 MC_LOG("restart_patrol: pa = %lx\n", pa); 1164 if (maddr_info->mi_advance) { 1165 uint64_t new_pa; 1166 1167 if (IS_MIRROR(mcp, bank)) 1168 new_pa = pa + 64 * 2; 1169 else 1170 new_pa = pa + 64; 1171 1172 if (!mc_valid_pa(mcp, new_pa)) { 1173 MC_LOG("Invalid PA\n"); 1174 pa = roundup(new_pa + 1, mc_isolation_bsize); 1175 } else { 1176 pp = page_numtopp_nolock(new_pa >> PAGESHIFT); 1177 if (pp != NULL) { 1178 uint64_t errors = 0; 1179 if (page_retire_check(new_pa, &errors) && 1180 (errors == 0)) { 1181 MC_LOG("Page has no error\n"); 1182 pa = new_pa; 1183 goto done; 1184 } 1185 /* 1186 * skip bad pages 1187 * and let the following loop to take care 1188 */ 1189 pa = roundup(new_pa + 1, PAGESIZE); 1190 MC_LOG("Skipping bad page to %lx\n", pa); 1191 } else { 1192 MC_LOG("Page has no page structure\n"); 1193 pa = new_pa; 1194 goto done; 1195 } 1196 } 1197 } 1198 1199 /* 1200 * if we wrap around twice, we just give up and let 1201 * mac patrol decide. 1202 */ 1203 MC_LOG("pa is now %lx\n", pa); 1204 while (loop_count <= 1) { 1205 if (!mc_valid_pa(mcp, pa)) { 1206 MC_LOG("pa is not valid. round up to 64 MB\n"); 1207 pa = roundup(pa + 1, 64 * 1024 * 1024); 1208 } else { 1209 pp = page_numtopp_nolock(pa >> PAGESHIFT); 1210 if (pp != NULL) { 1211 uint64_t errors = 0; 1212 if (page_retire_check(pa, &errors) && 1213 (errors == 0)) { 1214 MC_LOG("Page has no error\n"); 1215 break; 1216 } 1217 /* skip bad pages */ 1218 pa = roundup(pa + 1, PAGESIZE); 1219 MC_LOG("Skipping bad page to %lx\n", pa); 1220 } else { 1221 MC_LOG("Page has no page structure\n"); 1222 break; 1223 } 1224 } 1225 if (pa >= (mcp->mc_start_address + mcp->mc_size)) { 1226 MC_LOG("Wrap around\n"); 1227 pa = mcp->mc_start_address; 1228 loop_count++; 1229 } 1230 } 1231 1232 done: 1233 /* retstart MAC patrol: PA[37:6] */ 1234 MC_LOG("restart at pa = %lx\n", pa); 1235 ST_MAC_REG(MAC_RESTART_ADD(mcp, bank), MAC_RESTART_PA(pa)); 1236 MAC_PTRL_START_ADD(mcp, bank); 1237 1238 return (0); 1239 } 1240 1241 /* 1242 * Rewriting is used for two purposes. 1243 * - to correct the error in memory. 1244 * - to determine whether the error is permanent or intermittent. 1245 * It's done by writing the address in MAC_BANKm_REWRITE_ADD 1246 * and issuing REW_REQ command in MAC_BANKm_PTRL_CNRL. After that, 1247 * REW_END (and REW_CE/REW_UE if some error detected) is set when 1248 * rewrite operation is done. See 4.7.3 and 4.7.11 in Columbus2 PRM. 1249 * 1250 * Note that rewrite operation doesn't change RAW_UE to Marked UE. 1251 * Therefore, we use it only CE case. 1252 */ 1253 static uint32_t 1254 do_rewrite(mc_opl_t *mcp, int bank, uint32_t dimm_addr) 1255 { 1256 uint32_t cntl; 1257 int count = 0; 1258 1259 /* first wait to make sure PTRL_STATUS is 0 */ 1260 while (count++ < mc_max_rewrite_loop) { 1261 cntl = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank)); 1262 if (!(cntl & MAC_CNTL_PTRL_STATUS)) 1263 break; 1264 drv_usecwait(mc_rewrite_delay); 1265 } 1266 if (count >= mc_max_rewrite_loop) 1267 goto bad; 1268 1269 count = 0; 1270 1271 ST_MAC_REG(MAC_REWRITE_ADD(mcp, bank), dimm_addr); 1272 MAC_REW_REQ(mcp, bank); 1273 1274 do { 1275 cntl = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank)); 1276 if (count++ >= mc_max_rewrite_loop) { 1277 goto bad; 1278 } else { 1279 drv_usecwait(mc_rewrite_delay); 1280 } 1281 /* 1282 * If there are other MEMORY or PCI activities, this 1283 * will be BUSY, else it should be set immediately 1284 */ 1285 } while (!(cntl & MAC_CNTL_REW_END)); 1286 1287 MAC_CLEAR_ERRS(mcp, bank, MAC_CNTL_REW_ERRS); 1288 return (cntl); 1289 bad: 1290 /* This is bad. Just reset the circuit */ 1291 cmn_err(CE_WARN, "mc-opl rewrite timeout on /LSB%d/B%d\n", 1292 mcp->mc_board_num, bank); 1293 cntl = MAC_CNTL_REW_END; 1294 MAC_CMD(mcp, bank, MAC_CNTL_PTRL_RESET); 1295 MAC_CLEAR_ERRS(mcp, bank, MAC_CNTL_REW_ERRS); 1296 return (cntl); 1297 } 1298 void 1299 mc_process_scf_log(mc_opl_t *mcp) 1300 { 1301 int count; 1302 int n = 0; 1303 scf_log_t *p; 1304 int bank; 1305 1306 for (bank = 0; bank < BANKNUM_PER_SB; bank++) { 1307 while ((p = mcp->mc_scf_log[bank]) != NULL && 1308 (n < mc_max_errlog_processed)) { 1309 ASSERT(bank == p->sl_bank); 1310 count = 0; 1311 while ((LD_MAC_REG(MAC_STATIC_ERR_ADD(mcp, p->sl_bank)) 1312 & MAC_STATIC_ERR_VLD)) { 1313 if (count++ >= (mc_max_scf_loop)) { 1314 break; 1315 } 1316 drv_usecwait(mc_scf_delay); 1317 } 1318 1319 if (count < mc_max_scf_loop) { 1320 ST_MAC_REG(MAC_STATIC_ERR_LOG(mcp, p->sl_bank), 1321 p->sl_err_log); 1322 1323 ST_MAC_REG(MAC_STATIC_ERR_ADD(mcp, p->sl_bank), 1324 p->sl_err_add|MAC_STATIC_ERR_VLD); 1325 mcp->mc_scf_retry[bank] = 0; 1326 } else { 1327 /* if we try too many times, just drop the req */ 1328 if (mcp->mc_scf_retry[bank]++ <= mc_max_scf_retry) { 1329 return; 1330 } else { 1331 if ((++mc_pce_dropped & 0xff) == 0) { 1332 cmn_err(CE_WARN, 1333 "Cannot report Permanent CE to SCF\n"); 1334 } 1335 } 1336 } 1337 n++; 1338 mcp->mc_scf_log[bank] = p->sl_next; 1339 mcp->mc_scf_total[bank]--; 1340 ASSERT(mcp->mc_scf_total[bank] >= 0); 1341 kmem_free(p, sizeof (scf_log_t)); 1342 } 1343 } 1344 } 1345 void 1346 mc_queue_scf_log(mc_opl_t *mcp, mc_flt_stat_t *flt_stat, int bank) 1347 { 1348 scf_log_t *p; 1349 1350 if (mcp->mc_scf_total[bank] >= mc_max_scf_logs) { 1351 if ((++mc_pce_dropped & 0xff) == 0) { 1352 cmn_err(CE_WARN, "Too many Permanent CE requests.\n"); 1353 } 1354 return; 1355 } 1356 p = kmem_zalloc(sizeof (scf_log_t), KM_SLEEP); 1357 p->sl_next = 0; 1358 p->sl_err_add = flt_stat->mf_err_add; 1359 p->sl_err_log = flt_stat->mf_err_log; 1360 p->sl_bank = bank; 1361 1362 if (mcp->mc_scf_log[bank] == NULL) { 1363 /* 1364 * we rely on mc_scf_log to detect NULL queue. 1365 * mc_scf_log_tail is irrelevant is such case. 1366 */ 1367 mcp->mc_scf_log_tail[bank] = mcp->mc_scf_log[bank] = p; 1368 } else { 1369 mcp->mc_scf_log_tail[bank]->sl_next = p; 1370 mcp->mc_scf_log_tail[bank] = p; 1371 } 1372 mcp->mc_scf_total[bank]++; 1373 } 1374 /* 1375 * This routine determines what kind of CE happens, intermittent 1376 * or permanent as follows. (See 4.7.3 in Columbus2 PRM.) 1377 * - Do rewrite by issuing REW_REQ command to MAC_PTRL_CNTL register. 1378 * - If CE is still detected on the same address even after doing 1379 * rewrite operation twice, it is determined as permanent error. 1380 * - If error is not detected anymore, it is determined as intermittent 1381 * error. 1382 * - If UE is detected due to rewrite operation, it should be treated 1383 * as UE. 1384 */ 1385 1386 /* ARGSUSED */ 1387 static void 1388 mc_scrub_ce(mc_opl_t *mcp, int bank, mc_flt_stat_t *flt_stat, int ptrl_error) 1389 { 1390 uint32_t cntl; 1391 int i; 1392 1393 flt_stat->mf_type = FLT_TYPE_PERMANENT_CE; 1394 /* 1395 * rewrite request 1st time reads and correct error data 1396 * and write to DIMM. 2nd rewrite request must be issued 1397 * after REW_CE/UE/END is 0. When the 2nd request is completed, 1398 * if REW_CE = 1, then it is permanent CE. 1399 */ 1400 for (i = 0; i < 2; i++) { 1401 cntl = do_rewrite(mcp, bank, flt_stat->mf_err_add); 1402 /* 1403 * If the error becomes UE or CMPE 1404 * we return to the caller immediately. 1405 */ 1406 if (cntl & MAC_CNTL_REW_UE) { 1407 if (ptrl_error) 1408 flt_stat->mf_cntl |= MAC_CNTL_PTRL_UE; 1409 else 1410 flt_stat->mf_cntl |= MAC_CNTL_MI_UE; 1411 flt_stat->mf_type = FLT_TYPE_UE; 1412 return; 1413 } 1414 if (cntl & MAC_CNTL_REW_CMPE) { 1415 if (ptrl_error) 1416 flt_stat->mf_cntl |= MAC_CNTL_PTRL_CMPE; 1417 else 1418 flt_stat->mf_cntl |= MAC_CNTL_MI_CMPE; 1419 flt_stat->mf_type = FLT_TYPE_CMPE; 1420 return; 1421 } 1422 } 1423 if (!(cntl & MAC_CNTL_REW_CE)) { 1424 flt_stat->mf_type = FLT_TYPE_INTERMITTENT_CE; 1425 } 1426 1427 if (flt_stat->mf_type == FLT_TYPE_PERMANENT_CE) { 1428 /* report PERMANENT_CE to SP via SCF */ 1429 if (!(flt_stat->mf_err_log & MAC_ERR_LOG_INVALID)) { 1430 mc_queue_scf_log(mcp, flt_stat, bank); 1431 } 1432 } 1433 } 1434 1435 #define IS_CMPE(cntl, f) ((cntl) & ((f) ? MAC_CNTL_PTRL_CMPE :\ 1436 MAC_CNTL_MI_CMPE)) 1437 #define IS_UE(cntl, f) ((cntl) & ((f) ? MAC_CNTL_PTRL_UE : MAC_CNTL_MI_UE)) 1438 #define IS_CE(cntl, f) ((cntl) & ((f) ? MAC_CNTL_PTRL_CE : MAC_CNTL_MI_CE)) 1439 #define IS_OK(cntl, f) (!((cntl) & ((f) ? MAC_CNTL_PTRL_ERRS : \ 1440 MAC_CNTL_MI_ERRS))) 1441 1442 1443 static int 1444 IS_CE_ONLY(uint32_t cntl, int ptrl_error) 1445 { 1446 if (ptrl_error) { 1447 return ((cntl & MAC_CNTL_PTRL_ERRS) == MAC_CNTL_PTRL_CE); 1448 } else { 1449 return ((cntl & MAC_CNTL_MI_ERRS) == MAC_CNTL_MI_CE); 1450 } 1451 } 1452 1453 void 1454 mc_write_cntl(mc_opl_t *mcp, int bank, uint32_t value) 1455 { 1456 if (mcp->mc_speedup_period[bank] > 0) 1457 value |= mc_max_speed; 1458 else 1459 value |= mcp->mc_speed; 1460 ST_MAC_REG(MAC_PTRL_CNTL(mcp, bank), value); 1461 } 1462 1463 static void 1464 mc_read_ptrl_reg(mc_opl_t *mcp, int bank, mc_flt_stat_t *flt_stat) 1465 { 1466 flt_stat->mf_cntl = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank)) & 1467 MAC_CNTL_PTRL_ERRS; 1468 flt_stat->mf_err_add = LD_MAC_REG(MAC_PTRL_ERR_ADD(mcp, bank)); 1469 flt_stat->mf_err_log = LD_MAC_REG(MAC_PTRL_ERR_LOG(mcp, bank)); 1470 flt_stat->mf_flt_maddr.ma_bd = mcp->mc_board_num; 1471 flt_stat->mf_flt_maddr.ma_bank = bank; 1472 flt_stat->mf_flt_maddr.ma_dimm_addr = flt_stat->mf_err_add; 1473 } 1474 1475 static void 1476 mc_read_mi_reg(mc_opl_t *mcp, int bank, mc_flt_stat_t *flt_stat) 1477 { 1478 uint32_t status, old_status; 1479 1480 status = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank)) & 1481 MAC_CNTL_MI_ERRS; 1482 old_status = 0; 1483 1484 /* we keep reading until the status is stable */ 1485 while (old_status != status) { 1486 old_status = status; 1487 flt_stat->mf_err_add = 1488 LD_MAC_REG(MAC_MI_ERR_ADD(mcp, bank)); 1489 flt_stat->mf_err_log = 1490 LD_MAC_REG(MAC_MI_ERR_LOG(mcp, bank)); 1491 status = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank)) & 1492 MAC_CNTL_MI_ERRS; 1493 if (status == old_status) { 1494 break; 1495 } 1496 } 1497 1498 flt_stat->mf_cntl = status; 1499 flt_stat->mf_flt_maddr.ma_bd = mcp->mc_board_num; 1500 flt_stat->mf_flt_maddr.ma_bank = bank; 1501 flt_stat->mf_flt_maddr.ma_dimm_addr = flt_stat->mf_err_add; 1502 } 1503 1504 1505 /* 1506 * Error philosophy for mirror mode: 1507 * 1508 * PTRL (The error address for both banks are same, since ptrl stops if it 1509 * detects error.) 1510 * - Compaire error Report CMPE. 1511 * 1512 * - UE-UE Report MUE. No rewrite. 1513 * 1514 * - UE-* UE-(CE/OK). Rewrite to scrub UE. Report SUE. 1515 * 1516 * - CE-* CE-(CE/OK). Scrub to determine if CE is permanent. 1517 * If CE is permanent, inform SCF. Once for each 1518 * Dimm. If CE becomes UE or CMPE, go back to above. 1519 * 1520 * 1521 * MI (The error addresses for each bank are the same or different.) 1522 * - Compair error If addresses are the same. Just CMPE. 1523 * If addresses are different (this could happen 1524 * as a result of scrubbing. Report each seperately. 1525 * Only report error info on each side. 1526 * 1527 * - UE-UE Addresses are the same. Report MUE. 1528 * Addresses are different. Report SUE on each bank. 1529 * Rewrite to clear UE. 1530 * 1531 * - UE-* UE-(CE/OK) 1532 * Rewrite to clear UE. Report SUE for the bank. 1533 * 1534 * - CE-* CE-(CE/OK). Scrub to determine if CE is permanent. 1535 * If CE becomes UE or CMPE, go back to above. 1536 * 1537 */ 1538 1539 static int 1540 mc_process_error_mir(mc_opl_t *mcp, mc_aflt_t *mc_aflt, mc_flt_stat_t *flt_stat) 1541 { 1542 int ptrl_error = mc_aflt->mflt_is_ptrl; 1543 int i; 1544 int rv = 0; 1545 1546 MC_LOG("process mirror errors cntl[0] = %x, cntl[1] = %x\n", 1547 flt_stat[0].mf_cntl, flt_stat[1].mf_cntl); 1548 1549 if (ptrl_error) { 1550 if (((flt_stat[0].mf_cntl | flt_stat[1].mf_cntl) 1551 & MAC_CNTL_PTRL_ERRS) == 0) 1552 return (0); 1553 } else { 1554 if (((flt_stat[0].mf_cntl | flt_stat[1].mf_cntl) 1555 & MAC_CNTL_MI_ERRS) == 0) 1556 return (0); 1557 } 1558 1559 /* 1560 * First we take care of the case of CE 1561 * because they can become UE or CMPE 1562 */ 1563 for (i = 0; i < 2; i++) { 1564 if (IS_CE_ONLY(flt_stat[i].mf_cntl, ptrl_error)) { 1565 MC_LOG("CE detected on bank %d\n", 1566 flt_stat[i].mf_flt_maddr.ma_bank); 1567 mc_scrub_ce(mcp, flt_stat[i].mf_flt_maddr.ma_bank, 1568 &flt_stat[i], ptrl_error); 1569 rv = 1; 1570 } 1571 } 1572 1573 /* The above scrubbing can turn CE into UE or CMPE */ 1574 1575 /* 1576 * Now we distinguish two cases: same address or not 1577 * the same address. It might seem more intuitive to 1578 * distinguish PTRL v.s. MI error but it is more 1579 * complicated that way. 1580 */ 1581 1582 if (flt_stat[0].mf_err_add == flt_stat[1].mf_err_add) { 1583 1584 if (IS_CMPE(flt_stat[0].mf_cntl, ptrl_error) || 1585 IS_CMPE(flt_stat[1].mf_cntl, ptrl_error)) { 1586 flt_stat[0].mf_type = FLT_TYPE_CMPE; 1587 flt_stat[1].mf_type = FLT_TYPE_CMPE; 1588 mc_aflt->mflt_erpt_class = MC_OPL_CMPE; 1589 MC_LOG("cmpe error detected\n"); 1590 mc_aflt->mflt_nflts = 2; 1591 mc_aflt->mflt_stat[0] = &flt_stat[0]; 1592 mc_aflt->mflt_stat[1] = &flt_stat[1]; 1593 mc_aflt->mflt_pr = PR_UE; 1594 mc_err_drain(mc_aflt); 1595 return (1); 1596 } 1597 1598 if (IS_UE(flt_stat[0].mf_cntl, ptrl_error) && 1599 IS_UE(flt_stat[1].mf_cntl, ptrl_error)) { 1600 /* Both side are UE's */ 1601 1602 MAC_SET_ERRLOG_INFO(&flt_stat[0]); 1603 MAC_SET_ERRLOG_INFO(&flt_stat[1]); 1604 MC_LOG("MUE detected\n"); 1605 flt_stat[0].mf_type = FLT_TYPE_MUE; 1606 flt_stat[1].mf_type = FLT_TYPE_MUE; 1607 mc_aflt->mflt_erpt_class = MC_OPL_MUE; 1608 mc_aflt->mflt_nflts = 2; 1609 mc_aflt->mflt_stat[0] = &flt_stat[0]; 1610 mc_aflt->mflt_stat[1] = &flt_stat[1]; 1611 mc_aflt->mflt_pr = PR_UE; 1612 mc_err_drain(mc_aflt); 1613 return (1); 1614 } 1615 1616 /* Now the only case is UE/CE, UE/OK, or don't care */ 1617 for (i = 0; i < 2; i++) { 1618 if (IS_UE(flt_stat[i].mf_cntl, ptrl_error)) { 1619 1620 /* rewrite can clear the one side UE error */ 1621 1622 if (IS_OK(flt_stat[i^1].mf_cntl, ptrl_error)) { 1623 (void) do_rewrite(mcp, 1624 flt_stat[i].mf_flt_maddr.ma_bank, 1625 flt_stat[i].mf_flt_maddr.ma_dimm_addr); 1626 } 1627 flt_stat[i].mf_type = FLT_TYPE_UE; 1628 MAC_SET_ERRLOG_INFO(&flt_stat[i]); 1629 mc_aflt->mflt_erpt_class = MC_OPL_SUE; 1630 mc_aflt->mflt_stat[0] = &flt_stat[i]; 1631 mc_aflt->mflt_nflts = 1; 1632 mc_aflt->mflt_pr = PR_MCE; 1633 mc_err_drain(mc_aflt); 1634 /* Once we hit a UE/CE or UE/OK case, done */ 1635 return (1); 1636 } 1637 } 1638 1639 } else { 1640 /* 1641 * addresses are different. That means errors 1642 * on the 2 banks are not related at all. 1643 */ 1644 for (i = 0; i < 2; i++) { 1645 if (IS_CMPE(flt_stat[i].mf_cntl, ptrl_error)) { 1646 flt_stat[i].mf_type = FLT_TYPE_CMPE; 1647 mc_aflt->mflt_erpt_class = MC_OPL_CMPE; 1648 MC_LOG("cmpe error detected\n"); 1649 mc_aflt->mflt_nflts = 1; 1650 mc_aflt->mflt_stat[0] = &flt_stat[i]; 1651 mc_aflt->mflt_pr = PR_UE; 1652 mc_err_drain(mc_aflt); 1653 /* no more report on this bank */ 1654 flt_stat[i].mf_cntl = 0; 1655 rv = 1; 1656 } 1657 } 1658 1659 /* rewrite can clear the one side UE error */ 1660 1661 for (i = 0; i < 2; i++) { 1662 if (IS_UE(flt_stat[i].mf_cntl, ptrl_error)) { 1663 (void) do_rewrite(mcp, 1664 flt_stat[i].mf_flt_maddr.ma_bank, 1665 flt_stat[i].mf_flt_maddr.ma_dimm_addr); 1666 flt_stat[i].mf_type = FLT_TYPE_UE; 1667 MAC_SET_ERRLOG_INFO(&flt_stat[i]); 1668 mc_aflt->mflt_erpt_class = MC_OPL_SUE; 1669 mc_aflt->mflt_stat[0] = &flt_stat[i]; 1670 mc_aflt->mflt_nflts = 1; 1671 mc_aflt->mflt_pr = PR_MCE; 1672 mc_err_drain(mc_aflt); 1673 rv = 1; 1674 } 1675 } 1676 } 1677 return (rv); 1678 } 1679 static void 1680 mc_error_handler_mir(mc_opl_t *mcp, int bank, mc_addr_info_t *maddr) 1681 { 1682 mc_aflt_t mc_aflt; 1683 mc_flt_stat_t flt_stat[2], mi_flt_stat[2]; 1684 int i; 1685 int mi_valid; 1686 1687 bzero(&mc_aflt, sizeof (mc_aflt_t)); 1688 bzero(&flt_stat, 2 * sizeof (mc_flt_stat_t)); 1689 bzero(&mi_flt_stat, 2 * sizeof (mc_flt_stat_t)); 1690 1691 mc_aflt.mflt_mcp = mcp; 1692 mc_aflt.mflt_id = gethrtime(); 1693 1694 /* Now read all the registers into flt_stat */ 1695 1696 for (i = 0; i < 2; i++) { 1697 MC_LOG("Reading registers of bank %d\n", bank); 1698 /* patrol registers */ 1699 mc_read_ptrl_reg(mcp, bank, &flt_stat[i]); 1700 1701 ASSERT(maddr); 1702 maddr->mi_maddr = flt_stat[i].mf_flt_maddr; 1703 1704 MC_LOG("ptrl registers cntl %x add %x log %x\n", 1705 flt_stat[i].mf_cntl, 1706 flt_stat[i].mf_err_add, 1707 flt_stat[i].mf_err_log); 1708 1709 /* MI registers */ 1710 mc_read_mi_reg(mcp, bank, &mi_flt_stat[i]); 1711 1712 MC_LOG("MI registers cntl %x add %x log %x\n", 1713 mi_flt_stat[i].mf_cntl, 1714 mi_flt_stat[i].mf_err_add, 1715 mi_flt_stat[i].mf_err_log); 1716 1717 bank = bank^1; 1718 } 1719 1720 /* clear errors once we read all the registers */ 1721 MAC_CLEAR_ERRS(mcp, bank, 1722 (MAC_CNTL_PTRL_ERRS|MAC_CNTL_MI_ERRS)); 1723 1724 MAC_CLEAR_ERRS(mcp, bank ^ 1, (MAC_CNTL_PTRL_ERRS|MAC_CNTL_MI_ERRS)); 1725 1726 /* Process MI errors first */ 1727 1728 /* if not error mode, cntl1 is 0 */ 1729 if ((mi_flt_stat[0].mf_err_add & MAC_ERR_ADD_INVALID) || 1730 (mi_flt_stat[0].mf_err_log & MAC_ERR_LOG_INVALID)) 1731 mi_flt_stat[0].mf_cntl = 0; 1732 1733 if ((mi_flt_stat[1].mf_err_add & MAC_ERR_ADD_INVALID) || 1734 (mi_flt_stat[1].mf_err_log & MAC_ERR_LOG_INVALID)) 1735 mi_flt_stat[1].mf_cntl = 0; 1736 1737 mc_aflt.mflt_is_ptrl = 0; 1738 mi_valid = mc_process_error_mir(mcp, &mc_aflt, &mi_flt_stat[0]); 1739 1740 if ((((flt_stat[0].mf_cntl & MAC_CNTL_PTRL_ERRS) >> 1741 MAC_CNTL_PTRL_ERR_SHIFT) == 1742 ((mi_flt_stat[0].mf_cntl & MAC_CNTL_MI_ERRS) >> 1743 MAC_CNTL_MI_ERR_SHIFT)) && 1744 (flt_stat[0].mf_err_add == mi_flt_stat[0].mf_err_add) && 1745 (((flt_stat[1].mf_cntl & MAC_CNTL_PTRL_ERRS) >> 1746 MAC_CNTL_PTRL_ERR_SHIFT) == 1747 ((mi_flt_stat[1].mf_cntl & MAC_CNTL_MI_ERRS) >> 1748 MAC_CNTL_MI_ERR_SHIFT)) && 1749 (flt_stat[1].mf_err_add == mi_flt_stat[1].mf_err_add)) { 1750 #ifdef DEBUG 1751 MC_LOG("discarding PTRL error because " 1752 "it is the same as MI\n"); 1753 #endif 1754 maddr->mi_valid = mi_valid; 1755 return; 1756 } 1757 /* if not error mode, cntl1 is 0 */ 1758 if ((flt_stat[0].mf_err_add & MAC_ERR_ADD_INVALID) || 1759 (flt_stat[0].mf_err_log & MAC_ERR_LOG_INVALID)) 1760 flt_stat[0].mf_cntl = 0; 1761 1762 if ((flt_stat[1].mf_err_add & MAC_ERR_ADD_INVALID) || 1763 (flt_stat[1].mf_err_log & MAC_ERR_LOG_INVALID)) 1764 flt_stat[1].mf_cntl = 0; 1765 1766 mc_aflt.mflt_is_ptrl = 1; 1767 maddr->mi_valid = mc_process_error_mir(mcp, &mc_aflt, &flt_stat[0]); 1768 } 1769 static int 1770 mc_process_error(mc_opl_t *mcp, int bank, mc_aflt_t *mc_aflt, 1771 mc_flt_stat_t *flt_stat) 1772 { 1773 int ptrl_error = mc_aflt->mflt_is_ptrl; 1774 int rv = 0; 1775 1776 mc_aflt->mflt_erpt_class = NULL; 1777 if (IS_UE(flt_stat->mf_cntl, ptrl_error)) { 1778 MC_LOG("UE deteceted\n"); 1779 flt_stat->mf_type = FLT_TYPE_UE; 1780 mc_aflt->mflt_erpt_class = MC_OPL_UE; 1781 mc_aflt->mflt_pr = PR_UE; 1782 MAC_SET_ERRLOG_INFO(flt_stat); 1783 rv = 1; 1784 } else if (IS_CE(flt_stat->mf_cntl, ptrl_error)) { 1785 MC_LOG("CE deteceted\n"); 1786 MAC_SET_ERRLOG_INFO(flt_stat); 1787 1788 /* Error type can change after scrubing */ 1789 mc_scrub_ce(mcp, bank, flt_stat, ptrl_error); 1790 1791 if (flt_stat->mf_type == FLT_TYPE_PERMANENT_CE) { 1792 mc_aflt->mflt_erpt_class = MC_OPL_CE; 1793 mc_aflt->mflt_pr = PR_MCE; 1794 } else if (flt_stat->mf_type == FLT_TYPE_UE) { 1795 mc_aflt->mflt_erpt_class = MC_OPL_UE; 1796 mc_aflt->mflt_pr = PR_UE; 1797 } 1798 rv = 1; 1799 } 1800 MC_LOG("mc_process_error: fault type %x erpt %s\n", 1801 flt_stat->mf_type, 1802 mc_aflt->mflt_erpt_class); 1803 if (mc_aflt->mflt_erpt_class) { 1804 mc_aflt->mflt_stat[0] = flt_stat; 1805 mc_aflt->mflt_nflts = 1; 1806 mc_err_drain(mc_aflt); 1807 } 1808 return (rv); 1809 } 1810 1811 static void 1812 mc_error_handler(mc_opl_t *mcp, int bank, mc_addr_info_t *maddr) 1813 { 1814 mc_aflt_t mc_aflt; 1815 mc_flt_stat_t flt_stat, mi_flt_stat; 1816 int mi_valid; 1817 1818 bzero(&mc_aflt, sizeof (mc_aflt_t)); 1819 bzero(&flt_stat, sizeof (mc_flt_stat_t)); 1820 bzero(&mi_flt_stat, sizeof (mc_flt_stat_t)); 1821 1822 mc_aflt.mflt_mcp = mcp; 1823 mc_aflt.mflt_id = gethrtime(); 1824 1825 /* patrol registers */ 1826 mc_read_ptrl_reg(mcp, bank, &flt_stat); 1827 1828 ASSERT(maddr); 1829 maddr->mi_maddr = flt_stat.mf_flt_maddr; 1830 1831 MC_LOG("ptrl registers cntl %x add %x log %x\n", 1832 flt_stat.mf_cntl, 1833 flt_stat.mf_err_add, 1834 flt_stat.mf_err_log); 1835 1836 /* MI registers */ 1837 mc_read_mi_reg(mcp, bank, &mi_flt_stat); 1838 1839 1840 MC_LOG("MI registers cntl %x add %x log %x\n", 1841 mi_flt_stat.mf_cntl, 1842 mi_flt_stat.mf_err_add, 1843 mi_flt_stat.mf_err_log); 1844 1845 /* clear errors once we read all the registers */ 1846 MAC_CLEAR_ERRS(mcp, bank, (MAC_CNTL_PTRL_ERRS|MAC_CNTL_MI_ERRS)); 1847 1848 mc_aflt.mflt_is_ptrl = 0; 1849 if ((mi_flt_stat.mf_cntl & MAC_CNTL_MI_ERRS) && 1850 ((mi_flt_stat.mf_err_add & MAC_ERR_ADD_INVALID) == 0) && 1851 ((mi_flt_stat.mf_err_log & MAC_ERR_LOG_INVALID) == 0)) { 1852 mi_valid = mc_process_error(mcp, bank, &mc_aflt, &mi_flt_stat); 1853 } 1854 1855 if ((((flt_stat.mf_cntl & MAC_CNTL_PTRL_ERRS) >> 1856 MAC_CNTL_PTRL_ERR_SHIFT) == 1857 ((mi_flt_stat.mf_cntl & MAC_CNTL_MI_ERRS) >> 1858 MAC_CNTL_MI_ERR_SHIFT)) && 1859 (flt_stat.mf_err_add == mi_flt_stat.mf_err_add)) { 1860 #ifdef DEBUG 1861 MC_LOG("discarding PTRL error because " 1862 "it is the same as MI\n"); 1863 #endif 1864 maddr->mi_valid = mi_valid; 1865 return; 1866 } 1867 1868 mc_aflt.mflt_is_ptrl = 1; 1869 if ((flt_stat.mf_cntl & MAC_CNTL_PTRL_ERRS) && 1870 ((flt_stat.mf_err_add & MAC_ERR_ADD_INVALID) == 0) && 1871 ((flt_stat.mf_err_log & MAC_ERR_LOG_INVALID) == 0)) { 1872 maddr->mi_valid = mc_process_error(mcp, bank, 1873 &mc_aflt, &flt_stat); 1874 } 1875 } 1876 /* 1877 * memory patrol error handling algorithm: 1878 * timeout() is used to do periodic polling 1879 * This is the flow chart. 1880 * timeout -> 1881 * mc_check_errors() 1882 * if memory bank is installed, read the status register 1883 * if any error bit is set, 1884 * -> mc_error_handler() 1885 * -> read all error regsiters 1886 * -> mc_process_error() 1887 * determine error type 1888 * rewrite to clear error or scrub to determine CE type 1889 * inform SCF on permanent CE 1890 * -> mc_err_drain 1891 * page offline processing 1892 * -> mc_ereport_post() 1893 */ 1894 1895 static void 1896 mc_check_errors_func(mc_opl_t *mcp) 1897 { 1898 mc_addr_info_t maddr_info; 1899 int i, error_count = 0; 1900 uint32_t stat, cntl; 1901 int running; 1902 1903 /* 1904 * scan errors. 1905 */ 1906 if (mcp->mc_status & MC_MEMORYLESS) 1907 return; 1908 1909 for (i = 0; i < BANKNUM_PER_SB; i++) { 1910 if (mcp->mc_bank[i].mcb_status & BANK_INSTALLED) { 1911 stat = ldphysio(MAC_PTRL_STAT(mcp, i)); 1912 cntl = ldphysio(MAC_PTRL_CNTL(mcp, i)); 1913 running = cntl & MAC_CNTL_PTRL_START; 1914 1915 if (cntl & MAC_CNTL_PTRL_ADD_MAX) { 1916 mcp->mc_period[i]++; 1917 MC_LOG("mc period %ld on " 1918 "/LSB%d/B%d\n", mcp->mc_period[i], 1919 mcp->mc_board_num, i); 1920 MAC_CLEAR_MAX(mcp, i); 1921 if (mcp->mc_speedup_period[i] > 0) { 1922 /* If patrol is stoppped, we fall through */ 1923 if (--mcp->mc_speedup_period[i] == 0 && 1924 running) { 1925 MAC_CMD(mcp, i, 0); 1926 } 1927 } 1928 } 1929 if (mc_debug_show_all) { 1930 MC_LOG("/LSB%d/B%d stat %x cntl %x\n", 1931 mcp->mc_board_num, i, 1932 stat, cntl); 1933 } 1934 if (stat & (MAC_STAT_PTRL_ERRS|MAC_STAT_MI_ERRS)) { 1935 if (running) { 1936 MC_LOG("patrol running /LSB%d/B%d\n", 1937 mcp->mc_board_num, i); 1938 } 1939 if (running) { 1940 /* speed up the scanning */ 1941 mcp->mc_speedup_period[i] = 2; 1942 MAC_CMD(mcp, i, 0); 1943 } else { 1944 mcp->mc_speedup_period[i] = 0; 1945 maddr_info.mi_valid = 0; 1946 maddr_info.mi_advance = 1; 1947 if (IS_MIRROR(mcp, i)) 1948 mc_error_handler_mir(mcp, i, 1949 &maddr_info); 1950 else 1951 mc_error_handler(mcp, i, &maddr_info); 1952 1953 error_count++; 1954 restart_patrol(mcp, i, &maddr_info); 1955 } 1956 } else { 1957 restart_patrol(mcp, i, NULL); 1958 } 1959 } 1960 } 1961 if (error_count > 0) 1962 mcp->mc_last_error += error_count; 1963 else 1964 mcp->mc_last_error = 0; 1965 } 1966 1967 /* 1968 * mc_polling -- Check errors for only one instance, 1969 * but process errors for all instances to make sure we drain the errors 1970 * faster than they can be accumulated. 1971 * 1972 * Polling on each board should be done only once per each 1973 * mc_patrol_interval_sec. This is equivalent to setting mc_tick_left 1974 * to OPL_MAX_BOARDS and decrement by 1 on each timeout. 1975 * Once mc_tick_left becomes negative, the board becomes a candidate 1976 * for polling because it has waited for at least 1977 * mc_patrol_interval_sec's long. If mc_timeout_period is calculated 1978 * differently, this has to beupdated accordingly. 1979 */ 1980 1981 static void 1982 mc_polling(void) 1983 { 1984 int i, scan_error; 1985 mc_opl_t *mcp; 1986 1987 1988 scan_error = 1; 1989 for (i = 0; i < OPL_MAX_BOARDS; i++) { 1990 mutex_enter(&mcmutex); 1991 if ((mcp = mc_instances[i]) == NULL) { 1992 mutex_exit(&mcmutex); 1993 continue; 1994 } 1995 mutex_enter(&mcp->mc_lock); 1996 mutex_exit(&mcmutex); 1997 if (scan_error && mcp->mc_tick_left <= 0) { 1998 mc_check_errors_func((void *)mcp); 1999 mcp->mc_tick_left = OPL_MAX_BOARDS; 2000 scan_error = 0; 2001 } else { 2002 mcp->mc_tick_left--; 2003 } 2004 mc_process_scf_log(mcp); 2005 mutex_exit(&mcp->mc_lock); 2006 } 2007 } 2008 2009 static void 2010 get_ptrl_start_address(mc_opl_t *mcp, int bank, mc_addr_t *maddr) 2011 { 2012 maddr->ma_bd = mcp->mc_board_num; 2013 maddr->ma_bank = bank; 2014 maddr->ma_dimm_addr = 0; 2015 } 2016 2017 typedef struct mc_mem_range { 2018 uint64_t addr; 2019 uint64_t size; 2020 } mc_mem_range_t; 2021 2022 static int 2023 get_base_address(mc_opl_t *mcp) 2024 { 2025 mc_mem_range_t *mem_range; 2026 int len; 2027 2028 if (ddi_getlongprop(DDI_DEV_T_ANY, mcp->mc_dip, DDI_PROP_DONTPASS, 2029 "sb-mem-ranges", (caddr_t)&mem_range, &len) != DDI_SUCCESS) { 2030 return (DDI_FAILURE); 2031 } 2032 2033 mcp->mc_start_address = mem_range->addr; 2034 mcp->mc_size = mem_range->size; 2035 2036 kmem_free(mem_range, len); 2037 return (DDI_SUCCESS); 2038 } 2039 2040 struct mc_addr_spec { 2041 uint32_t bank; 2042 uint32_t phys_hi; 2043 uint32_t phys_lo; 2044 }; 2045 2046 #define REGS_PA(m, i) ((((uint64_t)m[i].phys_hi)<<32) | m[i].phys_lo) 2047 2048 static char *mc_tbl_name[] = { 2049 "cs0-mc-pa-trans-table", 2050 "cs1-mc-pa-trans-table" 2051 }; 2052 2053 static int 2054 mc_valid_pa(mc_opl_t *mcp, uint64_t pa) 2055 { 2056 struct memlist *ml; 2057 2058 if (mcp->mlist == NULL) 2059 mc_get_mlist(mcp); 2060 2061 for (ml = mcp->mlist; ml; ml = ml->next) { 2062 if (ml->address <= pa && pa < (ml->address + ml->size)) 2063 return (1); 2064 } 2065 return (0); 2066 } 2067 2068 static void 2069 mc_memlist_delete(struct memlist *mlist) 2070 { 2071 struct memlist *ml; 2072 2073 for (ml = mlist; ml; ml = mlist) { 2074 mlist = ml->next; 2075 kmem_free(ml, sizeof (struct memlist)); 2076 } 2077 } 2078 2079 static struct memlist * 2080 mc_memlist_dup(struct memlist *mlist) 2081 { 2082 struct memlist *hl = NULL, *tl, **mlp; 2083 2084 if (mlist == NULL) 2085 return (NULL); 2086 2087 mlp = &hl; 2088 tl = *mlp; 2089 for (; mlist; mlist = mlist->next) { 2090 *mlp = kmem_alloc(sizeof (struct memlist), KM_SLEEP); 2091 (*mlp)->address = mlist->address; 2092 (*mlp)->size = mlist->size; 2093 (*mlp)->prev = tl; 2094 tl = *mlp; 2095 mlp = &((*mlp)->next); 2096 } 2097 *mlp = NULL; 2098 2099 return (hl); 2100 } 2101 2102 2103 static struct memlist * 2104 mc_memlist_del_span(struct memlist *mlist, uint64_t base, uint64_t len) 2105 { 2106 uint64_t end; 2107 struct memlist *ml, *tl, *nlp; 2108 2109 if (mlist == NULL) 2110 return (NULL); 2111 2112 end = base + len; 2113 if ((end <= mlist->address) || (base == end)) 2114 return (mlist); 2115 2116 for (tl = ml = mlist; ml; tl = ml, ml = nlp) { 2117 uint64_t mend; 2118 2119 nlp = ml->next; 2120 2121 if (end <= ml->address) 2122 break; 2123 2124 mend = ml->address + ml->size; 2125 if (base < mend) { 2126 if (base <= ml->address) { 2127 ml->address = end; 2128 if (end >= mend) 2129 ml->size = 0ull; 2130 else 2131 ml->size = mend - ml->address; 2132 } else { 2133 ml->size = base - ml->address; 2134 if (end < mend) { 2135 struct memlist *nl; 2136 /* 2137 * splitting an memlist entry. 2138 */ 2139 nl = kmem_alloc(sizeof (struct memlist), 2140 KM_SLEEP); 2141 nl->address = end; 2142 nl->size = mend - nl->address; 2143 if ((nl->next = nlp) != NULL) 2144 nlp->prev = nl; 2145 nl->prev = ml; 2146 ml->next = nl; 2147 nlp = nl; 2148 } 2149 } 2150 if (ml->size == 0ull) { 2151 if (ml == mlist) { 2152 if ((mlist = nlp) != NULL) 2153 nlp->prev = NULL; 2154 kmem_free(ml, sizeof (struct memlist)); 2155 if (mlist == NULL) 2156 break; 2157 ml = nlp; 2158 } else { 2159 if ((tl->next = nlp) != NULL) 2160 nlp->prev = tl; 2161 kmem_free(ml, sizeof (struct memlist)); 2162 ml = tl; 2163 } 2164 } 2165 } 2166 } 2167 2168 return (mlist); 2169 } 2170 2171 static void 2172 mc_get_mlist(mc_opl_t *mcp) 2173 { 2174 struct memlist *mlist; 2175 2176 memlist_read_lock(); 2177 mlist = mc_memlist_dup(phys_install); 2178 memlist_read_unlock(); 2179 2180 if (mlist) { 2181 mlist = mc_memlist_del_span(mlist, 0ull, mcp->mc_start_address); 2182 } 2183 2184 if (mlist) { 2185 uint64_t startpa, endpa; 2186 2187 startpa = mcp->mc_start_address + mcp->mc_size; 2188 endpa = ptob(physmax + 1); 2189 if (endpa > startpa) { 2190 mlist = mc_memlist_del_span(mlist, 2191 startpa, endpa - startpa); 2192 } 2193 } 2194 2195 if (mlist) { 2196 mcp->mlist = mlist; 2197 } 2198 } 2199 2200 int 2201 mc_board_add(mc_opl_t *mcp) 2202 { 2203 struct mc_addr_spec *macaddr; 2204 cs_status_t *cs_status; 2205 int len, len1, i, bk, cc; 2206 mc_addr_info_t maddr; 2207 uint32_t mirr; 2208 int nbanks = 0; 2209 uint64_t nbytes = 0; 2210 2211 /* 2212 * Get configurations from "pseudo-mc" node which includes: 2213 * board# : LSB number 2214 * mac-addr : physical base address of MAC registers 2215 * csX-mac-pa-trans-table: translation table from DIMM address 2216 * to physical address or vice versa. 2217 */ 2218 mcp->mc_board_num = (int)ddi_getprop(DDI_DEV_T_ANY, mcp->mc_dip, 2219 DDI_PROP_DONTPASS, "board#", -1); 2220 2221 if (mcp->mc_board_num == -1) { 2222 return (DDI_FAILURE); 2223 } 2224 2225 /* 2226 * Get start address in this CAB. It can be gotten from 2227 * "sb-mem-ranges" property. 2228 */ 2229 2230 if (get_base_address(mcp) == DDI_FAILURE) { 2231 return (DDI_FAILURE); 2232 } 2233 /* get mac-pa trans tables */ 2234 for (i = 0; i < MC_TT_CS; i++) { 2235 len = MC_TT_ENTRIES; 2236 cc = ddi_getlongprop_buf(DDI_DEV_T_ANY, mcp->mc_dip, 2237 DDI_PROP_DONTPASS, mc_tbl_name[i], 2238 (caddr_t)mcp->mc_trans_table[i], &len); 2239 2240 if (cc != DDI_SUCCESS) { 2241 bzero(mcp->mc_trans_table[i], MC_TT_ENTRIES); 2242 } 2243 } 2244 mcp->mlist = NULL; 2245 2246 mc_get_mlist(mcp); 2247 2248 /* initialize bank informations */ 2249 cc = ddi_getlongprop(DDI_DEV_T_ANY, mcp->mc_dip, DDI_PROP_DONTPASS, 2250 "mc-addr", (caddr_t)&macaddr, &len); 2251 if (cc != DDI_SUCCESS) { 2252 cmn_err(CE_WARN, "Cannot get mc-addr. err=%d\n", cc); 2253 return (DDI_FAILURE); 2254 } 2255 2256 cc = ddi_getlongprop(DDI_DEV_T_ANY, mcp->mc_dip, DDI_PROP_DONTPASS, 2257 "cs-status", (caddr_t)&cs_status, &len1); 2258 2259 if (cc != DDI_SUCCESS) { 2260 if (len > 0) 2261 kmem_free(macaddr, len); 2262 cmn_err(CE_WARN, "Cannot get cs-status. err=%d\n", cc); 2263 return (DDI_FAILURE); 2264 } 2265 2266 mutex_init(&mcp->mc_lock, NULL, MUTEX_DRIVER, NULL); 2267 2268 for (i = 0; i < len1 / sizeof (cs_status_t); i++) { 2269 nbytes += ((uint64_t)cs_status[i].cs_avail_hi << 32) | 2270 ((uint64_t)cs_status[i].cs_avail_low); 2271 } 2272 if (len1 > 0) 2273 kmem_free(cs_status, len1); 2274 nbanks = len / sizeof (struct mc_addr_spec); 2275 2276 if (nbanks > 0) 2277 nbytes /= nbanks; 2278 else { 2279 /* No need to free macaddr because len must be 0 */ 2280 mcp->mc_status |= MC_MEMORYLESS; 2281 return (DDI_SUCCESS); 2282 } 2283 2284 for (i = 0; i < BANKNUM_PER_SB; i++) { 2285 mcp->mc_scf_retry[i] = 0; 2286 mcp->mc_period[i] = 0; 2287 mcp->mc_speedup_period[i] = 0; 2288 } 2289 2290 /* 2291 * Get the memory size here. Let it be B (bytes). 2292 * Let T be the time in u.s. to scan 64 bytes. 2293 * If we want to complete 1 round of scanning in P seconds. 2294 * 2295 * B * T * 10^(-6) = P 2296 * --------------- 2297 * 64 2298 * 2299 * T = P * 64 * 10^6 2300 * ------------- 2301 * B 2302 * 2303 * = P * 64 * 10^6 2304 * ------------- 2305 * B 2306 * 2307 * The timing bits are set in PTRL_CNTL[28:26] where 2308 * 2309 * 0 - 1 m.s 2310 * 1 - 512 u.s. 2311 * 10 - 256 u.s. 2312 * 11 - 128 u.s. 2313 * 100 - 64 u.s. 2314 * 101 - 32 u.s. 2315 * 110 - 0 u.s. 2316 * 111 - reserved. 2317 * 2318 * 2319 * a[0] = 110, a[1] = 101, ... a[6] = 0 2320 * 2321 * cs-status property is int x 7 2322 * 0 - cs# 2323 * 1 - cs-status 2324 * 2 - cs-avail.hi 2325 * 3 - cs-avail.lo 2326 * 4 - dimm-capa.hi 2327 * 5 - dimm-capa.lo 2328 * 6 - #of dimms 2329 */ 2330 2331 if (nbytes > 0) { 2332 int i; 2333 uint64_t ms; 2334 ms = ((uint64_t)mc_scan_period * 64 * 1000000)/nbytes; 2335 mcp->mc_speed = mc_scan_speeds[MC_MAX_SPEEDS - 1].mc_speeds; 2336 for (i = 0; i < MC_MAX_SPEEDS - 1; i++) { 2337 if (ms < mc_scan_speeds[i + 1].mc_period) { 2338 mcp->mc_speed = mc_scan_speeds[i].mc_speeds; 2339 break; 2340 } 2341 } 2342 } else 2343 mcp->mc_speed = 0; 2344 2345 2346 for (i = 0; i < len / sizeof (struct mc_addr_spec); i++) { 2347 struct mc_bank *bankp; 2348 uint32_t reg; 2349 2350 /* 2351 * setup bank 2352 */ 2353 bk = macaddr[i].bank; 2354 bankp = &(mcp->mc_bank[bk]); 2355 bankp->mcb_status = BANK_INSTALLED; 2356 bankp->mcb_reg_base = REGS_PA(macaddr, i); 2357 2358 reg = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bk)); 2359 bankp->mcb_ptrl_cntl = (reg & MAC_CNTL_PTRL_PRESERVE_BITS); 2360 2361 /* 2362 * check if mirror mode 2363 */ 2364 mirr = LD_MAC_REG(MAC_MIRR(mcp, bk)); 2365 2366 if (mirr & MAC_MIRR_MIRROR_MODE) { 2367 MC_LOG("Mirror -> /LSB%d/B%d\n", 2368 mcp->mc_board_num, bk); 2369 bankp->mcb_status |= BANK_MIRROR_MODE; 2370 /* 2371 * The following bit is only used for 2372 * error injection. We should clear it 2373 */ 2374 if (mirr & MAC_MIRR_BANK_EXCLUSIVE) 2375 ST_MAC_REG(MAC_MIRR(mcp, bk), 2376 0); 2377 } 2378 2379 /* 2380 * restart if not mirror mode or the other bank 2381 * of the mirror is not running 2382 */ 2383 if (!(mirr & MAC_MIRR_MIRROR_MODE) || 2384 !(mcp->mc_bank[bk^1].mcb_status & 2385 BANK_PTRL_RUNNING)) { 2386 MC_LOG("Starting up /LSB%d/B%d\n", 2387 mcp->mc_board_num, bk); 2388 get_ptrl_start_address(mcp, bk, &maddr.mi_maddr); 2389 maddr.mi_maddr.ma_bd = mcp->mc_board_num; 2390 maddr.mi_maddr.ma_bank = bk; 2391 maddr.mi_maddr.ma_dimm_addr = 0; 2392 maddr.mi_valid = 0; 2393 maddr.mi_advance = 0; 2394 restart_patrol(mcp, bk, &maddr); 2395 } else { 2396 MC_LOG("Not starting up /LSB%d/B%d\n", 2397 mcp->mc_board_num, bk); 2398 } 2399 bankp->mcb_status |= BANK_PTRL_RUNNING; 2400 } 2401 if (len > 0) 2402 kmem_free(macaddr, len); 2403 2404 mcp->mc_dimm_list = mc_get_dimm_list(mcp); 2405 2406 /* 2407 * set interval in HZ. 2408 */ 2409 mcp->mc_last_error = 0; 2410 2411 /* restart memory patrol checking */ 2412 mcp->mc_status |= MC_POLL_RUNNING; 2413 2414 return (DDI_SUCCESS); 2415 } 2416 2417 int 2418 mc_board_del(mc_opl_t *mcp) 2419 { 2420 int i; 2421 scf_log_t *p; 2422 2423 /* 2424 * cleanup mac state 2425 */ 2426 mutex_enter(&mcp->mc_lock); 2427 if (mcp->mc_status & MC_MEMORYLESS) { 2428 mutex_exit(&mcp->mc_lock); 2429 mutex_destroy(&mcp->mc_lock); 2430 return (DDI_SUCCESS); 2431 } 2432 for (i = 0; i < BANKNUM_PER_SB; i++) { 2433 if (mcp->mc_bank[i].mcb_status & BANK_INSTALLED) { 2434 mcp->mc_bank[i].mcb_status &= ~BANK_INSTALLED; 2435 } 2436 } 2437 2438 /* stop memory patrol checking */ 2439 if (mcp->mc_status & MC_POLL_RUNNING) { 2440 mcp->mc_status &= ~MC_POLL_RUNNING; 2441 } 2442 2443 /* just throw away all the scf logs */ 2444 for (i = 0; i < BANKNUM_PER_SB; i++) { 2445 while ((p = mcp->mc_scf_log[i]) != NULL) { 2446 mcp->mc_scf_log[i] = p->sl_next; 2447 mcp->mc_scf_total[i]--; 2448 kmem_free(p, sizeof (scf_log_t)); 2449 } 2450 } 2451 2452 if (mcp->mlist) 2453 mc_memlist_delete(mcp->mlist); 2454 2455 if (mcp->mc_dimm_list) 2456 mc_free_dimm_list(mcp->mc_dimm_list); 2457 2458 mutex_exit(&mcp->mc_lock); 2459 2460 mutex_destroy(&mcp->mc_lock); 2461 return (DDI_SUCCESS); 2462 } 2463 2464 int 2465 mc_suspend(mc_opl_t *mcp, uint32_t flag) 2466 { 2467 /* stop memory patrol checking */ 2468 mutex_enter(&mcp->mc_lock); 2469 if (mcp->mc_status & MC_MEMORYLESS) { 2470 mutex_exit(&mcp->mc_lock); 2471 return (DDI_SUCCESS); 2472 } 2473 2474 if (mcp->mc_status & MC_POLL_RUNNING) { 2475 mcp->mc_status &= ~MC_POLL_RUNNING; 2476 } 2477 mcp->mc_status |= flag; 2478 mutex_exit(&mcp->mc_lock); 2479 2480 return (DDI_SUCCESS); 2481 } 2482 2483 /* caller must clear the SUSPEND bits or this will do nothing */ 2484 2485 int 2486 mc_resume(mc_opl_t *mcp, uint32_t flag) 2487 { 2488 int i; 2489 uint64_t basepa; 2490 2491 mutex_enter(&mcp->mc_lock); 2492 if (mcp->mc_status & MC_MEMORYLESS) { 2493 mutex_exit(&mcp->mc_lock); 2494 return (DDI_SUCCESS); 2495 } 2496 basepa = mcp->mc_start_address; 2497 if (get_base_address(mcp) == DDI_FAILURE) { 2498 mutex_exit(&mcp->mc_lock); 2499 return (DDI_FAILURE); 2500 } 2501 2502 if (basepa != mcp->mc_start_address) { 2503 if (mcp->mlist) 2504 mc_memlist_delete(mcp->mlist); 2505 mcp->mlist = NULL; 2506 mc_get_mlist(mcp); 2507 } 2508 2509 mcp->mc_status &= ~flag; 2510 2511 if (mcp->mc_status & (MC_SOFT_SUSPENDED | MC_DRIVER_SUSPENDED)) { 2512 mutex_exit(&mcp->mc_lock); 2513 return (DDI_SUCCESS); 2514 } 2515 2516 if (!(mcp->mc_status & MC_POLL_RUNNING)) { 2517 /* restart memory patrol checking */ 2518 mcp->mc_status |= MC_POLL_RUNNING; 2519 for (i = 0; i < BANKNUM_PER_SB; i++) { 2520 if (mcp->mc_bank[i].mcb_status & BANK_INSTALLED) { 2521 restart_patrol(mcp, i, NULL); 2522 } 2523 } 2524 } 2525 mutex_exit(&mcp->mc_lock); 2526 2527 return (DDI_SUCCESS); 2528 } 2529 2530 static mc_opl_t * 2531 mc_pa_to_mcp(uint64_t pa) 2532 { 2533 mc_opl_t *mcp; 2534 int i; 2535 2536 ASSERT(MUTEX_HELD(&mcmutex)); 2537 for (i = 0; i < OPL_MAX_BOARDS; i++) { 2538 if ((mcp = mc_instances[i]) == NULL) 2539 continue; 2540 /* if mac patrol is suspended, we cannot rely on it */ 2541 if (!(mcp->mc_status & MC_POLL_RUNNING) || 2542 (mcp->mc_status & MC_SOFT_SUSPENDED)) 2543 continue; 2544 if ((mcp->mc_start_address <= pa) && 2545 (pa < (mcp->mc_start_address + mcp->mc_size))) { 2546 return (mcp); 2547 } 2548 } 2549 return (NULL); 2550 } 2551 2552 /* 2553 * Get Physical Board number from Logical one. 2554 */ 2555 static int 2556 mc_opl_get_physical_board(int sb) 2557 { 2558 if (&opl_get_physical_board) { 2559 return (opl_get_physical_board(sb)); 2560 } 2561 2562 cmn_err(CE_NOTE, "!opl_get_physical_board() not loaded\n"); 2563 return (-1); 2564 } 2565 2566 /* ARGSUSED */ 2567 int 2568 mc_get_mem_unum(int synd_code, uint64_t flt_addr, char *buf, int buflen, 2569 int *lenp) 2570 { 2571 int i; 2572 int sb; 2573 int bank; 2574 mc_opl_t *mcp; 2575 char memb_num; 2576 2577 mutex_enter(&mcmutex); 2578 2579 if (((mcp = mc_pa_to_mcp(flt_addr)) == NULL) || 2580 (!pa_is_valid(mcp, flt_addr))) { 2581 mutex_exit(&mcmutex); 2582 if (snprintf(buf, buflen, "UNKNOWN") >= buflen) { 2583 return (ENOSPC); 2584 } else { 2585 if (lenp) 2586 *lenp = strlen(buf); 2587 } 2588 return (0); 2589 } 2590 2591 bank = pa_to_bank(mcp, flt_addr - mcp->mc_start_address); 2592 sb = mc_opl_get_physical_board(mcp->mc_board_num); 2593 2594 if (sb == -1) { 2595 mutex_exit(&mcmutex); 2596 return (ENXIO); 2597 } 2598 2599 if (plat_model == MODEL_DC) { 2600 i = BD_BK_SLOT_TO_INDEX(0, bank, 0); 2601 snprintf(buf, buflen, "/%s%02d/MEM%s MEM%s MEM%s MEM%s", 2602 model_names[plat_model].unit_name, sb, 2603 mc_dc_dimm_unum_table[i], mc_dc_dimm_unum_table[i + 1], 2604 mc_dc_dimm_unum_table[i + 2], mc_dc_dimm_unum_table[i + 3]); 2605 } else { 2606 i = BD_BK_SLOT_TO_INDEX(sb, bank, 0); 2607 memb_num = mc_ff_dimm_unum_table[i][0]; 2608 snprintf(buf, buflen, "/%s/%s%c/MEM%s MEM%s MEM%s MEM%s", 2609 model_names[plat_model].unit_name, 2610 model_names[plat_model].mem_name, memb_num, 2611 &mc_ff_dimm_unum_table[i][1], 2612 2613 &mc_ff_dimm_unum_table[i + 1][1], 2614 &mc_ff_dimm_unum_table[i + 2][1], 2615 &mc_ff_dimm_unum_table[i + 3][1]); 2616 } 2617 if (lenp) { 2618 *lenp = strlen(buf); 2619 } 2620 mutex_exit(&mcmutex); 2621 return (0); 2622 } 2623 2624 int 2625 opl_mc_suspend(void) 2626 { 2627 mc_opl_t *mcp; 2628 int i; 2629 2630 mutex_enter(&mcmutex); 2631 for (i = 0; i < OPL_MAX_BOARDS; i++) { 2632 if ((mcp = mc_instances[i]) == NULL) 2633 continue; 2634 mc_suspend(mcp, MC_SOFT_SUSPENDED); 2635 } 2636 mutex_exit(&mcmutex); 2637 2638 return (0); 2639 } 2640 2641 int 2642 opl_mc_resume(void) 2643 { 2644 mc_opl_t *mcp; 2645 int i; 2646 2647 mutex_enter(&mcmutex); 2648 for (i = 0; i < OPL_MAX_BOARDS; i++) { 2649 if ((mcp = mc_instances[i]) == NULL) 2650 continue; 2651 mc_resume(mcp, MC_SOFT_SUSPENDED); 2652 } 2653 mutex_exit(&mcmutex); 2654 2655 return (0); 2656 } 2657 static void 2658 insert_mcp(mc_opl_t *mcp) 2659 { 2660 mutex_enter(&mcmutex); 2661 if (mc_instances[mcp->mc_board_num] != NULL) { 2662 MC_LOG("mc-opl instance for board# %d already exists\n", 2663 mcp->mc_board_num); 2664 } 2665 mc_instances[mcp->mc_board_num] = mcp; 2666 mutex_exit(&mcmutex); 2667 } 2668 2669 static void 2670 delete_mcp(mc_opl_t *mcp) 2671 { 2672 mutex_enter(&mcmutex); 2673 mc_instances[mcp->mc_board_num] = 0; 2674 mutex_exit(&mcmutex); 2675 } 2676 2677 /* Error injection interface */ 2678 2679 /* ARGSUSED */ 2680 int 2681 mc_inject_error(int error_type, uint64_t pa, uint32_t flags) 2682 { 2683 mc_opl_t *mcp; 2684 int bank; 2685 uint32_t dimm_addr; 2686 uint32_t cntl; 2687 mc_addr_info_t maddr; 2688 uint32_t data, stat; 2689 int both_sides = 0; 2690 uint64_t pa0; 2691 on_trap_data_t otd; 2692 extern void cpu_flush_ecache(void); 2693 2694 MC_LOG("HW mc_inject_error(%x, %lx, %x)\n", error_type, pa, flags); 2695 2696 mutex_enter(&mcmutex); 2697 if ((mcp = mc_pa_to_mcp(pa)) == NULL) { 2698 mutex_exit(&mcmutex); 2699 MC_LOG("mc_inject_error: invalid pa\n"); 2700 return (ENOTSUP); 2701 } 2702 2703 mutex_enter(&mcp->mc_lock); 2704 mutex_exit(&mcmutex); 2705 2706 if (mcp->mc_status & (MC_SOFT_SUSPENDED | MC_DRIVER_SUSPENDED)) { 2707 mutex_exit(&mcp->mc_lock); 2708 MC_LOG("mc-opl has been suspended. No error injection.\n"); 2709 return (EBUSY); 2710 } 2711 2712 /* convert pa to offset within the board */ 2713 MC_LOG("pa %lx, offset %lx\n", pa, pa - mcp->mc_start_address); 2714 2715 if (!pa_is_valid(mcp, pa)) { 2716 mutex_exit(&mcp->mc_lock); 2717 return (EINVAL); 2718 } 2719 2720 pa0 = pa - mcp->mc_start_address; 2721 2722 bank = pa_to_bank(mcp, pa0); 2723 2724 if (flags & MC_INJECT_FLAG_OTHER) 2725 bank = bank ^ 1; 2726 2727 if (MC_INJECT_MIRROR(error_type) && !IS_MIRROR(mcp, bank)) { 2728 mutex_exit(&mcp->mc_lock); 2729 MC_LOG("Not mirror mode\n"); 2730 return (EINVAL); 2731 } 2732 2733 dimm_addr = pa_to_dimm(mcp, pa0); 2734 2735 MC_LOG("injecting error to /LSB%d/B%d/D%x\n", 2736 mcp->mc_board_num, bank, dimm_addr); 2737 2738 2739 switch (error_type) { 2740 case MC_INJECT_INTERMITTENT_MCE: 2741 case MC_INJECT_PERMANENT_MCE: 2742 case MC_INJECT_MUE: 2743 both_sides = 1; 2744 } 2745 2746 if (flags & MC_INJECT_FLAG_RESET) 2747 ST_MAC_REG(MAC_EG_CNTL(mcp, bank), 0); 2748 2749 ST_MAC_REG(MAC_EG_ADD(mcp, bank), dimm_addr & MAC_EG_ADD_MASK); 2750 2751 if (both_sides) { 2752 ST_MAC_REG(MAC_EG_CNTL(mcp, bank^1), 0); 2753 ST_MAC_REG(MAC_EG_ADD(mcp, bank^1), 2754 dimm_addr & MAC_EG_ADD_MASK); 2755 } 2756 2757 switch (error_type) { 2758 case MC_INJECT_UE: 2759 case MC_INJECT_SUE: 2760 case MC_INJECT_MUE: 2761 if (flags & MC_INJECT_FLAG_PATH) { 2762 cntl = MAC_EG_ADD_FIX 2763 |MAC_EG_FORCE_READ00|MAC_EG_FORCE_READ16 2764 |MAC_EG_RDERR_ONCE; 2765 } else { 2766 cntl = MAC_EG_ADD_FIX|MAC_EG_FORCE_DERR00 2767 |MAC_EG_FORCE_DERR16|MAC_EG_DERR_ONCE; 2768 } 2769 flags |= MC_INJECT_FLAG_ST; 2770 break; 2771 case MC_INJECT_INTERMITTENT_CE: 2772 case MC_INJECT_INTERMITTENT_MCE: 2773 if (flags & MC_INJECT_FLAG_PATH) { 2774 cntl = MAC_EG_ADD_FIX 2775 |MAC_EG_FORCE_READ00 2776 |MAC_EG_RDERR_ONCE; 2777 } else { 2778 cntl = MAC_EG_ADD_FIX 2779 |MAC_EG_FORCE_DERR16 2780 |MAC_EG_DERR_ONCE; 2781 } 2782 flags |= MC_INJECT_FLAG_ST; 2783 break; 2784 case MC_INJECT_PERMANENT_CE: 2785 case MC_INJECT_PERMANENT_MCE: 2786 if (flags & MC_INJECT_FLAG_PATH) { 2787 cntl = MAC_EG_ADD_FIX 2788 |MAC_EG_FORCE_READ00 2789 |MAC_EG_RDERR_ALWAYS; 2790 } else { 2791 cntl = MAC_EG_ADD_FIX 2792 |MAC_EG_FORCE_DERR16 2793 |MAC_EG_DERR_ALWAYS; 2794 } 2795 flags |= MC_INJECT_FLAG_ST; 2796 break; 2797 case MC_INJECT_CMPE: 2798 data = 0xabcdefab; 2799 stphys(pa, data); 2800 cpu_flush_ecache(); 2801 MC_LOG("CMPE: writing data %x to %lx\n", data, pa); 2802 ST_MAC_REG(MAC_MIRR(mcp, bank), MAC_MIRR_BANK_EXCLUSIVE); 2803 stphys(pa, data ^ 0xffffffff); 2804 cpu_flush_ecache(); 2805 ST_MAC_REG(MAC_MIRR(mcp, bank), 0); 2806 MC_LOG("CMPE: write new data %xto %lx\n", data, pa); 2807 cntl = 0; 2808 break; 2809 case MC_INJECT_NOP: 2810 cntl = 0; 2811 break; 2812 default: 2813 MC_LOG("mc_inject_error: invalid option\n"); 2814 cntl = 0; 2815 } 2816 2817 if (cntl) { 2818 ST_MAC_REG(MAC_EG_CNTL(mcp, bank), cntl & MAC_EG_SETUP_MASK); 2819 ST_MAC_REG(MAC_EG_CNTL(mcp, bank), cntl); 2820 2821 if (both_sides) { 2822 ST_MAC_REG(MAC_EG_CNTL(mcp, bank^1), cntl & 2823 MAC_EG_SETUP_MASK); 2824 ST_MAC_REG(MAC_EG_CNTL(mcp, bank^1), cntl); 2825 } 2826 } 2827 2828 /* 2829 * For all injection cases except compare error, we 2830 * must write to the PA to trigger the error. 2831 */ 2832 2833 if (flags & MC_INJECT_FLAG_ST) { 2834 data = 0xf0e0d0c0; 2835 MC_LOG("Writing %x to %lx\n", data, pa); 2836 stphys(pa, data); 2837 cpu_flush_ecache(); 2838 } 2839 2840 2841 if (flags & MC_INJECT_FLAG_LD) { 2842 if (flags & MC_INJECT_FLAG_NO_TRAP) { 2843 if (on_trap(&otd, OT_DATA_EC)) { 2844 no_trap(); 2845 MC_LOG("Trap occurred\n"); 2846 } else { 2847 MC_LOG("On-trap Reading from %lx\n", pa); 2848 data = ldphys(pa); 2849 no_trap(); 2850 MC_LOG("data = %x\n", data); 2851 } 2852 } else { 2853 MC_LOG("Reading from %lx\n", pa); 2854 data = ldphys(pa); 2855 MC_LOG("data = %x\n", data); 2856 } 2857 } 2858 2859 if (flags & MC_INJECT_FLAG_RESTART) { 2860 MC_LOG("Restart patrol\n"); 2861 maddr.mi_maddr.ma_bd = mcp->mc_board_num; 2862 maddr.mi_maddr.ma_bank = bank; 2863 maddr.mi_maddr.ma_dimm_addr = dimm_addr; 2864 maddr.mi_valid = 1; 2865 maddr.mi_advance = 0; 2866 restart_patrol(mcp, bank, &maddr); 2867 } 2868 2869 if (flags & MC_INJECT_FLAG_POLL) { 2870 int running; 2871 2872 MC_LOG("Poll patrol error\n"); 2873 stat = LD_MAC_REG(MAC_PTRL_STAT(mcp, bank)); 2874 cntl = LD_MAC_REG(MAC_PTRL_CNTL(mcp, bank)); 2875 running = cntl & MAC_CNTL_PTRL_START; 2876 if (stat & (MAC_STAT_PTRL_ERRS|MAC_STAT_MI_ERRS)) { 2877 if (running) { 2878 /* speed up the scanning */ 2879 mcp->mc_speedup_period[bank] = 2; 2880 MAC_CMD(mcp, bank, 0); 2881 } else { 2882 mcp->mc_speedup_period[bank] = 0; 2883 maddr.mi_valid = 0; 2884 maddr.mi_advance = 1; 2885 if (IS_MIRROR(mcp, bank)) 2886 mc_error_handler_mir(mcp, bank, 2887 &maddr); 2888 else 2889 mc_error_handler(mcp, bank, &maddr); 2890 2891 restart_patrol(mcp, bank, &maddr); 2892 } 2893 } else 2894 restart_patrol(mcp, bank, NULL); 2895 } 2896 2897 mutex_exit(&mcp->mc_lock); 2898 return (0); 2899 } 2900 void 2901 mc_stphysio(uint64_t pa, uint32_t data) 2902 { 2903 #ifndef lint 2904 uint32_t dummy; 2905 #endif 2906 2907 MC_LOG("0x%x -> pa(%lx)\n", data, pa); 2908 stphysio(pa, data); 2909 2910 /* force the above write to be processed by mac patrol */ 2911 #ifndef lint 2912 dummy = ldphysio(pa); 2913 #endif 2914 } 2915 2916 uint32_t 2917 mc_ldphysio(uint64_t pa) 2918 { 2919 uint32_t rv; 2920 2921 rv = ldphysio(pa); 2922 MC_LOG("pa(%lx) = 0x%x\n", pa, rv); 2923 return (rv); 2924 } 2925 2926 #define isdigit(ch) ((ch) >= '0' && (ch) <= '9') 2927 2928 /* 2929 * parse_unum_memory -- extract the board number and the DIMM name from 2930 * the unum. 2931 * 2932 * Return 0 for success and non-zero for a failure. 2933 */ 2934 int 2935 parse_unum_memory(char *unum, int *board, char *dname) 2936 { 2937 char *c; 2938 char x, y, z; 2939 2940 if ((c = strstr(unum, "CMU")) != NULL) { 2941 /* DC Model */ 2942 c += 3; 2943 *board = (uint8_t)stoi(&c); 2944 if ((c = strstr(c, "MEM")) == NULL) { 2945 return (1); 2946 } 2947 c += 3; 2948 if (strlen(c) < 3) { 2949 return (2); 2950 } 2951 if ((!isdigit(c[0])) || (!(isdigit(c[1]))) || 2952 ((c[2] != 'A') && (c[2] != 'B'))) { 2953 return (3); 2954 } 2955 x = c[0]; 2956 y = c[1]; 2957 z = c[2]; 2958 } else if ((c = strstr(unum, "MBU_")) != NULL) { 2959 /* FF1/FF2 Model */ 2960 c += 4; 2961 if ((c[0] != 'A') && (c[0] != 'B')) { 2962 return (4); 2963 } 2964 if ((c = strstr(c, "MEMB")) == NULL) { 2965 return (5); 2966 } 2967 c += 4; 2968 2969 x = c[0]; 2970 *board = ((uint8_t)stoi(&c)) / 4; 2971 if ((c = strstr(c, "MEM")) == NULL) { 2972 return (6); 2973 } 2974 c += 3; 2975 if (strlen(c) < 2) { 2976 return (7); 2977 } 2978 if ((!isdigit(c[0])) || ((c[1] != 'A') && (c[1] != 'B'))) { 2979 return (8); 2980 } 2981 y = c[0]; 2982 z = c[1]; 2983 } else { 2984 return (9); 2985 } 2986 if (*board < 0) { 2987 return (10); 2988 } 2989 dname[0] = x; 2990 dname[1] = y; 2991 dname[2] = z; 2992 dname[3] = '\0'; 2993 return (0); 2994 } 2995 2996 /* 2997 * mc_get_mem_sid_dimm -- Get the serial-ID for a given board and 2998 * the DIMM name. 2999 */ 3000 int 3001 mc_get_mem_sid_dimm(mc_opl_t *mcp, char *dname, char *buf, 3002 int buflen, int *lenp) 3003 { 3004 int ret = ENODEV; 3005 mc_dimm_info_t *d = NULL; 3006 3007 if ((d = mcp->mc_dimm_list) == NULL) 3008 return (ENOTSUP); 3009 3010 for (; d != NULL; d = d->md_next) { 3011 if (strcmp(d->md_dimmname, dname) == 0) { 3012 break; 3013 } 3014 } 3015 if (d != NULL) { 3016 *lenp = strlen(d->md_serial) + strlen(d->md_partnum); 3017 if (buflen <= *lenp) { 3018 cmn_err(CE_WARN, "mc_get_mem_sid_dimm: " 3019 "buflen is smaller than %d\n", *lenp); 3020 ret = ENOSPC; 3021 } else { 3022 snprintf(buf, buflen, "%s:%s", 3023 d->md_serial, d->md_partnum); 3024 ret = 0; 3025 } 3026 } 3027 MC_LOG("mc_get_mem_sid_dimm: Ret=%d Name=%s Serial-ID=%s\n", 3028 ret, dname, (ret == 0) ? buf : ""); 3029 return (ret); 3030 } 3031 3032 int 3033 mc_set_mem_sid(mc_opl_t *mcp, char *buf, int buflen, int lsb, 3034 int bank, uint32_t mf_type, uint32_t d_slot) 3035 { 3036 int sb; 3037 int lenp = buflen; 3038 int id; 3039 int ret; 3040 char *dimmnm; 3041 3042 if ((sb = mc_opl_get_physical_board(lsb)) < 0) { 3043 return (ENODEV); 3044 } 3045 3046 if (mf_type == FLT_TYPE_PERMANENT_CE) { 3047 if (plat_model == MODEL_DC) { 3048 id = BD_BK_SLOT_TO_INDEX(0, bank, d_slot); 3049 } else { 3050 id = BD_BK_SLOT_TO_INDEX(sb, bank, d_slot); 3051 } 3052 dimmnm = mc_dc_dimm_unum_table[id]; 3053 if ((ret = mc_get_mem_sid_dimm(mcp, dimmnm, buf, buflen, 3054 &lenp)) != 0) { 3055 return (ret); 3056 } 3057 } else { 3058 return (1); 3059 } 3060 3061 return (0); 3062 } 3063 3064 /* 3065 * mc_get_mem_sid -- get the DIMM serial-ID corresponding to the unum. 3066 */ 3067 int 3068 mc_get_mem_sid(char *unum, char *buf, int buflen, int *lenp) 3069 { 3070 int i; 3071 int ret = ENODEV; 3072 int board; 3073 char dname[MCOPL_MAX_DIMMNAME + 1]; 3074 mc_opl_t *mcp; 3075 3076 MC_LOG("mc_get_mem_sid: unum=%s buflen=%d\n", unum, buflen); 3077 if ((ret = parse_unum_memory(unum, &board, dname)) != 0) { 3078 MC_LOG("mc_get_mem_sid: unum(%s) parsing failed ret=%d\n", 3079 unum, ret); 3080 return (EINVAL); 3081 } 3082 3083 if (board < 0) { 3084 MC_LOG("mc_get_mem_sid: Invalid board=%d dimm=%s\n", 3085 board, dname); 3086 return (EINVAL); 3087 } 3088 3089 mutex_enter(&mcmutex); 3090 for (i = 0; i < OPL_MAX_BOARDS; i++) { 3091 if ((mcp = mc_instances[i]) == NULL) 3092 continue; 3093 mutex_enter(&mcp->mc_lock); 3094 if (mcp->mc_board_num == board) { 3095 ret = mc_get_mem_sid_dimm(mcp, dname, buf, 3096 buflen, lenp); 3097 mutex_exit(&mcp->mc_lock); 3098 break; 3099 } 3100 mutex_exit(&mcp->mc_lock); 3101 } 3102 mutex_exit(&mcmutex); 3103 return (ret); 3104 } 3105 3106 /* 3107 * mc_get_mem_offset -- get the offset in a DIMM for a given physical address. 3108 */ 3109 int 3110 mc_get_mem_offset(uint64_t paddr, uint64_t *offp) 3111 { 3112 int i; 3113 int ret = ENODEV; 3114 mc_addr_t maddr; 3115 mc_opl_t *mcp; 3116 3117 mutex_enter(&mcmutex); 3118 for (i = 0; i < OPL_MAX_BOARDS; i++) { 3119 if ((mcp = mc_instances[i]) == NULL) 3120 continue; 3121 mutex_enter(&mcp->mc_lock); 3122 if (!pa_is_valid(mcp, paddr)) { 3123 mutex_exit(&mcp->mc_lock); 3124 continue; 3125 } 3126 if (pa_to_maddr(mcp, paddr, &maddr) == 0) { 3127 *offp = maddr.ma_dimm_addr; 3128 ret = 0; 3129 } 3130 mutex_exit(&mcp->mc_lock); 3131 } 3132 mutex_exit(&mcmutex); 3133 MC_LOG("mc_get_mem_offset: Ret=%d paddr=0x%lx offset=0x%lx\n", 3134 ret, paddr, *offp); 3135 return (ret); 3136 } 3137 3138 /* 3139 * dname_to_bankslot - Get the bank and slot number from the DIMM name. 3140 */ 3141 int 3142 dname_to_bankslot(char *dname, int *bank, int *slot) 3143 { 3144 int i; 3145 int tsz; 3146 char **tbl; 3147 3148 if (plat_model == MODEL_DC) { /* DC */ 3149 tbl = mc_dc_dimm_unum_table; 3150 tsz = OPL_MAX_DIMMS; 3151 } else { 3152 tbl = mc_ff_dimm_unum_table; 3153 tsz = 2 * OPL_MAX_DIMMS; 3154 } 3155 3156 for (i = 0; i < tsz; i++) { 3157 if (strcmp(dname, tbl[i]) == 0) { 3158 break; 3159 } 3160 } 3161 if (i == tsz) { 3162 return (1); 3163 } 3164 *bank = INDEX_TO_BANK(i); 3165 *slot = INDEX_TO_SLOT(i); 3166 return (0); 3167 } 3168 3169 /* 3170 * mc_get_mem_addr -- get the physical address of a DIMM corresponding 3171 * to the unum and sid. 3172 */ 3173 int 3174 mc_get_mem_addr(char *unum, char *sid, uint64_t offset, uint64_t *paddr) 3175 { 3176 int board; 3177 int bank; 3178 int slot; 3179 int i; 3180 int ret = ENODEV; 3181 char dname[MCOPL_MAX_DIMMNAME + 1]; 3182 mc_addr_t maddr; 3183 mc_opl_t *mcp; 3184 3185 MC_LOG("mc_get_mem_addr: unum=%s sid=%s offset=0x%lx\n", 3186 unum, sid, offset); 3187 if (parse_unum_memory(unum, &board, dname) != 0) { 3188 MC_LOG("mc_get_mem_sid: unum(%s) parsing failed ret=%d\n", 3189 unum, ret); 3190 return (EINVAL); 3191 } 3192 3193 if (board < 0) { 3194 MC_LOG("mc_get_mem_addr: Invalid board=%d dimm=%s\n", 3195 board, dname); 3196 return (EINVAL); 3197 } 3198 3199 mutex_enter(&mcmutex); 3200 for (i = 0; i < OPL_MAX_BOARDS; i++) { 3201 if ((mcp = mc_instances[i]) == NULL) 3202 continue; 3203 mutex_enter(&mcp->mc_lock); 3204 if (mcp->mc_board_num != board) { 3205 mutex_exit(&mcp->mc_lock); 3206 continue; 3207 } 3208 3209 ret = dname_to_bankslot(dname, &bank, &slot); 3210 MC_LOG("mc_get_mem_addr: bank=%d slot=%d\n", bank, slot); 3211 if (ret != 0) { 3212 MC_LOG("mc_get_mem_addr: dname_to_bankslot failed\n"); 3213 ret = ENODEV; 3214 } else { 3215 maddr.ma_bd = board; 3216 maddr.ma_bank = bank; 3217 maddr.ma_dimm_addr = offset; 3218 ret = mcaddr_to_pa(mcp, &maddr, paddr); 3219 if (ret != 0) { 3220 MC_LOG("mc_get_mem_addr: " 3221 "mcaddr_to_pa failed\n"); 3222 ret = ENODEV; 3223 } 3224 } 3225 mutex_exit(&mcp->mc_lock); 3226 } 3227 mutex_exit(&mcmutex); 3228 MC_LOG("mc_get_mem_addr: Ret=%d, Paddr=0x%lx\n", ret, *paddr); 3229 return (ret); 3230 } 3231 3232 static void 3233 mc_free_dimm_list(mc_dimm_info_t *d) 3234 { 3235 mc_dimm_info_t *next; 3236 3237 while (d != NULL) { 3238 next = d->md_next; 3239 kmem_free(d, sizeof (mc_dimm_info_t)); 3240 d = next; 3241 } 3242 } 3243 3244 /* 3245 * mc_get_dimm_list -- get the list of dimms with serial-id info 3246 * from the SP. 3247 */ 3248 mc_dimm_info_t * 3249 mc_get_dimm_list(mc_opl_t *mcp) 3250 { 3251 uint32_t bufsz; 3252 uint32_t maxbufsz; 3253 int ret; 3254 int sexp; 3255 board_dimm_info_t *bd_dimmp; 3256 mc_dimm_info_t *dimm_list = NULL; 3257 3258 maxbufsz = bufsz = sizeof (board_dimm_info_t) + 3259 ((MCOPL_MAX_DIMMNAME + MCOPL_MAX_SERIAL + 3260 MCOPL_MAX_PARTNUM) * OPL_MAX_DIMMS); 3261 3262 bd_dimmp = (board_dimm_info_t *)kmem_alloc(bufsz, KM_SLEEP); 3263 ret = scf_get_dimminfo(mcp->mc_board_num, (void *)bd_dimmp, &bufsz); 3264 3265 MC_LOG("mc_get_dimm_list: scf_service_getinfo returned=%d\n", ret); 3266 if (ret == 0) { 3267 sexp = sizeof (board_dimm_info_t) + 3268 ((bd_dimmp->bd_dnamesz + bd_dimmp->bd_serialsz + 3269 bd_dimmp->bd_partnumsz) * bd_dimmp->bd_numdimms); 3270 3271 if ((bd_dimmp->bd_version == OPL_DIMM_INFO_VERSION) && 3272 (bd_dimmp->bd_dnamesz <= MCOPL_MAX_DIMMNAME) && 3273 (bd_dimmp->bd_serialsz <= MCOPL_MAX_SERIAL) && 3274 (bd_dimmp->bd_partnumsz <= MCOPL_MAX_PARTNUM) && 3275 (sexp <= bufsz)) { 3276 3277 #ifdef DEBUG 3278 if (oplmc_debug) 3279 mc_dump_dimm_info(bd_dimmp); 3280 #endif 3281 dimm_list = mc_prepare_dimmlist(bd_dimmp); 3282 3283 } else { 3284 cmn_err(CE_WARN, "DIMM info version mismatch\n"); 3285 } 3286 } 3287 kmem_free(bd_dimmp, maxbufsz); 3288 MC_LOG("mc_get_dimm_list: dimmlist=0x%p\n", dimm_list); 3289 return (dimm_list); 3290 } 3291 3292 /* 3293 * mc_prepare_dimmlist - Prepare the dimm list from the infomation 3294 * recieved from the SP. 3295 */ 3296 mc_dimm_info_t * 3297 mc_prepare_dimmlist(board_dimm_info_t *bd_dimmp) 3298 { 3299 char *dimm_name; 3300 char *serial; 3301 char *part; 3302 int dimm; 3303 int dnamesz = bd_dimmp->bd_dnamesz; 3304 int sersz = bd_dimmp->bd_serialsz; 3305 int partsz = bd_dimmp->bd_partnumsz; 3306 mc_dimm_info_t *dimm_list = NULL; 3307 mc_dimm_info_t *d; 3308 3309 dimm_name = (char *)(bd_dimmp + 1); 3310 for (dimm = 0; dimm < bd_dimmp->bd_numdimms; dimm++) { 3311 3312 d = (mc_dimm_info_t *)kmem_alloc(sizeof (mc_dimm_info_t), 3313 KM_SLEEP); 3314 snprintf(d->md_dimmname, dnamesz + 1, "%s", dimm_name); 3315 serial = dimm_name + dnamesz; 3316 snprintf(d->md_serial, sersz + 1, "%s", serial); 3317 part = serial + sersz; 3318 snprintf(d->md_partnum, partsz + 1, "%s", part); 3319 3320 d->md_next = dimm_list; 3321 dimm_list = d; 3322 dimm_name = part + partsz; 3323 } 3324 return (dimm_list); 3325 } 3326 3327 #ifdef DEBUG 3328 void 3329 mc_dump_dimm(char *buf, int dnamesz, int serialsz, int partnumsz) 3330 { 3331 char dname[MCOPL_MAX_DIMMNAME + 1]; 3332 char serial[MCOPL_MAX_SERIAL + 1]; 3333 char part[ MCOPL_MAX_PARTNUM + 1]; 3334 char *b; 3335 3336 b = buf; 3337 snprintf(dname, dnamesz + 1, "%s", b); 3338 b += dnamesz; 3339 snprintf(serial, serialsz + 1, "%s", b); 3340 b += serialsz; 3341 snprintf(part, partnumsz + 1, "%s", b); 3342 printf("DIMM=%s Serial=%s PartNum=%s\n", dname, serial, part); 3343 } 3344 3345 void 3346 mc_dump_dimm_info(board_dimm_info_t *bd_dimmp) 3347 { 3348 int dimm; 3349 int dnamesz = bd_dimmp->bd_dnamesz; 3350 int sersz = bd_dimmp->bd_serialsz; 3351 int partsz = bd_dimmp->bd_partnumsz; 3352 char *buf; 3353 3354 printf("Version=%d Board=%02d DIMMs=%d NameSize=%d " 3355 "SerialSize=%d PartnumSize=%d\n", bd_dimmp->bd_version, 3356 bd_dimmp->bd_boardnum, bd_dimmp->bd_numdimms, bd_dimmp->bd_dnamesz, 3357 bd_dimmp->bd_serialsz, bd_dimmp->bd_partnumsz); 3358 printf("======================================================\n"); 3359 3360 buf = (char *)(bd_dimmp + 1); 3361 for (dimm = 0; dimm < bd_dimmp->bd_numdimms; dimm++) { 3362 mc_dump_dimm(buf, dnamesz, sersz, partsz); 3363 buf += dnamesz + sersz + partsz; 3364 } 3365 printf("======================================================\n"); 3366 } 3367 3368 3369 /* ARGSUSED */ 3370 static int 3371 mc_ioctl_debug(dev_t dev, int cmd, intptr_t arg, int mode, cred_t *credp, 3372 int *rvalp) 3373 { 3374 caddr_t buf; 3375 uint64_t pa; 3376 int rv = 0; 3377 int i; 3378 uint32_t flags; 3379 static uint32_t offset = 0; 3380 3381 3382 flags = (cmd >> 4) & 0xfffffff; 3383 3384 cmd &= 0xf; 3385 3386 MC_LOG("mc_ioctl(cmd = %x, flags = %x)\n", cmd, flags); 3387 3388 if (arg != NULL) { 3389 if (ddi_copyin((const void *)arg, (void *)&pa, 3390 sizeof (uint64_t), 0) < 0) { 3391 rv = EFAULT; 3392 return (rv); 3393 } 3394 buf = NULL; 3395 } else { 3396 buf = (caddr_t)kmem_alloc(PAGESIZE, KM_SLEEP); 3397 3398 pa = va_to_pa(buf); 3399 pa += offset; 3400 3401 offset += 64; 3402 if (offset >= PAGESIZE) 3403 offset = 0; 3404 } 3405 3406 switch (cmd) { 3407 case MCI_CE: 3408 mc_inject_error(MC_INJECT_INTERMITTENT_CE, pa, 3409 flags); 3410 break; 3411 case MCI_PERM_CE: 3412 mc_inject_error(MC_INJECT_PERMANENT_CE, pa, 3413 flags); 3414 break; 3415 case MCI_UE: 3416 mc_inject_error(MC_INJECT_UE, pa, 3417 flags); 3418 break; 3419 case MCI_M_CE: 3420 mc_inject_error(MC_INJECT_INTERMITTENT_MCE, pa, 3421 flags); 3422 break; 3423 case MCI_M_PCE: 3424 mc_inject_error(MC_INJECT_PERMANENT_MCE, pa, 3425 flags); 3426 break; 3427 case MCI_M_UE: 3428 mc_inject_error(MC_INJECT_MUE, pa, 3429 flags); 3430 break; 3431 case MCI_CMP: 3432 mc_inject_error(MC_INJECT_CMPE, pa, 3433 flags); 3434 break; 3435 case MCI_NOP: 3436 mc_inject_error(MC_INJECT_NOP, pa, flags); 3437 break; 3438 case MCI_SHOW_ALL: 3439 mc_debug_show_all = 1; 3440 break; 3441 case MCI_SHOW_NONE: 3442 mc_debug_show_all = 0; 3443 break; 3444 case MCI_ALLOC: 3445 /* 3446 * just allocate some kernel memory and never free it 3447 * 512 MB seems to be the maximum size supported. 3448 */ 3449 cmn_err(CE_NOTE, "Allocating kmem %d MB\n", flags * 512); 3450 for (i = 0; i < flags; i++) { 3451 buf = kmem_alloc(512 * 1024 * 1024, KM_SLEEP); 3452 cmn_err(CE_NOTE, "kmem buf %llx PA %llx\n", 3453 (u_longlong_t)buf, (u_longlong_t)va_to_pa(buf)); 3454 } 3455 break; 3456 case MCI_SUSPEND: 3457 (void) opl_mc_suspend(); 3458 break; 3459 case MCI_RESUME: 3460 (void) opl_mc_resume(); 3461 break; 3462 default: 3463 rv = ENXIO; 3464 } 3465 return (rv); 3466 } 3467 3468 #endif /* DEBUG */ 3469